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47dd7a54 GC |
1 | /******************************************************************************* |
2 | STMMAC Common Header File | |
3 | ||
4 | Copyright (C) 2007-2009 STMicroelectronics Ltd | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
23 | *******************************************************************************/ | |
24 | ||
bfab27a1 | 25 | #include <linux/etherdevice.h> |
5e33c791 | 26 | #include <linux/netdevice.h> |
bfab27a1 GC |
27 | #include <linux/phy.h> |
28 | #include <linux/module.h> | |
29 | #include <linux/init.h> | |
8f617541 GC |
30 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) |
31 | #define STMMAC_VLAN_TAG_USED | |
32 | #include <linux/if_vlan.h> | |
33 | #endif | |
34 | ||
56b106ae | 35 | #include "descs.h" |
1c901a46 | 36 | #include "mmc.h" |
56b106ae GC |
37 | |
38 | #undef CHIP_DEBUG_PRINT | |
39 | /* Turn-on extra printk debug for MAC core, dma and descriptors */ | |
40 | /* #define CHIP_DEBUG_PRINT */ | |
41 | ||
42 | #ifdef CHIP_DEBUG_PRINT | |
43 | #define CHIP_DBG(fmt, args...) printk(fmt, ## args) | |
44 | #else | |
45 | #define CHIP_DBG(fmt, args...) do { } while (0) | |
46 | #endif | |
47 | ||
48 | #undef FRAME_FILTER_DEBUG | |
49 | /* #define FRAME_FILTER_DEBUG */ | |
47dd7a54 | 50 | |
47dd7a54 GC |
51 | struct stmmac_extra_stats { |
52 | /* Transmit errors */ | |
53 | unsigned long tx_underflow ____cacheline_aligned; | |
54 | unsigned long tx_carrier; | |
55 | unsigned long tx_losscarrier; | |
3c20f72f | 56 | unsigned long vlan_tag; |
47dd7a54 GC |
57 | unsigned long tx_deferred; |
58 | unsigned long tx_vlan; | |
59 | unsigned long tx_jabber; | |
60 | unsigned long tx_frame_flushed; | |
61 | unsigned long tx_payload_error; | |
62 | unsigned long tx_ip_header_error; | |
63 | /* Receive errors */ | |
64 | unsigned long rx_desc; | |
3c20f72f GC |
65 | unsigned long sa_filter_fail; |
66 | unsigned long overflow_error; | |
67 | unsigned long ipc_csum_error; | |
47dd7a54 GC |
68 | unsigned long rx_collision; |
69 | unsigned long rx_crc; | |
1cc5a735 | 70 | unsigned long dribbling_bit; |
1b924032 | 71 | unsigned long rx_length; |
47dd7a54 GC |
72 | unsigned long rx_mii; |
73 | unsigned long rx_multicast; | |
74 | unsigned long rx_gmac_overflow; | |
75 | unsigned long rx_watchdog; | |
76 | unsigned long da_rx_filter_fail; | |
77 | unsigned long sa_rx_filter_fail; | |
78 | unsigned long rx_missed_cntr; | |
79 | unsigned long rx_overflow_cntr; | |
80 | unsigned long rx_vlan; | |
81 | /* Tx/Rx IRQ errors */ | |
82 | unsigned long tx_undeflow_irq; | |
83 | unsigned long tx_process_stopped_irq; | |
84 | unsigned long tx_jabber_irq; | |
85 | unsigned long rx_overflow_irq; | |
86 | unsigned long rx_buf_unav_irq; | |
87 | unsigned long rx_process_stopped_irq; | |
88 | unsigned long rx_watchdog_irq; | |
89 | unsigned long tx_early_irq; | |
90 | unsigned long fatal_bus_error_irq; | |
91 | /* Extra info */ | |
92 | unsigned long threshold; | |
93 | unsigned long tx_pkt_n; | |
94 | unsigned long rx_pkt_n; | |
95 | unsigned long poll_n; | |
96 | unsigned long sched_timer_n; | |
97 | unsigned long normal_irq_n; | |
98 | }; | |
99 | ||
cd7201f4 GC |
100 | /* CSR Frequency Access Defines*/ |
101 | #define CSR_F_35M 35000000 | |
102 | #define CSR_F_60M 60000000 | |
103 | #define CSR_F_100M 100000000 | |
104 | #define CSR_F_150M 150000000 | |
105 | #define CSR_F_250M 250000000 | |
106 | #define CSR_F_300M 300000000 | |
107 | ||
108 | #define MAC_CSR_H_FRQ_MASK 0x20 | |
109 | ||
aec7ff27 GC |
110 | #define HASH_TABLE_SIZE 64 |
111 | #define PAUSE_TIME 0x200 | |
112 | ||
113 | /* Flow Control defines */ | |
114 | #define FLOW_OFF 0 | |
115 | #define FLOW_RX 1 | |
116 | #define FLOW_TX 2 | |
117 | #define FLOW_AUTO (FLOW_TX | FLOW_RX) | |
118 | ||
119 | #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */ | |
120 | ||
1db123fb RK |
121 | /* DAM HW feature register fields */ |
122 | #define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */ | |
123 | #define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */ | |
124 | #define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */ | |
125 | #define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */ | |
126 | #define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */ | |
127 | #define DMA_HW_FEAT_ADDMACADRSEL 0x00000020 /* Multiple MAC Addr Reg */ | |
128 | #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */ | |
129 | #define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */ | |
130 | #define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */ | |
131 | #define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */ | |
132 | #define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */ | |
133 | #define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */ | |
134 | #define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 Timestamp */ | |
135 | #define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 Adv Timestamp */ | |
136 | #define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */ | |
137 | #define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */ | |
138 | #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */ | |
139 | #define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP csum Offload(Type 1) in Rx */ | |
140 | #define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP csum Offload(Type 2) in Rx */ | |
141 | #define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */ | |
142 | #define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. of additional Rx Channels */ | |
143 | #define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. of additional Tx Channels */ | |
144 | #define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate (Enhanced Descriptor) */ | |
145 | #define DMA_HW_FEAT_INTTSEN 0x02000000 /* Timestamping with Internal | |
146 | System Time */ | |
147 | #define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */ | |
148 | #define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN Insertion */ | |
149 | #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY interface */ | |
0f1f88a8 | 150 | #define DEFAULT_DMA_PBL 8 |
1db123fb | 151 | |
aec7ff27 | 152 | enum rx_frame_status { /* IPC status */ |
47dd7a54 GC |
153 | good_frame = 0, |
154 | discard_frame = 1, | |
155 | csum_none = 2, | |
3eeb2997 | 156 | llc_snap = 4, |
47dd7a54 GC |
157 | }; |
158 | ||
aec7ff27 GC |
159 | enum tx_dma_irq_status { |
160 | tx_hard_error = 1, | |
161 | tx_hard_error_bump_tc = 2, | |
162 | handle_tx_rx = 3, | |
163 | }; | |
47dd7a54 | 164 | |
e7434821 GC |
165 | /* DMA HW capabilities */ |
166 | struct dma_features { | |
167 | unsigned int mbps_10_100; | |
168 | unsigned int mbps_1000; | |
169 | unsigned int half_duplex; | |
170 | unsigned int hash_filter; | |
171 | unsigned int multi_addr; | |
172 | unsigned int pcs; | |
173 | unsigned int sma_mdio; | |
174 | unsigned int pmt_remote_wake_up; | |
175 | unsigned int pmt_magic_frame; | |
176 | unsigned int rmon; | |
177 | /* IEEE 1588-2002*/ | |
178 | unsigned int time_stamp; | |
179 | /* IEEE 1588-2008*/ | |
180 | unsigned int atime_stamp; | |
181 | /* 802.3az - Energy-Efficient Ethernet (EEE) */ | |
182 | unsigned int eee; | |
183 | unsigned int av; | |
184 | /* TX and RX csum */ | |
185 | unsigned int tx_coe; | |
186 | unsigned int rx_coe_type1; | |
187 | unsigned int rx_coe_type2; | |
188 | unsigned int rxfifo_over_2048; | |
189 | /* TX and RX number of channels */ | |
190 | unsigned int number_rx_channel; | |
191 | unsigned int number_tx_channel; | |
192 | /* Alternate (enhanced) DESC mode*/ | |
193 | unsigned int enh_desc; | |
194 | }; | |
195 | ||
aec7ff27 GC |
196 | /* GMAC TX FIFO is 8K, Rx FIFO is 16K */ |
197 | #define BUF_SIZE_16KiB 16384 | |
198 | #define BUF_SIZE_8KiB 8192 | |
199 | #define BUF_SIZE_4KiB 4096 | |
200 | #define BUF_SIZE_2KiB 2048 | |
47dd7a54 | 201 | |
aec7ff27 GC |
202 | /* Power Down and WOL */ |
203 | #define PMT_NOT_SUPPORTED 0 | |
204 | #define PMT_SUPPORTED 1 | |
47dd7a54 | 205 | |
aec7ff27 GC |
206 | /* Common MAC defines */ |
207 | #define MAC_CTRL_REG 0x00000000 /* MAC Control */ | |
208 | #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */ | |
209 | #define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */ | |
47dd7a54 | 210 | |
db98a0b0 GC |
211 | struct stmmac_desc_ops { |
212 | /* DMA RX descriptor ring initialization */ | |
47dd7a54 | 213 | void (*init_rx_desc) (struct dma_desc *p, unsigned int ring_size, |
db98a0b0 GC |
214 | int disable_rx_ic); |
215 | /* DMA TX descriptor ring initialization */ | |
47dd7a54 GC |
216 | void (*init_tx_desc) (struct dma_desc *p, unsigned int ring_size); |
217 | ||
218 | /* Invoked by the xmit function to prepare the tx descriptor */ | |
219 | void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len, | |
220 | int csum_flag); | |
221 | /* Set/get the owner of the descriptor */ | |
222 | void (*set_tx_owner) (struct dma_desc *p); | |
223 | int (*get_tx_owner) (struct dma_desc *p); | |
224 | /* Invoked by the xmit function to close the tx descriptor */ | |
225 | void (*close_tx_desc) (struct dma_desc *p); | |
226 | /* Clean the tx descriptor as soon as the tx irq is received */ | |
227 | void (*release_tx_desc) (struct dma_desc *p); | |
228 | /* Clear interrupt on tx frame completion. When this bit is | |
229 | * set an interrupt happens as soon as the frame is transmitted */ | |
230 | void (*clear_tx_ic) (struct dma_desc *p); | |
231 | /* Last tx segment reports the transmit status */ | |
232 | int (*get_tx_ls) (struct dma_desc *p); | |
233 | /* Return the transmit status looking at the TDES1 */ | |
234 | int (*tx_status) (void *data, struct stmmac_extra_stats *x, | |
ad01b7d4 | 235 | struct dma_desc *p, void __iomem *ioaddr); |
47dd7a54 GC |
236 | /* Get the buffer size from the descriptor */ |
237 | int (*get_tx_len) (struct dma_desc *p); | |
238 | /* Handle extra events on specific interrupts hw dependent */ | |
47dd7a54 GC |
239 | int (*get_rx_owner) (struct dma_desc *p); |
240 | void (*set_rx_owner) (struct dma_desc *p); | |
241 | /* Get the receive frame size */ | |
38912bdb | 242 | int (*get_rx_frame_len) (struct dma_desc *p, int rx_coe_type); |
47dd7a54 GC |
243 | /* Return the reception status looking at the RDES1 */ |
244 | int (*rx_status) (void *data, struct stmmac_extra_stats *x, | |
245 | struct dma_desc *p); | |
db98a0b0 GC |
246 | }; |
247 | ||
248 | struct stmmac_dma_ops { | |
249 | /* DMA core initialization */ | |
8327eb65 DS |
250 | int (*init) (void __iomem *ioaddr, int pbl, int fb, int burst_len, |
251 | u32 dma_tx, u32 dma_rx); | |
db98a0b0 | 252 | /* Dump DMA registers */ |
ad01b7d4 | 253 | void (*dump_regs) (void __iomem *ioaddr); |
db98a0b0 GC |
254 | /* Set tx/rx threshold in the csr6 register |
255 | * An invalid value enables the store-and-forward mode */ | |
ad01b7d4 | 256 | void (*dma_mode) (void __iomem *ioaddr, int txmode, int rxmode); |
db98a0b0 GC |
257 | /* To track extra statistic (if supported) */ |
258 | void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x, | |
ad01b7d4 GC |
259 | void __iomem *ioaddr); |
260 | void (*enable_dma_transmission) (void __iomem *ioaddr); | |
261 | void (*enable_dma_irq) (void __iomem *ioaddr); | |
262 | void (*disable_dma_irq) (void __iomem *ioaddr); | |
263 | void (*start_tx) (void __iomem *ioaddr); | |
264 | void (*stop_tx) (void __iomem *ioaddr); | |
265 | void (*start_rx) (void __iomem *ioaddr); | |
266 | void (*stop_rx) (void __iomem *ioaddr); | |
267 | int (*dma_interrupt) (void __iomem *ioaddr, | |
aec7ff27 | 268 | struct stmmac_extra_stats *x); |
e7434821 GC |
269 | /* If supported then get the optional core features */ |
270 | unsigned int (*get_hw_feature) (void __iomem *ioaddr); | |
db98a0b0 GC |
271 | }; |
272 | ||
273 | struct stmmac_ops { | |
274 | /* MAC core initialization */ | |
ad01b7d4 | 275 | void (*core_init) (void __iomem *ioaddr) ____cacheline_aligned; |
38912bdb DS |
276 | /* Enable and verify that the IPC module is supported */ |
277 | int (*rx_ipc) (void __iomem *ioaddr); | |
db98a0b0 | 278 | /* Dump MAC registers */ |
ad01b7d4 | 279 | void (*dump_regs) (void __iomem *ioaddr); |
db98a0b0 | 280 | /* Handle extra events on specific interrupts hw dependent */ |
ad01b7d4 | 281 | void (*host_irq_status) (void __iomem *ioaddr); |
47dd7a54 GC |
282 | /* Multicast filter setting */ |
283 | void (*set_filter) (struct net_device *dev); | |
284 | /* Flow control setting */ | |
ad01b7d4 | 285 | void (*flow_ctrl) (void __iomem *ioaddr, unsigned int duplex, |
47dd7a54 GC |
286 | unsigned int fc, unsigned int pause_time); |
287 | /* Set power management mode (e.g. magic frame) */ | |
ad01b7d4 | 288 | void (*pmt) (void __iomem *ioaddr, unsigned long mode); |
47dd7a54 | 289 | /* Set/Get Unicast MAC addresses */ |
ad01b7d4 | 290 | void (*set_umac_addr) (void __iomem *ioaddr, unsigned char *addr, |
db98a0b0 | 291 | unsigned int reg_n); |
ad01b7d4 | 292 | void (*get_umac_addr) (void __iomem *ioaddr, unsigned char *addr, |
db98a0b0 | 293 | unsigned int reg_n); |
47dd7a54 GC |
294 | }; |
295 | ||
296 | struct mac_link { | |
297 | int port; | |
298 | int duplex; | |
299 | int speed; | |
300 | }; | |
301 | ||
302 | struct mii_regs { | |
303 | unsigned int addr; /* MII Address */ | |
304 | unsigned int data; /* MII Data */ | |
305 | }; | |
306 | ||
286a8372 GC |
307 | struct stmmac_ring_mode_ops { |
308 | unsigned int (*is_jumbo_frm) (int len, int ehn_desc); | |
309 | unsigned int (*jumbo_frm) (void *priv, struct sk_buff *skb, int csum); | |
310 | void (*refill_desc3) (int bfsize, struct dma_desc *p); | |
311 | void (*init_desc3) (int des3_as_data_buf, struct dma_desc *p); | |
312 | void (*init_dma_chain) (struct dma_desc *des, dma_addr_t phy_addr, | |
313 | unsigned int size); | |
314 | void (*clean_desc3) (struct dma_desc *p); | |
315 | int (*set_16kib_bfsize) (int mtu); | |
316 | }; | |
317 | ||
47dd7a54 | 318 | struct mac_device_info { |
cadb7924 | 319 | const struct stmmac_ops *mac; |
320 | const struct stmmac_desc_ops *desc; | |
321 | const struct stmmac_dma_ops *dma; | |
286a8372 | 322 | const struct stmmac_ring_mode_ops *ring; |
db98a0b0 GC |
323 | struct mii_regs mii; /* MII register Addresses */ |
324 | struct mac_link link; | |
f0b9d786 | 325 | unsigned int synopsys_uid; |
47dd7a54 GC |
326 | }; |
327 | ||
ad01b7d4 GC |
328 | struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr); |
329 | struct mac_device_info *dwmac100_setup(void __iomem *ioaddr); | |
aec7ff27 | 330 | |
ad01b7d4 | 331 | extern void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6], |
aec7ff27 | 332 | unsigned int high, unsigned int low); |
ad01b7d4 | 333 | extern void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, |
aec7ff27 | 334 | unsigned int high, unsigned int low); |
bfab27a1 GC |
335 | |
336 | extern void stmmac_set_mac(void __iomem *ioaddr, bool enable); | |
337 | ||
ad01b7d4 | 338 | extern void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr); |
286a8372 | 339 | extern const struct stmmac_ring_mode_ops ring_mode_ops; |