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dev_ioctl: split out ndo_eth_ioctl
[linux-block.git] / drivers / net / ethernet / smsc / smsc9420.c
CommitLineData
1ccea77e 1// SPDX-License-Identifier: GPL-2.0-or-later
2cb37728
SG		 2 /***************************************************************************
3 *
4 * Copyright (C) 2007,2008 SMSC
5 *
2cb37728
SG		 6 ***************************************************************************
7 */
8
acec6d75
JP		 9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
a6b7a407 11#include <linux/interrupt.h>
2cb37728
SG		 12#include <linux/kernel.h>
13#include <linux/netdevice.h>
14#include <linux/phy.h>
15#include <linux/pci.h>
16#include <linux/if_vlan.h>
17#include <linux/dma-mapping.h>
18#include <linux/crc32.h>
5a0e3ad6 19#include <linux/slab.h>
9d9779e7 20#include <linux/module.h>
2cb37728
SG		 21#include <asm/unaligned.h>
22#include "smsc9420.h"
23
24#define DRV_NAME "smsc9420"
2cb37728
SG		 25#define DRV_MDIONAME "smsc9420-mdio"
26#define DRV_DESCRIPTION "SMSC LAN9420 driver"
27#define DRV_VERSION "1.01"
28
29MODULE_LICENSE("GPL");
30MODULE_VERSION(DRV_VERSION);
31
32struct smsc9420_dma_desc {
33 u32 status;
34 u32 length;
35 u32 buffer1;
36 u32 buffer2;
37};
38
39struct smsc9420_ring_info {
40 struct sk_buff *skb;
41 dma_addr_t mapping;
42};
43
44struct smsc9420_pdata {
b5a80837 45 void __iomem *ioaddr;
2cb37728
SG		 46 struct pci_dev *pdev;
47 struct net_device *dev;
48
49 struct smsc9420_dma_desc *rx_ring;
50 struct smsc9420_dma_desc *tx_ring;
51 struct smsc9420_ring_info *tx_buffers;
52 struct smsc9420_ring_info *rx_buffers;
53 dma_addr_t rx_dma_addr;
54 dma_addr_t tx_dma_addr;
55 int tx_ring_head, tx_ring_tail;
56 int rx_ring_head, rx_ring_tail;
57
58 spinlock_t int_lock;
59 spinlock_t phy_lock;
60
61 struct napi_struct napi;
62
63 bool software_irq_signal;
64 bool rx_csum;
65 u32 msg_enable;
66
2cb37728 67 struct mii_bus *mii_bus;
2cb37728
SG		 68 int last_duplex;
69 int last_carrier;
70};
71
9baa3c34 72static const struct pci_device_id smsc9420_id_table[] = {
2cb37728
SG		 73 { PCI_VENDOR_ID_9420, PCI_DEVICE_ID_9420, PCI_ANY_ID, PCI_ANY_ID, },
74 { 0, }
75};
76
77MODULE_DEVICE_TABLE(pci, smsc9420_id_table);
78
79#define SMSC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
80
81static uint smsc_debug;
82static uint debug = -1;
83module_param(debug, uint, 0);
84MODULE_PARM_DESC(debug, "debug level");
85
2cb37728
SG		 86static inline u32 smsc9420_reg_read(struct smsc9420_pdata *pd, u32 offset)
87{
b5a80837 88 return ioread32(pd->ioaddr + offset);
2cb37728
SG		 89}
90
91static inline void
92smsc9420_reg_write(struct smsc9420_pdata *pd, u32 offset, u32 value)
93{
b5a80837 94 iowrite32(value, pd->ioaddr + offset);
2cb37728
SG		 95}
96
97static inline void smsc9420_pci_flush_write(struct smsc9420_pdata *pd)
98{
99 /* to ensure PCI write completion, we must perform a PCI read */
100 smsc9420_reg_read(pd, ID_REV);
101}
102
103static int smsc9420_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
104{
105 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
106 unsigned long flags;
107 u32 addr;
108 int i, reg = -EIO;
109
110 spin_lock_irqsave(&pd->phy_lock, flags);
111
112 /* confirm MII not busy */
113 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
acec6d75 114 netif_warn(pd, drv, pd->dev, "MII is busy???\n");
2cb37728
SG		 115 goto out;
116 }
117
118 /* set the address, index & direction (read from PHY) */
119 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
120 MII_ACCESS_MII_READ_;
121 smsc9420_reg_write(pd, MII_ACCESS, addr);
122
123 /* wait for read to complete with 50us timeout */
124 for (i = 0; i < 5; i++) {
125 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
126 MII_ACCESS_MII_BUSY_)) {
127 reg = (u16)smsc9420_reg_read(pd, MII_DATA);
128 goto out;
129 }
130 udelay(10);
131 }
132
acec6d75 133 netif_warn(pd, drv, pd->dev, "MII busy timeout!\n");
2cb37728
SG		 134
135out:
136 spin_unlock_irqrestore(&pd->phy_lock, flags);
137 return reg;
138}
139
140static int smsc9420_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
141 u16 val)
142{
143 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
144 unsigned long flags;
145 u32 addr;
146 int i, reg = -EIO;
147
148 spin_lock_irqsave(&pd->phy_lock, flags);
149
150 /* confirm MII not busy */
151 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
acec6d75 152 netif_warn(pd, drv, pd->dev, "MII is busy???\n");
2cb37728
SG		 153 goto out;
154 }
155
156 /* put the data to write in the MAC */
157 smsc9420_reg_write(pd, MII_DATA, (u32)val);
158
159 /* set the address, index & direction (write to PHY) */
160 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
161 MII_ACCESS_MII_WRITE_;
162 smsc9420_reg_write(pd, MII_ACCESS, addr);
163
164 /* wait for write to complete with 50us timeout */
165 for (i = 0; i < 5; i++) {
166 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
167 MII_ACCESS_MII_BUSY_)) {
168 reg = 0;
169 goto out;
170 }
171 udelay(10);
172 }
173
acec6d75 174 netif_warn(pd, drv, pd->dev, "MII busy timeout!\n");
2cb37728
SG		 175
176out:
177 spin_unlock_irqrestore(&pd->phy_lock, flags);
178 return reg;
179}
180
181/* Returns hash bit number for given MAC address
182 * Example:
183 * 01 00 5E 00 00 01 -> returns bit number 31 */
184static u32 smsc9420_hash(u8 addr[ETH_ALEN])
185{
186 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
187}
188
189static int smsc9420_eeprom_reload(struct smsc9420_pdata *pd)
190{
191 int timeout = 100000;
192
193 BUG_ON(!pd);
194
195 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
acec6d75 196 netif_dbg(pd, drv, pd->dev, "%s: Eeprom busy\n", __func__);
2cb37728
SG		 197 return -EIO;
198 }
199
200 smsc9420_reg_write(pd, E2P_CMD,
201 (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_));
202
203 do {
204 udelay(10);
205 if (!(smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_))
206 return 0;
207 } while (timeout--);
208
acec6d75 209 netif_warn(pd, drv, pd->dev, "%s: Eeprom timed out\n", __func__);
2cb37728
SG		 210 return -EIO;
211}
212
2cb37728
SG		 213static void smsc9420_ethtool_get_drvinfo(struct net_device *netdev,
214 struct ethtool_drvinfo *drvinfo)
215{
216 struct smsc9420_pdata *pd = netdev_priv(netdev);
217
68aad78c
RJ		 218 strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
219 strlcpy(drvinfo->bus_info, pci_name(pd->pdev),
220 sizeof(drvinfo->bus_info));
221 strlcpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version));
2cb37728
SG		 222}
223
224static u32 smsc9420_ethtool_get_msglevel(struct net_device *netdev)
225{
226 struct smsc9420_pdata *pd = netdev_priv(netdev);
227 return pd->msg_enable;
228}
229
230static void smsc9420_ethtool_set_msglevel(struct net_device *netdev, u32 data)
231{
232 struct smsc9420_pdata *pd = netdev_priv(netdev);
233 pd->msg_enable = data;
234}
235
a7276db6
SG		 236static int smsc9420_ethtool_getregslen(struct net_device *dev)
237{
238 /* all smsc9420 registers plus all phy registers */
239 return 0x100 + (32 * sizeof(u32));
240}
241
242static void
243smsc9420_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
244 void *buf)
245{
246 struct smsc9420_pdata *pd = netdev_priv(dev);
5d872c50 247 struct phy_device *phy_dev = dev->phydev;
a7276db6
SG		 248 unsigned int i, j = 0;
249 u32 *data = buf;
250
251 regs->version = smsc9420_reg_read(pd, ID_REV);
252 for (i = 0; i < 0x100; i += (sizeof(u32)))
253 data[j++] = smsc9420_reg_read(pd, i);
254
6c53b1b1
SG		 255 // cannot read phy registers if the net device is down
256 if (!phy_dev)
257 return;
258
a7276db6 259 for (i = 0; i <= 31; i++)
e5a03bfd
AL		 260 data[j++] = smsc9420_mii_read(phy_dev->mdio.bus,
261 phy_dev->mdio.addr, i);
a7276db6
SG		 262}
263
012b215c
SG		 264static void smsc9420_eeprom_enable_access(struct smsc9420_pdata *pd)
265{
266 unsigned int temp = smsc9420_reg_read(pd, GPIO_CFG);
267 temp &= ~GPIO_CFG_EEPR_EN_;
268 smsc9420_reg_write(pd, GPIO_CFG, temp);
269 msleep(1);
270}
271
272static int smsc9420_eeprom_send_cmd(struct smsc9420_pdata *pd, u32 op)
273{
274 int timeout = 100;
275 u32 e2cmd;
276
acec6d75 277 netif_dbg(pd, hw, pd->dev, "op 0x%08x\n", op);
012b215c 278 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
acec6d75 279 netif_warn(pd, hw, pd->dev, "Busy at start\n");
012b215c
SG		 280 return -EBUSY;
281 }
282
283 e2cmd = op | E2P_CMD_EPC_BUSY_;
284 smsc9420_reg_write(pd, E2P_CMD, e2cmd);
285
286 do {
287 msleep(1);
288 e2cmd = smsc9420_reg_read(pd, E2P_CMD);
9df8f4e3 289 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
012b215c
SG		 290
291 if (!timeout) {
acec6d75 292 netif_info(pd, hw, pd->dev, "TIMED OUT\n");
012b215c
SG		 293 return -EAGAIN;
294 }
295
296 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
acec6d75
JP		 297 netif_info(pd, hw, pd->dev,
298 "Error occurred during eeprom operation\n");
012b215c
SG		 299 return -EINVAL;
300 }
301
302 return 0;
303}
304
305static int smsc9420_eeprom_read_location(struct smsc9420_pdata *pd,
306 u8 address, u8 *data)
307{
308 u32 op = E2P_CMD_EPC_CMD_READ_ | address;
309 int ret;
310
acec6d75 311 netif_dbg(pd, hw, pd->dev, "address 0x%x\n", address);
012b215c
SG		 312 ret = smsc9420_eeprom_send_cmd(pd, op);
313
314 if (!ret)
315 data[address] = smsc9420_reg_read(pd, E2P_DATA);
316
317 return ret;
318}
319
320static int smsc9420_eeprom_write_location(struct smsc9420_pdata *pd,
321 u8 address, u8 data)
322{
323 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
324 int ret;
325
acec6d75 326 netif_dbg(pd, hw, pd->dev, "address 0x%x, data 0x%x\n", address, data);
012b215c
SG		 327 ret = smsc9420_eeprom_send_cmd(pd, op);
328
329 if (!ret) {
330 op = E2P_CMD_EPC_CMD_WRITE_ | address;
331 smsc9420_reg_write(pd, E2P_DATA, (u32)data);
332 ret = smsc9420_eeprom_send_cmd(pd, op);
333 }
334
335 return ret;
336}
337
338static int smsc9420_ethtool_get_eeprom_len(struct net_device *dev)
339{
340 return SMSC9420_EEPROM_SIZE;
341}
342
343static int smsc9420_ethtool_get_eeprom(struct net_device *dev,
344 struct ethtool_eeprom *eeprom, u8 *data)
345{
346 struct smsc9420_pdata *pd = netdev_priv(dev);
347 u8 eeprom_data[SMSC9420_EEPROM_SIZE];
348 int len, i;
349
350 smsc9420_eeprom_enable_access(pd);
351
352 len = min(eeprom->len, SMSC9420_EEPROM_SIZE);
353 for (i = 0; i < len; i++) {
354 int ret = smsc9420_eeprom_read_location(pd, i, eeprom_data);
355 if (ret < 0) {
356 eeprom->len = 0;
357 return ret;
358 }
359 }
360
361 memcpy(data, &eeprom_data[eeprom->offset], len);
196b7e1b 362 eeprom->magic = SMSC9420_EEPROM_MAGIC;
012b215c
SG		 363 eeprom->len = len;
364 return 0;
365}
366
367static int smsc9420_ethtool_set_eeprom(struct net_device *dev,
368 struct ethtool_eeprom *eeprom, u8 *data)
369{
370 struct smsc9420_pdata *pd = netdev_priv(dev);
371 int ret;
372
196b7e1b
SG		 373 if (eeprom->magic != SMSC9420_EEPROM_MAGIC)
374 return -EINVAL;
375
012b215c
SG		 376 smsc9420_eeprom_enable_access(pd);
377 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWEN_);
378 ret = smsc9420_eeprom_write_location(pd, eeprom->offset, *data);
379 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWDS_);
380
381 /* Single byte write, according to man page */
382 eeprom->len = 1;
383
384 return ret;
385}
386
2cb37728 387static const struct ethtool_ops smsc9420_ethtool_ops = {
2cb37728
SG		 388 .get_drvinfo = smsc9420_ethtool_get_drvinfo,
389 .get_msglevel = smsc9420_ethtool_get_msglevel,
390 .set_msglevel = smsc9420_ethtool_set_msglevel,
8fd9ce0b 391 .nway_reset = phy_ethtool_nway_reset,
2cb37728 392 .get_link = ethtool_op_get_link,
012b215c
SG		 393 .get_eeprom_len = smsc9420_ethtool_get_eeprom_len,
394 .get_eeprom = smsc9420_ethtool_get_eeprom,
395 .set_eeprom = smsc9420_ethtool_set_eeprom,
a7276db6
SG		 396 .get_regs_len = smsc9420_ethtool_getregslen,
397 .get_regs = smsc9420_ethtool_getregs,
50c0c110 398 .get_ts_info = ethtool_op_get_ts_info,
a1b198b7
PR		 399 .get_link_ksettings = phy_ethtool_get_link_ksettings,
400 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2cb37728
SG		 401};
402
403/* Sets the device MAC address to dev_addr */
404static void smsc9420_set_mac_address(struct net_device *dev)
405{
406 struct smsc9420_pdata *pd = netdev_priv(dev);
407 u8 *dev_addr = dev->dev_addr;
408 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
409 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
410 (dev_addr[1] << 8) | dev_addr[0];
411
412 smsc9420_reg_write(pd, ADDRH, mac_high16);
413 smsc9420_reg_write(pd, ADDRL, mac_low32);
414}
415
416static void smsc9420_check_mac_address(struct net_device *dev)
417{
418 struct smsc9420_pdata *pd = netdev_priv(dev);
419
420 /* Check if mac address has been specified when bringing interface up */
421 if (is_valid_ether_addr(dev->dev_addr)) {
422 smsc9420_set_mac_address(dev);
acec6d75
JP		 423 netif_dbg(pd, probe, pd->dev,
424 "MAC Address is specified by configuration\n");
2cb37728
SG		 425 } else {
426 /* Try reading mac address from device. if EEPROM is present
427 * it will already have been set */
428 u32 mac_high16 = smsc9420_reg_read(pd, ADDRH);
429 u32 mac_low32 = smsc9420_reg_read(pd, ADDRL);
430 dev->dev_addr[0] = (u8)(mac_low32);
431 dev->dev_addr[1] = (u8)(mac_low32 >> 8);
432 dev->dev_addr[2] = (u8)(mac_low32 >> 16);
433 dev->dev_addr[3] = (u8)(mac_low32 >> 24);
434 dev->dev_addr[4] = (u8)(mac_high16);
435 dev->dev_addr[5] = (u8)(mac_high16 >> 8);
436
437 if (is_valid_ether_addr(dev->dev_addr)) {
438 /* eeprom values are valid so use them */
acec6d75
JP		 439 netif_dbg(pd, probe, pd->dev,
440 "Mac Address is read from EEPROM\n");
2cb37728
SG		 441 } else {
442 /* eeprom values are invalid, generate random MAC */
f2cedb63 443 eth_hw_addr_random(dev);
2cb37728 444 smsc9420_set_mac_address(dev);
acec6d75
JP		 445 netif_dbg(pd, probe, pd->dev,
446 "MAC Address is set to random\n");
2cb37728
SG		 447 }
448 }
449}
450
451static void smsc9420_stop_tx(struct smsc9420_pdata *pd)
452{
453 u32 dmac_control, mac_cr, dma_intr_ena;
46578a69 454 int timeout = 1000;
2cb37728
SG		 455
456 /* disable TX DMAC */
457 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
458 dmac_control &= (~DMAC_CONTROL_ST_);
459 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
460
461 /* Wait max 10ms for transmit process to stop */
46578a69 462 while (--timeout) {
2cb37728
SG		 463 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_TS_)
464 break;
465 udelay(10);
466 }
467
46578a69 468 if (!timeout)
acec6d75 469 netif_warn(pd, ifdown, pd->dev, "TX DMAC failed to stop\n");
2cb37728
SG		 470
471 /* ACK Tx DMAC stop bit */
472 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_TXPS_);
473
474 /* mask TX DMAC interrupts */
475 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
476 dma_intr_ena &= ~(DMAC_INTR_ENA_TX_);
477 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
478 smsc9420_pci_flush_write(pd);
479
480 /* stop MAC TX */
481 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_TXEN_);
482 smsc9420_reg_write(pd, MAC_CR, mac_cr);
483 smsc9420_pci_flush_write(pd);
484}
485
486static void smsc9420_free_tx_ring(struct smsc9420_pdata *pd)
487{
488 int i;
489
490 BUG_ON(!pd->tx_ring);
491
492 if (!pd->tx_buffers)
493 return;
494
495 for (i = 0; i < TX_RING_SIZE; i++) {
496 struct sk_buff *skb = pd->tx_buffers[i].skb;
497
498 if (skb) {
499 BUG_ON(!pd->tx_buffers[i].mapping);
3ab1270b
CJ		 500 dma_unmap_single(&pd->pdev->dev,
501 pd->tx_buffers[i].mapping, skb->len,
502 DMA_TO_DEVICE);
2cb37728
SG		 503 dev_kfree_skb_any(skb);
504 }
505
506 pd->tx_ring[i].status = 0;
507 pd->tx_ring[i].length = 0;
508 pd->tx_ring[i].buffer1 = 0;
509 pd->tx_ring[i].buffer2 = 0;
510 }
511 wmb();
512
513 kfree(pd->tx_buffers);
514 pd->tx_buffers = NULL;
515
516 pd->tx_ring_head = 0;
517 pd->tx_ring_tail = 0;
518}
519
520static void smsc9420_free_rx_ring(struct smsc9420_pdata *pd)
521{
522 int i;
523
524 BUG_ON(!pd->rx_ring);
525
526 if (!pd->rx_buffers)
527 return;
528
529 for (i = 0; i < RX_RING_SIZE; i++) {
530 if (pd->rx_buffers[i].skb)
531 dev_kfree_skb_any(pd->rx_buffers[i].skb);
532
533 if (pd->rx_buffers[i].mapping)
3ab1270b
CJ		 534 dma_unmap_single(&pd->pdev->dev,
535 pd->rx_buffers[i].mapping,
536 PKT_BUF_SZ, DMA_FROM_DEVICE);
2cb37728
SG		 537
538 pd->rx_ring[i].status = 0;
539 pd->rx_ring[i].length = 0;
540 pd->rx_ring[i].buffer1 = 0;
541 pd->rx_ring[i].buffer2 = 0;
542 }
543 wmb();
544
545 kfree(pd->rx_buffers);
546 pd->rx_buffers = NULL;
547
548 pd->rx_ring_head = 0;
549 pd->rx_ring_tail = 0;
550}
551
552static void smsc9420_stop_rx(struct smsc9420_pdata *pd)
553{
46578a69 554 int timeout = 1000;
2cb37728
SG		 555 u32 mac_cr, dmac_control, dma_intr_ena;
556
557 /* mask RX DMAC interrupts */
558 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
559 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
560 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
561 smsc9420_pci_flush_write(pd);
562
563 /* stop RX MAC prior to stoping DMA */
564 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_RXEN_);
565 smsc9420_reg_write(pd, MAC_CR, mac_cr);
566 smsc9420_pci_flush_write(pd);
567
568 /* stop RX DMAC */
569 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
570 dmac_control &= (~DMAC_CONTROL_SR_);
571 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
572 smsc9420_pci_flush_write(pd);
573
574 /* wait up to 10ms for receive to stop */
46578a69 575 while (--timeout) {
2cb37728
SG		 576 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_RS_)
577 break;
578 udelay(10);
579 }
580
46578a69 581 if (!timeout)
acec6d75
JP		 582 netif_warn(pd, ifdown, pd->dev,
583 "RX DMAC did not stop! timeout\n");
2cb37728
SG		 584
585 /* ACK the Rx DMAC stop bit */
586 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_RXPS_);
587}
588
589static irqreturn_t smsc9420_isr(int irq, void *dev_id)
590{
591 struct smsc9420_pdata *pd = dev_id;
592 u32 int_cfg, int_sts, int_ctl;
593 irqreturn_t ret = IRQ_NONE;
594 ulong flags;
595
596 BUG_ON(!pd);
b5a80837 597 BUG_ON(!pd->ioaddr);
2cb37728
SG		 598
599 int_cfg = smsc9420_reg_read(pd, INT_CFG);
600
601 /* check if it's our interrupt */
602 if ((int_cfg & (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) !=
603 (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_))
604 return IRQ_NONE;
605
606 int_sts = smsc9420_reg_read(pd, INT_STAT);
607
608 if (likely(INT_STAT_DMAC_INT_ & int_sts)) {
609 u32 status = smsc9420_reg_read(pd, DMAC_STATUS);
610 u32 ints_to_clear = 0;
611
612 if (status & DMAC_STS_TX_) {
613 ints_to_clear |= (DMAC_STS_TX_ | DMAC_STS_NIS_);
614 netif_wake_queue(pd->dev);
615 }
616
617 if (status & DMAC_STS_RX_) {
618 /* mask RX DMAC interrupts */
619 u32 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
620 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
621 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
622 smsc9420_pci_flush_write(pd);
623
624 ints_to_clear |= (DMAC_STS_RX_ | DMAC_STS_NIS_);
288379f0 625 napi_schedule(&pd->napi);
2cb37728
SG		 626 }
627
628 if (ints_to_clear)
629 smsc9420_reg_write(pd, DMAC_STATUS, ints_to_clear);
630
631 ret = IRQ_HANDLED;
632 }
633
634 if (unlikely(INT_STAT_SW_INT_ & int_sts)) {
635 /* mask software interrupt */
636 spin_lock_irqsave(&pd->int_lock, flags);
637 int_ctl = smsc9420_reg_read(pd, INT_CTL);
638 int_ctl &= (~INT_CTL_SW_INT_EN_);
639 smsc9420_reg_write(pd, INT_CTL, int_ctl);
640 spin_unlock_irqrestore(&pd->int_lock, flags);
641
642 smsc9420_reg_write(pd, INT_STAT, INT_STAT_SW_INT_);
643 pd->software_irq_signal = true;
644 smp_wmb();
645
646 ret = IRQ_HANDLED;
647 }
648
649 /* to ensure PCI write completion, we must perform a PCI read */
650 smsc9420_pci_flush_write(pd);
651
652 return ret;
653}
654
e312674f
SG		 655#ifdef CONFIG_NET_POLL_CONTROLLER
656static void smsc9420_poll_controller(struct net_device *dev)
657{
b5a80837
FR		 658 struct smsc9420_pdata *pd = netdev_priv(dev);
659 const int irq = pd->pdev->irq;
660
661 disable_irq(irq);
e312674f 662 smsc9420_isr(0, dev);
b5a80837 663 enable_irq(irq);
e312674f
SG		 664}
665#endif /* CONFIG_NET_POLL_CONTROLLER */
666
2cb37728
SG		 667static void smsc9420_dmac_soft_reset(struct smsc9420_pdata *pd)
668{
669 smsc9420_reg_write(pd, BUS_MODE, BUS_MODE_SWR_);
670 smsc9420_reg_read(pd, BUS_MODE);
671 udelay(2);
672 if (smsc9420_reg_read(pd, BUS_MODE) & BUS_MODE_SWR_)
acec6d75 673 netif_warn(pd, drv, pd->dev, "Software reset not cleared\n");
2cb37728
SG		 674}
675
676static int smsc9420_stop(struct net_device *dev)
677{
678 struct smsc9420_pdata *pd = netdev_priv(dev);
679 u32 int_cfg;
680 ulong flags;
681
682 BUG_ON(!pd);
5d872c50 683 BUG_ON(!dev->phydev);
2cb37728
SG		 684
685 /* disable master interrupt */
686 spin_lock_irqsave(&pd->int_lock, flags);
687 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
688 smsc9420_reg_write(pd, INT_CFG, int_cfg);
689 spin_unlock_irqrestore(&pd->int_lock, flags);
690
691 netif_tx_disable(dev);
692 napi_disable(&pd->napi);
693
694 smsc9420_stop_tx(pd);
695 smsc9420_free_tx_ring(pd);
696
697 smsc9420_stop_rx(pd);
698 smsc9420_free_rx_ring(pd);
699
b5a80837 700 free_irq(pd->pdev->irq, pd);
2cb37728
SG		 701
702 smsc9420_dmac_soft_reset(pd);
703
5d872c50 704 phy_stop(dev->phydev);
2cb37728 705
5d872c50 706 phy_disconnect(dev->phydev);
2cb37728
SG		 707 mdiobus_unregister(pd->mii_bus);
708 mdiobus_free(pd->mii_bus);
709
710 return 0;
711}
712
713static void smsc9420_rx_count_stats(struct net_device *dev, u32 desc_status)
714{
715 if (unlikely(desc_status & RDES0_ERROR_SUMMARY_)) {
716 dev->stats.rx_errors++;
717 if (desc_status & RDES0_DESCRIPTOR_ERROR_)
718 dev->stats.rx_over_errors++;
719 else if (desc_status & (RDES0_FRAME_TOO_LONG_ |
720 RDES0_RUNT_FRAME_ | RDES0_COLLISION_SEEN_))
721 dev->stats.rx_frame_errors++;
722 else if (desc_status & RDES0_CRC_ERROR_)
723 dev->stats.rx_crc_errors++;
724 }
725
726 if (unlikely(desc_status & RDES0_LENGTH_ERROR_))
727 dev->stats.rx_length_errors++;
728
729 if (unlikely(!((desc_status & RDES0_LAST_DESCRIPTOR_) &&
730 (desc_status & RDES0_FIRST_DESCRIPTOR_))))
731 dev->stats.rx_length_errors++;
732
733 if (desc_status & RDES0_MULTICAST_FRAME_)
734 dev->stats.multicast++;
735}
736
737static void smsc9420_rx_handoff(struct smsc9420_pdata *pd, const int index,
738 const u32 status)
739{
740 struct net_device *dev = pd->dev;
741 struct sk_buff *skb;
742 u16 packet_length = (status & RDES0_FRAME_LENGTH_MASK_)
743 >> RDES0_FRAME_LENGTH_SHFT_;
744
745 /* remove crc from packet lendth */
746 packet_length -= 4;
747
748 if (pd->rx_csum)
749 packet_length -= 2;
750
751 dev->stats.rx_packets++;
752 dev->stats.rx_bytes += packet_length;
753
3ab1270b
CJ		 754 dma_unmap_single(&pd->pdev->dev, pd->rx_buffers[index].mapping,
755 PKT_BUF_SZ, DMA_FROM_DEVICE);
2cb37728
SG		 756 pd->rx_buffers[index].mapping = 0;
757
758 skb = pd->rx_buffers[index].skb;
759 pd->rx_buffers[index].skb = NULL;
760
761 if (pd->rx_csum) {
762 u16 hw_csum = get_unaligned_le16(skb_tail_pointer(skb) +
763 NET_IP_ALIGN + packet_length + 4);
cd7a3b75 764 put_unaligned_le16(hw_csum, &skb->csum);
2cb37728
SG		 765 skb->ip_summed = CHECKSUM_COMPLETE;
766 }
767
768 skb_reserve(skb, NET_IP_ALIGN);
769 skb_put(skb, packet_length);
770
771 skb->protocol = eth_type_trans(skb, dev);
772
773 netif_receive_skb(skb);
2cb37728
SG		 774}
775
776static int smsc9420_alloc_rx_buffer(struct smsc9420_pdata *pd, int index)
777{
778 struct sk_buff *skb = netdev_alloc_skb(pd->dev, PKT_BUF_SZ);
779 dma_addr_t mapping;
780
781 BUG_ON(pd->rx_buffers[index].skb);
782 BUG_ON(pd->rx_buffers[index].mapping);
783
720a43ef 784 if (unlikely(!skb))
2cb37728 785 return -ENOMEM;
2cb37728 786
3ab1270b
CJ		 787 mapping = dma_map_single(&pd->pdev->dev, skb_tail_pointer(skb),
788 PKT_BUF_SZ, DMA_FROM_DEVICE);
789 if (dma_mapping_error(&pd->pdev->dev, mapping)) {
2cb37728 790 dev_kfree_skb_any(skb);
acec6d75 791 netif_warn(pd, rx_err, pd->dev, "pci_map_single failed!\n");
2cb37728
SG		 792 return -ENOMEM;
793 }
794
795 pd->rx_buffers[index].skb = skb;
796 pd->rx_buffers[index].mapping = mapping;
797 pd->rx_ring[index].buffer1 = mapping + NET_IP_ALIGN;
798 pd->rx_ring[index].status = RDES0_OWN_;
799 wmb();
800
801 return 0;
802}
803
804static void smsc9420_alloc_new_rx_buffers(struct smsc9420_pdata *pd)
805{
806 while (pd->rx_ring_tail != pd->rx_ring_head) {
807 if (smsc9420_alloc_rx_buffer(pd, pd->rx_ring_tail))
808 break;
809
810 pd->rx_ring_tail = (pd->rx_ring_tail + 1) % RX_RING_SIZE;
811 }
812}
813
814static int smsc9420_rx_poll(struct napi_struct *napi, int budget)
815{
816 struct smsc9420_pdata *pd =
817 container_of(napi, struct smsc9420_pdata, napi);
818 struct net_device *dev = pd->dev;
819 u32 drop_frame_cnt, dma_intr_ena, status;
820 int work_done;
821
822 for (work_done = 0; work_done < budget; work_done++) {
823 rmb();
824 status = pd->rx_ring[pd->rx_ring_head].status;
825
826 /* stop if DMAC owns this dma descriptor */
827 if (status & RDES0_OWN_)
828 break;
829
830 smsc9420_rx_count_stats(dev, status);
831 smsc9420_rx_handoff(pd, pd->rx_ring_head, status);
832 pd->rx_ring_head = (pd->rx_ring_head + 1) % RX_RING_SIZE;
833 smsc9420_alloc_new_rx_buffers(pd);
834 }
835
836 drop_frame_cnt = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
837 dev->stats.rx_dropped +=
838 (drop_frame_cnt & 0xFFFF) + ((drop_frame_cnt >> 17) & 0x3FF);
839
840 /* Kick RXDMA */
841 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
842 smsc9420_pci_flush_write(pd);
843
844 if (work_done < budget) {
6ad20165 845 napi_complete_done(&pd->napi, work_done);
2cb37728
SG		 846
847 /* re-enable RX DMA interrupts */
848 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
849 dma_intr_ena |= (DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
850 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
851 smsc9420_pci_flush_write(pd);
852 }
853 return work_done;
854}
855
856static void
857smsc9420_tx_update_stats(struct net_device *dev, u32 status, u32 length)
858{
859 if (unlikely(status & TDES0_ERROR_SUMMARY_)) {
860 dev->stats.tx_errors++;
861 if (status & (TDES0_EXCESSIVE_DEFERRAL_ |
862 TDES0_EXCESSIVE_COLLISIONS_))
863 dev->stats.tx_aborted_errors++;
864
865 if (status & (TDES0_LOSS_OF_CARRIER_ | TDES0_NO_CARRIER_))
866 dev->stats.tx_carrier_errors++;
867 } else {
868 dev->stats.tx_packets++;
869 dev->stats.tx_bytes += (length & 0x7FF);
870 }
871
872 if (unlikely(status & TDES0_EXCESSIVE_COLLISIONS_)) {
873 dev->stats.collisions += 16;
874 } else {
875 dev->stats.collisions +=
876 (status & TDES0_COLLISION_COUNT_MASK_) >>
877 TDES0_COLLISION_COUNT_SHFT_;
878 }
879
880 if (unlikely(status & TDES0_HEARTBEAT_FAIL_))
881 dev->stats.tx_heartbeat_errors++;
882}
883
884/* Check for completed dma transfers, update stats and free skbs */
885static void smsc9420_complete_tx(struct net_device *dev)
886{
887 struct smsc9420_pdata *pd = netdev_priv(dev);
888
889 while (pd->tx_ring_tail != pd->tx_ring_head) {
890 int index = pd->tx_ring_tail;
891 u32 status, length;
892
893 rmb();
894 status = pd->tx_ring[index].status;
895 length = pd->tx_ring[index].length;
896
897 /* Check if DMA still owns this descriptor */
898 if (unlikely(TDES0_OWN_ & status))
899 break;
900
901 smsc9420_tx_update_stats(dev, status, length);
902
903 BUG_ON(!pd->tx_buffers[index].skb);
904 BUG_ON(!pd->tx_buffers[index].mapping);
905
3ab1270b
CJ		 906 dma_unmap_single(&pd->pdev->dev,
907 pd->tx_buffers[index].mapping,
908 pd->tx_buffers[index].skb->len,
909 DMA_TO_DEVICE);
2cb37728
SG		 910 pd->tx_buffers[index].mapping = 0;
911
912 dev_kfree_skb_any(pd->tx_buffers[index].skb);
913 pd->tx_buffers[index].skb = NULL;
914
915 pd->tx_ring[index].buffer1 = 0;
916 wmb();
917
918 pd->tx_ring_tail = (pd->tx_ring_tail + 1) % TX_RING_SIZE;
919 }
920}
921
61357325
SH		 922static netdev_tx_t smsc9420_hard_start_xmit(struct sk_buff *skb,
923 struct net_device *dev)
2cb37728
SG		 924{
925 struct smsc9420_pdata *pd = netdev_priv(dev);
926 dma_addr_t mapping;
927 int index = pd->tx_ring_head;
928 u32 tmp_desc1;
929 bool about_to_take_last_desc =
930 (((pd->tx_ring_head + 2) % TX_RING_SIZE) == pd->tx_ring_tail);
931
932 smsc9420_complete_tx(dev);
933
934 rmb();
935 BUG_ON(pd->tx_ring[index].status & TDES0_OWN_);
936 BUG_ON(pd->tx_buffers[index].skb);
937 BUG_ON(pd->tx_buffers[index].mapping);
938
3ab1270b
CJ		 939 mapping = dma_map_single(&pd->pdev->dev, skb->data, skb->len,
940 DMA_TO_DEVICE);
941 if (dma_mapping_error(&pd->pdev->dev, mapping)) {
acec6d75
JP		 942 netif_warn(pd, tx_err, pd->dev,
943 "pci_map_single failed, dropping packet\n");
2cb37728
SG		 944 return NETDEV_TX_BUSY;
945 }
946
947 pd->tx_buffers[index].skb = skb;
948 pd->tx_buffers[index].mapping = mapping;
949
950 tmp_desc1 = (TDES1_LS_ | ((u32)skb->len & 0x7FF));
951 if (unlikely(about_to_take_last_desc)) {
952 tmp_desc1 |= TDES1_IC_;
953 netif_stop_queue(pd->dev);
954 }
955
956 /* check if we are at the last descriptor and need to set EOR */
957 if (unlikely(index == (TX_RING_SIZE - 1)))
958 tmp_desc1 |= TDES1_TER_;
959
960 pd->tx_ring[index].buffer1 = mapping;
961 pd->tx_ring[index].length = tmp_desc1;
962 wmb();
963
964 /* increment head */
965 pd->tx_ring_head = (pd->tx_ring_head + 1) % TX_RING_SIZE;
966
967 /* assign ownership to DMAC */
968 pd->tx_ring[index].status = TDES0_OWN_;
969 wmb();
970
62412072
RC		 971 skb_tx_timestamp(skb);
972
2cb37728
SG		 973 /* kick the DMA */
974 smsc9420_reg_write(pd, TX_POLL_DEMAND, 1);
975 smsc9420_pci_flush_write(pd);
976
2cb37728
SG		 977 return NETDEV_TX_OK;
978}
979
980static struct net_device_stats *smsc9420_get_stats(struct net_device *dev)
981{
982 struct smsc9420_pdata *pd = netdev_priv(dev);
983 u32 counter = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
984 dev->stats.rx_dropped +=
985 (counter & 0x0000FFFF) + ((counter >> 17) & 0x000003FF);
986 return &dev->stats;
987}
988
989static void smsc9420_set_multicast_list(struct net_device *dev)
990{
991 struct smsc9420_pdata *pd = netdev_priv(dev);
992 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
993
994 if (dev->flags & IFF_PROMISC) {
acec6d75 995 netif_dbg(pd, hw, pd->dev, "Promiscuous Mode Enabled\n");
2cb37728
SG		 996 mac_cr |= MAC_CR_PRMS_;
997 mac_cr &= (~MAC_CR_MCPAS_);
998 mac_cr &= (~MAC_CR_HPFILT_);
999 } else if (dev->flags & IFF_ALLMULTI) {
acec6d75 1000 netif_dbg(pd, hw, pd->dev, "Receive all Multicast Enabled\n");
2cb37728
SG		 1001 mac_cr &= (~MAC_CR_PRMS_);
1002 mac_cr |= MAC_CR_MCPAS_;
1003 mac_cr &= (~MAC_CR_HPFILT_);
4cd24eaf 1004 } else if (!netdev_mc_empty(dev)) {
22bedad3 1005 struct netdev_hw_addr *ha;
2cb37728
SG		 1006 u32 hash_lo = 0, hash_hi = 0;
1007
acec6d75 1008 netif_dbg(pd, hw, pd->dev, "Multicast filter enabled\n");
22bedad3
JP		 1009 netdev_for_each_mc_addr(ha, dev) {
1010 u32 bit_num = smsc9420_hash(ha->addr);
2cb37728
SG		 1011 u32 mask = 1 << (bit_num & 0x1F);
1012
1013 if (bit_num & 0x20)
1014 hash_hi |= mask;
1015 else
1016 hash_lo |= mask;
1017
2cb37728
SG		 1018 }
1019 smsc9420_reg_write(pd, HASHH, hash_hi);
1020 smsc9420_reg_write(pd, HASHL, hash_lo);
1021
1022 mac_cr &= (~MAC_CR_PRMS_);
1023 mac_cr &= (~MAC_CR_MCPAS_);
1024 mac_cr |= MAC_CR_HPFILT_;
1025 } else {
acec6d75 1026 netif_dbg(pd, hw, pd->dev, "Receive own packets only\n");
2cb37728
SG		 1027 smsc9420_reg_write(pd, HASHH, 0);
1028 smsc9420_reg_write(pd, HASHL, 0);
1029
1030 mac_cr &= (~MAC_CR_PRMS_);
1031 mac_cr &= (~MAC_CR_MCPAS_);
1032 mac_cr &= (~MAC_CR_HPFILT_);
1033 }
1034
1035 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1036 smsc9420_pci_flush_write(pd);
1037}
1038
2cb37728
SG		 1039static void smsc9420_phy_update_flowcontrol(struct smsc9420_pdata *pd)
1040{
5d872c50
PR		 1041 struct net_device *dev = pd->dev;
1042 struct phy_device *phy_dev = dev->phydev;
2cb37728
SG		 1043 u32 flow;
1044
1045 if (phy_dev->duplex == DUPLEX_FULL) {
1046 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
1047 u16 rmtadv = phy_read(phy_dev, MII_LPA);
bc02ff95 1048 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
2cb37728
SG		 1049
1050 if (cap & FLOW_CTRL_RX)
1051 flow = 0xFFFF0002;
1052 else
1053 flow = 0;
1054
acec6d75
JP		 1055 netif_info(pd, link, pd->dev, "rx pause %s, tx pause %s\n",
1056 cap & FLOW_CTRL_RX ? "enabled" : "disabled",
1057 cap & FLOW_CTRL_TX ? "enabled" : "disabled");
2cb37728 1058 } else {
acec6d75 1059 netif_info(pd, link, pd->dev, "half duplex\n");
2cb37728
SG		 1060 flow = 0;
1061 }
1062
1063 smsc9420_reg_write(pd, FLOW, flow);
1064}
1065
1066/* Update link mode if anything has changed. Called periodically when the
1067 * PHY is in polling mode, even if nothing has changed. */
1068static void smsc9420_phy_adjust_link(struct net_device *dev)
1069{
1070 struct smsc9420_pdata *pd = netdev_priv(dev);
5d872c50 1071 struct phy_device *phy_dev = dev->phydev;
2cb37728
SG		 1072 int carrier;
1073
1074 if (phy_dev->duplex != pd->last_duplex) {
1075 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1076 if (phy_dev->duplex) {
acec6d75 1077 netif_dbg(pd, link, pd->dev, "full duplex mode\n");
2cb37728
SG		 1078 mac_cr |= MAC_CR_FDPX_;
1079 } else {
acec6d75 1080 netif_dbg(pd, link, pd->dev, "half duplex mode\n");
2cb37728
SG		 1081 mac_cr &= ~MAC_CR_FDPX_;
1082 }
1083 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1084
1085 smsc9420_phy_update_flowcontrol(pd);
1086 pd->last_duplex = phy_dev->duplex;
1087 }
1088
1089 carrier = netif_carrier_ok(dev);
1090 if (carrier != pd->last_carrier) {
1091 if (carrier)
acec6d75 1092 netif_dbg(pd, link, pd->dev, "carrier OK\n");
2cb37728 1093 else
acec6d75 1094 netif_dbg(pd, link, pd->dev, "no carrier\n");
2cb37728
SG		 1095 pd->last_carrier = carrier;
1096 }
1097}
1098
1099static int smsc9420_mii_probe(struct net_device *dev)
1100{
1101 struct smsc9420_pdata *pd = netdev_priv(dev);
1102 struct phy_device *phydev = NULL;
1103
5d872c50 1104 BUG_ON(dev->phydev);
2cb37728
SG		 1105
1106 /* Device only supports internal PHY at address 1 */
7f854420
AL		 1107 phydev = mdiobus_get_phy(pd->mii_bus, 1);
1108 if (!phydev) {
48005993 1109 netdev_err(dev, "no PHY found at address 1\n");
2cb37728
SG		 1110 return -ENODEV;
1111 }
1112
84eff6d1 1113 phydev = phy_connect(dev, phydev_name(phydev),
f9a8f83b 1114 smsc9420_phy_adjust_link, PHY_INTERFACE_MODE_MII);
2cb37728
SG		 1115
1116 if (IS_ERR(phydev)) {
48005993 1117 netdev_err(dev, "Could not attach to PHY\n");
2cb37728
SG		 1118 return PTR_ERR(phydev);
1119 }
1120
58056c1e
AL		 1121 phy_set_max_speed(phydev, SPEED_100);
1122
2cb37728 1123 /* mask with MAC supported features */
af8d9bb2 1124 phy_support_asym_pause(phydev);
2cb37728 1125
2220943a
AL		 1126 phy_attached_info(phydev);
1127
2cb37728
SG		 1128 pd->last_duplex = -1;
1129 pd->last_carrier = -1;
1130
1131 return 0;
1132}
1133
1134static int smsc9420_mii_init(struct net_device *dev)
1135{
1136 struct smsc9420_pdata *pd = netdev_priv(dev);
e7f4dc35 1137 int err = -ENXIO;
2cb37728
SG		 1138
1139 pd->mii_bus = mdiobus_alloc();
1140 if (!pd->mii_bus) {
1141 err = -ENOMEM;
1142 goto err_out_1;
1143 }
1144 pd->mii_bus->name = DRV_MDIONAME;
1145 snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x",
1146 (pd->pdev->bus->number << 8) | pd->pdev->devfn);
1147 pd->mii_bus->priv = pd;
1148 pd->mii_bus->read = smsc9420_mii_read;
1149 pd->mii_bus->write = smsc9420_mii_write;
2cb37728
SG		 1150
1151 /* Mask all PHYs except ID 1 (internal) */
1152 pd->mii_bus->phy_mask = ~(1 << 1);
1153
1154 if (mdiobus_register(pd->mii_bus)) {
acec6d75 1155 netif_warn(pd, probe, pd->dev, "Error registering mii bus\n");
2cb37728
SG		 1156 goto err_out_free_bus_2;
1157 }
1158
1159 if (smsc9420_mii_probe(dev) < 0) {
acec6d75 1160 netif_warn(pd, probe, pd->dev, "Error probing mii bus\n");
2cb37728
SG		 1161 goto err_out_unregister_bus_3;
1162 }
1163
1164 return 0;
1165
1166err_out_unregister_bus_3:
1167 mdiobus_unregister(pd->mii_bus);
1168err_out_free_bus_2:
1169 mdiobus_free(pd->mii_bus);
1170err_out_1:
1171 return err;
1172}
1173
1174static int smsc9420_alloc_tx_ring(struct smsc9420_pdata *pd)
1175{
1176 int i;
1177
1178 BUG_ON(!pd->tx_ring);
1179
14f8dc49
JP		 1180 pd->tx_buffers = kmalloc_array(TX_RING_SIZE,
1181 sizeof(struct smsc9420_ring_info),
1182 GFP_KERNEL);
1183 if (!pd->tx_buffers)
2cb37728 1184 return -ENOMEM;
2cb37728
SG		 1185
1186 /* Initialize the TX Ring */
1187 for (i = 0; i < TX_RING_SIZE; i++) {
1188 pd->tx_buffers[i].skb = NULL;
1189 pd->tx_buffers[i].mapping = 0;
1190 pd->tx_ring[i].status = 0;
1191 pd->tx_ring[i].length = 0;
1192 pd->tx_ring[i].buffer1 = 0;
1193 pd->tx_ring[i].buffer2 = 0;
1194 }
1195 pd->tx_ring[TX_RING_SIZE - 1].length = TDES1_TER_;
1196 wmb();
1197
1198 pd->tx_ring_head = 0;
1199 pd->tx_ring_tail = 0;
1200
1201 smsc9420_reg_write(pd, TX_BASE_ADDR, pd->tx_dma_addr);
1202 smsc9420_pci_flush_write(pd);
1203
1204 return 0;
1205}
1206
1207static int smsc9420_alloc_rx_ring(struct smsc9420_pdata *pd)
1208{
1209 int i;
1210
1211 BUG_ON(!pd->rx_ring);
1212
acec6d75
JP		 1213 pd->rx_buffers = kmalloc_array(RX_RING_SIZE,
1214 sizeof(struct smsc9420_ring_info),
1215 GFP_KERNEL);
1216 if (pd->rx_buffers == NULL)
2cb37728 1217 goto out;
2cb37728
SG		 1218
1219 /* initialize the rx ring */
1220 for (i = 0; i < RX_RING_SIZE; i++) {
1221 pd->rx_ring[i].status = 0;
1222 pd->rx_ring[i].length = PKT_BUF_SZ;
1223 pd->rx_ring[i].buffer2 = 0;
1224 pd->rx_buffers[i].skb = NULL;
1225 pd->rx_buffers[i].mapping = 0;
1226 }
1227 pd->rx_ring[RX_RING_SIZE - 1].length = (PKT_BUF_SZ | RDES1_RER_);
1228
1229 /* now allocate the entire ring of skbs */
1230 for (i = 0; i < RX_RING_SIZE; i++) {
1231 if (smsc9420_alloc_rx_buffer(pd, i)) {
acec6d75
JP		 1232 netif_warn(pd, ifup, pd->dev,
1233 "failed to allocate rx skb %d\n", i);
2cb37728
SG		 1234 goto out_free_rx_skbs;
1235 }
1236 }
1237
1238 pd->rx_ring_head = 0;
1239 pd->rx_ring_tail = 0;
1240
1241 smsc9420_reg_write(pd, VLAN1, ETH_P_8021Q);
acec6d75
JP		 1242 netif_dbg(pd, ifup, pd->dev, "VLAN1 = 0x%08x\n",
1243 smsc9420_reg_read(pd, VLAN1));
2cb37728
SG		 1244
1245 if (pd->rx_csum) {
1246 /* Enable RX COE */
1247 u32 coe = smsc9420_reg_read(pd, COE_CR) | RX_COE_EN;
1248 smsc9420_reg_write(pd, COE_CR, coe);
acec6d75 1249 netif_dbg(pd, ifup, pd->dev, "COE_CR = 0x%08x\n", coe);
2cb37728
SG		 1250 }
1251
1252 smsc9420_reg_write(pd, RX_BASE_ADDR, pd->rx_dma_addr);
1253 smsc9420_pci_flush_write(pd);
1254
1255 return 0;
1256
1257out_free_rx_skbs:
1258 smsc9420_free_rx_ring(pd);
1259out:
1260 return -ENOMEM;
1261}
1262
1263static int smsc9420_open(struct net_device *dev)
1264{
b5a80837 1265 struct smsc9420_pdata *pd = netdev_priv(dev);
2cb37728 1266 u32 bus_mode, mac_cr, dmac_control, int_cfg, dma_intr_ena, int_ctl;
b5a80837 1267 const int irq = pd->pdev->irq;
2cb37728
SG		 1268 unsigned long flags;
1269 int result = 0, timeout;
1270
2cb37728 1271 if (!is_valid_ether_addr(dev->dev_addr)) {
acec6d75
JP		 1272 netif_warn(pd, ifup, pd->dev,
1273 "dev_addr is not a valid MAC address\n");
2cb37728
SG		 1274 result = -EADDRNOTAVAIL;
1275 goto out_0;
1276 }
1277
1278 netif_carrier_off(dev);
1279
3ad2f3fb 1280 /* disable, mask and acknowledge all interrupts */
2cb37728
SG		 1281 spin_lock_irqsave(&pd->int_lock, flags);
1282 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1283 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1284 smsc9420_reg_write(pd, INT_CTL, 0);
1285 spin_unlock_irqrestore(&pd->int_lock, flags);
1286 smsc9420_reg_write(pd, DMAC_INTR_ENA, 0);
1287 smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF);
1288 smsc9420_pci_flush_write(pd);
1289
cf68ca1e 1290 result = request_irq(irq, smsc9420_isr, IRQF_SHARED, DRV_NAME, pd);
b5a80837 1291 if (result) {
acec6d75 1292 netif_warn(pd, ifup, pd->dev, "Unable to use IRQ = %d\n", irq);
2cb37728
SG		 1293 result = -ENODEV;
1294 goto out_0;
1295 }
1296
1297 smsc9420_dmac_soft_reset(pd);
1298
1299 /* make sure MAC_CR is sane */
1300 smsc9420_reg_write(pd, MAC_CR, 0);
1301
1302 smsc9420_set_mac_address(dev);
1303
1304 /* Configure GPIO pins to drive LEDs */
1305 smsc9420_reg_write(pd, GPIO_CFG,
1306 (GPIO_CFG_LED_3_ | GPIO_CFG_LED_2_ | GPIO_CFG_LED_1_));
1307
1308 bus_mode = BUS_MODE_DMA_BURST_LENGTH_16;
1309
1310#ifdef __BIG_ENDIAN
1311 bus_mode |= BUS_MODE_DBO_;
1312#endif
1313
1314 smsc9420_reg_write(pd, BUS_MODE, bus_mode);
1315
1316 smsc9420_pci_flush_write(pd);
1317
1318 /* set bus master bridge arbitration priority for Rx and TX DMA */
1319 smsc9420_reg_write(pd, BUS_CFG, BUS_CFG_RXTXWEIGHT_4_1);
1320
1321 smsc9420_reg_write(pd, DMAC_CONTROL,
1322 (DMAC_CONTROL_SF_ | DMAC_CONTROL_OSF_));
1323
1324 smsc9420_pci_flush_write(pd);
1325
1326 /* test the IRQ connection to the ISR */
acec6d75 1327 netif_dbg(pd, ifup, pd->dev, "Testing ISR using IRQ %d\n", irq);
16095595 1328 pd->software_irq_signal = false;
2cb37728
SG		 1329
1330 spin_lock_irqsave(&pd->int_lock, flags);
1331 /* configure interrupt deassertion timer and enable interrupts */
1332 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1333 int_cfg &= ~(INT_CFG_INT_DEAS_MASK);
1334 int_cfg |= (INT_DEAS_TIME & INT_CFG_INT_DEAS_MASK);
1335 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1336
1337 /* unmask software interrupt */
1338 int_ctl = smsc9420_reg_read(pd, INT_CTL) | INT_CTL_SW_INT_EN_;
1339 smsc9420_reg_write(pd, INT_CTL, int_ctl);
1340 spin_unlock_irqrestore(&pd->int_lock, flags);
1341 smsc9420_pci_flush_write(pd);
1342
1343 timeout = 1000;
2cb37728
SG		 1344 while (timeout--) {
1345 if (pd->software_irq_signal)
1346 break;
1347 msleep(1);
1348 }
1349
1350 /* disable interrupts */
1351 spin_lock_irqsave(&pd->int_lock, flags);
1352 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1353 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1354 spin_unlock_irqrestore(&pd->int_lock, flags);
1355
1356 if (!pd->software_irq_signal) {
acec6d75 1357 netif_warn(pd, ifup, pd->dev, "ISR failed signaling test\n");
2cb37728
SG		 1358 result = -ENODEV;
1359 goto out_free_irq_1;
1360 }
1361
acec6d75 1362 netif_dbg(pd, ifup, pd->dev, "ISR passed test using IRQ %d\n", irq);
2cb37728
SG		 1363
1364 result = smsc9420_alloc_tx_ring(pd);
1365 if (result) {
acec6d75
JP		 1366 netif_warn(pd, ifup, pd->dev,
1367 "Failed to Initialize tx dma ring\n");
2cb37728
SG		 1368 result = -ENOMEM;
1369 goto out_free_irq_1;
1370 }
1371
1372 result = smsc9420_alloc_rx_ring(pd);
1373 if (result) {
acec6d75
JP		 1374 netif_warn(pd, ifup, pd->dev,
1375 "Failed to Initialize rx dma ring\n");
2cb37728
SG		 1376 result = -ENOMEM;
1377 goto out_free_tx_ring_2;
1378 }
1379
1380 result = smsc9420_mii_init(dev);
1381 if (result) {
acec6d75 1382 netif_warn(pd, ifup, pd->dev, "Failed to initialize Phy\n");
2cb37728
SG		 1383 result = -ENODEV;
1384 goto out_free_rx_ring_3;
1385 }
1386
1387 /* Bring the PHY up */
5d872c50 1388 phy_start(dev->phydev);
2cb37728
SG		 1389
1390 napi_enable(&pd->napi);
1391
1392 /* start tx and rx */
1393 mac_cr = smsc9420_reg_read(pd, MAC_CR) | MAC_CR_TXEN_ | MAC_CR_RXEN_;
1394 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1395
1396 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
1397 dmac_control |= DMAC_CONTROL_ST_ | DMAC_CONTROL_SR_;
1398 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
1399 smsc9420_pci_flush_write(pd);
1400
1401 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
1402 dma_intr_ena |=
1403 (DMAC_INTR_ENA_TX_ | DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
1404 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
1405 smsc9420_pci_flush_write(pd);
1406
1407 netif_wake_queue(dev);
1408
1409 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
1410
1411 /* enable interrupts */
1412 spin_lock_irqsave(&pd->int_lock, flags);
1413 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1414 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1415 spin_unlock_irqrestore(&pd->int_lock, flags);
1416
1417 return 0;
1418
1419out_free_rx_ring_3:
1420 smsc9420_free_rx_ring(pd);
1421out_free_tx_ring_2:
1422 smsc9420_free_tx_ring(pd);
1423out_free_irq_1:
b5a80837 1424 free_irq(irq, pd);
2cb37728
SG		 1425out_0:
1426 return result;
1427}
1428
53fff2bf 1429static int __maybe_unused smsc9420_suspend(struct device *dev_d)
2cb37728 1430{
53fff2bf 1431 struct net_device *dev = dev_get_drvdata(dev_d);
2cb37728
SG		 1432 struct smsc9420_pdata *pd = netdev_priv(dev);
1433 u32 int_cfg;
1434 ulong flags;
1435
1436 /* disable interrupts */
1437 spin_lock_irqsave(&pd->int_lock, flags);
1438 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1439 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1440 spin_unlock_irqrestore(&pd->int_lock, flags);
1441
1442 if (netif_running(dev)) {
1443 netif_tx_disable(dev);
1444 smsc9420_stop_tx(pd);
1445 smsc9420_free_tx_ring(pd);
1446
1447 napi_disable(&pd->napi);
1448 smsc9420_stop_rx(pd);
1449 smsc9420_free_rx_ring(pd);
1450
b5a80837 1451 free_irq(pd->pdev->irq, pd);
2cb37728
SG		 1452
1453 netif_device_detach(dev);
1454 }
1455
53fff2bf 1456 device_wakeup_disable(dev_d);
2cb37728
SG		 1457
1458 return 0;
1459}
1460
53fff2bf 1461static int __maybe_unused smsc9420_resume(struct device *dev_d)
2cb37728 1462{
53fff2bf 1463 struct net_device *dev = dev_get_drvdata(dev_d);
2cb37728
SG		 1464 int err;
1465
53fff2bf 1466 pci_set_master(to_pci_dev(dev_d));
2cb37728 1467
53fff2bf 1468 device_wakeup_disable(dev_d);
2cb37728 1469
53fff2bf 1470 err = 0;
2cb37728 1471 if (netif_running(dev)) {
b5a80837 1472 /* FIXME: gross. It looks like ancient PM relic.*/
2cb37728
SG		 1473 err = smsc9420_open(dev);
1474 netif_device_attach(dev);
1475 }
1476 return err;
1477}
1478
2cb37728
SG		 1479static const struct net_device_ops smsc9420_netdev_ops = {
1480 .ndo_open = smsc9420_open,
1481 .ndo_stop = smsc9420_stop,
1482 .ndo_start_xmit = smsc9420_hard_start_xmit,
1483 .ndo_get_stats = smsc9420_get_stats,
afc4b13d 1484 .ndo_set_rx_mode = smsc9420_set_multicast_list,
a7605370 1485 .ndo_eth_ioctl = phy_do_ioctl_running,
2cb37728 1486 .ndo_validate_addr = eth_validate_addr,
fe96aaa1 1487 .ndo_set_mac_address = eth_mac_addr,
e312674f
SG		 1488#ifdef CONFIG_NET_POLL_CONTROLLER
1489 .ndo_poll_controller = smsc9420_poll_controller,
1490#endif /* CONFIG_NET_POLL_CONTROLLER */
2cb37728
SG		 1491};
1492
f3f9e509 1493static int
2cb37728
SG		 1494smsc9420_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1495{
1496 struct net_device *dev;
1497 struct smsc9420_pdata *pd;
1498 void __iomem *virt_addr;
1499 int result = 0;
1500 u32 id_rev;
1501
acec6d75 1502 pr_info("%s version %s\n", DRV_DESCRIPTION, DRV_VERSION);
2cb37728
SG		 1503
1504 /* First do the PCI initialisation */
1505 result = pci_enable_device(pdev);
1506 if (unlikely(result)) {
48005993 1507 pr_err("Cannot enable smsc9420\n");
2cb37728
SG		 1508 goto out_0;
1509 }
1510
1511 pci_set_master(pdev);
1512
1513 dev = alloc_etherdev(sizeof(*pd));
41de8d4c 1514 if (!dev)
2cb37728 1515 goto out_disable_pci_device_1;
2cb37728
SG		 1516
1517 SET_NETDEV_DEV(dev, &pdev->dev);
1518
1519 if (!(pci_resource_flags(pdev, SMSC_BAR) & IORESOURCE_MEM)) {
48005993 1520 netdev_err(dev, "Cannot find PCI device base address\n");
2cb37728
SG		 1521 goto out_free_netdev_2;
1522 }
1523
1524 if ((pci_request_regions(pdev, DRV_NAME))) {
acec6d75 1525 netdev_err(dev, "Cannot obtain PCI resources, aborting\n");
2cb37728
SG		 1526 goto out_free_netdev_2;
1527 }
1528
3ab1270b 1529 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
acec6d75 1530 netdev_err(dev, "No usable DMA configuration, aborting\n");
2cb37728
SG		 1531 goto out_free_regions_3;
1532 }
1533
1534 virt_addr = ioremap(pci_resource_start(pdev, SMSC_BAR),
1535 pci_resource_len(pdev, SMSC_BAR));
1536 if (!virt_addr) {
acec6d75 1537 netdev_err(dev, "Cannot map device registers, aborting\n");
2cb37728
SG		 1538 goto out_free_regions_3;
1539 }
1540
1541 /* registers are double mapped with 0 offset for LE and 0x200 for BE */
1542 virt_addr += LAN9420_CPSR_ENDIAN_OFFSET;
1543
2cb37728
SG		 1544 pd = netdev_priv(dev);
1545
1546 /* pci descriptors are created in the PCI consistent area */
3ab1270b
CJ		 1547 pd->rx_ring = dma_alloc_coherent(&pdev->dev,
1548 sizeof(struct smsc9420_dma_desc) * (RX_RING_SIZE + TX_RING_SIZE),
1549 &pd->rx_dma_addr, GFP_KERNEL);
2cb37728
SG		 1550
1551 if (!pd->rx_ring)
1552 goto out_free_io_4;
1553
1554 /* descriptors are aligned due to the nature of pci_alloc_consistent */
64699336 1555 pd->tx_ring = (pd->rx_ring + RX_RING_SIZE);
2cb37728
SG		 1556 pd->tx_dma_addr = pd->rx_dma_addr +
1557 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE;
1558
1559 pd->pdev = pdev;
1560 pd->dev = dev;
b5a80837 1561 pd->ioaddr = virt_addr;
2cb37728
SG		 1562 pd->msg_enable = smsc_debug;
1563 pd->rx_csum = true;
1564
acec6d75 1565 netif_dbg(pd, probe, pd->dev, "lan_base=0x%08lx\n", (ulong)virt_addr);
2cb37728
SG		 1566
1567 id_rev = smsc9420_reg_read(pd, ID_REV);
1568 switch (id_rev & 0xFFFF0000) {
1569 case 0x94200000:
acec6d75
JP		 1570 netif_info(pd, probe, pd->dev,
1571 "LAN9420 identified, ID_REV=0x%08X\n", id_rev);
2cb37728
SG		 1572 break;
1573 default:
acec6d75
JP		 1574 netif_warn(pd, probe, pd->dev, "LAN9420 NOT identified\n");
1575 netif_warn(pd, probe, pd->dev, "ID_REV=0x%08X\n", id_rev);
2cb37728
SG		 1576 goto out_free_dmadesc_5;
1577 }
1578
1579 smsc9420_dmac_soft_reset(pd);
1580 smsc9420_eeprom_reload(pd);
1581 smsc9420_check_mac_address(dev);
1582
1583 dev->netdev_ops = &smsc9420_netdev_ops;
1584 dev->ethtool_ops = &smsc9420_ethtool_ops;
2cb37728
SG		 1585
1586 netif_napi_add(dev, &pd->napi, smsc9420_rx_poll, NAPI_WEIGHT);
1587
1588 result = register_netdev(dev);
1589 if (result) {
acec6d75
JP		 1590 netif_warn(pd, probe, pd->dev, "error %i registering device\n",
1591 result);
2cb37728
SG		 1592 goto out_free_dmadesc_5;
1593 }
1594
1595 pci_set_drvdata(pdev, dev);
1596
1597 spin_lock_init(&pd->int_lock);
1598 spin_lock_init(&pd->phy_lock);
1599
1600 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
1601
1602 return 0;
1603
1604out_free_dmadesc_5:
3ab1270b
CJ		 1605 dma_free_coherent(&pdev->dev,
1606 sizeof(struct smsc9420_dma_desc) * (RX_RING_SIZE + TX_RING_SIZE),
1607 pd->rx_ring, pd->rx_dma_addr);
2cb37728
SG		 1608out_free_io_4:
1609 iounmap(virt_addr - LAN9420_CPSR_ENDIAN_OFFSET);
1610out_free_regions_3:
1611 pci_release_regions(pdev);
1612out_free_netdev_2:
1613 free_netdev(dev);
1614out_disable_pci_device_1:
1615 pci_disable_device(pdev);
1616out_0:
1617 return -ENODEV;
1618}
1619
f3f9e509 1620static void smsc9420_remove(struct pci_dev *pdev)
2cb37728
SG		 1621{
1622 struct net_device *dev;
1623 struct smsc9420_pdata *pd;
1624
1625 dev = pci_get_drvdata(pdev);
1626 if (!dev)
1627 return;
2cb37728
SG		 1628
1629 pd = netdev_priv(dev);
1630 unregister_netdev(dev);
1631
1632 /* tx_buffers and rx_buffers are freed in stop */
1633 BUG_ON(pd->tx_buffers);
1634 BUG_ON(pd->rx_buffers);
1635
1636 BUG_ON(!pd->tx_ring);
1637 BUG_ON(!pd->rx_ring);
1638
3ab1270b
CJ		 1639 dma_free_coherent(&pdev->dev,
1640 sizeof(struct smsc9420_dma_desc) * (RX_RING_SIZE + TX_RING_SIZE),
1641 pd->rx_ring, pd->rx_dma_addr);
2cb37728 1642
b5a80837 1643 iounmap(pd->ioaddr - LAN9420_CPSR_ENDIAN_OFFSET);
2cb37728
SG		 1644 pci_release_regions(pdev);
1645 free_netdev(dev);
1646 pci_disable_device(pdev);
1647}
1648
53fff2bf
VG		 1649static SIMPLE_DEV_PM_OPS(smsc9420_pm_ops, smsc9420_suspend, smsc9420_resume);
1650
2cb37728
SG		 1651static struct pci_driver smsc9420_driver = {
1652 .name = DRV_NAME,
1653 .id_table = smsc9420_id_table,
1654 .probe = smsc9420_probe,
f3f9e509 1655 .remove = smsc9420_remove,
53fff2bf 1656 .driver.pm = &smsc9420_pm_ops,
2cb37728
SG		 1657};
1658
1659static int __init smsc9420_init_module(void)
1660{
1661 smsc_debug = netif_msg_init(debug, SMSC_MSG_DEFAULT);
1662
1663 return pci_register_driver(&smsc9420_driver);
1664}
1665
1666static void __exit smsc9420_exit_module(void)
1667{
1668 pci_unregister_driver(&smsc9420_driver);
1669}
1670
1671module_init(smsc9420_init_module);
1672module_exit(smsc9420_exit_module);
Linux 6.x block layer and io_uring tree(s)