[linux-2.6-block.git] / drivers / net / ethernet / smsc / smsc911x.h

/***************************************************************************
 *
 * Copyright (C) 2004-2008 SMSC
 * Copyright (C) 2005-2008 ARM
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see <http://www.gnu.org/licenses/>.
 *
 ***************************************************************************/
#ifndef __SMSC911X_H__
#define __SMSC911X_H__

/*Chip ID*/
#define LAN9115	0x01150000
#define LAN9116	0x01160000
#define LAN9117	0x01170000
#define LAN9118	0x01180000
#define LAN9215	0x115A0000
#define LAN9216	0x116A0000
#define LAN9217	0x117A0000
#define LAN9218	0x118A0000
#define LAN9210	0x92100000
#define LAN9211	0x92110000
#define LAN9220	0x92200000
#define LAN9221	0x92210000
#define LAN9250	0x92500000
#define LAN89218	0x218A0000

#define TX_FIFO_LOW_THRESHOLD	((u32)1600)
#define SMSC911X_EEPROM_SIZE	((u32)128)
#define USE_DEBUG		0

/* This is the maximum number of packets to be received every
 * NAPI poll */
#define SMSC_NAPI_WEIGHT	16

/* implements a PHY loopback test at initialisation time, to ensure a packet
 * can be successfully looped back */
#define USE_PHY_WORK_AROUND

#if USE_DEBUG >= 1
#define SMSC_WARN(pdata, nlevel, fmt, args...)			\
	netif_warn(pdata, nlevel, (pdata)->dev,			\
		   "%s: " fmt "\n", __func__, ##args)
#else
#define SMSC_WARN(pdata, nlevel, fmt, args...)			\
	no_printk(fmt "\n", ##args)
#endif

#if USE_DEBUG >= 2
#define SMSC_TRACE(pdata, nlevel, fmt, args...)			\
	netif_info(pdata, nlevel, pdata->dev, fmt "\n", ##args)
#else
#define SMSC_TRACE(pdata, nlevel, fmt, args...)			\
	no_printk(fmt "\n", ##args)
#endif

#ifdef CONFIG_DEBUG_SPINLOCK
#define SMSC_ASSERT_MAC_LOCK(pdata) \
		WARN_ON_SMP(!spin_is_locked(&pdata->mac_lock))
#else
#define SMSC_ASSERT_MAC_LOCK(pdata) do {} while (0)
#endif				/* CONFIG_DEBUG_SPINLOCK */

/* SMSC911x registers and bitfields */
#define RX_DATA_FIFO			0x00

#define TX_DATA_FIFO			0x20
#define TX_CMD_A_ON_COMP_		0x80000000
#define TX_CMD_A_BUF_END_ALGN_		0x03000000
#define TX_CMD_A_4_BYTE_ALGN_		0x00000000
#define TX_CMD_A_16_BYTE_ALGN_		0x01000000
#define TX_CMD_A_32_BYTE_ALGN_		0x02000000
#define TX_CMD_A_DATA_OFFSET_		0x001F0000
#define TX_CMD_A_FIRST_SEG_		0x00002000
#define TX_CMD_A_LAST_SEG_		0x00001000
#define TX_CMD_A_BUF_SIZE_		0x000007FF
#define TX_CMD_B_PKT_TAG_		0xFFFF0000
#define TX_CMD_B_ADD_CRC_DISABLE_	0x00002000
#define TX_CMD_B_DISABLE_PADDING_	0x00001000
#define TX_CMD_B_PKT_BYTE_LENGTH_	0x000007FF

#define RX_STATUS_FIFO			0x40
#define RX_STS_ES_			0x00008000
#define RX_STS_LENGTH_ERR_		0x00001000
#define RX_STS_MCAST_			0x00000400
#define RX_STS_FRAME_TYPE_		0x00000020
#define RX_STS_CRC_ERR_			0x00000002

#define RX_STATUS_FIFO_PEEK		0x44

#define TX_STATUS_FIFO			0x48
#define TX_STS_ES_			0x00008000
#define TX_STS_LOST_CARRIER_		0x00000800
#define TX_STS_NO_CARRIER_		0x00000400
#define TX_STS_LATE_COL_		0x00000200
#define TX_STS_EXCESS_COL_		0x00000100

#define TX_STATUS_FIFO_PEEK		0x4C

#define ID_REV				0x50
#define ID_REV_CHIP_ID_			0xFFFF0000
#define ID_REV_REV_ID_			0x0000FFFF

#define INT_CFG				0x54
#define INT_CFG_INT_DEAS_		0xFF000000
#define INT_CFG_INT_DEAS_CLR_		0x00004000
#define INT_CFG_INT_DEAS_STS_		0x00002000
#define INT_CFG_IRQ_INT_		0x00001000
#define INT_CFG_IRQ_EN_			0x00000100
#define INT_CFG_IRQ_POL_		0x00000010
#define INT_CFG_IRQ_TYPE_		0x00000001

#define INT_STS				0x58
#define INT_STS_SW_INT_			0x80000000
#define INT_STS_TXSTOP_INT_		0x02000000
#define INT_STS_RXSTOP_INT_		0x01000000
#define INT_STS_RXDFH_INT_		0x00800000
#define INT_STS_RXDF_INT_		0x00400000
#define INT_STS_TX_IOC_			0x00200000
#define INT_STS_RXD_INT_		0x00100000
#define INT_STS_GPT_INT_		0x00080000
#define INT_STS_PHY_INT_		0x00040000
#define INT_STS_PME_INT_		0x00020000
#define INT_STS_TXSO_			0x00010000
#define INT_STS_RWT_			0x00008000
#define INT_STS_RXE_			0x00004000
#define INT_STS_TXE_			0x00002000
#define INT_STS_TDFU_			0x00000800
#define INT_STS_TDFO_			0x00000400
#define INT_STS_TDFA_			0x00000200
#define INT_STS_TSFF_			0x00000100
#define INT_STS_TSFL_			0x00000080
#define INT_STS_RXDF_			0x00000040
#define INT_STS_RDFL_			0x00000020
#define INT_STS_RSFF_			0x00000010
#define INT_STS_RSFL_			0x00000008
#define INT_STS_GPIO2_INT_		0x00000004
#define INT_STS_GPIO1_INT_		0x00000002
#define INT_STS_GPIO0_INT_		0x00000001

#define INT_EN				0x5C
#define INT_EN_SW_INT_EN_		0x80000000
#define INT_EN_TXSTOP_INT_EN_		0x02000000
#define INT_EN_RXSTOP_INT_EN_		0x01000000
#define INT_EN_RXDFH_INT_EN_		0x00800000
#define INT_EN_TIOC_INT_EN_		0x00200000
#define INT_EN_RXD_INT_EN_		0x00100000
#define INT_EN_GPT_INT_EN_		0x00080000
#define INT_EN_PHY_INT_EN_		0x00040000
#define INT_EN_PME_INT_EN_		0x00020000
#define INT_EN_TXSO_EN_			0x00010000
#define INT_EN_RWT_EN_			0x00008000
#define INT_EN_RXE_EN_			0x00004000
#define INT_EN_TXE_EN_			0x00002000
#define INT_EN_TDFU_EN_			0x00000800
#define INT_EN_TDFO_EN_			0x00000400
#define INT_EN_TDFA_EN_			0x00000200
#define INT_EN_TSFF_EN_			0x00000100
#define INT_EN_TSFL_EN_			0x00000080
#define INT_EN_RXDF_EN_			0x00000040
#define INT_EN_RDFL_EN_			0x00000020
#define INT_EN_RSFF_EN_			0x00000010
#define INT_EN_RSFL_EN_			0x00000008
#define INT_EN_GPIO2_INT_		0x00000004
#define INT_EN_GPIO1_INT_		0x00000002
#define INT_EN_GPIO0_INT_		0x00000001

#define BYTE_TEST			0x64

#define FIFO_INT			0x68
#define FIFO_INT_TX_AVAIL_LEVEL_	0xFF000000
#define FIFO_INT_TX_STS_LEVEL_		0x00FF0000
#define FIFO_INT_RX_AVAIL_LEVEL_	0x0000FF00
#define FIFO_INT_RX_STS_LEVEL_		0x000000FF

#define RX_CFG				0x6C
#define RX_CFG_RX_END_ALGN_		0xC0000000
#define RX_CFG_RX_END_ALGN4_		0x00000000
#define RX_CFG_RX_END_ALGN16_		0x40000000
#define RX_CFG_RX_END_ALGN32_		0x80000000
#define RX_CFG_RX_DMA_CNT_		0x0FFF0000
#define RX_CFG_RX_DUMP_			0x00008000
#define RX_CFG_RXDOFF_			0x00001F00

#define TX_CFG				0x70
#define TX_CFG_TXS_DUMP_		0x00008000
#define TX_CFG_TXD_DUMP_		0x00004000
#define TX_CFG_TXSAO_			0x00000004
#define TX_CFG_TX_ON_			0x00000002
#define TX_CFG_STOP_TX_			0x00000001

#define HW_CFG				0x74
#define HW_CFG_TTM_			0x00200000
#define HW_CFG_SF_			0x00100000
#define HW_CFG_TX_FIF_SZ_		0x000F0000
#define HW_CFG_TR_			0x00003000
#define HW_CFG_SRST_			0x00000001

/* only available on 115/117 */
#define HW_CFG_PHY_CLK_SEL_		0x00000060
#define HW_CFG_PHY_CLK_SEL_INT_PHY_	0x00000000
#define HW_CFG_PHY_CLK_SEL_EXT_PHY_	0x00000020
#define HW_CFG_PHY_CLK_SEL_CLK_DIS_	0x00000040
#define HW_CFG_SMI_SEL_		 	0x00000010
#define HW_CFG_EXT_PHY_DET_		0x00000008
#define HW_CFG_EXT_PHY_EN_		0x00000004
#define HW_CFG_SRST_TO_			0x00000002

/* only available  on 116/118 */
#define HW_CFG_32_16_BIT_MODE_		0x00000004

#define RX_DP_CTRL			0x78
#define RX_DP_CTRL_RX_FFWD_		0x80000000

#define RX_FIFO_INF			0x7C
#define RX_FIFO_INF_RXSUSED_		0x00FF0000
#define RX_FIFO_INF_RXDUSED_		0x0000FFFF

#define TX_FIFO_INF			0x80
#define TX_FIFO_INF_TSUSED_		0x00FF0000
#define TX_FIFO_INF_TDFREE_		0x0000FFFF

#define PMT_CTRL			0x84
#define PMT_CTRL_PM_MODE_		0x00003000
#define PMT_CTRL_PM_MODE_D0_		0x00000000
#define PMT_CTRL_PM_MODE_D1_		0x00001000
#define PMT_CTRL_PM_MODE_D2_		0x00002000
#define PMT_CTRL_PM_MODE_D3_		0x00003000
#define PMT_CTRL_PHY_RST_		0x00000400
#define PMT_CTRL_WOL_EN_		0x00000200
#define PMT_CTRL_ED_EN_			0x00000100
#define PMT_CTRL_PME_TYPE_		0x00000040
#define PMT_CTRL_WUPS_			0x00000030
#define PMT_CTRL_WUPS_NOWAKE_		0x00000000
#define PMT_CTRL_WUPS_ED_		0x00000010
#define PMT_CTRL_WUPS_WOL_		0x00000020
#define PMT_CTRL_WUPS_MULTI_		0x00000030
#define PMT_CTRL_PME_IND_		0x00000008
#define PMT_CTRL_PME_POL_		0x00000004
#define PMT_CTRL_PME_EN_		0x00000002
#define PMT_CTRL_READY_			0x00000001

#define GPIO_CFG			0x88
#define GPIO_CFG_LED3_EN_		0x40000000
#define GPIO_CFG_LED2_EN_		0x20000000
#define GPIO_CFG_LED1_EN_		0x10000000
#define GPIO_CFG_GPIO2_INT_POL_		0x04000000
#define GPIO_CFG_GPIO1_INT_POL_		0x02000000
#define GPIO_CFG_GPIO0_INT_POL_		0x01000000
#define GPIO_CFG_EEPR_EN_		0x00700000
#define GPIO_CFG_GPIOBUF2_		0x00040000
#define GPIO_CFG_GPIOBUF1_		0x00020000
#define GPIO_CFG_GPIOBUF0_		0x00010000
#define GPIO_CFG_GPIODIR2_		0x00000400
#define GPIO_CFG_GPIODIR1_		0x00000200
#define GPIO_CFG_GPIODIR0_		0x00000100
#define GPIO_CFG_GPIOD4_		0x00000020
#define GPIO_CFG_GPIOD3_		0x00000010
#define GPIO_CFG_GPIOD2_		0x00000004
#define GPIO_CFG_GPIOD1_		0x00000002
#define GPIO_CFG_GPIOD0_		0x00000001

#define GPT_CFG				0x8C
#define GPT_CFG_TIMER_EN_		0x20000000
#define GPT_CFG_GPT_LOAD_		0x0000FFFF

#define GPT_CNT				0x90
#define GPT_CNT_GPT_CNT_		0x0000FFFF

#define WORD_SWAP			0x98

#define FREE_RUN			0x9C

#define RX_DROP				0xA0

#define MAC_CSR_CMD			0xA4
#define MAC_CSR_CMD_CSR_BUSY_		0x80000000
#define MAC_CSR_CMD_R_NOT_W_		0x40000000
#define MAC_CSR_CMD_CSR_ADDR_		0x000000FF

#define MAC_CSR_DATA			0xA8

#define AFC_CFG				0xAC
#define AFC_CFG_AFC_HI_			0x00FF0000
#define AFC_CFG_AFC_LO_			0x0000FF00
#define AFC_CFG_BACK_DUR_		0x000000F0
#define AFC_CFG_FCMULT_			0x00000008
#define AFC_CFG_FCBRD_			0x00000004
#define AFC_CFG_FCADD_			0x00000002
#define AFC_CFG_FCANY_			0x00000001

#define E2P_CMD				0xB0
#define E2P_CMD_EPC_BUSY_		0x80000000
#define E2P_CMD_EPC_CMD_		0x70000000
#define E2P_CMD_EPC_CMD_READ_		0x00000000
#define E2P_CMD_EPC_CMD_EWDS_		0x10000000
#define E2P_CMD_EPC_CMD_EWEN_		0x20000000
#define E2P_CMD_EPC_CMD_WRITE_		0x30000000
#define E2P_CMD_EPC_CMD_WRAL_		0x40000000
#define E2P_CMD_EPC_CMD_ERASE_		0x50000000
#define E2P_CMD_EPC_CMD_ERAL_		0x60000000
#define E2P_CMD_EPC_CMD_RELOAD_		0x70000000
#define E2P_CMD_EPC_TIMEOUT_		0x00000200
#define E2P_CMD_MAC_ADDR_LOADED_	0x00000100
#define E2P_CMD_EPC_ADDR_		0x000000FF

#define E2P_DATA			0xB4
#define E2P_DATA_EEPROM_DATA_		0x000000FF
#define LAN_REGISTER_EXTENT		0x00000100

#define RESET_CTL			0x1F8
#define RESET_CTL_DIGITAL_RST_		0x00000001

/*
 * MAC Control and Status Register (Indirect Address)
 * Offset (through the MAC_CSR CMD and DATA port)
 */
#define MAC_CR				0x01
#define MAC_CR_RXALL_			0x80000000
#define MAC_CR_HBDIS_			0x10000000
#define MAC_CR_RCVOWN_			0x00800000
#define MAC_CR_LOOPBK_			0x00200000
#define MAC_CR_FDPX_			0x00100000
#define MAC_CR_MCPAS_			0x00080000
#define MAC_CR_PRMS_			0x00040000
#define MAC_CR_INVFILT_			0x00020000
#define MAC_CR_PASSBAD_			0x00010000
#define MAC_CR_HFILT_			0x00008000
#define MAC_CR_HPFILT_			0x00002000
#define MAC_CR_LCOLL_			0x00001000
#define MAC_CR_BCAST_			0x00000800
#define MAC_CR_DISRTY_			0x00000400
#define MAC_CR_PADSTR_			0x00000100
#define MAC_CR_BOLMT_MASK_		0x000000C0
#define MAC_CR_DFCHK_			0x00000020
#define MAC_CR_TXEN_			0x00000008
#define MAC_CR_RXEN_			0x00000004

#define ADDRH				0x02

#define ADDRL				0x03

#define HASHH				0x04

#define HASHL				0x05

#define MII_ACC				0x06
#define MII_ACC_PHY_ADDR_		0x0000F800
#define MII_ACC_MIIRINDA_		0x000007C0
#define MII_ACC_MII_WRITE_		0x00000002
#define MII_ACC_MII_BUSY_		0x00000001

#define MII_DATA			0x07

#define FLOW				0x08
#define FLOW_FCPT_			0xFFFF0000
#define FLOW_FCPASS_			0x00000004
#define FLOW_FCEN_			0x00000002
#define FLOW_FCBSY_			0x00000001

#define VLAN1				0x09

#define VLAN2				0x0A

#define WUFF				0x0B

#define WUCSR				0x0C
#define WUCSR_GUE_			0x00000200
#define WUCSR_WUFR_			0x00000040
#define WUCSR_MPR_			0x00000020
#define WUCSR_WAKE_EN_			0x00000004
#define WUCSR_MPEN_			0x00000002

/*
 * Phy definitions (vendor-specific)
 */
#define LAN9118_PHY_ID			0x00C0001C

#define MII_INTSTS			0x1D

#define MII_INTMSK			0x1E
#define PHY_INTMSK_AN_RCV_		(1 << 1)
#define PHY_INTMSK_PDFAULT_		(1 << 2)
#define PHY_INTMSK_AN_ACK_		(1 << 3)
#define PHY_INTMSK_LNKDOWN_		(1 << 4)
#define PHY_INTMSK_RFAULT_		(1 << 5)
#define PHY_INTMSK_AN_COMP_		(1 << 6)
#define PHY_INTMSK_ENERGYON_		(1 << 7)
#define PHY_INTMSK_DEFAULT_		(PHY_INTMSK_ENERGYON_ | \
					 PHY_INTMSK_AN_COMP_ | \
					 PHY_INTMSK_RFAULT_ | \
					 PHY_INTMSK_LNKDOWN_)

#define ADVERTISE_PAUSE_ALL		(ADVERTISE_PAUSE_CAP | \
					 ADVERTISE_PAUSE_ASYM)

#define LPA_PAUSE_ALL			(LPA_PAUSE_CAP | \
					 LPA_PAUSE_ASYM)

/*
 * Provide hooks to let the arch add to the initialisation procedure
 * and to override the source of the MAC address.
 */
#define SMSC_INITIALIZE()		do {} while (0)
#define smsc_get_mac(dev)		smsc911x_read_mac_address((dev))

#ifdef CONFIG_SMSC911X_ARCH_HOOKS
#include <asm/smsc911x.h>
#endif

#include <linux/smscphy.h>

#endif				/* __SMSC911X_H__ */
Commit	Line	Data
fd9abb3d SG	1	/***************************************************************************
	2	*
	3	* Copyright (C) 2004-2008 SMSC
	4	* Copyright (C) 2005-2008 ARM
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
0ab75ae8	17	* along with this program; if not, see <http://www.gnu.org/licenses/>.
fd9abb3d SG	18	*
	19	***************************************************************************/
	20	#ifndef __SMSC911X_H__
	21	#define __SMSC911X_H__
	22
f6fec61e DC	23	/Chip ID/
	24	#define LAN9115 0x01150000
	25	#define LAN9116 0x01160000
	26	#define LAN9117 0x01170000
	27	#define LAN9118 0x01180000
	28	#define LAN9215 0x115A0000
	29	#define LAN9216 0x116A0000
	30	#define LAN9217 0x117A0000
	31	#define LAN9218 0x118A0000
	32	#define LAN9210 0x92100000
	33	#define LAN9211 0x92110000
	34	#define LAN9220 0x92200000
	35	#define LAN9221 0x92210000
	36	#define LAN9250 0x92500000
	37	#define LAN89218 0x218A0000
	38
fd9abb3d	39	#define TX_FIFO_LOW_THRESHOLD ((u32)1600)
6cc0e949	40	#define SMSC911X_EEPROM_SIZE ((u32)128)
fd9abb3d SG	41	#define USE_DEBUG 0
	42
	43	/* This is the maximum number of packets to be received every
	44	* NAPI poll */
	45	#define SMSC_NAPI_WEIGHT 16
	46
	47	/* implements a PHY loopback test at initialisation time, to ensure a packet
af901ca1	48	* can be successfully looped back */
fd9abb3d SG	49	#define USE_PHY_WORK_AROUND
fd9abb3d SG	50
fd9abb3d	51	#if USE_DEBUG >= 1
dffc6b24 JP	52	#define SMSC_WARN(pdata, nlevel, fmt, args...) \
	53	netif_warn(pdata, nlevel, (pdata)->dev, \
	54	"%s: " fmt "\n", __func__, ##args)
fd9abb3d	55	#else
dffc6b24 JP	56	#define SMSC_WARN(pdata, nlevel, fmt, args...) \
dffc6b24 JP	57	no_printk(fmt "\n", ##args)
fd9abb3d SG	58	#endif
	59
	60	#if USE_DEBUG >= 2
dffc6b24 JP	61	#define SMSC_TRACE(pdata, nlevel, fmt, args...) \
dffc6b24 JP	62	netif_info(pdata, nlevel, pdata->dev, fmt "\n", ##args)
fd9abb3d	63	#else
dffc6b24 JP	64	#define SMSC_TRACE(pdata, nlevel, fmt, args...) \
dffc6b24 JP	65	no_printk(fmt "\n", ##args)
fd9abb3d SG	66	#endif
	67
	68	#ifdef CONFIG_DEBUG_SPINLOCK
	69	#define SMSC_ASSERT_MAC_LOCK(pdata) \
200d7db7	70	WARN_ON_SMP(!spin_is_locked(&pdata->mac_lock))
fd9abb3d SG	71	#else
	72	#define SMSC_ASSERT_MAC_LOCK(pdata) do {} while (0)
	73	#endif /* CONFIG_DEBUG_SPINLOCK */
	74
fd9abb3d SG	75	/* SMSC911x registers and bitfields */
	76	#define RX_DATA_FIFO 0x00
	77
	78	#define TX_DATA_FIFO 0x20
	79	#define TX_CMD_A_ON_COMP_ 0x80000000
	80	#define TX_CMD_A_BUF_END_ALGN_ 0x03000000
	81	#define TX_CMD_A_4_BYTE_ALGN_ 0x00000000
	82	#define TX_CMD_A_16_BYTE_ALGN_ 0x01000000
	83	#define TX_CMD_A_32_BYTE_ALGN_ 0x02000000
	84	#define TX_CMD_A_DATA_OFFSET_ 0x001F0000
	85	#define TX_CMD_A_FIRST_SEG_ 0x00002000
	86	#define TX_CMD_A_LAST_SEG_ 0x00001000
	87	#define TX_CMD_A_BUF_SIZE_ 0x000007FF
	88	#define TX_CMD_B_PKT_TAG_ 0xFFFF0000
	89	#define TX_CMD_B_ADD_CRC_DISABLE_ 0x00002000
	90	#define TX_CMD_B_DISABLE_PADDING_ 0x00001000
	91	#define TX_CMD_B_PKT_BYTE_LENGTH_ 0x000007FF
	92
	93	#define RX_STATUS_FIFO 0x40
	94	#define RX_STS_ES_ 0x00008000
785b6f97	95	#define RX_STS_LENGTH_ERR_ 0x00001000
fd9abb3d	96	#define RX_STS_MCAST_ 0x00000400
785b6f97 SG	97	#define RX_STS_FRAME_TYPE_ 0x00000020
785b6f97 SG	98	#define RX_STS_CRC_ERR_ 0x00000002
fd9abb3d SG	99
	100	#define RX_STATUS_FIFO_PEEK 0x44
	101
	102	#define TX_STATUS_FIFO 0x48
	103	#define TX_STS_ES_ 0x00008000
785b6f97 SG	104	#define TX_STS_LOST_CARRIER_ 0x00000800
	105	#define TX_STS_NO_CARRIER_ 0x00000400
	106	#define TX_STS_LATE_COL_ 0x00000200
	107	#define TX_STS_EXCESS_COL_ 0x00000100
fd9abb3d SG	108
	109	#define TX_STATUS_FIFO_PEEK 0x4C
	110
	111	#define ID_REV 0x50
	112	#define ID_REV_CHIP_ID_ 0xFFFF0000
	113	#define ID_REV_REV_ID_ 0x0000FFFF
	114
	115	#define INT_CFG 0x54
	116	#define INT_CFG_INT_DEAS_ 0xFF000000
	117	#define INT_CFG_INT_DEAS_CLR_ 0x00004000
	118	#define INT_CFG_INT_DEAS_STS_ 0x00002000
	119	#define INT_CFG_IRQ_INT_ 0x00001000
	120	#define INT_CFG_IRQ_EN_ 0x00000100
	121	#define INT_CFG_IRQ_POL_ 0x00000010
	122	#define INT_CFG_IRQ_TYPE_ 0x00000001
	123
	124	#define INT_STS 0x58
	125	#define INT_STS_SW_INT_ 0x80000000
	126	#define INT_STS_TXSTOP_INT_ 0x02000000
	127	#define INT_STS_RXSTOP_INT_ 0x01000000
	128	#define INT_STS_RXDFH_INT_ 0x00800000
	129	#define INT_STS_RXDF_INT_ 0x00400000
	130	#define INT_STS_TX_IOC_ 0x00200000
	131	#define INT_STS_RXD_INT_ 0x00100000
	132	#define INT_STS_GPT_INT_ 0x00080000
	133	#define INT_STS_PHY_INT_ 0x00040000
	134	#define INT_STS_PME_INT_ 0x00020000
	135	#define INT_STS_TXSO_ 0x00010000
	136	#define INT_STS_RWT_ 0x00008000
	137	#define INT_STS_RXE_ 0x00004000
	138	#define INT_STS_TXE_ 0x00002000
	139	#define INT_STS_TDFU_ 0x00000800
	140	#define INT_STS_TDFO_ 0x00000400
	141	#define INT_STS_TDFA_ 0x00000200
	142	#define INT_STS_TSFF_ 0x00000100
	143	#define INT_STS_TSFL_ 0x00000080
	144	#define INT_STS_RXDF_ 0x00000040
	145	#define INT_STS_RDFL_ 0x00000020
	146	#define INT_STS_RSFF_ 0x00000010
	147	#define INT_STS_RSFL_ 0x00000008
	148	#define INT_STS_GPIO2_INT_ 0x00000004
	149	#define INT_STS_GPIO1_INT_ 0x00000002
	150	#define INT_STS_GPIO0_INT_ 0x00000001
	151
	152	#define INT_EN 0x5C
	153	#define INT_EN_SW_INT_EN_ 0x80000000
	154	#define INT_EN_TXSTOP_INT_EN_ 0x02000000
	155	#define INT_EN_RXSTOP_INT_EN_ 0x01000000
	156	#define INT_EN_RXDFH_INT_EN_ 0x00800000
	157	#define INT_EN_TIOC_INT_EN_ 0x00200000
	158	#define INT_EN_RXD_INT_EN_ 0x00100000
	159	#define INT_EN_GPT_INT_EN_ 0x00080000
	160	#define INT_EN_PHY_INT_EN_ 0x00040000
	161	#define INT_EN_PME_INT_EN_ 0x00020000
	162	#define INT_EN_TXSO_EN_ 0x00010000
	163	#define INT_EN_RWT_EN_ 0x00008000
	164	#define INT_EN_RXE_EN_ 0x00004000
	165	#define INT_EN_TXE_EN_ 0x00002000
	166	#define INT_EN_TDFU_EN_ 0x00000800
	167	#define INT_EN_TDFO_EN_ 0x00000400
	168	#define INT_EN_TDFA_EN_ 0x00000200
	169	#define INT_EN_TSFF_EN_ 0x00000100
	170	#define INT_EN_TSFL_EN_ 0x00000080
	171	#define INT_EN_RXDF_EN_ 0x00000040
172	#define INT_EN_RDFL_EN_ 0x00000020
173	#define INT_EN_RSFF_EN_ 0x00000010
174	#define INT_EN_RSFL_EN_ 0x00000008
175	#define INT_EN_GPIO2_INT_ 0x00000004
176	#define INT_EN_GPIO1_INT_ 0x00000002
177	#define INT_EN_GPIO0_INT_ 0x00000001
178
179	#define BYTE_TEST 0x64
180
181	#define FIFO_INT 0x68
182	#define FIFO_INT_TX_AVAIL_LEVEL_ 0xFF000000
183	#define FIFO_INT_TX_STS_LEVEL_ 0x00FF0000
184	#define FIFO_INT_RX_AVAIL_LEVEL_ 0x0000FF00
185	#define FIFO_INT_RX_STS_LEVEL_ 0x000000FF
186
187	#define RX_CFG 0x6C
188	#define RX_CFG_RX_END_ALGN_ 0xC0000000
189	#define RX_CFG_RX_END_ALGN4_ 0x00000000
190	#define RX_CFG_RX_END_ALGN16_ 0x40000000
191	#define RX_CFG_RX_END_ALGN32_ 0x80000000
192	#define RX_CFG_RX_DMA_CNT_ 0x0FFF0000
193	#define RX_CFG_RX_DUMP_ 0x00008000
194	#define RX_CFG_RXDOFF_ 0x00001F00
195
196	#define TX_CFG 0x70
197	#define TX_CFG_TXS_DUMP_ 0x00008000
198	#define TX_CFG_TXD_DUMP_ 0x00004000
199	#define TX_CFG_TXSAO_ 0x00000004
200	#define TX_CFG_TX_ON_ 0x00000002
201	#define TX_CFG_STOP_TX_ 0x00000001
202
203	#define HW_CFG 0x74
204	#define HW_CFG_TTM_ 0x00200000
205	#define HW_CFG_SF_ 0x00100000
206	#define HW_CFG_TX_FIF_SZ_ 0x000F0000
207	#define HW_CFG_TR_ 0x00003000
208	#define HW_CFG_SRST_ 0x00000001
209
210	/* only available on 115/117 */
211	#define HW_CFG_PHY_CLK_SEL_ 0x00000060
212	#define HW_CFG_PHY_CLK_SEL_INT_PHY_ 0x00000000
213	#define HW_CFG_PHY_CLK_SEL_EXT_PHY_ 0x00000020
214	#define HW_CFG_PHY_CLK_SEL_CLK_DIS_ 0x00000040
215	#define HW_CFG_SMI_SEL_ 0x00000010
216	#define HW_CFG_EXT_PHY_DET_ 0x00000008
217	#define HW_CFG_EXT_PHY_EN_ 0x00000004
218	#define HW_CFG_SRST_TO_ 0x00000002
219
220	/* only available on 116/118 */
221	#define HW_CFG_32_16_BIT_MODE_ 0x00000004
222
223	#define RX_DP_CTRL 0x78
224	#define RX_DP_CTRL_RX_FFWD_ 0x80000000
225
226	#define RX_FIFO_INF 0x7C
227	#define RX_FIFO_INF_RXSUSED_ 0x00FF0000
228	#define RX_FIFO_INF_RXDUSED_ 0x0000FFFF
229
230	#define TX_FIFO_INF 0x80
231	#define TX_FIFO_INF_TSUSED_ 0x00FF0000
232	#define TX_FIFO_INF_TDFREE_ 0x0000FFFF
233
234	#define PMT_CTRL 0x84
235	#define PMT_CTRL_PM_MODE_ 0x00003000
236	#define PMT_CTRL_PM_MODE_D0_ 0x00000000
237	#define PMT_CTRL_PM_MODE_D1_ 0x00001000
238	#define PMT_CTRL_PM_MODE_D2_ 0x00002000
239	#define PMT_CTRL_PM_MODE_D3_ 0x00003000
240	#define PMT_CTRL_PHY_RST_ 0x00000400
241	#define PMT_CTRL_WOL_EN_ 0x00000200
242	#define PMT_CTRL_ED_EN_ 0x00000100
243	#define PMT_CTRL_PME_TYPE_ 0x00000040
244	#define PMT_CTRL_WUPS_ 0x00000030
245	#define PMT_CTRL_WUPS_NOWAKE_ 0x00000000
246	#define PMT_CTRL_WUPS_ED_ 0x00000010
247	#define PMT_CTRL_WUPS_WOL_ 0x00000020
248	#define PMT_CTRL_WUPS_MULTI_ 0x00000030
249	#define PMT_CTRL_PME_IND_ 0x00000008
250	#define PMT_CTRL_PME_POL_ 0x00000004
251	#define PMT_CTRL_PME_EN_ 0x00000002
252	#define PMT_CTRL_READY_ 0x00000001
253
254	#define GPIO_CFG 0x88
255	#define GPIO_CFG_LED3_EN_ 0x40000000
256	#define GPIO_CFG_LED2_EN_ 0x20000000
257	#define GPIO_CFG_LED1_EN_ 0x10000000
258	#define GPIO_CFG_GPIO2_INT_POL_ 0x04000000
259	#define GPIO_CFG_GPIO1_INT_POL_ 0x02000000
260	#define GPIO_CFG_GPIO0_INT_POL_ 0x01000000
261	#define GPIO_CFG_EEPR_EN_ 0x00700000
262	#define GPIO_CFG_GPIOBUF2_ 0x00040000
263	#define GPIO_CFG_GPIOBUF1_ 0x00020000
264	#define GPIO_CFG_GPIOBUF0_ 0x00010000
265	#define GPIO_CFG_GPIODIR2_ 0x00000400
266	#define GPIO_CFG_GPIODIR1_ 0x00000200
267	#define GPIO_CFG_GPIODIR0_ 0x00000100
268	#define GPIO_CFG_GPIOD4_ 0x00000020
269	#define GPIO_CFG_GPIOD3_ 0x00000010
270	#define GPIO_CFG_GPIOD2_ 0x00000004
271	#define GPIO_CFG_GPIOD1_ 0x00000002
272	#define GPIO_CFG_GPIOD0_ 0x00000001
273
274	#define GPT_CFG 0x8C
275	#define GPT_CFG_TIMER_EN_ 0x20000000
276	#define GPT_CFG_GPT_LOAD_ 0x0000FFFF
277
278	#define GPT_CNT 0x90
279	#define GPT_CNT_GPT_CNT_ 0x0000FFFF
280
281	#define WORD_SWAP 0x98
282
283	#define FREE_RUN 0x9C
284
285	#define RX_DROP 0xA0
286
287	#define MAC_CSR_CMD 0xA4
288	#define MAC_CSR_CMD_CSR_BUSY_ 0x80000000
289	#define MAC_CSR_CMD_R_NOT_W_ 0x40000000
290	#define MAC_CSR_CMD_CSR_ADDR_ 0x000000FF
291
292	#define MAC_CSR_DATA 0xA8
293
294	#define AFC_CFG 0xAC
295	#define AFC_CFG_AFC_HI_ 0x00FF0000
296	#define AFC_CFG_AFC_LO_ 0x0000FF00
297	#define AFC_CFG_BACK_DUR_ 0x000000F0
298	#define AFC_CFG_FCMULT_ 0x00000008
299	#define AFC_CFG_FCBRD_ 0x00000004
300	#define AFC_CFG_FCADD_ 0x00000002
301	#define AFC_CFG_FCANY_ 0x00000001
302
303	#define E2P_CMD 0xB0
304	#define E2P_CMD_EPC_BUSY_ 0x80000000
305	#define E2P_CMD_EPC_CMD_ 0x70000000
306	#define E2P_CMD_EPC_CMD_READ_ 0x00000000
307	#define E2P_CMD_EPC_CMD_EWDS_ 0x10000000
308	#define E2P_CMD_EPC_CMD_EWEN_ 0x20000000
309	#define E2P_CMD_EPC_CMD_WRITE_ 0x30000000
310	#define E2P_CMD_EPC_CMD_WRAL_ 0x40000000
311	#define E2P_CMD_EPC_CMD_ERASE_ 0x50000000
312	#define E2P_CMD_EPC_CMD_ERAL_ 0x60000000
313	#define E2P_CMD_EPC_CMD_RELOAD_ 0x70000000
314	#define E2P_CMD_EPC_TIMEOUT_ 0x00000200
315	#define E2P_CMD_MAC_ADDR_LOADED_ 0x00000100
316	#define E2P_CMD_EPC_ADDR_ 0x000000FF
317
318	#define E2P_DATA 0xB4
319	#define E2P_DATA_EEPROM_DATA_ 0x000000FF
320	#define LAN_REGISTER_EXTENT 0x00000100
321
f6fec61e DC	322	#define RESET_CTL 0x1F8
	323	#define RESET_CTL_DIGITAL_RST_ 0x00000001
	324
fd9abb3d SG	325	/*
	326	* MAC Control and Status Register (Indirect Address)
	327	* Offset (through the MAC_CSR CMD and DATA port)
	328	*/
	329	#define MAC_CR 0x01
	330	#define MAC_CR_RXALL_ 0x80000000
	331	#define MAC_CR_HBDIS_ 0x10000000
	332	#define MAC_CR_RCVOWN_ 0x00800000
	333	#define MAC_CR_LOOPBK_ 0x00200000
	334	#define MAC_CR_FDPX_ 0x00100000
	335	#define MAC_CR_MCPAS_ 0x00080000
	336	#define MAC_CR_PRMS_ 0x00040000
	337	#define MAC_CR_INVFILT_ 0x00020000
	338	#define MAC_CR_PASSBAD_ 0x00010000
	339	#define MAC_CR_HFILT_ 0x00008000
	340	#define MAC_CR_HPFILT_ 0x00002000
	341	#define MAC_CR_LCOLL_ 0x00001000
	342	#define MAC_CR_BCAST_ 0x00000800
	343	#define MAC_CR_DISRTY_ 0x00000400
	344	#define MAC_CR_PADSTR_ 0x00000100
	345	#define MAC_CR_BOLMT_MASK_ 0x000000C0
	346	#define MAC_CR_DFCHK_ 0x00000020
	347	#define MAC_CR_TXEN_ 0x00000008
	348	#define MAC_CR_RXEN_ 0x00000004
	349
	350	#define ADDRH 0x02
	351
	352	#define ADDRL 0x03
	353
	354	#define HASHH 0x04
	355
	356	#define HASHL 0x05
	357
	358	#define MII_ACC 0x06
	359	#define MII_ACC_PHY_ADDR_ 0x0000F800
	360	#define MII_ACC_MIIRINDA_ 0x000007C0
	361	#define MII_ACC_MII_WRITE_ 0x00000002
	362	#define MII_ACC_MII_BUSY_ 0x00000001
	363
	364	#define MII_DATA 0x07
	365
	366	#define FLOW 0x08
	367	#define FLOW_FCPT_ 0xFFFF0000
	368	#define FLOW_FCPASS_ 0x00000004
	369	#define FLOW_FCEN_ 0x00000002
	370	#define FLOW_FCBSY_ 0x00000001
	371
	372	#define VLAN1 0x09
	373
	374	#define VLAN2 0x0A
	375
	376	#define WUFF 0x0B
	377
	378	#define WUCSR 0x0C
	379	#define WUCSR_GUE_ 0x00000200
	380	#define WUCSR_WUFR_ 0x00000040
	381	#define WUCSR_MPR_ 0x00000020
	382	#define WUCSR_WAKE_EN_ 0x00000004
	383	#define WUCSR_MPEN_ 0x00000002
	384
	385	/*
	386	* Phy definitions (vendor-specific)
	387	*/
	388	#define LAN9118_PHY_ID 0x00C0001C
389
390	#define MII_INTSTS 0x1D
391
392	#define MII_INTMSK 0x1E
393	#define PHY_INTMSK_AN_RCV_ (1 << 1)
394	#define PHY_INTMSK_PDFAULT_ (1 << 2)
395	#define PHY_INTMSK_AN_ACK_ (1 << 3)
396	#define PHY_INTMSK_LNKDOWN_ (1 << 4)
397	#define PHY_INTMSK_RFAULT_ (1 << 5)
398	#define PHY_INTMSK_AN_COMP_ (1 << 6)
399	#define PHY_INTMSK_ENERGYON_ (1 << 7)
400	#define PHY_INTMSK_DEFAULT_ (PHY_INTMSK_ENERGYON_ \| \
401	PHY_INTMSK_AN_COMP_ \| \
402	PHY_INTMSK_RFAULT_ \| \
403	PHY_INTMSK_LNKDOWN_)
404
405	#define ADVERTISE_PAUSE_ALL (ADVERTISE_PAUSE_CAP \| \
406	ADVERTISE_PAUSE_ASYM)
407
408	#define LPA_PAUSE_ALL (LPA_PAUSE_CAP \| \
409	LPA_PAUSE_ASYM)
410
62747cd2 AT	411	/*
	412	* Provide hooks to let the arch add to the initialisation procedure
	413	* and to override the source of the MAC address.
	414	*/
	415	#define SMSC_INITIALIZE() do {} while (0)
	416	#define smsc_get_mac(dev) smsc911x_read_mac_address((dev))
	417
	418	#ifdef CONFIG_SMSC911X_ARCH_HOOKS
	419	#include <asm/smsc911x.h>
	420	#endif
	421
43c6759e	422	#include <linux/smscphy.h>
43c6759e	423
fd9abb3d	424	#endif /* __SMSC911X_H__ */