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fd9abb3d SG |
1 | /*************************************************************************** |
2 | * | |
3 | * Copyright (C) 2004-2008 SMSC | |
4 | * Copyright (C) 2005-2008 ARM | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
0ab75ae8 | 17 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
fd9abb3d SG |
18 | * |
19 | *************************************************************************** | |
20 | * Rewritten, heavily based on smsc911x simple driver by SMSC. | |
21 | * Partly uses io macros from smc91x.c by Nicolas Pitre | |
22 | * | |
23 | * Supported devices: | |
24 | * LAN9115, LAN9116, LAN9117, LAN9118 | |
25 | * LAN9215, LAN9216, LAN9217, LAN9218 | |
26 | * LAN9210, LAN9211 | |
27 | * LAN9220, LAN9221 | |
f6fec61e | 28 | * LAN89218,LAN9250 |
fd9abb3d SG |
29 | * |
30 | */ | |
31 | ||
dffc6b24 JP |
32 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
33 | ||
fd9abb3d | 34 | #include <linux/crc32.h> |
b6c23019 | 35 | #include <linux/clk.h> |
fd9abb3d SG |
36 | #include <linux/delay.h> |
37 | #include <linux/errno.h> | |
38 | #include <linux/etherdevice.h> | |
39 | #include <linux/ethtool.h> | |
40 | #include <linux/init.h> | |
a6b7a407 | 41 | #include <linux/interrupt.h> |
fd9abb3d SG |
42 | #include <linux/ioport.h> |
43 | #include <linux/kernel.h> | |
44 | #include <linux/module.h> | |
45 | #include <linux/netdevice.h> | |
46 | #include <linux/platform_device.h> | |
c7e963f6 | 47 | #include <linux/regulator/consumer.h> |
fd9abb3d | 48 | #include <linux/sched.h> |
fd9abb3d | 49 | #include <linux/timer.h> |
fd9abb3d SG |
50 | #include <linux/bug.h> |
51 | #include <linux/bitops.h> | |
52 | #include <linux/irq.h> | |
53 | #include <linux/io.h> | |
833cc67c | 54 | #include <linux/swab.h> |
fd9abb3d SG |
55 | #include <linux/phy.h> |
56 | #include <linux/smsc911x.h> | |
6cb87823 | 57 | #include <linux/device.h> |
79f88ee9 SG |
58 | #include <linux/of.h> |
59 | #include <linux/of_device.h> | |
60 | #include <linux/of_gpio.h> | |
61 | #include <linux/of_net.h> | |
0b50dc4f | 62 | #include <linux/acpi.h> |
3a611e26 | 63 | #include <linux/pm_runtime.h> |
0b50dc4f | 64 | #include <linux/property.h> |
dd0cb7db | 65 | #include <linux/gpio/consumer.h> |
3a611e26 | 66 | |
fd9abb3d SG |
67 | #include "smsc911x.h" |
68 | ||
69 | #define SMSC_CHIPNAME "smsc911x" | |
70 | #define SMSC_MDIONAME "smsc911x-mdio" | |
71 | #define SMSC_DRV_VERSION "2008-10-21" | |
72 | ||
73 | MODULE_LICENSE("GPL"); | |
74 | MODULE_VERSION(SMSC_DRV_VERSION); | |
62038e4a | 75 | MODULE_ALIAS("platform:smsc911x"); |
fd9abb3d SG |
76 | |
77 | #if USE_DEBUG > 0 | |
78 | static int debug = 16; | |
79 | #else | |
80 | static int debug = 3; | |
81 | #endif | |
82 | ||
83 | module_param(debug, int, 0); | |
84 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
85 | ||
c326de88 MP |
86 | struct smsc911x_data; |
87 | ||
88 | struct smsc911x_ops { | |
89 | u32 (*reg_read)(struct smsc911x_data *pdata, u32 reg); | |
90 | void (*reg_write)(struct smsc911x_data *pdata, u32 reg, u32 val); | |
91 | void (*rx_readfifo)(struct smsc911x_data *pdata, | |
92 | unsigned int *buf, unsigned int wordcount); | |
93 | void (*tx_writefifo)(struct smsc911x_data *pdata, | |
94 | unsigned int *buf, unsigned int wordcount); | |
95 | }; | |
96 | ||
c7e963f6 RM |
97 | #define SMSC911X_NUM_SUPPLIES 2 |
98 | ||
fd9abb3d SG |
99 | struct smsc911x_data { |
100 | void __iomem *ioaddr; | |
101 | ||
102 | unsigned int idrev; | |
103 | ||
104 | /* used to decide which workarounds apply */ | |
105 | unsigned int generation; | |
106 | ||
107 | /* device configuration (copied from platform_data during probe) */ | |
2107fb8b | 108 | struct smsc911x_platform_config config; |
fd9abb3d SG |
109 | |
110 | /* This needs to be acquired before calling any of below: | |
111 | * smsc911x_mac_read(), smsc911x_mac_write() | |
112 | */ | |
113 | spinlock_t mac_lock; | |
114 | ||
492c5d94 | 115 | /* spinlock to ensure register accesses are serialised */ |
fd9abb3d | 116 | spinlock_t dev_lock; |
fd9abb3d | 117 | |
fd9abb3d | 118 | struct mii_bus *mii_bus; |
fd9abb3d SG |
119 | unsigned int using_extphy; |
120 | int last_duplex; | |
121 | int last_carrier; | |
122 | ||
123 | u32 msg_enable; | |
124 | unsigned int gpio_setting; | |
125 | unsigned int gpio_orig_setting; | |
126 | struct net_device *dev; | |
127 | struct napi_struct napi; | |
128 | ||
129 | unsigned int software_irq_signal; | |
130 | ||
131 | #ifdef USE_PHY_WORK_AROUND | |
132 | #define MIN_PACKET_SIZE (64) | |
133 | char loopback_tx_pkt[MIN_PACKET_SIZE]; | |
134 | char loopback_rx_pkt[MIN_PACKET_SIZE]; | |
135 | unsigned int resetcount; | |
136 | #endif | |
137 | ||
138 | /* Members for Multicast filter workaround */ | |
139 | unsigned int multicast_update_pending; | |
140 | unsigned int set_bits_mask; | |
141 | unsigned int clear_bits_mask; | |
142 | unsigned int hashhi; | |
143 | unsigned int hashlo; | |
c326de88 MP |
144 | |
145 | /* register access functions */ | |
146 | const struct smsc911x_ops *ops; | |
c7e963f6 RM |
147 | |
148 | /* regulators */ | |
149 | struct regulator_bulk_data supplies[SMSC911X_NUM_SUPPLIES]; | |
b6c23019 | 150 | |
dd0cb7db LW |
151 | /* Reset GPIO */ |
152 | struct gpio_desc *reset_gpiod; | |
153 | ||
b6c23019 LJ |
154 | /* clock */ |
155 | struct clk *clk; | |
fd9abb3d SG |
156 | }; |
157 | ||
c326de88 MP |
158 | /* Easy access to information */ |
159 | #define __smsc_shift(pdata, reg) ((reg) << ((pdata)->config.shift)) | |
160 | ||
492c5d94 | 161 | static inline u32 __smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg) |
fd9abb3d | 162 | { |
2107fb8b SG |
163 | if (pdata->config.flags & SMSC911X_USE_32BIT) |
164 | return readl(pdata->ioaddr + reg); | |
165 | ||
492c5d94 CM |
166 | if (pdata->config.flags & SMSC911X_USE_16BIT) |
167 | return ((readw(pdata->ioaddr + reg) & 0xFFFF) | | |
2107fb8b | 168 | ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16)); |
fd9abb3d | 169 | |
2107fb8b | 170 | BUG(); |
702403af | 171 | return 0; |
fd9abb3d SG |
172 | } |
173 | ||
c326de88 MP |
174 | static inline u32 |
175 | __smsc911x_reg_read_shift(struct smsc911x_data *pdata, u32 reg) | |
176 | { | |
177 | if (pdata->config.flags & SMSC911X_USE_32BIT) | |
178 | return readl(pdata->ioaddr + __smsc_shift(pdata, reg)); | |
179 | ||
180 | if (pdata->config.flags & SMSC911X_USE_16BIT) | |
181 | return (readw(pdata->ioaddr + | |
182 | __smsc_shift(pdata, reg)) & 0xFFFF) | | |
183 | ((readw(pdata->ioaddr + | |
184 | __smsc_shift(pdata, reg + 2)) & 0xFFFF) << 16); | |
185 | ||
186 | BUG(); | |
187 | return 0; | |
188 | } | |
189 | ||
492c5d94 CM |
190 | static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg) |
191 | { | |
192 | u32 data; | |
193 | unsigned long flags; | |
194 | ||
195 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
c326de88 | 196 | data = pdata->ops->reg_read(pdata, reg); |
492c5d94 CM |
197 | spin_unlock_irqrestore(&pdata->dev_lock, flags); |
198 | ||
199 | return data; | |
200 | } | |
201 | ||
202 | static inline void __smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg, | |
203 | u32 val) | |
fd9abb3d | 204 | { |
2107fb8b SG |
205 | if (pdata->config.flags & SMSC911X_USE_32BIT) { |
206 | writel(val, pdata->ioaddr + reg); | |
207 | return; | |
208 | } | |
209 | ||
210 | if (pdata->config.flags & SMSC911X_USE_16BIT) { | |
2107fb8b SG |
211 | writew(val & 0xFFFF, pdata->ioaddr + reg); |
212 | writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2); | |
2107fb8b SG |
213 | return; |
214 | } | |
fd9abb3d | 215 | |
2107fb8b | 216 | BUG(); |
fd9abb3d SG |
217 | } |
218 | ||
c326de88 MP |
219 | static inline void |
220 | __smsc911x_reg_write_shift(struct smsc911x_data *pdata, u32 reg, u32 val) | |
221 | { | |
222 | if (pdata->config.flags & SMSC911X_USE_32BIT) { | |
223 | writel(val, pdata->ioaddr + __smsc_shift(pdata, reg)); | |
224 | return; | |
225 | } | |
226 | ||
227 | if (pdata->config.flags & SMSC911X_USE_16BIT) { | |
228 | writew(val & 0xFFFF, | |
229 | pdata->ioaddr + __smsc_shift(pdata, reg)); | |
230 | writew((val >> 16) & 0xFFFF, | |
231 | pdata->ioaddr + __smsc_shift(pdata, reg + 2)); | |
232 | return; | |
233 | } | |
234 | ||
235 | BUG(); | |
236 | } | |
237 | ||
492c5d94 CM |
238 | static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg, |
239 | u32 val) | |
240 | { | |
241 | unsigned long flags; | |
242 | ||
243 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
c326de88 | 244 | pdata->ops->reg_write(pdata, reg, val); |
492c5d94 CM |
245 | spin_unlock_irqrestore(&pdata->dev_lock, flags); |
246 | } | |
247 | ||
fd9abb3d SG |
248 | /* Writes a packet to the TX_DATA_FIFO */ |
249 | static inline void | |
250 | smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf, | |
251 | unsigned int wordcount) | |
252 | { | |
492c5d94 CM |
253 | unsigned long flags; |
254 | ||
255 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
256 | ||
833cc67c MD |
257 | if (pdata->config.flags & SMSC911X_SWAP_FIFO) { |
258 | while (wordcount--) | |
492c5d94 CM |
259 | __smsc911x_reg_write(pdata, TX_DATA_FIFO, |
260 | swab32(*buf++)); | |
261 | goto out; | |
833cc67c MD |
262 | } |
263 | ||
2107fb8b | 264 | if (pdata->config.flags & SMSC911X_USE_32BIT) { |
2925f6c0 | 265 | iowrite32_rep(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount); |
492c5d94 | 266 | goto out; |
2107fb8b SG |
267 | } |
268 | ||
269 | if (pdata->config.flags & SMSC911X_USE_16BIT) { | |
270 | while (wordcount--) | |
492c5d94 CM |
271 | __smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++); |
272 | goto out; | |
2107fb8b SG |
273 | } |
274 | ||
275 | BUG(); | |
492c5d94 CM |
276 | out: |
277 | spin_unlock_irqrestore(&pdata->dev_lock, flags); | |
fd9abb3d SG |
278 | } |
279 | ||
c326de88 MP |
280 | /* Writes a packet to the TX_DATA_FIFO - shifted version */ |
281 | static inline void | |
282 | smsc911x_tx_writefifo_shift(struct smsc911x_data *pdata, unsigned int *buf, | |
283 | unsigned int wordcount) | |
284 | { | |
285 | unsigned long flags; | |
286 | ||
287 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
288 | ||
289 | if (pdata->config.flags & SMSC911X_SWAP_FIFO) { | |
290 | while (wordcount--) | |
291 | __smsc911x_reg_write_shift(pdata, TX_DATA_FIFO, | |
292 | swab32(*buf++)); | |
293 | goto out; | |
294 | } | |
295 | ||
296 | if (pdata->config.flags & SMSC911X_USE_32BIT) { | |
2925f6c0 | 297 | iowrite32_rep(pdata->ioaddr + __smsc_shift(pdata, |
c326de88 MP |
298 | TX_DATA_FIFO), buf, wordcount); |
299 | goto out; | |
300 | } | |
301 | ||
302 | if (pdata->config.flags & SMSC911X_USE_16BIT) { | |
303 | while (wordcount--) | |
304 | __smsc911x_reg_write_shift(pdata, | |
305 | TX_DATA_FIFO, *buf++); | |
306 | goto out; | |
307 | } | |
308 | ||
309 | BUG(); | |
310 | out: | |
311 | spin_unlock_irqrestore(&pdata->dev_lock, flags); | |
312 | } | |
313 | ||
fd9abb3d SG |
314 | /* Reads a packet out of the RX_DATA_FIFO */ |
315 | static inline void | |
316 | smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf, | |
317 | unsigned int wordcount) | |
318 | { | |
492c5d94 CM |
319 | unsigned long flags; |
320 | ||
321 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
322 | ||
833cc67c MD |
323 | if (pdata->config.flags & SMSC911X_SWAP_FIFO) { |
324 | while (wordcount--) | |
492c5d94 CM |
325 | *buf++ = swab32(__smsc911x_reg_read(pdata, |
326 | RX_DATA_FIFO)); | |
327 | goto out; | |
833cc67c MD |
328 | } |
329 | ||
2107fb8b | 330 | if (pdata->config.flags & SMSC911X_USE_32BIT) { |
2925f6c0 | 331 | ioread32_rep(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount); |
492c5d94 | 332 | goto out; |
2107fb8b | 333 | } |
fd9abb3d | 334 | |
2107fb8b SG |
335 | if (pdata->config.flags & SMSC911X_USE_16BIT) { |
336 | while (wordcount--) | |
492c5d94 CM |
337 | *buf++ = __smsc911x_reg_read(pdata, RX_DATA_FIFO); |
338 | goto out; | |
2107fb8b SG |
339 | } |
340 | ||
341 | BUG(); | |
492c5d94 CM |
342 | out: |
343 | spin_unlock_irqrestore(&pdata->dev_lock, flags); | |
2107fb8b | 344 | } |
fd9abb3d | 345 | |
c326de88 MP |
346 | /* Reads a packet out of the RX_DATA_FIFO - shifted version */ |
347 | static inline void | |
348 | smsc911x_rx_readfifo_shift(struct smsc911x_data *pdata, unsigned int *buf, | |
349 | unsigned int wordcount) | |
350 | { | |
351 | unsigned long flags; | |
352 | ||
353 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
354 | ||
355 | if (pdata->config.flags & SMSC911X_SWAP_FIFO) { | |
356 | while (wordcount--) | |
357 | *buf++ = swab32(__smsc911x_reg_read_shift(pdata, | |
358 | RX_DATA_FIFO)); | |
359 | goto out; | |
360 | } | |
361 | ||
362 | if (pdata->config.flags & SMSC911X_USE_32BIT) { | |
2925f6c0 | 363 | ioread32_rep(pdata->ioaddr + __smsc_shift(pdata, |
c326de88 MP |
364 | RX_DATA_FIFO), buf, wordcount); |
365 | goto out; | |
366 | } | |
367 | ||
368 | if (pdata->config.flags & SMSC911X_USE_16BIT) { | |
369 | while (wordcount--) | |
370 | *buf++ = __smsc911x_reg_read_shift(pdata, | |
371 | RX_DATA_FIFO); | |
372 | goto out; | |
373 | } | |
374 | ||
375 | BUG(); | |
376 | out: | |
377 | spin_unlock_irqrestore(&pdata->dev_lock, flags); | |
378 | } | |
379 | ||
c7e963f6 | 380 | /* |
b6c23019 | 381 | * enable regulator and clock resources. |
c7e963f6 RM |
382 | */ |
383 | static int smsc911x_enable_resources(struct platform_device *pdev) | |
384 | { | |
385 | struct net_device *ndev = platform_get_drvdata(pdev); | |
386 | struct smsc911x_data *pdata = netdev_priv(ndev); | |
387 | int ret = 0; | |
388 | ||
389 | ret = regulator_bulk_enable(ARRAY_SIZE(pdata->supplies), | |
390 | pdata->supplies); | |
391 | if (ret) | |
392 | netdev_err(ndev, "failed to enable regulators %d\n", | |
393 | ret); | |
b6c23019 LJ |
394 | |
395 | if (!IS_ERR(pdata->clk)) { | |
396 | ret = clk_prepare_enable(pdata->clk); | |
397 | if (ret < 0) | |
398 | netdev_err(ndev, "failed to enable clock %d\n", ret); | |
399 | } | |
400 | ||
c7e963f6 RM |
401 | return ret; |
402 | } | |
403 | ||
404 | /* | |
405 | * disable resources, currently just regulators. | |
406 | */ | |
407 | static int smsc911x_disable_resources(struct platform_device *pdev) | |
408 | { | |
409 | struct net_device *ndev = platform_get_drvdata(pdev); | |
410 | struct smsc911x_data *pdata = netdev_priv(ndev); | |
411 | int ret = 0; | |
412 | ||
413 | ret = regulator_bulk_disable(ARRAY_SIZE(pdata->supplies), | |
414 | pdata->supplies); | |
b6c23019 LJ |
415 | |
416 | if (!IS_ERR(pdata->clk)) | |
417 | clk_disable_unprepare(pdata->clk); | |
418 | ||
c7e963f6 RM |
419 | return ret; |
420 | } | |
421 | ||
422 | /* | |
423 | * Request resources, currently just regulators. | |
424 | * | |
425 | * The SMSC911x has two power pins: vddvario and vdd33a, in designs where | |
426 | * these are not always-on we need to request regulators to be turned on | |
427 | * before we can try to access the device registers. | |
428 | */ | |
429 | static int smsc911x_request_resources(struct platform_device *pdev) | |
430 | { | |
431 | struct net_device *ndev = platform_get_drvdata(pdev); | |
432 | struct smsc911x_data *pdata = netdev_priv(ndev); | |
433 | int ret = 0; | |
434 | ||
435 | /* Request regulators */ | |
436 | pdata->supplies[0].supply = "vdd33a"; | |
437 | pdata->supplies[1].supply = "vddvario"; | |
438 | ret = regulator_bulk_get(&pdev->dev, | |
439 | ARRAY_SIZE(pdata->supplies), | |
440 | pdata->supplies); | |
ab4e4c07 LW |
441 | if (ret) { |
442 | /* | |
443 | * Retry on deferrals, else just report the error | |
444 | * and try to continue. | |
445 | */ | |
446 | if (ret == -EPROBE_DEFER) | |
447 | return ret; | |
c7e963f6 RM |
448 | netdev_err(ndev, "couldn't get regulators %d\n", |
449 | ret); | |
ab4e4c07 | 450 | } |
b6c23019 | 451 | |
dd0cb7db LW |
452 | /* Request optional RESET GPIO */ |
453 | pdata->reset_gpiod = devm_gpiod_get_optional(&pdev->dev, | |
454 | "reset", | |
455 | GPIOD_OUT_LOW); | |
456 | ||
b6c23019 LJ |
457 | /* Request clock */ |
458 | pdata->clk = clk_get(&pdev->dev, NULL); | |
459 | if (IS_ERR(pdata->clk)) | |
1e87af97 FE |
460 | dev_dbg(&pdev->dev, "couldn't get clock %li\n", |
461 | PTR_ERR(pdata->clk)); | |
b6c23019 | 462 | |
c7e963f6 RM |
463 | return ret; |
464 | } | |
465 | ||
466 | /* | |
467 | * Free resources, currently just regulators. | |
468 | * | |
469 | */ | |
470 | static void smsc911x_free_resources(struct platform_device *pdev) | |
471 | { | |
472 | struct net_device *ndev = platform_get_drvdata(pdev); | |
473 | struct smsc911x_data *pdata = netdev_priv(ndev); | |
474 | ||
475 | /* Free regulators */ | |
476 | regulator_bulk_free(ARRAY_SIZE(pdata->supplies), | |
477 | pdata->supplies); | |
b6c23019 LJ |
478 | |
479 | /* Free clock */ | |
480 | if (!IS_ERR(pdata->clk)) { | |
481 | clk_put(pdata->clk); | |
482 | pdata->clk = NULL; | |
483 | } | |
c7e963f6 RM |
484 | } |
485 | ||
fd9abb3d SG |
486 | /* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read |
487 | * and smsc911x_mac_write, so assumes mac_lock is held */ | |
488 | static int smsc911x_mac_complete(struct smsc911x_data *pdata) | |
489 | { | |
490 | int i; | |
491 | u32 val; | |
492 | ||
493 | SMSC_ASSERT_MAC_LOCK(pdata); | |
494 | ||
495 | for (i = 0; i < 40; i++) { | |
496 | val = smsc911x_reg_read(pdata, MAC_CSR_CMD); | |
497 | if (!(val & MAC_CSR_CMD_CSR_BUSY_)) | |
498 | return 0; | |
499 | } | |
dffc6b24 JP |
500 | SMSC_WARN(pdata, hw, "Timed out waiting for MAC not BUSY. " |
501 | "MAC_CSR_CMD: 0x%08X", val); | |
fd9abb3d SG |
502 | return -EIO; |
503 | } | |
504 | ||
505 | /* Fetches a MAC register value. Assumes mac_lock is acquired */ | |
506 | static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset) | |
507 | { | |
508 | unsigned int temp; | |
509 | ||
510 | SMSC_ASSERT_MAC_LOCK(pdata); | |
511 | ||
512 | temp = smsc911x_reg_read(pdata, MAC_CSR_CMD); | |
513 | if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) { | |
dffc6b24 | 514 | SMSC_WARN(pdata, hw, "MAC busy at entry"); |
fd9abb3d SG |
515 | return 0xFFFFFFFF; |
516 | } | |
517 | ||
518 | /* Send the MAC cmd */ | |
519 | smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) | | |
520 | MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_)); | |
521 | ||
522 | /* Workaround for hardware read-after-write restriction */ | |
523 | temp = smsc911x_reg_read(pdata, BYTE_TEST); | |
524 | ||
525 | /* Wait for the read to complete */ | |
526 | if (likely(smsc911x_mac_complete(pdata) == 0)) | |
527 | return smsc911x_reg_read(pdata, MAC_CSR_DATA); | |
528 | ||
dffc6b24 | 529 | SMSC_WARN(pdata, hw, "MAC busy after read"); |
fd9abb3d SG |
530 | return 0xFFFFFFFF; |
531 | } | |
532 | ||
533 | /* Set a mac register, mac_lock must be acquired before calling */ | |
534 | static void smsc911x_mac_write(struct smsc911x_data *pdata, | |
535 | unsigned int offset, u32 val) | |
536 | { | |
537 | unsigned int temp; | |
538 | ||
539 | SMSC_ASSERT_MAC_LOCK(pdata); | |
540 | ||
541 | temp = smsc911x_reg_read(pdata, MAC_CSR_CMD); | |
542 | if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) { | |
dffc6b24 JP |
543 | SMSC_WARN(pdata, hw, |
544 | "smsc911x_mac_write failed, MAC busy at entry"); | |
fd9abb3d SG |
545 | return; |
546 | } | |
547 | ||
548 | /* Send data to write */ | |
549 | smsc911x_reg_write(pdata, MAC_CSR_DATA, val); | |
550 | ||
551 | /* Write the actual data */ | |
552 | smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) | | |
553 | MAC_CSR_CMD_CSR_BUSY_)); | |
554 | ||
555 | /* Workaround for hardware read-after-write restriction */ | |
556 | temp = smsc911x_reg_read(pdata, BYTE_TEST); | |
557 | ||
558 | /* Wait for the write to complete */ | |
559 | if (likely(smsc911x_mac_complete(pdata) == 0)) | |
560 | return; | |
561 | ||
dffc6b24 | 562 | SMSC_WARN(pdata, hw, "smsc911x_mac_write failed, MAC busy after write"); |
fd9abb3d SG |
563 | } |
564 | ||
565 | /* Get a phy register */ | |
566 | static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx) | |
567 | { | |
568 | struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv; | |
569 | unsigned long flags; | |
570 | unsigned int addr; | |
571 | int i, reg; | |
572 | ||
573 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
574 | ||
575 | /* Confirm MII not busy */ | |
576 | if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) { | |
dffc6b24 | 577 | SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_read???"); |
fd9abb3d SG |
578 | reg = -EIO; |
579 | goto out; | |
580 | } | |
581 | ||
582 | /* Set the address, index & direction (read from PHY) */ | |
583 | addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6); | |
584 | smsc911x_mac_write(pdata, MII_ACC, addr); | |
585 | ||
586 | /* Wait for read to complete w/ timeout */ | |
587 | for (i = 0; i < 100; i++) | |
588 | if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) { | |
589 | reg = smsc911x_mac_read(pdata, MII_DATA); | |
590 | goto out; | |
591 | } | |
592 | ||
dffc6b24 | 593 | SMSC_WARN(pdata, hw, "Timed out waiting for MII read to finish"); |
fd9abb3d SG |
594 | reg = -EIO; |
595 | ||
596 | out: | |
597 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
598 | return reg; | |
599 | } | |
600 | ||
601 | /* Set a phy register */ | |
602 | static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx, | |
603 | u16 val) | |
604 | { | |
605 | struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv; | |
606 | unsigned long flags; | |
607 | unsigned int addr; | |
608 | int i, reg; | |
609 | ||
610 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
611 | ||
612 | /* Confirm MII not busy */ | |
613 | if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) { | |
dffc6b24 | 614 | SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_write???"); |
fd9abb3d SG |
615 | reg = -EIO; |
616 | goto out; | |
617 | } | |
618 | ||
619 | /* Put the data to write in the MAC */ | |
620 | smsc911x_mac_write(pdata, MII_DATA, val); | |
621 | ||
622 | /* Set the address, index & direction (write to PHY) */ | |
623 | addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) | | |
624 | MII_ACC_MII_WRITE_; | |
625 | smsc911x_mac_write(pdata, MII_ACC, addr); | |
626 | ||
627 | /* Wait for write to complete w/ timeout */ | |
628 | for (i = 0; i < 100; i++) | |
629 | if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) { | |
630 | reg = 0; | |
631 | goto out; | |
632 | } | |
633 | ||
dffc6b24 | 634 | SMSC_WARN(pdata, hw, "Timed out waiting for MII write to finish"); |
fd9abb3d SG |
635 | reg = -EIO; |
636 | ||
637 | out: | |
638 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
639 | return reg; | |
640 | } | |
641 | ||
d23f028a SG |
642 | /* Switch to external phy. Assumes tx and rx are stopped. */ |
643 | static void smsc911x_phy_enable_external(struct smsc911x_data *pdata) | |
fd9abb3d SG |
644 | { |
645 | unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG); | |
646 | ||
d23f028a SG |
647 | /* Disable phy clocks to the MAC */ |
648 | hwcfg &= (~HW_CFG_PHY_CLK_SEL_); | |
649 | hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_; | |
650 | smsc911x_reg_write(pdata, HW_CFG, hwcfg); | |
651 | udelay(10); /* Enough time for clocks to stop */ | |
fd9abb3d | 652 | |
d23f028a SG |
653 | /* Switch to external phy */ |
654 | hwcfg |= HW_CFG_EXT_PHY_EN_; | |
655 | smsc911x_reg_write(pdata, HW_CFG, hwcfg); | |
fd9abb3d | 656 | |
d23f028a SG |
657 | /* Enable phy clocks to the MAC */ |
658 | hwcfg &= (~HW_CFG_PHY_CLK_SEL_); | |
659 | hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_; | |
660 | smsc911x_reg_write(pdata, HW_CFG, hwcfg); | |
661 | udelay(10); /* Enough time for clocks to restart */ | |
fd9abb3d | 662 | |
d23f028a SG |
663 | hwcfg |= HW_CFG_SMI_SEL_; |
664 | smsc911x_reg_write(pdata, HW_CFG, hwcfg); | |
665 | } | |
fd9abb3d | 666 | |
d23f028a SG |
667 | /* Autodetects and enables external phy if present on supported chips. |
668 | * autodetection can be overridden by specifying SMSC911X_FORCE_INTERNAL_PHY | |
669 | * or SMSC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */ | |
670 | static void smsc911x_phy_initialise_external(struct smsc911x_data *pdata) | |
671 | { | |
672 | unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG); | |
fd9abb3d | 673 | |
d23f028a | 674 | if (pdata->config.flags & SMSC911X_FORCE_INTERNAL_PHY) { |
dffc6b24 | 675 | SMSC_TRACE(pdata, hw, "Forcing internal PHY"); |
d23f028a SG |
676 | pdata->using_extphy = 0; |
677 | } else if (pdata->config.flags & SMSC911X_FORCE_EXTERNAL_PHY) { | |
dffc6b24 | 678 | SMSC_TRACE(pdata, hw, "Forcing external PHY"); |
d23f028a SG |
679 | smsc911x_phy_enable_external(pdata); |
680 | pdata->using_extphy = 1; | |
681 | } else if (hwcfg & HW_CFG_EXT_PHY_DET_) { | |
dffc6b24 JP |
682 | SMSC_TRACE(pdata, hw, |
683 | "HW_CFG EXT_PHY_DET set, using external PHY"); | |
d23f028a | 684 | smsc911x_phy_enable_external(pdata); |
fd9abb3d SG |
685 | pdata->using_extphy = 1; |
686 | } else { | |
dffc6b24 JP |
687 | SMSC_TRACE(pdata, hw, |
688 | "HW_CFG EXT_PHY_DET clear, using internal PHY"); | |
d23f028a | 689 | pdata->using_extphy = 0; |
fd9abb3d | 690 | } |
fd9abb3d SG |
691 | } |
692 | ||
693 | /* Fetches a tx status out of the status fifo */ | |
694 | static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata) | |
695 | { | |
696 | unsigned int result = | |
697 | smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_; | |
698 | ||
699 | if (result != 0) | |
700 | result = smsc911x_reg_read(pdata, TX_STATUS_FIFO); | |
701 | ||
702 | return result; | |
703 | } | |
704 | ||
705 | /* Fetches the next rx status */ | |
706 | static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata) | |
707 | { | |
708 | unsigned int result = | |
709 | smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_; | |
710 | ||
711 | if (result != 0) | |
712 | result = smsc911x_reg_read(pdata, RX_STATUS_FIFO); | |
713 | ||
714 | return result; | |
715 | } | |
716 | ||
717 | #ifdef USE_PHY_WORK_AROUND | |
718 | static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata) | |
719 | { | |
720 | unsigned int tries; | |
721 | u32 wrsz; | |
722 | u32 rdsz; | |
723 | ulong bufp; | |
724 | ||
725 | for (tries = 0; tries < 10; tries++) { | |
726 | unsigned int txcmd_a; | |
727 | unsigned int txcmd_b; | |
728 | unsigned int status; | |
729 | unsigned int pktlength; | |
730 | unsigned int i; | |
731 | ||
732 | /* Zero-out rx packet memory */ | |
733 | memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE); | |
734 | ||
735 | /* Write tx packet to 118 */ | |
736 | txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16; | |
737 | txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_; | |
738 | txcmd_a |= MIN_PACKET_SIZE; | |
739 | ||
740 | txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE; | |
741 | ||
742 | smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a); | |
743 | smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b); | |
744 | ||
745 | bufp = (ulong)pdata->loopback_tx_pkt & (~0x3); | |
746 | wrsz = MIN_PACKET_SIZE + 3; | |
747 | wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3); | |
748 | wrsz >>= 2; | |
749 | ||
c326de88 | 750 | pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz); |
fd9abb3d SG |
751 | |
752 | /* Wait till transmit is done */ | |
753 | i = 60; | |
754 | do { | |
755 | udelay(5); | |
756 | status = smsc911x_tx_get_txstatus(pdata); | |
757 | } while ((i--) && (!status)); | |
758 | ||
759 | if (!status) { | |
dffc6b24 JP |
760 | SMSC_WARN(pdata, hw, |
761 | "Failed to transmit during loopback test"); | |
fd9abb3d SG |
762 | continue; |
763 | } | |
764 | if (status & TX_STS_ES_) { | |
dffc6b24 JP |
765 | SMSC_WARN(pdata, hw, |
766 | "Transmit encountered errors during loopback test"); | |
fd9abb3d SG |
767 | continue; |
768 | } | |
769 | ||
770 | /* Wait till receive is done */ | |
771 | i = 60; | |
772 | do { | |
773 | udelay(5); | |
774 | status = smsc911x_rx_get_rxstatus(pdata); | |
775 | } while ((i--) && (!status)); | |
776 | ||
777 | if (!status) { | |
dffc6b24 JP |
778 | SMSC_WARN(pdata, hw, |
779 | "Failed to receive during loopback test"); | |
fd9abb3d SG |
780 | continue; |
781 | } | |
782 | if (status & RX_STS_ES_) { | |
dffc6b24 JP |
783 | SMSC_WARN(pdata, hw, |
784 | "Receive encountered errors during loopback test"); | |
fd9abb3d SG |
785 | continue; |
786 | } | |
787 | ||
788 | pktlength = ((status & 0x3FFF0000UL) >> 16); | |
789 | bufp = (ulong)pdata->loopback_rx_pkt; | |
790 | rdsz = pktlength + 3; | |
791 | rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3); | |
792 | rdsz >>= 2; | |
793 | ||
c326de88 | 794 | pdata->ops->rx_readfifo(pdata, (unsigned int *)bufp, rdsz); |
fd9abb3d SG |
795 | |
796 | if (pktlength != (MIN_PACKET_SIZE + 4)) { | |
dffc6b24 JP |
797 | SMSC_WARN(pdata, hw, "Unexpected packet size " |
798 | "during loop back test, size=%d, will retry", | |
799 | pktlength); | |
fd9abb3d SG |
800 | } else { |
801 | unsigned int j; | |
802 | int mismatch = 0; | |
803 | for (j = 0; j < MIN_PACKET_SIZE; j++) { | |
804 | if (pdata->loopback_tx_pkt[j] | |
805 | != pdata->loopback_rx_pkt[j]) { | |
806 | mismatch = 1; | |
807 | break; | |
808 | } | |
809 | } | |
810 | if (!mismatch) { | |
dffc6b24 | 811 | SMSC_TRACE(pdata, hw, "Successfully verified " |
fd9abb3d SG |
812 | "loopback packet"); |
813 | return 0; | |
814 | } else { | |
dffc6b24 JP |
815 | SMSC_WARN(pdata, hw, "Data mismatch " |
816 | "during loop back test, will retry"); | |
fd9abb3d SG |
817 | } |
818 | } | |
819 | } | |
820 | ||
821 | return -EIO; | |
822 | } | |
823 | ||
824 | static int smsc911x_phy_reset(struct smsc911x_data *pdata) | |
825 | { | |
fd9abb3d SG |
826 | unsigned int temp; |
827 | unsigned int i = 100000; | |
828 | ||
cd998ecd PF |
829 | temp = smsc911x_reg_read(pdata, PMT_CTRL); |
830 | smsc911x_reg_write(pdata, PMT_CTRL, temp | PMT_CTRL_PHY_RST_); | |
fd9abb3d SG |
831 | do { |
832 | msleep(1); | |
cd998ecd PF |
833 | temp = smsc911x_reg_read(pdata, PMT_CTRL); |
834 | } while ((i--) && (temp & PMT_CTRL_PHY_RST_)); | |
fd9abb3d | 835 | |
cd998ecd | 836 | if (unlikely(temp & PMT_CTRL_PHY_RST_)) { |
dffc6b24 | 837 | SMSC_WARN(pdata, hw, "PHY reset failed to complete"); |
fd9abb3d SG |
838 | return -EIO; |
839 | } | |
840 | /* Extra delay required because the phy may not be completed with | |
841 | * its reset when BMCR_RESET is cleared. Specs say 256 uS is | |
842 | * enough delay but using 1ms here to be safe */ | |
843 | msleep(1); | |
844 | ||
845 | return 0; | |
846 | } | |
847 | ||
848 | static int smsc911x_phy_loopbacktest(struct net_device *dev) | |
849 | { | |
850 | struct smsc911x_data *pdata = netdev_priv(dev); | |
f788e322 | 851 | struct phy_device *phy_dev = dev->phydev; |
fd9abb3d SG |
852 | int result = -EIO; |
853 | unsigned int i, val; | |
854 | unsigned long flags; | |
855 | ||
856 | /* Initialise tx packet using broadcast destination address */ | |
c7bf7169 | 857 | eth_broadcast_addr(pdata->loopback_tx_pkt); |
fd9abb3d SG |
858 | |
859 | /* Use incrementing source address */ | |
860 | for (i = 6; i < 12; i++) | |
861 | pdata->loopback_tx_pkt[i] = (char)i; | |
862 | ||
863 | /* Set length type field */ | |
864 | pdata->loopback_tx_pkt[12] = 0x00; | |
865 | pdata->loopback_tx_pkt[13] = 0x00; | |
866 | ||
867 | for (i = 14; i < MIN_PACKET_SIZE; i++) | |
868 | pdata->loopback_tx_pkt[i] = (char)i; | |
869 | ||
870 | val = smsc911x_reg_read(pdata, HW_CFG); | |
871 | val &= HW_CFG_TX_FIF_SZ_; | |
872 | val |= HW_CFG_SF_; | |
873 | smsc911x_reg_write(pdata, HW_CFG, val); | |
874 | ||
875 | smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_); | |
876 | smsc911x_reg_write(pdata, RX_CFG, | |
877 | (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8); | |
878 | ||
879 | for (i = 0; i < 10; i++) { | |
880 | /* Set PHY to 10/FD, no ANEG, and loopback mode */ | |
e5a03bfd AL |
881 | smsc911x_mii_write(phy_dev->mdio.bus, phy_dev->mdio.addr, |
882 | MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX); | |
fd9abb3d SG |
883 | |
884 | /* Enable MAC tx/rx, FD */ | |
885 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
886 | smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_ | |
887 | | MAC_CR_TXEN_ | MAC_CR_RXEN_); | |
888 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
889 | ||
890 | if (smsc911x_phy_check_loopbackpkt(pdata) == 0) { | |
891 | result = 0; | |
892 | break; | |
893 | } | |
894 | pdata->resetcount++; | |
895 | ||
896 | /* Disable MAC rx */ | |
897 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
898 | smsc911x_mac_write(pdata, MAC_CR, 0); | |
899 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
900 | ||
901 | smsc911x_phy_reset(pdata); | |
902 | } | |
903 | ||
904 | /* Disable MAC */ | |
905 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
906 | smsc911x_mac_write(pdata, MAC_CR, 0); | |
907 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
908 | ||
909 | /* Cancel PHY loopback mode */ | |
e5a03bfd | 910 | smsc911x_mii_write(phy_dev->mdio.bus, phy_dev->mdio.addr, MII_BMCR, 0); |
fd9abb3d SG |
911 | |
912 | smsc911x_reg_write(pdata, TX_CFG, 0); | |
913 | smsc911x_reg_write(pdata, RX_CFG, 0); | |
914 | ||
915 | return result; | |
916 | } | |
917 | #endif /* USE_PHY_WORK_AROUND */ | |
918 | ||
fd9abb3d SG |
919 | static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata) |
920 | { | |
f788e322 PR |
921 | struct net_device *ndev = pdata->dev; |
922 | struct phy_device *phy_dev = ndev->phydev; | |
fd9abb3d SG |
923 | u32 afc = smsc911x_reg_read(pdata, AFC_CFG); |
924 | u32 flow; | |
925 | unsigned long flags; | |
926 | ||
927 | if (phy_dev->duplex == DUPLEX_FULL) { | |
928 | u16 lcladv = phy_read(phy_dev, MII_ADVERTISE); | |
929 | u16 rmtadv = phy_read(phy_dev, MII_LPA); | |
bc02ff95 | 930 | u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); |
fd9abb3d SG |
931 | |
932 | if (cap & FLOW_CTRL_RX) | |
933 | flow = 0xFFFF0002; | |
934 | else | |
935 | flow = 0; | |
936 | ||
937 | if (cap & FLOW_CTRL_TX) | |
938 | afc |= 0xF; | |
939 | else | |
940 | afc &= ~0xF; | |
941 | ||
dffc6b24 JP |
942 | SMSC_TRACE(pdata, hw, "rx pause %s, tx pause %s", |
943 | (cap & FLOW_CTRL_RX ? "enabled" : "disabled"), | |
944 | (cap & FLOW_CTRL_TX ? "enabled" : "disabled")); | |
fd9abb3d | 945 | } else { |
dffc6b24 | 946 | SMSC_TRACE(pdata, hw, "half duplex"); |
fd9abb3d SG |
947 | flow = 0; |
948 | afc |= 0xF; | |
949 | } | |
950 | ||
951 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
952 | smsc911x_mac_write(pdata, FLOW, flow); | |
953 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
954 | ||
955 | smsc911x_reg_write(pdata, AFC_CFG, afc); | |
956 | } | |
957 | ||
958 | /* Update link mode if anything has changed. Called periodically when the | |
959 | * PHY is in polling mode, even if nothing has changed. */ | |
960 | static void smsc911x_phy_adjust_link(struct net_device *dev) | |
961 | { | |
962 | struct smsc911x_data *pdata = netdev_priv(dev); | |
f788e322 | 963 | struct phy_device *phy_dev = dev->phydev; |
fd9abb3d SG |
964 | unsigned long flags; |
965 | int carrier; | |
966 | ||
967 | if (phy_dev->duplex != pdata->last_duplex) { | |
968 | unsigned int mac_cr; | |
dffc6b24 | 969 | SMSC_TRACE(pdata, hw, "duplex state has changed"); |
fd9abb3d SG |
970 | |
971 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
972 | mac_cr = smsc911x_mac_read(pdata, MAC_CR); | |
973 | if (phy_dev->duplex) { | |
dffc6b24 JP |
974 | SMSC_TRACE(pdata, hw, |
975 | "configuring for full duplex mode"); | |
fd9abb3d SG |
976 | mac_cr |= MAC_CR_FDPX_; |
977 | } else { | |
dffc6b24 JP |
978 | SMSC_TRACE(pdata, hw, |
979 | "configuring for half duplex mode"); | |
fd9abb3d SG |
980 | mac_cr &= ~MAC_CR_FDPX_; |
981 | } | |
982 | smsc911x_mac_write(pdata, MAC_CR, mac_cr); | |
983 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
984 | ||
985 | smsc911x_phy_update_flowcontrol(pdata); | |
986 | pdata->last_duplex = phy_dev->duplex; | |
987 | } | |
988 | ||
989 | carrier = netif_carrier_ok(dev); | |
990 | if (carrier != pdata->last_carrier) { | |
dffc6b24 | 991 | SMSC_TRACE(pdata, hw, "carrier state has changed"); |
fd9abb3d | 992 | if (carrier) { |
dffc6b24 | 993 | SMSC_TRACE(pdata, hw, "configuring for carrier OK"); |
fd9abb3d SG |
994 | if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) && |
995 | (!pdata->using_extphy)) { | |
88393161 | 996 | /* Restore original GPIO configuration */ |
fd9abb3d SG |
997 | pdata->gpio_setting = pdata->gpio_orig_setting; |
998 | smsc911x_reg_write(pdata, GPIO_CFG, | |
999 | pdata->gpio_setting); | |
1000 | } | |
1001 | } else { | |
dffc6b24 | 1002 | SMSC_TRACE(pdata, hw, "configuring for no carrier"); |
fd9abb3d SG |
1003 | /* Check global setting that LED1 |
1004 | * usage is 10/100 indicator */ | |
1005 | pdata->gpio_setting = smsc911x_reg_read(pdata, | |
1006 | GPIO_CFG); | |
8e95a202 JP |
1007 | if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_) && |
1008 | (!pdata->using_extphy)) { | |
fd9abb3d | 1009 | /* Force 10/100 LED off, after saving |
88393161 | 1010 | * original GPIO configuration */ |
fd9abb3d SG |
1011 | pdata->gpio_orig_setting = pdata->gpio_setting; |
1012 | ||
1013 | pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_; | |
1014 | pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_ | |
1015 | | GPIO_CFG_GPIODIR0_ | |
1016 | | GPIO_CFG_GPIOD0_); | |
1017 | smsc911x_reg_write(pdata, GPIO_CFG, | |
1018 | pdata->gpio_setting); | |
1019 | } | |
1020 | } | |
1021 | pdata->last_carrier = carrier; | |
1022 | } | |
1023 | } | |
1024 | ||
1025 | static int smsc911x_mii_probe(struct net_device *dev) | |
1026 | { | |
1027 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1028 | struct phy_device *phydev = NULL; | |
e4a474f8 | 1029 | int ret; |
fd9abb3d SG |
1030 | |
1031 | /* find the first phy */ | |
e4a474f8 | 1032 | phydev = phy_find_first(pdata->mii_bus); |
fd9abb3d | 1033 | if (!phydev) { |
dffc6b24 | 1034 | netdev_err(dev, "no PHY found\n"); |
fd9abb3d SG |
1035 | return -ENODEV; |
1036 | } | |
1037 | ||
dffc6b24 | 1038 | SMSC_TRACE(pdata, probe, "PHY: addr %d, phy_id 0x%08X", |
e5a03bfd | 1039 | phydev->mdio.addr, phydev->phy_id); |
e4a474f8 | 1040 | |
f9a8f83b FF |
1041 | ret = phy_connect_direct(dev, phydev, &smsc911x_phy_adjust_link, |
1042 | pdata->config.phy_interface); | |
fd9abb3d | 1043 | |
e4a474f8 | 1044 | if (ret) { |
dffc6b24 | 1045 | netdev_err(dev, "Could not attach to PHY\n"); |
e4a474f8 | 1046 | return ret; |
fd9abb3d SG |
1047 | } |
1048 | ||
2220943a | 1049 | phy_attached_info(phydev); |
fd9abb3d | 1050 | |
58056c1e AL |
1051 | phy_set_max_speed(phydev, SPEED_100); |
1052 | ||
fd9abb3d | 1053 | /* mask with MAC supported features */ |
af8d9bb2 | 1054 | phy_support_asym_pause(phydev); |
fd9abb3d | 1055 | |
fd9abb3d SG |
1056 | pdata->last_duplex = -1; |
1057 | pdata->last_carrier = -1; | |
1058 | ||
1059 | #ifdef USE_PHY_WORK_AROUND | |
1060 | if (smsc911x_phy_loopbacktest(dev) < 0) { | |
dffc6b24 | 1061 | SMSC_WARN(pdata, hw, "Failed Loop Back Test"); |
b43c142f | 1062 | phy_disconnect(phydev); |
fd9abb3d SG |
1063 | return -ENODEV; |
1064 | } | |
dffc6b24 | 1065 | SMSC_TRACE(pdata, hw, "Passed Loop Back Test"); |
fd9abb3d SG |
1066 | #endif /* USE_PHY_WORK_AROUND */ |
1067 | ||
dffc6b24 | 1068 | SMSC_TRACE(pdata, hw, "phy initialised successfully"); |
fd9abb3d SG |
1069 | return 0; |
1070 | } | |
1071 | ||
8489ec1f | 1072 | static int smsc911x_mii_init(struct platform_device *pdev, |
1dd06ae8 | 1073 | struct net_device *dev) |
fd9abb3d SG |
1074 | { |
1075 | struct smsc911x_data *pdata = netdev_priv(dev); | |
e7f4dc35 | 1076 | int err = -ENXIO; |
fd9abb3d SG |
1077 | |
1078 | pdata->mii_bus = mdiobus_alloc(); | |
1079 | if (!pdata->mii_bus) { | |
1080 | err = -ENOMEM; | |
1081 | goto err_out_1; | |
1082 | } | |
1083 | ||
1084 | pdata->mii_bus->name = SMSC_MDIONAME; | |
09ef0789 FF |
1085 | snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
1086 | pdev->name, pdev->id); | |
fd9abb3d SG |
1087 | pdata->mii_bus->priv = pdata; |
1088 | pdata->mii_bus->read = smsc911x_mii_read; | |
1089 | pdata->mii_bus->write = smsc911x_mii_write; | |
fd9abb3d SG |
1090 | |
1091 | pdata->mii_bus->parent = &pdev->dev; | |
fd9abb3d | 1092 | |
fd9abb3d SG |
1093 | switch (pdata->idrev & 0xFFFF0000) { |
1094 | case 0x01170000: | |
1095 | case 0x01150000: | |
1096 | case 0x117A0000: | |
1097 | case 0x115A0000: | |
1098 | /* External PHY supported, try to autodetect */ | |
d23f028a | 1099 | smsc911x_phy_initialise_external(pdata); |
fd9abb3d SG |
1100 | break; |
1101 | default: | |
dffc6b24 JP |
1102 | SMSC_TRACE(pdata, hw, "External PHY is not supported, " |
1103 | "using internal PHY"); | |
d23f028a | 1104 | pdata->using_extphy = 0; |
fd9abb3d SG |
1105 | break; |
1106 | } | |
1107 | ||
1108 | if (!pdata->using_extphy) { | |
1109 | /* Mask all PHYs except ID 1 (internal) */ | |
1110 | pdata->mii_bus->phy_mask = ~(1 << 1); | |
1111 | } | |
1112 | ||
1113 | if (mdiobus_register(pdata->mii_bus)) { | |
dffc6b24 | 1114 | SMSC_WARN(pdata, probe, "Error registering mii bus"); |
fd9abb3d SG |
1115 | goto err_out_free_bus_2; |
1116 | } | |
1117 | ||
fd9abb3d SG |
1118 | return 0; |
1119 | ||
fd9abb3d SG |
1120 | err_out_free_bus_2: |
1121 | mdiobus_free(pdata->mii_bus); | |
1122 | err_out_1: | |
1123 | return err; | |
1124 | } | |
1125 | ||
1126 | /* Gets the number of tx statuses in the fifo */ | |
1127 | static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata) | |
1128 | { | |
1129 | return (smsc911x_reg_read(pdata, TX_FIFO_INF) | |
1130 | & TX_FIFO_INF_TSUSED_) >> 16; | |
1131 | } | |
1132 | ||
1133 | /* Reads tx statuses and increments counters where necessary */ | |
1134 | static void smsc911x_tx_update_txcounters(struct net_device *dev) | |
1135 | { | |
1136 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1137 | unsigned int tx_stat; | |
1138 | ||
1139 | while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) { | |
1140 | if (unlikely(tx_stat & 0x80000000)) { | |
1141 | /* In this driver the packet tag is used as the packet | |
1142 | * length. Since a packet length can never reach the | |
1143 | * size of 0x8000, this bit is reserved. It is worth | |
1144 | * noting that the "reserved bit" in the warning above | |
1145 | * does not reference a hardware defined reserved bit | |
1146 | * but rather a driver defined one. | |
1147 | */ | |
dffc6b24 | 1148 | SMSC_WARN(pdata, hw, "Packet tag reserved bit is high"); |
fd9abb3d | 1149 | } else { |
785b6f97 | 1150 | if (unlikely(tx_stat & TX_STS_ES_)) { |
fd9abb3d SG |
1151 | dev->stats.tx_errors++; |
1152 | } else { | |
1153 | dev->stats.tx_packets++; | |
1154 | dev->stats.tx_bytes += (tx_stat >> 16); | |
1155 | } | |
785b6f97 | 1156 | if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) { |
fd9abb3d SG |
1157 | dev->stats.collisions += 16; |
1158 | dev->stats.tx_aborted_errors += 1; | |
1159 | } else { | |
1160 | dev->stats.collisions += | |
1161 | ((tx_stat >> 3) & 0xF); | |
1162 | } | |
785b6f97 | 1163 | if (unlikely(tx_stat & TX_STS_LOST_CARRIER_)) |
fd9abb3d | 1164 | dev->stats.tx_carrier_errors += 1; |
785b6f97 | 1165 | if (unlikely(tx_stat & TX_STS_LATE_COL_)) { |
fd9abb3d SG |
1166 | dev->stats.collisions++; |
1167 | dev->stats.tx_aborted_errors++; | |
1168 | } | |
1169 | } | |
1170 | } | |
1171 | } | |
1172 | ||
1173 | /* Increments the Rx error counters */ | |
1174 | static void | |
1175 | smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat) | |
1176 | { | |
1177 | int crc_err = 0; | |
1178 | ||
785b6f97 | 1179 | if (unlikely(rxstat & RX_STS_ES_)) { |
fd9abb3d | 1180 | dev->stats.rx_errors++; |
785b6f97 | 1181 | if (unlikely(rxstat & RX_STS_CRC_ERR_)) { |
fd9abb3d SG |
1182 | dev->stats.rx_crc_errors++; |
1183 | crc_err = 1; | |
1184 | } | |
1185 | } | |
1186 | if (likely(!crc_err)) { | |
785b6f97 SG |
1187 | if (unlikely((rxstat & RX_STS_FRAME_TYPE_) && |
1188 | (rxstat & RX_STS_LENGTH_ERR_))) | |
fd9abb3d | 1189 | dev->stats.rx_length_errors++; |
fd9abb3d SG |
1190 | if (rxstat & RX_STS_MCAST_) |
1191 | dev->stats.multicast++; | |
1192 | } | |
1193 | } | |
1194 | ||
1195 | /* Quickly dumps bad packets */ | |
1196 | static void | |
3c5e979b | 1197 | smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktwords) |
fd9abb3d | 1198 | { |
fd9abb3d SG |
1199 | if (likely(pktwords >= 4)) { |
1200 | unsigned int timeout = 500; | |
1201 | unsigned int val; | |
1202 | smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_); | |
1203 | do { | |
1204 | udelay(1); | |
1205 | val = smsc911x_reg_read(pdata, RX_DP_CTRL); | |
8dacd548 | 1206 | } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout); |
fd9abb3d SG |
1207 | |
1208 | if (unlikely(timeout == 0)) | |
dffc6b24 JP |
1209 | SMSC_WARN(pdata, hw, "Timed out waiting for " |
1210 | "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val); | |
fd9abb3d SG |
1211 | } else { |
1212 | unsigned int temp; | |
1213 | while (pktwords--) | |
1214 | temp = smsc911x_reg_read(pdata, RX_DATA_FIFO); | |
1215 | } | |
1216 | } | |
1217 | ||
1218 | /* NAPI poll function */ | |
1219 | static int smsc911x_poll(struct napi_struct *napi, int budget) | |
1220 | { | |
1221 | struct smsc911x_data *pdata = | |
1222 | container_of(napi, struct smsc911x_data, napi); | |
1223 | struct net_device *dev = pdata->dev; | |
1224 | int npackets = 0; | |
1225 | ||
f88c5b98 | 1226 | while (npackets < budget) { |
fd9abb3d SG |
1227 | unsigned int pktlength; |
1228 | unsigned int pktwords; | |
1229 | struct sk_buff *skb; | |
1230 | unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata); | |
1231 | ||
1232 | if (!rxstat) { | |
1233 | unsigned int temp; | |
1234 | /* We processed all packets available. Tell NAPI it can | |
1235 | * stop polling then re-enable rx interrupts */ | |
1236 | smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_); | |
288379f0 | 1237 | napi_complete(napi); |
fd9abb3d SG |
1238 | temp = smsc911x_reg_read(pdata, INT_EN); |
1239 | temp |= INT_EN_RSFL_EN_; | |
1240 | smsc911x_reg_write(pdata, INT_EN, temp); | |
1241 | break; | |
1242 | } | |
1243 | ||
1244 | /* Count packet for NAPI scheduling, even if it has an error. | |
1245 | * Error packets still require cycles to discard */ | |
1246 | npackets++; | |
1247 | ||
1248 | pktlength = ((rxstat & 0x3FFF0000) >> 16); | |
1249 | pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2; | |
1250 | smsc911x_rx_counterrors(dev, rxstat); | |
1251 | ||
1252 | if (unlikely(rxstat & RX_STS_ES_)) { | |
dffc6b24 JP |
1253 | SMSC_WARN(pdata, rx_err, |
1254 | "Discarding packet with error bit set"); | |
fd9abb3d SG |
1255 | /* Packet has an error, discard it and continue with |
1256 | * the next */ | |
1257 | smsc911x_rx_fastforward(pdata, pktwords); | |
1258 | dev->stats.rx_dropped++; | |
1259 | continue; | |
1260 | } | |
1261 | ||
3c5e979b | 1262 | skb = netdev_alloc_skb(dev, pktwords << 2); |
fd9abb3d | 1263 | if (unlikely(!skb)) { |
dffc6b24 JP |
1264 | SMSC_WARN(pdata, rx_err, |
1265 | "Unable to allocate skb for rx packet"); | |
fd9abb3d SG |
1266 | /* Drop the packet and stop this polling iteration */ |
1267 | smsc911x_rx_fastforward(pdata, pktwords); | |
1268 | dev->stats.rx_dropped++; | |
1269 | break; | |
1270 | } | |
1271 | ||
3c5e979b WD |
1272 | pdata->ops->rx_readfifo(pdata, |
1273 | (unsigned int *)skb->data, pktwords); | |
fd9abb3d SG |
1274 | |
1275 | /* Align IP on 16B boundary */ | |
1276 | skb_reserve(skb, NET_IP_ALIGN); | |
1277 | skb_put(skb, pktlength - 4); | |
fd9abb3d | 1278 | skb->protocol = eth_type_trans(skb, dev); |
bc8acf2c | 1279 | skb_checksum_none_assert(skb); |
fd9abb3d SG |
1280 | netif_receive_skb(skb); |
1281 | ||
1282 | /* Update counters */ | |
1283 | dev->stats.rx_packets++; | |
1284 | dev->stats.rx_bytes += (pktlength - 4); | |
fd9abb3d SG |
1285 | } |
1286 | ||
1287 | /* Return total received packets */ | |
1288 | return npackets; | |
1289 | } | |
1290 | ||
1291 | /* Returns hash bit number for given MAC address | |
1292 | * Example: | |
1293 | * 01 00 5E 00 00 01 -> returns bit number 31 */ | |
1294 | static unsigned int smsc911x_hash(char addr[ETH_ALEN]) | |
1295 | { | |
1296 | return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f; | |
1297 | } | |
1298 | ||
1299 | static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata) | |
1300 | { | |
1301 | /* Performs the multicast & mac_cr update. This is called when | |
1302 | * safe on the current hardware, and with the mac_lock held */ | |
1303 | unsigned int mac_cr; | |
1304 | ||
1305 | SMSC_ASSERT_MAC_LOCK(pdata); | |
1306 | ||
1307 | mac_cr = smsc911x_mac_read(pdata, MAC_CR); | |
1308 | mac_cr |= pdata->set_bits_mask; | |
1309 | mac_cr &= ~(pdata->clear_bits_mask); | |
1310 | smsc911x_mac_write(pdata, MAC_CR, mac_cr); | |
1311 | smsc911x_mac_write(pdata, HASHH, pdata->hashhi); | |
1312 | smsc911x_mac_write(pdata, HASHL, pdata->hashlo); | |
dffc6b24 JP |
1313 | SMSC_TRACE(pdata, hw, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X", |
1314 | mac_cr, pdata->hashhi, pdata->hashlo); | |
fd9abb3d SG |
1315 | } |
1316 | ||
1317 | static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata) | |
1318 | { | |
1319 | unsigned int mac_cr; | |
1320 | ||
1321 | /* This function is only called for older LAN911x devices | |
1322 | * (revA or revB), where MAC_CR, HASHH and HASHL should not | |
1323 | * be modified during Rx - newer devices immediately update the | |
1324 | * registers. | |
1325 | * | |
1326 | * This is called from interrupt context */ | |
1327 | ||
1328 | spin_lock(&pdata->mac_lock); | |
1329 | ||
1330 | /* Check Rx has stopped */ | |
1331 | if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_) | |
dffc6b24 | 1332 | SMSC_WARN(pdata, drv, "Rx not stopped"); |
fd9abb3d SG |
1333 | |
1334 | /* Perform the update - safe to do now Rx has stopped */ | |
1335 | smsc911x_rx_multicast_update(pdata); | |
1336 | ||
1337 | /* Re-enable Rx */ | |
1338 | mac_cr = smsc911x_mac_read(pdata, MAC_CR); | |
1339 | mac_cr |= MAC_CR_RXEN_; | |
1340 | smsc911x_mac_write(pdata, MAC_CR, mac_cr); | |
1341 | ||
1342 | pdata->multicast_update_pending = 0; | |
1343 | ||
1344 | spin_unlock(&pdata->mac_lock); | |
1345 | } | |
1346 | ||
ccf899a2 EBS |
1347 | static int smsc911x_phy_general_power_up(struct smsc911x_data *pdata) |
1348 | { | |
f788e322 PR |
1349 | struct net_device *ndev = pdata->dev; |
1350 | struct phy_device *phy_dev = ndev->phydev; | |
ccf899a2 EBS |
1351 | int rc = 0; |
1352 | ||
f788e322 | 1353 | if (!phy_dev) |
ccf899a2 EBS |
1354 | return rc; |
1355 | ||
1356 | /* If the internal PHY is in General Power-Down mode, all, except the | |
1357 | * management interface, is powered-down and stays in that condition as | |
1358 | * long as Phy register bit 0.11 is HIGH. | |
1359 | * | |
1360 | * In that case, clear the bit 0.11, so the PHY powers up and we can | |
1361 | * access to the phy registers. | |
1362 | */ | |
f788e322 | 1363 | rc = phy_read(phy_dev, MII_BMCR); |
ccf899a2 EBS |
1364 | if (rc < 0) { |
1365 | SMSC_WARN(pdata, drv, "Failed reading PHY control reg"); | |
1366 | return rc; | |
1367 | } | |
1368 | ||
1369 | /* If the PHY general power-down bit is not set is not necessary to | |
1370 | * disable the general power down-mode. | |
1371 | */ | |
1372 | if (rc & BMCR_PDOWN) { | |
f788e322 | 1373 | rc = phy_write(phy_dev, MII_BMCR, rc & ~BMCR_PDOWN); |
ccf899a2 EBS |
1374 | if (rc < 0) { |
1375 | SMSC_WARN(pdata, drv, "Failed writing PHY control reg"); | |
1376 | return rc; | |
1377 | } | |
1378 | ||
1379 | usleep_range(1000, 1500); | |
1380 | } | |
1381 | ||
1382 | return 0; | |
1383 | } | |
1384 | ||
6386994e JMC |
1385 | static int smsc911x_phy_disable_energy_detect(struct smsc911x_data *pdata) |
1386 | { | |
f788e322 PR |
1387 | struct net_device *ndev = pdata->dev; |
1388 | struct phy_device *phy_dev = ndev->phydev; | |
6386994e JMC |
1389 | int rc = 0; |
1390 | ||
f788e322 | 1391 | if (!phy_dev) |
6386994e JMC |
1392 | return rc; |
1393 | ||
f788e322 | 1394 | rc = phy_read(phy_dev, MII_LAN83C185_CTRL_STATUS); |
6386994e JMC |
1395 | |
1396 | if (rc < 0) { | |
1397 | SMSC_WARN(pdata, drv, "Failed reading PHY control reg"); | |
1398 | return rc; | |
1399 | } | |
1400 | ||
242bcd5b AK |
1401 | /* Only disable if energy detect mode is already enabled */ |
1402 | if (rc & MII_LAN83C185_EDPWRDOWN) { | |
6386994e | 1403 | /* Disable energy detect mode for this SMSC Transceivers */ |
f788e322 | 1404 | rc = phy_write(phy_dev, MII_LAN83C185_CTRL_STATUS, |
6386994e JMC |
1405 | rc & (~MII_LAN83C185_EDPWRDOWN)); |
1406 | ||
1407 | if (rc < 0) { | |
1408 | SMSC_WARN(pdata, drv, "Failed writing PHY control reg"); | |
1409 | return rc; | |
1410 | } | |
6ff53fd3 AK |
1411 | /* Allow PHY to wakeup */ |
1412 | mdelay(2); | |
6386994e JMC |
1413 | } |
1414 | ||
1415 | return 0; | |
1416 | } | |
1417 | ||
1418 | static int smsc911x_phy_enable_energy_detect(struct smsc911x_data *pdata) | |
1419 | { | |
f788e322 PR |
1420 | struct net_device *ndev = pdata->dev; |
1421 | struct phy_device *phy_dev = ndev->phydev; | |
6386994e JMC |
1422 | int rc = 0; |
1423 | ||
f788e322 | 1424 | if (!phy_dev) |
6386994e JMC |
1425 | return rc; |
1426 | ||
f788e322 | 1427 | rc = phy_read(phy_dev, MII_LAN83C185_CTRL_STATUS); |
6386994e JMC |
1428 | |
1429 | if (rc < 0) { | |
1430 | SMSC_WARN(pdata, drv, "Failed reading PHY control reg"); | |
1431 | return rc; | |
1432 | } | |
1433 | ||
1434 | /* Only enable if energy detect mode is already disabled */ | |
1435 | if (!(rc & MII_LAN83C185_EDPWRDOWN)) { | |
6386994e | 1436 | /* Enable energy detect mode for this SMSC Transceivers */ |
f788e322 | 1437 | rc = phy_write(phy_dev, MII_LAN83C185_CTRL_STATUS, |
6386994e JMC |
1438 | rc | MII_LAN83C185_EDPWRDOWN); |
1439 | ||
1440 | if (rc < 0) { | |
1441 | SMSC_WARN(pdata, drv, "Failed writing PHY control reg"); | |
1442 | return rc; | |
1443 | } | |
6386994e JMC |
1444 | } |
1445 | return 0; | |
1446 | } | |
1447 | ||
fd9abb3d SG |
1448 | static int smsc911x_soft_reset(struct smsc911x_data *pdata) |
1449 | { | |
1450 | unsigned int timeout; | |
1451 | unsigned int temp; | |
6386994e | 1452 | int ret; |
f6fec61e DC |
1453 | unsigned int reset_offset = HW_CFG; |
1454 | unsigned int reset_mask = HW_CFG_SRST_; | |
6386994e | 1455 | |
ccf899a2 EBS |
1456 | /* |
1457 | * Make sure to power-up the PHY chip before doing a reset, otherwise | |
1458 | * the reset fails. | |
1459 | */ | |
1460 | ret = smsc911x_phy_general_power_up(pdata); | |
1461 | if (ret) { | |
1462 | SMSC_WARN(pdata, drv, "Failed to power-up the PHY chip"); | |
1463 | return ret; | |
1464 | } | |
1465 | ||
6386994e JMC |
1466 | /* |
1467 | * LAN9210/LAN9211/LAN9220/LAN9221 chips have an internal PHY that | |
1468 | * are initialized in a Energy Detect Power-Down mode that prevents | |
1469 | * the MAC chip to be software reseted. So we have to wakeup the PHY | |
1470 | * before. | |
1471 | */ | |
1472 | if (pdata->generation == 4) { | |
1473 | ret = smsc911x_phy_disable_energy_detect(pdata); | |
1474 | ||
1475 | if (ret) { | |
1476 | SMSC_WARN(pdata, drv, "Failed to wakeup the PHY chip"); | |
1477 | return ret; | |
1478 | } | |
1479 | } | |
fd9abb3d | 1480 | |
f6fec61e DC |
1481 | if ((pdata->idrev & 0xFFFF0000) == LAN9250) { |
1482 | /* special reset for LAN9250 */ | |
1483 | reset_offset = RESET_CTL; | |
1484 | reset_mask = RESET_CTL_DIGITAL_RST_; | |
1485 | } | |
1486 | ||
fd9abb3d | 1487 | /* Reset the LAN911x */ |
f6fec61e DC |
1488 | smsc911x_reg_write(pdata, reset_offset, reset_mask); |
1489 | ||
1490 | /* verify reset bit is cleared */ | |
fd9abb3d SG |
1491 | timeout = 10; |
1492 | do { | |
1493 | udelay(10); | |
f6fec61e DC |
1494 | temp = smsc911x_reg_read(pdata, reset_offset); |
1495 | } while ((--timeout) && (temp & reset_mask)); | |
fd9abb3d | 1496 | |
f6fec61e | 1497 | if (unlikely(temp & reset_mask)) { |
dffc6b24 | 1498 | SMSC_WARN(pdata, drv, "Failed to complete reset"); |
fd9abb3d SG |
1499 | return -EIO; |
1500 | } | |
6386994e JMC |
1501 | |
1502 | if (pdata->generation == 4) { | |
1503 | ret = smsc911x_phy_enable_energy_detect(pdata); | |
1504 | ||
1505 | if (ret) { | |
1506 | SMSC_WARN(pdata, drv, "Failed to wakeup the PHY chip"); | |
1507 | return ret; | |
1508 | } | |
1509 | } | |
1510 | ||
fd9abb3d SG |
1511 | return 0; |
1512 | } | |
1513 | ||
1514 | /* Sets the device MAC address to dev_addr, called with mac_lock held */ | |
1515 | static void | |
225ddf49 | 1516 | smsc911x_set_hw_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6]) |
fd9abb3d SG |
1517 | { |
1518 | u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4]; | |
1519 | u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) | | |
1520 | (dev_addr[1] << 8) | dev_addr[0]; | |
1521 | ||
1522 | SMSC_ASSERT_MAC_LOCK(pdata); | |
1523 | ||
1524 | smsc911x_mac_write(pdata, ADDRH, mac_high16); | |
1525 | smsc911x_mac_write(pdata, ADDRL, mac_low32); | |
1526 | } | |
1527 | ||
8e27628e MB |
1528 | static void smsc911x_disable_irq_chip(struct net_device *dev) |
1529 | { | |
1530 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1531 | ||
1532 | smsc911x_reg_write(pdata, INT_EN, 0); | |
1533 | smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF); | |
1534 | } | |
1535 | ||
a85f00c3 JL |
1536 | static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id) |
1537 | { | |
1538 | struct net_device *dev = dev_id; | |
1539 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1540 | u32 intsts = smsc911x_reg_read(pdata, INT_STS); | |
1541 | u32 inten = smsc911x_reg_read(pdata, INT_EN); | |
1542 | int serviced = IRQ_NONE; | |
1543 | u32 temp; | |
1544 | ||
1545 | if (unlikely(intsts & inten & INT_STS_SW_INT_)) { | |
1546 | temp = smsc911x_reg_read(pdata, INT_EN); | |
1547 | temp &= (~INT_EN_SW_INT_EN_); | |
1548 | smsc911x_reg_write(pdata, INT_EN, temp); | |
1549 | smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_); | |
1550 | pdata->software_irq_signal = 1; | |
1551 | smp_wmb(); | |
1552 | serviced = IRQ_HANDLED; | |
1553 | } | |
1554 | ||
1555 | if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) { | |
1556 | /* Called when there is a multicast update scheduled and | |
1557 | * it is now safe to complete the update */ | |
1558 | SMSC_TRACE(pdata, intr, "RX Stop interrupt"); | |
1559 | smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_); | |
1560 | if (pdata->multicast_update_pending) | |
1561 | smsc911x_rx_multicast_update_workaround(pdata); | |
1562 | serviced = IRQ_HANDLED; | |
1563 | } | |
1564 | ||
1565 | if (intsts & inten & INT_STS_TDFA_) { | |
1566 | temp = smsc911x_reg_read(pdata, FIFO_INT); | |
1567 | temp |= FIFO_INT_TX_AVAIL_LEVEL_; | |
1568 | smsc911x_reg_write(pdata, FIFO_INT, temp); | |
1569 | smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_); | |
1570 | netif_wake_queue(dev); | |
1571 | serviced = IRQ_HANDLED; | |
1572 | } | |
1573 | ||
1574 | if (unlikely(intsts & inten & INT_STS_RXE_)) { | |
1575 | SMSC_TRACE(pdata, intr, "RX Error interrupt"); | |
1576 | smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_); | |
1577 | serviced = IRQ_HANDLED; | |
1578 | } | |
1579 | ||
1580 | if (likely(intsts & inten & INT_STS_RSFL_)) { | |
1581 | if (likely(napi_schedule_prep(&pdata->napi))) { | |
1582 | /* Disable Rx interrupts */ | |
1583 | temp = smsc911x_reg_read(pdata, INT_EN); | |
1584 | temp &= (~INT_EN_RSFL_EN_); | |
1585 | smsc911x_reg_write(pdata, INT_EN, temp); | |
1586 | /* Schedule a NAPI poll */ | |
1587 | __napi_schedule(&pdata->napi); | |
1588 | } else { | |
1589 | SMSC_WARN(pdata, rx_err, "napi_schedule_prep failed"); | |
1590 | } | |
1591 | serviced = IRQ_HANDLED; | |
1592 | } | |
1593 | ||
1594 | return serviced; | |
1595 | } | |
1596 | ||
fd9abb3d SG |
1597 | static int smsc911x_open(struct net_device *dev) |
1598 | { | |
1599 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1600 | unsigned int timeout; | |
1601 | unsigned int temp; | |
1602 | unsigned int intcfg; | |
1358bd5a | 1603 | int retval; |
f252974e | 1604 | int irq_flags; |
fd9abb3d | 1605 | |
aea95dd5 | 1606 | /* find and start the given phy */ |
f788e322 | 1607 | if (!dev->phydev) { |
aea95dd5 JL |
1608 | retval = smsc911x_mii_probe(dev); |
1609 | if (retval < 0) { | |
1610 | SMSC_WARN(pdata, probe, "Error starting phy"); | |
1611 | goto out; | |
1612 | } | |
fd9abb3d SG |
1613 | } |
1614 | ||
fd9abb3d | 1615 | /* Reset the LAN911x */ |
1358bd5a JL |
1616 | retval = smsc911x_soft_reset(pdata); |
1617 | if (retval) { | |
dffc6b24 | 1618 | SMSC_WARN(pdata, hw, "soft reset failed"); |
aea95dd5 | 1619 | goto mii_free_out; |
fd9abb3d SG |
1620 | } |
1621 | ||
1622 | smsc911x_reg_write(pdata, HW_CFG, 0x00050000); | |
1623 | smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740); | |
1624 | ||
f277e65e GW |
1625 | /* Increase the legal frame size of VLAN tagged frames to 1522 bytes */ |
1626 | spin_lock_irq(&pdata->mac_lock); | |
1627 | smsc911x_mac_write(pdata, VLAN1, ETH_P_8021Q); | |
1628 | spin_unlock_irq(&pdata->mac_lock); | |
1629 | ||
fd9abb3d SG |
1630 | /* Make sure EEPROM has finished loading before setting GPIO_CFG */ |
1631 | timeout = 50; | |
f7efb6cc SG |
1632 | while ((smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) && |
1633 | --timeout) { | |
fd9abb3d SG |
1634 | udelay(10); |
1635 | } | |
1636 | ||
1637 | if (unlikely(timeout == 0)) | |
dffc6b24 JP |
1638 | SMSC_WARN(pdata, ifup, |
1639 | "Timed out waiting for EEPROM busy bit to clear"); | |
fd9abb3d SG |
1640 | |
1641 | smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000); | |
1642 | ||
1643 | /* The soft reset above cleared the device's MAC address, | |
1644 | * restore it from local copy (set in probe) */ | |
1645 | spin_lock_irq(&pdata->mac_lock); | |
225ddf49 | 1646 | smsc911x_set_hw_mac_address(pdata, dev->dev_addr); |
fd9abb3d SG |
1647 | spin_unlock_irq(&pdata->mac_lock); |
1648 | ||
1649 | /* Initialise irqs, but leave all sources disabled */ | |
8e27628e | 1650 | smsc911x_disable_irq_chip(dev); |
fd9abb3d SG |
1651 | |
1652 | /* Set interrupt deassertion to 100uS */ | |
1653 | intcfg = ((10 << 24) | INT_CFG_IRQ_EN_); | |
1654 | ||
2107fb8b | 1655 | if (pdata->config.irq_polarity) { |
dffc6b24 | 1656 | SMSC_TRACE(pdata, ifup, "irq polarity: active high"); |
fd9abb3d SG |
1657 | intcfg |= INT_CFG_IRQ_POL_; |
1658 | } else { | |
dffc6b24 | 1659 | SMSC_TRACE(pdata, ifup, "irq polarity: active low"); |
fd9abb3d SG |
1660 | } |
1661 | ||
2107fb8b | 1662 | if (pdata->config.irq_type) { |
dffc6b24 | 1663 | SMSC_TRACE(pdata, ifup, "irq type: push-pull"); |
fd9abb3d SG |
1664 | intcfg |= INT_CFG_IRQ_TYPE_; |
1665 | } else { | |
dffc6b24 | 1666 | SMSC_TRACE(pdata, ifup, "irq type: open drain"); |
fd9abb3d SG |
1667 | } |
1668 | ||
1669 | smsc911x_reg_write(pdata, INT_CFG, intcfg); | |
1670 | ||
dffc6b24 | 1671 | SMSC_TRACE(pdata, ifup, "Testing irq handler using IRQ %d", dev->irq); |
fd9abb3d SG |
1672 | pdata->software_irq_signal = 0; |
1673 | smp_wmb(); | |
1674 | ||
f252974e JL |
1675 | irq_flags = irq_get_trigger_type(dev->irq); |
1676 | retval = request_irq(dev->irq, smsc911x_irqhandler, | |
1677 | irq_flags | IRQF_SHARED, dev->name, dev); | |
1678 | if (retval) { | |
1679 | SMSC_WARN(pdata, probe, | |
1680 | "Unable to claim requested irq: %d", dev->irq); | |
1681 | goto mii_free_out; | |
1682 | } | |
1683 | ||
fd9abb3d SG |
1684 | temp = smsc911x_reg_read(pdata, INT_EN); |
1685 | temp |= INT_EN_SW_INT_EN_; | |
1686 | smsc911x_reg_write(pdata, INT_EN, temp); | |
1687 | ||
1688 | timeout = 1000; | |
1689 | while (timeout--) { | |
1690 | if (pdata->software_irq_signal) | |
1691 | break; | |
1692 | msleep(1); | |
1693 | } | |
1694 | ||
1695 | if (!pdata->software_irq_signal) { | |
dffc6b24 JP |
1696 | netdev_warn(dev, "ISR failed signaling test (IRQ %d)\n", |
1697 | dev->irq); | |
1358bd5a | 1698 | retval = -ENODEV; |
f252974e | 1699 | goto irq_stop_out; |
fd9abb3d | 1700 | } |
dffc6b24 JP |
1701 | SMSC_TRACE(pdata, ifup, "IRQ handler passed test using IRQ %d", |
1702 | dev->irq); | |
fd9abb3d | 1703 | |
dffc6b24 JP |
1704 | netdev_info(dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n", |
1705 | (unsigned long)pdata->ioaddr, dev->irq); | |
fd9abb3d | 1706 | |
44c1d6f9 SG |
1707 | /* Reset the last known duplex and carrier */ |
1708 | pdata->last_duplex = -1; | |
1709 | pdata->last_carrier = -1; | |
1710 | ||
fd9abb3d | 1711 | /* Bring the PHY up */ |
f788e322 | 1712 | phy_start(dev->phydev); |
fd9abb3d SG |
1713 | |
1714 | temp = smsc911x_reg_read(pdata, HW_CFG); | |
1715 | /* Preserve TX FIFO size and external PHY configuration */ | |
1716 | temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF); | |
1717 | temp |= HW_CFG_SF_; | |
1718 | smsc911x_reg_write(pdata, HW_CFG, temp); | |
1719 | ||
1720 | temp = smsc911x_reg_read(pdata, FIFO_INT); | |
1721 | temp |= FIFO_INT_TX_AVAIL_LEVEL_; | |
1722 | temp &= ~(FIFO_INT_RX_STS_LEVEL_); | |
1723 | smsc911x_reg_write(pdata, FIFO_INT, temp); | |
1724 | ||
1725 | /* set RX Data offset to 2 bytes for alignment */ | |
3c5e979b | 1726 | smsc911x_reg_write(pdata, RX_CFG, (NET_IP_ALIGN << 8)); |
fd9abb3d SG |
1727 | |
1728 | /* enable NAPI polling before enabling RX interrupts */ | |
1729 | napi_enable(&pdata->napi); | |
1730 | ||
1731 | temp = smsc911x_reg_read(pdata, INT_EN); | |
1373c0fd | 1732 | temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_RXSTOP_INT_EN_); |
fd9abb3d SG |
1733 | smsc911x_reg_write(pdata, INT_EN, temp); |
1734 | ||
1735 | spin_lock_irq(&pdata->mac_lock); | |
1736 | temp = smsc911x_mac_read(pdata, MAC_CR); | |
1737 | temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_); | |
1738 | smsc911x_mac_write(pdata, MAC_CR, temp); | |
1739 | spin_unlock_irq(&pdata->mac_lock); | |
1740 | ||
1741 | smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_); | |
1742 | ||
1743 | netif_start_queue(dev); | |
1744 | return 0; | |
aea95dd5 | 1745 | |
f252974e JL |
1746 | irq_stop_out: |
1747 | free_irq(dev->irq, dev); | |
aea95dd5 JL |
1748 | mii_free_out: |
1749 | phy_disconnect(dev->phydev); | |
1750 | dev->phydev = NULL; | |
1358bd5a JL |
1751 | out: |
1752 | return retval; | |
fd9abb3d SG |
1753 | } |
1754 | ||
1755 | /* Entry point for stopping the interface */ | |
1756 | static int smsc911x_stop(struct net_device *dev) | |
1757 | { | |
1758 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1759 | unsigned int temp; | |
1760 | ||
fd9abb3d SG |
1761 | /* Disable all device interrupts */ |
1762 | temp = smsc911x_reg_read(pdata, INT_CFG); | |
1763 | temp &= ~INT_CFG_IRQ_EN_; | |
1764 | smsc911x_reg_write(pdata, INT_CFG, temp); | |
1765 | ||
1766 | /* Stop Tx and Rx polling */ | |
1767 | netif_stop_queue(dev); | |
1768 | napi_disable(&pdata->napi); | |
1769 | ||
1770 | /* At this point all Rx and Tx activity is stopped */ | |
1771 | dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP); | |
1772 | smsc911x_tx_update_txcounters(dev); | |
1773 | ||
f252974e JL |
1774 | free_irq(dev->irq, dev); |
1775 | ||
fd9abb3d | 1776 | /* Bring the PHY down */ |
aea95dd5 | 1777 | if (dev->phydev) { |
f788e322 | 1778 | phy_stop(dev->phydev); |
aea95dd5 JL |
1779 | phy_disconnect(dev->phydev); |
1780 | dev->phydev = NULL; | |
1781 | } | |
1782 | netif_carrier_off(dev); | |
fd9abb3d | 1783 | |
dffc6b24 | 1784 | SMSC_TRACE(pdata, ifdown, "Interface stopped"); |
fd9abb3d SG |
1785 | return 0; |
1786 | } | |
1787 | ||
1788 | /* Entry point for transmitting a packet */ | |
1789 | static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1790 | { | |
1791 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1792 | unsigned int freespace; | |
1793 | unsigned int tx_cmd_a; | |
1794 | unsigned int tx_cmd_b; | |
1795 | unsigned int temp; | |
1796 | u32 wrsz; | |
1797 | ulong bufp; | |
1798 | ||
1799 | freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_; | |
1800 | ||
1801 | if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD)) | |
dffc6b24 JP |
1802 | SMSC_WARN(pdata, tx_err, |
1803 | "Tx data fifo low, space available: %d", freespace); | |
fd9abb3d SG |
1804 | |
1805 | /* Word alignment adjustment */ | |
1806 | tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16; | |
1807 | tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_; | |
1808 | tx_cmd_a |= (unsigned int)skb->len; | |
1809 | ||
1810 | tx_cmd_b = ((unsigned int)skb->len) << 16; | |
1811 | tx_cmd_b |= (unsigned int)skb->len; | |
1812 | ||
1813 | smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a); | |
1814 | smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b); | |
1815 | ||
1816 | bufp = (ulong)skb->data & (~0x3); | |
1817 | wrsz = (u32)skb->len + 3; | |
1818 | wrsz += (u32)((ulong)skb->data & 0x3); | |
1819 | wrsz >>= 2; | |
1820 | ||
c326de88 | 1821 | pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz); |
fd9abb3d | 1822 | freespace -= (skb->len + 32); |
8c0069ae | 1823 | skb_tx_timestamp(skb); |
89a9eb63 | 1824 | dev_consume_skb_any(skb); |
fd9abb3d SG |
1825 | |
1826 | if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30)) | |
1827 | smsc911x_tx_update_txcounters(dev); | |
1828 | ||
1829 | if (freespace < TX_FIFO_LOW_THRESHOLD) { | |
1830 | netif_stop_queue(dev); | |
1831 | temp = smsc911x_reg_read(pdata, FIFO_INT); | |
1832 | temp &= 0x00FFFFFF; | |
1833 | temp |= 0x32000000; | |
1834 | smsc911x_reg_write(pdata, FIFO_INT, temp); | |
1835 | } | |
1836 | ||
1837 | return NETDEV_TX_OK; | |
1838 | } | |
1839 | ||
1840 | /* Entry point for getting status counters */ | |
1841 | static struct net_device_stats *smsc911x_get_stats(struct net_device *dev) | |
1842 | { | |
1843 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1844 | smsc911x_tx_update_txcounters(dev); | |
1845 | dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP); | |
1846 | return &dev->stats; | |
1847 | } | |
1848 | ||
1849 | /* Entry point for setting addressing modes */ | |
1850 | static void smsc911x_set_multicast_list(struct net_device *dev) | |
1851 | { | |
1852 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1853 | unsigned long flags; | |
1854 | ||
1855 | if (dev->flags & IFF_PROMISC) { | |
1856 | /* Enabling promiscuous mode */ | |
1857 | pdata->set_bits_mask = MAC_CR_PRMS_; | |
1858 | pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_); | |
1859 | pdata->hashhi = 0; | |
1860 | pdata->hashlo = 0; | |
1861 | } else if (dev->flags & IFF_ALLMULTI) { | |
1862 | /* Enabling all multicast mode */ | |
1863 | pdata->set_bits_mask = MAC_CR_MCPAS_; | |
1864 | pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_); | |
1865 | pdata->hashhi = 0; | |
1866 | pdata->hashlo = 0; | |
4cd24eaf | 1867 | } else if (!netdev_mc_empty(dev)) { |
fd9abb3d SG |
1868 | /* Enabling specific multicast addresses */ |
1869 | unsigned int hash_high = 0; | |
1870 | unsigned int hash_low = 0; | |
22bedad3 | 1871 | struct netdev_hw_addr *ha; |
fd9abb3d SG |
1872 | |
1873 | pdata->set_bits_mask = MAC_CR_HPFILT_; | |
1874 | pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_); | |
1875 | ||
22bedad3 JP |
1876 | netdev_for_each_mc_addr(ha, dev) { |
1877 | unsigned int bitnum = smsc911x_hash(ha->addr); | |
2a0d18f9 JP |
1878 | unsigned int mask = 0x01 << (bitnum & 0x1F); |
1879 | ||
1880 | if (bitnum & 0x20) | |
1881 | hash_high |= mask; | |
1882 | else | |
1883 | hash_low |= mask; | |
fd9abb3d | 1884 | } |
fd9abb3d SG |
1885 | |
1886 | pdata->hashhi = hash_high; | |
1887 | pdata->hashlo = hash_low; | |
1888 | } else { | |
1889 | /* Enabling local MAC address only */ | |
1890 | pdata->set_bits_mask = 0; | |
1891 | pdata->clear_bits_mask = | |
1892 | (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_); | |
1893 | pdata->hashhi = 0; | |
1894 | pdata->hashlo = 0; | |
1895 | } | |
1896 | ||
1897 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
1898 | ||
1899 | if (pdata->generation <= 1) { | |
1900 | /* Older hardware revision - cannot change these flags while | |
1901 | * receiving data */ | |
1902 | if (!pdata->multicast_update_pending) { | |
1903 | unsigned int temp; | |
dffc6b24 | 1904 | SMSC_TRACE(pdata, hw, "scheduling mcast update"); |
fd9abb3d SG |
1905 | pdata->multicast_update_pending = 1; |
1906 | ||
1907 | /* Request the hardware to stop, then perform the | |
1908 | * update when we get an RX_STOP interrupt */ | |
fd9abb3d SG |
1909 | temp = smsc911x_mac_read(pdata, MAC_CR); |
1910 | temp &= ~(MAC_CR_RXEN_); | |
1911 | smsc911x_mac_write(pdata, MAC_CR, temp); | |
1912 | } else { | |
1913 | /* There is another update pending, this should now | |
1914 | * use the newer values */ | |
1915 | } | |
1916 | } else { | |
1917 | /* Newer hardware revision - can write immediately */ | |
1918 | smsc911x_rx_multicast_update(pdata); | |
1919 | } | |
1920 | ||
1921 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
1922 | } | |
1923 | ||
fd9abb3d | 1924 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1757ab2f | 1925 | static void smsc911x_poll_controller(struct net_device *dev) |
fd9abb3d SG |
1926 | { |
1927 | disable_irq(dev->irq); | |
1928 | smsc911x_irqhandler(0, dev); | |
1929 | enable_irq(dev->irq); | |
1930 | } | |
1931 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | |
1932 | ||
225ddf49 SG |
1933 | static int smsc911x_set_mac_address(struct net_device *dev, void *p) |
1934 | { | |
1935 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1936 | struct sockaddr *addr = p; | |
1937 | ||
1938 | /* On older hardware revisions we cannot change the mac address | |
1939 | * registers while receiving data. Newer devices can safely change | |
1940 | * this at any time. */ | |
1941 | if (pdata->generation <= 1 && netif_running(dev)) | |
1942 | return -EBUSY; | |
1943 | ||
1944 | if (!is_valid_ether_addr(addr->sa_data)) | |
1945 | return -EADDRNOTAVAIL; | |
1946 | ||
1947 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); | |
1948 | ||
1949 | spin_lock_irq(&pdata->mac_lock); | |
1950 | smsc911x_set_hw_mac_address(pdata, dev->dev_addr); | |
1951 | spin_unlock_irq(&pdata->mac_lock); | |
1952 | ||
dffc6b24 | 1953 | netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr); |
225ddf49 SG |
1954 | |
1955 | return 0; | |
1956 | } | |
1957 | ||
fd9abb3d SG |
1958 | /* Standard ioctls for mii-tool */ |
1959 | static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
1960 | { | |
f788e322 | 1961 | if (!netif_running(dev) || !dev->phydev) |
fd9abb3d SG |
1962 | return -EINVAL; |
1963 | ||
f788e322 | 1964 | return phy_mii_ioctl(dev->phydev, ifr, cmd); |
fd9abb3d SG |
1965 | } |
1966 | ||
fd9abb3d SG |
1967 | static void smsc911x_ethtool_getdrvinfo(struct net_device *dev, |
1968 | struct ethtool_drvinfo *info) | |
1969 | { | |
1970 | strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver)); | |
1971 | strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version)); | |
db1d7bf7 | 1972 | strlcpy(info->bus_info, dev_name(dev->dev.parent), |
fd9abb3d SG |
1973 | sizeof(info->bus_info)); |
1974 | } | |
1975 | ||
fd9abb3d SG |
1976 | static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev) |
1977 | { | |
1978 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1979 | return pdata->msg_enable; | |
1980 | } | |
1981 | ||
1982 | static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level) | |
1983 | { | |
1984 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1985 | pdata->msg_enable = level; | |
1986 | } | |
1987 | ||
1988 | static int smsc911x_ethtool_getregslen(struct net_device *dev) | |
1989 | { | |
1990 | return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) * | |
1991 | sizeof(u32); | |
1992 | } | |
1993 | ||
1994 | static void | |
1995 | smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs, | |
1996 | void *buf) | |
1997 | { | |
1998 | struct smsc911x_data *pdata = netdev_priv(dev); | |
f788e322 | 1999 | struct phy_device *phy_dev = dev->phydev; |
fd9abb3d SG |
2000 | unsigned long flags; |
2001 | unsigned int i; | |
2002 | unsigned int j = 0; | |
2003 | u32 *data = buf; | |
2004 | ||
2005 | regs->version = pdata->idrev; | |
2006 | for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32))) | |
2007 | data[j++] = smsc911x_reg_read(pdata, i); | |
2008 | ||
2009 | for (i = MAC_CR; i <= WUCSR; i++) { | |
2010 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
2011 | data[j++] = smsc911x_mac_read(pdata, i); | |
2012 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
2013 | } | |
2014 | ||
2015 | for (i = 0; i <= 31; i++) | |
e5a03bfd AL |
2016 | data[j++] = smsc911x_mii_read(phy_dev->mdio.bus, |
2017 | phy_dev->mdio.addr, i); | |
fd9abb3d SG |
2018 | } |
2019 | ||
2020 | static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata) | |
2021 | { | |
2022 | unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG); | |
2023 | temp &= ~GPIO_CFG_EEPR_EN_; | |
2024 | smsc911x_reg_write(pdata, GPIO_CFG, temp); | |
2025 | msleep(1); | |
2026 | } | |
2027 | ||
2028 | static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op) | |
2029 | { | |
2030 | int timeout = 100; | |
2031 | u32 e2cmd; | |
2032 | ||
dffc6b24 | 2033 | SMSC_TRACE(pdata, drv, "op 0x%08x", op); |
fd9abb3d | 2034 | if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) { |
dffc6b24 | 2035 | SMSC_WARN(pdata, drv, "Busy at start"); |
fd9abb3d SG |
2036 | return -EBUSY; |
2037 | } | |
2038 | ||
2039 | e2cmd = op | E2P_CMD_EPC_BUSY_; | |
2040 | smsc911x_reg_write(pdata, E2P_CMD, e2cmd); | |
2041 | ||
2042 | do { | |
2043 | msleep(1); | |
2044 | e2cmd = smsc911x_reg_read(pdata, E2P_CMD); | |
2cf0dbed | 2045 | } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout)); |
fd9abb3d SG |
2046 | |
2047 | if (!timeout) { | |
dffc6b24 | 2048 | SMSC_TRACE(pdata, drv, "TIMED OUT"); |
fd9abb3d SG |
2049 | return -EAGAIN; |
2050 | } | |
2051 | ||
2052 | if (e2cmd & E2P_CMD_EPC_TIMEOUT_) { | |
1c01a80c | 2053 | SMSC_TRACE(pdata, drv, "Error occurred during eeprom operation"); |
fd9abb3d SG |
2054 | return -EINVAL; |
2055 | } | |
2056 | ||
2057 | return 0; | |
2058 | } | |
2059 | ||
2060 | static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata, | |
2061 | u8 address, u8 *data) | |
2062 | { | |
2063 | u32 op = E2P_CMD_EPC_CMD_READ_ | address; | |
2064 | int ret; | |
2065 | ||
dffc6b24 | 2066 | SMSC_TRACE(pdata, drv, "address 0x%x", address); |
fd9abb3d SG |
2067 | ret = smsc911x_eeprom_send_cmd(pdata, op); |
2068 | ||
2069 | if (!ret) | |
2070 | data[address] = smsc911x_reg_read(pdata, E2P_DATA); | |
2071 | ||
2072 | return ret; | |
2073 | } | |
2074 | ||
2075 | static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata, | |
2076 | u8 address, u8 data) | |
2077 | { | |
2078 | u32 op = E2P_CMD_EPC_CMD_ERASE_ | address; | |
58add9fc | 2079 | u32 temp; |
fd9abb3d SG |
2080 | int ret; |
2081 | ||
dffc6b24 | 2082 | SMSC_TRACE(pdata, drv, "address 0x%x, data 0x%x", address, data); |
fd9abb3d SG |
2083 | ret = smsc911x_eeprom_send_cmd(pdata, op); |
2084 | ||
2085 | if (!ret) { | |
2086 | op = E2P_CMD_EPC_CMD_WRITE_ | address; | |
2087 | smsc911x_reg_write(pdata, E2P_DATA, (u32)data); | |
58add9fc SG |
2088 | |
2089 | /* Workaround for hardware read-after-write restriction */ | |
2090 | temp = smsc911x_reg_read(pdata, BYTE_TEST); | |
2091 | ||
fd9abb3d SG |
2092 | ret = smsc911x_eeprom_send_cmd(pdata, op); |
2093 | } | |
2094 | ||
2095 | return ret; | |
2096 | } | |
2097 | ||
2098 | static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev) | |
2099 | { | |
2100 | return SMSC911X_EEPROM_SIZE; | |
2101 | } | |
2102 | ||
2103 | static int smsc911x_ethtool_get_eeprom(struct net_device *dev, | |
2104 | struct ethtool_eeprom *eeprom, u8 *data) | |
2105 | { | |
2106 | struct smsc911x_data *pdata = netdev_priv(dev); | |
2107 | u8 eeprom_data[SMSC911X_EEPROM_SIZE]; | |
2108 | int len; | |
2109 | int i; | |
2110 | ||
2111 | smsc911x_eeprom_enable_access(pdata); | |
2112 | ||
2113 | len = min(eeprom->len, SMSC911X_EEPROM_SIZE); | |
2114 | for (i = 0; i < len; i++) { | |
2115 | int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data); | |
2116 | if (ret < 0) { | |
2117 | eeprom->len = 0; | |
2118 | return ret; | |
2119 | } | |
2120 | } | |
2121 | ||
2122 | memcpy(data, &eeprom_data[eeprom->offset], len); | |
2123 | eeprom->len = len; | |
2124 | return 0; | |
2125 | } | |
2126 | ||
2127 | static int smsc911x_ethtool_set_eeprom(struct net_device *dev, | |
2128 | struct ethtool_eeprom *eeprom, u8 *data) | |
2129 | { | |
2130 | int ret; | |
2131 | struct smsc911x_data *pdata = netdev_priv(dev); | |
2132 | ||
2133 | smsc911x_eeprom_enable_access(pdata); | |
2134 | smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_); | |
2135 | ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data); | |
2136 | smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_); | |
2137 | ||
2138 | /* Single byte write, according to man page */ | |
2139 | eeprom->len = 1; | |
2140 | ||
2141 | return ret; | |
2142 | } | |
2143 | ||
cb5b04fe | 2144 | static const struct ethtool_ops smsc911x_ethtool_ops = { |
fd9abb3d SG |
2145 | .get_link = ethtool_op_get_link, |
2146 | .get_drvinfo = smsc911x_ethtool_getdrvinfo, | |
fe1eb9c5 | 2147 | .nway_reset = phy_ethtool_nway_reset, |
fd9abb3d SG |
2148 | .get_msglevel = smsc911x_ethtool_getmsglevel, |
2149 | .set_msglevel = smsc911x_ethtool_setmsglevel, | |
2150 | .get_regs_len = smsc911x_ethtool_getregslen, | |
2151 | .get_regs = smsc911x_ethtool_getregs, | |
2152 | .get_eeprom_len = smsc911x_ethtool_get_eeprom_len, | |
2153 | .get_eeprom = smsc911x_ethtool_get_eeprom, | |
2154 | .set_eeprom = smsc911x_ethtool_set_eeprom, | |
b5d1d256 | 2155 | .get_ts_info = ethtool_op_get_ts_info, |
2c087409 PR |
2156 | .get_link_ksettings = phy_ethtool_get_link_ksettings, |
2157 | .set_link_ksettings = phy_ethtool_set_link_ksettings, | |
fd9abb3d SG |
2158 | }; |
2159 | ||
631b7568 SG |
2160 | static const struct net_device_ops smsc911x_netdev_ops = { |
2161 | .ndo_open = smsc911x_open, | |
2162 | .ndo_stop = smsc911x_stop, | |
2163 | .ndo_start_xmit = smsc911x_hard_start_xmit, | |
2164 | .ndo_get_stats = smsc911x_get_stats, | |
afc4b13d | 2165 | .ndo_set_rx_mode = smsc911x_set_multicast_list, |
631b7568 SG |
2166 | .ndo_do_ioctl = smsc911x_do_ioctl, |
2167 | .ndo_validate_addr = eth_validate_addr, | |
225ddf49 | 2168 | .ndo_set_mac_address = smsc911x_set_mac_address, |
631b7568 SG |
2169 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2170 | .ndo_poll_controller = smsc911x_poll_controller, | |
2171 | #endif | |
2172 | }; | |
2173 | ||
31f45747 | 2174 | /* copies the current mac address from hardware to dev->dev_addr */ |
8489ec1f | 2175 | static void smsc911x_read_mac_address(struct net_device *dev) |
31f45747 SG |
2176 | { |
2177 | struct smsc911x_data *pdata = netdev_priv(dev); | |
2178 | u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH); | |
2179 | u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL); | |
2180 | ||
2181 | dev->dev_addr[0] = (u8)(mac_low32); | |
2182 | dev->dev_addr[1] = (u8)(mac_low32 >> 8); | |
2183 | dev->dev_addr[2] = (u8)(mac_low32 >> 16); | |
2184 | dev->dev_addr[3] = (u8)(mac_low32 >> 24); | |
2185 | dev->dev_addr[4] = (u8)(mac_high16); | |
2186 | dev->dev_addr[5] = (u8)(mac_high16 >> 8); | |
2187 | } | |
2188 | ||
fd9abb3d | 2189 | /* Initializing private device structures, only called from probe */ |
8489ec1f | 2190 | static int smsc911x_init(struct net_device *dev) |
fd9abb3d SG |
2191 | { |
2192 | struct smsc911x_data *pdata = netdev_priv(dev); | |
769ce4c9 | 2193 | unsigned int byte_test, mask; |
3ac3546e | 2194 | unsigned int to = 100; |
fd9abb3d | 2195 | |
dffc6b24 JP |
2196 | SMSC_TRACE(pdata, probe, "Driver Parameters:"); |
2197 | SMSC_TRACE(pdata, probe, "LAN base: 0x%08lX", | |
2198 | (unsigned long)pdata->ioaddr); | |
2199 | SMSC_TRACE(pdata, probe, "IRQ: %d", dev->irq); | |
2200 | SMSC_TRACE(pdata, probe, "PHY will be autodetected."); | |
fd9abb3d | 2201 | |
fd9abb3d | 2202 | spin_lock_init(&pdata->dev_lock); |
35a67edf | 2203 | spin_lock_init(&pdata->mac_lock); |
fd9abb3d | 2204 | |
6fed9592 | 2205 | if (pdata->ioaddr == NULL) { |
dffc6b24 | 2206 | SMSC_WARN(pdata, probe, "pdata->ioaddr: 0x00000000"); |
fd9abb3d SG |
2207 | return -ENODEV; |
2208 | } | |
2209 | ||
3ac3546e RM |
2210 | /* |
2211 | * poll the READY bit in PMT_CTRL. Any other access to the device is | |
2212 | * forbidden while this bit isn't set. Try for 100ms | |
769ce4c9 KP |
2213 | * |
2214 | * Note that this test is done before the WORD_SWAP register is | |
2215 | * programmed. So in some configurations the READY bit is at 16 before | |
2216 | * WORD_SWAP is written to. This issue is worked around by waiting | |
2217 | * until either bit 0 or bit 16 gets set in PMT_CTRL. | |
2218 | * | |
2219 | * SMSC has confirmed that checking bit 16 (marked as reserved in | |
2220 | * the datasheet) is fine since these bits "will either never be set | |
2221 | * or can only go high after READY does (so also indicate the device | |
2222 | * is ready)". | |
3ac3546e | 2223 | */ |
769ce4c9 KP |
2224 | |
2225 | mask = PMT_CTRL_READY_ | swahw32(PMT_CTRL_READY_); | |
2226 | while (!(smsc911x_reg_read(pdata, PMT_CTRL) & mask) && --to) | |
3ac3546e | 2227 | udelay(1000); |
769ce4c9 | 2228 | |
3ac3546e | 2229 | if (to == 0) { |
b1a04a62 | 2230 | netdev_err(dev, "Device not READY in 100ms aborting\n"); |
3ac3546e RM |
2231 | return -ENODEV; |
2232 | } | |
2233 | ||
fd9abb3d SG |
2234 | /* Check byte ordering */ |
2235 | byte_test = smsc911x_reg_read(pdata, BYTE_TEST); | |
dffc6b24 | 2236 | SMSC_TRACE(pdata, probe, "BYTE_TEST: 0x%08X", byte_test); |
fd9abb3d | 2237 | if (byte_test == 0x43218765) { |
dffc6b24 JP |
2238 | SMSC_TRACE(pdata, probe, "BYTE_TEST looks swapped, " |
2239 | "applying WORD_SWAP"); | |
fd9abb3d SG |
2240 | smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff); |
2241 | ||
2242 | /* 1 dummy read of BYTE_TEST is needed after a write to | |
2243 | * WORD_SWAP before its contents are valid */ | |
2244 | byte_test = smsc911x_reg_read(pdata, BYTE_TEST); | |
2245 | ||
2246 | byte_test = smsc911x_reg_read(pdata, BYTE_TEST); | |
2247 | } | |
2248 | ||
2249 | if (byte_test != 0x87654321) { | |
dffc6b24 | 2250 | SMSC_WARN(pdata, drv, "BYTE_TEST: 0x%08X", byte_test); |
fd9abb3d | 2251 | if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) { |
dffc6b24 JP |
2252 | SMSC_WARN(pdata, probe, |
2253 | "top 16 bits equal to bottom 16 bits"); | |
2254 | SMSC_TRACE(pdata, probe, | |
2255 | "This may mean the chip is set " | |
2256 | "for 32 bit while the bus is reading 16 bit"); | |
fd9abb3d SG |
2257 | } |
2258 | return -ENODEV; | |
2259 | } | |
2260 | ||
2261 | /* Default generation to zero (all workarounds apply) */ | |
2262 | pdata->generation = 0; | |
2263 | ||
2264 | pdata->idrev = smsc911x_reg_read(pdata, ID_REV); | |
2265 | switch (pdata->idrev & 0xFFFF0000) { | |
f6fec61e DC |
2266 | case LAN9118: |
2267 | case LAN9117: | |
2268 | case LAN9116: | |
2269 | case LAN9115: | |
2270 | case LAN89218: | |
fd9abb3d SG |
2271 | /* LAN911[5678] family */ |
2272 | pdata->generation = pdata->idrev & 0x0000FFFF; | |
2273 | break; | |
2274 | ||
f6fec61e DC |
2275 | case LAN9218: |
2276 | case LAN9217: | |
2277 | case LAN9216: | |
2278 | case LAN9215: | |
fd9abb3d SG |
2279 | /* LAN921[5678] family */ |
2280 | pdata->generation = 3; | |
2281 | break; | |
2282 | ||
f6fec61e DC |
2283 | case LAN9210: |
2284 | case LAN9211: | |
2285 | case LAN9220: | |
2286 | case LAN9221: | |
2287 | case LAN9250: | |
2288 | /* LAN9210/LAN9211/LAN9220/LAN9221/LAN9250 */ | |
fd9abb3d SG |
2289 | pdata->generation = 4; |
2290 | break; | |
2291 | ||
2292 | default: | |
dffc6b24 JP |
2293 | SMSC_WARN(pdata, probe, "LAN911x not identified, idrev: 0x%08X", |
2294 | pdata->idrev); | |
fd9abb3d SG |
2295 | return -ENODEV; |
2296 | } | |
2297 | ||
dffc6b24 JP |
2298 | SMSC_TRACE(pdata, probe, |
2299 | "LAN911x identified, idrev: 0x%08X, generation: %d", | |
2300 | pdata->idrev, pdata->generation); | |
fd9abb3d SG |
2301 | |
2302 | if (pdata->generation == 0) | |
dffc6b24 JP |
2303 | SMSC_WARN(pdata, probe, |
2304 | "This driver is not intended for this chip revision"); | |
fd9abb3d | 2305 | |
31f45747 SG |
2306 | /* workaround for platforms without an eeprom, where the mac address |
2307 | * is stored elsewhere and set by the bootloader. This saves the | |
2308 | * mac address before resetting the device */ | |
35a67edf EBS |
2309 | if (pdata->config.flags & SMSC911X_SAVE_MAC_ADDRESS) { |
2310 | spin_lock_irq(&pdata->mac_lock); | |
31f45747 | 2311 | smsc911x_read_mac_address(dev); |
35a67edf EBS |
2312 | spin_unlock_irq(&pdata->mac_lock); |
2313 | } | |
31f45747 | 2314 | |
fd9abb3d | 2315 | /* Reset the LAN911x */ |
cd998ecd | 2316 | if (smsc911x_phy_reset(pdata) || smsc911x_soft_reset(pdata)) |
fd9abb3d SG |
2317 | return -ENODEV; |
2318 | ||
fd9abb3d | 2319 | dev->flags |= IFF_MULTICAST; |
fd9abb3d | 2320 | netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT); |
631b7568 | 2321 | dev->netdev_ops = &smsc911x_netdev_ops; |
fd9abb3d SG |
2322 | dev->ethtool_ops = &smsc911x_ethtool_ops; |
2323 | ||
fd9abb3d SG |
2324 | return 0; |
2325 | } | |
2326 | ||
8489ec1f | 2327 | static int smsc911x_drv_remove(struct platform_device *pdev) |
fd9abb3d SG |
2328 | { |
2329 | struct net_device *dev; | |
2330 | struct smsc911x_data *pdata; | |
2331 | struct resource *res; | |
2332 | ||
2333 | dev = platform_get_drvdata(pdev); | |
2334 | BUG_ON(!dev); | |
2335 | pdata = netdev_priv(dev); | |
2336 | BUG_ON(!pdata); | |
2337 | BUG_ON(!pdata->ioaddr); | |
fd9abb3d | 2338 | |
dffc6b24 | 2339 | SMSC_TRACE(pdata, ifdown, "Stopping driver"); |
fd9abb3d | 2340 | |
e06513d7 JL |
2341 | unregister_netdev(dev); |
2342 | ||
fd9abb3d SG |
2343 | mdiobus_unregister(pdata->mii_bus); |
2344 | mdiobus_free(pdata->mii_bus); | |
2345 | ||
fd9abb3d SG |
2346 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
2347 | "smsc911x-memory"); | |
2348 | if (!res) | |
d4522739 | 2349 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
fd9abb3d | 2350 | |
39424539 | 2351 | release_mem_region(res->start, resource_size(res)); |
fd9abb3d SG |
2352 | |
2353 | iounmap(pdata->ioaddr); | |
2354 | ||
c7e963f6 RM |
2355 | (void)smsc911x_disable_resources(pdev); |
2356 | smsc911x_free_resources(pdev); | |
2357 | ||
fd9abb3d SG |
2358 | free_netdev(dev); |
2359 | ||
3a611e26 GU |
2360 | pm_runtime_put(&pdev->dev); |
2361 | pm_runtime_disable(&pdev->dev); | |
2362 | ||
fd9abb3d SG |
2363 | return 0; |
2364 | } | |
2365 | ||
c326de88 MP |
2366 | /* standard register acces */ |
2367 | static const struct smsc911x_ops standard_smsc911x_ops = { | |
2368 | .reg_read = __smsc911x_reg_read, | |
2369 | .reg_write = __smsc911x_reg_write, | |
2370 | .rx_readfifo = smsc911x_rx_readfifo, | |
2371 | .tx_writefifo = smsc911x_tx_writefifo, | |
2372 | }; | |
2373 | ||
2374 | /* shifted register access */ | |
2375 | static const struct smsc911x_ops shifted_smsc911x_ops = { | |
2376 | .reg_read = __smsc911x_reg_read_shift, | |
2377 | .reg_write = __smsc911x_reg_write_shift, | |
2378 | .rx_readfifo = smsc911x_rx_readfifo_shift, | |
2379 | .tx_writefifo = smsc911x_tx_writefifo_shift, | |
2380 | }; | |
2381 | ||
0b50dc4f JL |
2382 | static int smsc911x_probe_config(struct smsc911x_platform_config *config, |
2383 | struct device *dev) | |
79f88ee9 | 2384 | { |
62ee783b | 2385 | int phy_interface; |
79f88ee9 | 2386 | u32 width = 0; |
31cb5c9e | 2387 | int err; |
79f88ee9 | 2388 | |
62ee783b GR |
2389 | phy_interface = device_get_phy_mode(dev); |
2390 | if (phy_interface < 0) | |
31cb5c9e | 2391 | phy_interface = PHY_INTERFACE_MODE_NA; |
62ee783b | 2392 | config->phy_interface = phy_interface; |
79f88ee9 | 2393 | |
0b50dc4f | 2394 | device_get_mac_address(dev, config->mac, ETH_ALEN); |
79f88ee9 | 2395 | |
31cb5c9e GR |
2396 | err = device_property_read_u32(dev, "reg-io-width", &width); |
2397 | if (err == -ENXIO) | |
2398 | return err; | |
2399 | if (!err && width == 4) | |
79f88ee9 | 2400 | config->flags |= SMSC911X_USE_32BIT; |
f26cd41a DM |
2401 | else |
2402 | config->flags |= SMSC911X_USE_16BIT; | |
79f88ee9 | 2403 | |
31cb5c9e GR |
2404 | device_property_read_u32(dev, "reg-shift", &config->shift); |
2405 | ||
0b50dc4f | 2406 | if (device_property_present(dev, "smsc,irq-active-high")) |
79f88ee9 SG |
2407 | config->irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH; |
2408 | ||
0b50dc4f | 2409 | if (device_property_present(dev, "smsc,irq-push-pull")) |
79f88ee9 SG |
2410 | config->irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL; |
2411 | ||
0b50dc4f | 2412 | if (device_property_present(dev, "smsc,force-internal-phy")) |
79f88ee9 SG |
2413 | config->flags |= SMSC911X_FORCE_INTERNAL_PHY; |
2414 | ||
0b50dc4f | 2415 | if (device_property_present(dev, "smsc,force-external-phy")) |
79f88ee9 SG |
2416 | config->flags |= SMSC911X_FORCE_EXTERNAL_PHY; |
2417 | ||
0b50dc4f | 2418 | if (device_property_present(dev, "smsc,save-mac-address")) |
79f88ee9 SG |
2419 | config->flags |= SMSC911X_SAVE_MAC_ADDRESS; |
2420 | ||
2421 | return 0; | |
2422 | } | |
79f88ee9 | 2423 | |
8489ec1f | 2424 | static int smsc911x_drv_probe(struct platform_device *pdev) |
fd9abb3d SG |
2425 | { |
2426 | struct net_device *dev; | |
2427 | struct smsc911x_data *pdata; | |
495c765d | 2428 | struct smsc911x_platform_config *config = dev_get_platdata(&pdev->dev); |
965b2aa7 | 2429 | struct resource *res; |
f252974e | 2430 | int res_size, irq; |
fd9abb3d | 2431 | int retval; |
fd9abb3d | 2432 | |
fd9abb3d SG |
2433 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
2434 | "smsc911x-memory"); | |
2435 | if (!res) | |
2436 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2437 | if (!res) { | |
dffc6b24 | 2438 | pr_warn("Could not allocate resource\n"); |
fd9abb3d SG |
2439 | retval = -ENODEV; |
2440 | goto out_0; | |
2441 | } | |
39424539 | 2442 | res_size = resource_size(res); |
fd9abb3d | 2443 | |
965b2aa7 | 2444 | irq = platform_get_irq(pdev, 0); |
f892a84c TL |
2445 | if (irq == -EPROBE_DEFER) { |
2446 | retval = -EPROBE_DEFER; | |
2447 | goto out_0; | |
2448 | } else if (irq <= 0) { | |
dffc6b24 | 2449 | pr_warn("Could not allocate irq resource\n"); |
61307ed8 SG |
2450 | retval = -ENODEV; |
2451 | goto out_0; | |
2452 | } | |
2453 | ||
fd9abb3d SG |
2454 | if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) { |
2455 | retval = -EBUSY; | |
2456 | goto out_0; | |
2457 | } | |
2458 | ||
2459 | dev = alloc_etherdev(sizeof(struct smsc911x_data)); | |
2460 | if (!dev) { | |
fd9abb3d SG |
2461 | retval = -ENOMEM; |
2462 | goto out_release_io_1; | |
2463 | } | |
2464 | ||
2465 | SET_NETDEV_DEV(dev, &pdev->dev); | |
2466 | ||
2467 | pdata = netdev_priv(dev); | |
965b2aa7 | 2468 | dev->irq = irq; |
fd9abb3d | 2469 | pdata->ioaddr = ioremap_nocache(res->start, res_size); |
57fe1479 AK |
2470 | if (!pdata->ioaddr) { |
2471 | retval = -ENOMEM; | |
2472 | goto out_ioremap_fail; | |
2473 | } | |
fd9abb3d | 2474 | |
fd9abb3d SG |
2475 | pdata->dev = dev; |
2476 | pdata->msg_enable = ((1 << debug) - 1); | |
2477 | ||
c7e963f6 RM |
2478 | platform_set_drvdata(pdev, dev); |
2479 | ||
2480 | retval = smsc911x_request_resources(pdev); | |
2481 | if (retval) | |
2e1d4a06 | 2482 | goto out_request_resources_fail; |
c7e963f6 RM |
2483 | |
2484 | retval = smsc911x_enable_resources(pdev); | |
2485 | if (retval) | |
2e1d4a06 | 2486 | goto out_enable_resources_fail; |
c7e963f6 | 2487 | |
fd9abb3d | 2488 | if (pdata->ioaddr == NULL) { |
dffc6b24 | 2489 | SMSC_WARN(pdata, probe, "Error smsc911x base address invalid"); |
fd9abb3d | 2490 | retval = -ENOMEM; |
c7e963f6 | 2491 | goto out_disable_resources; |
fd9abb3d SG |
2492 | } |
2493 | ||
0b50dc4f | 2494 | retval = smsc911x_probe_config(&pdata->config, &pdev->dev); |
79f88ee9 SG |
2495 | if (retval && config) { |
2496 | /* copy config parameters across to pdata */ | |
2497 | memcpy(&pdata->config, config, sizeof(pdata->config)); | |
2498 | retval = 0; | |
2499 | } | |
2500 | ||
2501 | if (retval) { | |
2502 | SMSC_WARN(pdata, probe, "Error smsc911x config not found"); | |
c7e963f6 | 2503 | goto out_disable_resources; |
79f88ee9 SG |
2504 | } |
2505 | ||
c326de88 MP |
2506 | /* assume standard, non-shifted, access to HW registers */ |
2507 | pdata->ops = &standard_smsc911x_ops; | |
2508 | /* apply the right access if shifting is needed */ | |
79f88ee9 | 2509 | if (pdata->config.shift) |
c326de88 MP |
2510 | pdata->ops = &shifted_smsc911x_ops; |
2511 | ||
3a611e26 GU |
2512 | pm_runtime_enable(&pdev->dev); |
2513 | pm_runtime_get_sync(&pdev->dev); | |
2514 | ||
fd9abb3d SG |
2515 | retval = smsc911x_init(dev); |
2516 | if (retval < 0) | |
c7e963f6 | 2517 | goto out_disable_resources; |
fd9abb3d | 2518 | |
31f6f291 | 2519 | netif_carrier_off(dev); |
fd9abb3d | 2520 | |
aea95dd5 | 2521 | retval = smsc911x_mii_init(pdev, dev); |
fd9abb3d | 2522 | if (retval) { |
aea95dd5 | 2523 | SMSC_WARN(pdata, probe, "Error %i initialising mii", retval); |
163faf31 | 2524 | goto out_disable_resources; |
fd9abb3d SG |
2525 | } |
2526 | ||
fd9abb3d SG |
2527 | retval = register_netdev(dev); |
2528 | if (retval) { | |
dffc6b24 | 2529 | SMSC_WARN(pdata, probe, "Error %i registering device", retval); |
f252974e | 2530 | goto out_disable_resources; |
fd9abb3d | 2531 | } else { |
dffc6b24 JP |
2532 | SMSC_TRACE(pdata, probe, |
2533 | "Network interface: \"%s\"", dev->name); | |
fd9abb3d SG |
2534 | } |
2535 | ||
fd9abb3d SG |
2536 | spin_lock_irq(&pdata->mac_lock); |
2537 | ||
2538 | /* Check if mac address has been specified when bringing interface up */ | |
2539 | if (is_valid_ether_addr(dev->dev_addr)) { | |
225ddf49 | 2540 | smsc911x_set_hw_mac_address(pdata, dev->dev_addr); |
dffc6b24 JP |
2541 | SMSC_TRACE(pdata, probe, |
2542 | "MAC Address is specified by configuration"); | |
aace4959 | 2543 | } else if (is_valid_ether_addr(pdata->config.mac)) { |
d458cdf7 | 2544 | memcpy(dev->dev_addr, pdata->config.mac, ETH_ALEN); |
dffc6b24 JP |
2545 | SMSC_TRACE(pdata, probe, |
2546 | "MAC Address specified by platform data"); | |
fd9abb3d SG |
2547 | } else { |
2548 | /* Try reading mac address from device. if EEPROM is present | |
2549 | * it will already have been set */ | |
62747cd2 | 2550 | smsc_get_mac(dev); |
fd9abb3d SG |
2551 | |
2552 | if (is_valid_ether_addr(dev->dev_addr)) { | |
2553 | /* eeprom values are valid so use them */ | |
dffc6b24 JP |
2554 | SMSC_TRACE(pdata, probe, |
2555 | "Mac Address is read from LAN911x EEPROM"); | |
fd9abb3d SG |
2556 | } else { |
2557 | /* eeprom values are invalid, generate random MAC */ | |
7ce5d222 | 2558 | eth_hw_addr_random(dev); |
225ddf49 | 2559 | smsc911x_set_hw_mac_address(pdata, dev->dev_addr); |
dffc6b24 | 2560 | SMSC_TRACE(pdata, probe, |
7efd26d0 | 2561 | "MAC Address is set to eth_random_addr"); |
fd9abb3d SG |
2562 | } |
2563 | } | |
2564 | ||
2565 | spin_unlock_irq(&pdata->mac_lock); | |
2566 | ||
dffc6b24 | 2567 | netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr); |
fd9abb3d SG |
2568 | |
2569 | return 0; | |
2570 | ||
c7e963f6 | 2571 | out_disable_resources: |
3a611e26 GU |
2572 | pm_runtime_put(&pdev->dev); |
2573 | pm_runtime_disable(&pdev->dev); | |
c7e963f6 | 2574 | (void)smsc911x_disable_resources(pdev); |
2e1d4a06 | 2575 | out_enable_resources_fail: |
c7e963f6 | 2576 | smsc911x_free_resources(pdev); |
2e1d4a06 | 2577 | out_request_resources_fail: |
fd9abb3d | 2578 | iounmap(pdata->ioaddr); |
57fe1479 | 2579 | out_ioremap_fail: |
fd9abb3d SG |
2580 | free_netdev(dev); |
2581 | out_release_io_1: | |
39424539 | 2582 | release_mem_region(res->start, resource_size(res)); |
fd9abb3d SG |
2583 | out_0: |
2584 | return retval; | |
2585 | } | |
2586 | ||
b6907b0c DM |
2587 | #ifdef CONFIG_PM |
2588 | /* This implementation assumes the devices remains powered on its VDDVARIO | |
2589 | * pins during suspend. */ | |
2590 | ||
6cb87823 DM |
2591 | /* TODO: implement freeze/thaw callbacks for hibernation.*/ |
2592 | ||
2593 | static int smsc911x_suspend(struct device *dev) | |
b6907b0c | 2594 | { |
6cb87823 DM |
2595 | struct net_device *ndev = dev_get_drvdata(dev); |
2596 | struct smsc911x_data *pdata = netdev_priv(ndev); | |
b6907b0c | 2597 | |
2aa70f86 GU |
2598 | if (netif_running(ndev)) { |
2599 | netif_stop_queue(ndev); | |
2600 | netif_device_detach(ndev); | |
2601 | } | |
2602 | ||
b6907b0c DM |
2603 | /* enable wake on LAN, energy detection and the external PME |
2604 | * signal. */ | |
2605 | smsc911x_reg_write(pdata, PMT_CTRL, | |
2606 | PMT_CTRL_PM_MODE_D1_ | PMT_CTRL_WOL_EN_ | | |
2607 | PMT_CTRL_ED_EN_ | PMT_CTRL_PME_EN_); | |
2608 | ||
88128729 UH |
2609 | pm_runtime_disable(dev); |
2610 | pm_runtime_set_suspended(dev); | |
2611 | ||
b6907b0c DM |
2612 | return 0; |
2613 | } | |
2614 | ||
6cb87823 | 2615 | static int smsc911x_resume(struct device *dev) |
b6907b0c | 2616 | { |
6cb87823 DM |
2617 | struct net_device *ndev = dev_get_drvdata(dev); |
2618 | struct smsc911x_data *pdata = netdev_priv(ndev); | |
b6907b0c DM |
2619 | unsigned int to = 100; |
2620 | ||
88128729 UH |
2621 | pm_runtime_enable(dev); |
2622 | pm_runtime_resume(dev); | |
2623 | ||
b6907b0c DM |
2624 | /* Note 3.11 from the datasheet: |
2625 | * "When the LAN9220 is in a power saving state, a write of any | |
2626 | * data to the BYTE_TEST register will wake-up the device." | |
2627 | */ | |
2628 | smsc911x_reg_write(pdata, BYTE_TEST, 0); | |
2629 | ||
2630 | /* poll the READY bit in PMT_CTRL. Any other access to the device is | |
2631 | * forbidden while this bit isn't set. Try for 100ms and return -EIO | |
2632 | * if it failed. */ | |
2633 | while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to) | |
2634 | udelay(1000); | |
2635 | ||
2aa70f86 GU |
2636 | if (to == 0) |
2637 | return -EIO; | |
2638 | ||
2639 | if (netif_running(ndev)) { | |
2640 | netif_device_attach(ndev); | |
2641 | netif_start_queue(ndev); | |
2642 | } | |
2643 | ||
2644 | return 0; | |
b6907b0c DM |
2645 | } |
2646 | ||
47145210 | 2647 | static const struct dev_pm_ops smsc911x_pm_ops = { |
6cb87823 DM |
2648 | .suspend = smsc911x_suspend, |
2649 | .resume = smsc911x_resume, | |
2650 | }; | |
2651 | ||
2652 | #define SMSC911X_PM_OPS (&smsc911x_pm_ops) | |
2653 | ||
b6907b0c | 2654 | #else |
6cb87823 | 2655 | #define SMSC911X_PM_OPS NULL |
b6907b0c DM |
2656 | #endif |
2657 | ||
d62fdf8b | 2658 | #ifdef CONFIG_OF |
79f88ee9 SG |
2659 | static const struct of_device_id smsc911x_dt_ids[] = { |
2660 | { .compatible = "smsc,lan9115", }, | |
2661 | { /* sentinel */ } | |
2662 | }; | |
2663 | MODULE_DEVICE_TABLE(of, smsc911x_dt_ids); | |
d62fdf8b | 2664 | #endif |
79f88ee9 | 2665 | |
0b50dc4f JL |
2666 | static const struct acpi_device_id smsc911x_acpi_match[] = { |
2667 | { "ARMH9118", 0 }, | |
2668 | { } | |
2669 | }; | |
2670 | MODULE_DEVICE_TABLE(acpi, smsc911x_acpi_match); | |
2671 | ||
fd9abb3d SG |
2672 | static struct platform_driver smsc911x_driver = { |
2673 | .probe = smsc911x_drv_probe, | |
8489ec1f | 2674 | .remove = smsc911x_drv_remove, |
fd9abb3d | 2675 | .driver = { |
6cb87823 | 2676 | .name = SMSC_CHIPNAME, |
6cb87823 | 2677 | .pm = SMSC911X_PM_OPS, |
d62fdf8b | 2678 | .of_match_table = of_match_ptr(smsc911x_dt_ids), |
0b50dc4f | 2679 | .acpi_match_table = ACPI_PTR(smsc911x_acpi_match), |
fd9abb3d SG |
2680 | }, |
2681 | }; | |
2682 | ||
2683 | /* Entry point for loading the module */ | |
2684 | static int __init smsc911x_init_module(void) | |
2685 | { | |
62747cd2 | 2686 | SMSC_INITIALIZE(); |
fd9abb3d SG |
2687 | return platform_driver_register(&smsc911x_driver); |
2688 | } | |
2689 | ||
2690 | /* entry point for unloading the module */ | |
2691 | static void __exit smsc911x_cleanup_module(void) | |
2692 | { | |
2693 | platform_driver_unregister(&smsc911x_driver); | |
2694 | } | |
2695 | ||
2696 | module_init(smsc911x_init_module); | |
2697 | module_exit(smsc911x_cleanup_module); |