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can: sja1000_isa: convert to platform driver to support x86_64 systems
[linux-2.6-block.git] / drivers / net / ethernet / smsc / smsc911x.c
CommitLineData
fd9abb3d
SG		 1/***************************************************************************
2 *
3 * Copyright (C) 2004-2008 SMSC
4 * Copyright (C) 2005-2008 ARM
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 *
20 ***************************************************************************
21 * Rewritten, heavily based on smsc911x simple driver by SMSC.
22 * Partly uses io macros from smc91x.c by Nicolas Pitre
23 *
24 * Supported devices:
25 * LAN9115, LAN9116, LAN9117, LAN9118
26 * LAN9215, LAN9216, LAN9217, LAN9218
27 * LAN9210, LAN9211
28 * LAN9220, LAN9221
28c21379 29 * LAN89218
fd9abb3d
SG		 30 *
31 */
32
dffc6b24
JP		 33#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
fd9abb3d
SG		 35#include <linux/crc32.h>
36#include <linux/delay.h>
37#include <linux/errno.h>
38#include <linux/etherdevice.h>
39#include <linux/ethtool.h>
40#include <linux/init.h>
a6b7a407 41#include <linux/interrupt.h>
fd9abb3d
SG		 42#include <linux/ioport.h>
43#include <linux/kernel.h>
44#include <linux/module.h>
45#include <linux/netdevice.h>
46#include <linux/platform_device.h>
47#include <linux/sched.h>
fd9abb3d 48#include <linux/timer.h>
fd9abb3d
SG		 49#include <linux/bug.h>
50#include <linux/bitops.h>
51#include <linux/irq.h>
52#include <linux/io.h>
833cc67c 53#include <linux/swab.h>
fd9abb3d
SG		 54#include <linux/phy.h>
55#include <linux/smsc911x.h>
6cb87823 56#include <linux/device.h>
79f88ee9
SG		 57#include <linux/of.h>
58#include <linux/of_device.h>
59#include <linux/of_gpio.h>
60#include <linux/of_net.h>
fd9abb3d
SG		 61#include "smsc911x.h"
62
63#define SMSC_CHIPNAME "smsc911x"
64#define SMSC_MDIONAME "smsc911x-mdio"
65#define SMSC_DRV_VERSION "2008-10-21"
66
67MODULE_LICENSE("GPL");
68MODULE_VERSION(SMSC_DRV_VERSION);
62038e4a 69MODULE_ALIAS("platform:smsc911x");
fd9abb3d
SG		 70
71#if USE_DEBUG > 0
72static int debug = 16;
73#else
74static int debug = 3;
75#endif
76
77module_param(debug, int, 0);
78MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
79
c326de88
MP		 80struct smsc911x_data;
81
82struct smsc911x_ops {
83 u32 (*reg_read)(struct smsc911x_data *pdata, u32 reg);
84 void (*reg_write)(struct smsc911x_data *pdata, u32 reg, u32 val);
85 void (*rx_readfifo)(struct smsc911x_data *pdata,
86 unsigned int *buf, unsigned int wordcount);
87 void (*tx_writefifo)(struct smsc911x_data *pdata,
88 unsigned int *buf, unsigned int wordcount);
89};
90
fd9abb3d
SG		 91struct smsc911x_data {
92 void __iomem *ioaddr;
93
94 unsigned int idrev;
95
96 /* used to decide which workarounds apply */
97 unsigned int generation;
98
99 /* device configuration (copied from platform_data during probe) */
2107fb8b 100 struct smsc911x_platform_config config;
fd9abb3d
SG		 101
102 /* This needs to be acquired before calling any of below:
103 * smsc911x_mac_read(), smsc911x_mac_write()
104 */
105 spinlock_t mac_lock;
106
492c5d94 107 /* spinlock to ensure register accesses are serialised */
fd9abb3d 108 spinlock_t dev_lock;
fd9abb3d
SG		 109
110 struct phy_device *phy_dev;
111 struct mii_bus *mii_bus;
112 int phy_irq[PHY_MAX_ADDR];
113 unsigned int using_extphy;
114 int last_duplex;
115 int last_carrier;
116
117 u32 msg_enable;
118 unsigned int gpio_setting;
119 unsigned int gpio_orig_setting;
120 struct net_device *dev;
121 struct napi_struct napi;
122
123 unsigned int software_irq_signal;
124
125#ifdef USE_PHY_WORK_AROUND
126#define MIN_PACKET_SIZE (64)
127 char loopback_tx_pkt[MIN_PACKET_SIZE];
128 char loopback_rx_pkt[MIN_PACKET_SIZE];
129 unsigned int resetcount;
130#endif
131
132 /* Members for Multicast filter workaround */
133 unsigned int multicast_update_pending;
134 unsigned int set_bits_mask;
135 unsigned int clear_bits_mask;
136 unsigned int hashhi;
137 unsigned int hashlo;
c326de88
MP		 138
139 /* register access functions */
140 const struct smsc911x_ops *ops;
fd9abb3d
SG		 141};
142
c326de88
MP		 143/* Easy access to information */
144#define __smsc_shift(pdata, reg) ((reg) << ((pdata)->config.shift))
145
492c5d94 146static inline u32 __smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
fd9abb3d 147{
2107fb8b
SG		 148 if (pdata->config.flags & SMSC911X_USE_32BIT)
149 return readl(pdata->ioaddr + reg);
150
492c5d94
CM		 151 if (pdata->config.flags & SMSC911X_USE_16BIT)
152 return ((readw(pdata->ioaddr + reg) & 0xFFFF) |
2107fb8b 153 ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16));
fd9abb3d 154
2107fb8b 155 BUG();
702403af 156 return 0;
fd9abb3d
SG		 157}
158
c326de88
MP		 159static inline u32
160__smsc911x_reg_read_shift(struct smsc911x_data *pdata, u32 reg)
161{
162 if (pdata->config.flags & SMSC911X_USE_32BIT)
163 return readl(pdata->ioaddr + __smsc_shift(pdata, reg));
164
165 if (pdata->config.flags & SMSC911X_USE_16BIT)
166 return (readw(pdata->ioaddr +
167 __smsc_shift(pdata, reg)) & 0xFFFF) |
168 ((readw(pdata->ioaddr +
169 __smsc_shift(pdata, reg + 2)) & 0xFFFF) << 16);
170
171 BUG();
172 return 0;
173}
174
492c5d94
CM		 175static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
176{
177 u32 data;
178 unsigned long flags;
179
180 spin_lock_irqsave(&pdata->dev_lock, flags);
c326de88 181 data = pdata->ops->reg_read(pdata, reg);
492c5d94
CM		 182 spin_unlock_irqrestore(&pdata->dev_lock, flags);
183
184 return data;
185}
186
187static inline void __smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
188 u32 val)
fd9abb3d 189{
2107fb8b
SG		 190 if (pdata->config.flags & SMSC911X_USE_32BIT) {
191 writel(val, pdata->ioaddr + reg);
192 return;
193 }
194
195 if (pdata->config.flags & SMSC911X_USE_16BIT) {
2107fb8b
SG		 196 writew(val & 0xFFFF, pdata->ioaddr + reg);
197 writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2);
2107fb8b
SG		 198 return;
199 }
fd9abb3d 200
2107fb8b 201 BUG();
fd9abb3d
SG		 202}
203
c326de88
MP		 204static inline void
205__smsc911x_reg_write_shift(struct smsc911x_data *pdata, u32 reg, u32 val)
206{
207 if (pdata->config.flags & SMSC911X_USE_32BIT) {
208 writel(val, pdata->ioaddr + __smsc_shift(pdata, reg));
209 return;
210 }
211
212 if (pdata->config.flags & SMSC911X_USE_16BIT) {
213 writew(val & 0xFFFF,
214 pdata->ioaddr + __smsc_shift(pdata, reg));
215 writew((val >> 16) & 0xFFFF,
216 pdata->ioaddr + __smsc_shift(pdata, reg + 2));
217 return;
218 }
219
220 BUG();
221}
222
492c5d94
CM		 223static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
224 u32 val)
225{
226 unsigned long flags;
227
228 spin_lock_irqsave(&pdata->dev_lock, flags);
c326de88 229 pdata->ops->reg_write(pdata, reg, val);
492c5d94
CM		 230 spin_unlock_irqrestore(&pdata->dev_lock, flags);
231}
232
fd9abb3d
SG		 233/* Writes a packet to the TX_DATA_FIFO */
234static inline void
235smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf,
236 unsigned int wordcount)
237{
492c5d94
CM		 238 unsigned long flags;
239
240 spin_lock_irqsave(&pdata->dev_lock, flags);
241
833cc67c
MD		 242 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
243 while (wordcount--)
492c5d94
CM		 244 __smsc911x_reg_write(pdata, TX_DATA_FIFO,
245 swab32(*buf++));
246 goto out;
833cc67c
MD		 247 }
248
2107fb8b
SG		 249 if (pdata->config.flags & SMSC911X_USE_32BIT) {
250 writesl(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount);
492c5d94 251 goto out;
2107fb8b
SG		 252 }
253
254 if (pdata->config.flags & SMSC911X_USE_16BIT) {
255 while (wordcount--)
492c5d94
CM		 256 __smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++);
257 goto out;
2107fb8b
SG		 258 }
259
260 BUG();
492c5d94
CM		 261out:
262 spin_unlock_irqrestore(&pdata->dev_lock, flags);
fd9abb3d
SG		 263}
264
c326de88
MP		 265/* Writes a packet to the TX_DATA_FIFO - shifted version */
266static inline void
267smsc911x_tx_writefifo_shift(struct smsc911x_data *pdata, unsigned int *buf,
268 unsigned int wordcount)
269{
270 unsigned long flags;
271
272 spin_lock_irqsave(&pdata->dev_lock, flags);
273
274 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
275 while (wordcount--)
276 __smsc911x_reg_write_shift(pdata, TX_DATA_FIFO,
277 swab32(*buf++));
278 goto out;
279 }
280
281 if (pdata->config.flags & SMSC911X_USE_32BIT) {
282 writesl(pdata->ioaddr + __smsc_shift(pdata,
283 TX_DATA_FIFO), buf, wordcount);
284 goto out;
285 }
286
287 if (pdata->config.flags & SMSC911X_USE_16BIT) {
288 while (wordcount--)
289 __smsc911x_reg_write_shift(pdata,
290 TX_DATA_FIFO, *buf++);
291 goto out;
292 }
293
294 BUG();
295out:
296 spin_unlock_irqrestore(&pdata->dev_lock, flags);
297}
298
fd9abb3d
SG		 299/* Reads a packet out of the RX_DATA_FIFO */
300static inline void
301smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf,
302 unsigned int wordcount)
303{
492c5d94
CM		 304 unsigned long flags;
305
306 spin_lock_irqsave(&pdata->dev_lock, flags);
307
833cc67c
MD		 308 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
309 while (wordcount--)
492c5d94
CM		 310 *buf++ = swab32(__smsc911x_reg_read(pdata,
311 RX_DATA_FIFO));
312 goto out;
833cc67c
MD		 313 }
314
2107fb8b
SG		 315 if (pdata->config.flags & SMSC911X_USE_32BIT) {
316 readsl(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount);
492c5d94 317 goto out;
2107fb8b 318 }
fd9abb3d 319
2107fb8b
SG		 320 if (pdata->config.flags & SMSC911X_USE_16BIT) {
321 while (wordcount--)
492c5d94
CM		 322 *buf++ = __smsc911x_reg_read(pdata, RX_DATA_FIFO);
323 goto out;
2107fb8b
SG		 324 }
325
326 BUG();
492c5d94
CM		 327out:
328 spin_unlock_irqrestore(&pdata->dev_lock, flags);
2107fb8b 329}
fd9abb3d 330
c326de88
MP		 331/* Reads a packet out of the RX_DATA_FIFO - shifted version */
332static inline void
333smsc911x_rx_readfifo_shift(struct smsc911x_data *pdata, unsigned int *buf,
334 unsigned int wordcount)
335{
336 unsigned long flags;
337
338 spin_lock_irqsave(&pdata->dev_lock, flags);
339
340 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
341 while (wordcount--)
342 *buf++ = swab32(__smsc911x_reg_read_shift(pdata,
343 RX_DATA_FIFO));
344 goto out;
345 }
346
347 if (pdata->config.flags & SMSC911X_USE_32BIT) {
348 readsl(pdata->ioaddr + __smsc_shift(pdata,
349 RX_DATA_FIFO), buf, wordcount);
350 goto out;
351 }
352
353 if (pdata->config.flags & SMSC911X_USE_16BIT) {
354 while (wordcount--)
355 *buf++ = __smsc911x_reg_read_shift(pdata,
356 RX_DATA_FIFO);
357 goto out;
358 }
359
360 BUG();
361out:
362 spin_unlock_irqrestore(&pdata->dev_lock, flags);
363}
364
fd9abb3d
SG		 365/* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read
366 * and smsc911x_mac_write, so assumes mac_lock is held */
367static int smsc911x_mac_complete(struct smsc911x_data *pdata)
368{
369 int i;
370 u32 val;
371
372 SMSC_ASSERT_MAC_LOCK(pdata);
373
374 for (i = 0; i < 40; i++) {
375 val = smsc911x_reg_read(pdata, MAC_CSR_CMD);
376 if (!(val & MAC_CSR_CMD_CSR_BUSY_))
377 return 0;
378 }
dffc6b24
JP		 379 SMSC_WARN(pdata, hw, "Timed out waiting for MAC not BUSY. "
380 "MAC_CSR_CMD: 0x%08X", val);
fd9abb3d
SG		 381 return -EIO;
382}
383
384/* Fetches a MAC register value. Assumes mac_lock is acquired */
385static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset)
386{
387 unsigned int temp;
388
389 SMSC_ASSERT_MAC_LOCK(pdata);
390
391 temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
392 if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
dffc6b24 393 SMSC_WARN(pdata, hw, "MAC busy at entry");
fd9abb3d
SG		 394 return 0xFFFFFFFF;
395 }
396
397 /* Send the MAC cmd */
398 smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
399 MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_));
400
401 /* Workaround for hardware read-after-write restriction */
402 temp = smsc911x_reg_read(pdata, BYTE_TEST);
403
404 /* Wait for the read to complete */
405 if (likely(smsc911x_mac_complete(pdata) == 0))
406 return smsc911x_reg_read(pdata, MAC_CSR_DATA);
407
dffc6b24 408 SMSC_WARN(pdata, hw, "MAC busy after read");
fd9abb3d
SG		 409 return 0xFFFFFFFF;
410}
411
412/* Set a mac register, mac_lock must be acquired before calling */
413static void smsc911x_mac_write(struct smsc911x_data *pdata,
414 unsigned int offset, u32 val)
415{
416 unsigned int temp;
417
418 SMSC_ASSERT_MAC_LOCK(pdata);
419
420 temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
421 if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
dffc6b24
JP		 422 SMSC_WARN(pdata, hw,
423 "smsc911x_mac_write failed, MAC busy at entry");
fd9abb3d
SG		 424 return;
425 }
426
427 /* Send data to write */
428 smsc911x_reg_write(pdata, MAC_CSR_DATA, val);
429
430 /* Write the actual data */
431 smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
432 MAC_CSR_CMD_CSR_BUSY_));
433
434 /* Workaround for hardware read-after-write restriction */
435 temp = smsc911x_reg_read(pdata, BYTE_TEST);
436
437 /* Wait for the write to complete */
438 if (likely(smsc911x_mac_complete(pdata) == 0))
439 return;
440
dffc6b24 441 SMSC_WARN(pdata, hw, "smsc911x_mac_write failed, MAC busy after write");
fd9abb3d
SG		 442}
443
444/* Get a phy register */
445static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
446{
447 struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
448 unsigned long flags;
449 unsigned int addr;
450 int i, reg;
451
452 spin_lock_irqsave(&pdata->mac_lock, flags);
453
454 /* Confirm MII not busy */
455 if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
dffc6b24 456 SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_read???");
fd9abb3d
SG		 457 reg = -EIO;
458 goto out;
459 }
460
461 /* Set the address, index & direction (read from PHY) */
462 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6);
463 smsc911x_mac_write(pdata, MII_ACC, addr);
464
465 /* Wait for read to complete w/ timeout */
466 for (i = 0; i < 100; i++)
467 if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
468 reg = smsc911x_mac_read(pdata, MII_DATA);
469 goto out;
470 }
471
dffc6b24 472 SMSC_WARN(pdata, hw, "Timed out waiting for MII read to finish");
fd9abb3d
SG		 473 reg = -EIO;
474
475out:
476 spin_unlock_irqrestore(&pdata->mac_lock, flags);
477 return reg;
478}
479
480/* Set a phy register */
481static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
482 u16 val)
483{
484 struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
485 unsigned long flags;
486 unsigned int addr;
487 int i, reg;
488
489 spin_lock_irqsave(&pdata->mac_lock, flags);
490
491 /* Confirm MII not busy */
492 if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
dffc6b24 493 SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_write???");
fd9abb3d
SG		 494 reg = -EIO;
495 goto out;
496 }
497
498 /* Put the data to write in the MAC */
499 smsc911x_mac_write(pdata, MII_DATA, val);
500
501 /* Set the address, index & direction (write to PHY) */
502 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
503 MII_ACC_MII_WRITE_;
504 smsc911x_mac_write(pdata, MII_ACC, addr);
505
506 /* Wait for write to complete w/ timeout */
507 for (i = 0; i < 100; i++)
508 if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
509 reg = 0;
510 goto out;
511 }
512
dffc6b24 513 SMSC_WARN(pdata, hw, "Timed out waiting for MII write to finish");
fd9abb3d
SG		 514 reg = -EIO;
515
516out:
517 spin_unlock_irqrestore(&pdata->mac_lock, flags);
518 return reg;
519}
520
d23f028a
SG		 521/* Switch to external phy. Assumes tx and rx are stopped. */
522static void smsc911x_phy_enable_external(struct smsc911x_data *pdata)
fd9abb3d
SG		 523{
524 unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
525
d23f028a
SG		 526 /* Disable phy clocks to the MAC */
527 hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
528 hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
529 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
530 udelay(10); /* Enough time for clocks to stop */
fd9abb3d 531
d23f028a
SG		 532 /* Switch to external phy */
533 hwcfg |= HW_CFG_EXT_PHY_EN_;
534 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
fd9abb3d 535
d23f028a
SG		 536 /* Enable phy clocks to the MAC */
537 hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
538 hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
539 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
540 udelay(10); /* Enough time for clocks to restart */
fd9abb3d 541
d23f028a
SG		 542 hwcfg |= HW_CFG_SMI_SEL_;
543 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
544}
fd9abb3d 545
d23f028a
SG		 546/* Autodetects and enables external phy if present on supported chips.
547 * autodetection can be overridden by specifying SMSC911X_FORCE_INTERNAL_PHY
548 * or SMSC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */
549static void smsc911x_phy_initialise_external(struct smsc911x_data *pdata)
550{
551 unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
fd9abb3d 552
d23f028a 553 if (pdata->config.flags & SMSC911X_FORCE_INTERNAL_PHY) {
dffc6b24 554 SMSC_TRACE(pdata, hw, "Forcing internal PHY");
d23f028a
SG		 555 pdata->using_extphy = 0;
556 } else if (pdata->config.flags & SMSC911X_FORCE_EXTERNAL_PHY) {
dffc6b24 557 SMSC_TRACE(pdata, hw, "Forcing external PHY");
d23f028a
SG		 558 smsc911x_phy_enable_external(pdata);
559 pdata->using_extphy = 1;
560 } else if (hwcfg & HW_CFG_EXT_PHY_DET_) {
dffc6b24
JP		 561 SMSC_TRACE(pdata, hw,
562 "HW_CFG EXT_PHY_DET set, using external PHY");
d23f028a 563 smsc911x_phy_enable_external(pdata);
fd9abb3d
SG		 564 pdata->using_extphy = 1;
565 } else {
dffc6b24
JP		 566 SMSC_TRACE(pdata, hw,
567 "HW_CFG EXT_PHY_DET clear, using internal PHY");
d23f028a 568 pdata->using_extphy = 0;
fd9abb3d 569 }
fd9abb3d
SG		 570}
571
572/* Fetches a tx status out of the status fifo */
573static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata)
574{
575 unsigned int result =
576 smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_;
577
578 if (result != 0)
579 result = smsc911x_reg_read(pdata, TX_STATUS_FIFO);
580
581 return result;
582}
583
584/* Fetches the next rx status */
585static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata)
586{
587 unsigned int result =
588 smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_;
589
590 if (result != 0)
591 result = smsc911x_reg_read(pdata, RX_STATUS_FIFO);
592
593 return result;
594}
595
596#ifdef USE_PHY_WORK_AROUND
597static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata)
598{
599 unsigned int tries;
600 u32 wrsz;
601 u32 rdsz;
602 ulong bufp;
603
604 for (tries = 0; tries < 10; tries++) {
605 unsigned int txcmd_a;
606 unsigned int txcmd_b;
607 unsigned int status;
608 unsigned int pktlength;
609 unsigned int i;
610
611 /* Zero-out rx packet memory */
612 memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE);
613
614 /* Write tx packet to 118 */
615 txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16;
616 txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
617 txcmd_a |= MIN_PACKET_SIZE;
618
619 txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE;
620
621 smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a);
622 smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b);
623
624 bufp = (ulong)pdata->loopback_tx_pkt & (~0x3);
625 wrsz = MIN_PACKET_SIZE + 3;
626 wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3);
627 wrsz >>= 2;
628
c326de88 629 pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
fd9abb3d
SG		 630
631 /* Wait till transmit is done */
632 i = 60;
633 do {
634 udelay(5);
635 status = smsc911x_tx_get_txstatus(pdata);
636 } while ((i--) && (!status));
637
638 if (!status) {
dffc6b24
JP		 639 SMSC_WARN(pdata, hw,
640 "Failed to transmit during loopback test");
fd9abb3d
SG		 641 continue;
642 }
643 if (status & TX_STS_ES_) {
dffc6b24
JP		 644 SMSC_WARN(pdata, hw,
645 "Transmit encountered errors during loopback test");
fd9abb3d
SG		 646 continue;
647 }
648
649 /* Wait till receive is done */
650 i = 60;
651 do {
652 udelay(5);
653 status = smsc911x_rx_get_rxstatus(pdata);
654 } while ((i--) && (!status));
655
656 if (!status) {
dffc6b24
JP		 657 SMSC_WARN(pdata, hw,
658 "Failed to receive during loopback test");
fd9abb3d
SG		 659 continue;
660 }
661 if (status & RX_STS_ES_) {
dffc6b24
JP		 662 SMSC_WARN(pdata, hw,
663 "Receive encountered errors during loopback test");
fd9abb3d
SG		 664 continue;
665 }
666
667 pktlength = ((status & 0x3FFF0000UL) >> 16);
668 bufp = (ulong)pdata->loopback_rx_pkt;
669 rdsz = pktlength + 3;
670 rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3);
671 rdsz >>= 2;
672
c326de88 673 pdata->ops->rx_readfifo(pdata, (unsigned int *)bufp, rdsz);
fd9abb3d
SG		 674
675 if (pktlength != (MIN_PACKET_SIZE + 4)) {
dffc6b24
JP		 676 SMSC_WARN(pdata, hw, "Unexpected packet size "
677 "during loop back test, size=%d, will retry",
678 pktlength);
fd9abb3d
SG		 679 } else {
680 unsigned int j;
681 int mismatch = 0;
682 for (j = 0; j < MIN_PACKET_SIZE; j++) {
683 if (pdata->loopback_tx_pkt[j]
684 != pdata->loopback_rx_pkt[j]) {
685 mismatch = 1;
686 break;
687 }
688 }
689 if (!mismatch) {
dffc6b24 690 SMSC_TRACE(pdata, hw, "Successfully verified "
fd9abb3d
SG		 691 "loopback packet");
692 return 0;
693 } else {
dffc6b24
JP		 694 SMSC_WARN(pdata, hw, "Data mismatch "
695 "during loop back test, will retry");
fd9abb3d
SG		 696 }
697 }
698 }
699
700 return -EIO;
701}
702
703static int smsc911x_phy_reset(struct smsc911x_data *pdata)
704{
705 struct phy_device *phy_dev = pdata->phy_dev;
706 unsigned int temp;
707 unsigned int i = 100000;
708
709 BUG_ON(!phy_dev);
710 BUG_ON(!phy_dev->bus);
711
dffc6b24 712 SMSC_TRACE(pdata, hw, "Performing PHY BCR Reset");
fd9abb3d
SG		 713 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_RESET);
714 do {
715 msleep(1);
716 temp = smsc911x_mii_read(phy_dev->bus, phy_dev->addr,
717 MII_BMCR);
718 } while ((i--) && (temp & BMCR_RESET));
719
720 if (temp & BMCR_RESET) {
dffc6b24 721 SMSC_WARN(pdata, hw, "PHY reset failed to complete");
fd9abb3d
SG		 722 return -EIO;
723 }
724 /* Extra delay required because the phy may not be completed with
725 * its reset when BMCR_RESET is cleared. Specs say 256 uS is
726 * enough delay but using 1ms here to be safe */
727 msleep(1);
728
729 return 0;
730}
731
732static int smsc911x_phy_loopbacktest(struct net_device *dev)
733{
734 struct smsc911x_data *pdata = netdev_priv(dev);
735 struct phy_device *phy_dev = pdata->phy_dev;
736 int result = -EIO;
737 unsigned int i, val;
738 unsigned long flags;
739
740 /* Initialise tx packet using broadcast destination address */
741 memset(pdata->loopback_tx_pkt, 0xff, ETH_ALEN);
742
743 /* Use incrementing source address */
744 for (i = 6; i < 12; i++)
745 pdata->loopback_tx_pkt[i] = (char)i;
746
747 /* Set length type field */
748 pdata->loopback_tx_pkt[12] = 0x00;
749 pdata->loopback_tx_pkt[13] = 0x00;
750
751 for (i = 14; i < MIN_PACKET_SIZE; i++)
752 pdata->loopback_tx_pkt[i] = (char)i;
753
754 val = smsc911x_reg_read(pdata, HW_CFG);
755 val &= HW_CFG_TX_FIF_SZ_;
756 val |= HW_CFG_SF_;
757 smsc911x_reg_write(pdata, HW_CFG, val);
758
759 smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
760 smsc911x_reg_write(pdata, RX_CFG,
761 (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8);
762
763 for (i = 0; i < 10; i++) {
764 /* Set PHY to 10/FD, no ANEG, and loopback mode */
765 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR,
766 BMCR_LOOPBACK | BMCR_FULLDPLX);
767
768 /* Enable MAC tx/rx, FD */
769 spin_lock_irqsave(&pdata->mac_lock, flags);
770 smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_
771 | MAC_CR_TXEN_ | MAC_CR_RXEN_);
772 spin_unlock_irqrestore(&pdata->mac_lock, flags);
773
774 if (smsc911x_phy_check_loopbackpkt(pdata) == 0) {
775 result = 0;
776 break;
777 }
778 pdata->resetcount++;
779
780 /* Disable MAC rx */
781 spin_lock_irqsave(&pdata->mac_lock, flags);
782 smsc911x_mac_write(pdata, MAC_CR, 0);
783 spin_unlock_irqrestore(&pdata->mac_lock, flags);
784
785 smsc911x_phy_reset(pdata);
786 }
787
788 /* Disable MAC */
789 spin_lock_irqsave(&pdata->mac_lock, flags);
790 smsc911x_mac_write(pdata, MAC_CR, 0);
791 spin_unlock_irqrestore(&pdata->mac_lock, flags);
792
793 /* Cancel PHY loopback mode */
794 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, 0);
795
796 smsc911x_reg_write(pdata, TX_CFG, 0);
797 smsc911x_reg_write(pdata, RX_CFG, 0);
798
799 return result;
800}
801#endif /* USE_PHY_WORK_AROUND */
802
fd9abb3d
SG		 803static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata)
804{
805 struct phy_device *phy_dev = pdata->phy_dev;
806 u32 afc = smsc911x_reg_read(pdata, AFC_CFG);
807 u32 flow;
808 unsigned long flags;
809
810 if (phy_dev->duplex == DUPLEX_FULL) {
811 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
812 u16 rmtadv = phy_read(phy_dev, MII_LPA);
bc02ff95 813 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
fd9abb3d
SG		 814
815 if (cap & FLOW_CTRL_RX)
816 flow = 0xFFFF0002;
817 else
818 flow = 0;
819
820 if (cap & FLOW_CTRL_TX)
821 afc |= 0xF;
822 else
823 afc &= ~0xF;
824
dffc6b24
JP		 825 SMSC_TRACE(pdata, hw, "rx pause %s, tx pause %s",
826 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
827 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
fd9abb3d 828 } else {
dffc6b24 829 SMSC_TRACE(pdata, hw, "half duplex");
fd9abb3d
SG		 830 flow = 0;
831 afc |= 0xF;
832 }
833
834 spin_lock_irqsave(&pdata->mac_lock, flags);
835 smsc911x_mac_write(pdata, FLOW, flow);
836 spin_unlock_irqrestore(&pdata->mac_lock, flags);
837
838 smsc911x_reg_write(pdata, AFC_CFG, afc);
839}
840
841/* Update link mode if anything has changed. Called periodically when the
842 * PHY is in polling mode, even if nothing has changed. */
843static void smsc911x_phy_adjust_link(struct net_device *dev)
844{
845 struct smsc911x_data *pdata = netdev_priv(dev);
846 struct phy_device *phy_dev = pdata->phy_dev;
847 unsigned long flags;
848 int carrier;
849
850 if (phy_dev->duplex != pdata->last_duplex) {
851 unsigned int mac_cr;
dffc6b24 852 SMSC_TRACE(pdata, hw, "duplex state has changed");
fd9abb3d
SG		 853
854 spin_lock_irqsave(&pdata->mac_lock, flags);
855 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
856 if (phy_dev->duplex) {
dffc6b24
JP		 857 SMSC_TRACE(pdata, hw,
858 "configuring for full duplex mode");
fd9abb3d
SG		 859 mac_cr |= MAC_CR_FDPX_;
860 } else {
dffc6b24
JP		 861 SMSC_TRACE(pdata, hw,
862 "configuring for half duplex mode");
fd9abb3d
SG		 863 mac_cr &= ~MAC_CR_FDPX_;
864 }
865 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
866 spin_unlock_irqrestore(&pdata->mac_lock, flags);
867
868 smsc911x_phy_update_flowcontrol(pdata);
869 pdata->last_duplex = phy_dev->duplex;
870 }
871
872 carrier = netif_carrier_ok(dev);
873 if (carrier != pdata->last_carrier) {
dffc6b24 874 SMSC_TRACE(pdata, hw, "carrier state has changed");
fd9abb3d 875 if (carrier) {
dffc6b24 876 SMSC_TRACE(pdata, hw, "configuring for carrier OK");
fd9abb3d
SG		 877 if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) &&
878 (!pdata->using_extphy)) {
88393161 879 /* Restore original GPIO configuration */
fd9abb3d
SG		 880 pdata->gpio_setting = pdata->gpio_orig_setting;
881 smsc911x_reg_write(pdata, GPIO_CFG,
882 pdata->gpio_setting);
883 }
884 } else {
dffc6b24 885 SMSC_TRACE(pdata, hw, "configuring for no carrier");
fd9abb3d
SG		 886 /* Check global setting that LED1
887 * usage is 10/100 indicator */
888 pdata->gpio_setting = smsc911x_reg_read(pdata,
889 GPIO_CFG);
8e95a202
JP		 890 if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_) &&
891 (!pdata->using_extphy)) {
fd9abb3d 892 /* Force 10/100 LED off, after saving
88393161 893 * original GPIO configuration */
fd9abb3d
SG		 894 pdata->gpio_orig_setting = pdata->gpio_setting;
895
896 pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_;
897 pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_
898 | GPIO_CFG_GPIODIR0_
899 | GPIO_CFG_GPIOD0_);
900 smsc911x_reg_write(pdata, GPIO_CFG,
901 pdata->gpio_setting);
902 }
903 }
904 pdata->last_carrier = carrier;
905 }
906}
907
908static int smsc911x_mii_probe(struct net_device *dev)
909{
910 struct smsc911x_data *pdata = netdev_priv(dev);
911 struct phy_device *phydev = NULL;
e4a474f8 912 int ret;
fd9abb3d
SG		 913
914 /* find the first phy */
e4a474f8 915 phydev = phy_find_first(pdata->mii_bus);
fd9abb3d 916 if (!phydev) {
dffc6b24 917 netdev_err(dev, "no PHY found\n");
fd9abb3d
SG		 918 return -ENODEV;
919 }
920
dffc6b24
JP		 921 SMSC_TRACE(pdata, probe, "PHY: addr %d, phy_id 0x%08X",
922 phydev->addr, phydev->phy_id);
e4a474f8 923
924 ret = phy_connect_direct(dev, phydev,
925 &smsc911x_phy_adjust_link, 0,
926 pdata->config.phy_interface);
fd9abb3d 927
e4a474f8 928 if (ret) {
dffc6b24 929 netdev_err(dev, "Could not attach to PHY\n");
e4a474f8 930 return ret;
fd9abb3d
SG		 931 }
932
dffc6b24
JP		 933 netdev_info(dev,
934 "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
935 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
fd9abb3d
SG		 936
937 /* mask with MAC supported features */
938 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
939 SUPPORTED_Asym_Pause);
940 phydev->advertising = phydev->supported;
941
942 pdata->phy_dev = phydev;
943 pdata->last_duplex = -1;
944 pdata->last_carrier = -1;
945
946#ifdef USE_PHY_WORK_AROUND
947 if (smsc911x_phy_loopbacktest(dev) < 0) {
dffc6b24 948 SMSC_WARN(pdata, hw, "Failed Loop Back Test");
fd9abb3d
SG		 949 return -ENODEV;
950 }
dffc6b24 951 SMSC_TRACE(pdata, hw, "Passed Loop Back Test");
fd9abb3d
SG		 952#endif /* USE_PHY_WORK_AROUND */
953
dffc6b24 954 SMSC_TRACE(pdata, hw, "phy initialised successfully");
fd9abb3d
SG		 955 return 0;
956}
957
958static int __devinit smsc911x_mii_init(struct platform_device *pdev,
959 struct net_device *dev)
960{
961 struct smsc911x_data *pdata = netdev_priv(dev);
962 int err = -ENXIO, i;
963
964 pdata->mii_bus = mdiobus_alloc();
965 if (!pdata->mii_bus) {
966 err = -ENOMEM;
967 goto err_out_1;
968 }
969
970 pdata->mii_bus->name = SMSC_MDIONAME;
971 snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
972 pdata->mii_bus->priv = pdata;
973 pdata->mii_bus->read = smsc911x_mii_read;
974 pdata->mii_bus->write = smsc911x_mii_write;
975 pdata->mii_bus->irq = pdata->phy_irq;
976 for (i = 0; i < PHY_MAX_ADDR; ++i)
977 pdata->mii_bus->irq[i] = PHY_POLL;
978
979 pdata->mii_bus->parent = &pdev->dev;
fd9abb3d 980
fd9abb3d
SG		 981 switch (pdata->idrev & 0xFFFF0000) {
982 case 0x01170000:
983 case 0x01150000:
984 case 0x117A0000:
985 case 0x115A0000:
986 /* External PHY supported, try to autodetect */
d23f028a 987 smsc911x_phy_initialise_external(pdata);
fd9abb3d
SG		 988 break;
989 default:
dffc6b24
JP		 990 SMSC_TRACE(pdata, hw, "External PHY is not supported, "
991 "using internal PHY");
d23f028a 992 pdata->using_extphy = 0;
fd9abb3d
SG		 993 break;
994 }
995
996 if (!pdata->using_extphy) {
997 /* Mask all PHYs except ID 1 (internal) */
998 pdata->mii_bus->phy_mask = ~(1 << 1);
999 }
1000
1001 if (mdiobus_register(pdata->mii_bus)) {
dffc6b24 1002 SMSC_WARN(pdata, probe, "Error registering mii bus");
fd9abb3d
SG		 1003 goto err_out_free_bus_2;
1004 }
1005
1006 if (smsc911x_mii_probe(dev) < 0) {
dffc6b24 1007 SMSC_WARN(pdata, probe, "Error registering mii bus");
fd9abb3d
SG		 1008 goto err_out_unregister_bus_3;
1009 }
1010
1011 return 0;
1012
1013err_out_unregister_bus_3:
1014 mdiobus_unregister(pdata->mii_bus);
1015err_out_free_bus_2:
1016 mdiobus_free(pdata->mii_bus);
1017err_out_1:
1018 return err;
1019}
1020
1021/* Gets the number of tx statuses in the fifo */
1022static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata)
1023{
1024 return (smsc911x_reg_read(pdata, TX_FIFO_INF)
1025 & TX_FIFO_INF_TSUSED_) >> 16;
1026}
1027
1028/* Reads tx statuses and increments counters where necessary */
1029static void smsc911x_tx_update_txcounters(struct net_device *dev)
1030{
1031 struct smsc911x_data *pdata = netdev_priv(dev);
1032 unsigned int tx_stat;
1033
1034 while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) {
1035 if (unlikely(tx_stat & 0x80000000)) {
1036 /* In this driver the packet tag is used as the packet
1037 * length. Since a packet length can never reach the
1038 * size of 0x8000, this bit is reserved. It is worth
1039 * noting that the "reserved bit" in the warning above
1040 * does not reference a hardware defined reserved bit
1041 * but rather a driver defined one.
1042 */
dffc6b24 1043 SMSC_WARN(pdata, hw, "Packet tag reserved bit is high");
fd9abb3d 1044 } else {
785b6f97 1045 if (unlikely(tx_stat & TX_STS_ES_)) {
fd9abb3d
SG		 1046 dev->stats.tx_errors++;
1047 } else {
1048 dev->stats.tx_packets++;
1049 dev->stats.tx_bytes += (tx_stat >> 16);
1050 }
785b6f97 1051 if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) {
fd9abb3d
SG		 1052 dev->stats.collisions += 16;
1053 dev->stats.tx_aborted_errors += 1;
1054 } else {
1055 dev->stats.collisions +=
1056 ((tx_stat >> 3) & 0xF);
1057 }
785b6f97 1058 if (unlikely(tx_stat & TX_STS_LOST_CARRIER_))
fd9abb3d 1059 dev->stats.tx_carrier_errors += 1;
785b6f97 1060 if (unlikely(tx_stat & TX_STS_LATE_COL_)) {
fd9abb3d
SG		 1061 dev->stats.collisions++;
1062 dev->stats.tx_aborted_errors++;
1063 }
1064 }
1065 }
1066}
1067
1068/* Increments the Rx error counters */
1069static void
1070smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat)
1071{
1072 int crc_err = 0;
1073
785b6f97 1074 if (unlikely(rxstat & RX_STS_ES_)) {
fd9abb3d 1075 dev->stats.rx_errors++;
785b6f97 1076 if (unlikely(rxstat & RX_STS_CRC_ERR_)) {
fd9abb3d
SG		 1077 dev->stats.rx_crc_errors++;
1078 crc_err = 1;
1079 }
1080 }
1081 if (likely(!crc_err)) {
785b6f97
SG		 1082 if (unlikely((rxstat & RX_STS_FRAME_TYPE_) &&
1083 (rxstat & RX_STS_LENGTH_ERR_)))
fd9abb3d 1084 dev->stats.rx_length_errors++;
fd9abb3d
SG		 1085 if (rxstat & RX_STS_MCAST_)
1086 dev->stats.multicast++;
1087 }
1088}
1089
1090/* Quickly dumps bad packets */
1091static void
1092smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktbytes)
1093{
1094 unsigned int pktwords = (pktbytes + NET_IP_ALIGN + 3) >> 2;
1095
1096 if (likely(pktwords >= 4)) {
1097 unsigned int timeout = 500;
1098 unsigned int val;
1099 smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_);
1100 do {
1101 udelay(1);
1102 val = smsc911x_reg_read(pdata, RX_DP_CTRL);
8dacd548 1103 } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout);
fd9abb3d
SG		 1104
1105 if (unlikely(timeout == 0))
dffc6b24
JP		 1106 SMSC_WARN(pdata, hw, "Timed out waiting for "
1107 "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val);
fd9abb3d
SG		 1108 } else {
1109 unsigned int temp;
1110 while (pktwords--)
1111 temp = smsc911x_reg_read(pdata, RX_DATA_FIFO);
1112 }
1113}
1114
1115/* NAPI poll function */
1116static int smsc911x_poll(struct napi_struct *napi, int budget)
1117{
1118 struct smsc911x_data *pdata =
1119 container_of(napi, struct smsc911x_data, napi);
1120 struct net_device *dev = pdata->dev;
1121 int npackets = 0;
1122
f88c5b98 1123 while (npackets < budget) {
fd9abb3d
SG		 1124 unsigned int pktlength;
1125 unsigned int pktwords;
1126 struct sk_buff *skb;
1127 unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata);
1128
1129 if (!rxstat) {
1130 unsigned int temp;
1131 /* We processed all packets available. Tell NAPI it can
1132 * stop polling then re-enable rx interrupts */
1133 smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_);
288379f0 1134 napi_complete(napi);
fd9abb3d
SG		 1135 temp = smsc911x_reg_read(pdata, INT_EN);
1136 temp |= INT_EN_RSFL_EN_;
1137 smsc911x_reg_write(pdata, INT_EN, temp);
1138 break;
1139 }
1140
1141 /* Count packet for NAPI scheduling, even if it has an error.
1142 * Error packets still require cycles to discard */
1143 npackets++;
1144
1145 pktlength = ((rxstat & 0x3FFF0000) >> 16);
1146 pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2;
1147 smsc911x_rx_counterrors(dev, rxstat);
1148
1149 if (unlikely(rxstat & RX_STS_ES_)) {
dffc6b24
JP		 1150 SMSC_WARN(pdata, rx_err,
1151 "Discarding packet with error bit set");
fd9abb3d
SG		 1152 /* Packet has an error, discard it and continue with
1153 * the next */
1154 smsc911x_rx_fastforward(pdata, pktwords);
1155 dev->stats.rx_dropped++;
1156 continue;
1157 }
1158
1159 skb = netdev_alloc_skb(dev, pktlength + NET_IP_ALIGN);
1160 if (unlikely(!skb)) {
dffc6b24
JP		 1161 SMSC_WARN(pdata, rx_err,
1162 "Unable to allocate skb for rx packet");
fd9abb3d
SG		 1163 /* Drop the packet and stop this polling iteration */
1164 smsc911x_rx_fastforward(pdata, pktwords);
1165 dev->stats.rx_dropped++;
1166 break;
1167 }
1168
1169 skb->data = skb->head;
1170 skb_reset_tail_pointer(skb);
1171
1172 /* Align IP on 16B boundary */
1173 skb_reserve(skb, NET_IP_ALIGN);
1174 skb_put(skb, pktlength - 4);
c326de88
MP		 1175 pdata->ops->rx_readfifo(pdata,
1176 (unsigned int *)skb->head, pktwords);
fd9abb3d 1177 skb->protocol = eth_type_trans(skb, dev);
bc8acf2c 1178 skb_checksum_none_assert(skb);
fd9abb3d
SG		 1179 netif_receive_skb(skb);
1180
1181 /* Update counters */
1182 dev->stats.rx_packets++;
1183 dev->stats.rx_bytes += (pktlength - 4);
fd9abb3d
SG		 1184 }
1185
1186 /* Return total received packets */
1187 return npackets;
1188}
1189
1190/* Returns hash bit number for given MAC address
1191 * Example:
1192 * 01 00 5E 00 00 01 -> returns bit number 31 */
1193static unsigned int smsc911x_hash(char addr[ETH_ALEN])
1194{
1195 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
1196}
1197
1198static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata)
1199{
1200 /* Performs the multicast & mac_cr update. This is called when
1201 * safe on the current hardware, and with the mac_lock held */
1202 unsigned int mac_cr;
1203
1204 SMSC_ASSERT_MAC_LOCK(pdata);
1205
1206 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
1207 mac_cr |= pdata->set_bits_mask;
1208 mac_cr &= ~(pdata->clear_bits_mask);
1209 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
1210 smsc911x_mac_write(pdata, HASHH, pdata->hashhi);
1211 smsc911x_mac_write(pdata, HASHL, pdata->hashlo);
dffc6b24
JP		 1212 SMSC_TRACE(pdata, hw, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X",
1213 mac_cr, pdata->hashhi, pdata->hashlo);
fd9abb3d
SG		 1214}
1215
1216static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata)
1217{
1218 unsigned int mac_cr;
1219
1220 /* This function is only called for older LAN911x devices
1221 * (revA or revB), where MAC_CR, HASHH and HASHL should not
1222 * be modified during Rx - newer devices immediately update the
1223 * registers.
1224 *
1225 * This is called from interrupt context */
1226
1227 spin_lock(&pdata->mac_lock);
1228
1229 /* Check Rx has stopped */
1230 if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_)
dffc6b24 1231 SMSC_WARN(pdata, drv, "Rx not stopped");
fd9abb3d
SG		 1232
1233 /* Perform the update - safe to do now Rx has stopped */
1234 smsc911x_rx_multicast_update(pdata);
1235
1236 /* Re-enable Rx */
1237 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
1238 mac_cr |= MAC_CR_RXEN_;
1239 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
1240
1241 pdata->multicast_update_pending = 0;
1242
1243 spin_unlock(&pdata->mac_lock);
1244}
1245
1246static int smsc911x_soft_reset(struct smsc911x_data *pdata)
1247{
1248 unsigned int timeout;
1249 unsigned int temp;
1250
1251 /* Reset the LAN911x */
1252 smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_);
1253 timeout = 10;
1254 do {
1255 udelay(10);
1256 temp = smsc911x_reg_read(pdata, HW_CFG);
1257 } while ((--timeout) && (temp & HW_CFG_SRST_));
1258
1259 if (unlikely(temp & HW_CFG_SRST_)) {
dffc6b24 1260 SMSC_WARN(pdata, drv, "Failed to complete reset");
fd9abb3d
SG		 1261 return -EIO;
1262 }
1263 return 0;
1264}
1265
1266/* Sets the device MAC address to dev_addr, called with mac_lock held */
1267static void
225ddf49 1268smsc911x_set_hw_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6])
fd9abb3d
SG		 1269{
1270 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
1271 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
1272 (dev_addr[1] << 8) | dev_addr[0];
1273
1274 SMSC_ASSERT_MAC_LOCK(pdata);
1275
1276 smsc911x_mac_write(pdata, ADDRH, mac_high16);
1277 smsc911x_mac_write(pdata, ADDRL, mac_low32);
1278}
1279
1280static int smsc911x_open(struct net_device *dev)
1281{
1282 struct smsc911x_data *pdata = netdev_priv(dev);
1283 unsigned int timeout;
1284 unsigned int temp;
1285 unsigned int intcfg;
1286
1287 /* if the phy is not yet registered, retry later*/
1288 if (!pdata->phy_dev) {
dffc6b24 1289 SMSC_WARN(pdata, hw, "phy_dev is NULL");
fd9abb3d
SG		 1290 return -EAGAIN;
1291 }
1292
1293 if (!is_valid_ether_addr(dev->dev_addr)) {
dffc6b24 1294 SMSC_WARN(pdata, hw, "dev_addr is not a valid MAC address");
fd9abb3d
SG		 1295 return -EADDRNOTAVAIL;
1296 }
1297
1298 /* Reset the LAN911x */
1299 if (smsc911x_soft_reset(pdata)) {
dffc6b24 1300 SMSC_WARN(pdata, hw, "soft reset failed");
fd9abb3d
SG		 1301 return -EIO;
1302 }
1303
1304 smsc911x_reg_write(pdata, HW_CFG, 0x00050000);
1305 smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740);
1306
f277e65e
GW		 1307 /* Increase the legal frame size of VLAN tagged frames to 1522 bytes */
1308 spin_lock_irq(&pdata->mac_lock);
1309 smsc911x_mac_write(pdata, VLAN1, ETH_P_8021Q);
1310 spin_unlock_irq(&pdata->mac_lock);
1311
fd9abb3d
SG		 1312 /* Make sure EEPROM has finished loading before setting GPIO_CFG */
1313 timeout = 50;
f7efb6cc
SG		 1314 while ((smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) &&
1315 --timeout) {
fd9abb3d
SG		 1316 udelay(10);
1317 }
1318
1319 if (unlikely(timeout == 0))
dffc6b24
JP		 1320 SMSC_WARN(pdata, ifup,
1321 "Timed out waiting for EEPROM busy bit to clear");
fd9abb3d
SG		 1322
1323 smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000);
1324
1325 /* The soft reset above cleared the device's MAC address,
1326 * restore it from local copy (set in probe) */
1327 spin_lock_irq(&pdata->mac_lock);
225ddf49 1328 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
fd9abb3d
SG		 1329 spin_unlock_irq(&pdata->mac_lock);
1330
1331 /* Initialise irqs, but leave all sources disabled */
1332 smsc911x_reg_write(pdata, INT_EN, 0);
1333 smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
1334
1335 /* Set interrupt deassertion to 100uS */
1336 intcfg = ((10 << 24) | INT_CFG_IRQ_EN_);
1337
2107fb8b 1338 if (pdata->config.irq_polarity) {
dffc6b24 1339 SMSC_TRACE(pdata, ifup, "irq polarity: active high");
fd9abb3d
SG		 1340 intcfg |= INT_CFG_IRQ_POL_;
1341 } else {
dffc6b24 1342 SMSC_TRACE(pdata, ifup, "irq polarity: active low");
fd9abb3d
SG		 1343 }
1344
2107fb8b 1345 if (pdata->config.irq_type) {
dffc6b24 1346 SMSC_TRACE(pdata, ifup, "irq type: push-pull");
fd9abb3d
SG		 1347 intcfg |= INT_CFG_IRQ_TYPE_;
1348 } else {
dffc6b24 1349 SMSC_TRACE(pdata, ifup, "irq type: open drain");
fd9abb3d
SG		 1350 }
1351
1352 smsc911x_reg_write(pdata, INT_CFG, intcfg);
1353
dffc6b24 1354 SMSC_TRACE(pdata, ifup, "Testing irq handler using IRQ %d", dev->irq);
fd9abb3d
SG		 1355 pdata->software_irq_signal = 0;
1356 smp_wmb();
1357
1358 temp = smsc911x_reg_read(pdata, INT_EN);
1359 temp |= INT_EN_SW_INT_EN_;
1360 smsc911x_reg_write(pdata, INT_EN, temp);
1361
1362 timeout = 1000;
1363 while (timeout--) {
1364 if (pdata->software_irq_signal)
1365 break;
1366 msleep(1);
1367 }
1368
1369 if (!pdata->software_irq_signal) {
dffc6b24
JP		 1370 netdev_warn(dev, "ISR failed signaling test (IRQ %d)\n",
1371 dev->irq);
fd9abb3d
SG		 1372 return -ENODEV;
1373 }
dffc6b24
JP		 1374 SMSC_TRACE(pdata, ifup, "IRQ handler passed test using IRQ %d",
1375 dev->irq);
fd9abb3d 1376
dffc6b24
JP		 1377 netdev_info(dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n",
1378 (unsigned long)pdata->ioaddr, dev->irq);
fd9abb3d 1379
44c1d6f9
SG		 1380 /* Reset the last known duplex and carrier */
1381 pdata->last_duplex = -1;
1382 pdata->last_carrier = -1;
1383
fd9abb3d
SG		 1384 /* Bring the PHY up */
1385 phy_start(pdata->phy_dev);
1386
1387 temp = smsc911x_reg_read(pdata, HW_CFG);
1388 /* Preserve TX FIFO size and external PHY configuration */
1389 temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF);
1390 temp |= HW_CFG_SF_;
1391 smsc911x_reg_write(pdata, HW_CFG, temp);
1392
1393 temp = smsc911x_reg_read(pdata, FIFO_INT);
1394 temp |= FIFO_INT_TX_AVAIL_LEVEL_;
1395 temp &= ~(FIFO_INT_RX_STS_LEVEL_);
1396 smsc911x_reg_write(pdata, FIFO_INT, temp);
1397
1398 /* set RX Data offset to 2 bytes for alignment */
1399 smsc911x_reg_write(pdata, RX_CFG, (2 << 8));
1400
1401 /* enable NAPI polling before enabling RX interrupts */
1402 napi_enable(&pdata->napi);
1403
1404 temp = smsc911x_reg_read(pdata, INT_EN);
1373c0fd 1405 temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_RXSTOP_INT_EN_);
fd9abb3d
SG		 1406 smsc911x_reg_write(pdata, INT_EN, temp);
1407
1408 spin_lock_irq(&pdata->mac_lock);
1409 temp = smsc911x_mac_read(pdata, MAC_CR);
1410 temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
1411 smsc911x_mac_write(pdata, MAC_CR, temp);
1412 spin_unlock_irq(&pdata->mac_lock);
1413
1414 smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
1415
1416 netif_start_queue(dev);
1417 return 0;
1418}
1419
1420/* Entry point for stopping the interface */
1421static int smsc911x_stop(struct net_device *dev)
1422{
1423 struct smsc911x_data *pdata = netdev_priv(dev);
1424 unsigned int temp;
1425
fd9abb3d
SG		 1426 /* Disable all device interrupts */
1427 temp = smsc911x_reg_read(pdata, INT_CFG);
1428 temp &= ~INT_CFG_IRQ_EN_;
1429 smsc911x_reg_write(pdata, INT_CFG, temp);
1430
1431 /* Stop Tx and Rx polling */
1432 netif_stop_queue(dev);
1433 napi_disable(&pdata->napi);
1434
1435 /* At this point all Rx and Tx activity is stopped */
1436 dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
1437 smsc911x_tx_update_txcounters(dev);
1438
1439 /* Bring the PHY down */
dd045193
SG		 1440 if (pdata->phy_dev)
1441 phy_stop(pdata->phy_dev);
fd9abb3d 1442
dffc6b24 1443 SMSC_TRACE(pdata, ifdown, "Interface stopped");
fd9abb3d
SG		 1444 return 0;
1445}
1446
1447/* Entry point for transmitting a packet */
1448static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
1449{
1450 struct smsc911x_data *pdata = netdev_priv(dev);
1451 unsigned int freespace;
1452 unsigned int tx_cmd_a;
1453 unsigned int tx_cmd_b;
1454 unsigned int temp;
1455 u32 wrsz;
1456 ulong bufp;
1457
1458 freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_;
1459
1460 if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD))
dffc6b24
JP		 1461 SMSC_WARN(pdata, tx_err,
1462 "Tx data fifo low, space available: %d", freespace);
fd9abb3d
SG		 1463
1464 /* Word alignment adjustment */
1465 tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16;
1466 tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
1467 tx_cmd_a |= (unsigned int)skb->len;
1468
1469 tx_cmd_b = ((unsigned int)skb->len) << 16;
1470 tx_cmd_b |= (unsigned int)skb->len;
1471
1472 smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a);
1473 smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b);
1474
1475 bufp = (ulong)skb->data & (~0x3);
1476 wrsz = (u32)skb->len + 3;
1477 wrsz += (u32)((ulong)skb->data & 0x3);
1478 wrsz >>= 2;
1479
c326de88 1480 pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
fd9abb3d 1481 freespace -= (skb->len + 32);
8c0069ae 1482 skb_tx_timestamp(skb);
fd9abb3d 1483 dev_kfree_skb(skb);
fd9abb3d
SG		 1484
1485 if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30))
1486 smsc911x_tx_update_txcounters(dev);
1487
1488 if (freespace < TX_FIFO_LOW_THRESHOLD) {
1489 netif_stop_queue(dev);
1490 temp = smsc911x_reg_read(pdata, FIFO_INT);
1491 temp &= 0x00FFFFFF;
1492 temp |= 0x32000000;
1493 smsc911x_reg_write(pdata, FIFO_INT, temp);
1494 }
1495
1496 return NETDEV_TX_OK;
1497}
1498
1499/* Entry point for getting status counters */
1500static struct net_device_stats *smsc911x_get_stats(struct net_device *dev)
1501{
1502 struct smsc911x_data *pdata = netdev_priv(dev);
1503 smsc911x_tx_update_txcounters(dev);
1504 dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
1505 return &dev->stats;
1506}
1507
1508/* Entry point for setting addressing modes */
1509static void smsc911x_set_multicast_list(struct net_device *dev)
1510{
1511 struct smsc911x_data *pdata = netdev_priv(dev);
1512 unsigned long flags;
1513
1514 if (dev->flags & IFF_PROMISC) {
1515 /* Enabling promiscuous mode */
1516 pdata->set_bits_mask = MAC_CR_PRMS_;
1517 pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
1518 pdata->hashhi = 0;
1519 pdata->hashlo = 0;
1520 } else if (dev->flags & IFF_ALLMULTI) {
1521 /* Enabling all multicast mode */
1522 pdata->set_bits_mask = MAC_CR_MCPAS_;
1523 pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_);
1524 pdata->hashhi = 0;
1525 pdata->hashlo = 0;
4cd24eaf 1526 } else if (!netdev_mc_empty(dev)) {
fd9abb3d
SG		 1527 /* Enabling specific multicast addresses */
1528 unsigned int hash_high = 0;
1529 unsigned int hash_low = 0;
22bedad3 1530 struct netdev_hw_addr *ha;
fd9abb3d
SG		 1531
1532 pdata->set_bits_mask = MAC_CR_HPFILT_;
1533 pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_);
1534
22bedad3
JP		 1535 netdev_for_each_mc_addr(ha, dev) {
1536 unsigned int bitnum = smsc911x_hash(ha->addr);
2a0d18f9
JP		 1537 unsigned int mask = 0x01 << (bitnum & 0x1F);
1538
1539 if (bitnum & 0x20)
1540 hash_high |= mask;
1541 else
1542 hash_low |= mask;
fd9abb3d 1543 }
fd9abb3d
SG		 1544
1545 pdata->hashhi = hash_high;
1546 pdata->hashlo = hash_low;
1547 } else {
1548 /* Enabling local MAC address only */
1549 pdata->set_bits_mask = 0;
1550 pdata->clear_bits_mask =
1551 (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
1552 pdata->hashhi = 0;
1553 pdata->hashlo = 0;
1554 }
1555
1556 spin_lock_irqsave(&pdata->mac_lock, flags);
1557
1558 if (pdata->generation <= 1) {
1559 /* Older hardware revision - cannot change these flags while
1560 * receiving data */
1561 if (!pdata->multicast_update_pending) {
1562 unsigned int temp;
dffc6b24 1563 SMSC_TRACE(pdata, hw, "scheduling mcast update");
fd9abb3d
SG		 1564 pdata->multicast_update_pending = 1;
1565
1566 /* Request the hardware to stop, then perform the
1567 * update when we get an RX_STOP interrupt */
fd9abb3d
SG		 1568 temp = smsc911x_mac_read(pdata, MAC_CR);
1569 temp &= ~(MAC_CR_RXEN_);
1570 smsc911x_mac_write(pdata, MAC_CR, temp);
1571 } else {
1572 /* There is another update pending, this should now
1573 * use the newer values */
1574 }
1575 } else {
1576 /* Newer hardware revision - can write immediately */
1577 smsc911x_rx_multicast_update(pdata);
1578 }
1579
1580 spin_unlock_irqrestore(&pdata->mac_lock, flags);
1581}
1582
1583static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id)
1584{
1585 struct net_device *dev = dev_id;
1586 struct smsc911x_data *pdata = netdev_priv(dev);
1587 u32 intsts = smsc911x_reg_read(pdata, INT_STS);
1588 u32 inten = smsc911x_reg_read(pdata, INT_EN);
1589 int serviced = IRQ_NONE;
1590 u32 temp;
1591
1592 if (unlikely(intsts & inten & INT_STS_SW_INT_)) {
1593 temp = smsc911x_reg_read(pdata, INT_EN);
1594 temp &= (~INT_EN_SW_INT_EN_);
1595 smsc911x_reg_write(pdata, INT_EN, temp);
1596 smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_);
1597 pdata->software_irq_signal = 1;
1598 smp_wmb();
1599 serviced = IRQ_HANDLED;
1600 }
1601
1602 if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) {
1603 /* Called when there is a multicast update scheduled and
1604 * it is now safe to complete the update */
dffc6b24 1605 SMSC_TRACE(pdata, intr, "RX Stop interrupt");
fd9abb3d 1606 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_);
1373c0fd
SG		 1607 if (pdata->multicast_update_pending)
1608 smsc911x_rx_multicast_update_workaround(pdata);
fd9abb3d
SG		 1609 serviced = IRQ_HANDLED;
1610 }
1611
1612 if (intsts & inten & INT_STS_TDFA_) {
1613 temp = smsc911x_reg_read(pdata, FIFO_INT);
1614 temp |= FIFO_INT_TX_AVAIL_LEVEL_;
1615 smsc911x_reg_write(pdata, FIFO_INT, temp);
1616 smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_);
1617 netif_wake_queue(dev);
1618 serviced = IRQ_HANDLED;
1619 }
1620
1621 if (unlikely(intsts & inten & INT_STS_RXE_)) {
dffc6b24 1622 SMSC_TRACE(pdata, intr, "RX Error interrupt");
fd9abb3d
SG		 1623 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_);
1624 serviced = IRQ_HANDLED;
1625 }
1626
1627 if (likely(intsts & inten & INT_STS_RSFL_)) {
288379f0 1628 if (likely(napi_schedule_prep(&pdata->napi))) {
fd9abb3d
SG		 1629 /* Disable Rx interrupts */
1630 temp = smsc911x_reg_read(pdata, INT_EN);
1631 temp &= (~INT_EN_RSFL_EN_);
1632 smsc911x_reg_write(pdata, INT_EN, temp);
1633 /* Schedule a NAPI poll */
288379f0 1634 __napi_schedule(&pdata->napi);
fd9abb3d 1635 } else {
dffc6b24 1636 SMSC_WARN(pdata, rx_err, "napi_schedule_prep failed");
fd9abb3d
SG		 1637 }
1638 serviced = IRQ_HANDLED;
1639 }
1640
1641 return serviced;
1642}
1643
1644#ifdef CONFIG_NET_POLL_CONTROLLER
1757ab2f 1645static void smsc911x_poll_controller(struct net_device *dev)
fd9abb3d
SG		 1646{
1647 disable_irq(dev->irq);
1648 smsc911x_irqhandler(0, dev);
1649 enable_irq(dev->irq);
1650}
1651#endif /* CONFIG_NET_POLL_CONTROLLER */
1652
225ddf49
SG		 1653static int smsc911x_set_mac_address(struct net_device *dev, void *p)
1654{
1655 struct smsc911x_data *pdata = netdev_priv(dev);
1656 struct sockaddr *addr = p;
1657
1658 /* On older hardware revisions we cannot change the mac address
1659 * registers while receiving data. Newer devices can safely change
1660 * this at any time. */
1661 if (pdata->generation <= 1 && netif_running(dev))
1662 return -EBUSY;
1663
1664 if (!is_valid_ether_addr(addr->sa_data))
1665 return -EADDRNOTAVAIL;
1666
1667 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
1668
1669 spin_lock_irq(&pdata->mac_lock);
1670 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
1671 spin_unlock_irq(&pdata->mac_lock);
1672
dffc6b24 1673 netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr);
225ddf49
SG		 1674
1675 return 0;
1676}
1677
fd9abb3d
SG		 1678/* Standard ioctls for mii-tool */
1679static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1680{
1681 struct smsc911x_data *pdata = netdev_priv(dev);
1682
1683 if (!netif_running(dev) || !pdata->phy_dev)
1684 return -EINVAL;
1685
28b04113 1686 return phy_mii_ioctl(pdata->phy_dev, ifr, cmd);
fd9abb3d
SG		 1687}
1688
1689static int
1690smsc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1691{
1692 struct smsc911x_data *pdata = netdev_priv(dev);
1693
1694 cmd->maxtxpkt = 1;
1695 cmd->maxrxpkt = 1;
1696 return phy_ethtool_gset(pdata->phy_dev, cmd);
1697}
1698
1699static int
1700smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1701{
1702 struct smsc911x_data *pdata = netdev_priv(dev);
1703
1704 return phy_ethtool_sset(pdata->phy_dev, cmd);
1705}
1706
1707static void smsc911x_ethtool_getdrvinfo(struct net_device *dev,
1708 struct ethtool_drvinfo *info)
1709{
1710 strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver));
1711 strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version));
db1d7bf7 1712 strlcpy(info->bus_info, dev_name(dev->dev.parent),
fd9abb3d
SG		 1713 sizeof(info->bus_info));
1714}
1715
1716static int smsc911x_ethtool_nwayreset(struct net_device *dev)
1717{
1718 struct smsc911x_data *pdata = netdev_priv(dev);
1719
1720 return phy_start_aneg(pdata->phy_dev);
1721}
1722
1723static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev)
1724{
1725 struct smsc911x_data *pdata = netdev_priv(dev);
1726 return pdata->msg_enable;
1727}
1728
1729static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
1730{
1731 struct smsc911x_data *pdata = netdev_priv(dev);
1732 pdata->msg_enable = level;
1733}
1734
1735static int smsc911x_ethtool_getregslen(struct net_device *dev)
1736{
1737 return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) *
1738 sizeof(u32);
1739}
1740
1741static void
1742smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
1743 void *buf)
1744{
1745 struct smsc911x_data *pdata = netdev_priv(dev);
1746 struct phy_device *phy_dev = pdata->phy_dev;
1747 unsigned long flags;
1748 unsigned int i;
1749 unsigned int j = 0;
1750 u32 *data = buf;
1751
1752 regs->version = pdata->idrev;
1753 for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32)))
1754 data[j++] = smsc911x_reg_read(pdata, i);
1755
1756 for (i = MAC_CR; i <= WUCSR; i++) {
1757 spin_lock_irqsave(&pdata->mac_lock, flags);
1758 data[j++] = smsc911x_mac_read(pdata, i);
1759 spin_unlock_irqrestore(&pdata->mac_lock, flags);
1760 }
1761
1762 for (i = 0; i <= 31; i++)
1763 data[j++] = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, i);
1764}
1765
1766static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata)
1767{
1768 unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG);
1769 temp &= ~GPIO_CFG_EEPR_EN_;
1770 smsc911x_reg_write(pdata, GPIO_CFG, temp);
1771 msleep(1);
1772}
1773
1774static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op)
1775{
1776 int timeout = 100;
1777 u32 e2cmd;
1778
dffc6b24 1779 SMSC_TRACE(pdata, drv, "op 0x%08x", op);
fd9abb3d 1780 if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
dffc6b24 1781 SMSC_WARN(pdata, drv, "Busy at start");
fd9abb3d
SG		 1782 return -EBUSY;
1783 }
1784
1785 e2cmd = op | E2P_CMD_EPC_BUSY_;
1786 smsc911x_reg_write(pdata, E2P_CMD, e2cmd);
1787
1788 do {
1789 msleep(1);
1790 e2cmd = smsc911x_reg_read(pdata, E2P_CMD);
2cf0dbed 1791 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
fd9abb3d
SG		 1792
1793 if (!timeout) {
dffc6b24 1794 SMSC_TRACE(pdata, drv, "TIMED OUT");
fd9abb3d
SG		 1795 return -EAGAIN;
1796 }
1797
1798 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
1c01a80c 1799 SMSC_TRACE(pdata, drv, "Error occurred during eeprom operation");
fd9abb3d
SG		 1800 return -EINVAL;
1801 }
1802
1803 return 0;
1804}
1805
1806static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata,
1807 u8 address, u8 *data)
1808{
1809 u32 op = E2P_CMD_EPC_CMD_READ_ | address;
1810 int ret;
1811
dffc6b24 1812 SMSC_TRACE(pdata, drv, "address 0x%x", address);
fd9abb3d
SG		 1813 ret = smsc911x_eeprom_send_cmd(pdata, op);
1814
1815 if (!ret)
1816 data[address] = smsc911x_reg_read(pdata, E2P_DATA);
1817
1818 return ret;
1819}
1820
1821static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
1822 u8 address, u8 data)
1823{
1824 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
58add9fc 1825 u32 temp;
fd9abb3d
SG		 1826 int ret;
1827
dffc6b24 1828 SMSC_TRACE(pdata, drv, "address 0x%x, data 0x%x", address, data);
fd9abb3d
SG		 1829 ret = smsc911x_eeprom_send_cmd(pdata, op);
1830
1831 if (!ret) {
1832 op = E2P_CMD_EPC_CMD_WRITE_ | address;
1833 smsc911x_reg_write(pdata, E2P_DATA, (u32)data);
58add9fc
SG		 1834
1835 /* Workaround for hardware read-after-write restriction */
1836 temp = smsc911x_reg_read(pdata, BYTE_TEST);
1837
fd9abb3d
SG		 1838 ret = smsc911x_eeprom_send_cmd(pdata, op);
1839 }
1840
1841 return ret;
1842}
1843
1844static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev)
1845{
1846 return SMSC911X_EEPROM_SIZE;
1847}
1848
1849static int smsc911x_ethtool_get_eeprom(struct net_device *dev,
1850 struct ethtool_eeprom *eeprom, u8 *data)
1851{
1852 struct smsc911x_data *pdata = netdev_priv(dev);
1853 u8 eeprom_data[SMSC911X_EEPROM_SIZE];
1854 int len;
1855 int i;
1856
1857 smsc911x_eeprom_enable_access(pdata);
1858
1859 len = min(eeprom->len, SMSC911X_EEPROM_SIZE);
1860 for (i = 0; i < len; i++) {
1861 int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data);
1862 if (ret < 0) {
1863 eeprom->len = 0;
1864 return ret;
1865 }
1866 }
1867
1868 memcpy(data, &eeprom_data[eeprom->offset], len);
1869 eeprom->len = len;
1870 return 0;
1871}
1872
1873static int smsc911x_ethtool_set_eeprom(struct net_device *dev,
1874 struct ethtool_eeprom *eeprom, u8 *data)
1875{
1876 int ret;
1877 struct smsc911x_data *pdata = netdev_priv(dev);
1878
1879 smsc911x_eeprom_enable_access(pdata);
1880 smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_);
1881 ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data);
1882 smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_);
1883
1884 /* Single byte write, according to man page */
1885 eeprom->len = 1;
1886
1887 return ret;
1888}
1889
cb5b04fe 1890static const struct ethtool_ops smsc911x_ethtool_ops = {
fd9abb3d
SG		 1891 .get_settings = smsc911x_ethtool_getsettings,
1892 .set_settings = smsc911x_ethtool_setsettings,
1893 .get_link = ethtool_op_get_link,
1894 .get_drvinfo = smsc911x_ethtool_getdrvinfo,
1895 .nway_reset = smsc911x_ethtool_nwayreset,
1896 .get_msglevel = smsc911x_ethtool_getmsglevel,
1897 .set_msglevel = smsc911x_ethtool_setmsglevel,
1898 .get_regs_len = smsc911x_ethtool_getregslen,
1899 .get_regs = smsc911x_ethtool_getregs,
1900 .get_eeprom_len = smsc911x_ethtool_get_eeprom_len,
1901 .get_eeprom = smsc911x_ethtool_get_eeprom,
1902 .set_eeprom = smsc911x_ethtool_set_eeprom,
1903};
1904
631b7568
SG		 1905static const struct net_device_ops smsc911x_netdev_ops = {
1906 .ndo_open = smsc911x_open,
1907 .ndo_stop = smsc911x_stop,
1908 .ndo_start_xmit = smsc911x_hard_start_xmit,
1909 .ndo_get_stats = smsc911x_get_stats,
afc4b13d 1910 .ndo_set_rx_mode = smsc911x_set_multicast_list,
631b7568 1911 .ndo_do_ioctl = smsc911x_do_ioctl,
635ecaa7 1912 .ndo_change_mtu = eth_change_mtu,
631b7568 1913 .ndo_validate_addr = eth_validate_addr,
225ddf49 1914 .ndo_set_mac_address = smsc911x_set_mac_address,
631b7568
SG		 1915#ifdef CONFIG_NET_POLL_CONTROLLER
1916 .ndo_poll_controller = smsc911x_poll_controller,
1917#endif
1918};
1919
31f45747
SG		 1920/* copies the current mac address from hardware to dev->dev_addr */
1921static void __devinit smsc911x_read_mac_address(struct net_device *dev)
1922{
1923 struct smsc911x_data *pdata = netdev_priv(dev);
1924 u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH);
1925 u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL);
1926
1927 dev->dev_addr[0] = (u8)(mac_low32);
1928 dev->dev_addr[1] = (u8)(mac_low32 >> 8);
1929 dev->dev_addr[2] = (u8)(mac_low32 >> 16);
1930 dev->dev_addr[3] = (u8)(mac_low32 >> 24);
1931 dev->dev_addr[4] = (u8)(mac_high16);
1932 dev->dev_addr[5] = (u8)(mac_high16 >> 8);
1933}
1934
fd9abb3d
SG		 1935/* Initializing private device structures, only called from probe */
1936static int __devinit smsc911x_init(struct net_device *dev)
1937{
1938 struct smsc911x_data *pdata = netdev_priv(dev);
1939 unsigned int byte_test;
3ac3546e 1940 unsigned int to = 100;
fd9abb3d 1941
dffc6b24
JP		 1942 SMSC_TRACE(pdata, probe, "Driver Parameters:");
1943 SMSC_TRACE(pdata, probe, "LAN base: 0x%08lX",
1944 (unsigned long)pdata->ioaddr);
1945 SMSC_TRACE(pdata, probe, "IRQ: %d", dev->irq);
1946 SMSC_TRACE(pdata, probe, "PHY will be autodetected.");
fd9abb3d 1947
fd9abb3d 1948 spin_lock_init(&pdata->dev_lock);
35a67edf 1949 spin_lock_init(&pdata->mac_lock);
fd9abb3d
SG		 1950
1951 if (pdata->ioaddr == 0) {
dffc6b24 1952 SMSC_WARN(pdata, probe, "pdata->ioaddr: 0x00000000");
fd9abb3d
SG		 1953 return -ENODEV;
1954 }
1955
3ac3546e
RM		 1956 /*
1957 * poll the READY bit in PMT_CTRL. Any other access to the device is
1958 * forbidden while this bit isn't set. Try for 100ms
1959 */
1960 while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to)
1961 udelay(1000);
1962 if (to == 0) {
1963 pr_err("Device not READY in 100ms aborting\n");
1964 return -ENODEV;
1965 }
1966
fd9abb3d
SG		 1967 /* Check byte ordering */
1968 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
dffc6b24 1969 SMSC_TRACE(pdata, probe, "BYTE_TEST: 0x%08X", byte_test);
fd9abb3d 1970 if (byte_test == 0x43218765) {
dffc6b24
JP		 1971 SMSC_TRACE(pdata, probe, "BYTE_TEST looks swapped, "
1972 "applying WORD_SWAP");
fd9abb3d
SG		 1973 smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff);
1974
1975 /* 1 dummy read of BYTE_TEST is needed after a write to
1976 * WORD_SWAP before its contents are valid */
1977 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1978
1979 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1980 }
1981
1982 if (byte_test != 0x87654321) {
dffc6b24 1983 SMSC_WARN(pdata, drv, "BYTE_TEST: 0x%08X", byte_test);
fd9abb3d 1984 if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) {
dffc6b24
JP		 1985 SMSC_WARN(pdata, probe,
1986 "top 16 bits equal to bottom 16 bits");
1987 SMSC_TRACE(pdata, probe,
1988 "This may mean the chip is set "
1989 "for 32 bit while the bus is reading 16 bit");
fd9abb3d
SG		 1990 }
1991 return -ENODEV;
1992 }
1993
1994 /* Default generation to zero (all workarounds apply) */
1995 pdata->generation = 0;
1996
1997 pdata->idrev = smsc911x_reg_read(pdata, ID_REV);
1998 switch (pdata->idrev & 0xFFFF0000) {
1999 case 0x01180000:
2000 case 0x01170000:
2001 case 0x01160000:
2002 case 0x01150000:
28c21379 2003 case 0x218A0000:
fd9abb3d
SG		 2004 /* LAN911[5678] family */
2005 pdata->generation = pdata->idrev & 0x0000FFFF;
2006 break;
2007
2008 case 0x118A0000:
2009 case 0x117A0000:
2010 case 0x116A0000:
2011 case 0x115A0000:
2012 /* LAN921[5678] family */
2013 pdata->generation = 3;
2014 break;
2015
2016 case 0x92100000:
2017 case 0x92110000:
2018 case 0x92200000:
2019 case 0x92210000:
2020 /* LAN9210/LAN9211/LAN9220/LAN9221 */
2021 pdata->generation = 4;
2022 break;
2023
2024 default:
dffc6b24
JP		 2025 SMSC_WARN(pdata, probe, "LAN911x not identified, idrev: 0x%08X",
2026 pdata->idrev);
fd9abb3d
SG		 2027 return -ENODEV;
2028 }
2029
dffc6b24
JP		 2030 SMSC_TRACE(pdata, probe,
2031 "LAN911x identified, idrev: 0x%08X, generation: %d",
2032 pdata->idrev, pdata->generation);
fd9abb3d
SG		 2033
2034 if (pdata->generation == 0)
dffc6b24
JP		 2035 SMSC_WARN(pdata, probe,
2036 "This driver is not intended for this chip revision");
fd9abb3d 2037
31f45747
SG		 2038 /* workaround for platforms without an eeprom, where the mac address
2039 * is stored elsewhere and set by the bootloader. This saves the
2040 * mac address before resetting the device */
35a67edf
EBS		 2041 if (pdata->config.flags & SMSC911X_SAVE_MAC_ADDRESS) {
2042 spin_lock_irq(&pdata->mac_lock);
31f45747 2043 smsc911x_read_mac_address(dev);
35a67edf
EBS		 2044 spin_unlock_irq(&pdata->mac_lock);
2045 }
31f45747 2046
fd9abb3d
SG		 2047 /* Reset the LAN911x */
2048 if (smsc911x_soft_reset(pdata))
2049 return -ENODEV;
2050
2051 /* Disable all interrupt sources until we bring the device up */
2052 smsc911x_reg_write(pdata, INT_EN, 0);
2053
2054 ether_setup(dev);
fd9abb3d 2055 dev->flags |= IFF_MULTICAST;
fd9abb3d 2056 netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT);
631b7568 2057 dev->netdev_ops = &smsc911x_netdev_ops;
fd9abb3d
SG		 2058 dev->ethtool_ops = &smsc911x_ethtool_ops;
2059
fd9abb3d
SG		 2060 return 0;
2061}
2062
2063static int __devexit smsc911x_drv_remove(struct platform_device *pdev)
2064{
2065 struct net_device *dev;
2066 struct smsc911x_data *pdata;
2067 struct resource *res;
2068
2069 dev = platform_get_drvdata(pdev);
2070 BUG_ON(!dev);
2071 pdata = netdev_priv(dev);
2072 BUG_ON(!pdata);
2073 BUG_ON(!pdata->ioaddr);
2074 BUG_ON(!pdata->phy_dev);
2075
dffc6b24 2076 SMSC_TRACE(pdata, ifdown, "Stopping driver");
fd9abb3d
SG		 2077
2078 phy_disconnect(pdata->phy_dev);
2079 pdata->phy_dev = NULL;
2080 mdiobus_unregister(pdata->mii_bus);
2081 mdiobus_free(pdata->mii_bus);
2082
2083 platform_set_drvdata(pdev, NULL);
2084 unregister_netdev(dev);
2085 free_irq(dev->irq, dev);
2086 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2087 "smsc911x-memory");
2088 if (!res)
d4522739 2089 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
fd9abb3d 2090
39424539 2091 release_mem_region(res->start, resource_size(res));
fd9abb3d
SG		 2092
2093 iounmap(pdata->ioaddr);
2094
2095 free_netdev(dev);
2096
2097 return 0;
2098}
2099
c326de88
MP		 2100/* standard register acces */
2101static const struct smsc911x_ops standard_smsc911x_ops = {
2102 .reg_read = __smsc911x_reg_read,
2103 .reg_write = __smsc911x_reg_write,
2104 .rx_readfifo = smsc911x_rx_readfifo,
2105 .tx_writefifo = smsc911x_tx_writefifo,
2106};
2107
2108/* shifted register access */
2109static const struct smsc911x_ops shifted_smsc911x_ops = {
2110 .reg_read = __smsc911x_reg_read_shift,
2111 .reg_write = __smsc911x_reg_write_shift,
2112 .rx_readfifo = smsc911x_rx_readfifo_shift,
2113 .tx_writefifo = smsc911x_tx_writefifo_shift,
2114};
2115
79f88ee9
SG		 2116#ifdef CONFIG_OF
2117static int __devinit smsc911x_probe_config_dt(
2118 struct smsc911x_platform_config *config,
2119 struct device_node *np)
2120{
2121 const char *mac;
2122 u32 width = 0;
2123
2124 if (!np)
2125 return -ENODEV;
2126
2127 config->phy_interface = of_get_phy_mode(np);
2128
2129 mac = of_get_mac_address(np);
2130 if (mac)
2131 memcpy(config->mac, mac, ETH_ALEN);
2132
2133 of_property_read_u32(np, "reg-shift", &config->shift);
2134
2135 of_property_read_u32(np, "reg-io-width", &width);
2136 if (width == 4)
2137 config->flags |= SMSC911X_USE_32BIT;
f26cd41a
DM		 2138 else
2139 config->flags |= SMSC911X_USE_16BIT;
79f88ee9
SG		 2140
2141 if (of_get_property(np, "smsc,irq-active-high", NULL))
2142 config->irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH;
2143
2144 if (of_get_property(np, "smsc,irq-push-pull", NULL))
2145 config->irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL;
2146
2147 if (of_get_property(np, "smsc,force-internal-phy", NULL))
2148 config->flags |= SMSC911X_FORCE_INTERNAL_PHY;
2149
2150 if (of_get_property(np, "smsc,force-external-phy", NULL))
2151 config->flags |= SMSC911X_FORCE_EXTERNAL_PHY;
2152
2153 if (of_get_property(np, "smsc,save-mac-address", NULL))
2154 config->flags |= SMSC911X_SAVE_MAC_ADDRESS;
2155
2156 return 0;
2157}
2158#else
2159static inline int smsc911x_probe_config_dt(
2160 struct smsc911x_platform_config *config,
2161 struct device_node *np)
2162{
2163 return -ENODEV;
2164}
2165#endif /* CONFIG_OF */
2166
fd9abb3d
SG		 2167static int __devinit smsc911x_drv_probe(struct platform_device *pdev)
2168{
79f88ee9 2169 struct device_node *np = pdev->dev.of_node;
fd9abb3d
SG		 2170 struct net_device *dev;
2171 struct smsc911x_data *pdata;
2107fb8b 2172 struct smsc911x_platform_config *config = pdev->dev.platform_data;
61307ed8 2173 struct resource *res, *irq_res;
fd9abb3d 2174 unsigned int intcfg = 0;
61307ed8 2175 int res_size, irq_flags;
fd9abb3d 2176 int retval;
fd9abb3d 2177
dffc6b24 2178 pr_info("Driver version %s\n", SMSC_DRV_VERSION);
fd9abb3d
SG		 2179
2180 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2181 "smsc911x-memory");
2182 if (!res)
2183 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2184 if (!res) {
dffc6b24 2185 pr_warn("Could not allocate resource\n");
fd9abb3d
SG		 2186 retval = -ENODEV;
2187 goto out_0;
2188 }
39424539 2189 res_size = resource_size(res);
fd9abb3d 2190
61307ed8
SG		 2191 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2192 if (!irq_res) {
dffc6b24 2193 pr_warn("Could not allocate irq resource\n");
61307ed8
SG		 2194 retval = -ENODEV;
2195 goto out_0;
2196 }
2197
fd9abb3d
SG		 2198 if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) {
2199 retval = -EBUSY;
2200 goto out_0;
2201 }
2202
2203 dev = alloc_etherdev(sizeof(struct smsc911x_data));
2204 if (!dev) {
dffc6b24 2205 pr_warn("Could not allocate device\n");
fd9abb3d
SG		 2206 retval = -ENOMEM;
2207 goto out_release_io_1;
2208 }
2209
2210 SET_NETDEV_DEV(dev, &pdev->dev);
2211
2212 pdata = netdev_priv(dev);
2213
61307ed8
SG		 2214 dev->irq = irq_res->start;
2215 irq_flags = irq_res->flags & IRQF_TRIGGER_MASK;
fd9abb3d
SG		 2216 pdata->ioaddr = ioremap_nocache(res->start, res_size);
2217
fd9abb3d
SG		 2218 pdata->dev = dev;
2219 pdata->msg_enable = ((1 << debug) - 1);
2220
2221 if (pdata->ioaddr == NULL) {
dffc6b24 2222 SMSC_WARN(pdata, probe, "Error smsc911x base address invalid");
fd9abb3d
SG		 2223 retval = -ENOMEM;
2224 goto out_free_netdev_2;
2225 }
2226
79f88ee9
SG		 2227 retval = smsc911x_probe_config_dt(&pdata->config, np);
2228 if (retval && config) {
2229 /* copy config parameters across to pdata */
2230 memcpy(&pdata->config, config, sizeof(pdata->config));
2231 retval = 0;
2232 }
2233
2234 if (retval) {
2235 SMSC_WARN(pdata, probe, "Error smsc911x config not found");
2236 goto out_unmap_io_3;
2237 }
2238
c326de88
MP		 2239 /* assume standard, non-shifted, access to HW registers */
2240 pdata->ops = &standard_smsc911x_ops;
2241 /* apply the right access if shifting is needed */
79f88ee9 2242 if (pdata->config.shift)
c326de88
MP		 2243 pdata->ops = &shifted_smsc911x_ops;
2244
fd9abb3d
SG		 2245 retval = smsc911x_init(dev);
2246 if (retval < 0)
2247 goto out_unmap_io_3;
2248
2249 /* configure irq polarity and type before connecting isr */
2107fb8b 2250 if (pdata->config.irq_polarity == SMSC911X_IRQ_POLARITY_ACTIVE_HIGH)
fd9abb3d
SG		 2251 intcfg |= INT_CFG_IRQ_POL_;
2252
2107fb8b 2253 if (pdata->config.irq_type == SMSC911X_IRQ_TYPE_PUSH_PULL)
fd9abb3d
SG		 2254 intcfg |= INT_CFG_IRQ_TYPE_;
2255
2256 smsc911x_reg_write(pdata, INT_CFG, intcfg);
2257
2258 /* Ensure interrupts are globally disabled before connecting ISR */
2259 smsc911x_reg_write(pdata, INT_EN, 0);
2260 smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
2261
61307ed8 2262 retval = request_irq(dev->irq, smsc911x_irqhandler,
e81259b4 2263 irq_flags | IRQF_SHARED, dev->name, dev);
fd9abb3d 2264 if (retval) {
dffc6b24
JP		 2265 SMSC_WARN(pdata, probe,
2266 "Unable to claim requested irq: %d", dev->irq);
fd9abb3d
SG		 2267 goto out_unmap_io_3;
2268 }
2269
2270 platform_set_drvdata(pdev, dev);
2271
2272 retval = register_netdev(dev);
2273 if (retval) {
dffc6b24 2274 SMSC_WARN(pdata, probe, "Error %i registering device", retval);
fd9abb3d
SG		 2275 goto out_unset_drvdata_4;
2276 } else {
dffc6b24
JP		 2277 SMSC_TRACE(pdata, probe,
2278 "Network interface: \"%s\"", dev->name);
fd9abb3d
SG		 2279 }
2280
fd9abb3d
SG		 2281 retval = smsc911x_mii_init(pdev, dev);
2282 if (retval) {
dffc6b24 2283 SMSC_WARN(pdata, probe, "Error %i initialising mii", retval);
fd9abb3d
SG		 2284 goto out_unregister_netdev_5;
2285 }
2286
2287 spin_lock_irq(&pdata->mac_lock);
2288
2289 /* Check if mac address has been specified when bringing interface up */
2290 if (is_valid_ether_addr(dev->dev_addr)) {
225ddf49 2291 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
dffc6b24
JP		 2292 SMSC_TRACE(pdata, probe,
2293 "MAC Address is specified by configuration");
aace4959
ML		 2294 } else if (is_valid_ether_addr(pdata->config.mac)) {
2295 memcpy(dev->dev_addr, pdata->config.mac, 6);
dffc6b24
JP		 2296 SMSC_TRACE(pdata, probe,
2297 "MAC Address specified by platform data");
fd9abb3d
SG		 2298 } else {
2299 /* Try reading mac address from device. if EEPROM is present
2300 * it will already have been set */
62747cd2 2301 smsc_get_mac(dev);
fd9abb3d
SG		 2302
2303 if (is_valid_ether_addr(dev->dev_addr)) {
2304 /* eeprom values are valid so use them */
dffc6b24
JP		 2305 SMSC_TRACE(pdata, probe,
2306 "Mac Address is read from LAN911x EEPROM");
fd9abb3d
SG		 2307 } else {
2308 /* eeprom values are invalid, generate random MAC */
2309 random_ether_addr(dev->dev_addr);
225ddf49 2310 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
dffc6b24
JP		 2311 SMSC_TRACE(pdata, probe,
2312 "MAC Address is set to random_ether_addr");
fd9abb3d
SG		 2313 }
2314 }
2315
2316 spin_unlock_irq(&pdata->mac_lock);
2317
dffc6b24 2318 netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr);
fd9abb3d
SG		 2319
2320 return 0;
2321
2322out_unregister_netdev_5:
2323 unregister_netdev(dev);
2324out_unset_drvdata_4:
2325 platform_set_drvdata(pdev, NULL);
2326 free_irq(dev->irq, dev);
2327out_unmap_io_3:
2328 iounmap(pdata->ioaddr);
2329out_free_netdev_2:
2330 free_netdev(dev);
2331out_release_io_1:
39424539 2332 release_mem_region(res->start, resource_size(res));
fd9abb3d
SG		 2333out_0:
2334 return retval;
2335}
2336
b6907b0c
DM		 2337#ifdef CONFIG_PM
2338/* This implementation assumes the devices remains powered on its VDDVARIO
2339 * pins during suspend. */
2340
6cb87823
DM		 2341/* TODO: implement freeze/thaw callbacks for hibernation.*/
2342
2343static int smsc911x_suspend(struct device *dev)
b6907b0c 2344{
6cb87823
DM		 2345 struct net_device *ndev = dev_get_drvdata(dev);
2346 struct smsc911x_data *pdata = netdev_priv(ndev);
b6907b0c
DM		 2347
2348 /* enable wake on LAN, energy detection and the external PME
2349 * signal. */
2350 smsc911x_reg_write(pdata, PMT_CTRL,
2351 PMT_CTRL_PM_MODE_D1_ | PMT_CTRL_WOL_EN_ |
2352 PMT_CTRL_ED_EN_ | PMT_CTRL_PME_EN_);
2353
2354 return 0;
2355}
2356
6cb87823 2357static int smsc911x_resume(struct device *dev)
b6907b0c 2358{
6cb87823
DM		 2359 struct net_device *ndev = dev_get_drvdata(dev);
2360 struct smsc911x_data *pdata = netdev_priv(ndev);
b6907b0c
DM		 2361 unsigned int to = 100;
2362
2363 /* Note 3.11 from the datasheet:
2364 * "When the LAN9220 is in a power saving state, a write of any
2365 * data to the BYTE_TEST register will wake-up the device."
2366 */
2367 smsc911x_reg_write(pdata, BYTE_TEST, 0);
2368
2369 /* poll the READY bit in PMT_CTRL. Any other access to the device is
2370 * forbidden while this bit isn't set. Try for 100ms and return -EIO
2371 * if it failed. */
2372 while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to)
2373 udelay(1000);
2374
2375 return (to == 0) ? -EIO : 0;
2376}
2377
47145210 2378static const struct dev_pm_ops smsc911x_pm_ops = {
6cb87823
DM		 2379 .suspend = smsc911x_suspend,
2380 .resume = smsc911x_resume,
2381};
2382
2383#define SMSC911X_PM_OPS (&smsc911x_pm_ops)
2384
b6907b0c 2385#else
6cb87823 2386#define SMSC911X_PM_OPS NULL
b6907b0c
DM		 2387#endif
2388
79f88ee9
SG		 2389static const struct of_device_id smsc911x_dt_ids[] = {
2390 { .compatible = "smsc,lan9115", },
2391 { /* sentinel */ }
2392};
2393MODULE_DEVICE_TABLE(of, smsc911x_dt_ids);
2394
fd9abb3d
SG		 2395static struct platform_driver smsc911x_driver = {
2396 .probe = smsc911x_drv_probe,
df911e2d 2397 .remove = __devexit_p(smsc911x_drv_remove),
fd9abb3d 2398 .driver = {
6cb87823
DM		 2399 .name = SMSC_CHIPNAME,
2400 .owner = THIS_MODULE,
2401 .pm = SMSC911X_PM_OPS,
79f88ee9 2402 .of_match_table = smsc911x_dt_ids,
fd9abb3d
SG		 2403 },
2404};
2405
2406/* Entry point for loading the module */
2407static int __init smsc911x_init_module(void)
2408{
62747cd2 2409 SMSC_INITIALIZE();
fd9abb3d
SG		 2410 return platform_driver_register(&smsc911x_driver);
2411}
2412
2413/* entry point for unloading the module */
2414static void __exit smsc911x_cleanup_module(void)
2415{
2416 platform_driver_unregister(&smsc911x_driver);
2417}
2418
2419module_init(smsc911x_init_module);
2420module_exit(smsc911x_cleanup_module);
Linux 6.x block layer and io_uring tree(s)