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include/linux/skbuff.h: move CONFIG_XFRM check inside the skb_sec_path()
[linux-2.6-block.git] / drivers / net / ethernet / smsc / smsc911x.c
CommitLineData
fd9abb3d
SG		 1/***************************************************************************
2 *
3 * Copyright (C) 2004-2008 SMSC
4 * Copyright (C) 2005-2008 ARM
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 *
20 ***************************************************************************
21 * Rewritten, heavily based on smsc911x simple driver by SMSC.
22 * Partly uses io macros from smc91x.c by Nicolas Pitre
23 *
24 * Supported devices:
25 * LAN9115, LAN9116, LAN9117, LAN9118
26 * LAN9215, LAN9216, LAN9217, LAN9218
27 * LAN9210, LAN9211
28 * LAN9220, LAN9221
28c21379 29 * LAN89218
fd9abb3d
SG		 30 *
31 */
32
dffc6b24
JP		 33#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
fd9abb3d 35#include <linux/crc32.h>
b6c23019 36#include <linux/clk.h>
fd9abb3d
SG		 37#include <linux/delay.h>
38#include <linux/errno.h>
39#include <linux/etherdevice.h>
40#include <linux/ethtool.h>
41#include <linux/init.h>
a6b7a407 42#include <linux/interrupt.h>
fd9abb3d
SG		 43#include <linux/ioport.h>
44#include <linux/kernel.h>
45#include <linux/module.h>
46#include <linux/netdevice.h>
47#include <linux/platform_device.h>
c7e963f6 48#include <linux/regulator/consumer.h>
fd9abb3d 49#include <linux/sched.h>
fd9abb3d 50#include <linux/timer.h>
fd9abb3d
SG		 51#include <linux/bug.h>
52#include <linux/bitops.h>
53#include <linux/irq.h>
54#include <linux/io.h>
833cc67c 55#include <linux/swab.h>
fd9abb3d
SG		 56#include <linux/phy.h>
57#include <linux/smsc911x.h>
6cb87823 58#include <linux/device.h>
79f88ee9
SG		 59#include <linux/of.h>
60#include <linux/of_device.h>
61#include <linux/of_gpio.h>
62#include <linux/of_net.h>
fd9abb3d
SG		 63#include "smsc911x.h"
64
65#define SMSC_CHIPNAME "smsc911x"
66#define SMSC_MDIONAME "smsc911x-mdio"
67#define SMSC_DRV_VERSION "2008-10-21"
68
69MODULE_LICENSE("GPL");
70MODULE_VERSION(SMSC_DRV_VERSION);
62038e4a 71MODULE_ALIAS("platform:smsc911x");
fd9abb3d
SG		 72
73#if USE_DEBUG > 0
74static int debug = 16;
75#else
76static int debug = 3;
77#endif
78
79module_param(debug, int, 0);
80MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
81
c326de88
MP		 82struct smsc911x_data;
83
84struct smsc911x_ops {
85 u32 (*reg_read)(struct smsc911x_data *pdata, u32 reg);
86 void (*reg_write)(struct smsc911x_data *pdata, u32 reg, u32 val);
87 void (*rx_readfifo)(struct smsc911x_data *pdata,
88 unsigned int *buf, unsigned int wordcount);
89 void (*tx_writefifo)(struct smsc911x_data *pdata,
90 unsigned int *buf, unsigned int wordcount);
91};
92
c7e963f6
RM		 93#define SMSC911X_NUM_SUPPLIES 2
94
fd9abb3d
SG		 95struct smsc911x_data {
96 void __iomem *ioaddr;
97
98 unsigned int idrev;
99
100 /* used to decide which workarounds apply */
101 unsigned int generation;
102
103 /* device configuration (copied from platform_data during probe) */
2107fb8b 104 struct smsc911x_platform_config config;
fd9abb3d
SG		 105
106 /* This needs to be acquired before calling any of below:
107 * smsc911x_mac_read(), smsc911x_mac_write()
108 */
109 spinlock_t mac_lock;
110
492c5d94 111 /* spinlock to ensure register accesses are serialised */
fd9abb3d 112 spinlock_t dev_lock;
fd9abb3d
SG		 113
114 struct phy_device *phy_dev;
115 struct mii_bus *mii_bus;
116 int phy_irq[PHY_MAX_ADDR];
117 unsigned int using_extphy;
118 int last_duplex;
119 int last_carrier;
120
121 u32 msg_enable;
122 unsigned int gpio_setting;
123 unsigned int gpio_orig_setting;
124 struct net_device *dev;
125 struct napi_struct napi;
126
127 unsigned int software_irq_signal;
128
129#ifdef USE_PHY_WORK_AROUND
130#define MIN_PACKET_SIZE (64)
131 char loopback_tx_pkt[MIN_PACKET_SIZE];
132 char loopback_rx_pkt[MIN_PACKET_SIZE];
133 unsigned int resetcount;
134#endif
135
136 /* Members for Multicast filter workaround */
137 unsigned int multicast_update_pending;
138 unsigned int set_bits_mask;
139 unsigned int clear_bits_mask;
140 unsigned int hashhi;
141 unsigned int hashlo;
c326de88
MP		 142
143 /* register access functions */
144 const struct smsc911x_ops *ops;
c7e963f6
RM		 145
146 /* regulators */
147 struct regulator_bulk_data supplies[SMSC911X_NUM_SUPPLIES];
b6c23019
LJ		 148
149 /* clock */
150 struct clk *clk;
fd9abb3d
SG		 151};
152
c326de88
MP		 153/* Easy access to information */
154#define __smsc_shift(pdata, reg) ((reg) << ((pdata)->config.shift))
155
492c5d94 156static inline u32 __smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
fd9abb3d 157{
2107fb8b
SG		 158 if (pdata->config.flags & SMSC911X_USE_32BIT)
159 return readl(pdata->ioaddr + reg);
160
492c5d94
CM		 161 if (pdata->config.flags & SMSC911X_USE_16BIT)
162 return ((readw(pdata->ioaddr + reg) & 0xFFFF) |
2107fb8b 163 ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16));
fd9abb3d 164
2107fb8b 165 BUG();
702403af 166 return 0;
fd9abb3d
SG		 167}
168
c326de88
MP		 169static inline u32
170__smsc911x_reg_read_shift(struct smsc911x_data *pdata, u32 reg)
171{
172 if (pdata->config.flags & SMSC911X_USE_32BIT)
173 return readl(pdata->ioaddr + __smsc_shift(pdata, reg));
174
175 if (pdata->config.flags & SMSC911X_USE_16BIT)
176 return (readw(pdata->ioaddr +
177 __smsc_shift(pdata, reg)) & 0xFFFF) |
178 ((readw(pdata->ioaddr +
179 __smsc_shift(pdata, reg + 2)) & 0xFFFF) << 16);
180
181 BUG();
182 return 0;
183}
184
492c5d94
CM		 185static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
186{
187 u32 data;
188 unsigned long flags;
189
190 spin_lock_irqsave(&pdata->dev_lock, flags);
c326de88 191 data = pdata->ops->reg_read(pdata, reg);
492c5d94
CM		 192 spin_unlock_irqrestore(&pdata->dev_lock, flags);
193
194 return data;
195}
196
197static inline void __smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
198 u32 val)
fd9abb3d 199{
2107fb8b
SG		 200 if (pdata->config.flags & SMSC911X_USE_32BIT) {
201 writel(val, pdata->ioaddr + reg);
202 return;
203 }
204
205 if (pdata->config.flags & SMSC911X_USE_16BIT) {
2107fb8b
SG		 206 writew(val & 0xFFFF, pdata->ioaddr + reg);
207 writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2);
2107fb8b
SG		 208 return;
209 }
fd9abb3d 210
2107fb8b 211 BUG();
fd9abb3d
SG		 212}
213
c326de88
MP		 214static inline void
215__smsc911x_reg_write_shift(struct smsc911x_data *pdata, u32 reg, u32 val)
216{
217 if (pdata->config.flags & SMSC911X_USE_32BIT) {
218 writel(val, pdata->ioaddr + __smsc_shift(pdata, reg));
219 return;
220 }
221
222 if (pdata->config.flags & SMSC911X_USE_16BIT) {
223 writew(val & 0xFFFF,
224 pdata->ioaddr + __smsc_shift(pdata, reg));
225 writew((val >> 16) & 0xFFFF,
226 pdata->ioaddr + __smsc_shift(pdata, reg + 2));
227 return;
228 }
229
230 BUG();
231}
232
492c5d94
CM		 233static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
234 u32 val)
235{
236 unsigned long flags;
237
238 spin_lock_irqsave(&pdata->dev_lock, flags);
c326de88 239 pdata->ops->reg_write(pdata, reg, val);
492c5d94
CM		 240 spin_unlock_irqrestore(&pdata->dev_lock, flags);
241}
242
fd9abb3d
SG		 243/* Writes a packet to the TX_DATA_FIFO */
244static inline void
245smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf,
246 unsigned int wordcount)
247{
492c5d94
CM		 248 unsigned long flags;
249
250 spin_lock_irqsave(&pdata->dev_lock, flags);
251
833cc67c
MD		 252 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
253 while (wordcount--)
492c5d94
CM		 254 __smsc911x_reg_write(pdata, TX_DATA_FIFO,
255 swab32(*buf++));
256 goto out;
833cc67c
MD		 257 }
258
2107fb8b 259 if (pdata->config.flags & SMSC911X_USE_32BIT) {
2925f6c0 260 iowrite32_rep(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount);
492c5d94 261 goto out;
2107fb8b
SG		 262 }
263
264 if (pdata->config.flags & SMSC911X_USE_16BIT) {
265 while (wordcount--)
492c5d94
CM		 266 __smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++);
267 goto out;
2107fb8b
SG		 268 }
269
270 BUG();
492c5d94
CM		 271out:
272 spin_unlock_irqrestore(&pdata->dev_lock, flags);
fd9abb3d
SG		 273}
274
c326de88
MP		 275/* Writes a packet to the TX_DATA_FIFO - shifted version */
276static inline void
277smsc911x_tx_writefifo_shift(struct smsc911x_data *pdata, unsigned int *buf,
278 unsigned int wordcount)
279{
280 unsigned long flags;
281
282 spin_lock_irqsave(&pdata->dev_lock, flags);
283
284 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
285 while (wordcount--)
286 __smsc911x_reg_write_shift(pdata, TX_DATA_FIFO,
287 swab32(*buf++));
288 goto out;
289 }
290
291 if (pdata->config.flags & SMSC911X_USE_32BIT) {
2925f6c0 292 iowrite32_rep(pdata->ioaddr + __smsc_shift(pdata,
c326de88
MP		 293 TX_DATA_FIFO), buf, wordcount);
294 goto out;
295 }
296
297 if (pdata->config.flags & SMSC911X_USE_16BIT) {
298 while (wordcount--)
299 __smsc911x_reg_write_shift(pdata,
300 TX_DATA_FIFO, *buf++);
301 goto out;
302 }
303
304 BUG();
305out:
306 spin_unlock_irqrestore(&pdata->dev_lock, flags);
307}
308
fd9abb3d
SG		 309/* Reads a packet out of the RX_DATA_FIFO */
310static inline void
311smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf,
312 unsigned int wordcount)
313{
492c5d94
CM		 314 unsigned long flags;
315
316 spin_lock_irqsave(&pdata->dev_lock, flags);
317
833cc67c
MD		 318 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
319 while (wordcount--)
492c5d94
CM		 320 *buf++ = swab32(__smsc911x_reg_read(pdata,
321 RX_DATA_FIFO));
322 goto out;
833cc67c
MD		 323 }
324
2107fb8b 325 if (pdata->config.flags & SMSC911X_USE_32BIT) {
2925f6c0 326 ioread32_rep(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount);
492c5d94 327 goto out;
2107fb8b 328 }
fd9abb3d 329
2107fb8b
SG		 330 if (pdata->config.flags & SMSC911X_USE_16BIT) {
331 while (wordcount--)
492c5d94
CM		 332 *buf++ = __smsc911x_reg_read(pdata, RX_DATA_FIFO);
333 goto out;
2107fb8b
SG		 334 }
335
336 BUG();
492c5d94
CM		 337out:
338 spin_unlock_irqrestore(&pdata->dev_lock, flags);
2107fb8b 339}
fd9abb3d 340
c326de88
MP		 341/* Reads a packet out of the RX_DATA_FIFO - shifted version */
342static inline void
343smsc911x_rx_readfifo_shift(struct smsc911x_data *pdata, unsigned int *buf,
344 unsigned int wordcount)
345{
346 unsigned long flags;
347
348 spin_lock_irqsave(&pdata->dev_lock, flags);
349
350 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
351 while (wordcount--)
352 *buf++ = swab32(__smsc911x_reg_read_shift(pdata,
353 RX_DATA_FIFO));
354 goto out;
355 }
356
357 if (pdata->config.flags & SMSC911X_USE_32BIT) {
2925f6c0 358 ioread32_rep(pdata->ioaddr + __smsc_shift(pdata,
c326de88
MP		 359 RX_DATA_FIFO), buf, wordcount);
360 goto out;
361 }
362
363 if (pdata->config.flags & SMSC911X_USE_16BIT) {
364 while (wordcount--)
365 *buf++ = __smsc911x_reg_read_shift(pdata,
366 RX_DATA_FIFO);
367 goto out;
368 }
369
370 BUG();
371out:
372 spin_unlock_irqrestore(&pdata->dev_lock, flags);
373}
374
c7e963f6 375/*
b6c23019 376 * enable regulator and clock resources.
c7e963f6
RM		 377 */
378static int smsc911x_enable_resources(struct platform_device *pdev)
379{
380 struct net_device *ndev = platform_get_drvdata(pdev);
381 struct smsc911x_data *pdata = netdev_priv(ndev);
382 int ret = 0;
383
384 ret = regulator_bulk_enable(ARRAY_SIZE(pdata->supplies),
385 pdata->supplies);
386 if (ret)
387 netdev_err(ndev, "failed to enable regulators %d\n",
388 ret);
b6c23019
LJ		 389
390 if (!IS_ERR(pdata->clk)) {
391 ret = clk_prepare_enable(pdata->clk);
392 if (ret < 0)
393 netdev_err(ndev, "failed to enable clock %d\n", ret);
394 }
395
c7e963f6
RM		 396 return ret;
397}
398
399/*
400 * disable resources, currently just regulators.
401 */
402static int smsc911x_disable_resources(struct platform_device *pdev)
403{
404 struct net_device *ndev = platform_get_drvdata(pdev);
405 struct smsc911x_data *pdata = netdev_priv(ndev);
406 int ret = 0;
407
408 ret = regulator_bulk_disable(ARRAY_SIZE(pdata->supplies),
409 pdata->supplies);
b6c23019
LJ		 410
411 if (!IS_ERR(pdata->clk))
412 clk_disable_unprepare(pdata->clk);
413
c7e963f6
RM		 414 return ret;
415}
416
417/*
418 * Request resources, currently just regulators.
419 *
420 * The SMSC911x has two power pins: vddvario and vdd33a, in designs where
421 * these are not always-on we need to request regulators to be turned on
422 * before we can try to access the device registers.
423 */
424static int smsc911x_request_resources(struct platform_device *pdev)
425{
426 struct net_device *ndev = platform_get_drvdata(pdev);
427 struct smsc911x_data *pdata = netdev_priv(ndev);
428 int ret = 0;
429
430 /* Request regulators */
431 pdata->supplies[0].supply = "vdd33a";
432 pdata->supplies[1].supply = "vddvario";
433 ret = regulator_bulk_get(&pdev->dev,
434 ARRAY_SIZE(pdata->supplies),
435 pdata->supplies);
436 if (ret)
437 netdev_err(ndev, "couldn't get regulators %d\n",
438 ret);
b6c23019
LJ		 439
440 /* Request clock */
441 pdata->clk = clk_get(&pdev->dev, NULL);
442 if (IS_ERR(pdata->clk))
443 netdev_warn(ndev, "couldn't get clock %li\n", PTR_ERR(pdata->clk));
444
c7e963f6
RM		 445 return ret;
446}
447
448/*
449 * Free resources, currently just regulators.
450 *
451 */
452static void smsc911x_free_resources(struct platform_device *pdev)
453{
454 struct net_device *ndev = platform_get_drvdata(pdev);
455 struct smsc911x_data *pdata = netdev_priv(ndev);
456
457 /* Free regulators */
458 regulator_bulk_free(ARRAY_SIZE(pdata->supplies),
459 pdata->supplies);
b6c23019
LJ		 460
461 /* Free clock */
462 if (!IS_ERR(pdata->clk)) {
463 clk_put(pdata->clk);
464 pdata->clk = NULL;
465 }
c7e963f6
RM		 466}
467
fd9abb3d
SG		 468/* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read
469 * and smsc911x_mac_write, so assumes mac_lock is held */
470static int smsc911x_mac_complete(struct smsc911x_data *pdata)
471{
472 int i;
473 u32 val;
474
475 SMSC_ASSERT_MAC_LOCK(pdata);
476
477 for (i = 0; i < 40; i++) {
478 val = smsc911x_reg_read(pdata, MAC_CSR_CMD);
479 if (!(val & MAC_CSR_CMD_CSR_BUSY_))
480 return 0;
481 }
dffc6b24
JP		 482 SMSC_WARN(pdata, hw, "Timed out waiting for MAC not BUSY. "
483 "MAC_CSR_CMD: 0x%08X", val);
fd9abb3d
SG		 484 return -EIO;
485}
486
487/* Fetches a MAC register value. Assumes mac_lock is acquired */
488static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset)
489{
490 unsigned int temp;
491
492 SMSC_ASSERT_MAC_LOCK(pdata);
493
494 temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
495 if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
dffc6b24 496 SMSC_WARN(pdata, hw, "MAC busy at entry");
fd9abb3d
SG		 497 return 0xFFFFFFFF;
498 }
499
500 /* Send the MAC cmd */
501 smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
502 MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_));
503
504 /* Workaround for hardware read-after-write restriction */
505 temp = smsc911x_reg_read(pdata, BYTE_TEST);
506
507 /* Wait for the read to complete */
508 if (likely(smsc911x_mac_complete(pdata) == 0))
509 return smsc911x_reg_read(pdata, MAC_CSR_DATA);
510
dffc6b24 511 SMSC_WARN(pdata, hw, "MAC busy after read");
fd9abb3d
SG		 512 return 0xFFFFFFFF;
513}
514
515/* Set a mac register, mac_lock must be acquired before calling */
516static void smsc911x_mac_write(struct smsc911x_data *pdata,
517 unsigned int offset, u32 val)
518{
519 unsigned int temp;
520
521 SMSC_ASSERT_MAC_LOCK(pdata);
522
523 temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
524 if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
dffc6b24
JP		 525 SMSC_WARN(pdata, hw,
526 "smsc911x_mac_write failed, MAC busy at entry");
fd9abb3d
SG		 527 return;
528 }
529
530 /* Send data to write */
531 smsc911x_reg_write(pdata, MAC_CSR_DATA, val);
532
533 /* Write the actual data */
534 smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
535 MAC_CSR_CMD_CSR_BUSY_));
536
537 /* Workaround for hardware read-after-write restriction */
538 temp = smsc911x_reg_read(pdata, BYTE_TEST);
539
540 /* Wait for the write to complete */
541 if (likely(smsc911x_mac_complete(pdata) == 0))
542 return;
543
dffc6b24 544 SMSC_WARN(pdata, hw, "smsc911x_mac_write failed, MAC busy after write");
fd9abb3d
SG		 545}
546
547/* Get a phy register */
548static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
549{
550 struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
551 unsigned long flags;
552 unsigned int addr;
553 int i, reg;
554
555 spin_lock_irqsave(&pdata->mac_lock, flags);
556
557 /* Confirm MII not busy */
558 if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
dffc6b24 559 SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_read???");
fd9abb3d
SG		 560 reg = -EIO;
561 goto out;
562 }
563
564 /* Set the address, index & direction (read from PHY) */
565 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6);
566 smsc911x_mac_write(pdata, MII_ACC, addr);
567
568 /* Wait for read to complete w/ timeout */
569 for (i = 0; i < 100; i++)
570 if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
571 reg = smsc911x_mac_read(pdata, MII_DATA);
572 goto out;
573 }
574
dffc6b24 575 SMSC_WARN(pdata, hw, "Timed out waiting for MII read to finish");
fd9abb3d
SG		 576 reg = -EIO;
577
578out:
579 spin_unlock_irqrestore(&pdata->mac_lock, flags);
580 return reg;
581}
582
583/* Set a phy register */
584static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
585 u16 val)
586{
587 struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
588 unsigned long flags;
589 unsigned int addr;
590 int i, reg;
591
592 spin_lock_irqsave(&pdata->mac_lock, flags);
593
594 /* Confirm MII not busy */
595 if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
dffc6b24 596 SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_write???");
fd9abb3d
SG		 597 reg = -EIO;
598 goto out;
599 }
600
601 /* Put the data to write in the MAC */
602 smsc911x_mac_write(pdata, MII_DATA, val);
603
604 /* Set the address, index & direction (write to PHY) */
605 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
606 MII_ACC_MII_WRITE_;
607 smsc911x_mac_write(pdata, MII_ACC, addr);
608
609 /* Wait for write to complete w/ timeout */
610 for (i = 0; i < 100; i++)
611 if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
612 reg = 0;
613 goto out;
614 }
615
dffc6b24 616 SMSC_WARN(pdata, hw, "Timed out waiting for MII write to finish");
fd9abb3d
SG		 617 reg = -EIO;
618
619out:
620 spin_unlock_irqrestore(&pdata->mac_lock, flags);
621 return reg;
622}
623
d23f028a
SG		 624/* Switch to external phy. Assumes tx and rx are stopped. */
625static void smsc911x_phy_enable_external(struct smsc911x_data *pdata)
fd9abb3d
SG		 626{
627 unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
628
d23f028a
SG		 629 /* Disable phy clocks to the MAC */
630 hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
631 hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
632 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
633 udelay(10); /* Enough time for clocks to stop */
fd9abb3d 634
d23f028a
SG		 635 /* Switch to external phy */
636 hwcfg |= HW_CFG_EXT_PHY_EN_;
637 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
fd9abb3d 638
d23f028a
SG		 639 /* Enable phy clocks to the MAC */
640 hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
641 hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
642 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
643 udelay(10); /* Enough time for clocks to restart */
fd9abb3d 644
d23f028a
SG		 645 hwcfg |= HW_CFG_SMI_SEL_;
646 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
647}
fd9abb3d 648
d23f028a
SG		 649/* Autodetects and enables external phy if present on supported chips.
650 * autodetection can be overridden by specifying SMSC911X_FORCE_INTERNAL_PHY
651 * or SMSC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */
652static void smsc911x_phy_initialise_external(struct smsc911x_data *pdata)
653{
654 unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
fd9abb3d 655
d23f028a 656 if (pdata->config.flags & SMSC911X_FORCE_INTERNAL_PHY) {
dffc6b24 657 SMSC_TRACE(pdata, hw, "Forcing internal PHY");
d23f028a
SG		 658 pdata->using_extphy = 0;
659 } else if (pdata->config.flags & SMSC911X_FORCE_EXTERNAL_PHY) {
dffc6b24 660 SMSC_TRACE(pdata, hw, "Forcing external PHY");
d23f028a
SG		 661 smsc911x_phy_enable_external(pdata);
662 pdata->using_extphy = 1;
663 } else if (hwcfg & HW_CFG_EXT_PHY_DET_) {
dffc6b24
JP		 664 SMSC_TRACE(pdata, hw,
665 "HW_CFG EXT_PHY_DET set, using external PHY");
d23f028a 666 smsc911x_phy_enable_external(pdata);
fd9abb3d
SG		 667 pdata->using_extphy = 1;
668 } else {
dffc6b24
JP		 669 SMSC_TRACE(pdata, hw,
670 "HW_CFG EXT_PHY_DET clear, using internal PHY");
d23f028a 671 pdata->using_extphy = 0;
fd9abb3d 672 }
fd9abb3d
SG		 673}
674
675/* Fetches a tx status out of the status fifo */
676static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata)
677{
678 unsigned int result =
679 smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_;
680
681 if (result != 0)
682 result = smsc911x_reg_read(pdata, TX_STATUS_FIFO);
683
684 return result;
685}
686
687/* Fetches the next rx status */
688static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata)
689{
690 unsigned int result =
691 smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_;
692
693 if (result != 0)
694 result = smsc911x_reg_read(pdata, RX_STATUS_FIFO);
695
696 return result;
697}
698
699#ifdef USE_PHY_WORK_AROUND
700static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata)
701{
702 unsigned int tries;
703 u32 wrsz;
704 u32 rdsz;
705 ulong bufp;
706
707 for (tries = 0; tries < 10; tries++) {
708 unsigned int txcmd_a;
709 unsigned int txcmd_b;
710 unsigned int status;
711 unsigned int pktlength;
712 unsigned int i;
713
714 /* Zero-out rx packet memory */
715 memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE);
716
717 /* Write tx packet to 118 */
718 txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16;
719 txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
720 txcmd_a |= MIN_PACKET_SIZE;
721
722 txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE;
723
724 smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a);
725 smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b);
726
727 bufp = (ulong)pdata->loopback_tx_pkt & (~0x3);
728 wrsz = MIN_PACKET_SIZE + 3;
729 wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3);
730 wrsz >>= 2;
731
c326de88 732 pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
fd9abb3d
SG		 733
734 /* Wait till transmit is done */
735 i = 60;
736 do {
737 udelay(5);
738 status = smsc911x_tx_get_txstatus(pdata);
739 } while ((i--) && (!status));
740
741 if (!status) {
dffc6b24
JP		 742 SMSC_WARN(pdata, hw,
743 "Failed to transmit during loopback test");
fd9abb3d
SG		 744 continue;
745 }
746 if (status & TX_STS_ES_) {
dffc6b24
JP		 747 SMSC_WARN(pdata, hw,
748 "Transmit encountered errors during loopback test");
fd9abb3d
SG		 749 continue;
750 }
751
752 /* Wait till receive is done */
753 i = 60;
754 do {
755 udelay(5);
756 status = smsc911x_rx_get_rxstatus(pdata);
757 } while ((i--) && (!status));
758
759 if (!status) {
dffc6b24
JP		 760 SMSC_WARN(pdata, hw,
761 "Failed to receive during loopback test");
fd9abb3d
SG		 762 continue;
763 }
764 if (status & RX_STS_ES_) {
dffc6b24
JP		 765 SMSC_WARN(pdata, hw,
766 "Receive encountered errors during loopback test");
fd9abb3d
SG		 767 continue;
768 }
769
770 pktlength = ((status & 0x3FFF0000UL) >> 16);
771 bufp = (ulong)pdata->loopback_rx_pkt;
772 rdsz = pktlength + 3;
773 rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3);
774 rdsz >>= 2;
775
c326de88 776 pdata->ops->rx_readfifo(pdata, (unsigned int *)bufp, rdsz);
fd9abb3d
SG		 777
778 if (pktlength != (MIN_PACKET_SIZE + 4)) {
dffc6b24
JP		 779 SMSC_WARN(pdata, hw, "Unexpected packet size "
780 "during loop back test, size=%d, will retry",
781 pktlength);
fd9abb3d
SG		 782 } else {
783 unsigned int j;
784 int mismatch = 0;
785 for (j = 0; j < MIN_PACKET_SIZE; j++) {
786 if (pdata->loopback_tx_pkt[j]
787 != pdata->loopback_rx_pkt[j]) {
788 mismatch = 1;
789 break;
790 }
791 }
792 if (!mismatch) {
dffc6b24 793 SMSC_TRACE(pdata, hw, "Successfully verified "
fd9abb3d
SG		 794 "loopback packet");
795 return 0;
796 } else {
dffc6b24
JP		 797 SMSC_WARN(pdata, hw, "Data mismatch "
798 "during loop back test, will retry");
fd9abb3d
SG		 799 }
800 }
801 }
802
803 return -EIO;
804}
805
806static int smsc911x_phy_reset(struct smsc911x_data *pdata)
807{
808 struct phy_device *phy_dev = pdata->phy_dev;
809 unsigned int temp;
810 unsigned int i = 100000;
811
812 BUG_ON(!phy_dev);
813 BUG_ON(!phy_dev->bus);
814
dffc6b24 815 SMSC_TRACE(pdata, hw, "Performing PHY BCR Reset");
fd9abb3d
SG		 816 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_RESET);
817 do {
818 msleep(1);
819 temp = smsc911x_mii_read(phy_dev->bus, phy_dev->addr,
820 MII_BMCR);
821 } while ((i--) && (temp & BMCR_RESET));
822
823 if (temp & BMCR_RESET) {
dffc6b24 824 SMSC_WARN(pdata, hw, "PHY reset failed to complete");
fd9abb3d
SG		 825 return -EIO;
826 }
827 /* Extra delay required because the phy may not be completed with
828 * its reset when BMCR_RESET is cleared. Specs say 256 uS is
829 * enough delay but using 1ms here to be safe */
830 msleep(1);
831
832 return 0;
833}
834
835static int smsc911x_phy_loopbacktest(struct net_device *dev)
836{
837 struct smsc911x_data *pdata = netdev_priv(dev);
838 struct phy_device *phy_dev = pdata->phy_dev;
839 int result = -EIO;
840 unsigned int i, val;
841 unsigned long flags;
842
843 /* Initialise tx packet using broadcast destination address */
844 memset(pdata->loopback_tx_pkt, 0xff, ETH_ALEN);
845
846 /* Use incrementing source address */
847 for (i = 6; i < 12; i++)
848 pdata->loopback_tx_pkt[i] = (char)i;
849
850 /* Set length type field */
851 pdata->loopback_tx_pkt[12] = 0x00;
852 pdata->loopback_tx_pkt[13] = 0x00;
853
854 for (i = 14; i < MIN_PACKET_SIZE; i++)
855 pdata->loopback_tx_pkt[i] = (char)i;
856
857 val = smsc911x_reg_read(pdata, HW_CFG);
858 val &= HW_CFG_TX_FIF_SZ_;
859 val |= HW_CFG_SF_;
860 smsc911x_reg_write(pdata, HW_CFG, val);
861
862 smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
863 smsc911x_reg_write(pdata, RX_CFG,
864 (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8);
865
866 for (i = 0; i < 10; i++) {
867 /* Set PHY to 10/FD, no ANEG, and loopback mode */
868 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR,
869 BMCR_LOOPBACK | BMCR_FULLDPLX);
870
871 /* Enable MAC tx/rx, FD */
872 spin_lock_irqsave(&pdata->mac_lock, flags);
873 smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_
874 | MAC_CR_TXEN_ | MAC_CR_RXEN_);
875 spin_unlock_irqrestore(&pdata->mac_lock, flags);
876
877 if (smsc911x_phy_check_loopbackpkt(pdata) == 0) {
878 result = 0;
879 break;
880 }
881 pdata->resetcount++;
882
883 /* Disable MAC rx */
884 spin_lock_irqsave(&pdata->mac_lock, flags);
885 smsc911x_mac_write(pdata, MAC_CR, 0);
886 spin_unlock_irqrestore(&pdata->mac_lock, flags);
887
888 smsc911x_phy_reset(pdata);
889 }
890
891 /* Disable MAC */
892 spin_lock_irqsave(&pdata->mac_lock, flags);
893 smsc911x_mac_write(pdata, MAC_CR, 0);
894 spin_unlock_irqrestore(&pdata->mac_lock, flags);
895
896 /* Cancel PHY loopback mode */
897 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, 0);
898
899 smsc911x_reg_write(pdata, TX_CFG, 0);
900 smsc911x_reg_write(pdata, RX_CFG, 0);
901
902 return result;
903}
904#endif /* USE_PHY_WORK_AROUND */
905
fd9abb3d
SG		 906static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata)
907{
908 struct phy_device *phy_dev = pdata->phy_dev;
909 u32 afc = smsc911x_reg_read(pdata, AFC_CFG);
910 u32 flow;
911 unsigned long flags;
912
913 if (phy_dev->duplex == DUPLEX_FULL) {
914 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
915 u16 rmtadv = phy_read(phy_dev, MII_LPA);
bc02ff95 916 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
fd9abb3d
SG		 917
918 if (cap & FLOW_CTRL_RX)
919 flow = 0xFFFF0002;
920 else
921 flow = 0;
922
923 if (cap & FLOW_CTRL_TX)
924 afc |= 0xF;
925 else
926 afc &= ~0xF;
927
dffc6b24
JP		 928 SMSC_TRACE(pdata, hw, "rx pause %s, tx pause %s",
929 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
930 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
fd9abb3d 931 } else {
dffc6b24 932 SMSC_TRACE(pdata, hw, "half duplex");
fd9abb3d
SG		 933 flow = 0;
934 afc |= 0xF;
935 }
936
937 spin_lock_irqsave(&pdata->mac_lock, flags);
938 smsc911x_mac_write(pdata, FLOW, flow);
939 spin_unlock_irqrestore(&pdata->mac_lock, flags);
940
941 smsc911x_reg_write(pdata, AFC_CFG, afc);
942}
943
944/* Update link mode if anything has changed. Called periodically when the
945 * PHY is in polling mode, even if nothing has changed. */
946static void smsc911x_phy_adjust_link(struct net_device *dev)
947{
948 struct smsc911x_data *pdata = netdev_priv(dev);
949 struct phy_device *phy_dev = pdata->phy_dev;
950 unsigned long flags;
951 int carrier;
952
953 if (phy_dev->duplex != pdata->last_duplex) {
954 unsigned int mac_cr;
dffc6b24 955 SMSC_TRACE(pdata, hw, "duplex state has changed");
fd9abb3d
SG		 956
957 spin_lock_irqsave(&pdata->mac_lock, flags);
958 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
959 if (phy_dev->duplex) {
dffc6b24
JP		 960 SMSC_TRACE(pdata, hw,
961 "configuring for full duplex mode");
fd9abb3d
SG		 962 mac_cr |= MAC_CR_FDPX_;
963 } else {
dffc6b24
JP		 964 SMSC_TRACE(pdata, hw,
965 "configuring for half duplex mode");
fd9abb3d
SG		 966 mac_cr &= ~MAC_CR_FDPX_;
967 }
968 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
969 spin_unlock_irqrestore(&pdata->mac_lock, flags);
970
971 smsc911x_phy_update_flowcontrol(pdata);
972 pdata->last_duplex = phy_dev->duplex;
973 }
974
975 carrier = netif_carrier_ok(dev);
976 if (carrier != pdata->last_carrier) {
dffc6b24 977 SMSC_TRACE(pdata, hw, "carrier state has changed");
fd9abb3d 978 if (carrier) {
dffc6b24 979 SMSC_TRACE(pdata, hw, "configuring for carrier OK");
fd9abb3d
SG		 980 if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) &&
981 (!pdata->using_extphy)) {
88393161 982 /* Restore original GPIO configuration */
fd9abb3d
SG		 983 pdata->gpio_setting = pdata->gpio_orig_setting;
984 smsc911x_reg_write(pdata, GPIO_CFG,
985 pdata->gpio_setting);
986 }
987 } else {
dffc6b24 988 SMSC_TRACE(pdata, hw, "configuring for no carrier");
fd9abb3d
SG		 989 /* Check global setting that LED1
990 * usage is 10/100 indicator */
991 pdata->gpio_setting = smsc911x_reg_read(pdata,
992 GPIO_CFG);
8e95a202
JP		 993 if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_) &&
994 (!pdata->using_extphy)) {
fd9abb3d 995 /* Force 10/100 LED off, after saving
88393161 996 * original GPIO configuration */
fd9abb3d
SG		 997 pdata->gpio_orig_setting = pdata->gpio_setting;
998
999 pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_;
1000 pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_
1001 | GPIO_CFG_GPIODIR0_
1002 | GPIO_CFG_GPIOD0_);
1003 smsc911x_reg_write(pdata, GPIO_CFG,
1004 pdata->gpio_setting);
1005 }
1006 }
1007 pdata->last_carrier = carrier;
1008 }
1009}
1010
1011static int smsc911x_mii_probe(struct net_device *dev)
1012{
1013 struct smsc911x_data *pdata = netdev_priv(dev);
1014 struct phy_device *phydev = NULL;
e4a474f8 1015 int ret;
fd9abb3d
SG		 1016
1017 /* find the first phy */
e4a474f8 1018 phydev = phy_find_first(pdata->mii_bus);
fd9abb3d 1019 if (!phydev) {
dffc6b24 1020 netdev_err(dev, "no PHY found\n");
fd9abb3d
SG		 1021 return -ENODEV;
1022 }
1023
dffc6b24
JP		 1024 SMSC_TRACE(pdata, probe, "PHY: addr %d, phy_id 0x%08X",
1025 phydev->addr, phydev->phy_id);
e4a474f8 1026
f9a8f83b
FF		 1027 ret = phy_connect_direct(dev, phydev, &smsc911x_phy_adjust_link,
1028 pdata->config.phy_interface);
fd9abb3d 1029
e4a474f8 1030 if (ret) {
dffc6b24 1031 netdev_err(dev, "Could not attach to PHY\n");
e4a474f8 1032 return ret;
fd9abb3d
SG		 1033 }
1034
dffc6b24
JP		 1035 netdev_info(dev,
1036 "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1037 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
fd9abb3d
SG		 1038
1039 /* mask with MAC supported features */
1040 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
1041 SUPPORTED_Asym_Pause);
1042 phydev->advertising = phydev->supported;
1043
1044 pdata->phy_dev = phydev;
1045 pdata->last_duplex = -1;
1046 pdata->last_carrier = -1;
1047
1048#ifdef USE_PHY_WORK_AROUND
1049 if (smsc911x_phy_loopbacktest(dev) < 0) {
dffc6b24 1050 SMSC_WARN(pdata, hw, "Failed Loop Back Test");
fd9abb3d
SG		 1051 return -ENODEV;
1052 }
dffc6b24 1053 SMSC_TRACE(pdata, hw, "Passed Loop Back Test");
fd9abb3d
SG		 1054#endif /* USE_PHY_WORK_AROUND */
1055
dffc6b24 1056 SMSC_TRACE(pdata, hw, "phy initialised successfully");
fd9abb3d
SG		 1057 return 0;
1058}
1059
8489ec1f 1060static int smsc911x_mii_init(struct platform_device *pdev,
1dd06ae8 1061 struct net_device *dev)
fd9abb3d
SG		 1062{
1063 struct smsc911x_data *pdata = netdev_priv(dev);
1064 int err = -ENXIO, i;
1065
1066 pdata->mii_bus = mdiobus_alloc();
1067 if (!pdata->mii_bus) {
1068 err = -ENOMEM;
1069 goto err_out_1;
1070 }
1071
1072 pdata->mii_bus->name = SMSC_MDIONAME;
09ef0789
FF		 1073 snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1074 pdev->name, pdev->id);
fd9abb3d
SG		 1075 pdata->mii_bus->priv = pdata;
1076 pdata->mii_bus->read = smsc911x_mii_read;
1077 pdata->mii_bus->write = smsc911x_mii_write;
1078 pdata->mii_bus->irq = pdata->phy_irq;
1079 for (i = 0; i < PHY_MAX_ADDR; ++i)
1080 pdata->mii_bus->irq[i] = PHY_POLL;
1081
1082 pdata->mii_bus->parent = &pdev->dev;
fd9abb3d 1083
fd9abb3d
SG		 1084 switch (pdata->idrev & 0xFFFF0000) {
1085 case 0x01170000:
1086 case 0x01150000:
1087 case 0x117A0000:
1088 case 0x115A0000:
1089 /* External PHY supported, try to autodetect */
d23f028a 1090 smsc911x_phy_initialise_external(pdata);
fd9abb3d
SG		 1091 break;
1092 default:
dffc6b24
JP		 1093 SMSC_TRACE(pdata, hw, "External PHY is not supported, "
1094 "using internal PHY");
d23f028a 1095 pdata->using_extphy = 0;
fd9abb3d
SG		 1096 break;
1097 }
1098
1099 if (!pdata->using_extphy) {
1100 /* Mask all PHYs except ID 1 (internal) */
1101 pdata->mii_bus->phy_mask = ~(1 << 1);
1102 }
1103
1104 if (mdiobus_register(pdata->mii_bus)) {
dffc6b24 1105 SMSC_WARN(pdata, probe, "Error registering mii bus");
fd9abb3d
SG		 1106 goto err_out_free_bus_2;
1107 }
1108
1109 if (smsc911x_mii_probe(dev) < 0) {
dffc6b24 1110 SMSC_WARN(pdata, probe, "Error registering mii bus");
fd9abb3d
SG		 1111 goto err_out_unregister_bus_3;
1112 }
1113
1114 return 0;
1115
1116err_out_unregister_bus_3:
1117 mdiobus_unregister(pdata->mii_bus);
1118err_out_free_bus_2:
1119 mdiobus_free(pdata->mii_bus);
1120err_out_1:
1121 return err;
1122}
1123
1124/* Gets the number of tx statuses in the fifo */
1125static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata)
1126{
1127 return (smsc911x_reg_read(pdata, TX_FIFO_INF)
1128 & TX_FIFO_INF_TSUSED_) >> 16;
1129}
1130
1131/* Reads tx statuses and increments counters where necessary */
1132static void smsc911x_tx_update_txcounters(struct net_device *dev)
1133{
1134 struct smsc911x_data *pdata = netdev_priv(dev);
1135 unsigned int tx_stat;
1136
1137 while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) {
1138 if (unlikely(tx_stat & 0x80000000)) {
1139 /* In this driver the packet tag is used as the packet
1140 * length. Since a packet length can never reach the
1141 * size of 0x8000, this bit is reserved. It is worth
1142 * noting that the "reserved bit" in the warning above
1143 * does not reference a hardware defined reserved bit
1144 * but rather a driver defined one.
1145 */
dffc6b24 1146 SMSC_WARN(pdata, hw, "Packet tag reserved bit is high");
fd9abb3d 1147 } else {
785b6f97 1148 if (unlikely(tx_stat & TX_STS_ES_)) {
fd9abb3d
SG		 1149 dev->stats.tx_errors++;
1150 } else {
1151 dev->stats.tx_packets++;
1152 dev->stats.tx_bytes += (tx_stat >> 16);
1153 }
785b6f97 1154 if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) {
fd9abb3d
SG		 1155 dev->stats.collisions += 16;
1156 dev->stats.tx_aborted_errors += 1;
1157 } else {
1158 dev->stats.collisions +=
1159 ((tx_stat >> 3) & 0xF);
1160 }
785b6f97 1161 if (unlikely(tx_stat & TX_STS_LOST_CARRIER_))
fd9abb3d 1162 dev->stats.tx_carrier_errors += 1;
785b6f97 1163 if (unlikely(tx_stat & TX_STS_LATE_COL_)) {
fd9abb3d
SG		 1164 dev->stats.collisions++;
1165 dev->stats.tx_aborted_errors++;
1166 }
1167 }
1168 }
1169}
1170
1171/* Increments the Rx error counters */
1172static void
1173smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat)
1174{
1175 int crc_err = 0;
1176
785b6f97 1177 if (unlikely(rxstat & RX_STS_ES_)) {
fd9abb3d 1178 dev->stats.rx_errors++;
785b6f97 1179 if (unlikely(rxstat & RX_STS_CRC_ERR_)) {
fd9abb3d
SG		 1180 dev->stats.rx_crc_errors++;
1181 crc_err = 1;
1182 }
1183 }
1184 if (likely(!crc_err)) {
785b6f97
SG		 1185 if (unlikely((rxstat & RX_STS_FRAME_TYPE_) &&
1186 (rxstat & RX_STS_LENGTH_ERR_)))
fd9abb3d 1187 dev->stats.rx_length_errors++;
fd9abb3d
SG		 1188 if (rxstat & RX_STS_MCAST_)
1189 dev->stats.multicast++;
1190 }
1191}
1192
1193/* Quickly dumps bad packets */
1194static void
3c5e979b 1195smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktwords)
fd9abb3d 1196{
fd9abb3d
SG		 1197 if (likely(pktwords >= 4)) {
1198 unsigned int timeout = 500;
1199 unsigned int val;
1200 smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_);
1201 do {
1202 udelay(1);
1203 val = smsc911x_reg_read(pdata, RX_DP_CTRL);
8dacd548 1204 } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout);
fd9abb3d
SG		 1205
1206 if (unlikely(timeout == 0))
dffc6b24
JP		 1207 SMSC_WARN(pdata, hw, "Timed out waiting for "
1208 "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val);
fd9abb3d
SG		 1209 } else {
1210 unsigned int temp;
1211 while (pktwords--)
1212 temp = smsc911x_reg_read(pdata, RX_DATA_FIFO);
1213 }
1214}
1215
1216/* NAPI poll function */
1217static int smsc911x_poll(struct napi_struct *napi, int budget)
1218{
1219 struct smsc911x_data *pdata =
1220 container_of(napi, struct smsc911x_data, napi);
1221 struct net_device *dev = pdata->dev;
1222 int npackets = 0;
1223
f88c5b98 1224 while (npackets < budget) {
fd9abb3d
SG		 1225 unsigned int pktlength;
1226 unsigned int pktwords;
1227 struct sk_buff *skb;
1228 unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata);
1229
1230 if (!rxstat) {
1231 unsigned int temp;
1232 /* We processed all packets available. Tell NAPI it can
1233 * stop polling then re-enable rx interrupts */
1234 smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_);
288379f0 1235 napi_complete(napi);
fd9abb3d
SG		 1236 temp = smsc911x_reg_read(pdata, INT_EN);
1237 temp |= INT_EN_RSFL_EN_;
1238 smsc911x_reg_write(pdata, INT_EN, temp);
1239 break;
1240 }
1241
1242 /* Count packet for NAPI scheduling, even if it has an error.
1243 * Error packets still require cycles to discard */
1244 npackets++;
1245
1246 pktlength = ((rxstat & 0x3FFF0000) >> 16);
1247 pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2;
1248 smsc911x_rx_counterrors(dev, rxstat);
1249
1250 if (unlikely(rxstat & RX_STS_ES_)) {
dffc6b24
JP		 1251 SMSC_WARN(pdata, rx_err,
1252 "Discarding packet with error bit set");
fd9abb3d
SG		 1253 /* Packet has an error, discard it and continue with
1254 * the next */
1255 smsc911x_rx_fastforward(pdata, pktwords);
1256 dev->stats.rx_dropped++;
1257 continue;
1258 }
1259
3c5e979b 1260 skb = netdev_alloc_skb(dev, pktwords << 2);
fd9abb3d 1261 if (unlikely(!skb)) {
dffc6b24
JP		 1262 SMSC_WARN(pdata, rx_err,
1263 "Unable to allocate skb for rx packet");
fd9abb3d
SG		 1264 /* Drop the packet and stop this polling iteration */
1265 smsc911x_rx_fastforward(pdata, pktwords);
1266 dev->stats.rx_dropped++;
1267 break;
1268 }
1269
3c5e979b
WD		 1270 pdata->ops->rx_readfifo(pdata,
1271 (unsigned int *)skb->data, pktwords);
fd9abb3d
SG		 1272
1273 /* Align IP on 16B boundary */
1274 skb_reserve(skb, NET_IP_ALIGN);
1275 skb_put(skb, pktlength - 4);
fd9abb3d 1276 skb->protocol = eth_type_trans(skb, dev);
bc8acf2c 1277 skb_checksum_none_assert(skb);
fd9abb3d
SG		 1278 netif_receive_skb(skb);
1279
1280 /* Update counters */
1281 dev->stats.rx_packets++;
1282 dev->stats.rx_bytes += (pktlength - 4);
fd9abb3d
SG		 1283 }
1284
1285 /* Return total received packets */
1286 return npackets;
1287}
1288
1289/* Returns hash bit number for given MAC address
1290 * Example:
1291 * 01 00 5E 00 00 01 -> returns bit number 31 */
1292static unsigned int smsc911x_hash(char addr[ETH_ALEN])
1293{
1294 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
1295}
1296
1297static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata)
1298{
1299 /* Performs the multicast & mac_cr update. This is called when
1300 * safe on the current hardware, and with the mac_lock held */
1301 unsigned int mac_cr;
1302
1303 SMSC_ASSERT_MAC_LOCK(pdata);
1304
1305 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
1306 mac_cr |= pdata->set_bits_mask;
1307 mac_cr &= ~(pdata->clear_bits_mask);
1308 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
1309 smsc911x_mac_write(pdata, HASHH, pdata->hashhi);
1310 smsc911x_mac_write(pdata, HASHL, pdata->hashlo);
dffc6b24
JP		 1311 SMSC_TRACE(pdata, hw, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X",
1312 mac_cr, pdata->hashhi, pdata->hashlo);
fd9abb3d
SG		 1313}
1314
1315static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata)
1316{
1317 unsigned int mac_cr;
1318
1319 /* This function is only called for older LAN911x devices
1320 * (revA or revB), where MAC_CR, HASHH and HASHL should not
1321 * be modified during Rx - newer devices immediately update the
1322 * registers.
1323 *
1324 * This is called from interrupt context */
1325
1326 spin_lock(&pdata->mac_lock);
1327
1328 /* Check Rx has stopped */
1329 if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_)
dffc6b24 1330 SMSC_WARN(pdata, drv, "Rx not stopped");
fd9abb3d
SG		 1331
1332 /* Perform the update - safe to do now Rx has stopped */
1333 smsc911x_rx_multicast_update(pdata);
1334
1335 /* Re-enable Rx */
1336 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
1337 mac_cr |= MAC_CR_RXEN_;
1338 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
1339
1340 pdata->multicast_update_pending = 0;
1341
1342 spin_unlock(&pdata->mac_lock);
1343}
1344
6386994e
JMC		 1345static int smsc911x_phy_disable_energy_detect(struct smsc911x_data *pdata)
1346{
1347 int rc = 0;
1348
1349 if (!pdata->phy_dev)
1350 return rc;
1351
1352 rc = phy_read(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS);
1353
1354 if (rc < 0) {
1355 SMSC_WARN(pdata, drv, "Failed reading PHY control reg");
1356 return rc;
1357 }
1358
1359 /*
1360 * If energy is detected the PHY is already awake so is not necessary
1361 * to disable the energy detect power-down mode.
1362 */
1363 if ((rc & MII_LAN83C185_EDPWRDOWN) &&
1364 !(rc & MII_LAN83C185_ENERGYON)) {
1365 /* Disable energy detect mode for this SMSC Transceivers */
1366 rc = phy_write(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS,
1367 rc & (~MII_LAN83C185_EDPWRDOWN));
1368
1369 if (rc < 0) {
1370 SMSC_WARN(pdata, drv, "Failed writing PHY control reg");
1371 return rc;
1372 }
1373
1374 mdelay(1);
1375 }
1376
1377 return 0;
1378}
1379
1380static int smsc911x_phy_enable_energy_detect(struct smsc911x_data *pdata)
1381{
1382 int rc = 0;
1383
1384 if (!pdata->phy_dev)
1385 return rc;
1386
1387 rc = phy_read(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS);
1388
1389 if (rc < 0) {
1390 SMSC_WARN(pdata, drv, "Failed reading PHY control reg");
1391 return rc;
1392 }
1393
1394 /* Only enable if energy detect mode is already disabled */
1395 if (!(rc & MII_LAN83C185_EDPWRDOWN)) {
1396 mdelay(100);
1397 /* Enable energy detect mode for this SMSC Transceivers */
1398 rc = phy_write(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS,
1399 rc | MII_LAN83C185_EDPWRDOWN);
1400
1401 if (rc < 0) {
1402 SMSC_WARN(pdata, drv, "Failed writing PHY control reg");
1403 return rc;
1404 }
1405
1406 mdelay(1);
1407 }
1408 return 0;
1409}
1410
fd9abb3d
SG		 1411static int smsc911x_soft_reset(struct smsc911x_data *pdata)
1412{
1413 unsigned int timeout;
1414 unsigned int temp;
6386994e
JMC		 1415 int ret;
1416
1417 /*
1418 * LAN9210/LAN9211/LAN9220/LAN9221 chips have an internal PHY that
1419 * are initialized in a Energy Detect Power-Down mode that prevents
1420 * the MAC chip to be software reseted. So we have to wakeup the PHY
1421 * before.
1422 */
1423 if (pdata->generation == 4) {
1424 ret = smsc911x_phy_disable_energy_detect(pdata);
1425
1426 if (ret) {
1427 SMSC_WARN(pdata, drv, "Failed to wakeup the PHY chip");
1428 return ret;
1429 }
1430 }
fd9abb3d
SG		 1431
1432 /* Reset the LAN911x */
1433 smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_);
1434 timeout = 10;
1435 do {
1436 udelay(10);
1437 temp = smsc911x_reg_read(pdata, HW_CFG);
1438 } while ((--timeout) && (temp & HW_CFG_SRST_));
1439
1440 if (unlikely(temp & HW_CFG_SRST_)) {
dffc6b24 1441 SMSC_WARN(pdata, drv, "Failed to complete reset");
fd9abb3d
SG		 1442 return -EIO;
1443 }
6386994e
JMC		 1444
1445 if (pdata->generation == 4) {
1446 ret = smsc911x_phy_enable_energy_detect(pdata);
1447
1448 if (ret) {
1449 SMSC_WARN(pdata, drv, "Failed to wakeup the PHY chip");
1450 return ret;
1451 }
1452 }
1453
fd9abb3d
SG		 1454 return 0;
1455}
1456
1457/* Sets the device MAC address to dev_addr, called with mac_lock held */
1458static void
225ddf49 1459smsc911x_set_hw_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6])
fd9abb3d
SG		 1460{
1461 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
1462 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
1463 (dev_addr[1] << 8) | dev_addr[0];
1464
1465 SMSC_ASSERT_MAC_LOCK(pdata);
1466
1467 smsc911x_mac_write(pdata, ADDRH, mac_high16);
1468 smsc911x_mac_write(pdata, ADDRL, mac_low32);
1469}
1470
8e27628e
MB		 1471static void smsc911x_disable_irq_chip(struct net_device *dev)
1472{
1473 struct smsc911x_data *pdata = netdev_priv(dev);
1474
1475 smsc911x_reg_write(pdata, INT_EN, 0);
1476 smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
1477}
1478
fd9abb3d
SG		 1479static int smsc911x_open(struct net_device *dev)
1480{
1481 struct smsc911x_data *pdata = netdev_priv(dev);
1482 unsigned int timeout;
1483 unsigned int temp;
1484 unsigned int intcfg;
1485
1486 /* if the phy is not yet registered, retry later*/
1487 if (!pdata->phy_dev) {
dffc6b24 1488 SMSC_WARN(pdata, hw, "phy_dev is NULL");
fd9abb3d
SG		 1489 return -EAGAIN;
1490 }
1491
fd9abb3d
SG		 1492 /* Reset the LAN911x */
1493 if (smsc911x_soft_reset(pdata)) {
dffc6b24 1494 SMSC_WARN(pdata, hw, "soft reset failed");
fd9abb3d
SG		 1495 return -EIO;
1496 }
1497
1498 smsc911x_reg_write(pdata, HW_CFG, 0x00050000);
1499 smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740);
1500
f277e65e
GW		 1501 /* Increase the legal frame size of VLAN tagged frames to 1522 bytes */
1502 spin_lock_irq(&pdata->mac_lock);
1503 smsc911x_mac_write(pdata, VLAN1, ETH_P_8021Q);
1504 spin_unlock_irq(&pdata->mac_lock);
1505
fd9abb3d
SG		 1506 /* Make sure EEPROM has finished loading before setting GPIO_CFG */
1507 timeout = 50;
f7efb6cc
SG		 1508 while ((smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) &&
1509 --timeout) {
fd9abb3d
SG		 1510 udelay(10);
1511 }
1512
1513 if (unlikely(timeout == 0))
dffc6b24
JP		 1514 SMSC_WARN(pdata, ifup,
1515 "Timed out waiting for EEPROM busy bit to clear");
fd9abb3d
SG		 1516
1517 smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000);
1518
1519 /* The soft reset above cleared the device's MAC address,
1520 * restore it from local copy (set in probe) */
1521 spin_lock_irq(&pdata->mac_lock);
225ddf49 1522 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
fd9abb3d
SG		 1523 spin_unlock_irq(&pdata->mac_lock);
1524
1525 /* Initialise irqs, but leave all sources disabled */
8e27628e 1526 smsc911x_disable_irq_chip(dev);
fd9abb3d
SG		 1527
1528 /* Set interrupt deassertion to 100uS */
1529 intcfg = ((10 << 24) | INT_CFG_IRQ_EN_);
1530
2107fb8b 1531 if (pdata->config.irq_polarity) {
dffc6b24 1532 SMSC_TRACE(pdata, ifup, "irq polarity: active high");
fd9abb3d
SG		 1533 intcfg |= INT_CFG_IRQ_POL_;
1534 } else {
dffc6b24 1535 SMSC_TRACE(pdata, ifup, "irq polarity: active low");
fd9abb3d
SG		 1536 }
1537
2107fb8b 1538 if (pdata->config.irq_type) {
dffc6b24 1539 SMSC_TRACE(pdata, ifup, "irq type: push-pull");
fd9abb3d
SG		 1540 intcfg |= INT_CFG_IRQ_TYPE_;
1541 } else {
dffc6b24 1542 SMSC_TRACE(pdata, ifup, "irq type: open drain");
fd9abb3d
SG		 1543 }
1544
1545 smsc911x_reg_write(pdata, INT_CFG, intcfg);
1546
dffc6b24 1547 SMSC_TRACE(pdata, ifup, "Testing irq handler using IRQ %d", dev->irq);
fd9abb3d
SG		 1548 pdata->software_irq_signal = 0;
1549 smp_wmb();
1550
1551 temp = smsc911x_reg_read(pdata, INT_EN);
1552 temp |= INT_EN_SW_INT_EN_;
1553 smsc911x_reg_write(pdata, INT_EN, temp);
1554
1555 timeout = 1000;
1556 while (timeout--) {
1557 if (pdata->software_irq_signal)
1558 break;
1559 msleep(1);
1560 }
1561
1562 if (!pdata->software_irq_signal) {
dffc6b24
JP		 1563 netdev_warn(dev, "ISR failed signaling test (IRQ %d)\n",
1564 dev->irq);
fd9abb3d
SG		 1565 return -ENODEV;
1566 }
dffc6b24
JP		 1567 SMSC_TRACE(pdata, ifup, "IRQ handler passed test using IRQ %d",
1568 dev->irq);
fd9abb3d 1569
dffc6b24
JP		 1570 netdev_info(dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n",
1571 (unsigned long)pdata->ioaddr, dev->irq);
fd9abb3d 1572
44c1d6f9
SG		 1573 /* Reset the last known duplex and carrier */
1574 pdata->last_duplex = -1;
1575 pdata->last_carrier = -1;
1576
fd9abb3d
SG		 1577 /* Bring the PHY up */
1578 phy_start(pdata->phy_dev);
1579
1580 temp = smsc911x_reg_read(pdata, HW_CFG);
1581 /* Preserve TX FIFO size and external PHY configuration */
1582 temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF);
1583 temp |= HW_CFG_SF_;
1584 smsc911x_reg_write(pdata, HW_CFG, temp);
1585
1586 temp = smsc911x_reg_read(pdata, FIFO_INT);
1587 temp |= FIFO_INT_TX_AVAIL_LEVEL_;
1588 temp &= ~(FIFO_INT_RX_STS_LEVEL_);
1589 smsc911x_reg_write(pdata, FIFO_INT, temp);
1590
1591 /* set RX Data offset to 2 bytes for alignment */
3c5e979b 1592 smsc911x_reg_write(pdata, RX_CFG, (NET_IP_ALIGN << 8));
fd9abb3d
SG		 1593
1594 /* enable NAPI polling before enabling RX interrupts */
1595 napi_enable(&pdata->napi);
1596
1597 temp = smsc911x_reg_read(pdata, INT_EN);
1373c0fd 1598 temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_RXSTOP_INT_EN_);
fd9abb3d
SG		 1599 smsc911x_reg_write(pdata, INT_EN, temp);
1600
1601 spin_lock_irq(&pdata->mac_lock);
1602 temp = smsc911x_mac_read(pdata, MAC_CR);
1603 temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
1604 smsc911x_mac_write(pdata, MAC_CR, temp);
1605 spin_unlock_irq(&pdata->mac_lock);
1606
1607 smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
1608
1609 netif_start_queue(dev);
1610 return 0;
1611}
1612
1613/* Entry point for stopping the interface */
1614static int smsc911x_stop(struct net_device *dev)
1615{
1616 struct smsc911x_data *pdata = netdev_priv(dev);
1617 unsigned int temp;
1618
fd9abb3d
SG		 1619 /* Disable all device interrupts */
1620 temp = smsc911x_reg_read(pdata, INT_CFG);
1621 temp &= ~INT_CFG_IRQ_EN_;
1622 smsc911x_reg_write(pdata, INT_CFG, temp);
1623
1624 /* Stop Tx and Rx polling */
1625 netif_stop_queue(dev);
1626 napi_disable(&pdata->napi);
1627
1628 /* At this point all Rx and Tx activity is stopped */
1629 dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
1630 smsc911x_tx_update_txcounters(dev);
1631
1632 /* Bring the PHY down */
dd045193
SG		 1633 if (pdata->phy_dev)
1634 phy_stop(pdata->phy_dev);
fd9abb3d 1635
dffc6b24 1636 SMSC_TRACE(pdata, ifdown, "Interface stopped");
fd9abb3d
SG		 1637 return 0;
1638}
1639
1640/* Entry point for transmitting a packet */
1641static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
1642{
1643 struct smsc911x_data *pdata = netdev_priv(dev);
1644 unsigned int freespace;
1645 unsigned int tx_cmd_a;
1646 unsigned int tx_cmd_b;
1647 unsigned int temp;
1648 u32 wrsz;
1649 ulong bufp;
1650
1651 freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_;
1652
1653 if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD))
dffc6b24
JP		 1654 SMSC_WARN(pdata, tx_err,
1655 "Tx data fifo low, space available: %d", freespace);
fd9abb3d
SG		 1656
1657 /* Word alignment adjustment */
1658 tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16;
1659 tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
1660 tx_cmd_a |= (unsigned int)skb->len;
1661
1662 tx_cmd_b = ((unsigned int)skb->len) << 16;
1663 tx_cmd_b |= (unsigned int)skb->len;
1664
1665 smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a);
1666 smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b);
1667
1668 bufp = (ulong)skb->data & (~0x3);
1669 wrsz = (u32)skb->len + 3;
1670 wrsz += (u32)((ulong)skb->data & 0x3);
1671 wrsz >>= 2;
1672
c326de88 1673 pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
fd9abb3d 1674 freespace -= (skb->len + 32);
8c0069ae 1675 skb_tx_timestamp(skb);
fd9abb3d 1676 dev_kfree_skb(skb);
fd9abb3d
SG		 1677
1678 if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30))
1679 smsc911x_tx_update_txcounters(dev);
1680
1681 if (freespace < TX_FIFO_LOW_THRESHOLD) {
1682 netif_stop_queue(dev);
1683 temp = smsc911x_reg_read(pdata, FIFO_INT);
1684 temp &= 0x00FFFFFF;
1685 temp |= 0x32000000;
1686 smsc911x_reg_write(pdata, FIFO_INT, temp);
1687 }
1688
1689 return NETDEV_TX_OK;
1690}
1691
1692/* Entry point for getting status counters */
1693static struct net_device_stats *smsc911x_get_stats(struct net_device *dev)
1694{
1695 struct smsc911x_data *pdata = netdev_priv(dev);
1696 smsc911x_tx_update_txcounters(dev);
1697 dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
1698 return &dev->stats;
1699}
1700
1701/* Entry point for setting addressing modes */
1702static void smsc911x_set_multicast_list(struct net_device *dev)
1703{
1704 struct smsc911x_data *pdata = netdev_priv(dev);
1705 unsigned long flags;
1706
1707 if (dev->flags & IFF_PROMISC) {
1708 /* Enabling promiscuous mode */
1709 pdata->set_bits_mask = MAC_CR_PRMS_;
1710 pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
1711 pdata->hashhi = 0;
1712 pdata->hashlo = 0;
1713 } else if (dev->flags & IFF_ALLMULTI) {
1714 /* Enabling all multicast mode */
1715 pdata->set_bits_mask = MAC_CR_MCPAS_;
1716 pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_);
1717 pdata->hashhi = 0;
1718 pdata->hashlo = 0;
4cd24eaf 1719 } else if (!netdev_mc_empty(dev)) {
fd9abb3d
SG		 1720 /* Enabling specific multicast addresses */
1721 unsigned int hash_high = 0;
1722 unsigned int hash_low = 0;
22bedad3 1723 struct netdev_hw_addr *ha;
fd9abb3d
SG		 1724
1725 pdata->set_bits_mask = MAC_CR_HPFILT_;
1726 pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_);
1727
22bedad3
JP		 1728 netdev_for_each_mc_addr(ha, dev) {
1729 unsigned int bitnum = smsc911x_hash(ha->addr);
2a0d18f9
JP		 1730 unsigned int mask = 0x01 << (bitnum & 0x1F);
1731
1732 if (bitnum & 0x20)
1733 hash_high |= mask;
1734 else
1735 hash_low |= mask;
fd9abb3d 1736 }
fd9abb3d
SG		 1737
1738 pdata->hashhi = hash_high;
1739 pdata->hashlo = hash_low;
1740 } else {
1741 /* Enabling local MAC address only */
1742 pdata->set_bits_mask = 0;
1743 pdata->clear_bits_mask =
1744 (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
1745 pdata->hashhi = 0;
1746 pdata->hashlo = 0;
1747 }
1748
1749 spin_lock_irqsave(&pdata->mac_lock, flags);
1750
1751 if (pdata->generation <= 1) {
1752 /* Older hardware revision - cannot change these flags while
1753 * receiving data */
1754 if (!pdata->multicast_update_pending) {
1755 unsigned int temp;
dffc6b24 1756 SMSC_TRACE(pdata, hw, "scheduling mcast update");
fd9abb3d
SG		 1757 pdata->multicast_update_pending = 1;
1758
1759 /* Request the hardware to stop, then perform the
1760 * update when we get an RX_STOP interrupt */
fd9abb3d
SG		 1761 temp = smsc911x_mac_read(pdata, MAC_CR);
1762 temp &= ~(MAC_CR_RXEN_);
1763 smsc911x_mac_write(pdata, MAC_CR, temp);
1764 } else {
1765 /* There is another update pending, this should now
1766 * use the newer values */
1767 }
1768 } else {
1769 /* Newer hardware revision - can write immediately */
1770 smsc911x_rx_multicast_update(pdata);
1771 }
1772
1773 spin_unlock_irqrestore(&pdata->mac_lock, flags);
1774}
1775
1776static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id)
1777{
1778 struct net_device *dev = dev_id;
1779 struct smsc911x_data *pdata = netdev_priv(dev);
1780 u32 intsts = smsc911x_reg_read(pdata, INT_STS);
1781 u32 inten = smsc911x_reg_read(pdata, INT_EN);
1782 int serviced = IRQ_NONE;
1783 u32 temp;
1784
1785 if (unlikely(intsts & inten & INT_STS_SW_INT_)) {
1786 temp = smsc911x_reg_read(pdata, INT_EN);
1787 temp &= (~INT_EN_SW_INT_EN_);
1788 smsc911x_reg_write(pdata, INT_EN, temp);
1789 smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_);
1790 pdata->software_irq_signal = 1;
1791 smp_wmb();
1792 serviced = IRQ_HANDLED;
1793 }
1794
1795 if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) {
1796 /* Called when there is a multicast update scheduled and
1797 * it is now safe to complete the update */
dffc6b24 1798 SMSC_TRACE(pdata, intr, "RX Stop interrupt");
fd9abb3d 1799 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_);
1373c0fd
SG		 1800 if (pdata->multicast_update_pending)
1801 smsc911x_rx_multicast_update_workaround(pdata);
fd9abb3d
SG		 1802 serviced = IRQ_HANDLED;
1803 }
1804
1805 if (intsts & inten & INT_STS_TDFA_) {
1806 temp = smsc911x_reg_read(pdata, FIFO_INT);
1807 temp |= FIFO_INT_TX_AVAIL_LEVEL_;
1808 smsc911x_reg_write(pdata, FIFO_INT, temp);
1809 smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_);
1810 netif_wake_queue(dev);
1811 serviced = IRQ_HANDLED;
1812 }
1813
1814 if (unlikely(intsts & inten & INT_STS_RXE_)) {
dffc6b24 1815 SMSC_TRACE(pdata, intr, "RX Error interrupt");
fd9abb3d
SG		 1816 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_);
1817 serviced = IRQ_HANDLED;
1818 }
1819
1820 if (likely(intsts & inten & INT_STS_RSFL_)) {
288379f0 1821 if (likely(napi_schedule_prep(&pdata->napi))) {
fd9abb3d
SG		 1822 /* Disable Rx interrupts */
1823 temp = smsc911x_reg_read(pdata, INT_EN);
1824 temp &= (~INT_EN_RSFL_EN_);
1825 smsc911x_reg_write(pdata, INT_EN, temp);
1826 /* Schedule a NAPI poll */
288379f0 1827 __napi_schedule(&pdata->napi);
fd9abb3d 1828 } else {
dffc6b24 1829 SMSC_WARN(pdata, rx_err, "napi_schedule_prep failed");
fd9abb3d
SG		 1830 }
1831 serviced = IRQ_HANDLED;
1832 }
1833
1834 return serviced;
1835}
1836
1837#ifdef CONFIG_NET_POLL_CONTROLLER
1757ab2f 1838static void smsc911x_poll_controller(struct net_device *dev)
fd9abb3d
SG		 1839{
1840 disable_irq(dev->irq);
1841 smsc911x_irqhandler(0, dev);
1842 enable_irq(dev->irq);
1843}
1844#endif /* CONFIG_NET_POLL_CONTROLLER */
1845
225ddf49
SG		 1846static int smsc911x_set_mac_address(struct net_device *dev, void *p)
1847{
1848 struct smsc911x_data *pdata = netdev_priv(dev);
1849 struct sockaddr *addr = p;
1850
1851 /* On older hardware revisions we cannot change the mac address
1852 * registers while receiving data. Newer devices can safely change
1853 * this at any time. */
1854 if (pdata->generation <= 1 && netif_running(dev))
1855 return -EBUSY;
1856
1857 if (!is_valid_ether_addr(addr->sa_data))
1858 return -EADDRNOTAVAIL;
1859
1860 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
1861
1862 spin_lock_irq(&pdata->mac_lock);
1863 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
1864 spin_unlock_irq(&pdata->mac_lock);
1865
dffc6b24 1866 netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr);
225ddf49
SG		 1867
1868 return 0;
1869}
1870
fd9abb3d
SG		 1871/* Standard ioctls for mii-tool */
1872static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1873{
1874 struct smsc911x_data *pdata = netdev_priv(dev);
1875
1876 if (!netif_running(dev) || !pdata->phy_dev)
1877 return -EINVAL;
1878
28b04113 1879 return phy_mii_ioctl(pdata->phy_dev, ifr, cmd);
fd9abb3d
SG		 1880}
1881
1882static int
1883smsc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1884{
1885 struct smsc911x_data *pdata = netdev_priv(dev);
1886
1887 cmd->maxtxpkt = 1;
1888 cmd->maxrxpkt = 1;
1889 return phy_ethtool_gset(pdata->phy_dev, cmd);
1890}
1891
1892static int
1893smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1894{
1895 struct smsc911x_data *pdata = netdev_priv(dev);
1896
1897 return phy_ethtool_sset(pdata->phy_dev, cmd);
1898}
1899
1900static void smsc911x_ethtool_getdrvinfo(struct net_device *dev,
1901 struct ethtool_drvinfo *info)
1902{
1903 strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver));
1904 strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version));
db1d7bf7 1905 strlcpy(info->bus_info, dev_name(dev->dev.parent),
fd9abb3d
SG		 1906 sizeof(info->bus_info));
1907}
1908
1909static int smsc911x_ethtool_nwayreset(struct net_device *dev)
1910{
1911 struct smsc911x_data *pdata = netdev_priv(dev);
1912
1913 return phy_start_aneg(pdata->phy_dev);
1914}
1915
1916static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev)
1917{
1918 struct smsc911x_data *pdata = netdev_priv(dev);
1919 return pdata->msg_enable;
1920}
1921
1922static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
1923{
1924 struct smsc911x_data *pdata = netdev_priv(dev);
1925 pdata->msg_enable = level;
1926}
1927
1928static int smsc911x_ethtool_getregslen(struct net_device *dev)
1929{
1930 return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) *
1931 sizeof(u32);
1932}
1933
1934static void
1935smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
1936 void *buf)
1937{
1938 struct smsc911x_data *pdata = netdev_priv(dev);
1939 struct phy_device *phy_dev = pdata->phy_dev;
1940 unsigned long flags;
1941 unsigned int i;
1942 unsigned int j = 0;
1943 u32 *data = buf;
1944
1945 regs->version = pdata->idrev;
1946 for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32)))
1947 data[j++] = smsc911x_reg_read(pdata, i);
1948
1949 for (i = MAC_CR; i <= WUCSR; i++) {
1950 spin_lock_irqsave(&pdata->mac_lock, flags);
1951 data[j++] = smsc911x_mac_read(pdata, i);
1952 spin_unlock_irqrestore(&pdata->mac_lock, flags);
1953 }
1954
1955 for (i = 0; i <= 31; i++)
1956 data[j++] = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, i);
1957}
1958
1959static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata)
1960{
1961 unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG);
1962 temp &= ~GPIO_CFG_EEPR_EN_;
1963 smsc911x_reg_write(pdata, GPIO_CFG, temp);
1964 msleep(1);
1965}
1966
1967static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op)
1968{
1969 int timeout = 100;
1970 u32 e2cmd;
1971
dffc6b24 1972 SMSC_TRACE(pdata, drv, "op 0x%08x", op);
fd9abb3d 1973 if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
dffc6b24 1974 SMSC_WARN(pdata, drv, "Busy at start");
fd9abb3d
SG		 1975 return -EBUSY;
1976 }
1977
1978 e2cmd = op | E2P_CMD_EPC_BUSY_;
1979 smsc911x_reg_write(pdata, E2P_CMD, e2cmd);
1980
1981 do {
1982 msleep(1);
1983 e2cmd = smsc911x_reg_read(pdata, E2P_CMD);
2cf0dbed 1984 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
fd9abb3d
SG		 1985
1986 if (!timeout) {
dffc6b24 1987 SMSC_TRACE(pdata, drv, "TIMED OUT");
fd9abb3d
SG		 1988 return -EAGAIN;
1989 }
1990
1991 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
1c01a80c 1992 SMSC_TRACE(pdata, drv, "Error occurred during eeprom operation");
fd9abb3d
SG		 1993 return -EINVAL;
1994 }
1995
1996 return 0;
1997}
1998
1999static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata,
2000 u8 address, u8 *data)
2001{
2002 u32 op = E2P_CMD_EPC_CMD_READ_ | address;
2003 int ret;
2004
dffc6b24 2005 SMSC_TRACE(pdata, drv, "address 0x%x", address);
fd9abb3d
SG		 2006 ret = smsc911x_eeprom_send_cmd(pdata, op);
2007
2008 if (!ret)
2009 data[address] = smsc911x_reg_read(pdata, E2P_DATA);
2010
2011 return ret;
2012}
2013
2014static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
2015 u8 address, u8 data)
2016{
2017 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
58add9fc 2018 u32 temp;
fd9abb3d
SG		 2019 int ret;
2020
dffc6b24 2021 SMSC_TRACE(pdata, drv, "address 0x%x, data 0x%x", address, data);
fd9abb3d
SG		 2022 ret = smsc911x_eeprom_send_cmd(pdata, op);
2023
2024 if (!ret) {
2025 op = E2P_CMD_EPC_CMD_WRITE_ | address;
2026 smsc911x_reg_write(pdata, E2P_DATA, (u32)data);
58add9fc
SG		 2027
2028 /* Workaround for hardware read-after-write restriction */
2029 temp = smsc911x_reg_read(pdata, BYTE_TEST);
2030
fd9abb3d
SG		 2031 ret = smsc911x_eeprom_send_cmd(pdata, op);
2032 }
2033
2034 return ret;
2035}
2036
2037static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev)
2038{
2039 return SMSC911X_EEPROM_SIZE;
2040}
2041
2042static int smsc911x_ethtool_get_eeprom(struct net_device *dev,
2043 struct ethtool_eeprom *eeprom, u8 *data)
2044{
2045 struct smsc911x_data *pdata = netdev_priv(dev);
2046 u8 eeprom_data[SMSC911X_EEPROM_SIZE];
2047 int len;
2048 int i;
2049
2050 smsc911x_eeprom_enable_access(pdata);
2051
2052 len = min(eeprom->len, SMSC911X_EEPROM_SIZE);
2053 for (i = 0; i < len; i++) {
2054 int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data);
2055 if (ret < 0) {
2056 eeprom->len = 0;
2057 return ret;
2058 }
2059 }
2060
2061 memcpy(data, &eeprom_data[eeprom->offset], len);
2062 eeprom->len = len;
2063 return 0;
2064}
2065
2066static int smsc911x_ethtool_set_eeprom(struct net_device *dev,
2067 struct ethtool_eeprom *eeprom, u8 *data)
2068{
2069 int ret;
2070 struct smsc911x_data *pdata = netdev_priv(dev);
2071
2072 smsc911x_eeprom_enable_access(pdata);
2073 smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_);
2074 ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data);
2075 smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_);
2076
2077 /* Single byte write, according to man page */
2078 eeprom->len = 1;
2079
2080 return ret;
2081}
2082
cb5b04fe 2083static const struct ethtool_ops smsc911x_ethtool_ops = {
fd9abb3d
SG		 2084 .get_settings = smsc911x_ethtool_getsettings,
2085 .set_settings = smsc911x_ethtool_setsettings,
2086 .get_link = ethtool_op_get_link,
2087 .get_drvinfo = smsc911x_ethtool_getdrvinfo,
2088 .nway_reset = smsc911x_ethtool_nwayreset,
2089 .get_msglevel = smsc911x_ethtool_getmsglevel,
2090 .set_msglevel = smsc911x_ethtool_setmsglevel,
2091 .get_regs_len = smsc911x_ethtool_getregslen,
2092 .get_regs = smsc911x_ethtool_getregs,
2093 .get_eeprom_len = smsc911x_ethtool_get_eeprom_len,
2094 .get_eeprom = smsc911x_ethtool_get_eeprom,
2095 .set_eeprom = smsc911x_ethtool_set_eeprom,
b5d1d256 2096 .get_ts_info = ethtool_op_get_ts_info,
fd9abb3d
SG		 2097};
2098
631b7568
SG		 2099static const struct net_device_ops smsc911x_netdev_ops = {
2100 .ndo_open = smsc911x_open,
2101 .ndo_stop = smsc911x_stop,
2102 .ndo_start_xmit = smsc911x_hard_start_xmit,
2103 .ndo_get_stats = smsc911x_get_stats,
afc4b13d 2104 .ndo_set_rx_mode = smsc911x_set_multicast_list,
631b7568 2105 .ndo_do_ioctl = smsc911x_do_ioctl,
635ecaa7 2106 .ndo_change_mtu = eth_change_mtu,
631b7568 2107 .ndo_validate_addr = eth_validate_addr,
225ddf49 2108 .ndo_set_mac_address = smsc911x_set_mac_address,
631b7568
SG		 2109#ifdef CONFIG_NET_POLL_CONTROLLER
2110 .ndo_poll_controller = smsc911x_poll_controller,
2111#endif
2112};
2113
31f45747 2114/* copies the current mac address from hardware to dev->dev_addr */
8489ec1f 2115static void smsc911x_read_mac_address(struct net_device *dev)
31f45747
SG		 2116{
2117 struct smsc911x_data *pdata = netdev_priv(dev);
2118 u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH);
2119 u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL);
2120
2121 dev->dev_addr[0] = (u8)(mac_low32);
2122 dev->dev_addr[1] = (u8)(mac_low32 >> 8);
2123 dev->dev_addr[2] = (u8)(mac_low32 >> 16);
2124 dev->dev_addr[3] = (u8)(mac_low32 >> 24);
2125 dev->dev_addr[4] = (u8)(mac_high16);
2126 dev->dev_addr[5] = (u8)(mac_high16 >> 8);
2127}
2128
fd9abb3d 2129/* Initializing private device structures, only called from probe */
8489ec1f 2130static int smsc911x_init(struct net_device *dev)
fd9abb3d
SG		 2131{
2132 struct smsc911x_data *pdata = netdev_priv(dev);
769ce4c9 2133 unsigned int byte_test, mask;
3ac3546e 2134 unsigned int to = 100;
fd9abb3d 2135
dffc6b24
JP		 2136 SMSC_TRACE(pdata, probe, "Driver Parameters:");
2137 SMSC_TRACE(pdata, probe, "LAN base: 0x%08lX",
2138 (unsigned long)pdata->ioaddr);
2139 SMSC_TRACE(pdata, probe, "IRQ: %d", dev->irq);
2140 SMSC_TRACE(pdata, probe, "PHY will be autodetected.");
fd9abb3d 2141
fd9abb3d 2142 spin_lock_init(&pdata->dev_lock);
35a67edf 2143 spin_lock_init(&pdata->mac_lock);
fd9abb3d 2144
6fed9592 2145 if (pdata->ioaddr == NULL) {
dffc6b24 2146 SMSC_WARN(pdata, probe, "pdata->ioaddr: 0x00000000");
fd9abb3d
SG		 2147 return -ENODEV;
2148 }
2149
3ac3546e
RM		 2150 /*
2151 * poll the READY bit in PMT_CTRL. Any other access to the device is
2152 * forbidden while this bit isn't set. Try for 100ms
769ce4c9
KP		 2153 *
2154 * Note that this test is done before the WORD_SWAP register is
2155 * programmed. So in some configurations the READY bit is at 16 before
2156 * WORD_SWAP is written to. This issue is worked around by waiting
2157 * until either bit 0 or bit 16 gets set in PMT_CTRL.
2158 *
2159 * SMSC has confirmed that checking bit 16 (marked as reserved in
2160 * the datasheet) is fine since these bits "will either never be set
2161 * or can only go high after READY does (so also indicate the device
2162 * is ready)".
3ac3546e 2163 */
769ce4c9
KP		 2164
2165 mask = PMT_CTRL_READY_ | swahw32(PMT_CTRL_READY_);
2166 while (!(smsc911x_reg_read(pdata, PMT_CTRL) & mask) && --to)
3ac3546e 2167 udelay(1000);
769ce4c9 2168
3ac3546e
RM		 2169 if (to == 0) {
2170 pr_err("Device not READY in 100ms aborting\n");
2171 return -ENODEV;
2172 }
2173
fd9abb3d
SG		 2174 /* Check byte ordering */
2175 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
dffc6b24 2176 SMSC_TRACE(pdata, probe, "BYTE_TEST: 0x%08X", byte_test);
fd9abb3d 2177 if (byte_test == 0x43218765) {
dffc6b24
JP		 2178 SMSC_TRACE(pdata, probe, "BYTE_TEST looks swapped, "
2179 "applying WORD_SWAP");
fd9abb3d
SG		 2180 smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff);
2181
2182 /* 1 dummy read of BYTE_TEST is needed after a write to
2183 * WORD_SWAP before its contents are valid */
2184 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
2185
2186 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
2187 }
2188
2189 if (byte_test != 0x87654321) {
dffc6b24 2190 SMSC_WARN(pdata, drv, "BYTE_TEST: 0x%08X", byte_test);
fd9abb3d 2191 if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) {
dffc6b24
JP		 2192 SMSC_WARN(pdata, probe,
2193 "top 16 bits equal to bottom 16 bits");
2194 SMSC_TRACE(pdata, probe,
2195 "This may mean the chip is set "
2196 "for 32 bit while the bus is reading 16 bit");
fd9abb3d
SG		 2197 }
2198 return -ENODEV;
2199 }
2200
2201 /* Default generation to zero (all workarounds apply) */
2202 pdata->generation = 0;
2203
2204 pdata->idrev = smsc911x_reg_read(pdata, ID_REV);
2205 switch (pdata->idrev & 0xFFFF0000) {
2206 case 0x01180000:
2207 case 0x01170000:
2208 case 0x01160000:
2209 case 0x01150000:
28c21379 2210 case 0x218A0000:
fd9abb3d
SG		 2211 /* LAN911[5678] family */
2212 pdata->generation = pdata->idrev & 0x0000FFFF;
2213 break;
2214
2215 case 0x118A0000:
2216 case 0x117A0000:
2217 case 0x116A0000:
2218 case 0x115A0000:
2219 /* LAN921[5678] family */
2220 pdata->generation = 3;
2221 break;
2222
2223 case 0x92100000:
2224 case 0x92110000:
2225 case 0x92200000:
2226 case 0x92210000:
2227 /* LAN9210/LAN9211/LAN9220/LAN9221 */
2228 pdata->generation = 4;
2229 break;
2230
2231 default:
dffc6b24
JP		 2232 SMSC_WARN(pdata, probe, "LAN911x not identified, idrev: 0x%08X",
2233 pdata->idrev);
fd9abb3d
SG		 2234 return -ENODEV;
2235 }
2236
dffc6b24
JP		 2237 SMSC_TRACE(pdata, probe,
2238 "LAN911x identified, idrev: 0x%08X, generation: %d",
2239 pdata->idrev, pdata->generation);
fd9abb3d
SG		 2240
2241 if (pdata->generation == 0)
dffc6b24
JP		 2242 SMSC_WARN(pdata, probe,
2243 "This driver is not intended for this chip revision");
fd9abb3d 2244
31f45747
SG		 2245 /* workaround for platforms without an eeprom, where the mac address
2246 * is stored elsewhere and set by the bootloader. This saves the
2247 * mac address before resetting the device */
35a67edf
EBS		 2248 if (pdata->config.flags & SMSC911X_SAVE_MAC_ADDRESS) {
2249 spin_lock_irq(&pdata->mac_lock);
31f45747 2250 smsc911x_read_mac_address(dev);
35a67edf
EBS		 2251 spin_unlock_irq(&pdata->mac_lock);
2252 }
31f45747 2253
fd9abb3d
SG		 2254 /* Reset the LAN911x */
2255 if (smsc911x_soft_reset(pdata))
2256 return -ENODEV;
2257
fd9abb3d 2258 ether_setup(dev);
fd9abb3d 2259 dev->flags |= IFF_MULTICAST;
fd9abb3d 2260 netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT);
631b7568 2261 dev->netdev_ops = &smsc911x_netdev_ops;
fd9abb3d
SG		 2262 dev->ethtool_ops = &smsc911x_ethtool_ops;
2263
fd9abb3d
SG		 2264 return 0;
2265}
2266
8489ec1f 2267static int smsc911x_drv_remove(struct platform_device *pdev)
fd9abb3d
SG		 2268{
2269 struct net_device *dev;
2270 struct smsc911x_data *pdata;
2271 struct resource *res;
2272
2273 dev = platform_get_drvdata(pdev);
2274 BUG_ON(!dev);
2275 pdata = netdev_priv(dev);
2276 BUG_ON(!pdata);
2277 BUG_ON(!pdata->ioaddr);
2278 BUG_ON(!pdata->phy_dev);
2279
dffc6b24 2280 SMSC_TRACE(pdata, ifdown, "Stopping driver");
fd9abb3d
SG		 2281
2282 phy_disconnect(pdata->phy_dev);
2283 pdata->phy_dev = NULL;
2284 mdiobus_unregister(pdata->mii_bus);
2285 mdiobus_free(pdata->mii_bus);
2286
fd9abb3d
SG		 2287 unregister_netdev(dev);
2288 free_irq(dev->irq, dev);
2289 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2290 "smsc911x-memory");
2291 if (!res)
d4522739 2292 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
fd9abb3d 2293
39424539 2294 release_mem_region(res->start, resource_size(res));
fd9abb3d
SG		 2295
2296 iounmap(pdata->ioaddr);
2297
c7e963f6
RM		 2298 (void)smsc911x_disable_resources(pdev);
2299 smsc911x_free_resources(pdev);
2300
fd9abb3d
SG		 2301 free_netdev(dev);
2302
2303 return 0;
2304}
2305
c326de88
MP		 2306/* standard register acces */
2307static const struct smsc911x_ops standard_smsc911x_ops = {
2308 .reg_read = __smsc911x_reg_read,
2309 .reg_write = __smsc911x_reg_write,
2310 .rx_readfifo = smsc911x_rx_readfifo,
2311 .tx_writefifo = smsc911x_tx_writefifo,
2312};
2313
2314/* shifted register access */
2315static const struct smsc911x_ops shifted_smsc911x_ops = {
2316 .reg_read = __smsc911x_reg_read_shift,
2317 .reg_write = __smsc911x_reg_write_shift,
2318 .rx_readfifo = smsc911x_rx_readfifo_shift,
2319 .tx_writefifo = smsc911x_tx_writefifo_shift,
2320};
2321
79f88ee9 2322#ifdef CONFIG_OF
1dd06ae8
GKH		 2323static int smsc911x_probe_config_dt(struct smsc911x_platform_config *config,
2324 struct device_node *np)
79f88ee9
SG		 2325{
2326 const char *mac;
2327 u32 width = 0;
2328
2329 if (!np)
2330 return -ENODEV;
2331
2332 config->phy_interface = of_get_phy_mode(np);
2333
2334 mac = of_get_mac_address(np);
2335 if (mac)
2336 memcpy(config->mac, mac, ETH_ALEN);
2337
2338 of_property_read_u32(np, "reg-shift", &config->shift);
2339
2340 of_property_read_u32(np, "reg-io-width", &width);
2341 if (width == 4)
2342 config->flags |= SMSC911X_USE_32BIT;
f26cd41a
DM		 2343 else
2344 config->flags |= SMSC911X_USE_16BIT;
79f88ee9
SG		 2345
2346 if (of_get_property(np, "smsc,irq-active-high", NULL))
2347 config->irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH;
2348
2349 if (of_get_property(np, "smsc,irq-push-pull", NULL))
2350 config->irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL;
2351
2352 if (of_get_property(np, "smsc,force-internal-phy", NULL))
2353 config->flags |= SMSC911X_FORCE_INTERNAL_PHY;
2354
2355 if (of_get_property(np, "smsc,force-external-phy", NULL))
2356 config->flags |= SMSC911X_FORCE_EXTERNAL_PHY;
2357
2358 if (of_get_property(np, "smsc,save-mac-address", NULL))
2359 config->flags |= SMSC911X_SAVE_MAC_ADDRESS;
2360
2361 return 0;
2362}
2363#else
2364static inline int smsc911x_probe_config_dt(
2365 struct smsc911x_platform_config *config,
2366 struct device_node *np)
2367{
2368 return -ENODEV;
2369}
2370#endif /* CONFIG_OF */
2371
8489ec1f 2372static int smsc911x_drv_probe(struct platform_device *pdev)
fd9abb3d 2373{
79f88ee9 2374 struct device_node *np = pdev->dev.of_node;
fd9abb3d
SG		 2375 struct net_device *dev;
2376 struct smsc911x_data *pdata;
495c765d 2377 struct smsc911x_platform_config *config = dev_get_platdata(&pdev->dev);
61307ed8 2378 struct resource *res, *irq_res;
fd9abb3d 2379 unsigned int intcfg = 0;
61307ed8 2380 int res_size, irq_flags;
fd9abb3d 2381 int retval;
fd9abb3d 2382
dffc6b24 2383 pr_info("Driver version %s\n", SMSC_DRV_VERSION);
fd9abb3d
SG		 2384
2385 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2386 "smsc911x-memory");
2387 if (!res)
2388 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2389 if (!res) {
dffc6b24 2390 pr_warn("Could not allocate resource\n");
fd9abb3d
SG		 2391 retval = -ENODEV;
2392 goto out_0;
2393 }
39424539 2394 res_size = resource_size(res);
fd9abb3d 2395
61307ed8
SG		 2396 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2397 if (!irq_res) {
dffc6b24 2398 pr_warn("Could not allocate irq resource\n");
61307ed8
SG		 2399 retval = -ENODEV;
2400 goto out_0;
2401 }
2402
fd9abb3d
SG		 2403 if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) {
2404 retval = -EBUSY;
2405 goto out_0;
2406 }
2407
2408 dev = alloc_etherdev(sizeof(struct smsc911x_data));
2409 if (!dev) {
fd9abb3d
SG		 2410 retval = -ENOMEM;
2411 goto out_release_io_1;
2412 }
2413
2414 SET_NETDEV_DEV(dev, &pdev->dev);
2415
2416 pdata = netdev_priv(dev);
61307ed8
SG		 2417 dev->irq = irq_res->start;
2418 irq_flags = irq_res->flags & IRQF_TRIGGER_MASK;
fd9abb3d
SG		 2419 pdata->ioaddr = ioremap_nocache(res->start, res_size);
2420
fd9abb3d
SG		 2421 pdata->dev = dev;
2422 pdata->msg_enable = ((1 << debug) - 1);
2423
c7e963f6
RM		 2424 platform_set_drvdata(pdev, dev);
2425
2426 retval = smsc911x_request_resources(pdev);
2427 if (retval)
2e1d4a06 2428 goto out_request_resources_fail;
c7e963f6
RM		 2429
2430 retval = smsc911x_enable_resources(pdev);
2431 if (retval)
2e1d4a06 2432 goto out_enable_resources_fail;
c7e963f6 2433
fd9abb3d 2434 if (pdata->ioaddr == NULL) {
dffc6b24 2435 SMSC_WARN(pdata, probe, "Error smsc911x base address invalid");
fd9abb3d 2436 retval = -ENOMEM;
c7e963f6 2437 goto out_disable_resources;
fd9abb3d
SG		 2438 }
2439
79f88ee9
SG		 2440 retval = smsc911x_probe_config_dt(&pdata->config, np);
2441 if (retval && config) {
2442 /* copy config parameters across to pdata */
2443 memcpy(&pdata->config, config, sizeof(pdata->config));
2444 retval = 0;
2445 }
2446
2447 if (retval) {
2448 SMSC_WARN(pdata, probe, "Error smsc911x config not found");
c7e963f6 2449 goto out_disable_resources;
79f88ee9
SG		 2450 }
2451
c326de88
MP		 2452 /* assume standard, non-shifted, access to HW registers */
2453 pdata->ops = &standard_smsc911x_ops;
2454 /* apply the right access if shifting is needed */
79f88ee9 2455 if (pdata->config.shift)
c326de88
MP		 2456 pdata->ops = &shifted_smsc911x_ops;
2457
fd9abb3d
SG		 2458 retval = smsc911x_init(dev);
2459 if (retval < 0)
c7e963f6 2460 goto out_disable_resources;
fd9abb3d
SG		 2461
2462 /* configure irq polarity and type before connecting isr */
2107fb8b 2463 if (pdata->config.irq_polarity == SMSC911X_IRQ_POLARITY_ACTIVE_HIGH)
fd9abb3d
SG		 2464 intcfg |= INT_CFG_IRQ_POL_;
2465
2107fb8b 2466 if (pdata->config.irq_type == SMSC911X_IRQ_TYPE_PUSH_PULL)
fd9abb3d
SG		 2467 intcfg |= INT_CFG_IRQ_TYPE_;
2468
2469 smsc911x_reg_write(pdata, INT_CFG, intcfg);
2470
2471 /* Ensure interrupts are globally disabled before connecting ISR */
8e27628e 2472 smsc911x_disable_irq_chip(dev);
fd9abb3d 2473
61307ed8 2474 retval = request_irq(dev->irq, smsc911x_irqhandler,
e81259b4 2475 irq_flags | IRQF_SHARED, dev->name, dev);
fd9abb3d 2476 if (retval) {
dffc6b24
JP		 2477 SMSC_WARN(pdata, probe,
2478 "Unable to claim requested irq: %d", dev->irq);
163faf31 2479 goto out_disable_resources;
fd9abb3d
SG		 2480 }
2481
fd9abb3d
SG		 2482 retval = register_netdev(dev);
2483 if (retval) {
dffc6b24 2484 SMSC_WARN(pdata, probe, "Error %i registering device", retval);
c7e963f6 2485 goto out_free_irq;
fd9abb3d 2486 } else {
dffc6b24
JP		 2487 SMSC_TRACE(pdata, probe,
2488 "Network interface: \"%s\"", dev->name);
fd9abb3d
SG		 2489 }
2490
fd9abb3d
SG		 2491 retval = smsc911x_mii_init(pdev, dev);
2492 if (retval) {
dffc6b24 2493 SMSC_WARN(pdata, probe, "Error %i initialising mii", retval);
fd9abb3d
SG		 2494 goto out_unregister_netdev_5;
2495 }
2496
2497 spin_lock_irq(&pdata->mac_lock);
2498
2499 /* Check if mac address has been specified when bringing interface up */
2500 if (is_valid_ether_addr(dev->dev_addr)) {
225ddf49 2501 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
dffc6b24
JP		 2502 SMSC_TRACE(pdata, probe,
2503 "MAC Address is specified by configuration");
aace4959
ML		 2504 } else if (is_valid_ether_addr(pdata->config.mac)) {
2505 memcpy(dev->dev_addr, pdata->config.mac, 6);
dffc6b24
JP		 2506 SMSC_TRACE(pdata, probe,
2507 "MAC Address specified by platform data");
fd9abb3d
SG		 2508 } else {
2509 /* Try reading mac address from device. if EEPROM is present
2510 * it will already have been set */
62747cd2 2511 smsc_get_mac(dev);
fd9abb3d
SG		 2512
2513 if (is_valid_ether_addr(dev->dev_addr)) {
2514 /* eeprom values are valid so use them */
dffc6b24
JP		 2515 SMSC_TRACE(pdata, probe,
2516 "Mac Address is read from LAN911x EEPROM");
fd9abb3d
SG		 2517 } else {
2518 /* eeprom values are invalid, generate random MAC */
7ce5d222 2519 eth_hw_addr_random(dev);
225ddf49 2520 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
dffc6b24 2521 SMSC_TRACE(pdata, probe,
7efd26d0 2522 "MAC Address is set to eth_random_addr");
fd9abb3d
SG		 2523 }
2524 }
2525
2526 spin_unlock_irq(&pdata->mac_lock);
2527
dffc6b24 2528 netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr);
fd9abb3d
SG		 2529
2530 return 0;
2531
2532out_unregister_netdev_5:
2533 unregister_netdev(dev);
c7e963f6 2534out_free_irq:
fd9abb3d 2535 free_irq(dev->irq, dev);
c7e963f6
RM		 2536out_disable_resources:
2537 (void)smsc911x_disable_resources(pdev);
2e1d4a06 2538out_enable_resources_fail:
c7e963f6 2539 smsc911x_free_resources(pdev);
2e1d4a06 2540out_request_resources_fail:
fd9abb3d 2541 iounmap(pdata->ioaddr);
fd9abb3d
SG		 2542 free_netdev(dev);
2543out_release_io_1:
39424539 2544 release_mem_region(res->start, resource_size(res));
fd9abb3d
SG		 2545out_0:
2546 return retval;
2547}
2548
b6907b0c
DM		 2549#ifdef CONFIG_PM
2550/* This implementation assumes the devices remains powered on its VDDVARIO
2551 * pins during suspend. */
2552
6cb87823
DM		 2553/* TODO: implement freeze/thaw callbacks for hibernation.*/
2554
2555static int smsc911x_suspend(struct device *dev)
b6907b0c 2556{
6cb87823
DM		 2557 struct net_device *ndev = dev_get_drvdata(dev);
2558 struct smsc911x_data *pdata = netdev_priv(ndev);
b6907b0c
DM		 2559
2560 /* enable wake on LAN, energy detection and the external PME
2561 * signal. */
2562 smsc911x_reg_write(pdata, PMT_CTRL,
2563 PMT_CTRL_PM_MODE_D1_ | PMT_CTRL_WOL_EN_ |
2564 PMT_CTRL_ED_EN_ | PMT_CTRL_PME_EN_);
2565
2566 return 0;
2567}
2568
6cb87823 2569static int smsc911x_resume(struct device *dev)
b6907b0c 2570{
6cb87823
DM		 2571 struct net_device *ndev = dev_get_drvdata(dev);
2572 struct smsc911x_data *pdata = netdev_priv(ndev);
b6907b0c
DM		 2573 unsigned int to = 100;
2574
2575 /* Note 3.11 from the datasheet:
2576 * "When the LAN9220 is in a power saving state, a write of any
2577 * data to the BYTE_TEST register will wake-up the device."
2578 */
2579 smsc911x_reg_write(pdata, BYTE_TEST, 0);
2580
2581 /* poll the READY bit in PMT_CTRL. Any other access to the device is
2582 * forbidden while this bit isn't set. Try for 100ms and return -EIO
2583 * if it failed. */
2584 while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to)
2585 udelay(1000);
2586
2587 return (to == 0) ? -EIO : 0;
2588}
2589
47145210 2590static const struct dev_pm_ops smsc911x_pm_ops = {
6cb87823
DM		 2591 .suspend = smsc911x_suspend,
2592 .resume = smsc911x_resume,
2593};
2594
2595#define SMSC911X_PM_OPS (&smsc911x_pm_ops)
2596
b6907b0c 2597#else
6cb87823 2598#define SMSC911X_PM_OPS NULL
b6907b0c
DM		 2599#endif
2600
d62fdf8b 2601#ifdef CONFIG_OF
79f88ee9
SG		 2602static const struct of_device_id smsc911x_dt_ids[] = {
2603 { .compatible = "smsc,lan9115", },
2604 { /* sentinel */ }
2605};
2606MODULE_DEVICE_TABLE(of, smsc911x_dt_ids);
d62fdf8b 2607#endif
79f88ee9 2608
fd9abb3d
SG		 2609static struct platform_driver smsc911x_driver = {
2610 .probe = smsc911x_drv_probe,
8489ec1f 2611 .remove = smsc911x_drv_remove,
fd9abb3d 2612 .driver = {
6cb87823
DM		 2613 .name = SMSC_CHIPNAME,
2614 .owner = THIS_MODULE,
2615 .pm = SMSC911X_PM_OPS,
d62fdf8b 2616 .of_match_table = of_match_ptr(smsc911x_dt_ids),
fd9abb3d
SG		 2617 },
2618};
2619
2620/* Entry point for loading the module */
2621static int __init smsc911x_init_module(void)
2622{
62747cd2 2623 SMSC_INITIALIZE();
fd9abb3d
SG		 2624 return platform_driver_register(&smsc911x_driver);
2625}
2626
2627/* entry point for unloading the module */
2628static void __exit smsc911x_cleanup_module(void)
2629{
2630 platform_driver_unregister(&smsc911x_driver);
2631}
2632
2633module_init(smsc911x_init_module);
2634module_exit(smsc911x_cleanup_module);
Linux 6.x block layer and io_uring tree(s)