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net: introduce IFF_UNICAST_FLT private flag
[linux-2.6-block.git] / drivers / net / ethernet / smsc / smsc911x.c
CommitLineData
fd9abb3d
SG		 1/***************************************************************************
2 *
3 * Copyright (C) 2004-2008 SMSC
4 * Copyright (C) 2005-2008 ARM
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 *
20 ***************************************************************************
21 * Rewritten, heavily based on smsc911x simple driver by SMSC.
22 * Partly uses io macros from smc91x.c by Nicolas Pitre
23 *
24 * Supported devices:
25 * LAN9115, LAN9116, LAN9117, LAN9118
26 * LAN9215, LAN9216, LAN9217, LAN9218
27 * LAN9210, LAN9211
28 * LAN9220, LAN9221
29 *
30 */
31
dffc6b24
JP		 32#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
33
fd9abb3d
SG		 34#include <linux/crc32.h>
35#include <linux/delay.h>
36#include <linux/errno.h>
37#include <linux/etherdevice.h>
38#include <linux/ethtool.h>
39#include <linux/init.h>
a6b7a407 40#include <linux/interrupt.h>
fd9abb3d
SG		 41#include <linux/ioport.h>
42#include <linux/kernel.h>
43#include <linux/module.h>
44#include <linux/netdevice.h>
45#include <linux/platform_device.h>
46#include <linux/sched.h>
fd9abb3d 47#include <linux/timer.h>
fd9abb3d
SG		 48#include <linux/bug.h>
49#include <linux/bitops.h>
50#include <linux/irq.h>
51#include <linux/io.h>
833cc67c 52#include <linux/swab.h>
fd9abb3d
SG		 53#include <linux/phy.h>
54#include <linux/smsc911x.h>
6cb87823 55#include <linux/device.h>
79f88ee9
SG		 56#include <linux/of.h>
57#include <linux/of_device.h>
58#include <linux/of_gpio.h>
59#include <linux/of_net.h>
fd9abb3d
SG		 60#include "smsc911x.h"
61
62#define SMSC_CHIPNAME "smsc911x"
63#define SMSC_MDIONAME "smsc911x-mdio"
64#define SMSC_DRV_VERSION "2008-10-21"
65
66MODULE_LICENSE("GPL");
67MODULE_VERSION(SMSC_DRV_VERSION);
62038e4a 68MODULE_ALIAS("platform:smsc911x");
fd9abb3d
SG		 69
70#if USE_DEBUG > 0
71static int debug = 16;
72#else
73static int debug = 3;
74#endif
75
76module_param(debug, int, 0);
77MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
78
c326de88
MP		 79struct smsc911x_data;
80
81struct smsc911x_ops {
82 u32 (*reg_read)(struct smsc911x_data *pdata, u32 reg);
83 void (*reg_write)(struct smsc911x_data *pdata, u32 reg, u32 val);
84 void (*rx_readfifo)(struct smsc911x_data *pdata,
85 unsigned int *buf, unsigned int wordcount);
86 void (*tx_writefifo)(struct smsc911x_data *pdata,
87 unsigned int *buf, unsigned int wordcount);
88};
89
fd9abb3d
SG		 90struct smsc911x_data {
91 void __iomem *ioaddr;
92
93 unsigned int idrev;
94
95 /* used to decide which workarounds apply */
96 unsigned int generation;
97
98 /* device configuration (copied from platform_data during probe) */
2107fb8b 99 struct smsc911x_platform_config config;
fd9abb3d
SG		 100
101 /* This needs to be acquired before calling any of below:
102 * smsc911x_mac_read(), smsc911x_mac_write()
103 */
104 spinlock_t mac_lock;
105
492c5d94 106 /* spinlock to ensure register accesses are serialised */
fd9abb3d 107 spinlock_t dev_lock;
fd9abb3d
SG		 108
109 struct phy_device *phy_dev;
110 struct mii_bus *mii_bus;
111 int phy_irq[PHY_MAX_ADDR];
112 unsigned int using_extphy;
113 int last_duplex;
114 int last_carrier;
115
116 u32 msg_enable;
117 unsigned int gpio_setting;
118 unsigned int gpio_orig_setting;
119 struct net_device *dev;
120 struct napi_struct napi;
121
122 unsigned int software_irq_signal;
123
124#ifdef USE_PHY_WORK_AROUND
125#define MIN_PACKET_SIZE (64)
126 char loopback_tx_pkt[MIN_PACKET_SIZE];
127 char loopback_rx_pkt[MIN_PACKET_SIZE];
128 unsigned int resetcount;
129#endif
130
131 /* Members for Multicast filter workaround */
132 unsigned int multicast_update_pending;
133 unsigned int set_bits_mask;
134 unsigned int clear_bits_mask;
135 unsigned int hashhi;
136 unsigned int hashlo;
c326de88
MP		 137
138 /* register access functions */
139 const struct smsc911x_ops *ops;
fd9abb3d
SG		 140};
141
c326de88
MP		 142/* Easy access to information */
143#define __smsc_shift(pdata, reg) ((reg) << ((pdata)->config.shift))
144
492c5d94 145static inline u32 __smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
fd9abb3d 146{
2107fb8b
SG		 147 if (pdata->config.flags & SMSC911X_USE_32BIT)
148 return readl(pdata->ioaddr + reg);
149
492c5d94
CM		 150 if (pdata->config.flags & SMSC911X_USE_16BIT)
151 return ((readw(pdata->ioaddr + reg) & 0xFFFF) |
2107fb8b 152 ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16));
fd9abb3d 153
2107fb8b 154 BUG();
702403af 155 return 0;
fd9abb3d
SG		 156}
157
c326de88
MP		 158static inline u32
159__smsc911x_reg_read_shift(struct smsc911x_data *pdata, u32 reg)
160{
161 if (pdata->config.flags & SMSC911X_USE_32BIT)
162 return readl(pdata->ioaddr + __smsc_shift(pdata, reg));
163
164 if (pdata->config.flags & SMSC911X_USE_16BIT)
165 return (readw(pdata->ioaddr +
166 __smsc_shift(pdata, reg)) & 0xFFFF) |
167 ((readw(pdata->ioaddr +
168 __smsc_shift(pdata, reg + 2)) & 0xFFFF) << 16);
169
170 BUG();
171 return 0;
172}
173
492c5d94
CM		 174static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
175{
176 u32 data;
177 unsigned long flags;
178
179 spin_lock_irqsave(&pdata->dev_lock, flags);
c326de88 180 data = pdata->ops->reg_read(pdata, reg);
492c5d94
CM		 181 spin_unlock_irqrestore(&pdata->dev_lock, flags);
182
183 return data;
184}
185
186static inline void __smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
187 u32 val)
fd9abb3d 188{
2107fb8b
SG		 189 if (pdata->config.flags & SMSC911X_USE_32BIT) {
190 writel(val, pdata->ioaddr + reg);
191 return;
192 }
193
194 if (pdata->config.flags & SMSC911X_USE_16BIT) {
2107fb8b
SG		 195 writew(val & 0xFFFF, pdata->ioaddr + reg);
196 writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2);
2107fb8b
SG		 197 return;
198 }
fd9abb3d 199
2107fb8b 200 BUG();
fd9abb3d
SG		 201}
202
c326de88
MP		 203static inline void
204__smsc911x_reg_write_shift(struct smsc911x_data *pdata, u32 reg, u32 val)
205{
206 if (pdata->config.flags & SMSC911X_USE_32BIT) {
207 writel(val, pdata->ioaddr + __smsc_shift(pdata, reg));
208 return;
209 }
210
211 if (pdata->config.flags & SMSC911X_USE_16BIT) {
212 writew(val & 0xFFFF,
213 pdata->ioaddr + __smsc_shift(pdata, reg));
214 writew((val >> 16) & 0xFFFF,
215 pdata->ioaddr + __smsc_shift(pdata, reg + 2));
216 return;
217 }
218
219 BUG();
220}
221
492c5d94
CM		 222static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
223 u32 val)
224{
225 unsigned long flags;
226
227 spin_lock_irqsave(&pdata->dev_lock, flags);
c326de88 228 pdata->ops->reg_write(pdata, reg, val);
492c5d94
CM		 229 spin_unlock_irqrestore(&pdata->dev_lock, flags);
230}
231
fd9abb3d
SG		 232/* Writes a packet to the TX_DATA_FIFO */
233static inline void
234smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf,
235 unsigned int wordcount)
236{
492c5d94
CM		 237 unsigned long flags;
238
239 spin_lock_irqsave(&pdata->dev_lock, flags);
240
833cc67c
MD		 241 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
242 while (wordcount--)
492c5d94
CM		 243 __smsc911x_reg_write(pdata, TX_DATA_FIFO,
244 swab32(*buf++));
245 goto out;
833cc67c
MD		 246 }
247
2107fb8b
SG		 248 if (pdata->config.flags & SMSC911X_USE_32BIT) {
249 writesl(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount);
492c5d94 250 goto out;
2107fb8b
SG		 251 }
252
253 if (pdata->config.flags & SMSC911X_USE_16BIT) {
254 while (wordcount--)
492c5d94
CM		 255 __smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++);
256 goto out;
2107fb8b
SG		 257 }
258
259 BUG();
492c5d94
CM		 260out:
261 spin_unlock_irqrestore(&pdata->dev_lock, flags);
fd9abb3d
SG		 262}
263
c326de88
MP		 264/* Writes a packet to the TX_DATA_FIFO - shifted version */
265static inline void
266smsc911x_tx_writefifo_shift(struct smsc911x_data *pdata, unsigned int *buf,
267 unsigned int wordcount)
268{
269 unsigned long flags;
270
271 spin_lock_irqsave(&pdata->dev_lock, flags);
272
273 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
274 while (wordcount--)
275 __smsc911x_reg_write_shift(pdata, TX_DATA_FIFO,
276 swab32(*buf++));
277 goto out;
278 }
279
280 if (pdata->config.flags & SMSC911X_USE_32BIT) {
281 writesl(pdata->ioaddr + __smsc_shift(pdata,
282 TX_DATA_FIFO), buf, wordcount);
283 goto out;
284 }
285
286 if (pdata->config.flags & SMSC911X_USE_16BIT) {
287 while (wordcount--)
288 __smsc911x_reg_write_shift(pdata,
289 TX_DATA_FIFO, *buf++);
290 goto out;
291 }
292
293 BUG();
294out:
295 spin_unlock_irqrestore(&pdata->dev_lock, flags);
296}
297
fd9abb3d
SG		 298/* Reads a packet out of the RX_DATA_FIFO */
299static inline void
300smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf,
301 unsigned int wordcount)
302{
492c5d94
CM		 303 unsigned long flags;
304
305 spin_lock_irqsave(&pdata->dev_lock, flags);
306
833cc67c
MD		 307 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
308 while (wordcount--)
492c5d94
CM		 309 *buf++ = swab32(__smsc911x_reg_read(pdata,
310 RX_DATA_FIFO));
311 goto out;
833cc67c
MD		 312 }
313
2107fb8b
SG		 314 if (pdata->config.flags & SMSC911X_USE_32BIT) {
315 readsl(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount);
492c5d94 316 goto out;
2107fb8b 317 }
fd9abb3d 318
2107fb8b
SG		 319 if (pdata->config.flags & SMSC911X_USE_16BIT) {
320 while (wordcount--)
492c5d94
CM		 321 *buf++ = __smsc911x_reg_read(pdata, RX_DATA_FIFO);
322 goto out;
2107fb8b
SG		 323 }
324
325 BUG();
492c5d94
CM		 326out:
327 spin_unlock_irqrestore(&pdata->dev_lock, flags);
2107fb8b 328}
fd9abb3d 329
c326de88
MP		 330/* Reads a packet out of the RX_DATA_FIFO - shifted version */
331static inline void
332smsc911x_rx_readfifo_shift(struct smsc911x_data *pdata, unsigned int *buf,
333 unsigned int wordcount)
334{
335 unsigned long flags;
336
337 spin_lock_irqsave(&pdata->dev_lock, flags);
338
339 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
340 while (wordcount--)
341 *buf++ = swab32(__smsc911x_reg_read_shift(pdata,
342 RX_DATA_FIFO));
343 goto out;
344 }
345
346 if (pdata->config.flags & SMSC911X_USE_32BIT) {
347 readsl(pdata->ioaddr + __smsc_shift(pdata,
348 RX_DATA_FIFO), buf, wordcount);
349 goto out;
350 }
351
352 if (pdata->config.flags & SMSC911X_USE_16BIT) {
353 while (wordcount--)
354 *buf++ = __smsc911x_reg_read_shift(pdata,
355 RX_DATA_FIFO);
356 goto out;
357 }
358
359 BUG();
360out:
361 spin_unlock_irqrestore(&pdata->dev_lock, flags);
362}
363
fd9abb3d
SG		 364/* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read
365 * and smsc911x_mac_write, so assumes mac_lock is held */
366static int smsc911x_mac_complete(struct smsc911x_data *pdata)
367{
368 int i;
369 u32 val;
370
371 SMSC_ASSERT_MAC_LOCK(pdata);
372
373 for (i = 0; i < 40; i++) {
374 val = smsc911x_reg_read(pdata, MAC_CSR_CMD);
375 if (!(val & MAC_CSR_CMD_CSR_BUSY_))
376 return 0;
377 }
dffc6b24
JP		 378 SMSC_WARN(pdata, hw, "Timed out waiting for MAC not BUSY. "
379 "MAC_CSR_CMD: 0x%08X", val);
fd9abb3d
SG		 380 return -EIO;
381}
382
383/* Fetches a MAC register value. Assumes mac_lock is acquired */
384static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset)
385{
386 unsigned int temp;
387
388 SMSC_ASSERT_MAC_LOCK(pdata);
389
390 temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
391 if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
dffc6b24 392 SMSC_WARN(pdata, hw, "MAC busy at entry");
fd9abb3d
SG		 393 return 0xFFFFFFFF;
394 }
395
396 /* Send the MAC cmd */
397 smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
398 MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_));
399
400 /* Workaround for hardware read-after-write restriction */
401 temp = smsc911x_reg_read(pdata, BYTE_TEST);
402
403 /* Wait for the read to complete */
404 if (likely(smsc911x_mac_complete(pdata) == 0))
405 return smsc911x_reg_read(pdata, MAC_CSR_DATA);
406
dffc6b24 407 SMSC_WARN(pdata, hw, "MAC busy after read");
fd9abb3d
SG		 408 return 0xFFFFFFFF;
409}
410
411/* Set a mac register, mac_lock must be acquired before calling */
412static void smsc911x_mac_write(struct smsc911x_data *pdata,
413 unsigned int offset, u32 val)
414{
415 unsigned int temp;
416
417 SMSC_ASSERT_MAC_LOCK(pdata);
418
419 temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
420 if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
dffc6b24
JP		 421 SMSC_WARN(pdata, hw,
422 "smsc911x_mac_write failed, MAC busy at entry");
fd9abb3d
SG		 423 return;
424 }
425
426 /* Send data to write */
427 smsc911x_reg_write(pdata, MAC_CSR_DATA, val);
428
429 /* Write the actual data */
430 smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
431 MAC_CSR_CMD_CSR_BUSY_));
432
433 /* Workaround for hardware read-after-write restriction */
434 temp = smsc911x_reg_read(pdata, BYTE_TEST);
435
436 /* Wait for the write to complete */
437 if (likely(smsc911x_mac_complete(pdata) == 0))
438 return;
439
dffc6b24 440 SMSC_WARN(pdata, hw, "smsc911x_mac_write failed, MAC busy after write");
fd9abb3d
SG		 441}
442
443/* Get a phy register */
444static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
445{
446 struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
447 unsigned long flags;
448 unsigned int addr;
449 int i, reg;
450
451 spin_lock_irqsave(&pdata->mac_lock, flags);
452
453 /* Confirm MII not busy */
454 if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
dffc6b24 455 SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_read???");
fd9abb3d
SG		 456 reg = -EIO;
457 goto out;
458 }
459
460 /* Set the address, index & direction (read from PHY) */
461 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6);
462 smsc911x_mac_write(pdata, MII_ACC, addr);
463
464 /* Wait for read to complete w/ timeout */
465 for (i = 0; i < 100; i++)
466 if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
467 reg = smsc911x_mac_read(pdata, MII_DATA);
468 goto out;
469 }
470
dffc6b24 471 SMSC_WARN(pdata, hw, "Timed out waiting for MII read to finish");
fd9abb3d
SG		 472 reg = -EIO;
473
474out:
475 spin_unlock_irqrestore(&pdata->mac_lock, flags);
476 return reg;
477}
478
479/* Set a phy register */
480static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
481 u16 val)
482{
483 struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
484 unsigned long flags;
485 unsigned int addr;
486 int i, reg;
487
488 spin_lock_irqsave(&pdata->mac_lock, flags);
489
490 /* Confirm MII not busy */
491 if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
dffc6b24 492 SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_write???");
fd9abb3d
SG		 493 reg = -EIO;
494 goto out;
495 }
496
497 /* Put the data to write in the MAC */
498 smsc911x_mac_write(pdata, MII_DATA, val);
499
500 /* Set the address, index & direction (write to PHY) */
501 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
502 MII_ACC_MII_WRITE_;
503 smsc911x_mac_write(pdata, MII_ACC, addr);
504
505 /* Wait for write to complete w/ timeout */
506 for (i = 0; i < 100; i++)
507 if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
508 reg = 0;
509 goto out;
510 }
511
dffc6b24 512 SMSC_WARN(pdata, hw, "Timed out waiting for MII write to finish");
fd9abb3d
SG		 513 reg = -EIO;
514
515out:
516 spin_unlock_irqrestore(&pdata->mac_lock, flags);
517 return reg;
518}
519
d23f028a
SG		 520/* Switch to external phy. Assumes tx and rx are stopped. */
521static void smsc911x_phy_enable_external(struct smsc911x_data *pdata)
fd9abb3d
SG		 522{
523 unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
524
d23f028a
SG		 525 /* Disable phy clocks to the MAC */
526 hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
527 hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
528 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
529 udelay(10); /* Enough time for clocks to stop */
fd9abb3d 530
d23f028a
SG		 531 /* Switch to external phy */
532 hwcfg |= HW_CFG_EXT_PHY_EN_;
533 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
fd9abb3d 534
d23f028a
SG		 535 /* Enable phy clocks to the MAC */
536 hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
537 hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
538 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
539 udelay(10); /* Enough time for clocks to restart */
fd9abb3d 540
d23f028a
SG		 541 hwcfg |= HW_CFG_SMI_SEL_;
542 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
543}
fd9abb3d 544
d23f028a
SG		 545/* Autodetects and enables external phy if present on supported chips.
546 * autodetection can be overridden by specifying SMSC911X_FORCE_INTERNAL_PHY
547 * or SMSC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */
548static void smsc911x_phy_initialise_external(struct smsc911x_data *pdata)
549{
550 unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
fd9abb3d 551
d23f028a 552 if (pdata->config.flags & SMSC911X_FORCE_INTERNAL_PHY) {
dffc6b24 553 SMSC_TRACE(pdata, hw, "Forcing internal PHY");
d23f028a
SG		 554 pdata->using_extphy = 0;
555 } else if (pdata->config.flags & SMSC911X_FORCE_EXTERNAL_PHY) {
dffc6b24 556 SMSC_TRACE(pdata, hw, "Forcing external PHY");
d23f028a
SG		 557 smsc911x_phy_enable_external(pdata);
558 pdata->using_extphy = 1;
559 } else if (hwcfg & HW_CFG_EXT_PHY_DET_) {
dffc6b24
JP		 560 SMSC_TRACE(pdata, hw,
561 "HW_CFG EXT_PHY_DET set, using external PHY");
d23f028a 562 smsc911x_phy_enable_external(pdata);
fd9abb3d
SG		 563 pdata->using_extphy = 1;
564 } else {
dffc6b24
JP		 565 SMSC_TRACE(pdata, hw,
566 "HW_CFG EXT_PHY_DET clear, using internal PHY");
d23f028a 567 pdata->using_extphy = 0;
fd9abb3d 568 }
fd9abb3d
SG		 569}
570
571/* Fetches a tx status out of the status fifo */
572static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata)
573{
574 unsigned int result =
575 smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_;
576
577 if (result != 0)
578 result = smsc911x_reg_read(pdata, TX_STATUS_FIFO);
579
580 return result;
581}
582
583/* Fetches the next rx status */
584static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata)
585{
586 unsigned int result =
587 smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_;
588
589 if (result != 0)
590 result = smsc911x_reg_read(pdata, RX_STATUS_FIFO);
591
592 return result;
593}
594
595#ifdef USE_PHY_WORK_AROUND
596static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata)
597{
598 unsigned int tries;
599 u32 wrsz;
600 u32 rdsz;
601 ulong bufp;
602
603 for (tries = 0; tries < 10; tries++) {
604 unsigned int txcmd_a;
605 unsigned int txcmd_b;
606 unsigned int status;
607 unsigned int pktlength;
608 unsigned int i;
609
610 /* Zero-out rx packet memory */
611 memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE);
612
613 /* Write tx packet to 118 */
614 txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16;
615 txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
616 txcmd_a |= MIN_PACKET_SIZE;
617
618 txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE;
619
620 smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a);
621 smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b);
622
623 bufp = (ulong)pdata->loopback_tx_pkt & (~0x3);
624 wrsz = MIN_PACKET_SIZE + 3;
625 wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3);
626 wrsz >>= 2;
627
c326de88 628 pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
fd9abb3d
SG		 629
630 /* Wait till transmit is done */
631 i = 60;
632 do {
633 udelay(5);
634 status = smsc911x_tx_get_txstatus(pdata);
635 } while ((i--) && (!status));
636
637 if (!status) {
dffc6b24
JP		 638 SMSC_WARN(pdata, hw,
639 "Failed to transmit during loopback test");
fd9abb3d
SG		 640 continue;
641 }
642 if (status & TX_STS_ES_) {
dffc6b24
JP		 643 SMSC_WARN(pdata, hw,
644 "Transmit encountered errors during loopback test");
fd9abb3d
SG		 645 continue;
646 }
647
648 /* Wait till receive is done */
649 i = 60;
650 do {
651 udelay(5);
652 status = smsc911x_rx_get_rxstatus(pdata);
653 } while ((i--) && (!status));
654
655 if (!status) {
dffc6b24
JP		 656 SMSC_WARN(pdata, hw,
657 "Failed to receive during loopback test");
fd9abb3d
SG		 658 continue;
659 }
660 if (status & RX_STS_ES_) {
dffc6b24
JP		 661 SMSC_WARN(pdata, hw,
662 "Receive encountered errors during loopback test");
fd9abb3d
SG		 663 continue;
664 }
665
666 pktlength = ((status & 0x3FFF0000UL) >> 16);
667 bufp = (ulong)pdata->loopback_rx_pkt;
668 rdsz = pktlength + 3;
669 rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3);
670 rdsz >>= 2;
671
c326de88 672 pdata->ops->rx_readfifo(pdata, (unsigned int *)bufp, rdsz);
fd9abb3d
SG		 673
674 if (pktlength != (MIN_PACKET_SIZE + 4)) {
dffc6b24
JP		 675 SMSC_WARN(pdata, hw, "Unexpected packet size "
676 "during loop back test, size=%d, will retry",
677 pktlength);
fd9abb3d
SG		 678 } else {
679 unsigned int j;
680 int mismatch = 0;
681 for (j = 0; j < MIN_PACKET_SIZE; j++) {
682 if (pdata->loopback_tx_pkt[j]
683 != pdata->loopback_rx_pkt[j]) {
684 mismatch = 1;
685 break;
686 }
687 }
688 if (!mismatch) {
dffc6b24 689 SMSC_TRACE(pdata, hw, "Successfully verified "
fd9abb3d
SG		 690 "loopback packet");
691 return 0;
692 } else {
dffc6b24
JP		 693 SMSC_WARN(pdata, hw, "Data mismatch "
694 "during loop back test, will retry");
fd9abb3d
SG		 695 }
696 }
697 }
698
699 return -EIO;
700}
701
702static int smsc911x_phy_reset(struct smsc911x_data *pdata)
703{
704 struct phy_device *phy_dev = pdata->phy_dev;
705 unsigned int temp;
706 unsigned int i = 100000;
707
708 BUG_ON(!phy_dev);
709 BUG_ON(!phy_dev->bus);
710
dffc6b24 711 SMSC_TRACE(pdata, hw, "Performing PHY BCR Reset");
fd9abb3d
SG		 712 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_RESET);
713 do {
714 msleep(1);
715 temp = smsc911x_mii_read(phy_dev->bus, phy_dev->addr,
716 MII_BMCR);
717 } while ((i--) && (temp & BMCR_RESET));
718
719 if (temp & BMCR_RESET) {
dffc6b24 720 SMSC_WARN(pdata, hw, "PHY reset failed to complete");
fd9abb3d
SG		 721 return -EIO;
722 }
723 /* Extra delay required because the phy may not be completed with
724 * its reset when BMCR_RESET is cleared. Specs say 256 uS is
725 * enough delay but using 1ms here to be safe */
726 msleep(1);
727
728 return 0;
729}
730
731static int smsc911x_phy_loopbacktest(struct net_device *dev)
732{
733 struct smsc911x_data *pdata = netdev_priv(dev);
734 struct phy_device *phy_dev = pdata->phy_dev;
735 int result = -EIO;
736 unsigned int i, val;
737 unsigned long flags;
738
739 /* Initialise tx packet using broadcast destination address */
740 memset(pdata->loopback_tx_pkt, 0xff, ETH_ALEN);
741
742 /* Use incrementing source address */
743 for (i = 6; i < 12; i++)
744 pdata->loopback_tx_pkt[i] = (char)i;
745
746 /* Set length type field */
747 pdata->loopback_tx_pkt[12] = 0x00;
748 pdata->loopback_tx_pkt[13] = 0x00;
749
750 for (i = 14; i < MIN_PACKET_SIZE; i++)
751 pdata->loopback_tx_pkt[i] = (char)i;
752
753 val = smsc911x_reg_read(pdata, HW_CFG);
754 val &= HW_CFG_TX_FIF_SZ_;
755 val |= HW_CFG_SF_;
756 smsc911x_reg_write(pdata, HW_CFG, val);
757
758 smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
759 smsc911x_reg_write(pdata, RX_CFG,
760 (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8);
761
762 for (i = 0; i < 10; i++) {
763 /* Set PHY to 10/FD, no ANEG, and loopback mode */
764 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR,
765 BMCR_LOOPBACK | BMCR_FULLDPLX);
766
767 /* Enable MAC tx/rx, FD */
768 spin_lock_irqsave(&pdata->mac_lock, flags);
769 smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_
770 | MAC_CR_TXEN_ | MAC_CR_RXEN_);
771 spin_unlock_irqrestore(&pdata->mac_lock, flags);
772
773 if (smsc911x_phy_check_loopbackpkt(pdata) == 0) {
774 result = 0;
775 break;
776 }
777 pdata->resetcount++;
778
779 /* Disable MAC rx */
780 spin_lock_irqsave(&pdata->mac_lock, flags);
781 smsc911x_mac_write(pdata, MAC_CR, 0);
782 spin_unlock_irqrestore(&pdata->mac_lock, flags);
783
784 smsc911x_phy_reset(pdata);
785 }
786
787 /* Disable MAC */
788 spin_lock_irqsave(&pdata->mac_lock, flags);
789 smsc911x_mac_write(pdata, MAC_CR, 0);
790 spin_unlock_irqrestore(&pdata->mac_lock, flags);
791
792 /* Cancel PHY loopback mode */
793 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, 0);
794
795 smsc911x_reg_write(pdata, TX_CFG, 0);
796 smsc911x_reg_write(pdata, RX_CFG, 0);
797
798 return result;
799}
800#endif /* USE_PHY_WORK_AROUND */
801
fd9abb3d
SG		 802static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata)
803{
804 struct phy_device *phy_dev = pdata->phy_dev;
805 u32 afc = smsc911x_reg_read(pdata, AFC_CFG);
806 u32 flow;
807 unsigned long flags;
808
809 if (phy_dev->duplex == DUPLEX_FULL) {
810 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
811 u16 rmtadv = phy_read(phy_dev, MII_LPA);
bc02ff95 812 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
fd9abb3d
SG		 813
814 if (cap & FLOW_CTRL_RX)
815 flow = 0xFFFF0002;
816 else
817 flow = 0;
818
819 if (cap & FLOW_CTRL_TX)
820 afc |= 0xF;
821 else
822 afc &= ~0xF;
823
dffc6b24
JP		 824 SMSC_TRACE(pdata, hw, "rx pause %s, tx pause %s",
825 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
826 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
fd9abb3d 827 } else {
dffc6b24 828 SMSC_TRACE(pdata, hw, "half duplex");
fd9abb3d
SG		 829 flow = 0;
830 afc |= 0xF;
831 }
832
833 spin_lock_irqsave(&pdata->mac_lock, flags);
834 smsc911x_mac_write(pdata, FLOW, flow);
835 spin_unlock_irqrestore(&pdata->mac_lock, flags);
836
837 smsc911x_reg_write(pdata, AFC_CFG, afc);
838}
839
840/* Update link mode if anything has changed. Called periodically when the
841 * PHY is in polling mode, even if nothing has changed. */
842static void smsc911x_phy_adjust_link(struct net_device *dev)
843{
844 struct smsc911x_data *pdata = netdev_priv(dev);
845 struct phy_device *phy_dev = pdata->phy_dev;
846 unsigned long flags;
847 int carrier;
848
849 if (phy_dev->duplex != pdata->last_duplex) {
850 unsigned int mac_cr;
dffc6b24 851 SMSC_TRACE(pdata, hw, "duplex state has changed");
fd9abb3d
SG		 852
853 spin_lock_irqsave(&pdata->mac_lock, flags);
854 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
855 if (phy_dev->duplex) {
dffc6b24
JP		 856 SMSC_TRACE(pdata, hw,
857 "configuring for full duplex mode");
fd9abb3d
SG		 858 mac_cr |= MAC_CR_FDPX_;
859 } else {
dffc6b24
JP		 860 SMSC_TRACE(pdata, hw,
861 "configuring for half duplex mode");
fd9abb3d
SG		 862 mac_cr &= ~MAC_CR_FDPX_;
863 }
864 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
865 spin_unlock_irqrestore(&pdata->mac_lock, flags);
866
867 smsc911x_phy_update_flowcontrol(pdata);
868 pdata->last_duplex = phy_dev->duplex;
869 }
870
871 carrier = netif_carrier_ok(dev);
872 if (carrier != pdata->last_carrier) {
dffc6b24 873 SMSC_TRACE(pdata, hw, "carrier state has changed");
fd9abb3d 874 if (carrier) {
dffc6b24 875 SMSC_TRACE(pdata, hw, "configuring for carrier OK");
fd9abb3d
SG		 876 if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) &&
877 (!pdata->using_extphy)) {
88393161 878 /* Restore original GPIO configuration */
fd9abb3d
SG		 879 pdata->gpio_setting = pdata->gpio_orig_setting;
880 smsc911x_reg_write(pdata, GPIO_CFG,
881 pdata->gpio_setting);
882 }
883 } else {
dffc6b24 884 SMSC_TRACE(pdata, hw, "configuring for no carrier");
fd9abb3d
SG		 885 /* Check global setting that LED1
886 * usage is 10/100 indicator */
887 pdata->gpio_setting = smsc911x_reg_read(pdata,
888 GPIO_CFG);
8e95a202
JP		 889 if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_) &&
890 (!pdata->using_extphy)) {
fd9abb3d 891 /* Force 10/100 LED off, after saving
88393161 892 * original GPIO configuration */
fd9abb3d
SG		 893 pdata->gpio_orig_setting = pdata->gpio_setting;
894
895 pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_;
896 pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_
897 | GPIO_CFG_GPIODIR0_
898 | GPIO_CFG_GPIOD0_);
899 smsc911x_reg_write(pdata, GPIO_CFG,
900 pdata->gpio_setting);
901 }
902 }
903 pdata->last_carrier = carrier;
904 }
905}
906
907static int smsc911x_mii_probe(struct net_device *dev)
908{
909 struct smsc911x_data *pdata = netdev_priv(dev);
910 struct phy_device *phydev = NULL;
e4a474f8 911 int ret;
fd9abb3d
SG		 912
913 /* find the first phy */
e4a474f8 914 phydev = phy_find_first(pdata->mii_bus);
fd9abb3d 915 if (!phydev) {
dffc6b24 916 netdev_err(dev, "no PHY found\n");
fd9abb3d
SG		 917 return -ENODEV;
918 }
919
dffc6b24
JP		 920 SMSC_TRACE(pdata, probe, "PHY: addr %d, phy_id 0x%08X",
921 phydev->addr, phydev->phy_id);
e4a474f8 922
923 ret = phy_connect_direct(dev, phydev,
924 &smsc911x_phy_adjust_link, 0,
925 pdata->config.phy_interface);
fd9abb3d 926
e4a474f8 927 if (ret) {
dffc6b24 928 netdev_err(dev, "Could not attach to PHY\n");
e4a474f8 929 return ret;
fd9abb3d
SG		 930 }
931
dffc6b24
JP		 932 netdev_info(dev,
933 "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
934 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
fd9abb3d
SG		 935
936 /* mask with MAC supported features */
937 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
938 SUPPORTED_Asym_Pause);
939 phydev->advertising = phydev->supported;
940
941 pdata->phy_dev = phydev;
942 pdata->last_duplex = -1;
943 pdata->last_carrier = -1;
944
945#ifdef USE_PHY_WORK_AROUND
946 if (smsc911x_phy_loopbacktest(dev) < 0) {
dffc6b24 947 SMSC_WARN(pdata, hw, "Failed Loop Back Test");
fd9abb3d
SG		 948 return -ENODEV;
949 }
dffc6b24 950 SMSC_TRACE(pdata, hw, "Passed Loop Back Test");
fd9abb3d
SG		 951#endif /* USE_PHY_WORK_AROUND */
952
dffc6b24 953 SMSC_TRACE(pdata, hw, "phy initialised successfully");
fd9abb3d
SG		 954 return 0;
955}
956
957static int __devinit smsc911x_mii_init(struct platform_device *pdev,
958 struct net_device *dev)
959{
960 struct smsc911x_data *pdata = netdev_priv(dev);
961 int err = -ENXIO, i;
962
963 pdata->mii_bus = mdiobus_alloc();
964 if (!pdata->mii_bus) {
965 err = -ENOMEM;
966 goto err_out_1;
967 }
968
969 pdata->mii_bus->name = SMSC_MDIONAME;
970 snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
971 pdata->mii_bus->priv = pdata;
972 pdata->mii_bus->read = smsc911x_mii_read;
973 pdata->mii_bus->write = smsc911x_mii_write;
974 pdata->mii_bus->irq = pdata->phy_irq;
975 for (i = 0; i < PHY_MAX_ADDR; ++i)
976 pdata->mii_bus->irq[i] = PHY_POLL;
977
978 pdata->mii_bus->parent = &pdev->dev;
fd9abb3d 979
fd9abb3d
SG		 980 switch (pdata->idrev & 0xFFFF0000) {
981 case 0x01170000:
982 case 0x01150000:
983 case 0x117A0000:
984 case 0x115A0000:
985 /* External PHY supported, try to autodetect */
d23f028a 986 smsc911x_phy_initialise_external(pdata);
fd9abb3d
SG		 987 break;
988 default:
dffc6b24
JP		 989 SMSC_TRACE(pdata, hw, "External PHY is not supported, "
990 "using internal PHY");
d23f028a 991 pdata->using_extphy = 0;
fd9abb3d
SG		 992 break;
993 }
994
995 if (!pdata->using_extphy) {
996 /* Mask all PHYs except ID 1 (internal) */
997 pdata->mii_bus->phy_mask = ~(1 << 1);
998 }
999
1000 if (mdiobus_register(pdata->mii_bus)) {
dffc6b24 1001 SMSC_WARN(pdata, probe, "Error registering mii bus");
fd9abb3d
SG		 1002 goto err_out_free_bus_2;
1003 }
1004
1005 if (smsc911x_mii_probe(dev) < 0) {
dffc6b24 1006 SMSC_WARN(pdata, probe, "Error registering mii bus");
fd9abb3d
SG		 1007 goto err_out_unregister_bus_3;
1008 }
1009
1010 return 0;
1011
1012err_out_unregister_bus_3:
1013 mdiobus_unregister(pdata->mii_bus);
1014err_out_free_bus_2:
1015 mdiobus_free(pdata->mii_bus);
1016err_out_1:
1017 return err;
1018}
1019
1020/* Gets the number of tx statuses in the fifo */
1021static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata)
1022{
1023 return (smsc911x_reg_read(pdata, TX_FIFO_INF)
1024 & TX_FIFO_INF_TSUSED_) >> 16;
1025}
1026
1027/* Reads tx statuses and increments counters where necessary */
1028static void smsc911x_tx_update_txcounters(struct net_device *dev)
1029{
1030 struct smsc911x_data *pdata = netdev_priv(dev);
1031 unsigned int tx_stat;
1032
1033 while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) {
1034 if (unlikely(tx_stat & 0x80000000)) {
1035 /* In this driver the packet tag is used as the packet
1036 * length. Since a packet length can never reach the
1037 * size of 0x8000, this bit is reserved. It is worth
1038 * noting that the "reserved bit" in the warning above
1039 * does not reference a hardware defined reserved bit
1040 * but rather a driver defined one.
1041 */
dffc6b24 1042 SMSC_WARN(pdata, hw, "Packet tag reserved bit is high");
fd9abb3d 1043 } else {
785b6f97 1044 if (unlikely(tx_stat & TX_STS_ES_)) {
fd9abb3d
SG		 1045 dev->stats.tx_errors++;
1046 } else {
1047 dev->stats.tx_packets++;
1048 dev->stats.tx_bytes += (tx_stat >> 16);
1049 }
785b6f97 1050 if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) {
fd9abb3d
SG		 1051 dev->stats.collisions += 16;
1052 dev->stats.tx_aborted_errors += 1;
1053 } else {
1054 dev->stats.collisions +=
1055 ((tx_stat >> 3) & 0xF);
1056 }
785b6f97 1057 if (unlikely(tx_stat & TX_STS_LOST_CARRIER_))
fd9abb3d 1058 dev->stats.tx_carrier_errors += 1;
785b6f97 1059 if (unlikely(tx_stat & TX_STS_LATE_COL_)) {
fd9abb3d
SG		 1060 dev->stats.collisions++;
1061 dev->stats.tx_aborted_errors++;
1062 }
1063 }
1064 }
1065}
1066
1067/* Increments the Rx error counters */
1068static void
1069smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat)
1070{
1071 int crc_err = 0;
1072
785b6f97 1073 if (unlikely(rxstat & RX_STS_ES_)) {
fd9abb3d 1074 dev->stats.rx_errors++;
785b6f97 1075 if (unlikely(rxstat & RX_STS_CRC_ERR_)) {
fd9abb3d
SG		 1076 dev->stats.rx_crc_errors++;
1077 crc_err = 1;
1078 }
1079 }
1080 if (likely(!crc_err)) {
785b6f97
SG		 1081 if (unlikely((rxstat & RX_STS_FRAME_TYPE_) &&
1082 (rxstat & RX_STS_LENGTH_ERR_)))
fd9abb3d 1083 dev->stats.rx_length_errors++;
fd9abb3d
SG		 1084 if (rxstat & RX_STS_MCAST_)
1085 dev->stats.multicast++;
1086 }
1087}
1088
1089/* Quickly dumps bad packets */
1090static void
1091smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktbytes)
1092{
1093 unsigned int pktwords = (pktbytes + NET_IP_ALIGN + 3) >> 2;
1094
1095 if (likely(pktwords >= 4)) {
1096 unsigned int timeout = 500;
1097 unsigned int val;
1098 smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_);
1099 do {
1100 udelay(1);
1101 val = smsc911x_reg_read(pdata, RX_DP_CTRL);
8dacd548 1102 } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout);
fd9abb3d
SG		 1103
1104 if (unlikely(timeout == 0))
dffc6b24
JP		 1105 SMSC_WARN(pdata, hw, "Timed out waiting for "
1106 "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val);
fd9abb3d
SG		 1107 } else {
1108 unsigned int temp;
1109 while (pktwords--)
1110 temp = smsc911x_reg_read(pdata, RX_DATA_FIFO);
1111 }
1112}
1113
1114/* NAPI poll function */
1115static int smsc911x_poll(struct napi_struct *napi, int budget)
1116{
1117 struct smsc911x_data *pdata =
1118 container_of(napi, struct smsc911x_data, napi);
1119 struct net_device *dev = pdata->dev;
1120 int npackets = 0;
1121
f88c5b98 1122 while (npackets < budget) {
fd9abb3d
SG		 1123 unsigned int pktlength;
1124 unsigned int pktwords;
1125 struct sk_buff *skb;
1126 unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata);
1127
1128 if (!rxstat) {
1129 unsigned int temp;
1130 /* We processed all packets available. Tell NAPI it can
1131 * stop polling then re-enable rx interrupts */
1132 smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_);
288379f0 1133 napi_complete(napi);
fd9abb3d
SG		 1134 temp = smsc911x_reg_read(pdata, INT_EN);
1135 temp |= INT_EN_RSFL_EN_;
1136 smsc911x_reg_write(pdata, INT_EN, temp);
1137 break;
1138 }
1139
1140 /* Count packet for NAPI scheduling, even if it has an error.
1141 * Error packets still require cycles to discard */
1142 npackets++;
1143
1144 pktlength = ((rxstat & 0x3FFF0000) >> 16);
1145 pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2;
1146 smsc911x_rx_counterrors(dev, rxstat);
1147
1148 if (unlikely(rxstat & RX_STS_ES_)) {
dffc6b24
JP		 1149 SMSC_WARN(pdata, rx_err,
1150 "Discarding packet with error bit set");
fd9abb3d
SG		 1151 /* Packet has an error, discard it and continue with
1152 * the next */
1153 smsc911x_rx_fastforward(pdata, pktwords);
1154 dev->stats.rx_dropped++;
1155 continue;
1156 }
1157
1158 skb = netdev_alloc_skb(dev, pktlength + NET_IP_ALIGN);
1159 if (unlikely(!skb)) {
dffc6b24
JP		 1160 SMSC_WARN(pdata, rx_err,
1161 "Unable to allocate skb for rx packet");
fd9abb3d
SG		 1162 /* Drop the packet and stop this polling iteration */
1163 smsc911x_rx_fastforward(pdata, pktwords);
1164 dev->stats.rx_dropped++;
1165 break;
1166 }
1167
1168 skb->data = skb->head;
1169 skb_reset_tail_pointer(skb);
1170
1171 /* Align IP on 16B boundary */
1172 skb_reserve(skb, NET_IP_ALIGN);
1173 skb_put(skb, pktlength - 4);
c326de88
MP		 1174 pdata->ops->rx_readfifo(pdata,
1175 (unsigned int *)skb->head, pktwords);
fd9abb3d 1176 skb->protocol = eth_type_trans(skb, dev);
bc8acf2c 1177 skb_checksum_none_assert(skb);
fd9abb3d
SG		 1178 netif_receive_skb(skb);
1179
1180 /* Update counters */
1181 dev->stats.rx_packets++;
1182 dev->stats.rx_bytes += (pktlength - 4);
fd9abb3d
SG		 1183 }
1184
1185 /* Return total received packets */
1186 return npackets;
1187}
1188
1189/* Returns hash bit number for given MAC address
1190 * Example:
1191 * 01 00 5E 00 00 01 -> returns bit number 31 */
1192static unsigned int smsc911x_hash(char addr[ETH_ALEN])
1193{
1194 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
1195}
1196
1197static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata)
1198{
1199 /* Performs the multicast & mac_cr update. This is called when
1200 * safe on the current hardware, and with the mac_lock held */
1201 unsigned int mac_cr;
1202
1203 SMSC_ASSERT_MAC_LOCK(pdata);
1204
1205 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
1206 mac_cr |= pdata->set_bits_mask;
1207 mac_cr &= ~(pdata->clear_bits_mask);
1208 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
1209 smsc911x_mac_write(pdata, HASHH, pdata->hashhi);
1210 smsc911x_mac_write(pdata, HASHL, pdata->hashlo);
dffc6b24
JP		 1211 SMSC_TRACE(pdata, hw, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X",
1212 mac_cr, pdata->hashhi, pdata->hashlo);
fd9abb3d
SG		 1213}
1214
1215static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata)
1216{
1217 unsigned int mac_cr;
1218
1219 /* This function is only called for older LAN911x devices
1220 * (revA or revB), where MAC_CR, HASHH and HASHL should not
1221 * be modified during Rx - newer devices immediately update the
1222 * registers.
1223 *
1224 * This is called from interrupt context */
1225
1226 spin_lock(&pdata->mac_lock);
1227
1228 /* Check Rx has stopped */
1229 if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_)
dffc6b24 1230 SMSC_WARN(pdata, drv, "Rx not stopped");
fd9abb3d
SG		 1231
1232 /* Perform the update - safe to do now Rx has stopped */
1233 smsc911x_rx_multicast_update(pdata);
1234
1235 /* Re-enable Rx */
1236 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
1237 mac_cr |= MAC_CR_RXEN_;
1238 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
1239
1240 pdata->multicast_update_pending = 0;
1241
1242 spin_unlock(&pdata->mac_lock);
1243}
1244
1245static int smsc911x_soft_reset(struct smsc911x_data *pdata)
1246{
1247 unsigned int timeout;
1248 unsigned int temp;
1249
1250 /* Reset the LAN911x */
1251 smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_);
1252 timeout = 10;
1253 do {
1254 udelay(10);
1255 temp = smsc911x_reg_read(pdata, HW_CFG);
1256 } while ((--timeout) && (temp & HW_CFG_SRST_));
1257
1258 if (unlikely(temp & HW_CFG_SRST_)) {
dffc6b24 1259 SMSC_WARN(pdata, drv, "Failed to complete reset");
fd9abb3d
SG		 1260 return -EIO;
1261 }
1262 return 0;
1263}
1264
1265/* Sets the device MAC address to dev_addr, called with mac_lock held */
1266static void
225ddf49 1267smsc911x_set_hw_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6])
fd9abb3d
SG		 1268{
1269 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
1270 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
1271 (dev_addr[1] << 8) | dev_addr[0];
1272
1273 SMSC_ASSERT_MAC_LOCK(pdata);
1274
1275 smsc911x_mac_write(pdata, ADDRH, mac_high16);
1276 smsc911x_mac_write(pdata, ADDRL, mac_low32);
1277}
1278
1279static int smsc911x_open(struct net_device *dev)
1280{
1281 struct smsc911x_data *pdata = netdev_priv(dev);
1282 unsigned int timeout;
1283 unsigned int temp;
1284 unsigned int intcfg;
1285
1286 /* if the phy is not yet registered, retry later*/
1287 if (!pdata->phy_dev) {
dffc6b24 1288 SMSC_WARN(pdata, hw, "phy_dev is NULL");
fd9abb3d
SG		 1289 return -EAGAIN;
1290 }
1291
1292 if (!is_valid_ether_addr(dev->dev_addr)) {
dffc6b24 1293 SMSC_WARN(pdata, hw, "dev_addr is not a valid MAC address");
fd9abb3d
SG		 1294 return -EADDRNOTAVAIL;
1295 }
1296
1297 /* Reset the LAN911x */
1298 if (smsc911x_soft_reset(pdata)) {
dffc6b24 1299 SMSC_WARN(pdata, hw, "soft reset failed");
fd9abb3d
SG		 1300 return -EIO;
1301 }
1302
1303 smsc911x_reg_write(pdata, HW_CFG, 0x00050000);
1304 smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740);
1305
f277e65e
GW		 1306 /* Increase the legal frame size of VLAN tagged frames to 1522 bytes */
1307 spin_lock_irq(&pdata->mac_lock);
1308 smsc911x_mac_write(pdata, VLAN1, ETH_P_8021Q);
1309 spin_unlock_irq(&pdata->mac_lock);
1310
fd9abb3d
SG		 1311 /* Make sure EEPROM has finished loading before setting GPIO_CFG */
1312 timeout = 50;
f7efb6cc
SG		 1313 while ((smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) &&
1314 --timeout) {
fd9abb3d
SG		 1315 udelay(10);
1316 }
1317
1318 if (unlikely(timeout == 0))
dffc6b24
JP		 1319 SMSC_WARN(pdata, ifup,
1320 "Timed out waiting for EEPROM busy bit to clear");
fd9abb3d
SG		 1321
1322 smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000);
1323
1324 /* The soft reset above cleared the device's MAC address,
1325 * restore it from local copy (set in probe) */
1326 spin_lock_irq(&pdata->mac_lock);
225ddf49 1327 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
fd9abb3d
SG		 1328 spin_unlock_irq(&pdata->mac_lock);
1329
1330 /* Initialise irqs, but leave all sources disabled */
1331 smsc911x_reg_write(pdata, INT_EN, 0);
1332 smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
1333
1334 /* Set interrupt deassertion to 100uS */
1335 intcfg = ((10 << 24) | INT_CFG_IRQ_EN_);
1336
2107fb8b 1337 if (pdata->config.irq_polarity) {
dffc6b24 1338 SMSC_TRACE(pdata, ifup, "irq polarity: active high");
fd9abb3d
SG		 1339 intcfg |= INT_CFG_IRQ_POL_;
1340 } else {
dffc6b24 1341 SMSC_TRACE(pdata, ifup, "irq polarity: active low");
fd9abb3d
SG		 1342 }
1343
2107fb8b 1344 if (pdata->config.irq_type) {
dffc6b24 1345 SMSC_TRACE(pdata, ifup, "irq type: push-pull");
fd9abb3d
SG		 1346 intcfg |= INT_CFG_IRQ_TYPE_;
1347 } else {
dffc6b24 1348 SMSC_TRACE(pdata, ifup, "irq type: open drain");
fd9abb3d
SG		 1349 }
1350
1351 smsc911x_reg_write(pdata, INT_CFG, intcfg);
1352
dffc6b24 1353 SMSC_TRACE(pdata, ifup, "Testing irq handler using IRQ %d", dev->irq);
fd9abb3d
SG		 1354 pdata->software_irq_signal = 0;
1355 smp_wmb();
1356
1357 temp = smsc911x_reg_read(pdata, INT_EN);
1358 temp |= INT_EN_SW_INT_EN_;
1359 smsc911x_reg_write(pdata, INT_EN, temp);
1360
1361 timeout = 1000;
1362 while (timeout--) {
1363 if (pdata->software_irq_signal)
1364 break;
1365 msleep(1);
1366 }
1367
1368 if (!pdata->software_irq_signal) {
dffc6b24
JP		 1369 netdev_warn(dev, "ISR failed signaling test (IRQ %d)\n",
1370 dev->irq);
fd9abb3d
SG		 1371 return -ENODEV;
1372 }
dffc6b24
JP		 1373 SMSC_TRACE(pdata, ifup, "IRQ handler passed test using IRQ %d",
1374 dev->irq);
fd9abb3d 1375
dffc6b24
JP		 1376 netdev_info(dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n",
1377 (unsigned long)pdata->ioaddr, dev->irq);
fd9abb3d 1378
44c1d6f9
SG		 1379 /* Reset the last known duplex and carrier */
1380 pdata->last_duplex = -1;
1381 pdata->last_carrier = -1;
1382
fd9abb3d
SG		 1383 /* Bring the PHY up */
1384 phy_start(pdata->phy_dev);
1385
1386 temp = smsc911x_reg_read(pdata, HW_CFG);
1387 /* Preserve TX FIFO size and external PHY configuration */
1388 temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF);
1389 temp |= HW_CFG_SF_;
1390 smsc911x_reg_write(pdata, HW_CFG, temp);
1391
1392 temp = smsc911x_reg_read(pdata, FIFO_INT);
1393 temp |= FIFO_INT_TX_AVAIL_LEVEL_;
1394 temp &= ~(FIFO_INT_RX_STS_LEVEL_);
1395 smsc911x_reg_write(pdata, FIFO_INT, temp);
1396
1397 /* set RX Data offset to 2 bytes for alignment */
1398 smsc911x_reg_write(pdata, RX_CFG, (2 << 8));
1399
1400 /* enable NAPI polling before enabling RX interrupts */
1401 napi_enable(&pdata->napi);
1402
1403 temp = smsc911x_reg_read(pdata, INT_EN);
1373c0fd 1404 temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_RXSTOP_INT_EN_);
fd9abb3d
SG		 1405 smsc911x_reg_write(pdata, INT_EN, temp);
1406
1407 spin_lock_irq(&pdata->mac_lock);
1408 temp = smsc911x_mac_read(pdata, MAC_CR);
1409 temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
1410 smsc911x_mac_write(pdata, MAC_CR, temp);
1411 spin_unlock_irq(&pdata->mac_lock);
1412
1413 smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
1414
1415 netif_start_queue(dev);
1416 return 0;
1417}
1418
1419/* Entry point for stopping the interface */
1420static int smsc911x_stop(struct net_device *dev)
1421{
1422 struct smsc911x_data *pdata = netdev_priv(dev);
1423 unsigned int temp;
1424
fd9abb3d
SG		 1425 /* Disable all device interrupts */
1426 temp = smsc911x_reg_read(pdata, INT_CFG);
1427 temp &= ~INT_CFG_IRQ_EN_;
1428 smsc911x_reg_write(pdata, INT_CFG, temp);
1429
1430 /* Stop Tx and Rx polling */
1431 netif_stop_queue(dev);
1432 napi_disable(&pdata->napi);
1433
1434 /* At this point all Rx and Tx activity is stopped */
1435 dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
1436 smsc911x_tx_update_txcounters(dev);
1437
1438 /* Bring the PHY down */
dd045193
SG		 1439 if (pdata->phy_dev)
1440 phy_stop(pdata->phy_dev);
fd9abb3d 1441
dffc6b24 1442 SMSC_TRACE(pdata, ifdown, "Interface stopped");
fd9abb3d
SG		 1443 return 0;
1444}
1445
1446/* Entry point for transmitting a packet */
1447static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
1448{
1449 struct smsc911x_data *pdata = netdev_priv(dev);
1450 unsigned int freespace;
1451 unsigned int tx_cmd_a;
1452 unsigned int tx_cmd_b;
1453 unsigned int temp;
1454 u32 wrsz;
1455 ulong bufp;
1456
1457 freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_;
1458
1459 if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD))
dffc6b24
JP		 1460 SMSC_WARN(pdata, tx_err,
1461 "Tx data fifo low, space available: %d", freespace);
fd9abb3d
SG		 1462
1463 /* Word alignment adjustment */
1464 tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16;
1465 tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
1466 tx_cmd_a |= (unsigned int)skb->len;
1467
1468 tx_cmd_b = ((unsigned int)skb->len) << 16;
1469 tx_cmd_b |= (unsigned int)skb->len;
1470
1471 smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a);
1472 smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b);
1473
1474 bufp = (ulong)skb->data & (~0x3);
1475 wrsz = (u32)skb->len + 3;
1476 wrsz += (u32)((ulong)skb->data & 0x3);
1477 wrsz >>= 2;
1478
c326de88 1479 pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
fd9abb3d 1480 freespace -= (skb->len + 32);
8c0069ae 1481 skb_tx_timestamp(skb);
fd9abb3d 1482 dev_kfree_skb(skb);
fd9abb3d
SG		 1483
1484 if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30))
1485 smsc911x_tx_update_txcounters(dev);
1486
1487 if (freespace < TX_FIFO_LOW_THRESHOLD) {
1488 netif_stop_queue(dev);
1489 temp = smsc911x_reg_read(pdata, FIFO_INT);
1490 temp &= 0x00FFFFFF;
1491 temp |= 0x32000000;
1492 smsc911x_reg_write(pdata, FIFO_INT, temp);
1493 }
1494
1495 return NETDEV_TX_OK;
1496}
1497
1498/* Entry point for getting status counters */
1499static struct net_device_stats *smsc911x_get_stats(struct net_device *dev)
1500{
1501 struct smsc911x_data *pdata = netdev_priv(dev);
1502 smsc911x_tx_update_txcounters(dev);
1503 dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
1504 return &dev->stats;
1505}
1506
1507/* Entry point for setting addressing modes */
1508static void smsc911x_set_multicast_list(struct net_device *dev)
1509{
1510 struct smsc911x_data *pdata = netdev_priv(dev);
1511 unsigned long flags;
1512
1513 if (dev->flags & IFF_PROMISC) {
1514 /* Enabling promiscuous mode */
1515 pdata->set_bits_mask = MAC_CR_PRMS_;
1516 pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
1517 pdata->hashhi = 0;
1518 pdata->hashlo = 0;
1519 } else if (dev->flags & IFF_ALLMULTI) {
1520 /* Enabling all multicast mode */
1521 pdata->set_bits_mask = MAC_CR_MCPAS_;
1522 pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_);
1523 pdata->hashhi = 0;
1524 pdata->hashlo = 0;
4cd24eaf 1525 } else if (!netdev_mc_empty(dev)) {
fd9abb3d
SG		 1526 /* Enabling specific multicast addresses */
1527 unsigned int hash_high = 0;
1528 unsigned int hash_low = 0;
22bedad3 1529 struct netdev_hw_addr *ha;
fd9abb3d
SG		 1530
1531 pdata->set_bits_mask = MAC_CR_HPFILT_;
1532 pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_);
1533
22bedad3
JP		 1534 netdev_for_each_mc_addr(ha, dev) {
1535 unsigned int bitnum = smsc911x_hash(ha->addr);
2a0d18f9
JP		 1536 unsigned int mask = 0x01 << (bitnum & 0x1F);
1537
1538 if (bitnum & 0x20)
1539 hash_high |= mask;
1540 else
1541 hash_low |= mask;
fd9abb3d 1542 }
fd9abb3d
SG		 1543
1544 pdata->hashhi = hash_high;
1545 pdata->hashlo = hash_low;
1546 } else {
1547 /* Enabling local MAC address only */
1548 pdata->set_bits_mask = 0;
1549 pdata->clear_bits_mask =
1550 (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
1551 pdata->hashhi = 0;
1552 pdata->hashlo = 0;
1553 }
1554
1555 spin_lock_irqsave(&pdata->mac_lock, flags);
1556
1557 if (pdata->generation <= 1) {
1558 /* Older hardware revision - cannot change these flags while
1559 * receiving data */
1560 if (!pdata->multicast_update_pending) {
1561 unsigned int temp;
dffc6b24 1562 SMSC_TRACE(pdata, hw, "scheduling mcast update");
fd9abb3d
SG		 1563 pdata->multicast_update_pending = 1;
1564
1565 /* Request the hardware to stop, then perform the
1566 * update when we get an RX_STOP interrupt */
fd9abb3d
SG		 1567 temp = smsc911x_mac_read(pdata, MAC_CR);
1568 temp &= ~(MAC_CR_RXEN_);
1569 smsc911x_mac_write(pdata, MAC_CR, temp);
1570 } else {
1571 /* There is another update pending, this should now
1572 * use the newer values */
1573 }
1574 } else {
1575 /* Newer hardware revision - can write immediately */
1576 smsc911x_rx_multicast_update(pdata);
1577 }
1578
1579 spin_unlock_irqrestore(&pdata->mac_lock, flags);
1580}
1581
1582static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id)
1583{
1584 struct net_device *dev = dev_id;
1585 struct smsc911x_data *pdata = netdev_priv(dev);
1586 u32 intsts = smsc911x_reg_read(pdata, INT_STS);
1587 u32 inten = smsc911x_reg_read(pdata, INT_EN);
1588 int serviced = IRQ_NONE;
1589 u32 temp;
1590
1591 if (unlikely(intsts & inten & INT_STS_SW_INT_)) {
1592 temp = smsc911x_reg_read(pdata, INT_EN);
1593 temp &= (~INT_EN_SW_INT_EN_);
1594 smsc911x_reg_write(pdata, INT_EN, temp);
1595 smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_);
1596 pdata->software_irq_signal = 1;
1597 smp_wmb();
1598 serviced = IRQ_HANDLED;
1599 }
1600
1601 if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) {
1602 /* Called when there is a multicast update scheduled and
1603 * it is now safe to complete the update */
dffc6b24 1604 SMSC_TRACE(pdata, intr, "RX Stop interrupt");
fd9abb3d 1605 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_);
1373c0fd
SG		 1606 if (pdata->multicast_update_pending)
1607 smsc911x_rx_multicast_update_workaround(pdata);
fd9abb3d
SG		 1608 serviced = IRQ_HANDLED;
1609 }
1610
1611 if (intsts & inten & INT_STS_TDFA_) {
1612 temp = smsc911x_reg_read(pdata, FIFO_INT);
1613 temp |= FIFO_INT_TX_AVAIL_LEVEL_;
1614 smsc911x_reg_write(pdata, FIFO_INT, temp);
1615 smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_);
1616 netif_wake_queue(dev);
1617 serviced = IRQ_HANDLED;
1618 }
1619
1620 if (unlikely(intsts & inten & INT_STS_RXE_)) {
dffc6b24 1621 SMSC_TRACE(pdata, intr, "RX Error interrupt");
fd9abb3d
SG		 1622 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_);
1623 serviced = IRQ_HANDLED;
1624 }
1625
1626 if (likely(intsts & inten & INT_STS_RSFL_)) {
288379f0 1627 if (likely(napi_schedule_prep(&pdata->napi))) {
fd9abb3d
SG		 1628 /* Disable Rx interrupts */
1629 temp = smsc911x_reg_read(pdata, INT_EN);
1630 temp &= (~INT_EN_RSFL_EN_);
1631 smsc911x_reg_write(pdata, INT_EN, temp);
1632 /* Schedule a NAPI poll */
288379f0 1633 __napi_schedule(&pdata->napi);
fd9abb3d 1634 } else {
dffc6b24 1635 SMSC_WARN(pdata, rx_err, "napi_schedule_prep failed");
fd9abb3d
SG		 1636 }
1637 serviced = IRQ_HANDLED;
1638 }
1639
1640 return serviced;
1641}
1642
1643#ifdef CONFIG_NET_POLL_CONTROLLER
1757ab2f 1644static void smsc911x_poll_controller(struct net_device *dev)
fd9abb3d
SG		 1645{
1646 disable_irq(dev->irq);
1647 smsc911x_irqhandler(0, dev);
1648 enable_irq(dev->irq);
1649}
1650#endif /* CONFIG_NET_POLL_CONTROLLER */
1651
225ddf49
SG		 1652static int smsc911x_set_mac_address(struct net_device *dev, void *p)
1653{
1654 struct smsc911x_data *pdata = netdev_priv(dev);
1655 struct sockaddr *addr = p;
1656
1657 /* On older hardware revisions we cannot change the mac address
1658 * registers while receiving data. Newer devices can safely change
1659 * this at any time. */
1660 if (pdata->generation <= 1 && netif_running(dev))
1661 return -EBUSY;
1662
1663 if (!is_valid_ether_addr(addr->sa_data))
1664 return -EADDRNOTAVAIL;
1665
1666 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
1667
1668 spin_lock_irq(&pdata->mac_lock);
1669 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
1670 spin_unlock_irq(&pdata->mac_lock);
1671
dffc6b24 1672 netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr);
225ddf49
SG		 1673
1674 return 0;
1675}
1676
fd9abb3d
SG		 1677/* Standard ioctls for mii-tool */
1678static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1679{
1680 struct smsc911x_data *pdata = netdev_priv(dev);
1681
1682 if (!netif_running(dev) || !pdata->phy_dev)
1683 return -EINVAL;
1684
28b04113 1685 return phy_mii_ioctl(pdata->phy_dev, ifr, cmd);
fd9abb3d
SG		 1686}
1687
1688static int
1689smsc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1690{
1691 struct smsc911x_data *pdata = netdev_priv(dev);
1692
1693 cmd->maxtxpkt = 1;
1694 cmd->maxrxpkt = 1;
1695 return phy_ethtool_gset(pdata->phy_dev, cmd);
1696}
1697
1698static int
1699smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1700{
1701 struct smsc911x_data *pdata = netdev_priv(dev);
1702
1703 return phy_ethtool_sset(pdata->phy_dev, cmd);
1704}
1705
1706static void smsc911x_ethtool_getdrvinfo(struct net_device *dev,
1707 struct ethtool_drvinfo *info)
1708{
1709 strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver));
1710 strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version));
db1d7bf7 1711 strlcpy(info->bus_info, dev_name(dev->dev.parent),
fd9abb3d
SG		 1712 sizeof(info->bus_info));
1713}
1714
1715static int smsc911x_ethtool_nwayreset(struct net_device *dev)
1716{
1717 struct smsc911x_data *pdata = netdev_priv(dev);
1718
1719 return phy_start_aneg(pdata->phy_dev);
1720}
1721
1722static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev)
1723{
1724 struct smsc911x_data *pdata = netdev_priv(dev);
1725 return pdata->msg_enable;
1726}
1727
1728static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
1729{
1730 struct smsc911x_data *pdata = netdev_priv(dev);
1731 pdata->msg_enable = level;
1732}
1733
1734static int smsc911x_ethtool_getregslen(struct net_device *dev)
1735{
1736 return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) *
1737 sizeof(u32);
1738}
1739
1740static void
1741smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
1742 void *buf)
1743{
1744 struct smsc911x_data *pdata = netdev_priv(dev);
1745 struct phy_device *phy_dev = pdata->phy_dev;
1746 unsigned long flags;
1747 unsigned int i;
1748 unsigned int j = 0;
1749 u32 *data = buf;
1750
1751 regs->version = pdata->idrev;
1752 for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32)))
1753 data[j++] = smsc911x_reg_read(pdata, i);
1754
1755 for (i = MAC_CR; i <= WUCSR; i++) {
1756 spin_lock_irqsave(&pdata->mac_lock, flags);
1757 data[j++] = smsc911x_mac_read(pdata, i);
1758 spin_unlock_irqrestore(&pdata->mac_lock, flags);
1759 }
1760
1761 for (i = 0; i <= 31; i++)
1762 data[j++] = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, i);
1763}
1764
1765static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata)
1766{
1767 unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG);
1768 temp &= ~GPIO_CFG_EEPR_EN_;
1769 smsc911x_reg_write(pdata, GPIO_CFG, temp);
1770 msleep(1);
1771}
1772
1773static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op)
1774{
1775 int timeout = 100;
1776 u32 e2cmd;
1777
dffc6b24 1778 SMSC_TRACE(pdata, drv, "op 0x%08x", op);
fd9abb3d 1779 if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
dffc6b24 1780 SMSC_WARN(pdata, drv, "Busy at start");
fd9abb3d
SG		 1781 return -EBUSY;
1782 }
1783
1784 e2cmd = op | E2P_CMD_EPC_BUSY_;
1785 smsc911x_reg_write(pdata, E2P_CMD, e2cmd);
1786
1787 do {
1788 msleep(1);
1789 e2cmd = smsc911x_reg_read(pdata, E2P_CMD);
2cf0dbed 1790 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
fd9abb3d
SG		 1791
1792 if (!timeout) {
dffc6b24 1793 SMSC_TRACE(pdata, drv, "TIMED OUT");
fd9abb3d
SG		 1794 return -EAGAIN;
1795 }
1796
1797 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
1c01a80c 1798 SMSC_TRACE(pdata, drv, "Error occurred during eeprom operation");
fd9abb3d
SG		 1799 return -EINVAL;
1800 }
1801
1802 return 0;
1803}
1804
1805static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata,
1806 u8 address, u8 *data)
1807{
1808 u32 op = E2P_CMD_EPC_CMD_READ_ | address;
1809 int ret;
1810
dffc6b24 1811 SMSC_TRACE(pdata, drv, "address 0x%x", address);
fd9abb3d
SG		 1812 ret = smsc911x_eeprom_send_cmd(pdata, op);
1813
1814 if (!ret)
1815 data[address] = smsc911x_reg_read(pdata, E2P_DATA);
1816
1817 return ret;
1818}
1819
1820static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
1821 u8 address, u8 data)
1822{
1823 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
58add9fc 1824 u32 temp;
fd9abb3d
SG		 1825 int ret;
1826
dffc6b24 1827 SMSC_TRACE(pdata, drv, "address 0x%x, data 0x%x", address, data);
fd9abb3d
SG		 1828 ret = smsc911x_eeprom_send_cmd(pdata, op);
1829
1830 if (!ret) {
1831 op = E2P_CMD_EPC_CMD_WRITE_ | address;
1832 smsc911x_reg_write(pdata, E2P_DATA, (u32)data);
58add9fc
SG		 1833
1834 /* Workaround for hardware read-after-write restriction */
1835 temp = smsc911x_reg_read(pdata, BYTE_TEST);
1836
fd9abb3d
SG		 1837 ret = smsc911x_eeprom_send_cmd(pdata, op);
1838 }
1839
1840 return ret;
1841}
1842
1843static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev)
1844{
1845 return SMSC911X_EEPROM_SIZE;
1846}
1847
1848static int smsc911x_ethtool_get_eeprom(struct net_device *dev,
1849 struct ethtool_eeprom *eeprom, u8 *data)
1850{
1851 struct smsc911x_data *pdata = netdev_priv(dev);
1852 u8 eeprom_data[SMSC911X_EEPROM_SIZE];
1853 int len;
1854 int i;
1855
1856 smsc911x_eeprom_enable_access(pdata);
1857
1858 len = min(eeprom->len, SMSC911X_EEPROM_SIZE);
1859 for (i = 0; i < len; i++) {
1860 int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data);
1861 if (ret < 0) {
1862 eeprom->len = 0;
1863 return ret;
1864 }
1865 }
1866
1867 memcpy(data, &eeprom_data[eeprom->offset], len);
1868 eeprom->len = len;
1869 return 0;
1870}
1871
1872static int smsc911x_ethtool_set_eeprom(struct net_device *dev,
1873 struct ethtool_eeprom *eeprom, u8 *data)
1874{
1875 int ret;
1876 struct smsc911x_data *pdata = netdev_priv(dev);
1877
1878 smsc911x_eeprom_enable_access(pdata);
1879 smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_);
1880 ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data);
1881 smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_);
1882
1883 /* Single byte write, according to man page */
1884 eeprom->len = 1;
1885
1886 return ret;
1887}
1888
cb5b04fe 1889static const struct ethtool_ops smsc911x_ethtool_ops = {
fd9abb3d
SG		 1890 .get_settings = smsc911x_ethtool_getsettings,
1891 .set_settings = smsc911x_ethtool_setsettings,
1892 .get_link = ethtool_op_get_link,
1893 .get_drvinfo = smsc911x_ethtool_getdrvinfo,
1894 .nway_reset = smsc911x_ethtool_nwayreset,
1895 .get_msglevel = smsc911x_ethtool_getmsglevel,
1896 .set_msglevel = smsc911x_ethtool_setmsglevel,
1897 .get_regs_len = smsc911x_ethtool_getregslen,
1898 .get_regs = smsc911x_ethtool_getregs,
1899 .get_eeprom_len = smsc911x_ethtool_get_eeprom_len,
1900 .get_eeprom = smsc911x_ethtool_get_eeprom,
1901 .set_eeprom = smsc911x_ethtool_set_eeprom,
1902};
1903
631b7568
SG		 1904static const struct net_device_ops smsc911x_netdev_ops = {
1905 .ndo_open = smsc911x_open,
1906 .ndo_stop = smsc911x_stop,
1907 .ndo_start_xmit = smsc911x_hard_start_xmit,
1908 .ndo_get_stats = smsc911x_get_stats,
1909 .ndo_set_multicast_list = smsc911x_set_multicast_list,
1910 .ndo_do_ioctl = smsc911x_do_ioctl,
635ecaa7 1911 .ndo_change_mtu = eth_change_mtu,
631b7568 1912 .ndo_validate_addr = eth_validate_addr,
225ddf49 1913 .ndo_set_mac_address = smsc911x_set_mac_address,
631b7568
SG		 1914#ifdef CONFIG_NET_POLL_CONTROLLER
1915 .ndo_poll_controller = smsc911x_poll_controller,
1916#endif
1917};
1918
31f45747
SG		 1919/* copies the current mac address from hardware to dev->dev_addr */
1920static void __devinit smsc911x_read_mac_address(struct net_device *dev)
1921{
1922 struct smsc911x_data *pdata = netdev_priv(dev);
1923 u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH);
1924 u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL);
1925
1926 dev->dev_addr[0] = (u8)(mac_low32);
1927 dev->dev_addr[1] = (u8)(mac_low32 >> 8);
1928 dev->dev_addr[2] = (u8)(mac_low32 >> 16);
1929 dev->dev_addr[3] = (u8)(mac_low32 >> 24);
1930 dev->dev_addr[4] = (u8)(mac_high16);
1931 dev->dev_addr[5] = (u8)(mac_high16 >> 8);
1932}
1933
fd9abb3d
SG		 1934/* Initializing private device structures, only called from probe */
1935static int __devinit smsc911x_init(struct net_device *dev)
1936{
1937 struct smsc911x_data *pdata = netdev_priv(dev);
1938 unsigned int byte_test;
1939
dffc6b24
JP		 1940 SMSC_TRACE(pdata, probe, "Driver Parameters:");
1941 SMSC_TRACE(pdata, probe, "LAN base: 0x%08lX",
1942 (unsigned long)pdata->ioaddr);
1943 SMSC_TRACE(pdata, probe, "IRQ: %d", dev->irq);
1944 SMSC_TRACE(pdata, probe, "PHY will be autodetected.");
fd9abb3d 1945
fd9abb3d 1946 spin_lock_init(&pdata->dev_lock);
35a67edf 1947 spin_lock_init(&pdata->mac_lock);
fd9abb3d
SG		 1948
1949 if (pdata->ioaddr == 0) {
dffc6b24 1950 SMSC_WARN(pdata, probe, "pdata->ioaddr: 0x00000000");
fd9abb3d
SG		 1951 return -ENODEV;
1952 }
1953
1954 /* Check byte ordering */
1955 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
dffc6b24 1956 SMSC_TRACE(pdata, probe, "BYTE_TEST: 0x%08X", byte_test);
fd9abb3d 1957 if (byte_test == 0x43218765) {
dffc6b24
JP		 1958 SMSC_TRACE(pdata, probe, "BYTE_TEST looks swapped, "
1959 "applying WORD_SWAP");
fd9abb3d
SG		 1960 smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff);
1961
1962 /* 1 dummy read of BYTE_TEST is needed after a write to
1963 * WORD_SWAP before its contents are valid */
1964 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1965
1966 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1967 }
1968
1969 if (byte_test != 0x87654321) {
dffc6b24 1970 SMSC_WARN(pdata, drv, "BYTE_TEST: 0x%08X", byte_test);
fd9abb3d 1971 if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) {
dffc6b24
JP		 1972 SMSC_WARN(pdata, probe,
1973 "top 16 bits equal to bottom 16 bits");
1974 SMSC_TRACE(pdata, probe,
1975 "This may mean the chip is set "
1976 "for 32 bit while the bus is reading 16 bit");
fd9abb3d
SG		 1977 }
1978 return -ENODEV;
1979 }
1980
1981 /* Default generation to zero (all workarounds apply) */
1982 pdata->generation = 0;
1983
1984 pdata->idrev = smsc911x_reg_read(pdata, ID_REV);
1985 switch (pdata->idrev & 0xFFFF0000) {
1986 case 0x01180000:
1987 case 0x01170000:
1988 case 0x01160000:
1989 case 0x01150000:
1990 /* LAN911[5678] family */
1991 pdata->generation = pdata->idrev & 0x0000FFFF;
1992 break;
1993
1994 case 0x118A0000:
1995 case 0x117A0000:
1996 case 0x116A0000:
1997 case 0x115A0000:
1998 /* LAN921[5678] family */
1999 pdata->generation = 3;
2000 break;
2001
2002 case 0x92100000:
2003 case 0x92110000:
2004 case 0x92200000:
2005 case 0x92210000:
2006 /* LAN9210/LAN9211/LAN9220/LAN9221 */
2007 pdata->generation = 4;
2008 break;
2009
2010 default:
dffc6b24
JP		 2011 SMSC_WARN(pdata, probe, "LAN911x not identified, idrev: 0x%08X",
2012 pdata->idrev);
fd9abb3d
SG		 2013 return -ENODEV;
2014 }
2015
dffc6b24
JP		 2016 SMSC_TRACE(pdata, probe,
2017 "LAN911x identified, idrev: 0x%08X, generation: %d",
2018 pdata->idrev, pdata->generation);
fd9abb3d
SG		 2019
2020 if (pdata->generation == 0)
dffc6b24
JP		 2021 SMSC_WARN(pdata, probe,
2022 "This driver is not intended for this chip revision");
fd9abb3d 2023
31f45747
SG		 2024 /* workaround for platforms without an eeprom, where the mac address
2025 * is stored elsewhere and set by the bootloader. This saves the
2026 * mac address before resetting the device */
35a67edf
EBS		 2027 if (pdata->config.flags & SMSC911X_SAVE_MAC_ADDRESS) {
2028 spin_lock_irq(&pdata->mac_lock);
31f45747 2029 smsc911x_read_mac_address(dev);
35a67edf
EBS		 2030 spin_unlock_irq(&pdata->mac_lock);
2031 }
31f45747 2032
fd9abb3d
SG		 2033 /* Reset the LAN911x */
2034 if (smsc911x_soft_reset(pdata))
2035 return -ENODEV;
2036
2037 /* Disable all interrupt sources until we bring the device up */
2038 smsc911x_reg_write(pdata, INT_EN, 0);
2039
2040 ether_setup(dev);
fd9abb3d 2041 dev->flags |= IFF_MULTICAST;
fd9abb3d 2042 netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT);
631b7568 2043 dev->netdev_ops = &smsc911x_netdev_ops;
fd9abb3d
SG		 2044 dev->ethtool_ops = &smsc911x_ethtool_ops;
2045
fd9abb3d
SG		 2046 return 0;
2047}
2048
2049static int __devexit smsc911x_drv_remove(struct platform_device *pdev)
2050{
2051 struct net_device *dev;
2052 struct smsc911x_data *pdata;
2053 struct resource *res;
2054
2055 dev = platform_get_drvdata(pdev);
2056 BUG_ON(!dev);
2057 pdata = netdev_priv(dev);
2058 BUG_ON(!pdata);
2059 BUG_ON(!pdata->ioaddr);
2060 BUG_ON(!pdata->phy_dev);
2061
dffc6b24 2062 SMSC_TRACE(pdata, ifdown, "Stopping driver");
fd9abb3d
SG		 2063
2064 phy_disconnect(pdata->phy_dev);
2065 pdata->phy_dev = NULL;
2066 mdiobus_unregister(pdata->mii_bus);
2067 mdiobus_free(pdata->mii_bus);
2068
2069 platform_set_drvdata(pdev, NULL);
2070 unregister_netdev(dev);
2071 free_irq(dev->irq, dev);
2072 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2073 "smsc911x-memory");
2074 if (!res)
d4522739 2075 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
fd9abb3d 2076
39424539 2077 release_mem_region(res->start, resource_size(res));
fd9abb3d
SG		 2078
2079 iounmap(pdata->ioaddr);
2080
2081 free_netdev(dev);
2082
2083 return 0;
2084}
2085
c326de88
MP		 2086/* standard register acces */
2087static const struct smsc911x_ops standard_smsc911x_ops = {
2088 .reg_read = __smsc911x_reg_read,
2089 .reg_write = __smsc911x_reg_write,
2090 .rx_readfifo = smsc911x_rx_readfifo,
2091 .tx_writefifo = smsc911x_tx_writefifo,
2092};
2093
2094/* shifted register access */
2095static const struct smsc911x_ops shifted_smsc911x_ops = {
2096 .reg_read = __smsc911x_reg_read_shift,
2097 .reg_write = __smsc911x_reg_write_shift,
2098 .rx_readfifo = smsc911x_rx_readfifo_shift,
2099 .tx_writefifo = smsc911x_tx_writefifo_shift,
2100};
2101
79f88ee9
SG		 2102#ifdef CONFIG_OF
2103static int __devinit smsc911x_probe_config_dt(
2104 struct smsc911x_platform_config *config,
2105 struct device_node *np)
2106{
2107 const char *mac;
2108 u32 width = 0;
2109
2110 if (!np)
2111 return -ENODEV;
2112
2113 config->phy_interface = of_get_phy_mode(np);
2114
2115 mac = of_get_mac_address(np);
2116 if (mac)
2117 memcpy(config->mac, mac, ETH_ALEN);
2118
2119 of_property_read_u32(np, "reg-shift", &config->shift);
2120
2121 of_property_read_u32(np, "reg-io-width", &width);
2122 if (width == 4)
2123 config->flags |= SMSC911X_USE_32BIT;
2124
2125 if (of_get_property(np, "smsc,irq-active-high", NULL))
2126 config->irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH;
2127
2128 if (of_get_property(np, "smsc,irq-push-pull", NULL))
2129 config->irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL;
2130
2131 if (of_get_property(np, "smsc,force-internal-phy", NULL))
2132 config->flags |= SMSC911X_FORCE_INTERNAL_PHY;
2133
2134 if (of_get_property(np, "smsc,force-external-phy", NULL))
2135 config->flags |= SMSC911X_FORCE_EXTERNAL_PHY;
2136
2137 if (of_get_property(np, "smsc,save-mac-address", NULL))
2138 config->flags |= SMSC911X_SAVE_MAC_ADDRESS;
2139
2140 return 0;
2141}
2142#else
2143static inline int smsc911x_probe_config_dt(
2144 struct smsc911x_platform_config *config,
2145 struct device_node *np)
2146{
2147 return -ENODEV;
2148}
2149#endif /* CONFIG_OF */
2150
fd9abb3d
SG		 2151static int __devinit smsc911x_drv_probe(struct platform_device *pdev)
2152{
79f88ee9 2153 struct device_node *np = pdev->dev.of_node;
fd9abb3d
SG		 2154 struct net_device *dev;
2155 struct smsc911x_data *pdata;
2107fb8b 2156 struct smsc911x_platform_config *config = pdev->dev.platform_data;
61307ed8 2157 struct resource *res, *irq_res;
fd9abb3d 2158 unsigned int intcfg = 0;
61307ed8 2159 int res_size, irq_flags;
fd9abb3d 2160 int retval;
fd9abb3d 2161
dffc6b24 2162 pr_info("Driver version %s\n", SMSC_DRV_VERSION);
fd9abb3d
SG		 2163
2164 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2165 "smsc911x-memory");
2166 if (!res)
2167 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2168 if (!res) {
dffc6b24 2169 pr_warn("Could not allocate resource\n");
fd9abb3d
SG		 2170 retval = -ENODEV;
2171 goto out_0;
2172 }
39424539 2173 res_size = resource_size(res);
fd9abb3d 2174
61307ed8
SG		 2175 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2176 if (!irq_res) {
dffc6b24 2177 pr_warn("Could not allocate irq resource\n");
61307ed8
SG		 2178 retval = -ENODEV;
2179 goto out_0;
2180 }
2181
fd9abb3d
SG		 2182 if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) {
2183 retval = -EBUSY;
2184 goto out_0;
2185 }
2186
2187 dev = alloc_etherdev(sizeof(struct smsc911x_data));
2188 if (!dev) {
dffc6b24 2189 pr_warn("Could not allocate device\n");
fd9abb3d
SG		 2190 retval = -ENOMEM;
2191 goto out_release_io_1;
2192 }
2193
2194 SET_NETDEV_DEV(dev, &pdev->dev);
2195
2196 pdata = netdev_priv(dev);
2197
61307ed8
SG		 2198 dev->irq = irq_res->start;
2199 irq_flags = irq_res->flags & IRQF_TRIGGER_MASK;
fd9abb3d
SG		 2200 pdata->ioaddr = ioremap_nocache(res->start, res_size);
2201
fd9abb3d
SG		 2202 pdata->dev = dev;
2203 pdata->msg_enable = ((1 << debug) - 1);
2204
2205 if (pdata->ioaddr == NULL) {
dffc6b24 2206 SMSC_WARN(pdata, probe, "Error smsc911x base address invalid");
fd9abb3d
SG		 2207 retval = -ENOMEM;
2208 goto out_free_netdev_2;
2209 }
2210
79f88ee9
SG		 2211 retval = smsc911x_probe_config_dt(&pdata->config, np);
2212 if (retval && config) {
2213 /* copy config parameters across to pdata */
2214 memcpy(&pdata->config, config, sizeof(pdata->config));
2215 retval = 0;
2216 }
2217
2218 if (retval) {
2219 SMSC_WARN(pdata, probe, "Error smsc911x config not found");
2220 goto out_unmap_io_3;
2221 }
2222
c326de88
MP		 2223 /* assume standard, non-shifted, access to HW registers */
2224 pdata->ops = &standard_smsc911x_ops;
2225 /* apply the right access if shifting is needed */
79f88ee9 2226 if (pdata->config.shift)
c326de88
MP		 2227 pdata->ops = &shifted_smsc911x_ops;
2228
fd9abb3d
SG		 2229 retval = smsc911x_init(dev);
2230 if (retval < 0)
2231 goto out_unmap_io_3;
2232
2233 /* configure irq polarity and type before connecting isr */
2107fb8b 2234 if (pdata->config.irq_polarity == SMSC911X_IRQ_POLARITY_ACTIVE_HIGH)
fd9abb3d
SG		 2235 intcfg |= INT_CFG_IRQ_POL_;
2236
2107fb8b 2237 if (pdata->config.irq_type == SMSC911X_IRQ_TYPE_PUSH_PULL)
fd9abb3d
SG		 2238 intcfg |= INT_CFG_IRQ_TYPE_;
2239
2240 smsc911x_reg_write(pdata, INT_CFG, intcfg);
2241
2242 /* Ensure interrupts are globally disabled before connecting ISR */
2243 smsc911x_reg_write(pdata, INT_EN, 0);
2244 smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
2245
61307ed8 2246 retval = request_irq(dev->irq, smsc911x_irqhandler,
e81259b4 2247 irq_flags | IRQF_SHARED, dev->name, dev);
fd9abb3d 2248 if (retval) {
dffc6b24
JP		 2249 SMSC_WARN(pdata, probe,
2250 "Unable to claim requested irq: %d", dev->irq);
fd9abb3d
SG		 2251 goto out_unmap_io_3;
2252 }
2253
2254 platform_set_drvdata(pdev, dev);
2255
2256 retval = register_netdev(dev);
2257 if (retval) {
dffc6b24 2258 SMSC_WARN(pdata, probe, "Error %i registering device", retval);
fd9abb3d
SG		 2259 goto out_unset_drvdata_4;
2260 } else {
dffc6b24
JP		 2261 SMSC_TRACE(pdata, probe,
2262 "Network interface: \"%s\"", dev->name);
fd9abb3d
SG		 2263 }
2264
fd9abb3d
SG		 2265 retval = smsc911x_mii_init(pdev, dev);
2266 if (retval) {
dffc6b24 2267 SMSC_WARN(pdata, probe, "Error %i initialising mii", retval);
fd9abb3d
SG		 2268 goto out_unregister_netdev_5;
2269 }
2270
2271 spin_lock_irq(&pdata->mac_lock);
2272
2273 /* Check if mac address has been specified when bringing interface up */
2274 if (is_valid_ether_addr(dev->dev_addr)) {
225ddf49 2275 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
dffc6b24
JP		 2276 SMSC_TRACE(pdata, probe,
2277 "MAC Address is specified by configuration");
aace4959
ML		 2278 } else if (is_valid_ether_addr(pdata->config.mac)) {
2279 memcpy(dev->dev_addr, pdata->config.mac, 6);
dffc6b24
JP		 2280 SMSC_TRACE(pdata, probe,
2281 "MAC Address specified by platform data");
fd9abb3d
SG		 2282 } else {
2283 /* Try reading mac address from device. if EEPROM is present
2284 * it will already have been set */
62747cd2 2285 smsc_get_mac(dev);
fd9abb3d
SG		 2286
2287 if (is_valid_ether_addr(dev->dev_addr)) {
2288 /* eeprom values are valid so use them */
dffc6b24
JP		 2289 SMSC_TRACE(pdata, probe,
2290 "Mac Address is read from LAN911x EEPROM");
fd9abb3d
SG		 2291 } else {
2292 /* eeprom values are invalid, generate random MAC */
2293 random_ether_addr(dev->dev_addr);
225ddf49 2294 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
dffc6b24
JP		 2295 SMSC_TRACE(pdata, probe,
2296 "MAC Address is set to random_ether_addr");
fd9abb3d
SG		 2297 }
2298 }
2299
2300 spin_unlock_irq(&pdata->mac_lock);
2301
dffc6b24 2302 netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr);
fd9abb3d
SG		 2303
2304 return 0;
2305
2306out_unregister_netdev_5:
2307 unregister_netdev(dev);
2308out_unset_drvdata_4:
2309 platform_set_drvdata(pdev, NULL);
2310 free_irq(dev->irq, dev);
2311out_unmap_io_3:
2312 iounmap(pdata->ioaddr);
2313out_free_netdev_2:
2314 free_netdev(dev);
2315out_release_io_1:
39424539 2316 release_mem_region(res->start, resource_size(res));
fd9abb3d
SG		 2317out_0:
2318 return retval;
2319}
2320
b6907b0c
DM		 2321#ifdef CONFIG_PM
2322/* This implementation assumes the devices remains powered on its VDDVARIO
2323 * pins during suspend. */
2324
6cb87823
DM		 2325/* TODO: implement freeze/thaw callbacks for hibernation.*/
2326
2327static int smsc911x_suspend(struct device *dev)
b6907b0c 2328{
6cb87823
DM		 2329 struct net_device *ndev = dev_get_drvdata(dev);
2330 struct smsc911x_data *pdata = netdev_priv(ndev);
b6907b0c
DM		 2331
2332 /* enable wake on LAN, energy detection and the external PME
2333 * signal. */
2334 smsc911x_reg_write(pdata, PMT_CTRL,
2335 PMT_CTRL_PM_MODE_D1_ | PMT_CTRL_WOL_EN_ |
2336 PMT_CTRL_ED_EN_ | PMT_CTRL_PME_EN_);
2337
2338 return 0;
2339}
2340
6cb87823 2341static int smsc911x_resume(struct device *dev)
b6907b0c 2342{
6cb87823
DM		 2343 struct net_device *ndev = dev_get_drvdata(dev);
2344 struct smsc911x_data *pdata = netdev_priv(ndev);
b6907b0c
DM		 2345 unsigned int to = 100;
2346
2347 /* Note 3.11 from the datasheet:
2348 * "When the LAN9220 is in a power saving state, a write of any
2349 * data to the BYTE_TEST register will wake-up the device."
2350 */
2351 smsc911x_reg_write(pdata, BYTE_TEST, 0);
2352
2353 /* poll the READY bit in PMT_CTRL. Any other access to the device is
2354 * forbidden while this bit isn't set. Try for 100ms and return -EIO
2355 * if it failed. */
2356 while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to)
2357 udelay(1000);
2358
2359 return (to == 0) ? -EIO : 0;
2360}
2361
47145210 2362static const struct dev_pm_ops smsc911x_pm_ops = {
6cb87823
DM		 2363 .suspend = smsc911x_suspend,
2364 .resume = smsc911x_resume,
2365};
2366
2367#define SMSC911X_PM_OPS (&smsc911x_pm_ops)
2368
b6907b0c 2369#else
6cb87823 2370#define SMSC911X_PM_OPS NULL
b6907b0c
DM		 2371#endif
2372
79f88ee9
SG		 2373static const struct of_device_id smsc911x_dt_ids[] = {
2374 { .compatible = "smsc,lan9115", },
2375 { /* sentinel */ }
2376};
2377MODULE_DEVICE_TABLE(of, smsc911x_dt_ids);
2378
fd9abb3d
SG		 2379static struct platform_driver smsc911x_driver = {
2380 .probe = smsc911x_drv_probe,
df911e2d 2381 .remove = __devexit_p(smsc911x_drv_remove),
fd9abb3d 2382 .driver = {
6cb87823
DM		 2383 .name = SMSC_CHIPNAME,
2384 .owner = THIS_MODULE,
2385 .pm = SMSC911X_PM_OPS,
79f88ee9 2386 .of_match_table = smsc911x_dt_ids,
fd9abb3d
SG		 2387 },
2388};
2389
2390/* Entry point for loading the module */
2391static int __init smsc911x_init_module(void)
2392{
62747cd2 2393 SMSC_INITIALIZE();
fd9abb3d
SG		 2394 return platform_driver_register(&smsc911x_driver);
2395}
2396
2397/* entry point for unloading the module */
2398static void __exit smsc911x_cleanup_module(void)
2399{
2400 platform_driver_unregister(&smsc911x_driver);
2401}
2402
2403module_init(smsc911x_init_module);
2404module_exit(smsc911x_cleanup_module);
Linux 6.x block layer and io_uring tree(s)