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e1253f39 AM |
1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /**************************************************************************** | |
3 | * Driver for Solarflare network controllers and boards | |
4 | * Copyright 2018 Solarflare Communications Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #ifndef EFX_RX_COMMON_H | |
12 | #define EFX_RX_COMMON_H | |
13 | ||
14 | /* Preferred number of descriptors to fill at once */ | |
15 | #define EFX_RX_PREFERRED_BATCH 8U | |
16 | ||
17 | /* Each packet can consume up to ceil(max_frame_len / buffer_size) buffers */ | |
18 | #define EFX_RX_MAX_FRAGS DIV_ROUND_UP(EFX_MAX_FRAME_LEN(EFX_MAX_MTU), \ | |
19 | EFX_RX_USR_BUF_SIZE) | |
20 | ||
000fe940 MH |
21 | /* Number of RX buffers to recycle pages for. When creating the RX page recycle |
22 | * ring, this number is divided by the number of buffers per page to calculate | |
23 | * the number of pages to store in the RX page recycle ring. | |
24 | */ | |
25 | #define EFX_RECYCLE_RING_SIZE_10G 256 | |
26 | ||
3d95b884 AM |
27 | static inline u8 *efx_rx_buf_va(struct efx_rx_buffer *buf) |
28 | { | |
29 | return page_address(buf->page) + buf->page_offset; | |
30 | } | |
31 | ||
32 | static inline u32 efx_rx_buf_hash(struct efx_nic *efx, const u8 *eh) | |
33 | { | |
34 | #if defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) | |
35 | return __le32_to_cpup((const __le32 *)(eh + efx->rx_packet_hash_offset)); | |
36 | #else | |
37 | const u8 *data = eh + efx->rx_packet_hash_offset; | |
38 | ||
39 | return (u32)data[0] | | |
40 | (u32)data[1] << 8 | | |
41 | (u32)data[2] << 16 | | |
42 | (u32)data[3] << 24; | |
43 | #endif | |
44 | } | |
45 | ||
e1253f39 AM |
46 | void efx_rx_slow_fill(struct timer_list *t); |
47 | ||
3d95b884 AM |
48 | void efx_recycle_rx_pages(struct efx_channel *channel, |
49 | struct efx_rx_buffer *rx_buf, | |
50 | unsigned int n_frags); | |
51 | void efx_discard_rx_packet(struct efx_channel *channel, | |
52 | struct efx_rx_buffer *rx_buf, | |
53 | unsigned int n_frags); | |
54 | ||
e1253f39 AM |
55 | int efx_probe_rx_queue(struct efx_rx_queue *rx_queue); |
56 | void efx_init_rx_queue(struct efx_rx_queue *rx_queue); | |
57 | void efx_fini_rx_queue(struct efx_rx_queue *rx_queue); | |
58 | void efx_remove_rx_queue(struct efx_rx_queue *rx_queue); | |
59 | void efx_destroy_rx_queue(struct efx_rx_queue *rx_queue); | |
60 | ||
61 | void efx_init_rx_buffer(struct efx_rx_queue *rx_queue, | |
62 | struct page *page, | |
63 | unsigned int page_offset, | |
64 | u16 flags); | |
65 | void efx_unmap_rx_buffer(struct efx_nic *efx, struct efx_rx_buffer *rx_buf); | |
80a0074e EC |
66 | |
67 | static inline void efx_sync_rx_buffer(struct efx_nic *efx, | |
68 | struct efx_rx_buffer *rx_buf, | |
69 | unsigned int len) | |
70 | { | |
71 | dma_sync_single_for_cpu(&efx->pci_dev->dev, rx_buf->dma_addr, len, | |
72 | DMA_FROM_DEVICE); | |
73 | } | |
74 | ||
e1253f39 AM |
75 | void efx_free_rx_buffers(struct efx_rx_queue *rx_queue, |
76 | struct efx_rx_buffer *rx_buf, | |
77 | unsigned int num_bufs); | |
78 | ||
79 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue); | |
80 | void efx_rx_config_page_split(struct efx_nic *efx); | |
81 | void efx_fast_push_rx_descriptors(struct efx_rx_queue *rx_queue, bool atomic); | |
82 | ||
3d95b884 AM |
83 | void |
84 | efx_rx_packet_gro(struct efx_channel *channel, struct efx_rx_buffer *rx_buf, | |
4d9c0a2d | 85 | unsigned int n_frags, u8 *eh, __wsum csum); |
960f1627 | 86 | |
a9ee8d4a EC |
87 | struct efx_rss_context_priv *efx_find_rss_context_entry(struct efx_nic *efx, |
88 | u32 id); | |
89 | void efx_set_default_rx_indir_table(struct efx_nic *efx, u32 *indir); | |
f7226e0f AM |
90 | |
91 | bool efx_filter_is_mc_recipient(const struct efx_filter_spec *spec); | |
92 | bool efx_filter_spec_equal(const struct efx_filter_spec *left, | |
93 | const struct efx_filter_spec *right); | |
94 | u32 efx_filter_spec_hash(const struct efx_filter_spec *spec); | |
95 | ||
96 | #ifdef CONFIG_RFS_ACCEL | |
97 | bool efx_rps_check_rule(struct efx_arfs_rule *rule, unsigned int filter_idx, | |
98 | bool *force); | |
99 | struct efx_arfs_rule *efx_rps_hash_find(struct efx_nic *efx, | |
100 | const struct efx_filter_spec *spec); | |
101 | struct efx_arfs_rule *efx_rps_hash_add(struct efx_nic *efx, | |
102 | const struct efx_filter_spec *spec, | |
103 | bool *new); | |
104 | void efx_rps_hash_del(struct efx_nic *efx, const struct efx_filter_spec *spec); | |
28abe825 EC |
105 | |
106 | int efx_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb, | |
107 | u16 rxq_index, u32 flow_id); | |
108 | bool __efx_filter_rfs_expire(struct efx_channel *channel, unsigned int quota); | |
f7226e0f AM |
109 | #endif |
110 | ||
111 | int efx_probe_filters(struct efx_nic *efx); | |
112 | void efx_remove_filters(struct efx_nic *efx); | |
113 | ||
e1253f39 | 114 | #endif |