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qlogic: Remove extern from function prototypes
[linux-2.6-block.git] / drivers / net / ethernet / sfc / nic.h
CommitLineData
8ceee660 1/****************************************************************************
f7a6d2c4 2 * Driver for Solarflare network controllers and boards
8ceee660 3 * Copyright 2005-2006 Fen Systems Ltd.
f7a6d2c4 4 * Copyright 2006-2013 Solarflare Communications Inc.
8ceee660
BH		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
744093c9
BH		 11#ifndef EFX_NIC_H
12#define EFX_NIC_H
8ceee660 13
7c236c43 14#include <linux/net_tstamp.h>
5c16a96c 15#include <linux/i2c-algo-bit.h>
8ceee660 16#include "net_driver.h"
177dfcd8 17#include "efx.h"
8880f4ec 18#include "mcdi.h"
8ceee660 19
daeda630
BH		 20enum {
21 EFX_REV_FALCON_A0 = 0,
22 EFX_REV_FALCON_A1 = 1,
23 EFX_REV_FALCON_B0 = 2,
8880f4ec 24 EFX_REV_SIENA_A0 = 3,
8127d661 25 EFX_REV_HUNT_A0 = 4,
8ceee660
BH		 26};
27
daeda630 28static inline int efx_nic_rev(struct efx_nic *efx)
55668611 29{
daeda630 30 return efx->type->revision;
55668611 31}
8ceee660 32
86094f7f 33extern u32 efx_farch_fpga_ver(struct efx_nic *efx);
152b6a62
BH		 34
35/* NIC has two interlinked PCI functions for the same port. */
36static inline bool efx_nic_is_dual_func(struct efx_nic *efx)
37{
38 return efx_nic_rev(efx) < EFX_REV_FALCON_B0;
39}
40
86094f7f
BH		 41/* Read the current event from the event queue */
42static inline efx_qword_t *efx_event(struct efx_channel *channel,
43 unsigned int index)
44{
45 return ((efx_qword_t *) (channel->eventq.buf.addr)) +
46 (index & channel->eventq_mask);
47}
48
49/* See if an event is present
50 *
51 * We check both the high and low dword of the event for all ones. We
52 * wrote all ones when we cleared the event, and no valid event can
53 * have all ones in either its high or low dwords. This approach is
54 * robust against reordering.
55 *
56 * Note that using a single 64-bit comparison is incorrect; even
57 * though the CPU read will be atomic, the DMA write may not be.
58 */
59static inline int efx_event_present(efx_qword_t *event)
60{
61 return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
62 EFX_DWORD_IS_ALL_ONES(event->dword[1]));
63}
64
65/* Returns a pointer to the specified transmit descriptor in the TX
66 * descriptor queue belonging to the specified channel.
67 */
68static inline efx_qword_t *
69efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index)
70{
71 return ((efx_qword_t *) (tx_queue->txd.buf.addr)) + index;
72}
73
306a2782
BH		 74/* Report whether the NIC considers this TX queue empty, given the
75 * write_count used for the last doorbell push. May return false
76 * negative.
77 */
78static inline bool __efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue,
79 unsigned int write_count)
80{
81 unsigned int empty_read_count = ACCESS_ONCE(tx_queue->empty_read_count);
82
83 if (empty_read_count == 0)
84 return false;
85
86 return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0;
87}
88
89static inline bool efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue)
90{
91 return __efx_nic_tx_is_empty(tx_queue, tx_queue->write_count);
92}
93
86094f7f
BH		 94/* Decide whether to push a TX descriptor to the NIC vs merely writing
95 * the doorbell. This can reduce latency when we are adding a single
96 * descriptor to an empty queue, but is otherwise pointless. Further,
97 * Falcon and Siena have hardware bugs (SF bug 33851) that may be
98 * triggered if we don't check this.
99 */
100static inline bool efx_nic_may_push_tx_desc(struct efx_tx_queue *tx_queue,
101 unsigned int write_count)
102{
306a2782 103 bool was_empty = __efx_nic_tx_is_empty(tx_queue, write_count);
86094f7f
BH		 104
105 tx_queue->empty_read_count = 0;
306a2782 106 return was_empty && tx_queue->write_count - write_count == 1;
86094f7f
BH		 107}
108
109/* Returns a pointer to the specified descriptor in the RX descriptor queue */
110static inline efx_qword_t *
111efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
112{
113 return ((efx_qword_t *) (rx_queue->rxd.buf.addr)) + index;
114}
115
c1c4f453
BH		 116enum {
117 PHY_TYPE_NONE = 0,
118 PHY_TYPE_TXC43128 = 1,
119 PHY_TYPE_88E1111 = 2,
120 PHY_TYPE_SFX7101 = 3,
121 PHY_TYPE_QT2022C2 = 4,
122 PHY_TYPE_PM8358 = 6,
123 PHY_TYPE_SFT9001A = 8,
124 PHY_TYPE_QT2025C = 9,
125 PHY_TYPE_SFT9001B = 10,
126};
127
128#define FALCON_XMAC_LOOPBACKS \
129 ((1 << LOOPBACK_XGMII) | \
130 (1 << LOOPBACK_XGXS) | \
131 (1 << LOOPBACK_XAUI))
132
5b6262d0
BH		 133/* Alignment of PCIe DMA boundaries (4KB) */
134#define EFX_PAGE_SIZE 4096
135/* Size and alignment of buffer table entries (same) */
136#define EFX_BUF_SIZE EFX_PAGE_SIZE
137
3759433d 138/**
44838a44
BH		 139 * struct falcon_board_type - board operations and type information
140 * @id: Board type id, as found in NVRAM
3759433d
BH		 141 * @init: Allocate resources and initialise peripheral hardware
142 * @init_phy: Do board-specific PHY initialisation
44838a44 143 * @fini: Shut down hardware and free resources
3759433d
BH		 144 * @set_id_led: Set state of identifying LED or revert to automatic function
145 * @monitor: Board-specific health check function
44838a44
BH		 146 */
147struct falcon_board_type {
148 u8 id;
44838a44
BH		 149 int (*init) (struct efx_nic *nic);
150 void (*init_phy) (struct efx_nic *efx);
151 void (*fini) (struct efx_nic *nic);
152 void (*set_id_led) (struct efx_nic *efx, enum efx_led_mode mode);
153 int (*monitor) (struct efx_nic *nic);
154};
155
156/**
157 * struct falcon_board - board information
158 * @type: Type of board
159 * @major: Major rev. ('A', 'B' ...)
160 * @minor: Minor rev. (0, 1, ...)
e775fb93
BH		 161 * @i2c_adap: I2C adapter for on-board peripherals
162 * @i2c_data: Data for bit-banging algorithm
3759433d
BH		 163 * @hwmon_client: I2C client for hardware monitor
164 * @ioexp_client: I2C client for power/port control
165 */
166struct falcon_board {
44838a44 167 const struct falcon_board_type *type;
3759433d
BH		 168 int major;
169 int minor;
e775fb93
BH		 170 struct i2c_adapter i2c_adap;
171 struct i2c_algo_bit_data i2c_data;
3759433d
BH		 172 struct i2c_client *hwmon_client, *ioexp_client;
173};
174
45a3fd55
BH		 175/**
176 * struct falcon_spi_device - a Falcon SPI (Serial Peripheral Interface) device
177 * @device_id: Controller's id for the device
178 * @size: Size (in bytes)
179 * @addr_len: Number of address bytes in read/write commands
180 * @munge_address: Flag whether addresses should be munged.
181 * Some devices with 9-bit addresses (e.g. AT25040A EEPROM)
182 * use bit 3 of the command byte as address bit A8, rather
183 * than having a two-byte address. If this flag is set, then
184 * commands should be munged in this way.
185 * @erase_command: Erase command (or 0 if sector erase not needed).
186 * @erase_size: Erase sector size (in bytes)
187 * Erase commands affect sectors with this size and alignment.
188 * This must be a power of two.
189 * @block_size: Write block size (in bytes).
190 * Write commands are limited to blocks with this size and alignment.
191 */
192struct falcon_spi_device {
193 int device_id;
194 unsigned int size;
195 unsigned int addr_len;
196 unsigned int munge_address:1;
197 u8 erase_command;
198 unsigned int erase_size;
199 unsigned int block_size;
200};
201
202static inline bool falcon_spi_present(const struct falcon_spi_device *spi)
203{
204 return spi->size != 0;
205}
206
cd0ecc9a
BH		 207enum {
208 FALCON_STAT_tx_bytes,
209 FALCON_STAT_tx_packets,
210 FALCON_STAT_tx_pause,
211 FALCON_STAT_tx_control,
212 FALCON_STAT_tx_unicast,
213 FALCON_STAT_tx_multicast,
214 FALCON_STAT_tx_broadcast,
215 FALCON_STAT_tx_lt64,
216 FALCON_STAT_tx_64,
217 FALCON_STAT_tx_65_to_127,
218 FALCON_STAT_tx_128_to_255,
219 FALCON_STAT_tx_256_to_511,
220 FALCON_STAT_tx_512_to_1023,
221 FALCON_STAT_tx_1024_to_15xx,
222 FALCON_STAT_tx_15xx_to_jumbo,
223 FALCON_STAT_tx_gtjumbo,
224 FALCON_STAT_tx_non_tcpudp,
225 FALCON_STAT_tx_mac_src_error,
226 FALCON_STAT_tx_ip_src_error,
227 FALCON_STAT_rx_bytes,
228 FALCON_STAT_rx_good_bytes,
229 FALCON_STAT_rx_bad_bytes,
230 FALCON_STAT_rx_packets,
231 FALCON_STAT_rx_good,
232 FALCON_STAT_rx_bad,
233 FALCON_STAT_rx_pause,
234 FALCON_STAT_rx_control,
235 FALCON_STAT_rx_unicast,
236 FALCON_STAT_rx_multicast,
237 FALCON_STAT_rx_broadcast,
238 FALCON_STAT_rx_lt64,
239 FALCON_STAT_rx_64,
240 FALCON_STAT_rx_65_to_127,
241 FALCON_STAT_rx_128_to_255,
242 FALCON_STAT_rx_256_to_511,
243 FALCON_STAT_rx_512_to_1023,
244 FALCON_STAT_rx_1024_to_15xx,
245 FALCON_STAT_rx_15xx_to_jumbo,
246 FALCON_STAT_rx_gtjumbo,
247 FALCON_STAT_rx_bad_lt64,
248 FALCON_STAT_rx_bad_gtjumbo,
249 FALCON_STAT_rx_overflow,
250 FALCON_STAT_rx_symbol_error,
251 FALCON_STAT_rx_align_error,
252 FALCON_STAT_rx_length_error,
253 FALCON_STAT_rx_internal_error,
254 FALCON_STAT_rx_nodesc_drop_cnt,
255 FALCON_STAT_COUNT
256};
257
5c16a96c
BH		 258/**
259 * struct falcon_nic_data - Falcon NIC state
8986352a 260 * @pci_dev2: Secondary function of Falcon A
3759433d 261 * @board: Board state and functions
cd0ecc9a 262 * @stats: Hardware statistics
55edc6e6
BH		 263 * @stats_disable_count: Nest count for disabling statistics fetches
264 * @stats_pending: Is there a pending DMA of MAC statistics.
265 * @stats_timer: A timer for regularly fetching MAC statistics.
4de92180
BH		 266 * @spi_flash: SPI flash device
267 * @spi_eeprom: SPI EEPROM device
268 * @spi_lock: SPI bus lock
4833f02a 269 * @mdio_lock: MDIO bus lock
cef68bde 270 * @xmac_poll_required: XMAC link state needs polling
5c16a96c
BH		 271 */
272struct falcon_nic_data {
273 struct pci_dev *pci_dev2;
3759433d 274 struct falcon_board board;
cd0ecc9a 275 u64 stats[FALCON_STAT_COUNT];
55edc6e6
BH		 276 unsigned int stats_disable_count;
277 bool stats_pending;
278 struct timer_list stats_timer;
ecd0a6f0
BH		 279 struct falcon_spi_device spi_flash;
280 struct falcon_spi_device spi_eeprom;
4de92180 281 struct mutex spi_lock;
4833f02a 282 struct mutex mdio_lock;
cef68bde 283 bool xmac_poll_required;
5c16a96c
BH		 284};
285
278c0621
BH		 286static inline struct falcon_board *falcon_board(struct efx_nic *efx)
287{
3759433d
BH		 288 struct falcon_nic_data *data = efx->nic_data;
289 return &data->board;
278c0621
BH		 290}
291
cd0ecc9a
BH		 292enum {
293 SIENA_STAT_tx_bytes,
294 SIENA_STAT_tx_good_bytes,
295 SIENA_STAT_tx_bad_bytes,
296 SIENA_STAT_tx_packets,
297 SIENA_STAT_tx_bad,
298 SIENA_STAT_tx_pause,
299 SIENA_STAT_tx_control,
300 SIENA_STAT_tx_unicast,
301 SIENA_STAT_tx_multicast,
302 SIENA_STAT_tx_broadcast,
303 SIENA_STAT_tx_lt64,
304 SIENA_STAT_tx_64,
305 SIENA_STAT_tx_65_to_127,
306 SIENA_STAT_tx_128_to_255,
307 SIENA_STAT_tx_256_to_511,
308 SIENA_STAT_tx_512_to_1023,
309 SIENA_STAT_tx_1024_to_15xx,
310 SIENA_STAT_tx_15xx_to_jumbo,
311 SIENA_STAT_tx_gtjumbo,
312 SIENA_STAT_tx_collision,
313 SIENA_STAT_tx_single_collision,
314 SIENA_STAT_tx_multiple_collision,
315 SIENA_STAT_tx_excessive_collision,
316 SIENA_STAT_tx_deferred,
317 SIENA_STAT_tx_late_collision,
318 SIENA_STAT_tx_excessive_deferred,
319 SIENA_STAT_tx_non_tcpudp,
320 SIENA_STAT_tx_mac_src_error,
321 SIENA_STAT_tx_ip_src_error,
322 SIENA_STAT_rx_bytes,
323 SIENA_STAT_rx_good_bytes,
324 SIENA_STAT_rx_bad_bytes,
325 SIENA_STAT_rx_packets,
326 SIENA_STAT_rx_good,
327 SIENA_STAT_rx_bad,
328 SIENA_STAT_rx_pause,
329 SIENA_STAT_rx_control,
330 SIENA_STAT_rx_unicast,
331 SIENA_STAT_rx_multicast,
332 SIENA_STAT_rx_broadcast,
333 SIENA_STAT_rx_lt64,
334 SIENA_STAT_rx_64,
335 SIENA_STAT_rx_65_to_127,
336 SIENA_STAT_rx_128_to_255,
337 SIENA_STAT_rx_256_to_511,
338 SIENA_STAT_rx_512_to_1023,
339 SIENA_STAT_rx_1024_to_15xx,
340 SIENA_STAT_rx_15xx_to_jumbo,
341 SIENA_STAT_rx_gtjumbo,
342 SIENA_STAT_rx_bad_gtjumbo,
343 SIENA_STAT_rx_overflow,
344 SIENA_STAT_rx_false_carrier,
345 SIENA_STAT_rx_symbol_error,
346 SIENA_STAT_rx_align_error,
347 SIENA_STAT_rx_length_error,
348 SIENA_STAT_rx_internal_error,
349 SIENA_STAT_rx_nodesc_drop_cnt,
350 SIENA_STAT_COUNT
351};
352
8880f4ec
BH		 353/**
354 * struct siena_nic_data - Siena NIC state
8880f4ec 355 * @wol_filter_id: Wake-on-LAN packet filter id
cd0ecc9a 356 * @stats: Hardware statistics
8880f4ec
BH		 357 */
358struct siena_nic_data {
8880f4ec 359 int wol_filter_id;
cd0ecc9a 360 u64 stats[SIENA_STAT_COUNT];
8880f4ec
BH		 361};
362
8127d661
BH		 363enum {
364 EF10_STAT_tx_bytes,
365 EF10_STAT_tx_packets,
366 EF10_STAT_tx_pause,
367 EF10_STAT_tx_control,
368 EF10_STAT_tx_unicast,
369 EF10_STAT_tx_multicast,
370 EF10_STAT_tx_broadcast,
371 EF10_STAT_tx_lt64,
372 EF10_STAT_tx_64,
373 EF10_STAT_tx_65_to_127,
374 EF10_STAT_tx_128_to_255,
375 EF10_STAT_tx_256_to_511,
376 EF10_STAT_tx_512_to_1023,
377 EF10_STAT_tx_1024_to_15xx,
378 EF10_STAT_tx_15xx_to_jumbo,
379 EF10_STAT_rx_bytes,
380 EF10_STAT_rx_bytes_minus_good_bytes,
381 EF10_STAT_rx_good_bytes,
382 EF10_STAT_rx_bad_bytes,
383 EF10_STAT_rx_packets,
384 EF10_STAT_rx_good,
385 EF10_STAT_rx_bad,
386 EF10_STAT_rx_pause,
387 EF10_STAT_rx_control,
388 EF10_STAT_rx_unicast,
389 EF10_STAT_rx_multicast,
390 EF10_STAT_rx_broadcast,
391 EF10_STAT_rx_lt64,
392 EF10_STAT_rx_64,
393 EF10_STAT_rx_65_to_127,
394 EF10_STAT_rx_128_to_255,
395 EF10_STAT_rx_256_to_511,
396 EF10_STAT_rx_512_to_1023,
397 EF10_STAT_rx_1024_to_15xx,
398 EF10_STAT_rx_15xx_to_jumbo,
399 EF10_STAT_rx_gtjumbo,
400 EF10_STAT_rx_bad_gtjumbo,
401 EF10_STAT_rx_overflow,
402 EF10_STAT_rx_align_error,
403 EF10_STAT_rx_length_error,
404 EF10_STAT_rx_nodesc_drops,
405 EF10_STAT_COUNT
406};
407
183233be
BH		 408/* Maximum number of TX PIO buffers we may allocate to a function.
409 * This matches the total number of buffers on each SFC9100-family
410 * controller.
411 */
412#define EF10_TX_PIOBUF_COUNT 16
413
8127d661
BH		 414/**
415 * struct efx_ef10_nic_data - EF10 architecture NIC state
416 * @mcdi_buf: DMA buffer for MCDI
417 * @warm_boot_count: Last seen MC warm boot count
418 * @vi_base: Absolute index of first VI in this function
419 * @n_allocated_vis: Number of VIs allocated to this function
420 * @must_realloc_vis: Flag: VIs have yet to be reallocated after MC reboot
421 * @must_restore_filters: Flag: filters have yet to be restored after MC reboot
183233be
BH		 422 * @n_piobufs: Number of PIO buffers allocated to this function
423 * @wc_membase: Base address of write-combining mapping of the memory BAR
424 * @pio_write_base: Base address for writing PIO buffers
425 * @pio_write_vi_base: Relative VI number for @pio_write_base
426 * @piobuf_handle: Handle of each PIO buffer allocated
427 * @must_restore_piobufs: Flag: PIO buffers have yet to be restored after MC
428 * reboot
8127d661
BH		 429 * @rx_rss_context: Firmware handle for our RSS context
430 * @stats: Hardware statistics
431 * @workaround_35388: Flag: firmware supports workaround for bug 35388
a915ccc9
BH		 432 * @must_check_datapath_caps: Flag: @datapath_caps needs to be revalidated
433 * after MC reboot
8127d661
BH		 434 * @datapath_caps: Capabilities of datapath firmware (FLAGS1 field of
435 * %MC_CMD_GET_CAPABILITIES response)
436 */
437struct efx_ef10_nic_data {
438 struct efx_buffer mcdi_buf;
439 u16 warm_boot_count;
440 unsigned int vi_base;
441 unsigned int n_allocated_vis;
442 bool must_realloc_vis;
443 bool must_restore_filters;
183233be
BH		 444 unsigned int n_piobufs;
445 void __iomem *wc_membase, *pio_write_base;
446 unsigned int pio_write_vi_base;
447 unsigned int piobuf_handle[EF10_TX_PIOBUF_COUNT];
448 bool must_restore_piobufs;
8127d661
BH		 449 u32 rx_rss_context;
450 u64 stats[EF10_STAT_COUNT];
451 bool workaround_35388;
a915ccc9 452 bool must_check_datapath_caps;
8127d661
BH		 453 u32 datapath_caps;
454};
455
cd2d5b52
BH		 456/*
457 * On the SFC9000 family each port is associated with 1 PCI physical
458 * function (PF) handled by sfc and a configurable number of virtual
459 * functions (VFs) that may be handled by some other driver, often in
460 * a VM guest. The queue pointer registers are mapped in both PF and
461 * VF BARs such that an 8K region provides access to a single RX, TX
462 * and event queue (collectively a Virtual Interface, VI or VNIC).
463 *
464 * The PF has access to all 1024 VIs while VFs are mapped to VIs
465 * according to VI_BASE and VI_SCALE: VF i has access to VIs numbered
466 * in range [VI_BASE + i << VI_SCALE, VI_BASE + i + 1 << VI_SCALE).
467 * The number of VIs and the VI_SCALE value are configurable but must
468 * be established at boot time by firmware.
469 */
470
471/* Maximum VI_SCALE parameter supported by Siena */
472#define EFX_VI_SCALE_MAX 6
473/* Base VI to use for SR-IOV. Must be aligned to (1 << EFX_VI_SCALE_MAX),
474 * so this is the smallest allowed value. */
475#define EFX_VI_BASE 128U
476/* Maximum number of VFs allowed */
477#define EFX_VF_COUNT_MAX 127
478/* Limit EVQs on VFs to be only 8k to reduce buffer table reservation */
479#define EFX_MAX_VF_EVQ_SIZE 8192UL
480/* The number of buffer table entries reserved for each VI on a VF */
481#define EFX_VF_BUFTBL_PER_VI \
482 ((EFX_MAX_VF_EVQ_SIZE + 2 * EFX_MAX_DMAQ_SIZE) * \
483 sizeof(efx_qword_t) / EFX_BUF_SIZE)
484
485#ifdef CONFIG_SFC_SRIOV
486
487static inline bool efx_sriov_wanted(struct efx_nic *efx)
488{
489 return efx->vf_count != 0;
490}
491static inline bool efx_sriov_enabled(struct efx_nic *efx)
492{
493 return efx->vf_init_count != 0;
494}
495static inline unsigned int efx_vf_size(struct efx_nic *efx)
496{
497 return 1 << efx->vi_scale;
498}
499
500extern int efx_init_sriov(void);
501extern void efx_sriov_probe(struct efx_nic *efx);
502extern int efx_sriov_init(struct efx_nic *efx);
503extern void efx_sriov_mac_address_changed(struct efx_nic *efx);
504extern void efx_sriov_tx_flush_done(struct efx_nic *efx, efx_qword_t *event);
505extern void efx_sriov_rx_flush_done(struct efx_nic *efx, efx_qword_t *event);
506extern void efx_sriov_event(struct efx_channel *channel, efx_qword_t *event);
507extern void efx_sriov_desc_fetch_err(struct efx_nic *efx, unsigned dmaq);
508extern void efx_sriov_flr(struct efx_nic *efx, unsigned flr);
509extern void efx_sriov_reset(struct efx_nic *efx);
510extern void efx_sriov_fini(struct efx_nic *efx);
511extern void efx_fini_sriov(void);
512
513#else
514
515static inline bool efx_sriov_wanted(struct efx_nic *efx) { return false; }
516static inline bool efx_sriov_enabled(struct efx_nic *efx) { return false; }
517static inline unsigned int efx_vf_size(struct efx_nic *efx) { return 0; }
518
519static inline int efx_init_sriov(void) { return 0; }
520static inline void efx_sriov_probe(struct efx_nic *efx) {}
521static inline int efx_sriov_init(struct efx_nic *efx) { return -EOPNOTSUPP; }
522static inline void efx_sriov_mac_address_changed(struct efx_nic *efx) {}
523static inline void efx_sriov_tx_flush_done(struct efx_nic *efx,
524 efx_qword_t *event) {}
525static inline void efx_sriov_rx_flush_done(struct efx_nic *efx,
526 efx_qword_t *event) {}
527static inline void efx_sriov_event(struct efx_channel *channel,
528 efx_qword_t *event) {}
529static inline void efx_sriov_desc_fetch_err(struct efx_nic *efx, unsigned dmaq) {}
530static inline void efx_sriov_flr(struct efx_nic *efx, unsigned flr) {}
531static inline void efx_sriov_reset(struct efx_nic *efx) {}
532static inline void efx_sriov_fini(struct efx_nic *efx) {}
533static inline void efx_fini_sriov(void) {}
534
535#endif
536
537extern int efx_sriov_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
538extern int efx_sriov_set_vf_vlan(struct net_device *dev, int vf,
539 u16 vlan, u8 qos);
540extern int efx_sriov_get_vf_config(struct net_device *dev, int vf,
541 struct ifla_vf_info *ivf);
542extern int efx_sriov_set_vf_spoofchk(struct net_device *net_dev, int vf,
543 bool spoofchk);
544
7c236c43 545struct ethtool_ts_info;
7c236c43
SH		 546extern void efx_ptp_probe(struct efx_nic *efx);
547extern int efx_ptp_ioctl(struct efx_nic *efx, struct ifreq *ifr, int cmd);
62ebac92
BH		 548extern void efx_ptp_get_ts_info(struct efx_nic *efx,
549 struct ethtool_ts_info *ts_info);
7c236c43
SH		 550extern bool efx_ptp_is_ptp_tx(struct efx_nic *efx, struct sk_buff *skb);
551extern int efx_ptp_tx(struct efx_nic *efx, struct sk_buff *skb);
552extern void efx_ptp_event(struct efx_nic *efx, efx_qword_t *ev);
7c236c43 553
6c8c2513 554extern const struct efx_nic_type falcon_a1_nic_type;
555extern const struct efx_nic_type falcon_b0_nic_type;
556extern const struct efx_nic_type siena_a0_nic_type;
8127d661 557extern const struct efx_nic_type efx_hunt_a0_nic_type;
8ceee660
BH		 558
559/**************************************************************************
560 *
561 * Externs
562 *
563 **************************************************************************
564 */
565
e41c11ee 566extern int falcon_probe_board(struct efx_nic *efx, u16 revision_info);
5087b54d 567
8ceee660 568/* TX data path */
86094f7f
BH		 569static inline int efx_nic_probe_tx(struct efx_tx_queue *tx_queue)
570{
571 return tx_queue->efx->type->tx_probe(tx_queue);
572}
573static inline void efx_nic_init_tx(struct efx_tx_queue *tx_queue)
574{
575 tx_queue->efx->type->tx_init(tx_queue);
576}
577static inline void efx_nic_remove_tx(struct efx_tx_queue *tx_queue)
578{
579 tx_queue->efx->type->tx_remove(tx_queue);
580}
581static inline void efx_nic_push_buffers(struct efx_tx_queue *tx_queue)
582{
583 tx_queue->efx->type->tx_write(tx_queue);
584}
8ceee660
BH		 585
586/* RX data path */
86094f7f
BH		 587static inline int efx_nic_probe_rx(struct efx_rx_queue *rx_queue)
588{
589 return rx_queue->efx->type->rx_probe(rx_queue);
590}
591static inline void efx_nic_init_rx(struct efx_rx_queue *rx_queue)
592{
593 rx_queue->efx->type->rx_init(rx_queue);
594}
595static inline void efx_nic_remove_rx(struct efx_rx_queue *rx_queue)
596{
597 rx_queue->efx->type->rx_remove(rx_queue);
598}
599static inline void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue)
600{
601 rx_queue->efx->type->rx_write(rx_queue);
602}
603static inline void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue)
604{
605 rx_queue->efx->type->rx_defer_refill(rx_queue);
606}
8ceee660
BH		 607
608/* Event data path */
86094f7f
BH		 609static inline int efx_nic_probe_eventq(struct efx_channel *channel)
610{
611 return channel->efx->type->ev_probe(channel);
612}
261e4d96 613static inline int efx_nic_init_eventq(struct efx_channel *channel)
86094f7f 614{
261e4d96 615 return channel->efx->type->ev_init(channel);
86094f7f
BH		 616}
617static inline void efx_nic_fini_eventq(struct efx_channel *channel)
618{
619 channel->efx->type->ev_fini(channel);
620}
621static inline void efx_nic_remove_eventq(struct efx_channel *channel)
622{
623 channel->efx->type->ev_remove(channel);
624}
625static inline int
626efx_nic_process_eventq(struct efx_channel *channel, int quota)
627{
628 return channel->efx->type->ev_process(channel, quota);
629}
630static inline void efx_nic_eventq_read_ack(struct efx_channel *channel)
631{
632 channel->efx->type->ev_read_ack(channel);
633}
634extern void efx_nic_event_test_start(struct efx_channel *channel);
635
636/* Falcon/Siena queue operations */
637extern int efx_farch_tx_probe(struct efx_tx_queue *tx_queue);
638extern void efx_farch_tx_init(struct efx_tx_queue *tx_queue);
639extern void efx_farch_tx_fini(struct efx_tx_queue *tx_queue);
640extern void efx_farch_tx_remove(struct efx_tx_queue *tx_queue);
641extern void efx_farch_tx_write(struct efx_tx_queue *tx_queue);
642extern int efx_farch_rx_probe(struct efx_rx_queue *rx_queue);
643extern void efx_farch_rx_init(struct efx_rx_queue *rx_queue);
644extern void efx_farch_rx_fini(struct efx_rx_queue *rx_queue);
645extern void efx_farch_rx_remove(struct efx_rx_queue *rx_queue);
646extern void efx_farch_rx_write(struct efx_rx_queue *rx_queue);
647extern void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue);
648extern int efx_farch_ev_probe(struct efx_channel *channel);
261e4d96 649extern int efx_farch_ev_init(struct efx_channel *channel);
86094f7f
BH		 650extern void efx_farch_ev_fini(struct efx_channel *channel);
651extern void efx_farch_ev_remove(struct efx_channel *channel);
652extern int efx_farch_ev_process(struct efx_channel *channel, int quota);
653extern void efx_farch_ev_read_ack(struct efx_channel *channel);
654extern void efx_farch_ev_test_generate(struct efx_channel *channel);
655
add72477
BH		 656/* Falcon/Siena filter operations */
657extern int efx_farch_filter_table_probe(struct efx_nic *efx);
658extern void efx_farch_filter_table_restore(struct efx_nic *efx);
659extern void efx_farch_filter_table_remove(struct efx_nic *efx);
660extern void efx_farch_filter_update_rx_scatter(struct efx_nic *efx);
661extern s32 efx_farch_filter_insert(struct efx_nic *efx,
662 struct efx_filter_spec *spec, bool replace);
663extern int efx_farch_filter_remove_safe(struct efx_nic *efx,
664 enum efx_filter_priority priority,
665 u32 filter_id);
666extern int efx_farch_filter_get_safe(struct efx_nic *efx,
667 enum efx_filter_priority priority,
668 u32 filter_id, struct efx_filter_spec *);
669extern void efx_farch_filter_clear_rx(struct efx_nic *efx,
670 enum efx_filter_priority priority);
671extern u32 efx_farch_filter_count_rx_used(struct efx_nic *efx,
672 enum efx_filter_priority priority);
673extern u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx);
674extern s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx,
675 enum efx_filter_priority priority,
676 u32 *buf, u32 size);
677#ifdef CONFIG_RFS_ACCEL
678extern s32 efx_farch_filter_rfs_insert(struct efx_nic *efx,
679 struct efx_filter_spec *spec);
680extern bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
681 unsigned int index);
682#endif
964e6135 683extern void efx_farch_filter_sync_rx_mode(struct efx_nic *efx);
add72477 684
d4fabcc8 685extern bool efx_nic_event_present(struct efx_channel *channel);
8ceee660 686
b7f514af
BH		 687/* Some statistics are computed as A - B where A and B each increase
688 * linearly with some hardware counter(s) and the counters are read
689 * asynchronously. If the counters contributing to B are always read
690 * after those contributing to A, the computed value may be lower than
691 * the true value by some variable amount, and may decrease between
692 * subsequent computations.
693 *
694 * We should never allow statistics to decrease or to exceed the true
695 * value. Since the computed value will never be greater than the
696 * true value, we can achieve this by only storing the computed value
697 * when it increases.
698 */
699static inline void efx_update_diff_stat(u64 *stat, u64 diff)
700{
701 if ((s64)(diff - *stat) > 0)
702 *stat = diff;
703}
704
86094f7f 705/* Interrupts */
152b6a62 706extern int efx_nic_init_interrupt(struct efx_nic *efx);
eee6f6a9 707extern void efx_nic_irq_test_start(struct efx_nic *efx);
152b6a62 708extern void efx_nic_fini_interrupt(struct efx_nic *efx);
86094f7f
BH		 709
710/* Falcon/Siena interrupts */
711extern void efx_farch_irq_enable_master(struct efx_nic *efx);
712extern void efx_farch_irq_test_generate(struct efx_nic *efx);
713extern void efx_farch_irq_disable_master(struct efx_nic *efx);
714extern irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id);
715extern irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id);
716extern irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx);
152b6a62 717
eee6f6a9
BH		 718static inline int efx_nic_event_test_irq_cpu(struct efx_channel *channel)
719{
dd40781e 720 return ACCESS_ONCE(channel->event_test_cpu);
eee6f6a9
BH		 721}
722static inline int efx_nic_irq_test_irq_cpu(struct efx_nic *efx)
723{
724 return ACCESS_ONCE(efx->last_irq_cpu);
725}
726
8ceee660 727/* Global Resources */
86094f7f 728extern int efx_nic_flush_queues(struct efx_nic *efx);
d5e8cc6c 729extern void siena_prepare_flush(struct efx_nic *efx);
86094f7f 730extern int efx_farch_fini_dmaq(struct efx_nic *efx);
d5e8cc6c 731extern void siena_finish_flush(struct efx_nic *efx);
55edc6e6
BH		 732extern void falcon_start_nic_stats(struct efx_nic *efx);
733extern void falcon_stop_nic_stats(struct efx_nic *efx);
8ceee660 734extern int falcon_reset_xaui(struct efx_nic *efx);
86094f7f
BH		 735extern void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw);
736extern void efx_farch_init_common(struct efx_nic *efx);
8127d661 737extern void efx_ef10_handle_drain_event(struct efx_nic *efx);
86094f7f
BH		 738static inline void efx_nic_push_rx_indir_table(struct efx_nic *efx)
739{
740 efx->type->rx_push_indir_table(efx);
741}
742extern void efx_farch_rx_push_indir_table(struct efx_nic *efx);
152b6a62
BH		 743
744int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
0d19a540 745 unsigned int len, gfp_t gfp_flags);
152b6a62 746void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer);
8ceee660 747
8c8661e4 748/* Tests */
86094f7f 749struct efx_farch_register_test {
152b6a62
BH		 750 unsigned address;
751 efx_oword_t mask;
752};
86094f7f
BH		 753extern int efx_farch_test_registers(struct efx_nic *efx,
754 const struct efx_farch_register_test *regs,
755 size_t n_regs);
8c8661e4 756
5b98c1bf
BH		 757extern size_t efx_nic_get_regs_len(struct efx_nic *efx);
758extern void efx_nic_get_regs(struct efx_nic *efx, void *buf);
759
cd0ecc9a
BH		 760extern size_t
761efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count,
762 const unsigned long *mask, u8 *names);
763extern void
764efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count,
765 const unsigned long *mask,
766 u64 *stats, const void *dma_buf, bool accumulate);
767
ab0115fc 768#define EFX_MAX_FLUSH_TIME 5000
8ceee660 769
86094f7f
BH		 770extern void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq,
771 efx_qword_t *event);
8ceee660 772
744093c9 773#endif /* EFX_NIC_H */
Linux 6.x block layer and io_uring tree(s)