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8ceee660 | 1 | /**************************************************************************** |
f7a6d2c4 | 2 | * Driver for Solarflare network controllers and boards |
8ceee660 | 3 | * Copyright 2005-2006 Fen Systems Ltd. |
f7a6d2c4 | 4 | * Copyright 2006-2013 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
744093c9 BH |
11 | #ifndef EFX_NIC_H |
12 | #define EFX_NIC_H | |
8ceee660 | 13 | |
7c236c43 | 14 | #include <linux/net_tstamp.h> |
5c16a96c | 15 | #include <linux/i2c-algo-bit.h> |
8ceee660 | 16 | #include "net_driver.h" |
177dfcd8 | 17 | #include "efx.h" |
8880f4ec | 18 | #include "mcdi.h" |
8ceee660 | 19 | |
daeda630 BH |
20 | enum { |
21 | EFX_REV_FALCON_A0 = 0, | |
22 | EFX_REV_FALCON_A1 = 1, | |
23 | EFX_REV_FALCON_B0 = 2, | |
8880f4ec | 24 | EFX_REV_SIENA_A0 = 3, |
8127d661 | 25 | EFX_REV_HUNT_A0 = 4, |
8ceee660 BH |
26 | }; |
27 | ||
daeda630 | 28 | static inline int efx_nic_rev(struct efx_nic *efx) |
55668611 | 29 | { |
daeda630 | 30 | return efx->type->revision; |
55668611 | 31 | } |
8ceee660 | 32 | |
00aef986 | 33 | u32 efx_farch_fpga_ver(struct efx_nic *efx); |
152b6a62 BH |
34 | |
35 | /* NIC has two interlinked PCI functions for the same port. */ | |
36 | static inline bool efx_nic_is_dual_func(struct efx_nic *efx) | |
37 | { | |
38 | return efx_nic_rev(efx) < EFX_REV_FALCON_B0; | |
39 | } | |
40 | ||
86094f7f BH |
41 | /* Read the current event from the event queue */ |
42 | static inline efx_qword_t *efx_event(struct efx_channel *channel, | |
43 | unsigned int index) | |
44 | { | |
45 | return ((efx_qword_t *) (channel->eventq.buf.addr)) + | |
46 | (index & channel->eventq_mask); | |
47 | } | |
48 | ||
49 | /* See if an event is present | |
50 | * | |
51 | * We check both the high and low dword of the event for all ones. We | |
52 | * wrote all ones when we cleared the event, and no valid event can | |
53 | * have all ones in either its high or low dwords. This approach is | |
54 | * robust against reordering. | |
55 | * | |
56 | * Note that using a single 64-bit comparison is incorrect; even | |
57 | * though the CPU read will be atomic, the DMA write may not be. | |
58 | */ | |
59 | static inline int efx_event_present(efx_qword_t *event) | |
60 | { | |
61 | return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) | | |
62 | EFX_DWORD_IS_ALL_ONES(event->dword[1])); | |
63 | } | |
64 | ||
65 | /* Returns a pointer to the specified transmit descriptor in the TX | |
66 | * descriptor queue belonging to the specified channel. | |
67 | */ | |
68 | static inline efx_qword_t * | |
69 | efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index) | |
70 | { | |
71 | return ((efx_qword_t *) (tx_queue->txd.buf.addr)) + index; | |
72 | } | |
73 | ||
70b33fb0 EC |
74 | /* Get partner of a TX queue, seen as part of the same net core queue */ |
75 | static struct efx_tx_queue *efx_tx_queue_partner(struct efx_tx_queue *tx_queue) | |
76 | { | |
77 | if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD) | |
78 | return tx_queue - EFX_TXQ_TYPE_OFFLOAD; | |
79 | else | |
80 | return tx_queue + EFX_TXQ_TYPE_OFFLOAD; | |
81 | } | |
82 | ||
83 | /* Report whether this TX queue would be empty for the given write_count. | |
84 | * May return false negative. | |
306a2782 BH |
85 | */ |
86 | static inline bool __efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue, | |
87 | unsigned int write_count) | |
88 | { | |
89 | unsigned int empty_read_count = ACCESS_ONCE(tx_queue->empty_read_count); | |
90 | ||
91 | if (empty_read_count == 0) | |
92 | return false; | |
93 | ||
94 | return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0; | |
95 | } | |
96 | ||
70b33fb0 EC |
97 | /* Decide whether we can use TX PIO, ie. write packet data directly into |
98 | * a buffer on the device. This can reduce latency at the expense of | |
99 | * throughput, so we only do this if both hardware and software TX rings | |
100 | * are empty. This also ensures that only one packet at a time can be | |
101 | * using the PIO buffer. | |
102 | */ | |
103 | static inline bool efx_nic_may_tx_pio(struct efx_tx_queue *tx_queue) | |
306a2782 | 104 | { |
70b33fb0 EC |
105 | struct efx_tx_queue *partner = efx_tx_queue_partner(tx_queue); |
106 | return tx_queue->piobuf && | |
107 | __efx_nic_tx_is_empty(tx_queue, tx_queue->insert_count) && | |
108 | __efx_nic_tx_is_empty(partner, partner->insert_count); | |
306a2782 BH |
109 | } |
110 | ||
86094f7f BH |
111 | /* Decide whether to push a TX descriptor to the NIC vs merely writing |
112 | * the doorbell. This can reduce latency when we are adding a single | |
113 | * descriptor to an empty queue, but is otherwise pointless. Further, | |
114 | * Falcon and Siena have hardware bugs (SF bug 33851) that may be | |
115 | * triggered if we don't check this. | |
70b33fb0 EC |
116 | * We use the write_count used for the last doorbell push, to get the |
117 | * NIC's view of the tx queue. | |
86094f7f BH |
118 | */ |
119 | static inline bool efx_nic_may_push_tx_desc(struct efx_tx_queue *tx_queue, | |
120 | unsigned int write_count) | |
121 | { | |
306a2782 | 122 | bool was_empty = __efx_nic_tx_is_empty(tx_queue, write_count); |
86094f7f BH |
123 | |
124 | tx_queue->empty_read_count = 0; | |
306a2782 | 125 | return was_empty && tx_queue->write_count - write_count == 1; |
86094f7f BH |
126 | } |
127 | ||
128 | /* Returns a pointer to the specified descriptor in the RX descriptor queue */ | |
129 | static inline efx_qword_t * | |
130 | efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) | |
131 | { | |
132 | return ((efx_qword_t *) (rx_queue->rxd.buf.addr)) + index; | |
133 | } | |
134 | ||
c1c4f453 BH |
135 | enum { |
136 | PHY_TYPE_NONE = 0, | |
137 | PHY_TYPE_TXC43128 = 1, | |
138 | PHY_TYPE_88E1111 = 2, | |
139 | PHY_TYPE_SFX7101 = 3, | |
140 | PHY_TYPE_QT2022C2 = 4, | |
141 | PHY_TYPE_PM8358 = 6, | |
142 | PHY_TYPE_SFT9001A = 8, | |
143 | PHY_TYPE_QT2025C = 9, | |
144 | PHY_TYPE_SFT9001B = 10, | |
145 | }; | |
146 | ||
147 | #define FALCON_XMAC_LOOPBACKS \ | |
148 | ((1 << LOOPBACK_XGMII) | \ | |
149 | (1 << LOOPBACK_XGXS) | \ | |
150 | (1 << LOOPBACK_XAUI)) | |
151 | ||
5b6262d0 BH |
152 | /* Alignment of PCIe DMA boundaries (4KB) */ |
153 | #define EFX_PAGE_SIZE 4096 | |
154 | /* Size and alignment of buffer table entries (same) */ | |
155 | #define EFX_BUF_SIZE EFX_PAGE_SIZE | |
156 | ||
e4d112e4 EC |
157 | /* NIC-generic software stats */ |
158 | enum { | |
159 | GENERIC_STAT_rx_noskb_drops, | |
160 | GENERIC_STAT_rx_nodesc_trunc, | |
161 | GENERIC_STAT_COUNT | |
162 | }; | |
163 | ||
3759433d | 164 | /** |
44838a44 BH |
165 | * struct falcon_board_type - board operations and type information |
166 | * @id: Board type id, as found in NVRAM | |
3759433d BH |
167 | * @init: Allocate resources and initialise peripheral hardware |
168 | * @init_phy: Do board-specific PHY initialisation | |
44838a44 | 169 | * @fini: Shut down hardware and free resources |
3759433d BH |
170 | * @set_id_led: Set state of identifying LED or revert to automatic function |
171 | * @monitor: Board-specific health check function | |
44838a44 BH |
172 | */ |
173 | struct falcon_board_type { | |
174 | u8 id; | |
44838a44 BH |
175 | int (*init) (struct efx_nic *nic); |
176 | void (*init_phy) (struct efx_nic *efx); | |
177 | void (*fini) (struct efx_nic *nic); | |
178 | void (*set_id_led) (struct efx_nic *efx, enum efx_led_mode mode); | |
179 | int (*monitor) (struct efx_nic *nic); | |
180 | }; | |
181 | ||
182 | /** | |
183 | * struct falcon_board - board information | |
184 | * @type: Type of board | |
185 | * @major: Major rev. ('A', 'B' ...) | |
186 | * @minor: Minor rev. (0, 1, ...) | |
e775fb93 BH |
187 | * @i2c_adap: I2C adapter for on-board peripherals |
188 | * @i2c_data: Data for bit-banging algorithm | |
3759433d BH |
189 | * @hwmon_client: I2C client for hardware monitor |
190 | * @ioexp_client: I2C client for power/port control | |
191 | */ | |
192 | struct falcon_board { | |
44838a44 | 193 | const struct falcon_board_type *type; |
3759433d BH |
194 | int major; |
195 | int minor; | |
e775fb93 BH |
196 | struct i2c_adapter i2c_adap; |
197 | struct i2c_algo_bit_data i2c_data; | |
3759433d BH |
198 | struct i2c_client *hwmon_client, *ioexp_client; |
199 | }; | |
200 | ||
45a3fd55 BH |
201 | /** |
202 | * struct falcon_spi_device - a Falcon SPI (Serial Peripheral Interface) device | |
203 | * @device_id: Controller's id for the device | |
204 | * @size: Size (in bytes) | |
205 | * @addr_len: Number of address bytes in read/write commands | |
206 | * @munge_address: Flag whether addresses should be munged. | |
207 | * Some devices with 9-bit addresses (e.g. AT25040A EEPROM) | |
208 | * use bit 3 of the command byte as address bit A8, rather | |
209 | * than having a two-byte address. If this flag is set, then | |
210 | * commands should be munged in this way. | |
211 | * @erase_command: Erase command (or 0 if sector erase not needed). | |
212 | * @erase_size: Erase sector size (in bytes) | |
213 | * Erase commands affect sectors with this size and alignment. | |
214 | * This must be a power of two. | |
215 | * @block_size: Write block size (in bytes). | |
216 | * Write commands are limited to blocks with this size and alignment. | |
217 | */ | |
218 | struct falcon_spi_device { | |
219 | int device_id; | |
220 | unsigned int size; | |
221 | unsigned int addr_len; | |
222 | unsigned int munge_address:1; | |
223 | u8 erase_command; | |
224 | unsigned int erase_size; | |
225 | unsigned int block_size; | |
226 | }; | |
227 | ||
228 | static inline bool falcon_spi_present(const struct falcon_spi_device *spi) | |
229 | { | |
230 | return spi->size != 0; | |
231 | } | |
232 | ||
cd0ecc9a | 233 | enum { |
e4d112e4 | 234 | FALCON_STAT_tx_bytes = GENERIC_STAT_COUNT, |
cd0ecc9a BH |
235 | FALCON_STAT_tx_packets, |
236 | FALCON_STAT_tx_pause, | |
237 | FALCON_STAT_tx_control, | |
238 | FALCON_STAT_tx_unicast, | |
239 | FALCON_STAT_tx_multicast, | |
240 | FALCON_STAT_tx_broadcast, | |
241 | FALCON_STAT_tx_lt64, | |
242 | FALCON_STAT_tx_64, | |
243 | FALCON_STAT_tx_65_to_127, | |
244 | FALCON_STAT_tx_128_to_255, | |
245 | FALCON_STAT_tx_256_to_511, | |
246 | FALCON_STAT_tx_512_to_1023, | |
247 | FALCON_STAT_tx_1024_to_15xx, | |
248 | FALCON_STAT_tx_15xx_to_jumbo, | |
249 | FALCON_STAT_tx_gtjumbo, | |
250 | FALCON_STAT_tx_non_tcpudp, | |
251 | FALCON_STAT_tx_mac_src_error, | |
252 | FALCON_STAT_tx_ip_src_error, | |
253 | FALCON_STAT_rx_bytes, | |
254 | FALCON_STAT_rx_good_bytes, | |
255 | FALCON_STAT_rx_bad_bytes, | |
256 | FALCON_STAT_rx_packets, | |
257 | FALCON_STAT_rx_good, | |
258 | FALCON_STAT_rx_bad, | |
259 | FALCON_STAT_rx_pause, | |
260 | FALCON_STAT_rx_control, | |
261 | FALCON_STAT_rx_unicast, | |
262 | FALCON_STAT_rx_multicast, | |
263 | FALCON_STAT_rx_broadcast, | |
264 | FALCON_STAT_rx_lt64, | |
265 | FALCON_STAT_rx_64, | |
266 | FALCON_STAT_rx_65_to_127, | |
267 | FALCON_STAT_rx_128_to_255, | |
268 | FALCON_STAT_rx_256_to_511, | |
269 | FALCON_STAT_rx_512_to_1023, | |
270 | FALCON_STAT_rx_1024_to_15xx, | |
271 | FALCON_STAT_rx_15xx_to_jumbo, | |
272 | FALCON_STAT_rx_gtjumbo, | |
273 | FALCON_STAT_rx_bad_lt64, | |
274 | FALCON_STAT_rx_bad_gtjumbo, | |
275 | FALCON_STAT_rx_overflow, | |
276 | FALCON_STAT_rx_symbol_error, | |
277 | FALCON_STAT_rx_align_error, | |
278 | FALCON_STAT_rx_length_error, | |
279 | FALCON_STAT_rx_internal_error, | |
280 | FALCON_STAT_rx_nodesc_drop_cnt, | |
281 | FALCON_STAT_COUNT | |
282 | }; | |
283 | ||
5c16a96c BH |
284 | /** |
285 | * struct falcon_nic_data - Falcon NIC state | |
8986352a | 286 | * @pci_dev2: Secondary function of Falcon A |
3759433d | 287 | * @board: Board state and functions |
cd0ecc9a | 288 | * @stats: Hardware statistics |
55edc6e6 BH |
289 | * @stats_disable_count: Nest count for disabling statistics fetches |
290 | * @stats_pending: Is there a pending DMA of MAC statistics. | |
291 | * @stats_timer: A timer for regularly fetching MAC statistics. | |
4de92180 BH |
292 | * @spi_flash: SPI flash device |
293 | * @spi_eeprom: SPI EEPROM device | |
294 | * @spi_lock: SPI bus lock | |
4833f02a | 295 | * @mdio_lock: MDIO bus lock |
cef68bde | 296 | * @xmac_poll_required: XMAC link state needs polling |
5c16a96c BH |
297 | */ |
298 | struct falcon_nic_data { | |
299 | struct pci_dev *pci_dev2; | |
3759433d | 300 | struct falcon_board board; |
cd0ecc9a | 301 | u64 stats[FALCON_STAT_COUNT]; |
55edc6e6 BH |
302 | unsigned int stats_disable_count; |
303 | bool stats_pending; | |
304 | struct timer_list stats_timer; | |
ecd0a6f0 BH |
305 | struct falcon_spi_device spi_flash; |
306 | struct falcon_spi_device spi_eeprom; | |
4de92180 | 307 | struct mutex spi_lock; |
4833f02a | 308 | struct mutex mdio_lock; |
cef68bde | 309 | bool xmac_poll_required; |
5c16a96c BH |
310 | }; |
311 | ||
278c0621 BH |
312 | static inline struct falcon_board *falcon_board(struct efx_nic *efx) |
313 | { | |
3759433d BH |
314 | struct falcon_nic_data *data = efx->nic_data; |
315 | return &data->board; | |
278c0621 BH |
316 | } |
317 | ||
cd0ecc9a | 318 | enum { |
e4d112e4 | 319 | SIENA_STAT_tx_bytes = GENERIC_STAT_COUNT, |
cd0ecc9a BH |
320 | SIENA_STAT_tx_good_bytes, |
321 | SIENA_STAT_tx_bad_bytes, | |
322 | SIENA_STAT_tx_packets, | |
323 | SIENA_STAT_tx_bad, | |
324 | SIENA_STAT_tx_pause, | |
325 | SIENA_STAT_tx_control, | |
326 | SIENA_STAT_tx_unicast, | |
327 | SIENA_STAT_tx_multicast, | |
328 | SIENA_STAT_tx_broadcast, | |
329 | SIENA_STAT_tx_lt64, | |
330 | SIENA_STAT_tx_64, | |
331 | SIENA_STAT_tx_65_to_127, | |
332 | SIENA_STAT_tx_128_to_255, | |
333 | SIENA_STAT_tx_256_to_511, | |
334 | SIENA_STAT_tx_512_to_1023, | |
335 | SIENA_STAT_tx_1024_to_15xx, | |
336 | SIENA_STAT_tx_15xx_to_jumbo, | |
337 | SIENA_STAT_tx_gtjumbo, | |
338 | SIENA_STAT_tx_collision, | |
339 | SIENA_STAT_tx_single_collision, | |
340 | SIENA_STAT_tx_multiple_collision, | |
341 | SIENA_STAT_tx_excessive_collision, | |
342 | SIENA_STAT_tx_deferred, | |
343 | SIENA_STAT_tx_late_collision, | |
344 | SIENA_STAT_tx_excessive_deferred, | |
345 | SIENA_STAT_tx_non_tcpudp, | |
346 | SIENA_STAT_tx_mac_src_error, | |
347 | SIENA_STAT_tx_ip_src_error, | |
348 | SIENA_STAT_rx_bytes, | |
349 | SIENA_STAT_rx_good_bytes, | |
350 | SIENA_STAT_rx_bad_bytes, | |
351 | SIENA_STAT_rx_packets, | |
352 | SIENA_STAT_rx_good, | |
353 | SIENA_STAT_rx_bad, | |
354 | SIENA_STAT_rx_pause, | |
355 | SIENA_STAT_rx_control, | |
356 | SIENA_STAT_rx_unicast, | |
357 | SIENA_STAT_rx_multicast, | |
358 | SIENA_STAT_rx_broadcast, | |
359 | SIENA_STAT_rx_lt64, | |
360 | SIENA_STAT_rx_64, | |
361 | SIENA_STAT_rx_65_to_127, | |
362 | SIENA_STAT_rx_128_to_255, | |
363 | SIENA_STAT_rx_256_to_511, | |
364 | SIENA_STAT_rx_512_to_1023, | |
365 | SIENA_STAT_rx_1024_to_15xx, | |
366 | SIENA_STAT_rx_15xx_to_jumbo, | |
367 | SIENA_STAT_rx_gtjumbo, | |
368 | SIENA_STAT_rx_bad_gtjumbo, | |
369 | SIENA_STAT_rx_overflow, | |
370 | SIENA_STAT_rx_false_carrier, | |
371 | SIENA_STAT_rx_symbol_error, | |
372 | SIENA_STAT_rx_align_error, | |
373 | SIENA_STAT_rx_length_error, | |
374 | SIENA_STAT_rx_internal_error, | |
375 | SIENA_STAT_rx_nodesc_drop_cnt, | |
376 | SIENA_STAT_COUNT | |
377 | }; | |
378 | ||
8880f4ec BH |
379 | /** |
380 | * struct siena_nic_data - Siena NIC state | |
2dc313ec | 381 | * @efx: Pointer back to main interface structure |
8880f4ec | 382 | * @wol_filter_id: Wake-on-LAN packet filter id |
cd0ecc9a | 383 | * @stats: Hardware statistics |
2dc313ec SS |
384 | * @vf_buftbl_base: The zeroth buffer table index used to back VF queues. |
385 | * @vfdi_status: Common VFDI status page to be dmad to VF address space. | |
386 | * @local_addr_list: List of local addresses. Protected by %local_lock. | |
387 | * @local_page_list: List of DMA addressable pages used to broadcast | |
388 | * %local_addr_list. Protected by %local_lock. | |
389 | * @local_lock: Mutex protecting %local_addr_list and %local_page_list. | |
390 | * @peer_work: Work item to broadcast peer addresses to VMs. | |
8880f4ec BH |
391 | */ |
392 | struct siena_nic_data { | |
2dc313ec | 393 | struct efx_nic *efx; |
8880f4ec | 394 | int wol_filter_id; |
cd0ecc9a | 395 | u64 stats[SIENA_STAT_COUNT]; |
2dc313ec SS |
396 | #ifdef CONFIG_SFC_SRIOV |
397 | struct efx_channel *vfdi_channel; | |
398 | unsigned vf_buftbl_base; | |
399 | struct efx_buffer vfdi_status; | |
400 | struct list_head local_addr_list; | |
401 | struct list_head local_page_list; | |
402 | struct mutex local_lock; | |
403 | struct work_struct peer_work; | |
404 | #endif | |
8880f4ec BH |
405 | }; |
406 | ||
8127d661 | 407 | enum { |
e4d112e4 | 408 | EF10_STAT_tx_bytes = GENERIC_STAT_COUNT, |
8127d661 BH |
409 | EF10_STAT_tx_packets, |
410 | EF10_STAT_tx_pause, | |
411 | EF10_STAT_tx_control, | |
412 | EF10_STAT_tx_unicast, | |
413 | EF10_STAT_tx_multicast, | |
414 | EF10_STAT_tx_broadcast, | |
415 | EF10_STAT_tx_lt64, | |
416 | EF10_STAT_tx_64, | |
417 | EF10_STAT_tx_65_to_127, | |
418 | EF10_STAT_tx_128_to_255, | |
419 | EF10_STAT_tx_256_to_511, | |
420 | EF10_STAT_tx_512_to_1023, | |
421 | EF10_STAT_tx_1024_to_15xx, | |
422 | EF10_STAT_tx_15xx_to_jumbo, | |
423 | EF10_STAT_rx_bytes, | |
424 | EF10_STAT_rx_bytes_minus_good_bytes, | |
425 | EF10_STAT_rx_good_bytes, | |
426 | EF10_STAT_rx_bad_bytes, | |
427 | EF10_STAT_rx_packets, | |
428 | EF10_STAT_rx_good, | |
429 | EF10_STAT_rx_bad, | |
430 | EF10_STAT_rx_pause, | |
431 | EF10_STAT_rx_control, | |
432 | EF10_STAT_rx_unicast, | |
433 | EF10_STAT_rx_multicast, | |
434 | EF10_STAT_rx_broadcast, | |
435 | EF10_STAT_rx_lt64, | |
436 | EF10_STAT_rx_64, | |
437 | EF10_STAT_rx_65_to_127, | |
438 | EF10_STAT_rx_128_to_255, | |
439 | EF10_STAT_rx_256_to_511, | |
440 | EF10_STAT_rx_512_to_1023, | |
441 | EF10_STAT_rx_1024_to_15xx, | |
442 | EF10_STAT_rx_15xx_to_jumbo, | |
443 | EF10_STAT_rx_gtjumbo, | |
444 | EF10_STAT_rx_bad_gtjumbo, | |
445 | EF10_STAT_rx_overflow, | |
446 | EF10_STAT_rx_align_error, | |
447 | EF10_STAT_rx_length_error, | |
448 | EF10_STAT_rx_nodesc_drops, | |
568d7a00 EC |
449 | EF10_STAT_rx_pm_trunc_bb_overflow, |
450 | EF10_STAT_rx_pm_discard_bb_overflow, | |
451 | EF10_STAT_rx_pm_trunc_vfifo_full, | |
452 | EF10_STAT_rx_pm_discard_vfifo_full, | |
453 | EF10_STAT_rx_pm_trunc_qbb, | |
454 | EF10_STAT_rx_pm_discard_qbb, | |
455 | EF10_STAT_rx_pm_discard_mapping, | |
456 | EF10_STAT_rx_dp_q_disabled_packets, | |
457 | EF10_STAT_rx_dp_di_dropped_packets, | |
458 | EF10_STAT_rx_dp_streaming_packets, | |
79ac47ae SS |
459 | EF10_STAT_rx_dp_hlb_fetch, |
460 | EF10_STAT_rx_dp_hlb_wait, | |
8127d661 BH |
461 | EF10_STAT_COUNT |
462 | }; | |
463 | ||
183233be BH |
464 | /* Maximum number of TX PIO buffers we may allocate to a function. |
465 | * This matches the total number of buffers on each SFC9100-family | |
466 | * controller. | |
467 | */ | |
468 | #define EF10_TX_PIOBUF_COUNT 16 | |
469 | ||
8127d661 BH |
470 | /** |
471 | * struct efx_ef10_nic_data - EF10 architecture NIC state | |
472 | * @mcdi_buf: DMA buffer for MCDI | |
473 | * @warm_boot_count: Last seen MC warm boot count | |
474 | * @vi_base: Absolute index of first VI in this function | |
475 | * @n_allocated_vis: Number of VIs allocated to this function | |
476 | * @must_realloc_vis: Flag: VIs have yet to be reallocated after MC reboot | |
477 | * @must_restore_filters: Flag: filters have yet to be restored after MC reboot | |
183233be BH |
478 | * @n_piobufs: Number of PIO buffers allocated to this function |
479 | * @wc_membase: Base address of write-combining mapping of the memory BAR | |
480 | * @pio_write_base: Base address for writing PIO buffers | |
481 | * @pio_write_vi_base: Relative VI number for @pio_write_base | |
482 | * @piobuf_handle: Handle of each PIO buffer allocated | |
483 | * @must_restore_piobufs: Flag: PIO buffers have yet to be restored after MC | |
484 | * reboot | |
8127d661 BH |
485 | * @rx_rss_context: Firmware handle for our RSS context |
486 | * @stats: Hardware statistics | |
487 | * @workaround_35388: Flag: firmware supports workaround for bug 35388 | |
a915ccc9 BH |
488 | * @must_check_datapath_caps: Flag: @datapath_caps needs to be revalidated |
489 | * after MC reboot | |
8127d661 BH |
490 | * @datapath_caps: Capabilities of datapath firmware (FLAGS1 field of |
491 | * %MC_CMD_GET_CAPABILITIES response) | |
492 | */ | |
493 | struct efx_ef10_nic_data { | |
494 | struct efx_buffer mcdi_buf; | |
495 | u16 warm_boot_count; | |
496 | unsigned int vi_base; | |
497 | unsigned int n_allocated_vis; | |
498 | bool must_realloc_vis; | |
499 | bool must_restore_filters; | |
183233be BH |
500 | unsigned int n_piobufs; |
501 | void __iomem *wc_membase, *pio_write_base; | |
502 | unsigned int pio_write_vi_base; | |
503 | unsigned int piobuf_handle[EF10_TX_PIOBUF_COUNT]; | |
504 | bool must_restore_piobufs; | |
8127d661 BH |
505 | u32 rx_rss_context; |
506 | u64 stats[EF10_STAT_COUNT]; | |
507 | bool workaround_35388; | |
a915ccc9 | 508 | bool must_check_datapath_caps; |
8127d661 BH |
509 | u32 datapath_caps; |
510 | }; | |
511 | ||
cd2d5b52 BH |
512 | /* |
513 | * On the SFC9000 family each port is associated with 1 PCI physical | |
514 | * function (PF) handled by sfc and a configurable number of virtual | |
515 | * functions (VFs) that may be handled by some other driver, often in | |
516 | * a VM guest. The queue pointer registers are mapped in both PF and | |
517 | * VF BARs such that an 8K region provides access to a single RX, TX | |
518 | * and event queue (collectively a Virtual Interface, VI or VNIC). | |
519 | * | |
520 | * The PF has access to all 1024 VIs while VFs are mapped to VIs | |
521 | * according to VI_BASE and VI_SCALE: VF i has access to VIs numbered | |
522 | * in range [VI_BASE + i << VI_SCALE, VI_BASE + i + 1 << VI_SCALE). | |
523 | * The number of VIs and the VI_SCALE value are configurable but must | |
524 | * be established at boot time by firmware. | |
525 | */ | |
526 | ||
527 | /* Maximum VI_SCALE parameter supported by Siena */ | |
528 | #define EFX_VI_SCALE_MAX 6 | |
529 | /* Base VI to use for SR-IOV. Must be aligned to (1 << EFX_VI_SCALE_MAX), | |
530 | * so this is the smallest allowed value. */ | |
531 | #define EFX_VI_BASE 128U | |
532 | /* Maximum number of VFs allowed */ | |
533 | #define EFX_VF_COUNT_MAX 127 | |
534 | /* Limit EVQs on VFs to be only 8k to reduce buffer table reservation */ | |
535 | #define EFX_MAX_VF_EVQ_SIZE 8192UL | |
536 | /* The number of buffer table entries reserved for each VI on a VF */ | |
537 | #define EFX_VF_BUFTBL_PER_VI \ | |
538 | ((EFX_MAX_VF_EVQ_SIZE + 2 * EFX_MAX_DMAQ_SIZE) * \ | |
539 | sizeof(efx_qword_t) / EFX_BUF_SIZE) | |
540 | ||
541 | #ifdef CONFIG_SFC_SRIOV | |
542 | ||
d98a4ffe | 543 | /* SIENA */ |
327c685e | 544 | static inline bool efx_siena_sriov_wanted(struct efx_nic *efx) |
cd2d5b52 BH |
545 | { |
546 | return efx->vf_count != 0; | |
547 | } | |
327c685e SS |
548 | |
549 | static inline bool efx_siena_sriov_enabled(struct efx_nic *efx) | |
cd2d5b52 BH |
550 | { |
551 | return efx->vf_init_count != 0; | |
552 | } | |
327c685e | 553 | |
cd2d5b52 BH |
554 | static inline unsigned int efx_vf_size(struct efx_nic *efx) |
555 | { | |
556 | return 1 << efx->vi_scale; | |
557 | } | |
558 | ||
00aef986 | 559 | int efx_init_sriov(void); |
327c685e SS |
560 | void efx_siena_sriov_probe(struct efx_nic *efx); |
561 | int efx_siena_sriov_init(struct efx_nic *efx); | |
562 | void efx_siena_sriov_mac_address_changed(struct efx_nic *efx); | |
563 | void efx_siena_sriov_tx_flush_done(struct efx_nic *efx, efx_qword_t *event); | |
564 | void efx_siena_sriov_rx_flush_done(struct efx_nic *efx, efx_qword_t *event); | |
565 | void efx_siena_sriov_event(struct efx_channel *channel, efx_qword_t *event); | |
566 | void efx_siena_sriov_desc_fetch_err(struct efx_nic *efx, unsigned dmaq); | |
567 | void efx_siena_sriov_flr(struct efx_nic *efx, unsigned flr); | |
568 | void efx_siena_sriov_reset(struct efx_nic *efx); | |
569 | void efx_siena_sriov_fini(struct efx_nic *efx); | |
00aef986 | 570 | void efx_fini_sriov(void); |
cd2d5b52 | 571 | |
d98a4ffe SS |
572 | /* EF10 */ |
573 | static inline bool efx_ef10_sriov_wanted(struct efx_nic *efx) { return false; } | |
574 | static inline int efx_ef10_sriov_init(struct efx_nic *efx) { return -EOPNOTSUPP; } | |
575 | static inline void efx_ef10_sriov_mac_address_changed(struct efx_nic *efx) {} | |
576 | static inline void efx_ef10_sriov_reset(struct efx_nic *efx) {} | |
577 | static inline void efx_ef10_sriov_fini(struct efx_nic *efx) {} | |
578 | ||
cd2d5b52 BH |
579 | #else |
580 | ||
d98a4ffe | 581 | /* SIENA */ |
327c685e SS |
582 | static inline bool efx_siena_sriov_wanted(struct efx_nic *efx) { return false; } |
583 | static inline bool efx_siena_sriov_enabled(struct efx_nic *efx) { return false; } | |
cd2d5b52 | 584 | static inline unsigned int efx_vf_size(struct efx_nic *efx) { return 0; } |
cd2d5b52 | 585 | static inline int efx_init_sriov(void) { return 0; } |
327c685e SS |
586 | static inline void efx_siena_sriov_probe(struct efx_nic *efx) {} |
587 | static inline int efx_siena_sriov_init(struct efx_nic *efx) { return -EOPNOTSUPP; } | |
588 | static inline void efx_siena_sriov_mac_address_changed(struct efx_nic *efx) {} | |
589 | static inline void efx_siena_sriov_tx_flush_done(struct efx_nic *efx, | |
590 | efx_qword_t *event) {} | |
591 | static inline void efx_siena_sriov_rx_flush_done(struct efx_nic *efx, | |
592 | efx_qword_t *event) {} | |
593 | static inline void efx_siena_sriov_event(struct efx_channel *channel, | |
594 | efx_qword_t *event) {} | |
595 | static inline void efx_siena_sriov_desc_fetch_err(struct efx_nic *efx, | |
596 | unsigned dmaq) {} | |
597 | static inline void efx_siena_sriov_flr(struct efx_nic *efx, unsigned flr) {} | |
598 | static inline void efx_siena_sriov_reset(struct efx_nic *efx) {} | |
599 | static inline void efx_siena_sriov_fini(struct efx_nic *efx) {} | |
cd2d5b52 BH |
600 | static inline void efx_fini_sriov(void) {} |
601 | ||
d98a4ffe SS |
602 | /* EF10 */ |
603 | static inline bool efx_ef10_sriov_wanted(struct efx_nic *efx) { return false; } | |
604 | static inline int efx_ef10_sriov_init(struct efx_nic *efx) { return -EOPNOTSUPP; } | |
605 | static inline void efx_ef10_sriov_mac_address_changed(struct efx_nic *efx) {} | |
606 | static inline void efx_ef10_sriov_reset(struct efx_nic *efx) {} | |
607 | static inline void efx_ef10_sriov_fini(struct efx_nic *efx) {} | |
608 | ||
cd2d5b52 BH |
609 | #endif |
610 | ||
d98a4ffe SS |
611 | /* FALCON */ |
612 | static inline bool efx_falcon_sriov_wanted(struct efx_nic *efx) { return false; } | |
613 | static inline int efx_falcon_sriov_init(struct efx_nic *efx) { return -EOPNOTSUPP; } | |
614 | static inline void efx_falcon_sriov_mac_address_changed(struct efx_nic *efx) {} | |
615 | static inline void efx_falcon_sriov_reset(struct efx_nic *efx) {} | |
616 | static inline void efx_falcon_sriov_fini(struct efx_nic *efx) {} | |
617 | ||
327c685e SS |
618 | int efx_siena_sriov_set_vf_mac(struct net_device *dev, int vf, u8 *mac); |
619 | int efx_siena_sriov_set_vf_vlan(struct net_device *dev, int vf, | |
620 | u16 vlan, u8 qos); | |
621 | int efx_siena_sriov_get_vf_config(struct net_device *dev, int vf, | |
622 | struct ifla_vf_info *ivf); | |
623 | int efx_siena_sriov_set_vf_spoofchk(struct net_device *net_dev, int vf, | |
624 | bool spoofchk); | |
cd2d5b52 | 625 | |
7c236c43 | 626 | struct ethtool_ts_info; |
ac36baf8 BH |
627 | int efx_ptp_probe(struct efx_nic *efx, struct efx_channel *channel); |
628 | void efx_ptp_defer_probe_with_channel(struct efx_nic *efx); | |
629 | void efx_ptp_remove(struct efx_nic *efx); | |
433dc9b3 BH |
630 | int efx_ptp_set_ts_config(struct efx_nic *efx, struct ifreq *ifr); |
631 | int efx_ptp_get_ts_config(struct efx_nic *efx, struct ifreq *ifr); | |
00aef986 JP |
632 | void efx_ptp_get_ts_info(struct efx_nic *efx, struct ethtool_ts_info *ts_info); |
633 | bool efx_ptp_is_ptp_tx(struct efx_nic *efx, struct sk_buff *skb); | |
9ec06595 DP |
634 | int efx_ptp_get_mode(struct efx_nic *efx); |
635 | int efx_ptp_change_mode(struct efx_nic *efx, bool enable_wanted, | |
636 | unsigned int new_mode); | |
00aef986 JP |
637 | int efx_ptp_tx(struct efx_nic *efx, struct sk_buff *skb); |
638 | void efx_ptp_event(struct efx_nic *efx, efx_qword_t *ev); | |
99691c4a BH |
639 | size_t efx_ptp_describe_stats(struct efx_nic *efx, u8 *strings); |
640 | size_t efx_ptp_update_stats(struct efx_nic *efx, u64 *stats); | |
bd9a265d JC |
641 | void efx_time_sync_event(struct efx_channel *channel, efx_qword_t *ev); |
642 | void __efx_rx_skb_attach_timestamp(struct efx_channel *channel, | |
643 | struct sk_buff *skb); | |
644 | static inline void efx_rx_skb_attach_timestamp(struct efx_channel *channel, | |
645 | struct sk_buff *skb) | |
646 | { | |
647 | if (channel->sync_events_state == SYNC_EVENTS_VALID) | |
648 | __efx_rx_skb_attach_timestamp(channel, skb); | |
649 | } | |
2ea4dc28 AR |
650 | void efx_ptp_start_datapath(struct efx_nic *efx); |
651 | void efx_ptp_stop_datapath(struct efx_nic *efx); | |
7c236c43 | 652 | |
6c8c2513 | 653 | extern const struct efx_nic_type falcon_a1_nic_type; |
654 | extern const struct efx_nic_type falcon_b0_nic_type; | |
655 | extern const struct efx_nic_type siena_a0_nic_type; | |
8127d661 | 656 | extern const struct efx_nic_type efx_hunt_a0_nic_type; |
8ceee660 BH |
657 | |
658 | /************************************************************************** | |
659 | * | |
660 | * Externs | |
661 | * | |
662 | ************************************************************************** | |
663 | */ | |
664 | ||
00aef986 | 665 | int falcon_probe_board(struct efx_nic *efx, u16 revision_info); |
5087b54d | 666 | |
8ceee660 | 667 | /* TX data path */ |
86094f7f BH |
668 | static inline int efx_nic_probe_tx(struct efx_tx_queue *tx_queue) |
669 | { | |
670 | return tx_queue->efx->type->tx_probe(tx_queue); | |
671 | } | |
672 | static inline void efx_nic_init_tx(struct efx_tx_queue *tx_queue) | |
673 | { | |
674 | tx_queue->efx->type->tx_init(tx_queue); | |
675 | } | |
676 | static inline void efx_nic_remove_tx(struct efx_tx_queue *tx_queue) | |
677 | { | |
678 | tx_queue->efx->type->tx_remove(tx_queue); | |
679 | } | |
680 | static inline void efx_nic_push_buffers(struct efx_tx_queue *tx_queue) | |
681 | { | |
682 | tx_queue->efx->type->tx_write(tx_queue); | |
683 | } | |
8ceee660 BH |
684 | |
685 | /* RX data path */ | |
86094f7f BH |
686 | static inline int efx_nic_probe_rx(struct efx_rx_queue *rx_queue) |
687 | { | |
688 | return rx_queue->efx->type->rx_probe(rx_queue); | |
689 | } | |
690 | static inline void efx_nic_init_rx(struct efx_rx_queue *rx_queue) | |
691 | { | |
692 | rx_queue->efx->type->rx_init(rx_queue); | |
693 | } | |
694 | static inline void efx_nic_remove_rx(struct efx_rx_queue *rx_queue) | |
695 | { | |
696 | rx_queue->efx->type->rx_remove(rx_queue); | |
697 | } | |
698 | static inline void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue) | |
699 | { | |
700 | rx_queue->efx->type->rx_write(rx_queue); | |
701 | } | |
702 | static inline void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue) | |
703 | { | |
704 | rx_queue->efx->type->rx_defer_refill(rx_queue); | |
705 | } | |
8ceee660 BH |
706 | |
707 | /* Event data path */ | |
86094f7f BH |
708 | static inline int efx_nic_probe_eventq(struct efx_channel *channel) |
709 | { | |
710 | return channel->efx->type->ev_probe(channel); | |
711 | } | |
261e4d96 | 712 | static inline int efx_nic_init_eventq(struct efx_channel *channel) |
86094f7f | 713 | { |
261e4d96 | 714 | return channel->efx->type->ev_init(channel); |
86094f7f BH |
715 | } |
716 | static inline void efx_nic_fini_eventq(struct efx_channel *channel) | |
717 | { | |
718 | channel->efx->type->ev_fini(channel); | |
719 | } | |
720 | static inline void efx_nic_remove_eventq(struct efx_channel *channel) | |
721 | { | |
722 | channel->efx->type->ev_remove(channel); | |
723 | } | |
724 | static inline int | |
725 | efx_nic_process_eventq(struct efx_channel *channel, int quota) | |
726 | { | |
727 | return channel->efx->type->ev_process(channel, quota); | |
728 | } | |
729 | static inline void efx_nic_eventq_read_ack(struct efx_channel *channel) | |
730 | { | |
731 | channel->efx->type->ev_read_ack(channel); | |
732 | } | |
00aef986 | 733 | void efx_nic_event_test_start(struct efx_channel *channel); |
86094f7f BH |
734 | |
735 | /* Falcon/Siena queue operations */ | |
00aef986 JP |
736 | int efx_farch_tx_probe(struct efx_tx_queue *tx_queue); |
737 | void efx_farch_tx_init(struct efx_tx_queue *tx_queue); | |
738 | void efx_farch_tx_fini(struct efx_tx_queue *tx_queue); | |
739 | void efx_farch_tx_remove(struct efx_tx_queue *tx_queue); | |
740 | void efx_farch_tx_write(struct efx_tx_queue *tx_queue); | |
741 | int efx_farch_rx_probe(struct efx_rx_queue *rx_queue); | |
742 | void efx_farch_rx_init(struct efx_rx_queue *rx_queue); | |
743 | void efx_farch_rx_fini(struct efx_rx_queue *rx_queue); | |
744 | void efx_farch_rx_remove(struct efx_rx_queue *rx_queue); | |
745 | void efx_farch_rx_write(struct efx_rx_queue *rx_queue); | |
746 | void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue); | |
747 | int efx_farch_ev_probe(struct efx_channel *channel); | |
748 | int efx_farch_ev_init(struct efx_channel *channel); | |
749 | void efx_farch_ev_fini(struct efx_channel *channel); | |
750 | void efx_farch_ev_remove(struct efx_channel *channel); | |
751 | int efx_farch_ev_process(struct efx_channel *channel, int quota); | |
752 | void efx_farch_ev_read_ack(struct efx_channel *channel); | |
753 | void efx_farch_ev_test_generate(struct efx_channel *channel); | |
86094f7f | 754 | |
add72477 | 755 | /* Falcon/Siena filter operations */ |
00aef986 JP |
756 | int efx_farch_filter_table_probe(struct efx_nic *efx); |
757 | void efx_farch_filter_table_restore(struct efx_nic *efx); | |
758 | void efx_farch_filter_table_remove(struct efx_nic *efx); | |
759 | void efx_farch_filter_update_rx_scatter(struct efx_nic *efx); | |
760 | s32 efx_farch_filter_insert(struct efx_nic *efx, struct efx_filter_spec *spec, | |
761 | bool replace); | |
762 | int efx_farch_filter_remove_safe(struct efx_nic *efx, | |
763 | enum efx_filter_priority priority, | |
764 | u32 filter_id); | |
765 | int efx_farch_filter_get_safe(struct efx_nic *efx, | |
766 | enum efx_filter_priority priority, u32 filter_id, | |
767 | struct efx_filter_spec *); | |
fbd79120 BH |
768 | int efx_farch_filter_clear_rx(struct efx_nic *efx, |
769 | enum efx_filter_priority priority); | |
00aef986 JP |
770 | u32 efx_farch_filter_count_rx_used(struct efx_nic *efx, |
771 | enum efx_filter_priority priority); | |
772 | u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx); | |
773 | s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx, | |
774 | enum efx_filter_priority priority, u32 *buf, | |
775 | u32 size); | |
add72477 | 776 | #ifdef CONFIG_RFS_ACCEL |
00aef986 JP |
777 | s32 efx_farch_filter_rfs_insert(struct efx_nic *efx, |
778 | struct efx_filter_spec *spec); | |
779 | bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id, | |
780 | unsigned int index); | |
add72477 | 781 | #endif |
00aef986 | 782 | void efx_farch_filter_sync_rx_mode(struct efx_nic *efx); |
add72477 | 783 | |
00aef986 | 784 | bool efx_nic_event_present(struct efx_channel *channel); |
8ceee660 | 785 | |
b7f514af BH |
786 | /* Some statistics are computed as A - B where A and B each increase |
787 | * linearly with some hardware counter(s) and the counters are read | |
788 | * asynchronously. If the counters contributing to B are always read | |
789 | * after those contributing to A, the computed value may be lower than | |
790 | * the true value by some variable amount, and may decrease between | |
791 | * subsequent computations. | |
792 | * | |
793 | * We should never allow statistics to decrease or to exceed the true | |
794 | * value. Since the computed value will never be greater than the | |
795 | * true value, we can achieve this by only storing the computed value | |
796 | * when it increases. | |
797 | */ | |
798 | static inline void efx_update_diff_stat(u64 *stat, u64 diff) | |
799 | { | |
800 | if ((s64)(diff - *stat) > 0) | |
801 | *stat = diff; | |
802 | } | |
803 | ||
86094f7f | 804 | /* Interrupts */ |
00aef986 JP |
805 | int efx_nic_init_interrupt(struct efx_nic *efx); |
806 | void efx_nic_irq_test_start(struct efx_nic *efx); | |
807 | void efx_nic_fini_interrupt(struct efx_nic *efx); | |
86094f7f BH |
808 | |
809 | /* Falcon/Siena interrupts */ | |
00aef986 JP |
810 | void efx_farch_irq_enable_master(struct efx_nic *efx); |
811 | void efx_farch_irq_test_generate(struct efx_nic *efx); | |
812 | void efx_farch_irq_disable_master(struct efx_nic *efx); | |
813 | irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id); | |
814 | irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id); | |
815 | irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx); | |
152b6a62 | 816 | |
eee6f6a9 BH |
817 | static inline int efx_nic_event_test_irq_cpu(struct efx_channel *channel) |
818 | { | |
dd40781e | 819 | return ACCESS_ONCE(channel->event_test_cpu); |
eee6f6a9 BH |
820 | } |
821 | static inline int efx_nic_irq_test_irq_cpu(struct efx_nic *efx) | |
822 | { | |
823 | return ACCESS_ONCE(efx->last_irq_cpu); | |
824 | } | |
825 | ||
8ceee660 | 826 | /* Global Resources */ |
00aef986 JP |
827 | int efx_nic_flush_queues(struct efx_nic *efx); |
828 | void siena_prepare_flush(struct efx_nic *efx); | |
829 | int efx_farch_fini_dmaq(struct efx_nic *efx); | |
e283546c | 830 | void efx_farch_finish_flr(struct efx_nic *efx); |
00aef986 JP |
831 | void siena_finish_flush(struct efx_nic *efx); |
832 | void falcon_start_nic_stats(struct efx_nic *efx); | |
833 | void falcon_stop_nic_stats(struct efx_nic *efx); | |
834 | int falcon_reset_xaui(struct efx_nic *efx); | |
835 | void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw); | |
836 | void efx_farch_init_common(struct efx_nic *efx); | |
837 | void efx_ef10_handle_drain_event(struct efx_nic *efx); | |
00aef986 | 838 | void efx_farch_rx_push_indir_table(struct efx_nic *efx); |
152b6a62 BH |
839 | |
840 | int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer, | |
0d19a540 | 841 | unsigned int len, gfp_t gfp_flags); |
152b6a62 | 842 | void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer); |
8ceee660 | 843 | |
8c8661e4 | 844 | /* Tests */ |
86094f7f | 845 | struct efx_farch_register_test { |
152b6a62 BH |
846 | unsigned address; |
847 | efx_oword_t mask; | |
848 | }; | |
00aef986 JP |
849 | int efx_farch_test_registers(struct efx_nic *efx, |
850 | const struct efx_farch_register_test *regs, | |
851 | size_t n_regs); | |
8c8661e4 | 852 | |
00aef986 JP |
853 | size_t efx_nic_get_regs_len(struct efx_nic *efx); |
854 | void efx_nic_get_regs(struct efx_nic *efx, void *buf); | |
5b98c1bf | 855 | |
00aef986 JP |
856 | size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count, |
857 | const unsigned long *mask, u8 *names); | |
858 | void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count, | |
859 | const unsigned long *mask, u64 *stats, | |
860 | const void *dma_buf, bool accumulate); | |
f8f3b5ae | 861 | void efx_nic_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *stat); |
cd0ecc9a | 862 | |
ab0115fc | 863 | #define EFX_MAX_FLUSH_TIME 5000 |
8ceee660 | 864 | |
00aef986 JP |
865 | void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq, |
866 | efx_qword_t *event); | |
8ceee660 | 867 | |
744093c9 | 868 | #endif /* EFX_NIC_H */ |