Commit | Line | Data |
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d2912cb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
8ceee660 | 2 | /**************************************************************************** |
f7a6d2c4 | 3 | * Driver for Solarflare network controllers and boards |
8ceee660 | 4 | * Copyright 2005-2006 Fen Systems Ltd. |
f7a6d2c4 | 5 | * Copyright 2006-2013 Solarflare Communications Inc. |
8ceee660 BH |
6 | */ |
7 | ||
744093c9 BH |
8 | #ifndef EFX_NIC_H |
9 | #define EFX_NIC_H | |
8ceee660 | 10 | |
9043f48f | 11 | #include "nic_common.h" |
177dfcd8 | 12 | #include "efx.h" |
8ceee660 | 13 | |
00aef986 | 14 | u32 efx_farch_fpga_ver(struct efx_nic *efx); |
152b6a62 | 15 | |
c1c4f453 BH |
16 | enum { |
17 | PHY_TYPE_NONE = 0, | |
18 | PHY_TYPE_TXC43128 = 1, | |
19 | PHY_TYPE_88E1111 = 2, | |
20 | PHY_TYPE_SFX7101 = 3, | |
21 | PHY_TYPE_QT2022C2 = 4, | |
22 | PHY_TYPE_PM8358 = 6, | |
23 | PHY_TYPE_SFT9001A = 8, | |
24 | PHY_TYPE_QT2025C = 9, | |
25 | PHY_TYPE_SFT9001B = 10, | |
26 | }; | |
27 | ||
cd0ecc9a | 28 | enum { |
e4d112e4 | 29 | SIENA_STAT_tx_bytes = GENERIC_STAT_COUNT, |
cd0ecc9a BH |
30 | SIENA_STAT_tx_good_bytes, |
31 | SIENA_STAT_tx_bad_bytes, | |
32 | SIENA_STAT_tx_packets, | |
33 | SIENA_STAT_tx_bad, | |
34 | SIENA_STAT_tx_pause, | |
35 | SIENA_STAT_tx_control, | |
36 | SIENA_STAT_tx_unicast, | |
37 | SIENA_STAT_tx_multicast, | |
38 | SIENA_STAT_tx_broadcast, | |
39 | SIENA_STAT_tx_lt64, | |
40 | SIENA_STAT_tx_64, | |
41 | SIENA_STAT_tx_65_to_127, | |
42 | SIENA_STAT_tx_128_to_255, | |
43 | SIENA_STAT_tx_256_to_511, | |
44 | SIENA_STAT_tx_512_to_1023, | |
45 | SIENA_STAT_tx_1024_to_15xx, | |
46 | SIENA_STAT_tx_15xx_to_jumbo, | |
47 | SIENA_STAT_tx_gtjumbo, | |
48 | SIENA_STAT_tx_collision, | |
49 | SIENA_STAT_tx_single_collision, | |
50 | SIENA_STAT_tx_multiple_collision, | |
51 | SIENA_STAT_tx_excessive_collision, | |
52 | SIENA_STAT_tx_deferred, | |
53 | SIENA_STAT_tx_late_collision, | |
54 | SIENA_STAT_tx_excessive_deferred, | |
55 | SIENA_STAT_tx_non_tcpudp, | |
56 | SIENA_STAT_tx_mac_src_error, | |
57 | SIENA_STAT_tx_ip_src_error, | |
58 | SIENA_STAT_rx_bytes, | |
59 | SIENA_STAT_rx_good_bytes, | |
60 | SIENA_STAT_rx_bad_bytes, | |
61 | SIENA_STAT_rx_packets, | |
62 | SIENA_STAT_rx_good, | |
63 | SIENA_STAT_rx_bad, | |
64 | SIENA_STAT_rx_pause, | |
65 | SIENA_STAT_rx_control, | |
66 | SIENA_STAT_rx_unicast, | |
67 | SIENA_STAT_rx_multicast, | |
68 | SIENA_STAT_rx_broadcast, | |
69 | SIENA_STAT_rx_lt64, | |
70 | SIENA_STAT_rx_64, | |
71 | SIENA_STAT_rx_65_to_127, | |
72 | SIENA_STAT_rx_128_to_255, | |
73 | SIENA_STAT_rx_256_to_511, | |
74 | SIENA_STAT_rx_512_to_1023, | |
75 | SIENA_STAT_rx_1024_to_15xx, | |
76 | SIENA_STAT_rx_15xx_to_jumbo, | |
77 | SIENA_STAT_rx_gtjumbo, | |
78 | SIENA_STAT_rx_bad_gtjumbo, | |
79 | SIENA_STAT_rx_overflow, | |
80 | SIENA_STAT_rx_false_carrier, | |
81 | SIENA_STAT_rx_symbol_error, | |
82 | SIENA_STAT_rx_align_error, | |
83 | SIENA_STAT_rx_length_error, | |
84 | SIENA_STAT_rx_internal_error, | |
85 | SIENA_STAT_rx_nodesc_drop_cnt, | |
86 | SIENA_STAT_COUNT | |
87 | }; | |
88 | ||
8880f4ec BH |
89 | /** |
90 | * struct siena_nic_data - Siena NIC state | |
2dc313ec | 91 | * @efx: Pointer back to main interface structure |
8880f4ec | 92 | * @wol_filter_id: Wake-on-LAN packet filter id |
cd0ecc9a | 93 | * @stats: Hardware statistics |
bf3d0156 | 94 | * @vf: Array of &struct siena_vf objects |
2dc313ec SS |
95 | * @vf_buftbl_base: The zeroth buffer table index used to back VF queues. |
96 | * @vfdi_status: Common VFDI status page to be dmad to VF address space. | |
97 | * @local_addr_list: List of local addresses. Protected by %local_lock. | |
98 | * @local_page_list: List of DMA addressable pages used to broadcast | |
99 | * %local_addr_list. Protected by %local_lock. | |
100 | * @local_lock: Mutex protecting %local_addr_list and %local_page_list. | |
101 | * @peer_work: Work item to broadcast peer addresses to VMs. | |
8880f4ec BH |
102 | */ |
103 | struct siena_nic_data { | |
2dc313ec | 104 | struct efx_nic *efx; |
8880f4ec | 105 | int wol_filter_id; |
cd0ecc9a | 106 | u64 stats[SIENA_STAT_COUNT]; |
2dc313ec | 107 | #ifdef CONFIG_SFC_SRIOV |
bf3d0156 | 108 | struct siena_vf *vf; |
2dc313ec SS |
109 | struct efx_channel *vfdi_channel; |
110 | unsigned vf_buftbl_base; | |
111 | struct efx_buffer vfdi_status; | |
112 | struct list_head local_addr_list; | |
113 | struct list_head local_page_list; | |
114 | struct mutex local_lock; | |
115 | struct work_struct peer_work; | |
116 | #endif | |
8880f4ec BH |
117 | }; |
118 | ||
8127d661 | 119 | enum { |
e80ca013 DP |
120 | EF10_STAT_port_tx_bytes = GENERIC_STAT_COUNT, |
121 | EF10_STAT_port_tx_packets, | |
122 | EF10_STAT_port_tx_pause, | |
123 | EF10_STAT_port_tx_control, | |
124 | EF10_STAT_port_tx_unicast, | |
125 | EF10_STAT_port_tx_multicast, | |
126 | EF10_STAT_port_tx_broadcast, | |
127 | EF10_STAT_port_tx_lt64, | |
128 | EF10_STAT_port_tx_64, | |
129 | EF10_STAT_port_tx_65_to_127, | |
130 | EF10_STAT_port_tx_128_to_255, | |
131 | EF10_STAT_port_tx_256_to_511, | |
132 | EF10_STAT_port_tx_512_to_1023, | |
133 | EF10_STAT_port_tx_1024_to_15xx, | |
134 | EF10_STAT_port_tx_15xx_to_jumbo, | |
135 | EF10_STAT_port_rx_bytes, | |
136 | EF10_STAT_port_rx_bytes_minus_good_bytes, | |
137 | EF10_STAT_port_rx_good_bytes, | |
138 | EF10_STAT_port_rx_bad_bytes, | |
139 | EF10_STAT_port_rx_packets, | |
140 | EF10_STAT_port_rx_good, | |
141 | EF10_STAT_port_rx_bad, | |
142 | EF10_STAT_port_rx_pause, | |
143 | EF10_STAT_port_rx_control, | |
144 | EF10_STAT_port_rx_unicast, | |
145 | EF10_STAT_port_rx_multicast, | |
146 | EF10_STAT_port_rx_broadcast, | |
147 | EF10_STAT_port_rx_lt64, | |
148 | EF10_STAT_port_rx_64, | |
149 | EF10_STAT_port_rx_65_to_127, | |
150 | EF10_STAT_port_rx_128_to_255, | |
151 | EF10_STAT_port_rx_256_to_511, | |
152 | EF10_STAT_port_rx_512_to_1023, | |
153 | EF10_STAT_port_rx_1024_to_15xx, | |
154 | EF10_STAT_port_rx_15xx_to_jumbo, | |
155 | EF10_STAT_port_rx_gtjumbo, | |
156 | EF10_STAT_port_rx_bad_gtjumbo, | |
157 | EF10_STAT_port_rx_overflow, | |
158 | EF10_STAT_port_rx_align_error, | |
159 | EF10_STAT_port_rx_length_error, | |
160 | EF10_STAT_port_rx_nodesc_drops, | |
161 | EF10_STAT_port_rx_pm_trunc_bb_overflow, | |
162 | EF10_STAT_port_rx_pm_discard_bb_overflow, | |
163 | EF10_STAT_port_rx_pm_trunc_vfifo_full, | |
164 | EF10_STAT_port_rx_pm_discard_vfifo_full, | |
165 | EF10_STAT_port_rx_pm_trunc_qbb, | |
166 | EF10_STAT_port_rx_pm_discard_qbb, | |
167 | EF10_STAT_port_rx_pm_discard_mapping, | |
168 | EF10_STAT_port_rx_dp_q_disabled_packets, | |
169 | EF10_STAT_port_rx_dp_di_dropped_packets, | |
170 | EF10_STAT_port_rx_dp_streaming_packets, | |
171 | EF10_STAT_port_rx_dp_hlb_fetch, | |
172 | EF10_STAT_port_rx_dp_hlb_wait, | |
3c36a2ad DP |
173 | EF10_STAT_rx_unicast, |
174 | EF10_STAT_rx_unicast_bytes, | |
175 | EF10_STAT_rx_multicast, | |
176 | EF10_STAT_rx_multicast_bytes, | |
177 | EF10_STAT_rx_broadcast, | |
178 | EF10_STAT_rx_broadcast_bytes, | |
179 | EF10_STAT_rx_bad, | |
180 | EF10_STAT_rx_bad_bytes, | |
181 | EF10_STAT_rx_overflow, | |
182 | EF10_STAT_tx_unicast, | |
183 | EF10_STAT_tx_unicast_bytes, | |
184 | EF10_STAT_tx_multicast, | |
185 | EF10_STAT_tx_multicast_bytes, | |
186 | EF10_STAT_tx_broadcast, | |
187 | EF10_STAT_tx_broadcast_bytes, | |
188 | EF10_STAT_tx_bad, | |
189 | EF10_STAT_tx_bad_bytes, | |
190 | EF10_STAT_tx_overflow, | |
f411b54d EC |
191 | EF10_STAT_V1_COUNT, |
192 | EF10_STAT_fec_uncorrected_errors = EF10_STAT_V1_COUNT, | |
193 | EF10_STAT_fec_corrected_errors, | |
194 | EF10_STAT_fec_corrected_symbols_lane0, | |
195 | EF10_STAT_fec_corrected_symbols_lane1, | |
196 | EF10_STAT_fec_corrected_symbols_lane2, | |
197 | EF10_STAT_fec_corrected_symbols_lane3, | |
2c0b6ee8 BK |
198 | EF10_STAT_ctpio_vi_busy_fallback, |
199 | EF10_STAT_ctpio_long_write_success, | |
200 | EF10_STAT_ctpio_missing_dbell_fail, | |
201 | EF10_STAT_ctpio_overflow_fail, | |
202 | EF10_STAT_ctpio_underflow_fail, | |
203 | EF10_STAT_ctpio_timeout_fail, | |
204 | EF10_STAT_ctpio_noncontig_wr_fail, | |
205 | EF10_STAT_ctpio_frm_clobber_fail, | |
206 | EF10_STAT_ctpio_invalid_wr_fail, | |
207 | EF10_STAT_ctpio_vi_clobber_fallback, | |
208 | EF10_STAT_ctpio_unqualified_fallback, | |
209 | EF10_STAT_ctpio_runt_fallback, | |
210 | EF10_STAT_ctpio_success, | |
211 | EF10_STAT_ctpio_fallback, | |
212 | EF10_STAT_ctpio_poison, | |
213 | EF10_STAT_ctpio_erase, | |
8127d661 BH |
214 | EF10_STAT_COUNT |
215 | }; | |
216 | ||
183233be BH |
217 | /* Maximum number of TX PIO buffers we may allocate to a function. |
218 | * This matches the total number of buffers on each SFC9100-family | |
219 | * controller. | |
220 | */ | |
221 | #define EF10_TX_PIOBUF_COUNT 16 | |
222 | ||
8127d661 BH |
223 | /** |
224 | * struct efx_ef10_nic_data - EF10 architecture NIC state | |
225 | * @mcdi_buf: DMA buffer for MCDI | |
226 | * @warm_boot_count: Last seen MC warm boot count | |
227 | * @vi_base: Absolute index of first VI in this function | |
228 | * @n_allocated_vis: Number of VIs allocated to this function | |
183233be BH |
229 | * @n_piobufs: Number of PIO buffers allocated to this function |
230 | * @wc_membase: Base address of write-combining mapping of the memory BAR | |
231 | * @pio_write_base: Base address for writing PIO buffers | |
232 | * @pio_write_vi_base: Relative VI number for @pio_write_base | |
233 | * @piobuf_handle: Handle of each PIO buffer allocated | |
c634700f | 234 | * @piobuf_size: size of a single PIO buffer |
183233be BH |
235 | * @must_restore_piobufs: Flag: PIO buffers have yet to be restored after MC |
236 | * reboot | |
d3142c19 | 237 | * @mc_stats: Scratch buffer for converting statistics to the kernel's format |
8127d661 BH |
238 | * @stats: Hardware statistics |
239 | * @workaround_35388: Flag: firmware supports workaround for bug 35388 | |
46e612b0 | 240 | * @workaround_26807: Flag: firmware supports workaround for bug 26807 |
539de7c5 | 241 | * @workaround_61265: Flag: firmware supports workaround for bug 61265 |
a915ccc9 BH |
242 | * @must_check_datapath_caps: Flag: @datapath_caps needs to be revalidated |
243 | * after MC reboot | |
8127d661 BH |
244 | * @datapath_caps: Capabilities of datapath firmware (FLAGS1 field of |
245 | * %MC_CMD_GET_CAPABILITIES response) | |
ca889a05 BK |
246 | * @datapath_caps2: Further Capabilities of datapath firmware (FLAGS2 field of |
247 | * %MC_CMD_GET_CAPABILITIES response) | |
8d9f9dd4 DP |
248 | * @rx_dpcpu_fw_id: Firmware ID of the RxDPCPU |
249 | * @tx_dpcpu_fw_id: Firmware ID of the TxDPCPU | |
6d8aaaf6 | 250 | * @must_probe_vswitching: Flag: vswitching has yet to be setup after MC reboot |
1cd9ecbb | 251 | * @pf_index: The number for this PF, or the parent PF if this is a VF |
3c5eb876 SS |
252 | #ifdef CONFIG_SFC_SRIOV |
253 | * @vf: Pointer to VF data structure | |
254 | #endif | |
34813fe2 AR |
255 | * @vport_mac: The MAC address on the vport, only for PFs; VFs will be zero |
256 | * @vlan_list: List of VLANs added over the interface. Serialised by vlan_lock. | |
257 | * @vlan_lock: Lock to serialize access to vlan_list. | |
e5fbd977 JC |
258 | * @udp_tunnels: UDP tunnel port numbers and types. |
259 | * @udp_tunnels_dirty: flag indicating a reboot occurred while pushing | |
260 | * @udp_tunnels to hardware and thus the push must be re-done. | |
261 | * @udp_tunnels_lock: Serialises writes to @udp_tunnels and @udp_tunnels_dirty. | |
8127d661 BH |
262 | */ |
263 | struct efx_ef10_nic_data { | |
264 | struct efx_buffer mcdi_buf; | |
265 | u16 warm_boot_count; | |
266 | unsigned int vi_base; | |
267 | unsigned int n_allocated_vis; | |
183233be BH |
268 | unsigned int n_piobufs; |
269 | void __iomem *wc_membase, *pio_write_base; | |
270 | unsigned int pio_write_vi_base; | |
271 | unsigned int piobuf_handle[EF10_TX_PIOBUF_COUNT]; | |
c634700f | 272 | u16 piobuf_size; |
183233be | 273 | bool must_restore_piobufs; |
d3142c19 | 274 | __le64 *mc_stats; |
8127d661 BH |
275 | u64 stats[EF10_STAT_COUNT]; |
276 | bool workaround_35388; | |
46e612b0 | 277 | bool workaround_26807; |
539de7c5 | 278 | bool workaround_61265; |
a915ccc9 | 279 | bool must_check_datapath_caps; |
8127d661 | 280 | u32 datapath_caps; |
ca889a05 | 281 | u32 datapath_caps2; |
8d9f9dd4 DP |
282 | unsigned int rx_dpcpu_fw_id; |
283 | unsigned int tx_dpcpu_fw_id; | |
6d8aaaf6 | 284 | bool must_probe_vswitching; |
1cd9ecbb | 285 | unsigned int pf_index; |
1d051e00 | 286 | u8 port_id[ETH_ALEN]; |
3c5eb876 | 287 | #ifdef CONFIG_SFC_SRIOV |
88a37de6 | 288 | unsigned int vf_index; |
3c5eb876 SS |
289 | struct ef10_vf *vf; |
290 | #endif | |
291 | u8 vport_mac[ETH_ALEN]; | |
34813fe2 AR |
292 | struct list_head vlan_list; |
293 | struct mutex vlan_lock; | |
e5fbd977 JC |
294 | struct efx_udp_tunnel udp_tunnels[16]; |
295 | bool udp_tunnels_dirty; | |
296 | struct mutex udp_tunnels_lock; | |
50663fe1 | 297 | u64 licensed_features; |
8127d661 BH |
298 | }; |
299 | ||
1679c72c EC |
300 | /* TSOv2 */ |
301 | int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue, struct sk_buff *skb, | |
302 | bool *data_mapped); | |
303 | ||
8127d661 | 304 | extern const struct efx_nic_type efx_hunt_a0_nic_type; |
02246a7f | 305 | extern const struct efx_nic_type efx_hunt_a0_vf_nic_type; |
8ceee660 | 306 | |
00aef986 | 307 | int falcon_probe_board(struct efx_nic *efx, u16 revision_info); |
5087b54d | 308 | |
86094f7f | 309 | /* Falcon/Siena queue operations */ |
00aef986 JP |
310 | int efx_farch_tx_probe(struct efx_tx_queue *tx_queue); |
311 | void efx_farch_tx_init(struct efx_tx_queue *tx_queue); | |
312 | void efx_farch_tx_fini(struct efx_tx_queue *tx_queue); | |
313 | void efx_farch_tx_remove(struct efx_tx_queue *tx_queue); | |
314 | void efx_farch_tx_write(struct efx_tx_queue *tx_queue); | |
e9117e50 BK |
315 | unsigned int efx_farch_tx_limit_len(struct efx_tx_queue *tx_queue, |
316 | dma_addr_t dma_addr, unsigned int len); | |
00aef986 JP |
317 | int efx_farch_rx_probe(struct efx_rx_queue *rx_queue); |
318 | void efx_farch_rx_init(struct efx_rx_queue *rx_queue); | |
319 | void efx_farch_rx_fini(struct efx_rx_queue *rx_queue); | |
320 | void efx_farch_rx_remove(struct efx_rx_queue *rx_queue); | |
321 | void efx_farch_rx_write(struct efx_rx_queue *rx_queue); | |
322 | void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue); | |
323 | int efx_farch_ev_probe(struct efx_channel *channel); | |
324 | int efx_farch_ev_init(struct efx_channel *channel); | |
325 | void efx_farch_ev_fini(struct efx_channel *channel); | |
326 | void efx_farch_ev_remove(struct efx_channel *channel); | |
327 | int efx_farch_ev_process(struct efx_channel *channel, int quota); | |
328 | void efx_farch_ev_read_ack(struct efx_channel *channel); | |
329 | void efx_farch_ev_test_generate(struct efx_channel *channel); | |
86094f7f | 330 | |
add72477 | 331 | /* Falcon/Siena filter operations */ |
00aef986 JP |
332 | int efx_farch_filter_table_probe(struct efx_nic *efx); |
333 | void efx_farch_filter_table_restore(struct efx_nic *efx); | |
334 | void efx_farch_filter_table_remove(struct efx_nic *efx); | |
335 | void efx_farch_filter_update_rx_scatter(struct efx_nic *efx); | |
336 | s32 efx_farch_filter_insert(struct efx_nic *efx, struct efx_filter_spec *spec, | |
337 | bool replace); | |
338 | int efx_farch_filter_remove_safe(struct efx_nic *efx, | |
339 | enum efx_filter_priority priority, | |
340 | u32 filter_id); | |
341 | int efx_farch_filter_get_safe(struct efx_nic *efx, | |
342 | enum efx_filter_priority priority, u32 filter_id, | |
343 | struct efx_filter_spec *); | |
fbd79120 BH |
344 | int efx_farch_filter_clear_rx(struct efx_nic *efx, |
345 | enum efx_filter_priority priority); | |
00aef986 JP |
346 | u32 efx_farch_filter_count_rx_used(struct efx_nic *efx, |
347 | enum efx_filter_priority priority); | |
348 | u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx); | |
349 | s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx, | |
350 | enum efx_filter_priority priority, u32 *buf, | |
351 | u32 size); | |
add72477 | 352 | #ifdef CONFIG_RFS_ACCEL |
00aef986 JP |
353 | bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id, |
354 | unsigned int index); | |
add72477 | 355 | #endif |
00aef986 | 356 | void efx_farch_filter_sync_rx_mode(struct efx_nic *efx); |
add72477 | 357 | |
86094f7f | 358 | /* Falcon/Siena interrupts */ |
00aef986 | 359 | void efx_farch_irq_enable_master(struct efx_nic *efx); |
942e298e | 360 | int efx_farch_irq_test_generate(struct efx_nic *efx); |
00aef986 JP |
361 | void efx_farch_irq_disable_master(struct efx_nic *efx); |
362 | irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id); | |
363 | irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id); | |
364 | irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx); | |
152b6a62 | 365 | |
8ceee660 | 366 | /* Global Resources */ |
00aef986 JP |
367 | void siena_prepare_flush(struct efx_nic *efx); |
368 | int efx_farch_fini_dmaq(struct efx_nic *efx); | |
e283546c | 369 | void efx_farch_finish_flr(struct efx_nic *efx); |
00aef986 JP |
370 | void siena_finish_flush(struct efx_nic *efx); |
371 | void falcon_start_nic_stats(struct efx_nic *efx); | |
372 | void falcon_stop_nic_stats(struct efx_nic *efx); | |
373 | int falcon_reset_xaui(struct efx_nic *efx); | |
374 | void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw); | |
375 | void efx_farch_init_common(struct efx_nic *efx); | |
00aef986 | 376 | void efx_farch_rx_push_indir_table(struct efx_nic *efx); |
a707d188 | 377 | void efx_farch_rx_pull_indir_table(struct efx_nic *efx); |
152b6a62 | 378 | |
8c8661e4 | 379 | /* Tests */ |
86094f7f | 380 | struct efx_farch_register_test { |
152b6a62 BH |
381 | unsigned address; |
382 | efx_oword_t mask; | |
383 | }; | |
e1253f39 | 384 | |
00aef986 JP |
385 | int efx_farch_test_registers(struct efx_nic *efx, |
386 | const struct efx_farch_register_test *regs, | |
387 | size_t n_regs); | |
8c8661e4 | 388 | |
00aef986 JP |
389 | void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq, |
390 | efx_qword_t *event); | |
8ceee660 | 391 | |
744093c9 | 392 | #endif /* EFX_NIC_H */ |