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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
0a6f40c6 | 4 | * Copyright 2005-2011 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | /* Common definitions for all Efx net driver code */ | |
12 | ||
13 | #ifndef EFX_NET_DRIVER_H | |
14 | #define EFX_NET_DRIVER_H | |
15 | ||
8ceee660 BH |
16 | #include <linux/netdevice.h> |
17 | #include <linux/etherdevice.h> | |
18 | #include <linux/ethtool.h> | |
19 | #include <linux/if_vlan.h> | |
90d683af | 20 | #include <linux/timer.h> |
68e7f45e | 21 | #include <linux/mdio.h> |
8ceee660 BH |
22 | #include <linux/list.h> |
23 | #include <linux/pci.h> | |
24 | #include <linux/device.h> | |
25 | #include <linux/highmem.h> | |
26 | #include <linux/workqueue.h> | |
10ed61c4 | 27 | #include <linux/vmalloc.h> |
37b5a603 | 28 | #include <linux/i2c.h> |
8ceee660 BH |
29 | |
30 | #include "enum.h" | |
31 | #include "bitfield.h" | |
8ceee660 | 32 | |
8ceee660 BH |
33 | /************************************************************************** |
34 | * | |
35 | * Build definitions | |
36 | * | |
37 | **************************************************************************/ | |
c5d5f5fd | 38 | |
6d84b986 | 39 | #define EFX_DRIVER_VERSION "3.1" |
8ceee660 | 40 | |
5f3f9d6c | 41 | #ifdef DEBUG |
8ceee660 BH |
42 | #define EFX_BUG_ON_PARANOID(x) BUG_ON(x) |
43 | #define EFX_WARN_ON_PARANOID(x) WARN_ON(x) | |
44 | #else | |
45 | #define EFX_BUG_ON_PARANOID(x) do {} while (0) | |
46 | #define EFX_WARN_ON_PARANOID(x) do {} while (0) | |
47 | #endif | |
48 | ||
8ceee660 BH |
49 | /************************************************************************** |
50 | * | |
51 | * Efx data structures | |
52 | * | |
53 | **************************************************************************/ | |
54 | ||
55 | #define EFX_MAX_CHANNELS 32 | |
8ceee660 BH |
56 | #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS |
57 | ||
a4900ac9 BH |
58 | /* Checksum generation is a per-queue option in hardware, so each |
59 | * queue visible to the networking core is backed by two hardware TX | |
60 | * queues. */ | |
94b274bf BH |
61 | #define EFX_MAX_TX_TC 2 |
62 | #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS) | |
63 | #define EFX_TXQ_TYPE_OFFLOAD 1 /* flag */ | |
64 | #define EFX_TXQ_TYPE_HIGHPRI 2 /* flag */ | |
65 | #define EFX_TXQ_TYPES 4 | |
66 | #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CHANNELS) | |
60ac1065 | 67 | |
8ceee660 BH |
68 | /** |
69 | * struct efx_special_buffer - An Efx special buffer | |
70 | * @addr: CPU base address of the buffer | |
71 | * @dma_addr: DMA base address of the buffer | |
72 | * @len: Buffer length, in bytes | |
73 | * @index: Buffer index within controller;s buffer table | |
74 | * @entries: Number of buffer table entries | |
75 | * | |
76 | * Special buffers are used for the event queues and the TX and RX | |
77 | * descriptor queues for each channel. They are *not* used for the | |
78 | * actual transmit and receive buffers. | |
8ceee660 BH |
79 | */ |
80 | struct efx_special_buffer { | |
81 | void *addr; | |
82 | dma_addr_t dma_addr; | |
83 | unsigned int len; | |
5bbe2f4f BH |
84 | unsigned int index; |
85 | unsigned int entries; | |
8ceee660 BH |
86 | }; |
87 | ||
88 | /** | |
89 | * struct efx_tx_buffer - An Efx TX buffer | |
90 | * @skb: The associated socket buffer. | |
91 | * Set only on the final fragment of a packet; %NULL for all other | |
92 | * fragments. When this fragment completes, then we can free this | |
93 | * skb. | |
b9b39b62 BH |
94 | * @tsoh: The associated TSO header structure, or %NULL if this |
95 | * buffer is not a TSO header. | |
8ceee660 BH |
96 | * @dma_addr: DMA address of the fragment. |
97 | * @len: Length of this fragment. | |
98 | * This field is zero when the queue slot is empty. | |
99 | * @continuation: True if this fragment is not the end of a packet. | |
100 | * @unmap_single: True if pci_unmap_single should be used. | |
8ceee660 BH |
101 | * @unmap_len: Length of this fragment to unmap |
102 | */ | |
103 | struct efx_tx_buffer { | |
104 | const struct sk_buff *skb; | |
b9b39b62 | 105 | struct efx_tso_header *tsoh; |
8ceee660 BH |
106 | dma_addr_t dma_addr; |
107 | unsigned short len; | |
dc8cfa55 BH |
108 | bool continuation; |
109 | bool unmap_single; | |
8ceee660 BH |
110 | unsigned short unmap_len; |
111 | }; | |
112 | ||
113 | /** | |
114 | * struct efx_tx_queue - An Efx TX queue | |
115 | * | |
116 | * This is a ring buffer of TX fragments. | |
117 | * Since the TX completion path always executes on the same | |
118 | * CPU and the xmit path can operate on different CPUs, | |
119 | * performance is increased by ensuring that the completion | |
120 | * path and the xmit path operate on different cache lines. | |
121 | * This is particularly important if the xmit path is always | |
122 | * executing on one CPU which is different from the completion | |
123 | * path. There is also a cache line for members which are | |
124 | * read but not written on the fast path. | |
125 | * | |
126 | * @efx: The associated Efx NIC | |
127 | * @queue: DMA queue number | |
8ceee660 | 128 | * @channel: The associated channel |
c04bfc6b | 129 | * @core_txq: The networking core TX queue structure |
8ceee660 BH |
130 | * @buffer: The software buffer ring |
131 | * @txd: The hardware descriptor ring | |
ecc910f5 | 132 | * @ptr_mask: The size of the ring minus 1. |
94b274bf | 133 | * @initialised: Has hardware queue been initialised? |
8ceee660 BH |
134 | * @read_count: Current read pointer. |
135 | * This is the number of buffers that have been removed from both rings. | |
cd38557d BH |
136 | * @old_write_count: The value of @write_count when last checked. |
137 | * This is here for performance reasons. The xmit path will | |
138 | * only get the up-to-date value of @write_count if this | |
139 | * variable indicates that the queue is empty. This is to | |
140 | * avoid cache-line ping-pong between the xmit path and the | |
141 | * completion path. | |
8ceee660 BH |
142 | * @insert_count: Current insert pointer |
143 | * This is the number of buffers that have been added to the | |
144 | * software ring. | |
145 | * @write_count: Current write pointer | |
146 | * This is the number of buffers that have been added to the | |
147 | * hardware ring. | |
148 | * @old_read_count: The value of read_count when last checked. | |
149 | * This is here for performance reasons. The xmit path will | |
150 | * only get the up-to-date value of read_count if this | |
151 | * variable indicates that the queue is full. This is to | |
152 | * avoid cache-line ping-pong between the xmit path and the | |
153 | * completion path. | |
b9b39b62 BH |
154 | * @tso_headers_free: A list of TSO headers allocated for this TX queue |
155 | * that are not in use, and so available for new TSO sends. The list | |
156 | * is protected by the TX queue lock. | |
157 | * @tso_bursts: Number of times TSO xmit invoked by kernel | |
158 | * @tso_long_headers: Number of packets with headers too long for standard | |
159 | * blocks | |
160 | * @tso_packets: Number of packets via the TSO xmit path | |
cd38557d BH |
161 | * @pushes: Number of times the TX push feature has been used |
162 | * @empty_read_count: If the completion path has seen the queue as empty | |
163 | * and the transmission path has not yet checked this, the value of | |
164 | * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0. | |
8ceee660 BH |
165 | */ |
166 | struct efx_tx_queue { | |
167 | /* Members which don't change on the fast path */ | |
168 | struct efx_nic *efx ____cacheline_aligned_in_smp; | |
a4900ac9 | 169 | unsigned queue; |
8ceee660 | 170 | struct efx_channel *channel; |
c04bfc6b | 171 | struct netdev_queue *core_txq; |
8ceee660 BH |
172 | struct efx_tx_buffer *buffer; |
173 | struct efx_special_buffer txd; | |
ecc910f5 | 174 | unsigned int ptr_mask; |
94b274bf | 175 | bool initialised; |
8ceee660 BH |
176 | |
177 | /* Members used mainly on the completion path */ | |
178 | unsigned int read_count ____cacheline_aligned_in_smp; | |
cd38557d | 179 | unsigned int old_write_count; |
8ceee660 BH |
180 | |
181 | /* Members used only on the xmit path */ | |
182 | unsigned int insert_count ____cacheline_aligned_in_smp; | |
183 | unsigned int write_count; | |
184 | unsigned int old_read_count; | |
b9b39b62 BH |
185 | struct efx_tso_header *tso_headers_free; |
186 | unsigned int tso_bursts; | |
187 | unsigned int tso_long_headers; | |
188 | unsigned int tso_packets; | |
cd38557d BH |
189 | unsigned int pushes; |
190 | ||
191 | /* Members shared between paths and sometimes updated */ | |
192 | unsigned int empty_read_count ____cacheline_aligned_in_smp; | |
193 | #define EFX_EMPTY_COUNT_VALID 0x80000000 | |
8ceee660 BH |
194 | }; |
195 | ||
196 | /** | |
197 | * struct efx_rx_buffer - An Efx RX data buffer | |
198 | * @dma_addr: DMA base address of the buffer | |
db339569 BH |
199 | * @skb: The associated socket buffer. Valid iff !(@flags & %EFX_RX_BUF_PAGE). |
200 | * Will be %NULL if the buffer slot is currently free. | |
201 | * @page: The associated page buffer. Valif iff @flags & %EFX_RX_BUF_PAGE. | |
202 | * Will be %NULL if the buffer slot is currently free. | |
8ceee660 | 203 | * @len: Buffer length, in bytes. |
db339569 | 204 | * @flags: Flags for buffer and packet state. |
8ceee660 BH |
205 | */ |
206 | struct efx_rx_buffer { | |
207 | dma_addr_t dma_addr; | |
8ba5366a SH |
208 | union { |
209 | struct sk_buff *skb; | |
210 | struct page *page; | |
211 | } u; | |
8ceee660 | 212 | unsigned int len; |
db339569 | 213 | u16 flags; |
8ceee660 | 214 | }; |
db339569 BH |
215 | #define EFX_RX_BUF_PAGE 0x0001 |
216 | #define EFX_RX_PKT_CSUMMED 0x0002 | |
217 | #define EFX_RX_PKT_DISCARD 0x0004 | |
8ceee660 | 218 | |
62b330ba SH |
219 | /** |
220 | * struct efx_rx_page_state - Page-based rx buffer state | |
221 | * | |
222 | * Inserted at the start of every page allocated for receive buffers. | |
223 | * Used to facilitate sharing dma mappings between recycled rx buffers | |
224 | * and those passed up to the kernel. | |
225 | * | |
226 | * @refcnt: Number of struct efx_rx_buffer's referencing this page. | |
227 | * When refcnt falls to zero, the page is unmapped for dma | |
228 | * @dma_addr: The dma address of this page. | |
229 | */ | |
230 | struct efx_rx_page_state { | |
231 | unsigned refcnt; | |
232 | dma_addr_t dma_addr; | |
233 | ||
234 | unsigned int __pad[0] ____cacheline_aligned; | |
235 | }; | |
236 | ||
8ceee660 BH |
237 | /** |
238 | * struct efx_rx_queue - An Efx RX queue | |
239 | * @efx: The associated Efx NIC | |
8ceee660 BH |
240 | * @buffer: The software buffer ring |
241 | * @rxd: The hardware descriptor ring | |
ecc910f5 | 242 | * @ptr_mask: The size of the ring minus 1. |
9f2cb71c BH |
243 | * @enabled: Receive queue enabled indicator. |
244 | * @flush_pending: Set when a RX flush is pending. Has the same lifetime as | |
245 | * @rxq_flush_pending. | |
8ceee660 BH |
246 | * @added_count: Number of buffers added to the receive queue. |
247 | * @notified_count: Number of buffers given to NIC (<= @added_count). | |
248 | * @removed_count: Number of buffers removed from the receive queue. | |
8ceee660 BH |
249 | * @max_fill: RX descriptor maximum fill level (<= ring size) |
250 | * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill | |
251 | * (<= @max_fill) | |
252 | * @fast_fill_limit: The level to which a fast fill will fill | |
253 | * (@fast_fill_trigger <= @fast_fill_limit <= @max_fill) | |
254 | * @min_fill: RX descriptor minimum non-zero fill level. | |
255 | * This records the minimum fill level observed when a ring | |
256 | * refill was triggered. | |
8ceee660 BH |
257 | * @alloc_page_count: RX allocation strategy counter. |
258 | * @alloc_skb_count: RX allocation strategy counter. | |
90d683af | 259 | * @slow_fill: Timer used to defer efx_nic_generate_fill_event(). |
8ceee660 BH |
260 | */ |
261 | struct efx_rx_queue { | |
262 | struct efx_nic *efx; | |
8ceee660 BH |
263 | struct efx_rx_buffer *buffer; |
264 | struct efx_special_buffer rxd; | |
ecc910f5 | 265 | unsigned int ptr_mask; |
9f2cb71c BH |
266 | bool enabled; |
267 | bool flush_pending; | |
8ceee660 BH |
268 | |
269 | int added_count; | |
270 | int notified_count; | |
271 | int removed_count; | |
8ceee660 BH |
272 | unsigned int max_fill; |
273 | unsigned int fast_fill_trigger; | |
274 | unsigned int fast_fill_limit; | |
275 | unsigned int min_fill; | |
276 | unsigned int min_overfill; | |
277 | unsigned int alloc_page_count; | |
278 | unsigned int alloc_skb_count; | |
90d683af | 279 | struct timer_list slow_fill; |
8ceee660 | 280 | unsigned int slow_fill_count; |
8ceee660 BH |
281 | }; |
282 | ||
283 | /** | |
284 | * struct efx_buffer - An Efx general-purpose buffer | |
285 | * @addr: host base address of the buffer | |
286 | * @dma_addr: DMA base address of the buffer | |
287 | * @len: Buffer length, in bytes | |
288 | * | |
754c653a | 289 | * The NIC uses these buffers for its interrupt status registers and |
8ceee660 BH |
290 | * MAC stats dumps. |
291 | */ | |
292 | struct efx_buffer { | |
293 | void *addr; | |
294 | dma_addr_t dma_addr; | |
295 | unsigned int len; | |
296 | }; | |
297 | ||
298 | ||
8ceee660 BH |
299 | enum efx_rx_alloc_method { |
300 | RX_ALLOC_METHOD_AUTO = 0, | |
301 | RX_ALLOC_METHOD_SKB = 1, | |
302 | RX_ALLOC_METHOD_PAGE = 2, | |
303 | }; | |
304 | ||
305 | /** | |
306 | * struct efx_channel - An Efx channel | |
307 | * | |
308 | * A channel comprises an event queue, at least one TX queue, at least | |
309 | * one RX queue, and an associated tasklet for processing the event | |
310 | * queue. | |
311 | * | |
312 | * @efx: Associated Efx NIC | |
8ceee660 | 313 | * @channel: Channel instance number |
8ceee660 BH |
314 | * @enabled: Channel enabled indicator |
315 | * @irq: IRQ number (MSI and MSI-X only) | |
0d86ebd8 | 316 | * @irq_moderation: IRQ moderation value (in hardware ticks) |
8ceee660 BH |
317 | * @napi_dev: Net device used with NAPI |
318 | * @napi_str: NAPI control structure | |
8ceee660 BH |
319 | * @work_pending: Is work pending via NAPI? |
320 | * @eventq: Event queue buffer | |
ecc910f5 | 321 | * @eventq_mask: Event queue pointer mask |
8ceee660 BH |
322 | * @eventq_read_ptr: Event queue read pointer |
323 | * @last_eventq_read_ptr: Last event queue read pointer value. | |
1646a6f3 | 324 | * @last_irq_cpu: Last CPU to handle interrupt for this channel |
6fb70fd1 BH |
325 | * @irq_count: Number of IRQs since last adaptive moderation decision |
326 | * @irq_mod_score: IRQ moderation score | |
8ceee660 BH |
327 | * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors |
328 | * and diagnostic counters | |
329 | * @rx_alloc_push_pages: RX allocation method currently in use for pushing | |
330 | * descriptors | |
8ceee660 | 331 | * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors |
8ceee660 BH |
332 | * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors |
333 | * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors | |
c1ac403b | 334 | * @n_rx_mcast_mismatch: Count of unmatched multicast frames |
8ceee660 BH |
335 | * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors |
336 | * @n_rx_overlength: Count of RX_OVERLENGTH errors | |
337 | * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun | |
8313aca3 | 338 | * @rx_queue: RX queue for this channel |
8313aca3 | 339 | * @tx_queue: TX queues for this channel |
8ceee660 BH |
340 | */ |
341 | struct efx_channel { | |
342 | struct efx_nic *efx; | |
8ceee660 | 343 | int channel; |
dc8cfa55 | 344 | bool enabled; |
8ceee660 | 345 | int irq; |
8ceee660 BH |
346 | unsigned int irq_moderation; |
347 | struct net_device *napi_dev; | |
348 | struct napi_struct napi_str; | |
dc8cfa55 | 349 | bool work_pending; |
8ceee660 | 350 | struct efx_special_buffer eventq; |
ecc910f5 | 351 | unsigned int eventq_mask; |
8ceee660 BH |
352 | unsigned int eventq_read_ptr; |
353 | unsigned int last_eventq_read_ptr; | |
8ceee660 | 354 | |
1646a6f3 | 355 | int last_irq_cpu; |
6fb70fd1 BH |
356 | unsigned int irq_count; |
357 | unsigned int irq_mod_score; | |
64d8ad6d BH |
358 | #ifdef CONFIG_RFS_ACCEL |
359 | unsigned int rfs_filters_added; | |
360 | #endif | |
6fb70fd1 | 361 | |
8ceee660 BH |
362 | int rx_alloc_level; |
363 | int rx_alloc_push_pages; | |
8ceee660 BH |
364 | |
365 | unsigned n_rx_tobe_disc; | |
8ceee660 BH |
366 | unsigned n_rx_ip_hdr_chksum_err; |
367 | unsigned n_rx_tcp_udp_chksum_err; | |
c1ac403b | 368 | unsigned n_rx_mcast_mismatch; |
8ceee660 BH |
369 | unsigned n_rx_frm_trunc; |
370 | unsigned n_rx_overlength; | |
371 | unsigned n_skbuff_leaks; | |
372 | ||
373 | /* Used to pipeline received packets in order to optimise memory | |
374 | * access with prefetches. | |
375 | */ | |
376 | struct efx_rx_buffer *rx_pkt; | |
8ceee660 | 377 | |
8313aca3 | 378 | struct efx_rx_queue rx_queue; |
94b274bf | 379 | struct efx_tx_queue tx_queue[EFX_TXQ_TYPES]; |
8ceee660 BH |
380 | }; |
381 | ||
398468ed BH |
382 | enum efx_led_mode { |
383 | EFX_LED_OFF = 0, | |
384 | EFX_LED_ON = 1, | |
385 | EFX_LED_DEFAULT = 2 | |
386 | }; | |
387 | ||
c459302d BH |
388 | #define STRING_TABLE_LOOKUP(val, member) \ |
389 | ((val) < member ## _max) ? member ## _names[val] : "(invalid)" | |
390 | ||
18e83e4c | 391 | extern const char *const efx_loopback_mode_names[]; |
c459302d BH |
392 | extern const unsigned int efx_loopback_mode_max; |
393 | #define LOOPBACK_MODE(efx) \ | |
394 | STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode) | |
395 | ||
18e83e4c | 396 | extern const char *const efx_reset_type_names[]; |
c459302d BH |
397 | extern const unsigned int efx_reset_type_max; |
398 | #define RESET_TYPE(type) \ | |
399 | STRING_TABLE_LOOKUP(type, efx_reset_type) | |
3273c2e8 | 400 | |
8ceee660 BH |
401 | enum efx_int_mode { |
402 | /* Be careful if altering to correct macro below */ | |
403 | EFX_INT_MODE_MSIX = 0, | |
404 | EFX_INT_MODE_MSI = 1, | |
405 | EFX_INT_MODE_LEGACY = 2, | |
406 | EFX_INT_MODE_MAX /* Insert any new items before this */ | |
407 | }; | |
408 | #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI) | |
409 | ||
8ceee660 BH |
410 | enum nic_state { |
411 | STATE_INIT = 0, | |
412 | STATE_RUNNING = 1, | |
413 | STATE_FINI = 2, | |
3c78708f | 414 | STATE_DISABLED = 3, |
8ceee660 BH |
415 | STATE_MAX, |
416 | }; | |
417 | ||
418 | /* | |
419 | * Alignment of page-allocated RX buffers | |
420 | * | |
421 | * Controls the number of bytes inserted at the start of an RX buffer. | |
422 | * This is the equivalent of NET_IP_ALIGN [which controls the alignment | |
423 | * of the skb->head for hardware DMA]. | |
424 | */ | |
13e9ab11 | 425 | #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
8ceee660 BH |
426 | #define EFX_PAGE_IP_ALIGN 0 |
427 | #else | |
428 | #define EFX_PAGE_IP_ALIGN NET_IP_ALIGN | |
429 | #endif | |
430 | ||
431 | /* | |
432 | * Alignment of the skb->head which wraps a page-allocated RX buffer | |
433 | * | |
434 | * The skb allocated to wrap an rx_buffer can have this alignment. Since | |
435 | * the data is memcpy'd from the rx_buf, it does not need to be equal to | |
436 | * EFX_PAGE_IP_ALIGN. | |
437 | */ | |
438 | #define EFX_PAGE_SKB_ALIGN 2 | |
439 | ||
440 | /* Forward declaration */ | |
441 | struct efx_nic; | |
442 | ||
443 | /* Pseudo bit-mask flow control field */ | |
b5626946 DM |
444 | #define EFX_FC_RX FLOW_CTRL_RX |
445 | #define EFX_FC_TX FLOW_CTRL_TX | |
446 | #define EFX_FC_AUTO 4 | |
8ceee660 | 447 | |
eb50c0d6 BH |
448 | /** |
449 | * struct efx_link_state - Current state of the link | |
450 | * @up: Link is up | |
451 | * @fd: Link is full-duplex | |
452 | * @fc: Actual flow control flags | |
453 | * @speed: Link speed (Mbps) | |
454 | */ | |
455 | struct efx_link_state { | |
456 | bool up; | |
457 | bool fd; | |
b5626946 | 458 | u8 fc; |
eb50c0d6 BH |
459 | unsigned int speed; |
460 | }; | |
461 | ||
fdaa9aed SH |
462 | static inline bool efx_link_state_equal(const struct efx_link_state *left, |
463 | const struct efx_link_state *right) | |
464 | { | |
465 | return left->up == right->up && left->fd == right->fd && | |
466 | left->fc == right->fc && left->speed == right->speed; | |
467 | } | |
468 | ||
8ceee660 BH |
469 | /** |
470 | * struct efx_phy_operations - Efx PHY operations table | |
c1c4f453 BH |
471 | * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds, |
472 | * efx->loopback_modes. | |
8ceee660 BH |
473 | * @init: Initialise PHY |
474 | * @fini: Shut down PHY | |
475 | * @reconfigure: Reconfigure PHY (e.g. for new link parameters) | |
fdaa9aed SH |
476 | * @poll: Update @link_state and report whether it changed. |
477 | * Serialised by the mac_lock. | |
177dfcd8 BH |
478 | * @get_settings: Get ethtool settings. Serialised by the mac_lock. |
479 | * @set_settings: Set ethtool settings. Serialised by the mac_lock. | |
af4ad9bc | 480 | * @set_npage_adv: Set abilities advertised in (Extended) Next Page |
04cc8cac | 481 | * (only needed where AN bit is set in mmds) |
4f16c073 | 482 | * @test_alive: Test that PHY is 'alive' (online) |
c1c4f453 | 483 | * @test_name: Get the name of a PHY-specific test/result |
4f16c073 | 484 | * @run_tests: Run tests and record results as appropriate (offline). |
1796721a | 485 | * Flags are the ethtool tests flags. |
8ceee660 BH |
486 | */ |
487 | struct efx_phy_operations { | |
c1c4f453 | 488 | int (*probe) (struct efx_nic *efx); |
8ceee660 BH |
489 | int (*init) (struct efx_nic *efx); |
490 | void (*fini) (struct efx_nic *efx); | |
ff3b00a0 | 491 | void (*remove) (struct efx_nic *efx); |
d3245b28 | 492 | int (*reconfigure) (struct efx_nic *efx); |
fdaa9aed | 493 | bool (*poll) (struct efx_nic *efx); |
177dfcd8 BH |
494 | void (*get_settings) (struct efx_nic *efx, |
495 | struct ethtool_cmd *ecmd); | |
496 | int (*set_settings) (struct efx_nic *efx, | |
497 | struct ethtool_cmd *ecmd); | |
af4ad9bc | 498 | void (*set_npage_adv) (struct efx_nic *efx, u32); |
4f16c073 | 499 | int (*test_alive) (struct efx_nic *efx); |
c1c4f453 | 500 | const char *(*test_name) (struct efx_nic *efx, unsigned int index); |
1796721a | 501 | int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags); |
8ceee660 BH |
502 | }; |
503 | ||
f8b87c17 BH |
504 | /** |
505 | * @enum efx_phy_mode - PHY operating mode flags | |
506 | * @PHY_MODE_NORMAL: on and should pass traffic | |
507 | * @PHY_MODE_TX_DISABLED: on with TX disabled | |
3e133c44 BH |
508 | * @PHY_MODE_LOW_POWER: set to low power through MDIO |
509 | * @PHY_MODE_OFF: switched off through external control | |
f8b87c17 BH |
510 | * @PHY_MODE_SPECIAL: on but will not pass traffic |
511 | */ | |
512 | enum efx_phy_mode { | |
513 | PHY_MODE_NORMAL = 0, | |
514 | PHY_MODE_TX_DISABLED = 1, | |
3e133c44 BH |
515 | PHY_MODE_LOW_POWER = 2, |
516 | PHY_MODE_OFF = 4, | |
f8b87c17 BH |
517 | PHY_MODE_SPECIAL = 8, |
518 | }; | |
519 | ||
520 | static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode) | |
521 | { | |
8c8661e4 | 522 | return !!(mode & ~PHY_MODE_TX_DISABLED); |
f8b87c17 BH |
523 | } |
524 | ||
8ceee660 BH |
525 | /* |
526 | * Efx extended statistics | |
527 | * | |
528 | * Not all statistics are provided by all supported MACs. The purpose | |
529 | * is this structure is to contain the raw statistics provided by each | |
530 | * MAC. | |
531 | */ | |
532 | struct efx_mac_stats { | |
533 | u64 tx_bytes; | |
534 | u64 tx_good_bytes; | |
535 | u64 tx_bad_bytes; | |
f9c76250 BH |
536 | u64 tx_packets; |
537 | u64 tx_bad; | |
538 | u64 tx_pause; | |
539 | u64 tx_control; | |
540 | u64 tx_unicast; | |
541 | u64 tx_multicast; | |
542 | u64 tx_broadcast; | |
543 | u64 tx_lt64; | |
544 | u64 tx_64; | |
545 | u64 tx_65_to_127; | |
546 | u64 tx_128_to_255; | |
547 | u64 tx_256_to_511; | |
548 | u64 tx_512_to_1023; | |
549 | u64 tx_1024_to_15xx; | |
550 | u64 tx_15xx_to_jumbo; | |
551 | u64 tx_gtjumbo; | |
552 | u64 tx_collision; | |
553 | u64 tx_single_collision; | |
554 | u64 tx_multiple_collision; | |
555 | u64 tx_excessive_collision; | |
556 | u64 tx_deferred; | |
557 | u64 tx_late_collision; | |
558 | u64 tx_excessive_deferred; | |
559 | u64 tx_non_tcpudp; | |
560 | u64 tx_mac_src_error; | |
561 | u64 tx_ip_src_error; | |
8ceee660 BH |
562 | u64 rx_bytes; |
563 | u64 rx_good_bytes; | |
564 | u64 rx_bad_bytes; | |
f9c76250 BH |
565 | u64 rx_packets; |
566 | u64 rx_good; | |
567 | u64 rx_bad; | |
568 | u64 rx_pause; | |
569 | u64 rx_control; | |
570 | u64 rx_unicast; | |
571 | u64 rx_multicast; | |
572 | u64 rx_broadcast; | |
573 | u64 rx_lt64; | |
574 | u64 rx_64; | |
575 | u64 rx_65_to_127; | |
576 | u64 rx_128_to_255; | |
577 | u64 rx_256_to_511; | |
578 | u64 rx_512_to_1023; | |
579 | u64 rx_1024_to_15xx; | |
580 | u64 rx_15xx_to_jumbo; | |
581 | u64 rx_gtjumbo; | |
582 | u64 rx_bad_lt64; | |
583 | u64 rx_bad_64_to_15xx; | |
584 | u64 rx_bad_15xx_to_jumbo; | |
585 | u64 rx_bad_gtjumbo; | |
586 | u64 rx_overflow; | |
587 | u64 rx_missed; | |
588 | u64 rx_false_carrier; | |
589 | u64 rx_symbol_error; | |
590 | u64 rx_align_error; | |
591 | u64 rx_length_error; | |
592 | u64 rx_internal_error; | |
593 | u64 rx_good_lt64; | |
8ceee660 BH |
594 | }; |
595 | ||
596 | /* Number of bits used in a multicast filter hash address */ | |
597 | #define EFX_MCAST_HASH_BITS 8 | |
598 | ||
599 | /* Number of (single-bit) entries in a multicast filter hash */ | |
600 | #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS) | |
601 | ||
602 | /* An Efx multicast filter hash */ | |
603 | union efx_multicast_hash { | |
604 | u8 byte[EFX_MCAST_HASH_ENTRIES / 8]; | |
605 | efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8]; | |
606 | }; | |
607 | ||
64eebcfd BH |
608 | struct efx_filter_state; |
609 | ||
8ceee660 BH |
610 | /** |
611 | * struct efx_nic - an Efx NIC | |
612 | * @name: Device name (net device name or bus id before net device registered) | |
613 | * @pci_dev: The PCI device | |
614 | * @type: Controller type attributes | |
615 | * @legacy_irq: IRQ number | |
94dec6a2 | 616 | * @legacy_irq_enabled: Are IRQs enabled on NIC (INT_EN_KER register)? |
8d9853d9 BH |
617 | * @workqueue: Workqueue for port reconfigures and the HW monitor. |
618 | * Work items do not hold and must not acquire RTNL. | |
6977dc63 | 619 | * @workqueue_name: Name of workqueue |
8ceee660 | 620 | * @reset_work: Scheduled reset workitem |
8ceee660 BH |
621 | * @membase_phys: Memory BAR value as physical address |
622 | * @membase: Memory BAR value | |
8ceee660 | 623 | * @interrupt_mode: Interrupt mode |
cc180b69 | 624 | * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds |
6fb70fd1 BH |
625 | * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues |
626 | * @irq_rx_moderation: IRQ moderation time for RX event queues | |
62776d03 | 627 | * @msg_enable: Log message enable flags |
8ceee660 | 628 | * @state: Device state flag. Serialised by the rtnl_lock. |
a7d529ae | 629 | * @reset_pending: Bitmask for pending resets |
8ceee660 BH |
630 | * @tx_queue: TX DMA queues |
631 | * @rx_queue: RX DMA queues | |
632 | * @channel: Channels | |
4642610c | 633 | * @channel_name: Names for channels and their IRQs |
ecc910f5 SH |
634 | * @rxq_entries: Size of receive queues requested by user. |
635 | * @txq_entries: Size of transmit queues requested by user. | |
0484e0db | 636 | * @next_buffer_table: First available buffer table id |
28b581ab | 637 | * @n_channels: Number of channels in use |
a4900ac9 BH |
638 | * @n_rx_channels: Number of channels used for RX (= number of RX queues) |
639 | * @n_tx_channels: Number of channels used for TX | |
8ceee660 BH |
640 | * @rx_buffer_len: RX buffer length |
641 | * @rx_buffer_order: Order (log2) of number of pages for each RX buffer | |
78d4189d | 642 | * @rx_hash_key: Toeplitz hash key for RSS |
765c9f46 | 643 | * @rx_indir_table: Indirection table for RSS |
0484e0db BH |
644 | * @int_error_count: Number of internal errors seen recently |
645 | * @int_error_expire: Time at which error count will be expired | |
8ceee660 | 646 | * @irq_status: Interrupt status buffer |
c28884c5 | 647 | * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0 |
1646a6f3 | 648 | * @irq_level: IRQ level/index for IRQs not triggered by an event queue |
76884835 | 649 | * @mtd_list: List of MTDs attached to the NIC |
25985edc | 650 | * @nic_data: Hardware dependent state |
8c8661e4 | 651 | * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode, |
e4abce85 | 652 | * efx_monitor() and efx_reconfigure_port() |
8ceee660 | 653 | * @port_enabled: Port enabled indicator. |
fdaa9aed SH |
654 | * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and |
655 | * efx_mac_work() with kernel interfaces. Safe to read under any | |
656 | * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must | |
657 | * be held to modify it. | |
8ceee660 BH |
658 | * @port_initialized: Port initialized? |
659 | * @net_dev: Operating system network device. Consider holding the rtnl lock | |
8ceee660 | 660 | * @stats_buffer: DMA buffer for statistics |
8ceee660 | 661 | * @phy_type: PHY type |
8ceee660 BH |
662 | * @phy_op: PHY interface |
663 | * @phy_data: PHY private data (including PHY-specific stats) | |
68e7f45e | 664 | * @mdio: PHY MDIO interface |
8880f4ec | 665 | * @mdio_bus: PHY MDIO bus ID (only used by Siena) |
8c8661e4 | 666 | * @phy_mode: PHY operating mode. Serialised by @mac_lock. |
d3245b28 | 667 | * @link_advertising: Autonegotiation advertising flags |
eb50c0d6 | 668 | * @link_state: Current state of the link |
8ceee660 BH |
669 | * @n_link_state_changes: Number of times the link has changed state |
670 | * @promiscuous: Promiscuous flag. Protected by netif_tx_lock. | |
671 | * @multicast_hash: Multicast hash table | |
04cc8cac | 672 | * @wanted_fc: Wanted flow control flags |
a606f432 SH |
673 | * @fc_disable: When non-zero flow control is disabled. Typically used to |
674 | * ensure that network back pressure doesn't delay dma queue flushes. | |
675 | * Serialised by the rtnl lock. | |
8be4f3e6 | 676 | * @mac_work: Work item for changing MAC promiscuity and multicast hash |
3273c2e8 BH |
677 | * @loopback_mode: Loopback status |
678 | * @loopback_modes: Supported loopback mode bitmask | |
679 | * @loopback_selftest: Offline self-test private state | |
9f2cb71c BH |
680 | * @drain_pending: Count of RX and TX queues that haven't been flushed and drained. |
681 | * @rxq_flush_pending: Count of number of receive queues that need to be flushed. | |
682 | * Decremented when the efx_flush_rx_queue() is called. | |
683 | * @rxq_flush_outstanding: Count of number of RX flushes started but not yet | |
684 | * completed (either success or failure). Not used when MCDI is used to | |
685 | * flush receive queues. | |
686 | * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions. | |
ab28c12a BH |
687 | * @monitor_work: Hardware monitor workitem |
688 | * @biu_lock: BIU (bus interface unit) lock | |
1646a6f3 BH |
689 | * @last_irq_cpu: Last CPU to handle a possible test interrupt. This |
690 | * field is used by efx_test_interrupts() to verify that an | |
691 | * interrupt has occurred. | |
ab28c12a BH |
692 | * @n_rx_nodesc_drop_cnt: RX no descriptor drop count |
693 | * @mac_stats: MAC statistics. These include all statistics the MACs | |
694 | * can provide. Generic code converts these into a standard | |
695 | * &struct net_device_stats. | |
696 | * @stats_lock: Statistics update lock. Serialises statistics fetches | |
1cb34522 | 697 | * and access to @mac_stats. |
8ceee660 | 698 | * |
754c653a | 699 | * This is stored in the private area of the &struct net_device. |
8ceee660 BH |
700 | */ |
701 | struct efx_nic { | |
ab28c12a BH |
702 | /* The following fields should be written very rarely */ |
703 | ||
8ceee660 BH |
704 | char name[IFNAMSIZ]; |
705 | struct pci_dev *pci_dev; | |
706 | const struct efx_nic_type *type; | |
707 | int legacy_irq; | |
94dec6a2 | 708 | bool legacy_irq_enabled; |
8ceee660 | 709 | struct workqueue_struct *workqueue; |
6977dc63 | 710 | char workqueue_name[16]; |
8ceee660 | 711 | struct work_struct reset_work; |
086ea356 | 712 | resource_size_t membase_phys; |
8ceee660 | 713 | void __iomem *membase; |
ab28c12a | 714 | |
8ceee660 | 715 | enum efx_int_mode interrupt_mode; |
cc180b69 | 716 | unsigned int timer_quantum_ns; |
6fb70fd1 BH |
717 | bool irq_rx_adaptive; |
718 | unsigned int irq_rx_moderation; | |
62776d03 | 719 | u32 msg_enable; |
8ceee660 | 720 | |
8ceee660 | 721 | enum nic_state state; |
a7d529ae | 722 | unsigned long reset_pending; |
8ceee660 | 723 | |
8313aca3 | 724 | struct efx_channel *channel[EFX_MAX_CHANNELS]; |
efbc2d7c | 725 | char channel_name[EFX_MAX_CHANNELS][IFNAMSIZ + 6]; |
8ceee660 | 726 | |
ecc910f5 SH |
727 | unsigned rxq_entries; |
728 | unsigned txq_entries; | |
0484e0db | 729 | unsigned next_buffer_table; |
a4900ac9 BH |
730 | unsigned n_channels; |
731 | unsigned n_rx_channels; | |
97653431 | 732 | unsigned tx_channel_offset; |
a4900ac9 | 733 | unsigned n_tx_channels; |
8ceee660 BH |
734 | unsigned int rx_buffer_len; |
735 | unsigned int rx_buffer_order; | |
5d3a6fca | 736 | u8 rx_hash_key[40]; |
765c9f46 | 737 | u32 rx_indir_table[128]; |
8ceee660 | 738 | |
0484e0db BH |
739 | unsigned int_error_count; |
740 | unsigned long int_error_expire; | |
741 | ||
8ceee660 | 742 | struct efx_buffer irq_status; |
c28884c5 | 743 | unsigned irq_zero_count; |
1646a6f3 | 744 | unsigned irq_level; |
8ceee660 | 745 | |
76884835 BH |
746 | #ifdef CONFIG_SFC_MTD |
747 | struct list_head mtd_list; | |
748 | #endif | |
4a5b504d | 749 | |
8880f4ec | 750 | void *nic_data; |
8ceee660 BH |
751 | |
752 | struct mutex mac_lock; | |
766ca0fa | 753 | struct work_struct mac_work; |
dc8cfa55 | 754 | bool port_enabled; |
8ceee660 | 755 | |
dc8cfa55 | 756 | bool port_initialized; |
8ceee660 | 757 | struct net_device *net_dev; |
8ceee660 | 758 | |
8ceee660 | 759 | struct efx_buffer stats_buffer; |
8ceee660 | 760 | |
c1c4f453 | 761 | unsigned int phy_type; |
6c8c2513 | 762 | const struct efx_phy_operations *phy_op; |
8ceee660 | 763 | void *phy_data; |
68e7f45e | 764 | struct mdio_if_info mdio; |
8880f4ec | 765 | unsigned int mdio_bus; |
f8b87c17 | 766 | enum efx_phy_mode phy_mode; |
8ceee660 | 767 | |
d3245b28 | 768 | u32 link_advertising; |
eb50c0d6 | 769 | struct efx_link_state link_state; |
8ceee660 BH |
770 | unsigned int n_link_state_changes; |
771 | ||
dc8cfa55 | 772 | bool promiscuous; |
8ceee660 | 773 | union efx_multicast_hash multicast_hash; |
b5626946 | 774 | u8 wanted_fc; |
a606f432 | 775 | unsigned fc_disable; |
8ceee660 BH |
776 | |
777 | atomic_t rx_reset; | |
3273c2e8 | 778 | enum efx_loopback_mode loopback_mode; |
e58f69f4 | 779 | u64 loopback_modes; |
3273c2e8 BH |
780 | |
781 | void *loopback_selftest; | |
64eebcfd BH |
782 | |
783 | struct efx_filter_state *filter_state; | |
ab28c12a | 784 | |
9f2cb71c BH |
785 | atomic_t drain_pending; |
786 | atomic_t rxq_flush_pending; | |
787 | atomic_t rxq_flush_outstanding; | |
788 | wait_queue_head_t flush_wq; | |
789 | ||
ab28c12a BH |
790 | /* The following fields may be written more often */ |
791 | ||
792 | struct delayed_work monitor_work ____cacheline_aligned_in_smp; | |
793 | spinlock_t biu_lock; | |
1646a6f3 | 794 | int last_irq_cpu; |
ab28c12a BH |
795 | unsigned n_rx_nodesc_drop_cnt; |
796 | struct efx_mac_stats mac_stats; | |
797 | spinlock_t stats_lock; | |
8ceee660 BH |
798 | }; |
799 | ||
55668611 BH |
800 | static inline int efx_dev_registered(struct efx_nic *efx) |
801 | { | |
802 | return efx->net_dev->reg_state == NETREG_REGISTERED; | |
803 | } | |
804 | ||
8880f4ec BH |
805 | static inline unsigned int efx_port_num(struct efx_nic *efx) |
806 | { | |
3df95ce9 | 807 | return efx->net_dev->dev_id; |
8880f4ec BH |
808 | } |
809 | ||
8ceee660 BH |
810 | /** |
811 | * struct efx_nic_type - Efx device type definition | |
ef2b90ee BH |
812 | * @probe: Probe the controller |
813 | * @remove: Free resources allocated by probe() | |
814 | * @init: Initialise the controller | |
815 | * @fini: Shut down the controller | |
816 | * @monitor: Periodic function for polling link state and hardware monitor | |
0e2a9c7c BH |
817 | * @map_reset_reason: Map ethtool reset reason to a reset method |
818 | * @map_reset_flags: Map ethtool reset flags to a reset method, if possible | |
ef2b90ee BH |
819 | * @reset: Reset the controller hardware and possibly the PHY. This will |
820 | * be called while the controller is uninitialised. | |
821 | * @probe_port: Probe the MAC and PHY | |
822 | * @remove_port: Free resources allocated by probe_port() | |
40641ed9 | 823 | * @handle_global_event: Handle a "global" event (may be %NULL) |
ef2b90ee BH |
824 | * @prepare_flush: Prepare the hardware for flushing the DMA queues |
825 | * @update_stats: Update statistics not provided by event handling | |
826 | * @start_stats: Start the regular fetching of statistics | |
827 | * @stop_stats: Stop the regular fetching of statistics | |
06629f07 | 828 | * @set_id_led: Set state of identifying LED or revert to automatic function |
ef2b90ee | 829 | * @push_irq_moderation: Apply interrupt moderation value |
d3245b28 | 830 | * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY |
30b81cda BH |
831 | * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings |
832 | * to the hardware. Serialised by the mac_lock. | |
710b208d | 833 | * @check_mac_fault: Check MAC fault state. True if fault present. |
89c758fa BH |
834 | * @get_wol: Get WoL configuration from driver state |
835 | * @set_wol: Push WoL configuration to the NIC | |
836 | * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume) | |
9bfc4bb1 | 837 | * @test_registers: Test read/write functionality of control registers |
0aa3fbaa | 838 | * @test_nvram: Test validity of NVRAM contents |
daeda630 | 839 | * @revision: Hardware architecture revision |
8ceee660 BH |
840 | * @mem_map_size: Memory BAR mapped size |
841 | * @txd_ptr_tbl_base: TX descriptor ring base address | |
842 | * @rxd_ptr_tbl_base: RX descriptor ring base address | |
843 | * @buf_tbl_base: Buffer table base address | |
844 | * @evq_ptr_tbl_base: Event queue pointer table base address | |
845 | * @evq_rptr_tbl_base: Event queue read-pointer table base address | |
8ceee660 | 846 | * @max_dma_mask: Maximum possible DMA mask |
39c9cf07 BH |
847 | * @rx_buffer_hash_size: Size of hash at start of RX buffer |
848 | * @rx_buffer_padding: Size of padding at end of RX buffer | |
8ceee660 BH |
849 | * @max_interrupt_mode: Highest capability interrupt mode supported |
850 | * from &enum efx_init_mode. | |
851 | * @phys_addr_channels: Number of channels with physically addressed | |
852 | * descriptors | |
cc180b69 | 853 | * @timer_period_max: Maximum period of interrupt timer (in ticks) |
0228f5cd BH |
854 | * @tx_dc_base: Base address in SRAM of TX queue descriptor caches |
855 | * @rx_dc_base: Base address in SRAM of RX queue descriptor caches | |
c383b537 BH |
856 | * @offload_features: net_device feature flags for protocol offload |
857 | * features implemented in hardware | |
8ceee660 BH |
858 | */ |
859 | struct efx_nic_type { | |
ef2b90ee BH |
860 | int (*probe)(struct efx_nic *efx); |
861 | void (*remove)(struct efx_nic *efx); | |
862 | int (*init)(struct efx_nic *efx); | |
863 | void (*fini)(struct efx_nic *efx); | |
864 | void (*monitor)(struct efx_nic *efx); | |
0e2a9c7c BH |
865 | enum reset_type (*map_reset_reason)(enum reset_type reason); |
866 | int (*map_reset_flags)(u32 *flags); | |
ef2b90ee BH |
867 | int (*reset)(struct efx_nic *efx, enum reset_type method); |
868 | int (*probe_port)(struct efx_nic *efx); | |
869 | void (*remove_port)(struct efx_nic *efx); | |
40641ed9 | 870 | bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *); |
ef2b90ee BH |
871 | void (*prepare_flush)(struct efx_nic *efx); |
872 | void (*update_stats)(struct efx_nic *efx); | |
873 | void (*start_stats)(struct efx_nic *efx); | |
874 | void (*stop_stats)(struct efx_nic *efx); | |
06629f07 | 875 | void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode); |
ef2b90ee | 876 | void (*push_irq_moderation)(struct efx_channel *channel); |
d3245b28 | 877 | int (*reconfigure_port)(struct efx_nic *efx); |
710b208d BH |
878 | int (*reconfigure_mac)(struct efx_nic *efx); |
879 | bool (*check_mac_fault)(struct efx_nic *efx); | |
89c758fa BH |
880 | void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol); |
881 | int (*set_wol)(struct efx_nic *efx, u32 type); | |
882 | void (*resume_wol)(struct efx_nic *efx); | |
9bfc4bb1 | 883 | int (*test_registers)(struct efx_nic *efx); |
0aa3fbaa | 884 | int (*test_nvram)(struct efx_nic *efx); |
b895d73e | 885 | |
daeda630 | 886 | int revision; |
8ceee660 BH |
887 | unsigned int mem_map_size; |
888 | unsigned int txd_ptr_tbl_base; | |
889 | unsigned int rxd_ptr_tbl_base; | |
890 | unsigned int buf_tbl_base; | |
891 | unsigned int evq_ptr_tbl_base; | |
892 | unsigned int evq_rptr_tbl_base; | |
9bbd7d9a | 893 | u64 max_dma_mask; |
39c9cf07 | 894 | unsigned int rx_buffer_hash_size; |
8ceee660 BH |
895 | unsigned int rx_buffer_padding; |
896 | unsigned int max_interrupt_mode; | |
897 | unsigned int phys_addr_channels; | |
cc180b69 | 898 | unsigned int timer_period_max; |
0228f5cd BH |
899 | unsigned int tx_dc_base; |
900 | unsigned int rx_dc_base; | |
c8f44aff | 901 | netdev_features_t offload_features; |
8ceee660 BH |
902 | }; |
903 | ||
904 | /************************************************************************** | |
905 | * | |
906 | * Prototypes and inline functions | |
907 | * | |
908 | *************************************************************************/ | |
909 | ||
f7d12cdc BH |
910 | static inline struct efx_channel * |
911 | efx_get_channel(struct efx_nic *efx, unsigned index) | |
912 | { | |
913 | EFX_BUG_ON_PARANOID(index >= efx->n_channels); | |
8313aca3 | 914 | return efx->channel[index]; |
f7d12cdc BH |
915 | } |
916 | ||
8ceee660 BH |
917 | /* Iterate over all used channels */ |
918 | #define efx_for_each_channel(_channel, _efx) \ | |
8313aca3 BH |
919 | for (_channel = (_efx)->channel[0]; \ |
920 | _channel; \ | |
921 | _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \ | |
922 | (_efx)->channel[_channel->channel + 1] : NULL) | |
8ceee660 | 923 | |
97653431 BH |
924 | static inline struct efx_tx_queue * |
925 | efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type) | |
926 | { | |
927 | EFX_BUG_ON_PARANOID(index >= efx->n_tx_channels || | |
928 | type >= EFX_TXQ_TYPES); | |
929 | return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type]; | |
930 | } | |
f7d12cdc | 931 | |
525da907 BH |
932 | static inline bool efx_channel_has_tx_queues(struct efx_channel *channel) |
933 | { | |
934 | return channel->channel - channel->efx->tx_channel_offset < | |
935 | channel->efx->n_tx_channels; | |
936 | } | |
937 | ||
f7d12cdc BH |
938 | static inline struct efx_tx_queue * |
939 | efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type) | |
940 | { | |
525da907 BH |
941 | EFX_BUG_ON_PARANOID(!efx_channel_has_tx_queues(channel) || |
942 | type >= EFX_TXQ_TYPES); | |
943 | return &channel->tx_queue[type]; | |
f7d12cdc | 944 | } |
8ceee660 | 945 | |
94b274bf BH |
946 | static inline bool efx_tx_queue_used(struct efx_tx_queue *tx_queue) |
947 | { | |
948 | return !(tx_queue->efx->net_dev->num_tc < 2 && | |
949 | tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI); | |
950 | } | |
951 | ||
8ceee660 BH |
952 | /* Iterate over all TX queues belonging to a channel */ |
953 | #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \ | |
525da907 BH |
954 | if (!efx_channel_has_tx_queues(_channel)) \ |
955 | ; \ | |
956 | else \ | |
957 | for (_tx_queue = (_channel)->tx_queue; \ | |
94b274bf BH |
958 | _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \ |
959 | efx_tx_queue_used(_tx_queue); \ | |
525da907 | 960 | _tx_queue++) |
8ceee660 | 961 | |
94b274bf BH |
962 | /* Iterate over all possible TX queues belonging to a channel */ |
963 | #define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel) \ | |
964 | for (_tx_queue = (_channel)->tx_queue; \ | |
965 | _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \ | |
966 | _tx_queue++) | |
967 | ||
525da907 BH |
968 | static inline bool efx_channel_has_rx_queue(struct efx_channel *channel) |
969 | { | |
970 | return channel->channel < channel->efx->n_rx_channels; | |
971 | } | |
972 | ||
f7d12cdc BH |
973 | static inline struct efx_rx_queue * |
974 | efx_channel_get_rx_queue(struct efx_channel *channel) | |
975 | { | |
525da907 BH |
976 | EFX_BUG_ON_PARANOID(!efx_channel_has_rx_queue(channel)); |
977 | return &channel->rx_queue; | |
f7d12cdc BH |
978 | } |
979 | ||
8ceee660 BH |
980 | /* Iterate over all RX queues belonging to a channel */ |
981 | #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \ | |
525da907 BH |
982 | if (!efx_channel_has_rx_queue(_channel)) \ |
983 | ; \ | |
984 | else \ | |
985 | for (_rx_queue = &(_channel)->rx_queue; \ | |
986 | _rx_queue; \ | |
987 | _rx_queue = NULL) | |
8ceee660 | 988 | |
ba1e8a35 BH |
989 | static inline struct efx_channel * |
990 | efx_rx_queue_channel(struct efx_rx_queue *rx_queue) | |
991 | { | |
8313aca3 | 992 | return container_of(rx_queue, struct efx_channel, rx_queue); |
ba1e8a35 BH |
993 | } |
994 | ||
995 | static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue) | |
996 | { | |
8313aca3 | 997 | return efx_rx_queue_channel(rx_queue)->channel; |
ba1e8a35 BH |
998 | } |
999 | ||
8ceee660 BH |
1000 | /* Returns a pointer to the specified receive buffer in the RX |
1001 | * descriptor queue. | |
1002 | */ | |
1003 | static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue, | |
1004 | unsigned int index) | |
1005 | { | |
807540ba | 1006 | return &rx_queue->buffer[index]; |
8ceee660 BH |
1007 | } |
1008 | ||
1009 | /* Set bit in a little-endian bitfield */ | |
18c2fc04 | 1010 | static inline void set_bit_le(unsigned nr, unsigned char *addr) |
8ceee660 BH |
1011 | { |
1012 | addr[nr / 8] |= (1 << (nr % 8)); | |
1013 | } | |
1014 | ||
1015 | /* Clear bit in a little-endian bitfield */ | |
18c2fc04 | 1016 | static inline void clear_bit_le(unsigned nr, unsigned char *addr) |
8ceee660 BH |
1017 | { |
1018 | addr[nr / 8] &= ~(1 << (nr % 8)); | |
1019 | } | |
1020 | ||
1021 | ||
1022 | /** | |
1023 | * EFX_MAX_FRAME_LEN - calculate maximum frame length | |
1024 | * | |
1025 | * This calculates the maximum frame length that will be used for a | |
1026 | * given MTU. The frame length will be equal to the MTU plus a | |
1027 | * constant amount of header space and padding. This is the quantity | |
1028 | * that the net driver will program into the MAC as the maximum frame | |
1029 | * length. | |
1030 | * | |
754c653a | 1031 | * The 10G MAC requires 8-byte alignment on the frame |
8ceee660 | 1032 | * length, so we round up to the nearest 8. |
cc11763b BH |
1033 | * |
1034 | * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an | |
1035 | * XGMII cycle). If the frame length reaches the maximum value in the | |
1036 | * same cycle, the XMAC can miss the IPG altogether. We work around | |
1037 | * this by adding a further 16 bytes. | |
8ceee660 BH |
1038 | */ |
1039 | #define EFX_MAX_FRAME_LEN(mtu) \ | |
cc11763b | 1040 | ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16) |
8ceee660 BH |
1041 | |
1042 | ||
1043 | #endif /* EFX_NET_DRIVER_H */ |