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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
0a6f40c6 | 4 | * Copyright 2005-2011 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | /* Common definitions for all Efx net driver code */ | |
12 | ||
13 | #ifndef EFX_NET_DRIVER_H | |
14 | #define EFX_NET_DRIVER_H | |
15 | ||
8ceee660 BH |
16 | #include <linux/netdevice.h> |
17 | #include <linux/etherdevice.h> | |
18 | #include <linux/ethtool.h> | |
19 | #include <linux/if_vlan.h> | |
90d683af | 20 | #include <linux/timer.h> |
68e7f45e | 21 | #include <linux/mdio.h> |
8ceee660 BH |
22 | #include <linux/list.h> |
23 | #include <linux/pci.h> | |
24 | #include <linux/device.h> | |
25 | #include <linux/highmem.h> | |
26 | #include <linux/workqueue.h> | |
cd2d5b52 | 27 | #include <linux/mutex.h> |
10ed61c4 | 28 | #include <linux/vmalloc.h> |
37b5a603 | 29 | #include <linux/i2c.h> |
45a3fd55 | 30 | #include <linux/mtd/mtd.h> |
8ceee660 BH |
31 | |
32 | #include "enum.h" | |
33 | #include "bitfield.h" | |
add72477 | 34 | #include "filter.h" |
8ceee660 | 35 | |
8ceee660 BH |
36 | /************************************************************************** |
37 | * | |
38 | * Build definitions | |
39 | * | |
40 | **************************************************************************/ | |
c5d5f5fd | 41 | |
25ce2002 | 42 | #define EFX_DRIVER_VERSION "3.2" |
8ceee660 | 43 | |
5f3f9d6c | 44 | #ifdef DEBUG |
8ceee660 BH |
45 | #define EFX_BUG_ON_PARANOID(x) BUG_ON(x) |
46 | #define EFX_WARN_ON_PARANOID(x) WARN_ON(x) | |
47 | #else | |
48 | #define EFX_BUG_ON_PARANOID(x) do {} while (0) | |
49 | #define EFX_WARN_ON_PARANOID(x) do {} while (0) | |
50 | #endif | |
51 | ||
8ceee660 BH |
52 | /************************************************************************** |
53 | * | |
54 | * Efx data structures | |
55 | * | |
56 | **************************************************************************/ | |
57 | ||
a16e5b24 | 58 | #define EFX_MAX_CHANNELS 32U |
8ceee660 | 59 | #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS |
cd2d5b52 | 60 | #define EFX_EXTRA_CHANNEL_IOV 0 |
7c236c43 SH |
61 | #define EFX_EXTRA_CHANNEL_PTP 1 |
62 | #define EFX_MAX_EXTRA_CHANNELS 2U | |
8ceee660 | 63 | |
a4900ac9 BH |
64 | /* Checksum generation is a per-queue option in hardware, so each |
65 | * queue visible to the networking core is backed by two hardware TX | |
66 | * queues. */ | |
94b274bf BH |
67 | #define EFX_MAX_TX_TC 2 |
68 | #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS) | |
69 | #define EFX_TXQ_TYPE_OFFLOAD 1 /* flag */ | |
70 | #define EFX_TXQ_TYPE_HIGHPRI 2 /* flag */ | |
71 | #define EFX_TXQ_TYPES 4 | |
72 | #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CHANNELS) | |
60ac1065 | 73 | |
85740cdf BH |
74 | /* Maximum possible MTU the driver supports */ |
75 | #define EFX_MAX_MTU (9 * 1024) | |
76 | ||
950c54df BH |
77 | /* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page, |
78 | * and should be a multiple of the cache line size. | |
79 | */ | |
80 | #define EFX_RX_USR_BUF_SIZE (2048 - 256) | |
81 | ||
82 | /* If possible, we should ensure cache line alignment at start and end | |
83 | * of every buffer. Otherwise, we just need to ensure 4-byte | |
84 | * alignment of the network header. | |
85 | */ | |
86 | #if NET_IP_ALIGN == 0 | |
87 | #define EFX_RX_BUF_ALIGNMENT L1_CACHE_BYTES | |
88 | #else | |
89 | #define EFX_RX_BUF_ALIGNMENT 4 | |
90 | #endif | |
85740cdf | 91 | |
7c236c43 SH |
92 | /* Forward declare Precision Time Protocol (PTP) support structure. */ |
93 | struct efx_ptp_data; | |
94 | ||
d4f2cecc BH |
95 | struct efx_self_tests; |
96 | ||
8ceee660 | 97 | /** |
caa75586 BH |
98 | * struct efx_buffer - A general-purpose DMA buffer |
99 | * @addr: host base address of the buffer | |
8ceee660 BH |
100 | * @dma_addr: DMA base address of the buffer |
101 | * @len: Buffer length, in bytes | |
8ceee660 | 102 | * |
caa75586 BH |
103 | * The NIC uses these buffers for its interrupt status registers and |
104 | * MAC stats dumps. | |
8ceee660 | 105 | */ |
caa75586 | 106 | struct efx_buffer { |
8ceee660 BH |
107 | void *addr; |
108 | dma_addr_t dma_addr; | |
109 | unsigned int len; | |
caa75586 BH |
110 | }; |
111 | ||
112 | /** | |
113 | * struct efx_special_buffer - DMA buffer entered into buffer table | |
114 | * @buf: Standard &struct efx_buffer | |
115 | * @index: Buffer index within controller;s buffer table | |
116 | * @entries: Number of buffer table entries | |
117 | * | |
118 | * The NIC has a buffer table that maps buffers of size %EFX_BUF_SIZE. | |
119 | * Event and descriptor rings are addressed via one or more buffer | |
120 | * table entries (and so can be physically non-contiguous, although we | |
121 | * currently do not take advantage of that). On Falcon and Siena we | |
122 | * have to take care of allocating and initialising the entries | |
123 | * ourselves. On later hardware this is managed by the firmware and | |
124 | * @index and @entries are left as 0. | |
125 | */ | |
126 | struct efx_special_buffer { | |
127 | struct efx_buffer buf; | |
5bbe2f4f BH |
128 | unsigned int index; |
129 | unsigned int entries; | |
8ceee660 BH |
130 | }; |
131 | ||
132 | /** | |
7668ff9c BH |
133 | * struct efx_tx_buffer - buffer state for a TX descriptor |
134 | * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be | |
135 | * freed when descriptor completes | |
f7251a9c BH |
136 | * @heap_buf: When @flags & %EFX_TX_BUF_HEAP, the associated heap buffer to be |
137 | * freed when descriptor completes. | |
8ceee660 | 138 | * @dma_addr: DMA address of the fragment. |
7668ff9c | 139 | * @flags: Flags for allocation and DMA mapping type |
8ceee660 BH |
140 | * @len: Length of this fragment. |
141 | * This field is zero when the queue slot is empty. | |
8ceee660 BH |
142 | * @unmap_len: Length of this fragment to unmap |
143 | */ | |
144 | struct efx_tx_buffer { | |
7668ff9c BH |
145 | union { |
146 | const struct sk_buff *skb; | |
f7251a9c | 147 | void *heap_buf; |
7668ff9c | 148 | }; |
8ceee660 | 149 | dma_addr_t dma_addr; |
7668ff9c | 150 | unsigned short flags; |
8ceee660 | 151 | unsigned short len; |
8ceee660 BH |
152 | unsigned short unmap_len; |
153 | }; | |
7668ff9c BH |
154 | #define EFX_TX_BUF_CONT 1 /* not last descriptor of packet */ |
155 | #define EFX_TX_BUF_SKB 2 /* buffer is last part of skb */ | |
f7251a9c | 156 | #define EFX_TX_BUF_HEAP 4 /* buffer was allocated with kmalloc() */ |
7668ff9c | 157 | #define EFX_TX_BUF_MAP_SINGLE 8 /* buffer was mapped with dma_map_single() */ |
8ceee660 BH |
158 | |
159 | /** | |
160 | * struct efx_tx_queue - An Efx TX queue | |
161 | * | |
162 | * This is a ring buffer of TX fragments. | |
163 | * Since the TX completion path always executes on the same | |
164 | * CPU and the xmit path can operate on different CPUs, | |
165 | * performance is increased by ensuring that the completion | |
166 | * path and the xmit path operate on different cache lines. | |
167 | * This is particularly important if the xmit path is always | |
168 | * executing on one CPU which is different from the completion | |
169 | * path. There is also a cache line for members which are | |
170 | * read but not written on the fast path. | |
171 | * | |
172 | * @efx: The associated Efx NIC | |
173 | * @queue: DMA queue number | |
8ceee660 | 174 | * @channel: The associated channel |
c04bfc6b | 175 | * @core_txq: The networking core TX queue structure |
8ceee660 | 176 | * @buffer: The software buffer ring |
f7251a9c | 177 | * @tsoh_page: Array of pages of TSO header buffers |
8ceee660 | 178 | * @txd: The hardware descriptor ring |
ecc910f5 | 179 | * @ptr_mask: The size of the ring minus 1. |
94b274bf | 180 | * @initialised: Has hardware queue been initialised? |
8ceee660 BH |
181 | * @read_count: Current read pointer. |
182 | * This is the number of buffers that have been removed from both rings. | |
cd38557d BH |
183 | * @old_write_count: The value of @write_count when last checked. |
184 | * This is here for performance reasons. The xmit path will | |
185 | * only get the up-to-date value of @write_count if this | |
186 | * variable indicates that the queue is empty. This is to | |
187 | * avoid cache-line ping-pong between the xmit path and the | |
188 | * completion path. | |
8ceee660 BH |
189 | * @insert_count: Current insert pointer |
190 | * This is the number of buffers that have been added to the | |
191 | * software ring. | |
192 | * @write_count: Current write pointer | |
193 | * This is the number of buffers that have been added to the | |
194 | * hardware ring. | |
195 | * @old_read_count: The value of read_count when last checked. | |
196 | * This is here for performance reasons. The xmit path will | |
197 | * only get the up-to-date value of read_count if this | |
198 | * variable indicates that the queue is full. This is to | |
199 | * avoid cache-line ping-pong between the xmit path and the | |
200 | * completion path. | |
b9b39b62 BH |
201 | * @tso_bursts: Number of times TSO xmit invoked by kernel |
202 | * @tso_long_headers: Number of packets with headers too long for standard | |
203 | * blocks | |
204 | * @tso_packets: Number of packets via the TSO xmit path | |
cd38557d BH |
205 | * @pushes: Number of times the TX push feature has been used |
206 | * @empty_read_count: If the completion path has seen the queue as empty | |
207 | * and the transmission path has not yet checked this, the value of | |
208 | * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0. | |
8ceee660 BH |
209 | */ |
210 | struct efx_tx_queue { | |
211 | /* Members which don't change on the fast path */ | |
212 | struct efx_nic *efx ____cacheline_aligned_in_smp; | |
a4900ac9 | 213 | unsigned queue; |
8ceee660 | 214 | struct efx_channel *channel; |
c04bfc6b | 215 | struct netdev_queue *core_txq; |
8ceee660 | 216 | struct efx_tx_buffer *buffer; |
f7251a9c | 217 | struct efx_buffer *tsoh_page; |
8ceee660 | 218 | struct efx_special_buffer txd; |
ecc910f5 | 219 | unsigned int ptr_mask; |
94b274bf | 220 | bool initialised; |
8ceee660 BH |
221 | |
222 | /* Members used mainly on the completion path */ | |
223 | unsigned int read_count ____cacheline_aligned_in_smp; | |
cd38557d | 224 | unsigned int old_write_count; |
8ceee660 BH |
225 | |
226 | /* Members used only on the xmit path */ | |
227 | unsigned int insert_count ____cacheline_aligned_in_smp; | |
228 | unsigned int write_count; | |
229 | unsigned int old_read_count; | |
b9b39b62 BH |
230 | unsigned int tso_bursts; |
231 | unsigned int tso_long_headers; | |
232 | unsigned int tso_packets; | |
cd38557d BH |
233 | unsigned int pushes; |
234 | ||
235 | /* Members shared between paths and sometimes updated */ | |
236 | unsigned int empty_read_count ____cacheline_aligned_in_smp; | |
237 | #define EFX_EMPTY_COUNT_VALID 0x80000000 | |
525d9e82 | 238 | atomic_t flush_outstanding; |
8ceee660 BH |
239 | }; |
240 | ||
241 | /** | |
242 | * struct efx_rx_buffer - An Efx RX data buffer | |
243 | * @dma_addr: DMA base address of the buffer | |
97d48a10 | 244 | * @page: The associated page buffer. |
db339569 | 245 | * Will be %NULL if the buffer slot is currently free. |
b74e3e8c BH |
246 | * @page_offset: If pending: offset in @page of DMA base address. |
247 | * If completed: offset in @page of Ethernet header. | |
80c2e716 BH |
248 | * @len: If pending: length for DMA descriptor. |
249 | * If completed: received length, excluding hash prefix. | |
85740cdf BH |
250 | * @flags: Flags for buffer and packet state. These are only set on the |
251 | * first buffer of a scattered packet. | |
8ceee660 BH |
252 | */ |
253 | struct efx_rx_buffer { | |
254 | dma_addr_t dma_addr; | |
97d48a10 | 255 | struct page *page; |
b590ace0 BH |
256 | u16 page_offset; |
257 | u16 len; | |
db339569 | 258 | u16 flags; |
8ceee660 | 259 | }; |
179ea7f0 | 260 | #define EFX_RX_BUF_LAST_IN_PAGE 0x0001 |
db339569 BH |
261 | #define EFX_RX_PKT_CSUMMED 0x0002 |
262 | #define EFX_RX_PKT_DISCARD 0x0004 | |
d07df8ec | 263 | #define EFX_RX_PKT_TCP 0x0040 |
8ceee660 | 264 | |
62b330ba SH |
265 | /** |
266 | * struct efx_rx_page_state - Page-based rx buffer state | |
267 | * | |
268 | * Inserted at the start of every page allocated for receive buffers. | |
269 | * Used to facilitate sharing dma mappings between recycled rx buffers | |
270 | * and those passed up to the kernel. | |
271 | * | |
272 | * @refcnt: Number of struct efx_rx_buffer's referencing this page. | |
273 | * When refcnt falls to zero, the page is unmapped for dma | |
274 | * @dma_addr: The dma address of this page. | |
275 | */ | |
276 | struct efx_rx_page_state { | |
277 | unsigned refcnt; | |
278 | dma_addr_t dma_addr; | |
279 | ||
280 | unsigned int __pad[0] ____cacheline_aligned; | |
281 | }; | |
282 | ||
8ceee660 BH |
283 | /** |
284 | * struct efx_rx_queue - An Efx RX queue | |
285 | * @efx: The associated Efx NIC | |
79d68b37 SH |
286 | * @core_index: Index of network core RX queue. Will be >= 0 iff this |
287 | * is associated with a real RX queue. | |
8ceee660 BH |
288 | * @buffer: The software buffer ring |
289 | * @rxd: The hardware descriptor ring | |
ecc910f5 | 290 | * @ptr_mask: The size of the ring minus 1. |
d8aec745 | 291 | * @refill_enabled: Enable refill whenever fill level is low |
9f2cb71c BH |
292 | * @flush_pending: Set when a RX flush is pending. Has the same lifetime as |
293 | * @rxq_flush_pending. | |
8ceee660 BH |
294 | * @added_count: Number of buffers added to the receive queue. |
295 | * @notified_count: Number of buffers given to NIC (<= @added_count). | |
296 | * @removed_count: Number of buffers removed from the receive queue. | |
85740cdf | 297 | * @scatter_n: Number of buffers used by current packet |
2768935a DP |
298 | * @page_ring: The ring to store DMA mapped pages for reuse. |
299 | * @page_add: Counter to calculate the write pointer for the recycle ring. | |
300 | * @page_remove: Counter to calculate the read pointer for the recycle ring. | |
301 | * @page_recycle_count: The number of pages that have been recycled. | |
302 | * @page_recycle_failed: The number of pages that couldn't be recycled because | |
303 | * the kernel still held a reference to them. | |
304 | * @page_recycle_full: The number of pages that were released because the | |
305 | * recycle ring was full. | |
306 | * @page_ptr_mask: The number of pages in the RX recycle ring minus 1. | |
8ceee660 BH |
307 | * @max_fill: RX descriptor maximum fill level (<= ring size) |
308 | * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill | |
309 | * (<= @max_fill) | |
8ceee660 BH |
310 | * @min_fill: RX descriptor minimum non-zero fill level. |
311 | * This records the minimum fill level observed when a ring | |
312 | * refill was triggered. | |
2768935a | 313 | * @recycle_count: RX buffer recycle counter. |
90d683af | 314 | * @slow_fill: Timer used to defer efx_nic_generate_fill_event(). |
8ceee660 BH |
315 | */ |
316 | struct efx_rx_queue { | |
317 | struct efx_nic *efx; | |
79d68b37 | 318 | int core_index; |
8ceee660 BH |
319 | struct efx_rx_buffer *buffer; |
320 | struct efx_special_buffer rxd; | |
ecc910f5 | 321 | unsigned int ptr_mask; |
d8aec745 | 322 | bool refill_enabled; |
9f2cb71c | 323 | bool flush_pending; |
8ceee660 | 324 | |
9bc2fc9b BH |
325 | unsigned int added_count; |
326 | unsigned int notified_count; | |
327 | unsigned int removed_count; | |
85740cdf | 328 | unsigned int scatter_n; |
2768935a DP |
329 | struct page **page_ring; |
330 | unsigned int page_add; | |
331 | unsigned int page_remove; | |
332 | unsigned int page_recycle_count; | |
333 | unsigned int page_recycle_failed; | |
334 | unsigned int page_recycle_full; | |
335 | unsigned int page_ptr_mask; | |
8ceee660 BH |
336 | unsigned int max_fill; |
337 | unsigned int fast_fill_trigger; | |
8ceee660 BH |
338 | unsigned int min_fill; |
339 | unsigned int min_overfill; | |
2768935a | 340 | unsigned int recycle_count; |
90d683af | 341 | struct timer_list slow_fill; |
8ceee660 | 342 | unsigned int slow_fill_count; |
8ceee660 BH |
343 | }; |
344 | ||
8ceee660 BH |
345 | enum efx_rx_alloc_method { |
346 | RX_ALLOC_METHOD_AUTO = 0, | |
347 | RX_ALLOC_METHOD_SKB = 1, | |
348 | RX_ALLOC_METHOD_PAGE = 2, | |
349 | }; | |
350 | ||
351 | /** | |
352 | * struct efx_channel - An Efx channel | |
353 | * | |
354 | * A channel comprises an event queue, at least one TX queue, at least | |
355 | * one RX queue, and an associated tasklet for processing the event | |
356 | * queue. | |
357 | * | |
358 | * @efx: Associated Efx NIC | |
8ceee660 | 359 | * @channel: Channel instance number |
7f967c01 | 360 | * @type: Channel type definition |
be3fc09c | 361 | * @eventq_init: Event queue initialised flag |
8ceee660 BH |
362 | * @enabled: Channel enabled indicator |
363 | * @irq: IRQ number (MSI and MSI-X only) | |
0d86ebd8 | 364 | * @irq_moderation: IRQ moderation value (in hardware ticks) |
8ceee660 BH |
365 | * @napi_dev: Net device used with NAPI |
366 | * @napi_str: NAPI control structure | |
8ceee660 | 367 | * @eventq: Event queue buffer |
ecc910f5 | 368 | * @eventq_mask: Event queue pointer mask |
8ceee660 | 369 | * @eventq_read_ptr: Event queue read pointer |
dd40781e | 370 | * @event_test_cpu: Last CPU to handle interrupt or test event for this channel |
6fb70fd1 BH |
371 | * @irq_count: Number of IRQs since last adaptive moderation decision |
372 | * @irq_mod_score: IRQ moderation score | |
8ceee660 | 373 | * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors |
8ceee660 BH |
374 | * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors |
375 | * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors | |
c1ac403b | 376 | * @n_rx_mcast_mismatch: Count of unmatched multicast frames |
8ceee660 BH |
377 | * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors |
378 | * @n_rx_overlength: Count of RX_OVERLENGTH errors | |
379 | * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun | |
85740cdf BH |
380 | * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to |
381 | * lack of descriptors | |
382 | * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by | |
383 | * __efx_rx_packet(), or zero if there is none | |
384 | * @rx_pkt_index: Ring index of first buffer for next packet to be delivered | |
385 | * by __efx_rx_packet(), if @rx_pkt_n_frags != 0 | |
8313aca3 | 386 | * @rx_queue: RX queue for this channel |
8313aca3 | 387 | * @tx_queue: TX queues for this channel |
8ceee660 BH |
388 | */ |
389 | struct efx_channel { | |
390 | struct efx_nic *efx; | |
8ceee660 | 391 | int channel; |
7f967c01 | 392 | const struct efx_channel_type *type; |
be3fc09c | 393 | bool eventq_init; |
dc8cfa55 | 394 | bool enabled; |
8ceee660 | 395 | int irq; |
8ceee660 BH |
396 | unsigned int irq_moderation; |
397 | struct net_device *napi_dev; | |
398 | struct napi_struct napi_str; | |
8ceee660 | 399 | struct efx_special_buffer eventq; |
ecc910f5 | 400 | unsigned int eventq_mask; |
8ceee660 | 401 | unsigned int eventq_read_ptr; |
dd40781e | 402 | int event_test_cpu; |
8ceee660 | 403 | |
6fb70fd1 BH |
404 | unsigned int irq_count; |
405 | unsigned int irq_mod_score; | |
64d8ad6d BH |
406 | #ifdef CONFIG_RFS_ACCEL |
407 | unsigned int rfs_filters_added; | |
408 | #endif | |
6fb70fd1 | 409 | |
8ceee660 | 410 | unsigned n_rx_tobe_disc; |
8ceee660 BH |
411 | unsigned n_rx_ip_hdr_chksum_err; |
412 | unsigned n_rx_tcp_udp_chksum_err; | |
c1ac403b | 413 | unsigned n_rx_mcast_mismatch; |
8ceee660 BH |
414 | unsigned n_rx_frm_trunc; |
415 | unsigned n_rx_overlength; | |
416 | unsigned n_skbuff_leaks; | |
85740cdf | 417 | unsigned int n_rx_nodesc_trunc; |
8ceee660 | 418 | |
85740cdf BH |
419 | unsigned int rx_pkt_n_frags; |
420 | unsigned int rx_pkt_index; | |
8ceee660 | 421 | |
8313aca3 | 422 | struct efx_rx_queue rx_queue; |
94b274bf | 423 | struct efx_tx_queue tx_queue[EFX_TXQ_TYPES]; |
8ceee660 BH |
424 | }; |
425 | ||
d8291187 BH |
426 | /** |
427 | * struct efx_msi_context - Context for each MSI | |
428 | * @efx: The associated NIC | |
429 | * @index: Index of the channel/IRQ | |
430 | * @name: Name of the channel/IRQ | |
431 | * | |
432 | * Unlike &struct efx_channel, this is never reallocated and is always | |
433 | * safe for the IRQ handler to access. | |
434 | */ | |
435 | struct efx_msi_context { | |
436 | struct efx_nic *efx; | |
437 | unsigned int index; | |
438 | char name[IFNAMSIZ + 6]; | |
439 | }; | |
440 | ||
7f967c01 BH |
441 | /** |
442 | * struct efx_channel_type - distinguishes traffic and extra channels | |
443 | * @handle_no_channel: Handle failure to allocate an extra channel | |
444 | * @pre_probe: Set up extra state prior to initialisation | |
445 | * @post_remove: Tear down extra state after finalisation, if allocated. | |
446 | * May be called on channels that have not been probed. | |
447 | * @get_name: Generate the channel's name (used for its IRQ handler) | |
448 | * @copy: Copy the channel state prior to reallocation. May be %NULL if | |
449 | * reallocation is not supported. | |
c31e5f9f | 450 | * @receive_skb: Handle an skb ready to be passed to netif_receive_skb() |
7f967c01 BH |
451 | * @keep_eventq: Flag for whether event queue should be kept initialised |
452 | * while the device is stopped | |
453 | */ | |
454 | struct efx_channel_type { | |
455 | void (*handle_no_channel)(struct efx_nic *); | |
456 | int (*pre_probe)(struct efx_channel *); | |
c31e5f9f | 457 | void (*post_remove)(struct efx_channel *); |
7f967c01 BH |
458 | void (*get_name)(struct efx_channel *, char *buf, size_t len); |
459 | struct efx_channel *(*copy)(const struct efx_channel *); | |
4a74dc65 | 460 | bool (*receive_skb)(struct efx_channel *, struct sk_buff *); |
7f967c01 BH |
461 | bool keep_eventq; |
462 | }; | |
463 | ||
398468ed BH |
464 | enum efx_led_mode { |
465 | EFX_LED_OFF = 0, | |
466 | EFX_LED_ON = 1, | |
467 | EFX_LED_DEFAULT = 2 | |
468 | }; | |
469 | ||
c459302d BH |
470 | #define STRING_TABLE_LOOKUP(val, member) \ |
471 | ((val) < member ## _max) ? member ## _names[val] : "(invalid)" | |
472 | ||
18e83e4c | 473 | extern const char *const efx_loopback_mode_names[]; |
c459302d BH |
474 | extern const unsigned int efx_loopback_mode_max; |
475 | #define LOOPBACK_MODE(efx) \ | |
476 | STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode) | |
477 | ||
18e83e4c | 478 | extern const char *const efx_reset_type_names[]; |
c459302d BH |
479 | extern const unsigned int efx_reset_type_max; |
480 | #define RESET_TYPE(type) \ | |
481 | STRING_TABLE_LOOKUP(type, efx_reset_type) | |
3273c2e8 | 482 | |
8ceee660 BH |
483 | enum efx_int_mode { |
484 | /* Be careful if altering to correct macro below */ | |
485 | EFX_INT_MODE_MSIX = 0, | |
486 | EFX_INT_MODE_MSI = 1, | |
487 | EFX_INT_MODE_LEGACY = 2, | |
488 | EFX_INT_MODE_MAX /* Insert any new items before this */ | |
489 | }; | |
490 | #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI) | |
491 | ||
8ceee660 | 492 | enum nic_state { |
f16aeea0 BH |
493 | STATE_UNINIT = 0, /* device being probed/removed or is frozen */ |
494 | STATE_READY = 1, /* hardware ready and netdev registered */ | |
495 | STATE_DISABLED = 2, /* device disabled due to hardware errors */ | |
626950db | 496 | STATE_RECOVERY = 3, /* device recovering from PCI error */ |
8ceee660 BH |
497 | }; |
498 | ||
8ceee660 BH |
499 | /* |
500 | * Alignment of the skb->head which wraps a page-allocated RX buffer | |
501 | * | |
502 | * The skb allocated to wrap an rx_buffer can have this alignment. Since | |
503 | * the data is memcpy'd from the rx_buf, it does not need to be equal to | |
c14ff2ea | 504 | * NET_IP_ALIGN. |
8ceee660 BH |
505 | */ |
506 | #define EFX_PAGE_SKB_ALIGN 2 | |
507 | ||
508 | /* Forward declaration */ | |
509 | struct efx_nic; | |
510 | ||
511 | /* Pseudo bit-mask flow control field */ | |
b5626946 DM |
512 | #define EFX_FC_RX FLOW_CTRL_RX |
513 | #define EFX_FC_TX FLOW_CTRL_TX | |
514 | #define EFX_FC_AUTO 4 | |
8ceee660 | 515 | |
eb50c0d6 BH |
516 | /** |
517 | * struct efx_link_state - Current state of the link | |
518 | * @up: Link is up | |
519 | * @fd: Link is full-duplex | |
520 | * @fc: Actual flow control flags | |
521 | * @speed: Link speed (Mbps) | |
522 | */ | |
523 | struct efx_link_state { | |
524 | bool up; | |
525 | bool fd; | |
b5626946 | 526 | u8 fc; |
eb50c0d6 BH |
527 | unsigned int speed; |
528 | }; | |
529 | ||
fdaa9aed SH |
530 | static inline bool efx_link_state_equal(const struct efx_link_state *left, |
531 | const struct efx_link_state *right) | |
532 | { | |
533 | return left->up == right->up && left->fd == right->fd && | |
534 | left->fc == right->fc && left->speed == right->speed; | |
535 | } | |
536 | ||
8ceee660 BH |
537 | /** |
538 | * struct efx_phy_operations - Efx PHY operations table | |
c1c4f453 BH |
539 | * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds, |
540 | * efx->loopback_modes. | |
8ceee660 BH |
541 | * @init: Initialise PHY |
542 | * @fini: Shut down PHY | |
543 | * @reconfigure: Reconfigure PHY (e.g. for new link parameters) | |
fdaa9aed SH |
544 | * @poll: Update @link_state and report whether it changed. |
545 | * Serialised by the mac_lock. | |
177dfcd8 BH |
546 | * @get_settings: Get ethtool settings. Serialised by the mac_lock. |
547 | * @set_settings: Set ethtool settings. Serialised by the mac_lock. | |
af4ad9bc | 548 | * @set_npage_adv: Set abilities advertised in (Extended) Next Page |
04cc8cac | 549 | * (only needed where AN bit is set in mmds) |
4f16c073 | 550 | * @test_alive: Test that PHY is 'alive' (online) |
c1c4f453 | 551 | * @test_name: Get the name of a PHY-specific test/result |
4f16c073 | 552 | * @run_tests: Run tests and record results as appropriate (offline). |
1796721a | 553 | * Flags are the ethtool tests flags. |
8ceee660 BH |
554 | */ |
555 | struct efx_phy_operations { | |
c1c4f453 | 556 | int (*probe) (struct efx_nic *efx); |
8ceee660 BH |
557 | int (*init) (struct efx_nic *efx); |
558 | void (*fini) (struct efx_nic *efx); | |
ff3b00a0 | 559 | void (*remove) (struct efx_nic *efx); |
d3245b28 | 560 | int (*reconfigure) (struct efx_nic *efx); |
fdaa9aed | 561 | bool (*poll) (struct efx_nic *efx); |
177dfcd8 BH |
562 | void (*get_settings) (struct efx_nic *efx, |
563 | struct ethtool_cmd *ecmd); | |
564 | int (*set_settings) (struct efx_nic *efx, | |
565 | struct ethtool_cmd *ecmd); | |
af4ad9bc | 566 | void (*set_npage_adv) (struct efx_nic *efx, u32); |
4f16c073 | 567 | int (*test_alive) (struct efx_nic *efx); |
c1c4f453 | 568 | const char *(*test_name) (struct efx_nic *efx, unsigned int index); |
1796721a | 569 | int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags); |
c087bd2c SH |
570 | int (*get_module_eeprom) (struct efx_nic *efx, |
571 | struct ethtool_eeprom *ee, | |
572 | u8 *data); | |
573 | int (*get_module_info) (struct efx_nic *efx, | |
574 | struct ethtool_modinfo *modinfo); | |
8ceee660 BH |
575 | }; |
576 | ||
f8b87c17 | 577 | /** |
49ce9c2c | 578 | * enum efx_phy_mode - PHY operating mode flags |
f8b87c17 BH |
579 | * @PHY_MODE_NORMAL: on and should pass traffic |
580 | * @PHY_MODE_TX_DISABLED: on with TX disabled | |
3e133c44 BH |
581 | * @PHY_MODE_LOW_POWER: set to low power through MDIO |
582 | * @PHY_MODE_OFF: switched off through external control | |
f8b87c17 BH |
583 | * @PHY_MODE_SPECIAL: on but will not pass traffic |
584 | */ | |
585 | enum efx_phy_mode { | |
586 | PHY_MODE_NORMAL = 0, | |
587 | PHY_MODE_TX_DISABLED = 1, | |
3e133c44 BH |
588 | PHY_MODE_LOW_POWER = 2, |
589 | PHY_MODE_OFF = 4, | |
f8b87c17 BH |
590 | PHY_MODE_SPECIAL = 8, |
591 | }; | |
592 | ||
593 | static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode) | |
594 | { | |
8c8661e4 | 595 | return !!(mode & ~PHY_MODE_TX_DISABLED); |
f8b87c17 BH |
596 | } |
597 | ||
cd0ecc9a BH |
598 | /** |
599 | * struct efx_hw_stat_desc - Description of a hardware statistic | |
600 | * @name: Name of the statistic as visible through ethtool, or %NULL if | |
601 | * it should not be exposed | |
602 | * @dma_width: Width in bits (0 for non-DMA statistics) | |
603 | * @offset: Offset within stats (ignored for non-DMA statistics) | |
8ceee660 | 604 | */ |
cd0ecc9a BH |
605 | struct efx_hw_stat_desc { |
606 | const char *name; | |
607 | u16 dma_width; | |
608 | u16 offset; | |
8ceee660 BH |
609 | }; |
610 | ||
611 | /* Number of bits used in a multicast filter hash address */ | |
612 | #define EFX_MCAST_HASH_BITS 8 | |
613 | ||
614 | /* Number of (single-bit) entries in a multicast filter hash */ | |
615 | #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS) | |
616 | ||
617 | /* An Efx multicast filter hash */ | |
618 | union efx_multicast_hash { | |
619 | u8 byte[EFX_MCAST_HASH_ENTRIES / 8]; | |
620 | efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8]; | |
621 | }; | |
622 | ||
cd2d5b52 BH |
623 | struct efx_vf; |
624 | struct vfdi_status; | |
64eebcfd | 625 | |
8ceee660 BH |
626 | /** |
627 | * struct efx_nic - an Efx NIC | |
628 | * @name: Device name (net device name or bus id before net device registered) | |
629 | * @pci_dev: The PCI device | |
630 | * @type: Controller type attributes | |
631 | * @legacy_irq: IRQ number | |
8d9853d9 BH |
632 | * @workqueue: Workqueue for port reconfigures and the HW monitor. |
633 | * Work items do not hold and must not acquire RTNL. | |
6977dc63 | 634 | * @workqueue_name: Name of workqueue |
8ceee660 | 635 | * @reset_work: Scheduled reset workitem |
8ceee660 BH |
636 | * @membase_phys: Memory BAR value as physical address |
637 | * @membase: Memory BAR value | |
8ceee660 | 638 | * @interrupt_mode: Interrupt mode |
cc180b69 | 639 | * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds |
6fb70fd1 BH |
640 | * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues |
641 | * @irq_rx_moderation: IRQ moderation time for RX event queues | |
62776d03 | 642 | * @msg_enable: Log message enable flags |
f16aeea0 | 643 | * @state: Device state number (%STATE_*). Serialised by the rtnl_lock. |
a7d529ae | 644 | * @reset_pending: Bitmask for pending resets |
8ceee660 BH |
645 | * @tx_queue: TX DMA queues |
646 | * @rx_queue: RX DMA queues | |
647 | * @channel: Channels | |
d8291187 | 648 | * @msi_context: Context for each MSI |
7f967c01 BH |
649 | * @extra_channel_types: Types of extra (non-traffic) channels that |
650 | * should be allocated for this NIC | |
ecc910f5 SH |
651 | * @rxq_entries: Size of receive queues requested by user. |
652 | * @txq_entries: Size of transmit queues requested by user. | |
14bf718f BH |
653 | * @txq_stop_thresh: TX queue fill level at or above which we stop it. |
654 | * @txq_wake_thresh: TX queue fill level at or below which we wake it. | |
28e47c49 BH |
655 | * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches |
656 | * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches | |
657 | * @sram_lim_qw: Qword address limit of SRAM | |
0484e0db | 658 | * @next_buffer_table: First available buffer table id |
28b581ab | 659 | * @n_channels: Number of channels in use |
a4900ac9 BH |
660 | * @n_rx_channels: Number of channels used for RX (= number of RX queues) |
661 | * @n_tx_channels: Number of channels used for TX | |
272baeeb | 662 | * @rx_dma_len: Current maximum RX DMA length |
8ceee660 | 663 | * @rx_buffer_order: Order (log2) of number of pages for each RX buffer |
85740cdf BH |
664 | * @rx_buffer_truesize: Amortised allocation size of an RX buffer, |
665 | * for use in sk_buff::truesize | |
43a3739d JC |
666 | * @rx_prefix_size: Size of RX prefix before packet data |
667 | * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data | |
668 | * (valid only if @rx_prefix_size != 0; always negative) | |
78d4189d | 669 | * @rx_hash_key: Toeplitz hash key for RSS |
765c9f46 | 670 | * @rx_indir_table: Indirection table for RSS |
85740cdf | 671 | * @rx_scatter: Scatter mode enabled for receives |
0484e0db BH |
672 | * @int_error_count: Number of internal errors seen recently |
673 | * @int_error_expire: Time at which error count will be expired | |
d8291187 BH |
674 | * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will |
675 | * acknowledge but do nothing else. | |
8ceee660 | 676 | * @irq_status: Interrupt status buffer |
c28884c5 | 677 | * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0 |
1646a6f3 | 678 | * @irq_level: IRQ level/index for IRQs not triggered by an event queue |
dd40781e | 679 | * @selftest_work: Work item for asynchronous self-test |
76884835 | 680 | * @mtd_list: List of MTDs attached to the NIC |
25985edc | 681 | * @nic_data: Hardware dependent state |
f3ad5003 | 682 | * @mcdi: Management-Controller-to-Driver Interface state |
8c8661e4 | 683 | * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode, |
e4abce85 | 684 | * efx_monitor() and efx_reconfigure_port() |
8ceee660 | 685 | * @port_enabled: Port enabled indicator. |
fdaa9aed SH |
686 | * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and |
687 | * efx_mac_work() with kernel interfaces. Safe to read under any | |
688 | * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must | |
689 | * be held to modify it. | |
8ceee660 BH |
690 | * @port_initialized: Port initialized? |
691 | * @net_dev: Operating system network device. Consider holding the rtnl lock | |
8ceee660 | 692 | * @stats_buffer: DMA buffer for statistics |
8ceee660 | 693 | * @phy_type: PHY type |
8ceee660 BH |
694 | * @phy_op: PHY interface |
695 | * @phy_data: PHY private data (including PHY-specific stats) | |
68e7f45e | 696 | * @mdio: PHY MDIO interface |
8880f4ec | 697 | * @mdio_bus: PHY MDIO bus ID (only used by Siena) |
8c8661e4 | 698 | * @phy_mode: PHY operating mode. Serialised by @mac_lock. |
d3245b28 | 699 | * @link_advertising: Autonegotiation advertising flags |
eb50c0d6 | 700 | * @link_state: Current state of the link |
8ceee660 | 701 | * @n_link_state_changes: Number of times the link has changed state |
964e6135 BH |
702 | * @unicast_filter: Flag for Falcon-arch simple unicast filter. |
703 | * Protected by @mac_lock. | |
704 | * @multicast_hash: Multicast hash table for Falcon-arch. | |
705 | * Protected by @mac_lock. | |
04cc8cac | 706 | * @wanted_fc: Wanted flow control flags |
a606f432 SH |
707 | * @fc_disable: When non-zero flow control is disabled. Typically used to |
708 | * ensure that network back pressure doesn't delay dma queue flushes. | |
709 | * Serialised by the rtnl lock. | |
8be4f3e6 | 710 | * @mac_work: Work item for changing MAC promiscuity and multicast hash |
3273c2e8 BH |
711 | * @loopback_mode: Loopback status |
712 | * @loopback_modes: Supported loopback mode bitmask | |
713 | * @loopback_selftest: Offline self-test private state | |
6d661cec BH |
714 | * @filter_lock: Filter table lock |
715 | * @filter_state: Architecture-dependent filter table state | |
716 | * @rps_flow_id: Flow IDs of filters allocated for accelerated RFS, | |
717 | * indexed by filter ID | |
718 | * @rps_expire_index: Next index to check for expiry in @rps_flow_id | |
9f2cb71c BH |
719 | * @drain_pending: Count of RX and TX queues that haven't been flushed and drained. |
720 | * @rxq_flush_pending: Count of number of receive queues that need to be flushed. | |
721 | * Decremented when the efx_flush_rx_queue() is called. | |
722 | * @rxq_flush_outstanding: Count of number of RX flushes started but not yet | |
723 | * completed (either success or failure). Not used when MCDI is used to | |
724 | * flush receive queues. | |
725 | * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions. | |
cd2d5b52 BH |
726 | * @vf: Array of &struct efx_vf objects. |
727 | * @vf_count: Number of VFs intended to be enabled. | |
728 | * @vf_init_count: Number of VFs that have been fully initialised. | |
729 | * @vi_scale: log2 number of vnics per VF. | |
730 | * @vf_buftbl_base: The zeroth buffer table index used to back VF queues. | |
731 | * @vfdi_status: Common VFDI status page to be dmad to VF address space. | |
732 | * @local_addr_list: List of local addresses. Protected by %local_lock. | |
733 | * @local_page_list: List of DMA addressable pages used to broadcast | |
734 | * %local_addr_list. Protected by %local_lock. | |
735 | * @local_lock: Mutex protecting %local_addr_list and %local_page_list. | |
736 | * @peer_work: Work item to broadcast peer addresses to VMs. | |
7c236c43 | 737 | * @ptp_data: PTP state data |
ab28c12a BH |
738 | * @monitor_work: Hardware monitor workitem |
739 | * @biu_lock: BIU (bus interface unit) lock | |
1646a6f3 BH |
740 | * @last_irq_cpu: Last CPU to handle a possible test interrupt. This |
741 | * field is used by efx_test_interrupts() to verify that an | |
742 | * interrupt has occurred. | |
cd0ecc9a BH |
743 | * @stats_lock: Statistics update lock. Must be held when calling |
744 | * efx_nic_type::{update,start,stop}_stats. | |
8ceee660 | 745 | * |
754c653a | 746 | * This is stored in the private area of the &struct net_device. |
8ceee660 BH |
747 | */ |
748 | struct efx_nic { | |
ab28c12a BH |
749 | /* The following fields should be written very rarely */ |
750 | ||
8ceee660 BH |
751 | char name[IFNAMSIZ]; |
752 | struct pci_dev *pci_dev; | |
6602041b | 753 | unsigned int port_num; |
8ceee660 BH |
754 | const struct efx_nic_type *type; |
755 | int legacy_irq; | |
b28405b0 | 756 | bool eeh_disabled_legacy_irq; |
8ceee660 | 757 | struct workqueue_struct *workqueue; |
6977dc63 | 758 | char workqueue_name[16]; |
8ceee660 | 759 | struct work_struct reset_work; |
086ea356 | 760 | resource_size_t membase_phys; |
8ceee660 | 761 | void __iomem *membase; |
ab28c12a | 762 | |
8ceee660 | 763 | enum efx_int_mode interrupt_mode; |
cc180b69 | 764 | unsigned int timer_quantum_ns; |
6fb70fd1 BH |
765 | bool irq_rx_adaptive; |
766 | unsigned int irq_rx_moderation; | |
62776d03 | 767 | u32 msg_enable; |
8ceee660 | 768 | |
8ceee660 | 769 | enum nic_state state; |
a7d529ae | 770 | unsigned long reset_pending; |
8ceee660 | 771 | |
8313aca3 | 772 | struct efx_channel *channel[EFX_MAX_CHANNELS]; |
d8291187 | 773 | struct efx_msi_context msi_context[EFX_MAX_CHANNELS]; |
7f967c01 BH |
774 | const struct efx_channel_type * |
775 | extra_channel_type[EFX_MAX_EXTRA_CHANNELS]; | |
8ceee660 | 776 | |
ecc910f5 SH |
777 | unsigned rxq_entries; |
778 | unsigned txq_entries; | |
14bf718f BH |
779 | unsigned int txq_stop_thresh; |
780 | unsigned int txq_wake_thresh; | |
781 | ||
28e47c49 BH |
782 | unsigned tx_dc_base; |
783 | unsigned rx_dc_base; | |
784 | unsigned sram_lim_qw; | |
0484e0db | 785 | unsigned next_buffer_table; |
b105798f BH |
786 | |
787 | unsigned int max_channels; | |
a4900ac9 BH |
788 | unsigned n_channels; |
789 | unsigned n_rx_channels; | |
cd2d5b52 | 790 | unsigned rss_spread; |
97653431 | 791 | unsigned tx_channel_offset; |
a4900ac9 | 792 | unsigned n_tx_channels; |
272baeeb | 793 | unsigned int rx_dma_len; |
8ceee660 | 794 | unsigned int rx_buffer_order; |
85740cdf | 795 | unsigned int rx_buffer_truesize; |
1648a23f | 796 | unsigned int rx_page_buf_step; |
2768935a | 797 | unsigned int rx_bufs_per_page; |
1648a23f | 798 | unsigned int rx_pages_per_batch; |
43a3739d JC |
799 | unsigned int rx_prefix_size; |
800 | int rx_packet_hash_offset; | |
5d3a6fca | 801 | u8 rx_hash_key[40]; |
765c9f46 | 802 | u32 rx_indir_table[128]; |
85740cdf | 803 | bool rx_scatter; |
8ceee660 | 804 | |
0484e0db BH |
805 | unsigned int_error_count; |
806 | unsigned long int_error_expire; | |
807 | ||
d8291187 | 808 | bool irq_soft_enabled; |
8ceee660 | 809 | struct efx_buffer irq_status; |
c28884c5 | 810 | unsigned irq_zero_count; |
1646a6f3 | 811 | unsigned irq_level; |
dd40781e | 812 | struct delayed_work selftest_work; |
8ceee660 | 813 | |
76884835 BH |
814 | #ifdef CONFIG_SFC_MTD |
815 | struct list_head mtd_list; | |
816 | #endif | |
4a5b504d | 817 | |
8880f4ec | 818 | void *nic_data; |
f3ad5003 | 819 | struct efx_mcdi_data *mcdi; |
8ceee660 BH |
820 | |
821 | struct mutex mac_lock; | |
766ca0fa | 822 | struct work_struct mac_work; |
dc8cfa55 | 823 | bool port_enabled; |
8ceee660 | 824 | |
dc8cfa55 | 825 | bool port_initialized; |
8ceee660 | 826 | struct net_device *net_dev; |
8ceee660 | 827 | |
8ceee660 | 828 | struct efx_buffer stats_buffer; |
8ceee660 | 829 | |
c1c4f453 | 830 | unsigned int phy_type; |
6c8c2513 | 831 | const struct efx_phy_operations *phy_op; |
8ceee660 | 832 | void *phy_data; |
68e7f45e | 833 | struct mdio_if_info mdio; |
8880f4ec | 834 | unsigned int mdio_bus; |
f8b87c17 | 835 | enum efx_phy_mode phy_mode; |
8ceee660 | 836 | |
d3245b28 | 837 | u32 link_advertising; |
eb50c0d6 | 838 | struct efx_link_state link_state; |
8ceee660 BH |
839 | unsigned int n_link_state_changes; |
840 | ||
964e6135 | 841 | bool unicast_filter; |
8ceee660 | 842 | union efx_multicast_hash multicast_hash; |
b5626946 | 843 | u8 wanted_fc; |
a606f432 | 844 | unsigned fc_disable; |
8ceee660 BH |
845 | |
846 | atomic_t rx_reset; | |
3273c2e8 | 847 | enum efx_loopback_mode loopback_mode; |
e58f69f4 | 848 | u64 loopback_modes; |
3273c2e8 BH |
849 | |
850 | void *loopback_selftest; | |
64eebcfd | 851 | |
6d661cec BH |
852 | spinlock_t filter_lock; |
853 | void *filter_state; | |
854 | #ifdef CONFIG_RFS_ACCEL | |
855 | u32 *rps_flow_id; | |
856 | unsigned int rps_expire_index; | |
857 | #endif | |
ab28c12a | 858 | |
9f2cb71c BH |
859 | atomic_t drain_pending; |
860 | atomic_t rxq_flush_pending; | |
861 | atomic_t rxq_flush_outstanding; | |
862 | wait_queue_head_t flush_wq; | |
863 | ||
cd2d5b52 BH |
864 | #ifdef CONFIG_SFC_SRIOV |
865 | struct efx_channel *vfdi_channel; | |
866 | struct efx_vf *vf; | |
867 | unsigned vf_count; | |
868 | unsigned vf_init_count; | |
869 | unsigned vi_scale; | |
870 | unsigned vf_buftbl_base; | |
871 | struct efx_buffer vfdi_status; | |
872 | struct list_head local_addr_list; | |
873 | struct list_head local_page_list; | |
874 | struct mutex local_lock; | |
875 | struct work_struct peer_work; | |
876 | #endif | |
877 | ||
7c236c43 | 878 | struct efx_ptp_data *ptp_data; |
7c236c43 | 879 | |
ab28c12a BH |
880 | /* The following fields may be written more often */ |
881 | ||
882 | struct delayed_work monitor_work ____cacheline_aligned_in_smp; | |
883 | spinlock_t biu_lock; | |
1646a6f3 | 884 | int last_irq_cpu; |
ab28c12a | 885 | spinlock_t stats_lock; |
8ceee660 BH |
886 | }; |
887 | ||
55668611 BH |
888 | static inline int efx_dev_registered(struct efx_nic *efx) |
889 | { | |
890 | return efx->net_dev->reg_state == NETREG_REGISTERED; | |
891 | } | |
892 | ||
8880f4ec BH |
893 | static inline unsigned int efx_port_num(struct efx_nic *efx) |
894 | { | |
6602041b | 895 | return efx->port_num; |
8880f4ec BH |
896 | } |
897 | ||
45a3fd55 BH |
898 | struct efx_mtd_partition { |
899 | struct list_head node; | |
900 | struct mtd_info mtd; | |
901 | const char *dev_type_name; | |
902 | const char *type_name; | |
903 | char name[IFNAMSIZ + 20]; | |
904 | }; | |
905 | ||
8ceee660 BH |
906 | /** |
907 | * struct efx_nic_type - Efx device type definition | |
b105798f | 908 | * @mem_map_size: Get memory BAR mapped size |
ef2b90ee BH |
909 | * @probe: Probe the controller |
910 | * @remove: Free resources allocated by probe() | |
911 | * @init: Initialise the controller | |
28e47c49 BH |
912 | * @dimension_resources: Dimension controller resources (buffer table, |
913 | * and VIs once the available interrupt resources are clear) | |
ef2b90ee BH |
914 | * @fini: Shut down the controller |
915 | * @monitor: Periodic function for polling link state and hardware monitor | |
0e2a9c7c BH |
916 | * @map_reset_reason: Map ethtool reset reason to a reset method |
917 | * @map_reset_flags: Map ethtool reset flags to a reset method, if possible | |
ef2b90ee BH |
918 | * @reset: Reset the controller hardware and possibly the PHY. This will |
919 | * be called while the controller is uninitialised. | |
920 | * @probe_port: Probe the MAC and PHY | |
921 | * @remove_port: Free resources allocated by probe_port() | |
40641ed9 | 922 | * @handle_global_event: Handle a "global" event (may be %NULL) |
e42c3d85 | 923 | * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues) |
ef2b90ee | 924 | * @prepare_flush: Prepare the hardware for flushing the DMA queues |
e42c3d85 BH |
925 | * (for Falcon architecture) |
926 | * @finish_flush: Clean up after flushing the DMA queues (for Falcon | |
927 | * architecture) | |
cd0ecc9a BH |
928 | * @describe_stats: Describe statistics for ethtool |
929 | * @update_stats: Update statistics not provided by event handling. | |
930 | * Either argument may be %NULL. | |
ef2b90ee BH |
931 | * @start_stats: Start the regular fetching of statistics |
932 | * @stop_stats: Stop the regular fetching of statistics | |
06629f07 | 933 | * @set_id_led: Set state of identifying LED or revert to automatic function |
ef2b90ee | 934 | * @push_irq_moderation: Apply interrupt moderation value |
d3245b28 | 935 | * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY |
9dd3a13b | 936 | * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL) |
30b81cda BH |
937 | * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings |
938 | * to the hardware. Serialised by the mac_lock. | |
710b208d | 939 | * @check_mac_fault: Check MAC fault state. True if fault present. |
89c758fa BH |
940 | * @get_wol: Get WoL configuration from driver state |
941 | * @set_wol: Push WoL configuration to the NIC | |
942 | * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume) | |
86094f7f | 943 | * @test_chip: Test registers. May use efx_farch_test_registers(), and is |
d4f2cecc | 944 | * expected to reset the NIC. |
0aa3fbaa | 945 | * @test_nvram: Test validity of NVRAM contents |
f3ad5003 BH |
946 | * @mcdi_request: Send an MCDI request with the given header and SDU. |
947 | * The SDU length may be any value from 0 up to the protocol- | |
948 | * defined maximum, but its buffer will be padded to a multiple | |
949 | * of 4 bytes. | |
950 | * @mcdi_poll_response: Test whether an MCDI response is available. | |
951 | * @mcdi_read_response: Read the MCDI response PDU. The offset will | |
952 | * be a multiple of 4. The length may not be, but the buffer | |
953 | * will be padded so it is safe to round up. | |
954 | * @mcdi_poll_reboot: Test whether the MCDI has rebooted. If so, | |
955 | * return an appropriate error code for aborting any current | |
956 | * request; otherwise return 0. | |
86094f7f BH |
957 | * @irq_enable_master: Enable IRQs on the NIC. Each event queue must |
958 | * be separately enabled after this. | |
959 | * @irq_test_generate: Generate a test IRQ | |
960 | * @irq_disable_non_ev: Disable non-event IRQs on the NIC. Each event | |
961 | * queue must be separately disabled before this. | |
962 | * @irq_handle_msi: Handle MSI for a channel. The @dev_id argument is | |
963 | * a pointer to the &struct efx_msi_context for the channel. | |
964 | * @irq_handle_legacy: Handle legacy interrupt. The @dev_id argument | |
965 | * is a pointer to the &struct efx_nic. | |
966 | * @tx_probe: Allocate resources for TX queue | |
967 | * @tx_init: Initialise TX queue on the NIC | |
968 | * @tx_remove: Free resources for TX queue | |
969 | * @tx_write: Write TX descriptors and doorbell | |
970 | * @rx_push_indir_table: Write RSS indirection table to the NIC | |
971 | * @rx_probe: Allocate resources for RX queue | |
972 | * @rx_init: Initialise RX queue on the NIC | |
973 | * @rx_remove: Free resources for RX queue | |
974 | * @rx_write: Write RX descriptors and doorbell | |
975 | * @rx_defer_refill: Generate a refill reminder event | |
976 | * @ev_probe: Allocate resources for event queue | |
977 | * @ev_init: Initialise event queue on the NIC | |
978 | * @ev_fini: Deinitialise event queue on the NIC | |
979 | * @ev_remove: Free resources for event queue | |
980 | * @ev_process: Process events for a queue, up to the given NAPI quota | |
981 | * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ | |
982 | * @ev_test_generate: Generate a test event | |
add72477 BH |
983 | * @filter_table_probe: Probe filter capabilities and set up filter software state |
984 | * @filter_table_restore: Restore filters removed from hardware | |
985 | * @filter_table_remove: Remove filters from hardware and tear down software state | |
986 | * @filter_update_rx_scatter: Update filters after change to rx scatter setting | |
987 | * @filter_insert: add or replace a filter | |
988 | * @filter_remove_safe: remove a filter by ID, carefully | |
989 | * @filter_get_safe: retrieve a filter by ID, carefully | |
990 | * @filter_clear_rx: remove RX filters by priority | |
991 | * @filter_count_rx_used: Get the number of filters in use at a given priority | |
992 | * @filter_get_rx_id_limit: Get maximum value of a filter id, plus 1 | |
993 | * @filter_get_rx_ids: Get list of RX filters at a given priority | |
994 | * @filter_rfs_insert: Add or replace a filter for RFS. This must be | |
995 | * atomic. The hardware change may be asynchronous but should | |
996 | * not be delayed for long. It may fail if this can't be done | |
997 | * atomically. | |
998 | * @filter_rfs_expire_one: Consider expiring a filter inserted for RFS. | |
999 | * This must check whether the specified table entry is used by RFS | |
1000 | * and that rps_may_expire_flow() returns true for it. | |
45a3fd55 BH |
1001 | * @mtd_probe: Probe and add MTD partitions associated with this net device, |
1002 | * using efx_mtd_add() | |
1003 | * @mtd_rename: Set an MTD partition name using the net device name | |
1004 | * @mtd_read: Read from an MTD partition | |
1005 | * @mtd_erase: Erase part of an MTD partition | |
1006 | * @mtd_write: Write to an MTD partition | |
1007 | * @mtd_sync: Wait for write-back to complete on MTD partition. This | |
1008 | * also notifies the driver that a writer has finished using this | |
1009 | * partition. | |
daeda630 | 1010 | * @revision: Hardware architecture revision |
8ceee660 BH |
1011 | * @txd_ptr_tbl_base: TX descriptor ring base address |
1012 | * @rxd_ptr_tbl_base: RX descriptor ring base address | |
1013 | * @buf_tbl_base: Buffer table base address | |
1014 | * @evq_ptr_tbl_base: Event queue pointer table base address | |
1015 | * @evq_rptr_tbl_base: Event queue read-pointer table base address | |
8ceee660 | 1016 | * @max_dma_mask: Maximum possible DMA mask |
43a3739d JC |
1017 | * @rx_prefix_size: Size of RX prefix before packet data |
1018 | * @rx_hash_offset: Offset of RX flow hash within prefix | |
85740cdf BH |
1019 | * @rx_buffer_padding: Size of padding at end of RX packet |
1020 | * @can_rx_scatter: NIC is able to scatter packet to multiple buffers | |
8ceee660 BH |
1021 | * @max_interrupt_mode: Highest capability interrupt mode supported |
1022 | * from &enum efx_init_mode. | |
cc180b69 | 1023 | * @timer_period_max: Maximum period of interrupt timer (in ticks) |
c383b537 BH |
1024 | * @offload_features: net_device feature flags for protocol offload |
1025 | * features implemented in hardware | |
df2cd8af | 1026 | * @mcdi_max_ver: Maximum MCDI version supported |
8ceee660 BH |
1027 | */ |
1028 | struct efx_nic_type { | |
b105798f | 1029 | unsigned int (*mem_map_size)(struct efx_nic *efx); |
ef2b90ee BH |
1030 | int (*probe)(struct efx_nic *efx); |
1031 | void (*remove)(struct efx_nic *efx); | |
1032 | int (*init)(struct efx_nic *efx); | |
28e47c49 | 1033 | void (*dimension_resources)(struct efx_nic *efx); |
ef2b90ee BH |
1034 | void (*fini)(struct efx_nic *efx); |
1035 | void (*monitor)(struct efx_nic *efx); | |
0e2a9c7c BH |
1036 | enum reset_type (*map_reset_reason)(enum reset_type reason); |
1037 | int (*map_reset_flags)(u32 *flags); | |
ef2b90ee BH |
1038 | int (*reset)(struct efx_nic *efx, enum reset_type method); |
1039 | int (*probe_port)(struct efx_nic *efx); | |
1040 | void (*remove_port)(struct efx_nic *efx); | |
40641ed9 | 1041 | bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *); |
e42c3d85 | 1042 | int (*fini_dmaq)(struct efx_nic *efx); |
ef2b90ee | 1043 | void (*prepare_flush)(struct efx_nic *efx); |
d5e8cc6c | 1044 | void (*finish_flush)(struct efx_nic *efx); |
cd0ecc9a BH |
1045 | size_t (*describe_stats)(struct efx_nic *efx, u8 *names); |
1046 | size_t (*update_stats)(struct efx_nic *efx, u64 *full_stats, | |
1047 | struct rtnl_link_stats64 *core_stats); | |
ef2b90ee BH |
1048 | void (*start_stats)(struct efx_nic *efx); |
1049 | void (*stop_stats)(struct efx_nic *efx); | |
06629f07 | 1050 | void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode); |
ef2b90ee | 1051 | void (*push_irq_moderation)(struct efx_channel *channel); |
d3245b28 | 1052 | int (*reconfigure_port)(struct efx_nic *efx); |
9dd3a13b | 1053 | void (*prepare_enable_fc_tx)(struct efx_nic *efx); |
710b208d BH |
1054 | int (*reconfigure_mac)(struct efx_nic *efx); |
1055 | bool (*check_mac_fault)(struct efx_nic *efx); | |
89c758fa BH |
1056 | void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol); |
1057 | int (*set_wol)(struct efx_nic *efx, u32 type); | |
1058 | void (*resume_wol)(struct efx_nic *efx); | |
d4f2cecc | 1059 | int (*test_chip)(struct efx_nic *efx, struct efx_self_tests *tests); |
0aa3fbaa | 1060 | int (*test_nvram)(struct efx_nic *efx); |
f3ad5003 BH |
1061 | void (*mcdi_request)(struct efx_nic *efx, |
1062 | const efx_dword_t *hdr, size_t hdr_len, | |
1063 | const efx_dword_t *sdu, size_t sdu_len); | |
1064 | bool (*mcdi_poll_response)(struct efx_nic *efx); | |
1065 | void (*mcdi_read_response)(struct efx_nic *efx, efx_dword_t *pdu, | |
1066 | size_t pdu_offset, size_t pdu_len); | |
1067 | int (*mcdi_poll_reboot)(struct efx_nic *efx); | |
86094f7f BH |
1068 | void (*irq_enable_master)(struct efx_nic *efx); |
1069 | void (*irq_test_generate)(struct efx_nic *efx); | |
1070 | void (*irq_disable_non_ev)(struct efx_nic *efx); | |
1071 | irqreturn_t (*irq_handle_msi)(int irq, void *dev_id); | |
1072 | irqreturn_t (*irq_handle_legacy)(int irq, void *dev_id); | |
1073 | int (*tx_probe)(struct efx_tx_queue *tx_queue); | |
1074 | void (*tx_init)(struct efx_tx_queue *tx_queue); | |
1075 | void (*tx_remove)(struct efx_tx_queue *tx_queue); | |
1076 | void (*tx_write)(struct efx_tx_queue *tx_queue); | |
1077 | void (*rx_push_indir_table)(struct efx_nic *efx); | |
1078 | int (*rx_probe)(struct efx_rx_queue *rx_queue); | |
1079 | void (*rx_init)(struct efx_rx_queue *rx_queue); | |
1080 | void (*rx_remove)(struct efx_rx_queue *rx_queue); | |
1081 | void (*rx_write)(struct efx_rx_queue *rx_queue); | |
1082 | void (*rx_defer_refill)(struct efx_rx_queue *rx_queue); | |
1083 | int (*ev_probe)(struct efx_channel *channel); | |
1084 | void (*ev_init)(struct efx_channel *channel); | |
1085 | void (*ev_fini)(struct efx_channel *channel); | |
1086 | void (*ev_remove)(struct efx_channel *channel); | |
1087 | int (*ev_process)(struct efx_channel *channel, int quota); | |
1088 | void (*ev_read_ack)(struct efx_channel *channel); | |
1089 | void (*ev_test_generate)(struct efx_channel *channel); | |
add72477 BH |
1090 | int (*filter_table_probe)(struct efx_nic *efx); |
1091 | void (*filter_table_restore)(struct efx_nic *efx); | |
1092 | void (*filter_table_remove)(struct efx_nic *efx); | |
1093 | void (*filter_update_rx_scatter)(struct efx_nic *efx); | |
1094 | s32 (*filter_insert)(struct efx_nic *efx, | |
1095 | struct efx_filter_spec *spec, bool replace); | |
1096 | int (*filter_remove_safe)(struct efx_nic *efx, | |
1097 | enum efx_filter_priority priority, | |
1098 | u32 filter_id); | |
1099 | int (*filter_get_safe)(struct efx_nic *efx, | |
1100 | enum efx_filter_priority priority, | |
1101 | u32 filter_id, struct efx_filter_spec *); | |
1102 | void (*filter_clear_rx)(struct efx_nic *efx, | |
1103 | enum efx_filter_priority priority); | |
1104 | u32 (*filter_count_rx_used)(struct efx_nic *efx, | |
1105 | enum efx_filter_priority priority); | |
1106 | u32 (*filter_get_rx_id_limit)(struct efx_nic *efx); | |
1107 | s32 (*filter_get_rx_ids)(struct efx_nic *efx, | |
1108 | enum efx_filter_priority priority, | |
1109 | u32 *buf, u32 size); | |
1110 | #ifdef CONFIG_RFS_ACCEL | |
1111 | s32 (*filter_rfs_insert)(struct efx_nic *efx, | |
1112 | struct efx_filter_spec *spec); | |
1113 | bool (*filter_rfs_expire_one)(struct efx_nic *efx, u32 flow_id, | |
1114 | unsigned int index); | |
1115 | #endif | |
45a3fd55 BH |
1116 | #ifdef CONFIG_SFC_MTD |
1117 | int (*mtd_probe)(struct efx_nic *efx); | |
1118 | void (*mtd_rename)(struct efx_mtd_partition *part); | |
1119 | int (*mtd_read)(struct mtd_info *mtd, loff_t start, size_t len, | |
1120 | size_t *retlen, u8 *buffer); | |
1121 | int (*mtd_erase)(struct mtd_info *mtd, loff_t start, size_t len); | |
1122 | int (*mtd_write)(struct mtd_info *mtd, loff_t start, size_t len, | |
1123 | size_t *retlen, const u8 *buffer); | |
1124 | int (*mtd_sync)(struct mtd_info *mtd); | |
1125 | #endif | |
977a5d5d | 1126 | void (*ptp_write_host_time)(struct efx_nic *efx, u32 host_time); |
b895d73e | 1127 | |
daeda630 | 1128 | int revision; |
8ceee660 BH |
1129 | unsigned int txd_ptr_tbl_base; |
1130 | unsigned int rxd_ptr_tbl_base; | |
1131 | unsigned int buf_tbl_base; | |
1132 | unsigned int evq_ptr_tbl_base; | |
1133 | unsigned int evq_rptr_tbl_base; | |
9bbd7d9a | 1134 | u64 max_dma_mask; |
43a3739d JC |
1135 | unsigned int rx_prefix_size; |
1136 | unsigned int rx_hash_offset; | |
8ceee660 | 1137 | unsigned int rx_buffer_padding; |
85740cdf | 1138 | bool can_rx_scatter; |
8ceee660 | 1139 | unsigned int max_interrupt_mode; |
cc180b69 | 1140 | unsigned int timer_period_max; |
c8f44aff | 1141 | netdev_features_t offload_features; |
df2cd8af | 1142 | int mcdi_max_ver; |
add72477 | 1143 | unsigned int max_rx_ip_filters; |
8ceee660 BH |
1144 | }; |
1145 | ||
1146 | /************************************************************************** | |
1147 | * | |
1148 | * Prototypes and inline functions | |
1149 | * | |
1150 | *************************************************************************/ | |
1151 | ||
f7d12cdc BH |
1152 | static inline struct efx_channel * |
1153 | efx_get_channel(struct efx_nic *efx, unsigned index) | |
1154 | { | |
1155 | EFX_BUG_ON_PARANOID(index >= efx->n_channels); | |
8313aca3 | 1156 | return efx->channel[index]; |
f7d12cdc BH |
1157 | } |
1158 | ||
8ceee660 BH |
1159 | /* Iterate over all used channels */ |
1160 | #define efx_for_each_channel(_channel, _efx) \ | |
8313aca3 BH |
1161 | for (_channel = (_efx)->channel[0]; \ |
1162 | _channel; \ | |
1163 | _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \ | |
1164 | (_efx)->channel[_channel->channel + 1] : NULL) | |
8ceee660 | 1165 | |
7f967c01 BH |
1166 | /* Iterate over all used channels in reverse */ |
1167 | #define efx_for_each_channel_rev(_channel, _efx) \ | |
1168 | for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \ | |
1169 | _channel; \ | |
1170 | _channel = _channel->channel ? \ | |
1171 | (_efx)->channel[_channel->channel - 1] : NULL) | |
1172 | ||
97653431 BH |
1173 | static inline struct efx_tx_queue * |
1174 | efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type) | |
1175 | { | |
1176 | EFX_BUG_ON_PARANOID(index >= efx->n_tx_channels || | |
1177 | type >= EFX_TXQ_TYPES); | |
1178 | return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type]; | |
1179 | } | |
f7d12cdc | 1180 | |
525da907 BH |
1181 | static inline bool efx_channel_has_tx_queues(struct efx_channel *channel) |
1182 | { | |
1183 | return channel->channel - channel->efx->tx_channel_offset < | |
1184 | channel->efx->n_tx_channels; | |
1185 | } | |
1186 | ||
f7d12cdc BH |
1187 | static inline struct efx_tx_queue * |
1188 | efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type) | |
1189 | { | |
525da907 BH |
1190 | EFX_BUG_ON_PARANOID(!efx_channel_has_tx_queues(channel) || |
1191 | type >= EFX_TXQ_TYPES); | |
1192 | return &channel->tx_queue[type]; | |
f7d12cdc | 1193 | } |
8ceee660 | 1194 | |
94b274bf BH |
1195 | static inline bool efx_tx_queue_used(struct efx_tx_queue *tx_queue) |
1196 | { | |
1197 | return !(tx_queue->efx->net_dev->num_tc < 2 && | |
1198 | tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI); | |
1199 | } | |
1200 | ||
8ceee660 BH |
1201 | /* Iterate over all TX queues belonging to a channel */ |
1202 | #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \ | |
525da907 BH |
1203 | if (!efx_channel_has_tx_queues(_channel)) \ |
1204 | ; \ | |
1205 | else \ | |
1206 | for (_tx_queue = (_channel)->tx_queue; \ | |
94b274bf BH |
1207 | _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \ |
1208 | efx_tx_queue_used(_tx_queue); \ | |
525da907 | 1209 | _tx_queue++) |
8ceee660 | 1210 | |
94b274bf BH |
1211 | /* Iterate over all possible TX queues belonging to a channel */ |
1212 | #define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel) \ | |
73e0026f BH |
1213 | if (!efx_channel_has_tx_queues(_channel)) \ |
1214 | ; \ | |
1215 | else \ | |
1216 | for (_tx_queue = (_channel)->tx_queue; \ | |
1217 | _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \ | |
1218 | _tx_queue++) | |
94b274bf | 1219 | |
525da907 BH |
1220 | static inline bool efx_channel_has_rx_queue(struct efx_channel *channel) |
1221 | { | |
79d68b37 | 1222 | return channel->rx_queue.core_index >= 0; |
525da907 BH |
1223 | } |
1224 | ||
f7d12cdc BH |
1225 | static inline struct efx_rx_queue * |
1226 | efx_channel_get_rx_queue(struct efx_channel *channel) | |
1227 | { | |
525da907 BH |
1228 | EFX_BUG_ON_PARANOID(!efx_channel_has_rx_queue(channel)); |
1229 | return &channel->rx_queue; | |
f7d12cdc BH |
1230 | } |
1231 | ||
8ceee660 BH |
1232 | /* Iterate over all RX queues belonging to a channel */ |
1233 | #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \ | |
525da907 BH |
1234 | if (!efx_channel_has_rx_queue(_channel)) \ |
1235 | ; \ | |
1236 | else \ | |
1237 | for (_rx_queue = &(_channel)->rx_queue; \ | |
1238 | _rx_queue; \ | |
1239 | _rx_queue = NULL) | |
8ceee660 | 1240 | |
ba1e8a35 BH |
1241 | static inline struct efx_channel * |
1242 | efx_rx_queue_channel(struct efx_rx_queue *rx_queue) | |
1243 | { | |
8313aca3 | 1244 | return container_of(rx_queue, struct efx_channel, rx_queue); |
ba1e8a35 BH |
1245 | } |
1246 | ||
1247 | static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue) | |
1248 | { | |
8313aca3 | 1249 | return efx_rx_queue_channel(rx_queue)->channel; |
ba1e8a35 BH |
1250 | } |
1251 | ||
8ceee660 BH |
1252 | /* Returns a pointer to the specified receive buffer in the RX |
1253 | * descriptor queue. | |
1254 | */ | |
1255 | static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue, | |
1256 | unsigned int index) | |
1257 | { | |
807540ba | 1258 | return &rx_queue->buffer[index]; |
8ceee660 BH |
1259 | } |
1260 | ||
8ceee660 BH |
1261 | |
1262 | /** | |
1263 | * EFX_MAX_FRAME_LEN - calculate maximum frame length | |
1264 | * | |
1265 | * This calculates the maximum frame length that will be used for a | |
1266 | * given MTU. The frame length will be equal to the MTU plus a | |
1267 | * constant amount of header space and padding. This is the quantity | |
1268 | * that the net driver will program into the MAC as the maximum frame | |
1269 | * length. | |
1270 | * | |
754c653a | 1271 | * The 10G MAC requires 8-byte alignment on the frame |
8ceee660 | 1272 | * length, so we round up to the nearest 8. |
cc11763b BH |
1273 | * |
1274 | * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an | |
1275 | * XGMII cycle). If the frame length reaches the maximum value in the | |
1276 | * same cycle, the XMAC can miss the IPG altogether. We work around | |
1277 | * this by adding a further 16 bytes. | |
8ceee660 BH |
1278 | */ |
1279 | #define EFX_MAX_FRAME_LEN(mtu) \ | |
cc11763b | 1280 | ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16) |
8ceee660 | 1281 | |
7c236c43 SH |
1282 | static inline bool efx_xmit_with_hwtstamp(struct sk_buff *skb) |
1283 | { | |
1284 | return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP; | |
1285 | } | |
1286 | static inline void efx_xmit_hwtstamp_pending(struct sk_buff *skb) | |
1287 | { | |
1288 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
1289 | } | |
8ceee660 BH |
1290 | |
1291 | #endif /* EFX_NET_DRIVER_H */ |