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8ceee660 | 1 | /**************************************************************************** |
f7a6d2c4 | 2 | * Driver for Solarflare network controllers and boards |
8ceee660 | 3 | * Copyright 2005-2006 Fen Systems Ltd. |
f7a6d2c4 | 4 | * Copyright 2006-2013 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/bitops.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/seq_file.h> | |
37b5a603 | 16 | #include <linux/i2c.h> |
f31a45d2 | 17 | #include <linux/mii.h> |
5a0e3ad6 | 18 | #include <linux/slab.h> |
174cd4b1 IM |
19 | #include <linux/sched/signal.h> |
20 | ||
8ceee660 BH |
21 | #include "net_driver.h" |
22 | #include "bitfield.h" | |
23 | #include "efx.h" | |
744093c9 | 24 | #include "nic.h" |
8b8a95a1 | 25 | #include "farch_regs.h" |
12d00cad | 26 | #include "io.h" |
8ceee660 | 27 | #include "phy.h" |
8ceee660 | 28 | #include "workarounds.h" |
d4f2cecc | 29 | #include "selftest.h" |
ab0115fc | 30 | #include "mdio_10g.h" |
8ceee660 | 31 | |
8986352a | 32 | /* Hardware control for SFC4000 (aka Falcon). */ |
8ceee660 | 33 | |
ab0115fc BH |
34 | /************************************************************************** |
35 | * | |
cd0ecc9a | 36 | * NIC stats |
ab0115fc BH |
37 | * |
38 | ************************************************************************** | |
39 | */ | |
40 | ||
41 | #define FALCON_MAC_STATS_SIZE 0x100 | |
42 | ||
43 | #define XgRxOctets_offset 0x0 | |
44 | #define XgRxOctets_WIDTH 48 | |
45 | #define XgRxOctetsOK_offset 0x8 | |
46 | #define XgRxOctetsOK_WIDTH 48 | |
47 | #define XgRxPkts_offset 0x10 | |
48 | #define XgRxPkts_WIDTH 32 | |
49 | #define XgRxPktsOK_offset 0x14 | |
50 | #define XgRxPktsOK_WIDTH 32 | |
51 | #define XgRxBroadcastPkts_offset 0x18 | |
52 | #define XgRxBroadcastPkts_WIDTH 32 | |
53 | #define XgRxMulticastPkts_offset 0x1C | |
54 | #define XgRxMulticastPkts_WIDTH 32 | |
55 | #define XgRxUnicastPkts_offset 0x20 | |
56 | #define XgRxUnicastPkts_WIDTH 32 | |
57 | #define XgRxUndersizePkts_offset 0x24 | |
58 | #define XgRxUndersizePkts_WIDTH 32 | |
59 | #define XgRxOversizePkts_offset 0x28 | |
60 | #define XgRxOversizePkts_WIDTH 32 | |
61 | #define XgRxJabberPkts_offset 0x2C | |
62 | #define XgRxJabberPkts_WIDTH 32 | |
63 | #define XgRxUndersizeFCSerrorPkts_offset 0x30 | |
64 | #define XgRxUndersizeFCSerrorPkts_WIDTH 32 | |
65 | #define XgRxDropEvents_offset 0x34 | |
66 | #define XgRxDropEvents_WIDTH 32 | |
67 | #define XgRxFCSerrorPkts_offset 0x38 | |
68 | #define XgRxFCSerrorPkts_WIDTH 32 | |
69 | #define XgRxAlignError_offset 0x3C | |
70 | #define XgRxAlignError_WIDTH 32 | |
71 | #define XgRxSymbolError_offset 0x40 | |
72 | #define XgRxSymbolError_WIDTH 32 | |
73 | #define XgRxInternalMACError_offset 0x44 | |
74 | #define XgRxInternalMACError_WIDTH 32 | |
75 | #define XgRxControlPkts_offset 0x48 | |
76 | #define XgRxControlPkts_WIDTH 32 | |
77 | #define XgRxPausePkts_offset 0x4C | |
78 | #define XgRxPausePkts_WIDTH 32 | |
79 | #define XgRxPkts64Octets_offset 0x50 | |
80 | #define XgRxPkts64Octets_WIDTH 32 | |
81 | #define XgRxPkts65to127Octets_offset 0x54 | |
82 | #define XgRxPkts65to127Octets_WIDTH 32 | |
83 | #define XgRxPkts128to255Octets_offset 0x58 | |
84 | #define XgRxPkts128to255Octets_WIDTH 32 | |
85 | #define XgRxPkts256to511Octets_offset 0x5C | |
86 | #define XgRxPkts256to511Octets_WIDTH 32 | |
87 | #define XgRxPkts512to1023Octets_offset 0x60 | |
88 | #define XgRxPkts512to1023Octets_WIDTH 32 | |
89 | #define XgRxPkts1024to15xxOctets_offset 0x64 | |
90 | #define XgRxPkts1024to15xxOctets_WIDTH 32 | |
91 | #define XgRxPkts15xxtoMaxOctets_offset 0x68 | |
92 | #define XgRxPkts15xxtoMaxOctets_WIDTH 32 | |
93 | #define XgRxLengthError_offset 0x6C | |
94 | #define XgRxLengthError_WIDTH 32 | |
95 | #define XgTxPkts_offset 0x80 | |
96 | #define XgTxPkts_WIDTH 32 | |
97 | #define XgTxOctets_offset 0x88 | |
98 | #define XgTxOctets_WIDTH 48 | |
99 | #define XgTxMulticastPkts_offset 0x90 | |
100 | #define XgTxMulticastPkts_WIDTH 32 | |
101 | #define XgTxBroadcastPkts_offset 0x94 | |
102 | #define XgTxBroadcastPkts_WIDTH 32 | |
103 | #define XgTxUnicastPkts_offset 0x98 | |
104 | #define XgTxUnicastPkts_WIDTH 32 | |
105 | #define XgTxControlPkts_offset 0x9C | |
106 | #define XgTxControlPkts_WIDTH 32 | |
107 | #define XgTxPausePkts_offset 0xA0 | |
108 | #define XgTxPausePkts_WIDTH 32 | |
109 | #define XgTxPkts64Octets_offset 0xA4 | |
110 | #define XgTxPkts64Octets_WIDTH 32 | |
111 | #define XgTxPkts65to127Octets_offset 0xA8 | |
112 | #define XgTxPkts65to127Octets_WIDTH 32 | |
113 | #define XgTxPkts128to255Octets_offset 0xAC | |
114 | #define XgTxPkts128to255Octets_WIDTH 32 | |
115 | #define XgTxPkts256to511Octets_offset 0xB0 | |
116 | #define XgTxPkts256to511Octets_WIDTH 32 | |
117 | #define XgTxPkts512to1023Octets_offset 0xB4 | |
118 | #define XgTxPkts512to1023Octets_WIDTH 32 | |
119 | #define XgTxPkts1024to15xxOctets_offset 0xB8 | |
120 | #define XgTxPkts1024to15xxOctets_WIDTH 32 | |
121 | #define XgTxPkts1519toMaxOctets_offset 0xBC | |
122 | #define XgTxPkts1519toMaxOctets_WIDTH 32 | |
123 | #define XgTxUndersizePkts_offset 0xC0 | |
124 | #define XgTxUndersizePkts_WIDTH 32 | |
125 | #define XgTxOversizePkts_offset 0xC4 | |
126 | #define XgTxOversizePkts_WIDTH 32 | |
127 | #define XgTxNonTcpUdpPkt_offset 0xC8 | |
128 | #define XgTxNonTcpUdpPkt_WIDTH 16 | |
129 | #define XgTxMacSrcErrPkt_offset 0xCC | |
130 | #define XgTxMacSrcErrPkt_WIDTH 16 | |
131 | #define XgTxIpSrcErrPkt_offset 0xD0 | |
132 | #define XgTxIpSrcErrPkt_WIDTH 16 | |
133 | #define XgDmaDone_offset 0xD4 | |
134 | #define XgDmaDone_WIDTH 32 | |
135 | ||
e5136124 BH |
136 | #define FALCON_XMAC_STATS_DMA_FLAG(efx) \ |
137 | (*(u32 *)((efx)->stats_buffer.addr + XgDmaDone_offset)) | |
ab0115fc | 138 | |
cd0ecc9a BH |
139 | #define FALCON_DMA_STAT(ext_name, hw_name) \ |
140 | [FALCON_STAT_ ## ext_name] = \ | |
141 | { #ext_name, \ | |
142 | /* 48-bit stats are zero-padded to 64 on DMA */ \ | |
143 | hw_name ## _ ## WIDTH == 48 ? 64 : hw_name ## _ ## WIDTH, \ | |
144 | hw_name ## _ ## offset } | |
145 | #define FALCON_OTHER_STAT(ext_name) \ | |
146 | [FALCON_STAT_ ## ext_name] = { #ext_name, 0, 0 } | |
e4d112e4 EC |
147 | #define GENERIC_SW_STAT(ext_name) \ |
148 | [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 } | |
cd0ecc9a | 149 | |
5a6681e2 | 150 | static const struct ef4_hw_stat_desc falcon_stat_desc[FALCON_STAT_COUNT] = { |
cd0ecc9a BH |
151 | FALCON_DMA_STAT(tx_bytes, XgTxOctets), |
152 | FALCON_DMA_STAT(tx_packets, XgTxPkts), | |
153 | FALCON_DMA_STAT(tx_pause, XgTxPausePkts), | |
154 | FALCON_DMA_STAT(tx_control, XgTxControlPkts), | |
155 | FALCON_DMA_STAT(tx_unicast, XgTxUnicastPkts), | |
156 | FALCON_DMA_STAT(tx_multicast, XgTxMulticastPkts), | |
157 | FALCON_DMA_STAT(tx_broadcast, XgTxBroadcastPkts), | |
158 | FALCON_DMA_STAT(tx_lt64, XgTxUndersizePkts), | |
159 | FALCON_DMA_STAT(tx_64, XgTxPkts64Octets), | |
160 | FALCON_DMA_STAT(tx_65_to_127, XgTxPkts65to127Octets), | |
161 | FALCON_DMA_STAT(tx_128_to_255, XgTxPkts128to255Octets), | |
162 | FALCON_DMA_STAT(tx_256_to_511, XgTxPkts256to511Octets), | |
163 | FALCON_DMA_STAT(tx_512_to_1023, XgTxPkts512to1023Octets), | |
164 | FALCON_DMA_STAT(tx_1024_to_15xx, XgTxPkts1024to15xxOctets), | |
165 | FALCON_DMA_STAT(tx_15xx_to_jumbo, XgTxPkts1519toMaxOctets), | |
166 | FALCON_DMA_STAT(tx_gtjumbo, XgTxOversizePkts), | |
167 | FALCON_DMA_STAT(tx_non_tcpudp, XgTxNonTcpUdpPkt), | |
168 | FALCON_DMA_STAT(tx_mac_src_error, XgTxMacSrcErrPkt), | |
169 | FALCON_DMA_STAT(tx_ip_src_error, XgTxIpSrcErrPkt), | |
170 | FALCON_DMA_STAT(rx_bytes, XgRxOctets), | |
171 | FALCON_DMA_STAT(rx_good_bytes, XgRxOctetsOK), | |
172 | FALCON_OTHER_STAT(rx_bad_bytes), | |
173 | FALCON_DMA_STAT(rx_packets, XgRxPkts), | |
174 | FALCON_DMA_STAT(rx_good, XgRxPktsOK), | |
175 | FALCON_DMA_STAT(rx_bad, XgRxFCSerrorPkts), | |
176 | FALCON_DMA_STAT(rx_pause, XgRxPausePkts), | |
177 | FALCON_DMA_STAT(rx_control, XgRxControlPkts), | |
178 | FALCON_DMA_STAT(rx_unicast, XgRxUnicastPkts), | |
179 | FALCON_DMA_STAT(rx_multicast, XgRxMulticastPkts), | |
180 | FALCON_DMA_STAT(rx_broadcast, XgRxBroadcastPkts), | |
181 | FALCON_DMA_STAT(rx_lt64, XgRxUndersizePkts), | |
182 | FALCON_DMA_STAT(rx_64, XgRxPkts64Octets), | |
183 | FALCON_DMA_STAT(rx_65_to_127, XgRxPkts65to127Octets), | |
184 | FALCON_DMA_STAT(rx_128_to_255, XgRxPkts128to255Octets), | |
185 | FALCON_DMA_STAT(rx_256_to_511, XgRxPkts256to511Octets), | |
186 | FALCON_DMA_STAT(rx_512_to_1023, XgRxPkts512to1023Octets), | |
187 | FALCON_DMA_STAT(rx_1024_to_15xx, XgRxPkts1024to15xxOctets), | |
188 | FALCON_DMA_STAT(rx_15xx_to_jumbo, XgRxPkts15xxtoMaxOctets), | |
189 | FALCON_DMA_STAT(rx_gtjumbo, XgRxOversizePkts), | |
190 | FALCON_DMA_STAT(rx_bad_lt64, XgRxUndersizeFCSerrorPkts), | |
191 | FALCON_DMA_STAT(rx_bad_gtjumbo, XgRxJabberPkts), | |
192 | FALCON_DMA_STAT(rx_overflow, XgRxDropEvents), | |
193 | FALCON_DMA_STAT(rx_symbol_error, XgRxSymbolError), | |
194 | FALCON_DMA_STAT(rx_align_error, XgRxAlignError), | |
195 | FALCON_DMA_STAT(rx_length_error, XgRxLengthError), | |
196 | FALCON_DMA_STAT(rx_internal_error, XgRxInternalMACError), | |
197 | FALCON_OTHER_STAT(rx_nodesc_drop_cnt), | |
e4d112e4 EC |
198 | GENERIC_SW_STAT(rx_nodesc_trunc), |
199 | GENERIC_SW_STAT(rx_noskb_drops), | |
cd0ecc9a BH |
200 | }; |
201 | static const unsigned long falcon_stat_mask[] = { | |
202 | [0 ... BITS_TO_LONGS(FALCON_STAT_COUNT) - 1] = ~0UL, | |
203 | }; | |
ab0115fc BH |
204 | |
205 | /************************************************************************** | |
206 | * | |
45a3fd55 BH |
207 | * Basic SPI command set and bit definitions |
208 | * | |
209 | *************************************************************************/ | |
210 | ||
211 | #define SPI_WRSR 0x01 /* Write status register */ | |
212 | #define SPI_WRITE 0x02 /* Write data to memory array */ | |
213 | #define SPI_READ 0x03 /* Read data from memory array */ | |
214 | #define SPI_WRDI 0x04 /* Reset write enable latch */ | |
215 | #define SPI_RDSR 0x05 /* Read status register */ | |
216 | #define SPI_WREN 0x06 /* Set write enable latch */ | |
217 | #define SPI_SST_EWSR 0x50 /* SST: Enable write to status register */ | |
218 | ||
219 | #define SPI_STATUS_WPEN 0x80 /* Write-protect pin enabled */ | |
220 | #define SPI_STATUS_BP2 0x10 /* Block protection bit 2 */ | |
221 | #define SPI_STATUS_BP1 0x08 /* Block protection bit 1 */ | |
222 | #define SPI_STATUS_BP0 0x04 /* Block protection bit 0 */ | |
223 | #define SPI_STATUS_WEN 0x02 /* State of the write enable latch */ | |
224 | #define SPI_STATUS_NRDY 0x01 /* Device busy flag */ | |
225 | ||
226 | /************************************************************************** | |
227 | * | |
228 | * Non-volatile memory layout | |
ab0115fc BH |
229 | * |
230 | ************************************************************************** | |
231 | */ | |
232 | ||
45a3fd55 BH |
233 | /* SFC4000 flash is partitioned into: |
234 | * 0-0x400 chip and board config (see struct falcon_nvconfig) | |
235 | * 0x400-0x8000 unused (or may contain VPD if EEPROM not present) | |
236 | * 0x8000-end boot code (mapped to PCI expansion ROM) | |
237 | * SFC4000 small EEPROM (size < 0x400) is used for VPD only. | |
238 | * SFC4000 large EEPROM (size >= 0x400) is partitioned into: | |
239 | * 0-0x400 chip and board config | |
240 | * configurable VPD | |
241 | * 0x800-0x1800 boot config | |
242 | * Aside from the chip and board config, all of these are optional and may | |
243 | * be absent or truncated depending on the devices used. | |
244 | */ | |
245 | #define FALCON_NVCONFIG_END 0x400U | |
246 | #define FALCON_FLASH_BOOTCODE_START 0x8000U | |
247 | #define FALCON_EEPROM_BOOTCONFIG_START 0x800U | |
248 | #define FALCON_EEPROM_BOOTCONFIG_END 0x1800U | |
249 | ||
ab0115fc BH |
250 | /* Board configuration v2 (v1 is obsolete; later versions are compatible) */ |
251 | struct falcon_nvconfig_board_v2 { | |
252 | __le16 nports; | |
253 | u8 port0_phy_addr; | |
254 | u8 port0_phy_type; | |
255 | u8 port1_phy_addr; | |
256 | u8 port1_phy_type; | |
257 | __le16 asic_sub_revision; | |
258 | __le16 board_revision; | |
259 | } __packed; | |
260 | ||
261 | /* Board configuration v3 extra information */ | |
262 | struct falcon_nvconfig_board_v3 { | |
263 | __le32 spi_device_type[2]; | |
264 | } __packed; | |
265 | ||
266 | /* Bit numbers for spi_device_type */ | |
267 | #define SPI_DEV_TYPE_SIZE_LBN 0 | |
268 | #define SPI_DEV_TYPE_SIZE_WIDTH 5 | |
269 | #define SPI_DEV_TYPE_ADDR_LEN_LBN 6 | |
270 | #define SPI_DEV_TYPE_ADDR_LEN_WIDTH 2 | |
271 | #define SPI_DEV_TYPE_ERASE_CMD_LBN 8 | |
272 | #define SPI_DEV_TYPE_ERASE_CMD_WIDTH 8 | |
273 | #define SPI_DEV_TYPE_ERASE_SIZE_LBN 16 | |
274 | #define SPI_DEV_TYPE_ERASE_SIZE_WIDTH 5 | |
275 | #define SPI_DEV_TYPE_BLOCK_SIZE_LBN 24 | |
276 | #define SPI_DEV_TYPE_BLOCK_SIZE_WIDTH 5 | |
277 | #define SPI_DEV_TYPE_FIELD(type, field) \ | |
5a6681e2 | 278 | (((type) >> EF4_LOW_BIT(field)) & EF4_MASK32(EF4_WIDTH(field))) |
ab0115fc BH |
279 | |
280 | #define FALCON_NVCONFIG_OFFSET 0x300 | |
281 | ||
282 | #define FALCON_NVCONFIG_BOARD_MAGIC_NUM 0xFA1C | |
283 | struct falcon_nvconfig { | |
5a6681e2 | 284 | ef4_oword_t ee_vpd_cfg_reg; /* 0x300 */ |
ab0115fc | 285 | u8 mac_address[2][8]; /* 0x310 */ |
5a6681e2 EC |
286 | ef4_oword_t pcie_sd_ctl0123_reg; /* 0x320 */ |
287 | ef4_oword_t pcie_sd_ctl45_reg; /* 0x330 */ | |
288 | ef4_oword_t pcie_pcs_ctl_stat_reg; /* 0x340 */ | |
289 | ef4_oword_t hw_init_reg; /* 0x350 */ | |
290 | ef4_oword_t nic_stat_reg; /* 0x360 */ | |
291 | ef4_oword_t glb_ctl_reg; /* 0x370 */ | |
292 | ef4_oword_t srm_cfg_reg; /* 0x380 */ | |
293 | ef4_oword_t spare_reg; /* 0x390 */ | |
ab0115fc BH |
294 | __le16 board_magic_num; /* 0x3A0 */ |
295 | __le16 board_struct_ver; | |
296 | __le16 board_checksum; | |
297 | struct falcon_nvconfig_board_v2 board_v2; | |
5a6681e2 | 298 | ef4_oword_t ee_base_page_reg; /* 0x3B0 */ |
ab0115fc BH |
299 | struct falcon_nvconfig_board_v3 board_v3; /* 0x3C0 */ |
300 | } __packed; | |
301 | ||
302 | /*************************************************************************/ | |
303 | ||
5a6681e2 EC |
304 | static int falcon_reset_hw(struct ef4_nic *efx, enum reset_type method); |
305 | static void falcon_reconfigure_mac_wrapper(struct ef4_nic *efx); | |
d4f2cecc | 306 | |
2f7f5730 BH |
307 | static const unsigned int |
308 | /* "Large" EEPROM device: Atmel AT25640 or similar | |
309 | * 8 KB, 16-bit address, 32 B write block */ | |
310 | large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN) | |
311 | | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN) | |
312 | | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)), | |
313 | /* Default flash device: Atmel AT25F1024 | |
314 | * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */ | |
315 | default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN) | |
316 | | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN) | |
317 | | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN) | |
318 | | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN) | |
319 | | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)); | |
320 | ||
8ceee660 BH |
321 | /************************************************************************** |
322 | * | |
323 | * I2C bus - this is a bit-bashing interface using GPIO pins | |
324 | * Note that it uses the output enables to tristate the outputs | |
325 | * SDA is the data pin and SCL is the clock | |
326 | * | |
327 | ************************************************************************** | |
328 | */ | |
37b5a603 | 329 | static void falcon_setsda(void *data, int state) |
8ceee660 | 330 | { |
5a6681e2 EC |
331 | struct ef4_nic *efx = (struct ef4_nic *)data; |
332 | ef4_oword_t reg; | |
8ceee660 | 333 | |
5a6681e2 EC |
334 | ef4_reado(efx, ®, FR_AB_GPIO_CTL); |
335 | EF4_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state); | |
336 | ef4_writeo(efx, ®, FR_AB_GPIO_CTL); | |
8ceee660 BH |
337 | } |
338 | ||
37b5a603 | 339 | static void falcon_setscl(void *data, int state) |
8ceee660 | 340 | { |
5a6681e2 EC |
341 | struct ef4_nic *efx = (struct ef4_nic *)data; |
342 | ef4_oword_t reg; | |
8ceee660 | 343 | |
5a6681e2 EC |
344 | ef4_reado(efx, ®, FR_AB_GPIO_CTL); |
345 | EF4_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state); | |
346 | ef4_writeo(efx, ®, FR_AB_GPIO_CTL); | |
37b5a603 BH |
347 | } |
348 | ||
8e730c15 BH |
349 | static int falcon_getsda(void *data) |
350 | { | |
5a6681e2 EC |
351 | struct ef4_nic *efx = (struct ef4_nic *)data; |
352 | ef4_oword_t reg; | |
8ceee660 | 353 | |
5a6681e2 EC |
354 | ef4_reado(efx, ®, FR_AB_GPIO_CTL); |
355 | return EF4_OWORD_FIELD(reg, FRF_AB_GPIO3_IN); | |
8e730c15 | 356 | } |
8ceee660 | 357 | |
8e730c15 BH |
358 | static int falcon_getscl(void *data) |
359 | { | |
5a6681e2 EC |
360 | struct ef4_nic *efx = (struct ef4_nic *)data; |
361 | ef4_oword_t reg; | |
8ceee660 | 362 | |
5a6681e2 EC |
363 | ef4_reado(efx, ®, FR_AB_GPIO_CTL); |
364 | return EF4_OWORD_FIELD(reg, FRF_AB_GPIO0_IN); | |
8ceee660 BH |
365 | } |
366 | ||
18e83e4c | 367 | static const struct i2c_algo_bit_data falcon_i2c_bit_operations = { |
8e730c15 BH |
368 | .setsda = falcon_setsda, |
369 | .setscl = falcon_setscl, | |
370 | .getsda = falcon_getsda, | |
371 | .getscl = falcon_getscl, | |
372 | .udelay = 5, | |
373 | /* Wait up to 50 ms for slave to let us pull SCL high */ | |
374 | .timeout = DIV_ROUND_UP(HZ, 20), | |
375 | }; | |
376 | ||
5a6681e2 | 377 | static void falcon_push_irq_moderation(struct ef4_channel *channel) |
8ceee660 | 378 | { |
5a6681e2 EC |
379 | ef4_dword_t timer_cmd; |
380 | struct ef4_nic *efx = channel->efx; | |
8ceee660 BH |
381 | |
382 | /* Set timer register */ | |
539de7c5 BK |
383 | if (channel->irq_moderation_us) { |
384 | unsigned int ticks; | |
385 | ||
5a6681e2 EC |
386 | ticks = ef4_usecs_to_ticks(efx, channel->irq_moderation_us); |
387 | EF4_POPULATE_DWORD_2(timer_cmd, | |
3e6c4538 BH |
388 | FRF_AB_TC_TIMER_MODE, |
389 | FFE_BB_TIMER_MODE_INT_HLDOFF, | |
390 | FRF_AB_TC_TIMER_VAL, | |
539de7c5 | 391 | ticks - 1); |
8ceee660 | 392 | } else { |
5a6681e2 | 393 | EF4_POPULATE_DWORD_2(timer_cmd, |
3e6c4538 BH |
394 | FRF_AB_TC_TIMER_MODE, |
395 | FFE_BB_TIMER_MODE_DIS, | |
396 | FRF_AB_TC_TIMER_VAL, 0); | |
8ceee660 | 397 | } |
3e6c4538 | 398 | BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0); |
5a6681e2 | 399 | ef4_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0, |
12d00cad | 400 | channel->channel); |
127e6e10 BH |
401 | } |
402 | ||
5a6681e2 | 403 | static void falcon_deconfigure_mac_wrapper(struct ef4_nic *efx); |
d3245b28 | 404 | |
5a6681e2 | 405 | static void falcon_prepare_flush(struct ef4_nic *efx) |
127e6e10 BH |
406 | { |
407 | falcon_deconfigure_mac_wrapper(efx); | |
408 | ||
409 | /* Wait for the tx and rx fifo's to get to the next packet boundary | |
410 | * (~1ms without back-pressure), then to drain the remainder of the | |
411 | * fifo's at data path speeds (negligible), with a healthy margin. */ | |
412 | msleep(10); | |
6bc5d3a9 BH |
413 | } |
414 | ||
8ceee660 BH |
415 | /* Acknowledge a legacy interrupt from Falcon |
416 | * | |
417 | * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG. | |
418 | * | |
419 | * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the | |
420 | * BIU. Interrupt acknowledge is read sensitive so must write instead | |
421 | * (then read to ensure the BIU collector is flushed) | |
422 | * | |
423 | * NB most hardware supports MSI interrupts | |
424 | */ | |
5a6681e2 | 425 | static inline void falcon_irq_ack_a1(struct ef4_nic *efx) |
8ceee660 | 426 | { |
5a6681e2 | 427 | ef4_dword_t reg; |
8ceee660 | 428 | |
5a6681e2 EC |
429 | EF4_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e); |
430 | ef4_writed(efx, ®, FR_AA_INT_ACK_KER); | |
431 | ef4_readd(efx, ®, FR_AA_WORK_AROUND_BROKEN_PCI_READS); | |
8ceee660 BH |
432 | } |
433 | ||
86094f7f | 434 | static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id) |
8ceee660 | 435 | { |
5a6681e2 EC |
436 | struct ef4_nic *efx = dev_id; |
437 | ef4_oword_t *int_ker = efx->irq_status.addr; | |
8ceee660 BH |
438 | int syserr; |
439 | int queues; | |
440 | ||
441 | /* Check to see if this is our interrupt. If it isn't, we | |
442 | * exit without having touched the hardware. | |
443 | */ | |
5a6681e2 | 444 | if (unlikely(EF4_OWORD_IS_ZERO(*int_ker))) { |
62776d03 BH |
445 | netif_vdbg(efx, intr, efx->net_dev, |
446 | "IRQ %d on CPU %d not for me\n", irq, | |
447 | raw_smp_processor_id()); | |
8ceee660 BH |
448 | return IRQ_NONE; |
449 | } | |
450 | efx->last_irq_cpu = raw_smp_processor_id(); | |
62776d03 | 451 | netif_vdbg(efx, intr, efx->net_dev, |
5a6681e2 EC |
452 | "IRQ %d on CPU %d status " EF4_OWORD_FMT "\n", |
453 | irq, raw_smp_processor_id(), EF4_OWORD_VAL(*int_ker)); | |
8ceee660 | 454 | |
d8291187 BH |
455 | if (!likely(ACCESS_ONCE(efx->irq_soft_enabled))) |
456 | return IRQ_HANDLED; | |
457 | ||
f70d1847 | 458 | /* Check to see if we have a serious error condition */ |
5a6681e2 | 459 | syserr = EF4_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); |
f70d1847 | 460 | if (unlikely(syserr)) |
5a6681e2 | 461 | return ef4_farch_fatal_interrupt(efx); |
f70d1847 | 462 | |
8ceee660 BH |
463 | /* Determine interrupting queues, clear interrupt status |
464 | * register and acknowledge the device interrupt. | |
465 | */ | |
5a6681e2 EC |
466 | BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EF4_MAX_CHANNELS); |
467 | queues = EF4_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q); | |
468 | EF4_ZERO_OWORD(*int_ker); | |
8ceee660 BH |
469 | wmb(); /* Ensure the vector is cleared before interrupt ack */ |
470 | falcon_irq_ack_a1(efx); | |
471 | ||
8313aca3 | 472 | if (queues & 1) |
5a6681e2 | 473 | ef4_schedule_channel_irq(ef4_get_channel(efx, 0)); |
8313aca3 | 474 | if (queues & 2) |
5a6681e2 | 475 | ef4_schedule_channel_irq(ef4_get_channel(efx, 1)); |
8ceee660 BH |
476 | return IRQ_HANDLED; |
477 | } | |
5b3b7608 | 478 | |
d43050c0 AR |
479 | /************************************************************************** |
480 | * | |
481 | * RSS | |
482 | * | |
483 | ************************************************************************** | |
484 | */ | |
5a6681e2 | 485 | static int dummy_rx_push_rss_config(struct ef4_nic *efx, bool user, |
267c0157 JC |
486 | const u32 *rx_indir_table) |
487 | { | |
488 | (void) efx; | |
489 | (void) user; | |
490 | (void) rx_indir_table; | |
491 | return -ENOSYS; | |
492 | } | |
d43050c0 | 493 | |
5a6681e2 | 494 | static int falcon_b0_rx_push_rss_config(struct ef4_nic *efx, bool user, |
267c0157 | 495 | const u32 *rx_indir_table) |
d43050c0 | 496 | { |
5a6681e2 | 497 | ef4_oword_t temp; |
d43050c0 | 498 | |
267c0157 | 499 | (void) user; |
d43050c0 AR |
500 | /* Set hash key for IPv4 */ |
501 | memcpy(&temp, efx->rx_hash_key, sizeof(temp)); | |
5a6681e2 | 502 | ef4_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY); |
d43050c0 | 503 | |
267c0157 JC |
504 | memcpy(efx->rx_indir_table, rx_indir_table, |
505 | sizeof(efx->rx_indir_table)); | |
5a6681e2 | 506 | ef4_farch_rx_push_indir_table(efx); |
267c0157 | 507 | return 0; |
d43050c0 AR |
508 | } |
509 | ||
8ceee660 BH |
510 | /************************************************************************** |
511 | * | |
512 | * EEPROM/flash | |
513 | * | |
514 | ************************************************************************** | |
515 | */ | |
516 | ||
5a6681e2 | 517 | #define FALCON_SPI_MAX_LEN sizeof(ef4_oword_t) |
8ceee660 | 518 | |
5a6681e2 | 519 | static int falcon_spi_poll(struct ef4_nic *efx) |
be4ea89c | 520 | { |
5a6681e2 EC |
521 | ef4_oword_t reg; |
522 | ef4_reado(efx, ®, FR_AB_EE_SPI_HCMD); | |
523 | return EF4_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0; | |
be4ea89c BH |
524 | } |
525 | ||
8ceee660 | 526 | /* Wait for SPI command completion */ |
5a6681e2 | 527 | static int falcon_spi_wait(struct ef4_nic *efx) |
8ceee660 | 528 | { |
be4ea89c BH |
529 | /* Most commands will finish quickly, so we start polling at |
530 | * very short intervals. Sometimes the command may have to | |
531 | * wait for VPD or expansion ROM access outside of our | |
532 | * control, so we allow up to 100 ms. */ | |
533 | unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10); | |
534 | int i; | |
535 | ||
536 | for (i = 0; i < 10; i++) { | |
537 | if (!falcon_spi_poll(efx)) | |
538 | return 0; | |
539 | udelay(10); | |
540 | } | |
8ceee660 | 541 | |
4a5b504d | 542 | for (;;) { |
be4ea89c | 543 | if (!falcon_spi_poll(efx)) |
8ceee660 | 544 | return 0; |
4a5b504d | 545 | if (time_after_eq(jiffies, timeout)) { |
62776d03 BH |
546 | netif_err(efx, hw, efx->net_dev, |
547 | "timed out waiting for SPI\n"); | |
4a5b504d BH |
548 | return -ETIMEDOUT; |
549 | } | |
be4ea89c | 550 | schedule_timeout_uninterruptible(1); |
4a5b504d | 551 | } |
8ceee660 BH |
552 | } |
553 | ||
45a3fd55 | 554 | static int |
5a6681e2 | 555 | falcon_spi_cmd(struct ef4_nic *efx, const struct falcon_spi_device *spi, |
45a3fd55 BH |
556 | unsigned int command, int address, |
557 | const void *in, void *out, size_t len) | |
8ceee660 | 558 | { |
4a5b504d BH |
559 | bool addressed = (address >= 0); |
560 | bool reading = (out != NULL); | |
5a6681e2 | 561 | ef4_oword_t reg; |
8ceee660 BH |
562 | int rc; |
563 | ||
4a5b504d BH |
564 | /* Input validation */ |
565 | if (len > FALCON_SPI_MAX_LEN) | |
566 | return -EINVAL; | |
8ceee660 | 567 | |
be4ea89c BH |
568 | /* Check that previous command is not still running */ |
569 | rc = falcon_spi_poll(efx); | |
8ceee660 BH |
570 | if (rc) |
571 | return rc; | |
572 | ||
4a5b504d BH |
573 | /* Program address register, if we have an address */ |
574 | if (addressed) { | |
5a6681e2 EC |
575 | EF4_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address); |
576 | ef4_writeo(efx, ®, FR_AB_EE_SPI_HADR); | |
4a5b504d BH |
577 | } |
578 | ||
579 | /* Program data register, if we have data */ | |
580 | if (in != NULL) { | |
581 | memcpy(®, in, len); | |
5a6681e2 | 582 | ef4_writeo(efx, ®, FR_AB_EE_SPI_HDATA); |
4a5b504d | 583 | } |
8ceee660 | 584 | |
4a5b504d | 585 | /* Issue read/write command */ |
5a6681e2 | 586 | EF4_POPULATE_OWORD_7(reg, |
3e6c4538 BH |
587 | FRF_AB_EE_SPI_HCMD_CMD_EN, 1, |
588 | FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id, | |
589 | FRF_AB_EE_SPI_HCMD_DABCNT, len, | |
590 | FRF_AB_EE_SPI_HCMD_READ, reading, | |
591 | FRF_AB_EE_SPI_HCMD_DUBCNT, 0, | |
592 | FRF_AB_EE_SPI_HCMD_ADBCNT, | |
4a5b504d | 593 | (addressed ? spi->addr_len : 0), |
3e6c4538 | 594 | FRF_AB_EE_SPI_HCMD_ENC, command); |
5a6681e2 | 595 | ef4_writeo(efx, ®, FR_AB_EE_SPI_HCMD); |
8ceee660 | 596 | |
4a5b504d | 597 | /* Wait for read/write to complete */ |
8ceee660 BH |
598 | rc = falcon_spi_wait(efx); |
599 | if (rc) | |
600 | return rc; | |
601 | ||
602 | /* Read data */ | |
4a5b504d | 603 | if (out != NULL) { |
5a6681e2 | 604 | ef4_reado(efx, ®, FR_AB_EE_SPI_HDATA); |
4a5b504d BH |
605 | memcpy(out, ®, len); |
606 | } | |
607 | ||
8ceee660 BH |
608 | return 0; |
609 | } | |
610 | ||
4a5b504d | 611 | static inline u8 |
ecd0a6f0 BH |
612 | falcon_spi_munge_command(const struct falcon_spi_device *spi, |
613 | const u8 command, const unsigned int address) | |
4a5b504d BH |
614 | { |
615 | return command | (((address >> 8) & spi->munge_address) << 3); | |
616 | } | |
617 | ||
45a3fd55 | 618 | static int |
5a6681e2 | 619 | falcon_spi_read(struct ef4_nic *efx, const struct falcon_spi_device *spi, |
45a3fd55 | 620 | loff_t start, size_t len, size_t *retlen, u8 *buffer) |
4a5b504d | 621 | { |
23d30f02 BH |
622 | size_t block_len, pos = 0; |
623 | unsigned int command; | |
4a5b504d BH |
624 | int rc = 0; |
625 | ||
626 | while (pos < len) { | |
23d30f02 | 627 | block_len = min(len - pos, FALCON_SPI_MAX_LEN); |
4a5b504d | 628 | |
ecd0a6f0 | 629 | command = falcon_spi_munge_command(spi, SPI_READ, start + pos); |
76884835 | 630 | rc = falcon_spi_cmd(efx, spi, command, start + pos, NULL, |
4a5b504d BH |
631 | buffer + pos, block_len); |
632 | if (rc) | |
633 | break; | |
634 | pos += block_len; | |
635 | ||
636 | /* Avoid locking up the system */ | |
637 | cond_resched(); | |
638 | if (signal_pending(current)) { | |
639 | rc = -EINTR; | |
640 | break; | |
641 | } | |
642 | } | |
643 | ||
644 | if (retlen) | |
645 | *retlen = pos; | |
646 | return rc; | |
647 | } | |
648 | ||
5a6681e2 | 649 | #ifdef CONFIG_SFC_FALCON_MTD |
45a3fd55 BH |
650 | |
651 | struct falcon_mtd_partition { | |
5a6681e2 | 652 | struct ef4_mtd_partition common; |
45a3fd55 BH |
653 | const struct falcon_spi_device *spi; |
654 | size_t offset; | |
655 | }; | |
656 | ||
657 | #define to_falcon_mtd_partition(mtd) \ | |
658 | container_of(mtd, struct falcon_mtd_partition, common.mtd) | |
659 | ||
660 | static size_t | |
661 | falcon_spi_write_limit(const struct falcon_spi_device *spi, size_t start) | |
662 | { | |
663 | return min(FALCON_SPI_MAX_LEN, | |
664 | (spi->block_size - (start & (spi->block_size - 1)))); | |
665 | } | |
666 | ||
667 | /* Wait up to 10 ms for buffered write completion */ | |
668 | static int | |
5a6681e2 | 669 | falcon_spi_wait_write(struct ef4_nic *efx, const struct falcon_spi_device *spi) |
45a3fd55 BH |
670 | { |
671 | unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100); | |
672 | u8 status; | |
673 | int rc; | |
674 | ||
675 | for (;;) { | |
676 | rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL, | |
677 | &status, sizeof(status)); | |
678 | if (rc) | |
679 | return rc; | |
680 | if (!(status & SPI_STATUS_NRDY)) | |
681 | return 0; | |
682 | if (time_after_eq(jiffies, timeout)) { | |
683 | netif_err(efx, hw, efx->net_dev, | |
684 | "SPI write timeout on device %d" | |
685 | " last status=0x%02x\n", | |
686 | spi->device_id, status); | |
687 | return -ETIMEDOUT; | |
688 | } | |
689 | schedule_timeout_uninterruptible(1); | |
690 | } | |
691 | } | |
692 | ||
693 | static int | |
5a6681e2 | 694 | falcon_spi_write(struct ef4_nic *efx, const struct falcon_spi_device *spi, |
76884835 | 695 | loff_t start, size_t len, size_t *retlen, const u8 *buffer) |
4a5b504d BH |
696 | { |
697 | u8 verify_buffer[FALCON_SPI_MAX_LEN]; | |
23d30f02 BH |
698 | size_t block_len, pos = 0; |
699 | unsigned int command; | |
4a5b504d BH |
700 | int rc = 0; |
701 | ||
702 | while (pos < len) { | |
76884835 | 703 | rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0); |
4a5b504d BH |
704 | if (rc) |
705 | break; | |
706 | ||
23d30f02 | 707 | block_len = min(len - pos, |
4a5b504d | 708 | falcon_spi_write_limit(spi, start + pos)); |
ecd0a6f0 | 709 | command = falcon_spi_munge_command(spi, SPI_WRITE, start + pos); |
76884835 | 710 | rc = falcon_spi_cmd(efx, spi, command, start + pos, |
4a5b504d BH |
711 | buffer + pos, NULL, block_len); |
712 | if (rc) | |
713 | break; | |
714 | ||
76884835 | 715 | rc = falcon_spi_wait_write(efx, spi); |
4a5b504d BH |
716 | if (rc) |
717 | break; | |
718 | ||
ecd0a6f0 | 719 | command = falcon_spi_munge_command(spi, SPI_READ, start + pos); |
76884835 | 720 | rc = falcon_spi_cmd(efx, spi, command, start + pos, |
4a5b504d BH |
721 | NULL, verify_buffer, block_len); |
722 | if (memcmp(verify_buffer, buffer + pos, block_len)) { | |
723 | rc = -EIO; | |
724 | break; | |
725 | } | |
726 | ||
727 | pos += block_len; | |
728 | ||
729 | /* Avoid locking up the system */ | |
730 | cond_resched(); | |
731 | if (signal_pending(current)) { | |
732 | rc = -EINTR; | |
733 | break; | |
734 | } | |
735 | } | |
736 | ||
737 | if (retlen) | |
738 | *retlen = pos; | |
739 | return rc; | |
740 | } | |
741 | ||
45a3fd55 BH |
742 | static int |
743 | falcon_spi_slow_wait(struct falcon_mtd_partition *part, bool uninterruptible) | |
744 | { | |
745 | const struct falcon_spi_device *spi = part->spi; | |
5a6681e2 | 746 | struct ef4_nic *efx = part->common.mtd.priv; |
45a3fd55 BH |
747 | u8 status; |
748 | int rc, i; | |
749 | ||
750 | /* Wait up to 4s for flash/EEPROM to finish a slow operation. */ | |
751 | for (i = 0; i < 40; i++) { | |
752 | __set_current_state(uninterruptible ? | |
753 | TASK_UNINTERRUPTIBLE : TASK_INTERRUPTIBLE); | |
754 | schedule_timeout(HZ / 10); | |
755 | rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL, | |
756 | &status, sizeof(status)); | |
757 | if (rc) | |
758 | return rc; | |
759 | if (!(status & SPI_STATUS_NRDY)) | |
760 | return 0; | |
761 | if (signal_pending(current)) | |
762 | return -EINTR; | |
763 | } | |
764 | pr_err("%s: timed out waiting for %s\n", | |
765 | part->common.name, part->common.dev_type_name); | |
766 | return -ETIMEDOUT; | |
767 | } | |
768 | ||
769 | static int | |
5a6681e2 | 770 | falcon_spi_unlock(struct ef4_nic *efx, const struct falcon_spi_device *spi) |
45a3fd55 BH |
771 | { |
772 | const u8 unlock_mask = (SPI_STATUS_BP2 | SPI_STATUS_BP1 | | |
773 | SPI_STATUS_BP0); | |
774 | u8 status; | |
775 | int rc; | |
776 | ||
777 | rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL, | |
778 | &status, sizeof(status)); | |
779 | if (rc) | |
780 | return rc; | |
781 | ||
782 | if (!(status & unlock_mask)) | |
783 | return 0; /* already unlocked */ | |
784 | ||
785 | rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0); | |
786 | if (rc) | |
787 | return rc; | |
788 | rc = falcon_spi_cmd(efx, spi, SPI_SST_EWSR, -1, NULL, NULL, 0); | |
789 | if (rc) | |
790 | return rc; | |
791 | ||
792 | status &= ~unlock_mask; | |
793 | rc = falcon_spi_cmd(efx, spi, SPI_WRSR, -1, &status, | |
794 | NULL, sizeof(status)); | |
795 | if (rc) | |
796 | return rc; | |
797 | rc = falcon_spi_wait_write(efx, spi); | |
798 | if (rc) | |
799 | return rc; | |
800 | ||
801 | return 0; | |
802 | } | |
803 | ||
804 | #define FALCON_SPI_VERIFY_BUF_LEN 16 | |
805 | ||
806 | static int | |
807 | falcon_spi_erase(struct falcon_mtd_partition *part, loff_t start, size_t len) | |
808 | { | |
809 | const struct falcon_spi_device *spi = part->spi; | |
5a6681e2 | 810 | struct ef4_nic *efx = part->common.mtd.priv; |
45a3fd55 BH |
811 | unsigned pos, block_len; |
812 | u8 empty[FALCON_SPI_VERIFY_BUF_LEN]; | |
813 | u8 buffer[FALCON_SPI_VERIFY_BUF_LEN]; | |
814 | int rc; | |
815 | ||
816 | if (len != spi->erase_size) | |
817 | return -EINVAL; | |
818 | ||
819 | if (spi->erase_command == 0) | |
820 | return -EOPNOTSUPP; | |
821 | ||
822 | rc = falcon_spi_unlock(efx, spi); | |
823 | if (rc) | |
824 | return rc; | |
825 | rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0); | |
826 | if (rc) | |
827 | return rc; | |
828 | rc = falcon_spi_cmd(efx, spi, spi->erase_command, start, NULL, | |
829 | NULL, 0); | |
830 | if (rc) | |
831 | return rc; | |
832 | rc = falcon_spi_slow_wait(part, false); | |
833 | ||
834 | /* Verify the entire region has been wiped */ | |
835 | memset(empty, 0xff, sizeof(empty)); | |
836 | for (pos = 0; pos < len; pos += block_len) { | |
837 | block_len = min(len - pos, sizeof(buffer)); | |
838 | rc = falcon_spi_read(efx, spi, start + pos, block_len, | |
839 | NULL, buffer); | |
840 | if (rc) | |
841 | return rc; | |
842 | if (memcmp(empty, buffer, block_len)) | |
843 | return -EIO; | |
844 | ||
845 | /* Avoid locking up the system */ | |
846 | cond_resched(); | |
847 | if (signal_pending(current)) | |
848 | return -EINTR; | |
849 | } | |
850 | ||
851 | return rc; | |
852 | } | |
853 | ||
5a6681e2 | 854 | static void falcon_mtd_rename(struct ef4_mtd_partition *part) |
45a3fd55 | 855 | { |
5a6681e2 | 856 | struct ef4_nic *efx = part->mtd.priv; |
45a3fd55 BH |
857 | |
858 | snprintf(part->name, sizeof(part->name), "%s %s", | |
859 | efx->name, part->type_name); | |
860 | } | |
861 | ||
862 | static int falcon_mtd_read(struct mtd_info *mtd, loff_t start, | |
863 | size_t len, size_t *retlen, u8 *buffer) | |
864 | { | |
865 | struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd); | |
5a6681e2 | 866 | struct ef4_nic *efx = mtd->priv; |
45a3fd55 BH |
867 | struct falcon_nic_data *nic_data = efx->nic_data; |
868 | int rc; | |
869 | ||
870 | rc = mutex_lock_interruptible(&nic_data->spi_lock); | |
871 | if (rc) | |
872 | return rc; | |
873 | rc = falcon_spi_read(efx, part->spi, part->offset + start, | |
874 | len, retlen, buffer); | |
875 | mutex_unlock(&nic_data->spi_lock); | |
876 | return rc; | |
877 | } | |
878 | ||
879 | static int falcon_mtd_erase(struct mtd_info *mtd, loff_t start, size_t len) | |
880 | { | |
881 | struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd); | |
5a6681e2 | 882 | struct ef4_nic *efx = mtd->priv; |
45a3fd55 BH |
883 | struct falcon_nic_data *nic_data = efx->nic_data; |
884 | int rc; | |
885 | ||
886 | rc = mutex_lock_interruptible(&nic_data->spi_lock); | |
887 | if (rc) | |
888 | return rc; | |
889 | rc = falcon_spi_erase(part, part->offset + start, len); | |
890 | mutex_unlock(&nic_data->spi_lock); | |
891 | return rc; | |
892 | } | |
893 | ||
894 | static int falcon_mtd_write(struct mtd_info *mtd, loff_t start, | |
895 | size_t len, size_t *retlen, const u8 *buffer) | |
896 | { | |
897 | struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd); | |
5a6681e2 | 898 | struct ef4_nic *efx = mtd->priv; |
45a3fd55 BH |
899 | struct falcon_nic_data *nic_data = efx->nic_data; |
900 | int rc; | |
901 | ||
902 | rc = mutex_lock_interruptible(&nic_data->spi_lock); | |
903 | if (rc) | |
904 | return rc; | |
905 | rc = falcon_spi_write(efx, part->spi, part->offset + start, | |
906 | len, retlen, buffer); | |
907 | mutex_unlock(&nic_data->spi_lock); | |
908 | return rc; | |
909 | } | |
910 | ||
911 | static int falcon_mtd_sync(struct mtd_info *mtd) | |
912 | { | |
913 | struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd); | |
5a6681e2 | 914 | struct ef4_nic *efx = mtd->priv; |
45a3fd55 BH |
915 | struct falcon_nic_data *nic_data = efx->nic_data; |
916 | int rc; | |
917 | ||
918 | mutex_lock(&nic_data->spi_lock); | |
919 | rc = falcon_spi_slow_wait(part, true); | |
920 | mutex_unlock(&nic_data->spi_lock); | |
921 | return rc; | |
922 | } | |
923 | ||
5a6681e2 | 924 | static int falcon_mtd_probe(struct ef4_nic *efx) |
45a3fd55 BH |
925 | { |
926 | struct falcon_nic_data *nic_data = efx->nic_data; | |
927 | struct falcon_mtd_partition *parts; | |
928 | struct falcon_spi_device *spi; | |
929 | size_t n_parts; | |
930 | int rc = -ENODEV; | |
931 | ||
932 | ASSERT_RTNL(); | |
933 | ||
934 | /* Allocate space for maximum number of partitions */ | |
935 | parts = kcalloc(2, sizeof(*parts), GFP_KERNEL); | |
42a5a5c1 DC |
936 | if (!parts) |
937 | return -ENOMEM; | |
45a3fd55 BH |
938 | n_parts = 0; |
939 | ||
940 | spi = &nic_data->spi_flash; | |
941 | if (falcon_spi_present(spi) && spi->size > FALCON_FLASH_BOOTCODE_START) { | |
942 | parts[n_parts].spi = spi; | |
943 | parts[n_parts].offset = FALCON_FLASH_BOOTCODE_START; | |
944 | parts[n_parts].common.dev_type_name = "flash"; | |
945 | parts[n_parts].common.type_name = "sfc_flash_bootrom"; | |
946 | parts[n_parts].common.mtd.type = MTD_NORFLASH; | |
947 | parts[n_parts].common.mtd.flags = MTD_CAP_NORFLASH; | |
948 | parts[n_parts].common.mtd.size = spi->size - FALCON_FLASH_BOOTCODE_START; | |
949 | parts[n_parts].common.mtd.erasesize = spi->erase_size; | |
950 | n_parts++; | |
951 | } | |
952 | ||
953 | spi = &nic_data->spi_eeprom; | |
954 | if (falcon_spi_present(spi) && spi->size > FALCON_EEPROM_BOOTCONFIG_START) { | |
955 | parts[n_parts].spi = spi; | |
956 | parts[n_parts].offset = FALCON_EEPROM_BOOTCONFIG_START; | |
957 | parts[n_parts].common.dev_type_name = "EEPROM"; | |
958 | parts[n_parts].common.type_name = "sfc_bootconfig"; | |
959 | parts[n_parts].common.mtd.type = MTD_RAM; | |
960 | parts[n_parts].common.mtd.flags = MTD_CAP_RAM; | |
961 | parts[n_parts].common.mtd.size = | |
962 | min(spi->size, FALCON_EEPROM_BOOTCONFIG_END) - | |
963 | FALCON_EEPROM_BOOTCONFIG_START; | |
964 | parts[n_parts].common.mtd.erasesize = spi->erase_size; | |
965 | n_parts++; | |
966 | } | |
967 | ||
5a6681e2 | 968 | rc = ef4_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts)); |
45a3fd55 BH |
969 | if (rc) |
970 | kfree(parts); | |
971 | return rc; | |
972 | } | |
973 | ||
5a6681e2 | 974 | #endif /* CONFIG_SFC_FALCON_MTD */ |
45a3fd55 | 975 | |
ab0115fc BH |
976 | /************************************************************************** |
977 | * | |
978 | * XMAC operations | |
979 | * | |
980 | ************************************************************************** | |
981 | */ | |
982 | ||
983 | /* Configure the XAUI driver that is an output from Falcon */ | |
5a6681e2 | 984 | static void falcon_setup_xaui(struct ef4_nic *efx) |
ab0115fc | 985 | { |
5a6681e2 | 986 | ef4_oword_t sdctl, txdrv; |
ab0115fc BH |
987 | |
988 | /* Move the XAUI into low power, unless there is no PHY, in | |
989 | * which case the XAUI will have to drive a cable. */ | |
990 | if (efx->phy_type == PHY_TYPE_NONE) | |
991 | return; | |
992 | ||
5a6681e2 EC |
993 | ef4_reado(efx, &sdctl, FR_AB_XX_SD_CTL); |
994 | EF4_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVD, FFE_AB_XX_SD_CTL_DRV_DEF); | |
995 | EF4_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVD, FFE_AB_XX_SD_CTL_DRV_DEF); | |
996 | EF4_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVC, FFE_AB_XX_SD_CTL_DRV_DEF); | |
997 | EF4_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVC, FFE_AB_XX_SD_CTL_DRV_DEF); | |
998 | EF4_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVB, FFE_AB_XX_SD_CTL_DRV_DEF); | |
999 | EF4_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVB, FFE_AB_XX_SD_CTL_DRV_DEF); | |
1000 | EF4_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVA, FFE_AB_XX_SD_CTL_DRV_DEF); | |
1001 | EF4_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVA, FFE_AB_XX_SD_CTL_DRV_DEF); | |
1002 | ef4_writeo(efx, &sdctl, FR_AB_XX_SD_CTL); | |
1003 | ||
1004 | EF4_POPULATE_OWORD_8(txdrv, | |
ab0115fc BH |
1005 | FRF_AB_XX_DEQD, FFE_AB_XX_TXDRV_DEQ_DEF, |
1006 | FRF_AB_XX_DEQC, FFE_AB_XX_TXDRV_DEQ_DEF, | |
1007 | FRF_AB_XX_DEQB, FFE_AB_XX_TXDRV_DEQ_DEF, | |
1008 | FRF_AB_XX_DEQA, FFE_AB_XX_TXDRV_DEQ_DEF, | |
1009 | FRF_AB_XX_DTXD, FFE_AB_XX_TXDRV_DTX_DEF, | |
1010 | FRF_AB_XX_DTXC, FFE_AB_XX_TXDRV_DTX_DEF, | |
1011 | FRF_AB_XX_DTXB, FFE_AB_XX_TXDRV_DTX_DEF, | |
1012 | FRF_AB_XX_DTXA, FFE_AB_XX_TXDRV_DTX_DEF); | |
5a6681e2 | 1013 | ef4_writeo(efx, &txdrv, FR_AB_XX_TXDRV_CTL); |
ab0115fc BH |
1014 | } |
1015 | ||
5a6681e2 | 1016 | int falcon_reset_xaui(struct ef4_nic *efx) |
ab0115fc BH |
1017 | { |
1018 | struct falcon_nic_data *nic_data = efx->nic_data; | |
5a6681e2 | 1019 | ef4_oword_t reg; |
ab0115fc BH |
1020 | int count; |
1021 | ||
1022 | /* Don't fetch MAC statistics over an XMAC reset */ | |
1023 | WARN_ON(nic_data->stats_disable_count == 0); | |
1024 | ||
1025 | /* Start reset sequence */ | |
5a6681e2 EC |
1026 | EF4_POPULATE_OWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1); |
1027 | ef4_writeo(efx, ®, FR_AB_XX_PWR_RST); | |
ab0115fc BH |
1028 | |
1029 | /* Wait up to 10 ms for completion, then reinitialise */ | |
1030 | for (count = 0; count < 1000; count++) { | |
5a6681e2 EC |
1031 | ef4_reado(efx, ®, FR_AB_XX_PWR_RST); |
1032 | if (EF4_OWORD_FIELD(reg, FRF_AB_XX_RST_XX_EN) == 0 && | |
1033 | EF4_OWORD_FIELD(reg, FRF_AB_XX_SD_RST_ACT) == 0) { | |
ab0115fc BH |
1034 | falcon_setup_xaui(efx); |
1035 | return 0; | |
1036 | } | |
1037 | udelay(10); | |
1038 | } | |
1039 | netif_err(efx, hw, efx->net_dev, | |
1040 | "timed out waiting for XAUI/XGXS reset\n"); | |
1041 | return -ETIMEDOUT; | |
1042 | } | |
1043 | ||
5a6681e2 | 1044 | static void falcon_ack_status_intr(struct ef4_nic *efx) |
ab0115fc BH |
1045 | { |
1046 | struct falcon_nic_data *nic_data = efx->nic_data; | |
5a6681e2 | 1047 | ef4_oword_t reg; |
ab0115fc | 1048 | |
5a6681e2 | 1049 | if ((ef4_nic_rev(efx) != EF4_REV_FALCON_B0) || LOOPBACK_INTERNAL(efx)) |
ab0115fc BH |
1050 | return; |
1051 | ||
1052 | /* We expect xgmii faults if the wireside link is down */ | |
ab3b8250 | 1053 | if (!efx->link_state.up) |
ab0115fc BH |
1054 | return; |
1055 | ||
1056 | /* We can only use this interrupt to signal the negative edge of | |
1057 | * xaui_align [we have to poll the positive edge]. */ | |
1058 | if (nic_data->xmac_poll_required) | |
1059 | return; | |
1060 | ||
5a6681e2 | 1061 | ef4_reado(efx, ®, FR_AB_XM_MGT_INT_MSK); |
ab0115fc BH |
1062 | } |
1063 | ||
5a6681e2 | 1064 | static bool falcon_xgxs_link_ok(struct ef4_nic *efx) |
ab0115fc | 1065 | { |
5a6681e2 | 1066 | ef4_oword_t reg; |
ab0115fc BH |
1067 | bool align_done, link_ok = false; |
1068 | int sync_status; | |
1069 | ||
1070 | /* Read link status */ | |
5a6681e2 | 1071 | ef4_reado(efx, ®, FR_AB_XX_CORE_STAT); |
ab0115fc | 1072 | |
5a6681e2 EC |
1073 | align_done = EF4_OWORD_FIELD(reg, FRF_AB_XX_ALIGN_DONE); |
1074 | sync_status = EF4_OWORD_FIELD(reg, FRF_AB_XX_SYNC_STAT); | |
ab0115fc BH |
1075 | if (align_done && (sync_status == FFE_AB_XX_STAT_ALL_LANES)) |
1076 | link_ok = true; | |
1077 | ||
1078 | /* Clear link status ready for next read */ | |
5a6681e2 EC |
1079 | EF4_SET_OWORD_FIELD(reg, FRF_AB_XX_COMMA_DET, FFE_AB_XX_STAT_ALL_LANES); |
1080 | EF4_SET_OWORD_FIELD(reg, FRF_AB_XX_CHAR_ERR, FFE_AB_XX_STAT_ALL_LANES); | |
1081 | EF4_SET_OWORD_FIELD(reg, FRF_AB_XX_DISPERR, FFE_AB_XX_STAT_ALL_LANES); | |
1082 | ef4_writeo(efx, ®, FR_AB_XX_CORE_STAT); | |
ab0115fc BH |
1083 | |
1084 | return link_ok; | |
1085 | } | |
1086 | ||
5a6681e2 | 1087 | static bool falcon_xmac_link_ok(struct ef4_nic *efx) |
ab0115fc BH |
1088 | { |
1089 | /* | |
1090 | * Check MAC's XGXS link status except when using XGMII loopback | |
1091 | * which bypasses the XGXS block. | |
1092 | * If possible, check PHY's XGXS link status except when using | |
1093 | * MAC loopback. | |
1094 | */ | |
1095 | return (efx->loopback_mode == LOOPBACK_XGMII || | |
1096 | falcon_xgxs_link_ok(efx)) && | |
1097 | (!(efx->mdio.mmds & (1 << MDIO_MMD_PHYXS)) || | |
1098 | LOOPBACK_INTERNAL(efx) || | |
5a6681e2 | 1099 | ef4_mdio_phyxgxs_lane_sync(efx)); |
ab0115fc BH |
1100 | } |
1101 | ||
5a6681e2 | 1102 | static void falcon_reconfigure_xmac_core(struct ef4_nic *efx) |
ab0115fc BH |
1103 | { |
1104 | unsigned int max_frame_len; | |
5a6681e2 EC |
1105 | ef4_oword_t reg; |
1106 | bool rx_fc = !!(efx->link_state.fc & EF4_FC_RX); | |
1107 | bool tx_fc = !!(efx->link_state.fc & EF4_FC_TX); | |
ab0115fc BH |
1108 | |
1109 | /* Configure MAC - cut-thru mode is hard wired on */ | |
5a6681e2 | 1110 | EF4_POPULATE_OWORD_3(reg, |
ab0115fc BH |
1111 | FRF_AB_XM_RX_JUMBO_MODE, 1, |
1112 | FRF_AB_XM_TX_STAT_EN, 1, | |
1113 | FRF_AB_XM_RX_STAT_EN, 1); | |
5a6681e2 | 1114 | ef4_writeo(efx, ®, FR_AB_XM_GLB_CFG); |
ab0115fc BH |
1115 | |
1116 | /* Configure TX */ | |
5a6681e2 | 1117 | EF4_POPULATE_OWORD_6(reg, |
ab0115fc BH |
1118 | FRF_AB_XM_TXEN, 1, |
1119 | FRF_AB_XM_TX_PRMBL, 1, | |
1120 | FRF_AB_XM_AUTO_PAD, 1, | |
1121 | FRF_AB_XM_TXCRC, 1, | |
1122 | FRF_AB_XM_FCNTL, tx_fc, | |
1123 | FRF_AB_XM_IPG, 0x3); | |
5a6681e2 | 1124 | ef4_writeo(efx, ®, FR_AB_XM_TX_CFG); |
ab0115fc BH |
1125 | |
1126 | /* Configure RX */ | |
5a6681e2 | 1127 | EF4_POPULATE_OWORD_5(reg, |
ab0115fc BH |
1128 | FRF_AB_XM_RXEN, 1, |
1129 | FRF_AB_XM_AUTO_DEPAD, 0, | |
1130 | FRF_AB_XM_ACPT_ALL_MCAST, 1, | |
964e6135 | 1131 | FRF_AB_XM_ACPT_ALL_UCAST, !efx->unicast_filter, |
ab0115fc | 1132 | FRF_AB_XM_PASS_CRC_ERR, 1); |
5a6681e2 | 1133 | ef4_writeo(efx, ®, FR_AB_XM_RX_CFG); |
ab0115fc BH |
1134 | |
1135 | /* Set frame length */ | |
5a6681e2 EC |
1136 | max_frame_len = EF4_MAX_FRAME_LEN(efx->net_dev->mtu); |
1137 | EF4_POPULATE_OWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len); | |
1138 | ef4_writeo(efx, ®, FR_AB_XM_RX_PARAM); | |
1139 | EF4_POPULATE_OWORD_2(reg, | |
ab0115fc BH |
1140 | FRF_AB_XM_MAX_TX_FRM_SIZE, max_frame_len, |
1141 | FRF_AB_XM_TX_JUMBO_MODE, 1); | |
5a6681e2 | 1142 | ef4_writeo(efx, ®, FR_AB_XM_TX_PARAM); |
ab0115fc | 1143 | |
5a6681e2 | 1144 | EF4_POPULATE_OWORD_2(reg, |
ab0115fc BH |
1145 | FRF_AB_XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */ |
1146 | FRF_AB_XM_DIS_FCNTL, !rx_fc); | |
5a6681e2 | 1147 | ef4_writeo(efx, ®, FR_AB_XM_FC); |
ab0115fc BH |
1148 | |
1149 | /* Set MAC address */ | |
1150 | memcpy(®, &efx->net_dev->dev_addr[0], 4); | |
5a6681e2 | 1151 | ef4_writeo(efx, ®, FR_AB_XM_ADR_LO); |
ab0115fc | 1152 | memcpy(®, &efx->net_dev->dev_addr[4], 2); |
5a6681e2 | 1153 | ef4_writeo(efx, ®, FR_AB_XM_ADR_HI); |
ab0115fc BH |
1154 | } |
1155 | ||
5a6681e2 | 1156 | static void falcon_reconfigure_xgxs_core(struct ef4_nic *efx) |
ab0115fc | 1157 | { |
5a6681e2 | 1158 | ef4_oword_t reg; |
ab0115fc BH |
1159 | bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS); |
1160 | bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI); | |
1161 | bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII); | |
ab3b8250 | 1162 | bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback; |
ab0115fc BH |
1163 | |
1164 | /* XGXS block is flaky and will need to be reset if moving | |
1165 | * into our out of XGMII, XGXS or XAUI loopbacks. */ | |
5a6681e2 EC |
1166 | ef4_reado(efx, ®, FR_AB_XX_CORE_STAT); |
1167 | old_xgxs_loopback = EF4_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN); | |
1168 | old_xgmii_loopback = EF4_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN); | |
ab0115fc | 1169 | |
5a6681e2 EC |
1170 | ef4_reado(efx, ®, FR_AB_XX_SD_CTL); |
1171 | old_xaui_loopback = EF4_OWORD_FIELD(reg, FRF_AB_XX_LPBKA); | |
ab0115fc | 1172 | |
ab3b8250 BH |
1173 | /* The PHY driver may have turned XAUI off */ |
1174 | if ((xgxs_loopback != old_xgxs_loopback) || | |
1175 | (xaui_loopback != old_xaui_loopback) || | |
1176 | (xgmii_loopback != old_xgmii_loopback)) | |
1177 | falcon_reset_xaui(efx); | |
ab0115fc | 1178 | |
5a6681e2 EC |
1179 | ef4_reado(efx, ®, FR_AB_XX_CORE_STAT); |
1180 | EF4_SET_OWORD_FIELD(reg, FRF_AB_XX_FORCE_SIG, | |
ab0115fc BH |
1181 | (xgxs_loopback || xaui_loopback) ? |
1182 | FFE_AB_XX_FORCE_SIG_ALL_LANES : 0); | |
5a6681e2 EC |
1183 | EF4_SET_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN, xgxs_loopback); |
1184 | EF4_SET_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN, xgmii_loopback); | |
1185 | ef4_writeo(efx, ®, FR_AB_XX_CORE_STAT); | |
ab0115fc | 1186 | |
5a6681e2 EC |
1187 | ef4_reado(efx, ®, FR_AB_XX_SD_CTL); |
1188 | EF4_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKD, xaui_loopback); | |
1189 | EF4_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKC, xaui_loopback); | |
1190 | EF4_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKB, xaui_loopback); | |
1191 | EF4_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKA, xaui_loopback); | |
1192 | ef4_writeo(efx, ®, FR_AB_XX_SD_CTL); | |
ab0115fc BH |
1193 | } |
1194 | ||
1195 | ||
1196 | /* Try to bring up the Falcon side of the Falcon-Phy XAUI link */ | |
5a6681e2 | 1197 | static bool falcon_xmac_link_ok_retry(struct ef4_nic *efx, int tries) |
ab0115fc BH |
1198 | { |
1199 | bool mac_up = falcon_xmac_link_ok(efx); | |
1200 | ||
1201 | if (LOOPBACK_MASK(efx) & LOOPBACKS_EXTERNAL(efx) & LOOPBACKS_WS || | |
5a6681e2 | 1202 | ef4_phy_mode_disabled(efx->phy_mode)) |
ab0115fc BH |
1203 | /* XAUI link is expected to be down */ |
1204 | return mac_up; | |
1205 | ||
1206 | falcon_stop_nic_stats(efx); | |
1207 | ||
1208 | while (!mac_up && tries) { | |
1209 | netif_dbg(efx, hw, efx->net_dev, "bashing xaui\n"); | |
1210 | falcon_reset_xaui(efx); | |
1211 | udelay(200); | |
1212 | ||
1213 | mac_up = falcon_xmac_link_ok(efx); | |
1214 | --tries; | |
1215 | } | |
1216 | ||
1217 | falcon_start_nic_stats(efx); | |
1218 | ||
1219 | return mac_up; | |
1220 | } | |
1221 | ||
5a6681e2 | 1222 | static bool falcon_xmac_check_fault(struct ef4_nic *efx) |
ab0115fc BH |
1223 | { |
1224 | return !falcon_xmac_link_ok_retry(efx, 5); | |
1225 | } | |
1226 | ||
5a6681e2 | 1227 | static int falcon_reconfigure_xmac(struct ef4_nic *efx) |
ab0115fc BH |
1228 | { |
1229 | struct falcon_nic_data *nic_data = efx->nic_data; | |
1230 | ||
5a6681e2 | 1231 | ef4_farch_filter_sync_rx_mode(efx); |
964e6135 | 1232 | |
ab0115fc BH |
1233 | falcon_reconfigure_xgxs_core(efx); |
1234 | falcon_reconfigure_xmac_core(efx); | |
1235 | ||
1236 | falcon_reconfigure_mac_wrapper(efx); | |
1237 | ||
1238 | nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 5); | |
1239 | falcon_ack_status_intr(efx); | |
1240 | ||
1241 | return 0; | |
1242 | } | |
1243 | ||
5a6681e2 | 1244 | static void falcon_poll_xmac(struct ef4_nic *efx) |
ab0115fc BH |
1245 | { |
1246 | struct falcon_nic_data *nic_data = efx->nic_data; | |
1247 | ||
ab3b8250 BH |
1248 | /* We expect xgmii faults if the wireside link is down */ |
1249 | if (!efx->link_state.up || !nic_data->xmac_poll_required) | |
ab0115fc BH |
1250 | return; |
1251 | ||
1252 | nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 1); | |
1253 | falcon_ack_status_intr(efx); | |
1254 | } | |
1255 | ||
8ceee660 BH |
1256 | /************************************************************************** |
1257 | * | |
1258 | * MAC wrapper | |
1259 | * | |
1260 | ************************************************************************** | |
1261 | */ | |
177dfcd8 | 1262 | |
5a6681e2 | 1263 | static void falcon_push_multicast_hash(struct ef4_nic *efx) |
ef2b90ee | 1264 | { |
5a6681e2 | 1265 | union ef4_multicast_hash *mc_hash = &efx->multicast_hash; |
ef2b90ee BH |
1266 | |
1267 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | |
1268 | ||
5a6681e2 EC |
1269 | ef4_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0); |
1270 | ef4_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1); | |
ef2b90ee BH |
1271 | } |
1272 | ||
5a6681e2 | 1273 | static void falcon_reset_macs(struct ef4_nic *efx) |
8ceee660 | 1274 | { |
d3245b28 | 1275 | struct falcon_nic_data *nic_data = efx->nic_data; |
5a6681e2 | 1276 | ef4_oword_t reg, mac_ctrl; |
8ceee660 BH |
1277 | int count; |
1278 | ||
5a6681e2 | 1279 | if (ef4_nic_rev(efx) < EF4_REV_FALCON_B0) { |
177dfcd8 BH |
1280 | /* It's not safe to use GLB_CTL_REG to reset the |
1281 | * macs, so instead use the internal MAC resets | |
1282 | */ | |
5a6681e2 EC |
1283 | EF4_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1); |
1284 | ef4_writeo(efx, ®, FR_AB_XM_GLB_CFG); | |
8fbca791 BH |
1285 | |
1286 | for (count = 0; count < 10000; count++) { | |
5a6681e2 EC |
1287 | ef4_reado(efx, ®, FR_AB_XM_GLB_CFG); |
1288 | if (EF4_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) == | |
8fbca791 BH |
1289 | 0) |
1290 | return; | |
1291 | udelay(10); | |
177dfcd8 | 1292 | } |
8fbca791 BH |
1293 | |
1294 | netif_err(efx, hw, efx->net_dev, | |
1295 | "timed out waiting for XMAC core reset\n"); | |
177dfcd8 | 1296 | } |
8ceee660 | 1297 | |
d3245b28 BH |
1298 | /* Mac stats will fail whist the TX fifo is draining */ |
1299 | WARN_ON(nic_data->stats_disable_count == 0); | |
8ceee660 | 1300 | |
5a6681e2 EC |
1301 | ef4_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL); |
1302 | EF4_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1); | |
1303 | ef4_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL); | |
8ceee660 | 1304 | |
5a6681e2 EC |
1305 | ef4_reado(efx, ®, FR_AB_GLB_CTL); |
1306 | EF4_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1); | |
1307 | EF4_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1); | |
1308 | EF4_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1); | |
1309 | ef4_writeo(efx, ®, FR_AB_GLB_CTL); | |
8ceee660 BH |
1310 | |
1311 | count = 0; | |
1312 | while (1) { | |
5a6681e2 EC |
1313 | ef4_reado(efx, ®, FR_AB_GLB_CTL); |
1314 | if (!EF4_OWORD_FIELD(reg, FRF_AB_RST_XGTX) && | |
1315 | !EF4_OWORD_FIELD(reg, FRF_AB_RST_XGRX) && | |
1316 | !EF4_OWORD_FIELD(reg, FRF_AB_RST_EM)) { | |
62776d03 BH |
1317 | netif_dbg(efx, hw, efx->net_dev, |
1318 | "Completed MAC reset after %d loops\n", | |
1319 | count); | |
8ceee660 BH |
1320 | break; |
1321 | } | |
1322 | if (count > 20) { | |
62776d03 | 1323 | netif_err(efx, hw, efx->net_dev, "MAC reset failed\n"); |
8ceee660 BH |
1324 | break; |
1325 | } | |
1326 | count++; | |
1327 | udelay(10); | |
1328 | } | |
1329 | ||
d3245b28 BH |
1330 | /* Ensure the correct MAC is selected before statistics |
1331 | * are re-enabled by the caller */ | |
5a6681e2 | 1332 | ef4_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL); |
b7b40eeb | 1333 | |
b7b40eeb | 1334 | falcon_setup_xaui(efx); |
177dfcd8 BH |
1335 | } |
1336 | ||
5a6681e2 | 1337 | static void falcon_drain_tx_fifo(struct ef4_nic *efx) |
177dfcd8 | 1338 | { |
5a6681e2 | 1339 | ef4_oword_t reg; |
177dfcd8 | 1340 | |
5a6681e2 | 1341 | if ((ef4_nic_rev(efx) < EF4_REV_FALCON_B0) || |
177dfcd8 BH |
1342 | (efx->loopback_mode != LOOPBACK_NONE)) |
1343 | return; | |
1344 | ||
5a6681e2 | 1345 | ef4_reado(efx, ®, FR_AB_MAC_CTRL); |
177dfcd8 | 1346 | /* There is no point in draining more than once */ |
5a6681e2 | 1347 | if (EF4_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN)) |
177dfcd8 BH |
1348 | return; |
1349 | ||
1350 | falcon_reset_macs(efx); | |
8ceee660 BH |
1351 | } |
1352 | ||
5a6681e2 | 1353 | static void falcon_deconfigure_mac_wrapper(struct ef4_nic *efx) |
8ceee660 | 1354 | { |
5a6681e2 | 1355 | ef4_oword_t reg; |
8ceee660 | 1356 | |
5a6681e2 | 1357 | if (ef4_nic_rev(efx) < EF4_REV_FALCON_B0) |
8ceee660 BH |
1358 | return; |
1359 | ||
1360 | /* Isolate the MAC -> RX */ | |
5a6681e2 EC |
1361 | ef4_reado(efx, ®, FR_AZ_RX_CFG); |
1362 | EF4_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0); | |
1363 | ef4_writeo(efx, ®, FR_AZ_RX_CFG); | |
8ceee660 | 1364 | |
d3245b28 BH |
1365 | /* Isolate TX -> MAC */ |
1366 | falcon_drain_tx_fifo(efx); | |
8ceee660 BH |
1367 | } |
1368 | ||
5a6681e2 | 1369 | static void falcon_reconfigure_mac_wrapper(struct ef4_nic *efx) |
8ceee660 | 1370 | { |
5a6681e2 EC |
1371 | struct ef4_link_state *link_state = &efx->link_state; |
1372 | ef4_oword_t reg; | |
fd371e32 SH |
1373 | int link_speed, isolate; |
1374 | ||
a7d529ae | 1375 | isolate = !!ACCESS_ONCE(efx->reset_pending); |
8ceee660 | 1376 | |
eb50c0d6 | 1377 | switch (link_state->speed) { |
f31a45d2 BH |
1378 | case 10000: link_speed = 3; break; |
1379 | case 1000: link_speed = 2; break; | |
1380 | case 100: link_speed = 1; break; | |
1381 | default: link_speed = 0; break; | |
1382 | } | |
5b3b7608 | 1383 | |
8ceee660 BH |
1384 | /* MAC_LINK_STATUS controls MAC backpressure but doesn't work |
1385 | * as advertised. Disable to ensure packets are not | |
1386 | * indefinitely held and TX queue can be flushed at any point | |
1387 | * while the link is down. */ | |
5a6681e2 | 1388 | EF4_POPULATE_OWORD_5(reg, |
3e6c4538 BH |
1389 | FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */, |
1390 | FRF_AB_MAC_BCAD_ACPT, 1, | |
964e6135 | 1391 | FRF_AB_MAC_UC_PROM, !efx->unicast_filter, |
3e6c4538 BH |
1392 | FRF_AB_MAC_LINK_STATUS, 1, /* always set */ |
1393 | FRF_AB_MAC_SPEED, link_speed); | |
8ceee660 BH |
1394 | /* On B0, MAC backpressure can be disabled and packets get |
1395 | * discarded. */ | |
5a6681e2 EC |
1396 | if (ef4_nic_rev(efx) >= EF4_REV_FALCON_B0) { |
1397 | EF4_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, | |
fd371e32 | 1398 | !link_state->up || isolate); |
8ceee660 BH |
1399 | } |
1400 | ||
5a6681e2 | 1401 | ef4_writeo(efx, ®, FR_AB_MAC_CTRL); |
8ceee660 BH |
1402 | |
1403 | /* Restore the multicast hash registers. */ | |
8be4f3e6 | 1404 | falcon_push_multicast_hash(efx); |
8ceee660 | 1405 | |
5a6681e2 | 1406 | ef4_reado(efx, ®, FR_AZ_RX_CFG); |
4b0d29dc BH |
1407 | /* Enable XOFF signal from RX FIFO (we enabled it during NIC |
1408 | * initialisation but it may read back as 0) */ | |
5a6681e2 | 1409 | EF4_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1); |
8ceee660 | 1410 | /* Unisolate the MAC -> RX */ |
5a6681e2 EC |
1411 | if (ef4_nic_rev(efx) >= EF4_REV_FALCON_B0) |
1412 | EF4_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, !isolate); | |
1413 | ef4_writeo(efx, ®, FR_AZ_RX_CFG); | |
8ceee660 BH |
1414 | } |
1415 | ||
5a6681e2 | 1416 | static void falcon_stats_request(struct ef4_nic *efx) |
8ceee660 | 1417 | { |
55edc6e6 | 1418 | struct falcon_nic_data *nic_data = efx->nic_data; |
5a6681e2 | 1419 | ef4_oword_t reg; |
8ceee660 | 1420 | |
55edc6e6 BH |
1421 | WARN_ON(nic_data->stats_pending); |
1422 | WARN_ON(nic_data->stats_disable_count); | |
8ceee660 | 1423 | |
e5136124 | 1424 | FALCON_XMAC_STATS_DMA_FLAG(efx) = 0; |
55edc6e6 | 1425 | nic_data->stats_pending = true; |
8ceee660 BH |
1426 | wmb(); /* ensure done flag is clear */ |
1427 | ||
1428 | /* Initiate DMA transfer of stats */ | |
5a6681e2 | 1429 | EF4_POPULATE_OWORD_2(reg, |
3e6c4538 BH |
1430 | FRF_AB_MAC_STAT_DMA_CMD, 1, |
1431 | FRF_AB_MAC_STAT_DMA_ADR, | |
8ceee660 | 1432 | efx->stats_buffer.dma_addr); |
5a6681e2 | 1433 | ef4_writeo(efx, ®, FR_AB_MAC_STAT_DMA); |
8ceee660 | 1434 | |
55edc6e6 BH |
1435 | mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2)); |
1436 | } | |
1437 | ||
5a6681e2 | 1438 | static void falcon_stats_complete(struct ef4_nic *efx) |
55edc6e6 BH |
1439 | { |
1440 | struct falcon_nic_data *nic_data = efx->nic_data; | |
1441 | ||
1442 | if (!nic_data->stats_pending) | |
1443 | return; | |
1444 | ||
3db1cd5c | 1445 | nic_data->stats_pending = false; |
e5136124 | 1446 | if (FALCON_XMAC_STATS_DMA_FLAG(efx)) { |
55edc6e6 | 1447 | rmb(); /* read the done flag before the stats */ |
5a6681e2 | 1448 | ef4_nic_update_stats(falcon_stat_desc, FALCON_STAT_COUNT, |
cd0ecc9a BH |
1449 | falcon_stat_mask, nic_data->stats, |
1450 | efx->stats_buffer.addr, true); | |
55edc6e6 | 1451 | } else { |
62776d03 BH |
1452 | netif_err(efx, hw, efx->net_dev, |
1453 | "timed out waiting for statistics\n"); | |
8ceee660 | 1454 | } |
55edc6e6 | 1455 | } |
8ceee660 | 1456 | |
55edc6e6 BH |
1457 | static void falcon_stats_timer_func(unsigned long context) |
1458 | { | |
5a6681e2 | 1459 | struct ef4_nic *efx = (struct ef4_nic *)context; |
55edc6e6 BH |
1460 | struct falcon_nic_data *nic_data = efx->nic_data; |
1461 | ||
1462 | spin_lock(&efx->stats_lock); | |
1463 | ||
1464 | falcon_stats_complete(efx); | |
1465 | if (nic_data->stats_disable_count == 0) | |
1466 | falcon_stats_request(efx); | |
1467 | ||
1468 | spin_unlock(&efx->stats_lock); | |
8ceee660 BH |
1469 | } |
1470 | ||
5a6681e2 | 1471 | static bool falcon_loopback_link_poll(struct ef4_nic *efx) |
fdaa9aed | 1472 | { |
5a6681e2 | 1473 | struct ef4_link_state old_state = efx->link_state; |
fdaa9aed SH |
1474 | |
1475 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | |
1476 | WARN_ON(!LOOPBACK_INTERNAL(efx)); | |
1477 | ||
1478 | efx->link_state.fd = true; | |
1479 | efx->link_state.fc = efx->wanted_fc; | |
1480 | efx->link_state.up = true; | |
8fbca791 | 1481 | efx->link_state.speed = 10000; |
fdaa9aed | 1482 | |
5a6681e2 | 1483 | return !ef4_link_state_equal(&efx->link_state, &old_state); |
fdaa9aed SH |
1484 | } |
1485 | ||
5a6681e2 | 1486 | static int falcon_reconfigure_port(struct ef4_nic *efx) |
d3245b28 BH |
1487 | { |
1488 | int rc; | |
1489 | ||
5a6681e2 | 1490 | WARN_ON(ef4_nic_rev(efx) > EF4_REV_FALCON_B0); |
d3245b28 BH |
1491 | |
1492 | /* Poll the PHY link state *before* reconfiguring it. This means we | |
1493 | * will pick up the correct speed (in loopback) to select the correct | |
1494 | * MAC. | |
1495 | */ | |
1496 | if (LOOPBACK_INTERNAL(efx)) | |
1497 | falcon_loopback_link_poll(efx); | |
1498 | else | |
1499 | efx->phy_op->poll(efx); | |
1500 | ||
1501 | falcon_stop_nic_stats(efx); | |
1502 | falcon_deconfigure_mac_wrapper(efx); | |
1503 | ||
8fbca791 | 1504 | falcon_reset_macs(efx); |
d3245b28 BH |
1505 | |
1506 | efx->phy_op->reconfigure(efx); | |
710b208d | 1507 | rc = falcon_reconfigure_xmac(efx); |
d3245b28 BH |
1508 | BUG_ON(rc); |
1509 | ||
1510 | falcon_start_nic_stats(efx); | |
1511 | ||
1512 | /* Synchronise efx->link_state with the kernel */ | |
5a6681e2 | 1513 | ef4_link_status_changed(efx); |
d3245b28 BH |
1514 | |
1515 | return 0; | |
1516 | } | |
1517 | ||
9dd3a13b BH |
1518 | /* TX flow control may automatically turn itself off if the link |
1519 | * partner (intermittently) stops responding to pause frames. There | |
1520 | * isn't any indication that this has happened, so the best we do is | |
1521 | * leave it up to the user to spot this and fix it by cycling transmit | |
1522 | * flow control on this end. | |
1523 | */ | |
1524 | ||
5a6681e2 | 1525 | static void falcon_a1_prepare_enable_fc_tx(struct ef4_nic *efx) |
9dd3a13b BH |
1526 | { |
1527 | /* Schedule a reset to recover */ | |
5a6681e2 | 1528 | ef4_schedule_reset(efx, RESET_TYPE_INVISIBLE); |
9dd3a13b BH |
1529 | } |
1530 | ||
5a6681e2 | 1531 | static void falcon_b0_prepare_enable_fc_tx(struct ef4_nic *efx) |
9dd3a13b BH |
1532 | { |
1533 | /* Recover by resetting the EM block */ | |
1534 | falcon_stop_nic_stats(efx); | |
1535 | falcon_drain_tx_fifo(efx); | |
1536 | falcon_reconfigure_xmac(efx); | |
1537 | falcon_start_nic_stats(efx); | |
1538 | } | |
1539 | ||
8ceee660 BH |
1540 | /************************************************************************** |
1541 | * | |
1542 | * PHY access via GMII | |
1543 | * | |
1544 | ************************************************************************** | |
1545 | */ | |
1546 | ||
8ceee660 | 1547 | /* Wait for GMII access to complete */ |
5a6681e2 | 1548 | static int falcon_gmii_wait(struct ef4_nic *efx) |
8ceee660 | 1549 | { |
5a6681e2 | 1550 | ef4_oword_t md_stat; |
8ceee660 BH |
1551 | int count; |
1552 | ||
25985edc | 1553 | /* wait up to 50ms - taken max from datasheet */ |
177dfcd8 | 1554 | for (count = 0; count < 5000; count++) { |
5a6681e2 EC |
1555 | ef4_reado(efx, &md_stat, FR_AB_MD_STAT); |
1556 | if (EF4_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) { | |
1557 | if (EF4_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 || | |
1558 | EF4_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) { | |
62776d03 BH |
1559 | netif_err(efx, hw, efx->net_dev, |
1560 | "error from GMII access " | |
5a6681e2 EC |
1561 | EF4_OWORD_FMT"\n", |
1562 | EF4_OWORD_VAL(md_stat)); | |
8ceee660 BH |
1563 | return -EIO; |
1564 | } | |
1565 | return 0; | |
1566 | } | |
1567 | udelay(10); | |
1568 | } | |
62776d03 | 1569 | netif_err(efx, hw, efx->net_dev, "timed out waiting for GMII\n"); |
8ceee660 BH |
1570 | return -ETIMEDOUT; |
1571 | } | |
1572 | ||
68e7f45e BH |
1573 | /* Write an MDIO register of a PHY connected to Falcon. */ |
1574 | static int falcon_mdio_write(struct net_device *net_dev, | |
1575 | int prtad, int devad, u16 addr, u16 value) | |
8ceee660 | 1576 | { |
5a6681e2 | 1577 | struct ef4_nic *efx = netdev_priv(net_dev); |
4833f02a | 1578 | struct falcon_nic_data *nic_data = efx->nic_data; |
5a6681e2 | 1579 | ef4_oword_t reg; |
68e7f45e | 1580 | int rc; |
8ceee660 | 1581 | |
62776d03 BH |
1582 | netif_vdbg(efx, hw, efx->net_dev, |
1583 | "writing MDIO %d register %d.%d with 0x%04x\n", | |
68e7f45e | 1584 | prtad, devad, addr, value); |
8ceee660 | 1585 | |
4833f02a | 1586 | mutex_lock(&nic_data->mdio_lock); |
8ceee660 | 1587 | |
68e7f45e BH |
1588 | /* Check MDIO not currently being accessed */ |
1589 | rc = falcon_gmii_wait(efx); | |
1590 | if (rc) | |
8ceee660 BH |
1591 | goto out; |
1592 | ||
1593 | /* Write the address/ID register */ | |
5a6681e2 EC |
1594 | EF4_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr); |
1595 | ef4_writeo(efx, ®, FR_AB_MD_PHY_ADR); | |
8ceee660 | 1596 | |
5a6681e2 | 1597 | EF4_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad, |
3e6c4538 | 1598 | FRF_AB_MD_DEV_ADR, devad); |
5a6681e2 | 1599 | ef4_writeo(efx, ®, FR_AB_MD_ID); |
8ceee660 BH |
1600 | |
1601 | /* Write data */ | |
5a6681e2 EC |
1602 | EF4_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value); |
1603 | ef4_writeo(efx, ®, FR_AB_MD_TXD); | |
8ceee660 | 1604 | |
5a6681e2 | 1605 | EF4_POPULATE_OWORD_2(reg, |
3e6c4538 BH |
1606 | FRF_AB_MD_WRC, 1, |
1607 | FRF_AB_MD_GC, 0); | |
5a6681e2 | 1608 | ef4_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 BH |
1609 | |
1610 | /* Wait for data to be written */ | |
68e7f45e BH |
1611 | rc = falcon_gmii_wait(efx); |
1612 | if (rc) { | |
8ceee660 | 1613 | /* Abort the write operation */ |
5a6681e2 | 1614 | EF4_POPULATE_OWORD_2(reg, |
3e6c4538 BH |
1615 | FRF_AB_MD_WRC, 0, |
1616 | FRF_AB_MD_GC, 1); | |
5a6681e2 | 1617 | ef4_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 BH |
1618 | udelay(10); |
1619 | } | |
1620 | ||
ab867461 | 1621 | out: |
4833f02a | 1622 | mutex_unlock(&nic_data->mdio_lock); |
68e7f45e | 1623 | return rc; |
8ceee660 BH |
1624 | } |
1625 | ||
68e7f45e BH |
1626 | /* Read an MDIO register of a PHY connected to Falcon. */ |
1627 | static int falcon_mdio_read(struct net_device *net_dev, | |
1628 | int prtad, int devad, u16 addr) | |
8ceee660 | 1629 | { |
5a6681e2 | 1630 | struct ef4_nic *efx = netdev_priv(net_dev); |
4833f02a | 1631 | struct falcon_nic_data *nic_data = efx->nic_data; |
5a6681e2 | 1632 | ef4_oword_t reg; |
68e7f45e | 1633 | int rc; |
8ceee660 | 1634 | |
4833f02a | 1635 | mutex_lock(&nic_data->mdio_lock); |
8ceee660 | 1636 | |
68e7f45e BH |
1637 | /* Check MDIO not currently being accessed */ |
1638 | rc = falcon_gmii_wait(efx); | |
1639 | if (rc) | |
8ceee660 BH |
1640 | goto out; |
1641 | ||
5a6681e2 EC |
1642 | EF4_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr); |
1643 | ef4_writeo(efx, ®, FR_AB_MD_PHY_ADR); | |
8ceee660 | 1644 | |
5a6681e2 | 1645 | EF4_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad, |
3e6c4538 | 1646 | FRF_AB_MD_DEV_ADR, devad); |
5a6681e2 | 1647 | ef4_writeo(efx, ®, FR_AB_MD_ID); |
8ceee660 BH |
1648 | |
1649 | /* Request data to be read */ | |
5a6681e2 EC |
1650 | EF4_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0); |
1651 | ef4_writeo(efx, ®, FR_AB_MD_CS); | |
8ceee660 BH |
1652 | |
1653 | /* Wait for data to become available */ | |
68e7f45e BH |
1654 | rc = falcon_gmii_wait(efx); |
1655 | if (rc == 0) { | |
5a6681e2 EC |
1656 | ef4_reado(efx, ®, FR_AB_MD_RXD); |
1657 | rc = EF4_OWORD_FIELD(reg, FRF_AB_MD_RXD); | |
62776d03 BH |
1658 | netif_vdbg(efx, hw, efx->net_dev, |
1659 | "read from MDIO %d register %d.%d, got %04x\n", | |
1660 | prtad, devad, addr, rc); | |
8ceee660 BH |
1661 | } else { |
1662 | /* Abort the read operation */ | |
5a6681e2 | 1663 | EF4_POPULATE_OWORD_2(reg, |
3e6c4538 BH |
1664 | FRF_AB_MD_RIC, 0, |
1665 | FRF_AB_MD_GC, 1); | |
5a6681e2 | 1666 | ef4_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 | 1667 | |
62776d03 BH |
1668 | netif_dbg(efx, hw, efx->net_dev, |
1669 | "read from MDIO %d register %d.%d, got error %d\n", | |
1670 | prtad, devad, addr, rc); | |
8ceee660 BH |
1671 | } |
1672 | ||
ab867461 | 1673 | out: |
4833f02a | 1674 | mutex_unlock(&nic_data->mdio_lock); |
68e7f45e | 1675 | return rc; |
8ceee660 BH |
1676 | } |
1677 | ||
8ceee660 | 1678 | /* This call is responsible for hooking in the MAC and PHY operations */ |
5a6681e2 | 1679 | static int falcon_probe_port(struct ef4_nic *efx) |
8ceee660 | 1680 | { |
8fbca791 | 1681 | struct falcon_nic_data *nic_data = efx->nic_data; |
8ceee660 BH |
1682 | int rc; |
1683 | ||
96c45726 BH |
1684 | switch (efx->phy_type) { |
1685 | case PHY_TYPE_SFX7101: | |
1686 | efx->phy_op = &falcon_sfx7101_phy_ops; | |
1687 | break; | |
96c45726 BH |
1688 | case PHY_TYPE_QT2022C2: |
1689 | case PHY_TYPE_QT2025C: | |
b37b62fe | 1690 | efx->phy_op = &falcon_qt202x_phy_ops; |
96c45726 | 1691 | break; |
7e51b439 BH |
1692 | case PHY_TYPE_TXC43128: |
1693 | efx->phy_op = &falcon_txc_phy_ops; | |
1694 | break; | |
96c45726 | 1695 | default: |
62776d03 BH |
1696 | netif_err(efx, probe, efx->net_dev, "Unknown PHY type %d\n", |
1697 | efx->phy_type); | |
96c45726 BH |
1698 | return -ENODEV; |
1699 | } | |
1700 | ||
c1c4f453 | 1701 | /* Fill out MDIO structure and loopback modes */ |
4833f02a | 1702 | mutex_init(&nic_data->mdio_lock); |
68e7f45e BH |
1703 | efx->mdio.mdio_read = falcon_mdio_read; |
1704 | efx->mdio.mdio_write = falcon_mdio_write; | |
c1c4f453 BH |
1705 | rc = efx->phy_op->probe(efx); |
1706 | if (rc != 0) | |
1707 | return rc; | |
8ceee660 | 1708 | |
b895d73e SH |
1709 | /* Initial assumption */ |
1710 | efx->link_state.speed = 10000; | |
1711 | efx->link_state.fd = true; | |
1712 | ||
8ceee660 | 1713 | /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */ |
5a6681e2 EC |
1714 | if (ef4_nic_rev(efx) >= EF4_REV_FALCON_B0) |
1715 | efx->wanted_fc = EF4_FC_RX | EF4_FC_TX; | |
8ceee660 | 1716 | else |
5a6681e2 | 1717 | efx->wanted_fc = EF4_FC_RX; |
7a6b8f6f | 1718 | if (efx->mdio.mmds & MDIO_DEVS_AN) |
5a6681e2 | 1719 | efx->wanted_fc |= EF4_FC_AUTO; |
8ceee660 BH |
1720 | |
1721 | /* Allocate buffer for stats */ | |
5a6681e2 | 1722 | rc = ef4_nic_alloc_buffer(efx, &efx->stats_buffer, |
0d19a540 | 1723 | FALCON_MAC_STATS_SIZE, GFP_KERNEL); |
8ceee660 BH |
1724 | if (rc) |
1725 | return rc; | |
62776d03 BH |
1726 | netif_dbg(efx, probe, efx->net_dev, |
1727 | "stats buffer at %llx (virt %p phys %llx)\n", | |
1728 | (u64)efx->stats_buffer.dma_addr, | |
1729 | efx->stats_buffer.addr, | |
1730 | (u64)virt_to_phys(efx->stats_buffer.addr)); | |
8ceee660 BH |
1731 | |
1732 | return 0; | |
1733 | } | |
1734 | ||
5a6681e2 | 1735 | static void falcon_remove_port(struct ef4_nic *efx) |
8ceee660 | 1736 | { |
ff3b00a0 | 1737 | efx->phy_op->remove(efx); |
5a6681e2 | 1738 | ef4_nic_free_buffer(efx, &efx->stats_buffer); |
8ceee660 BH |
1739 | } |
1740 | ||
40641ed9 BH |
1741 | /* Global events are basically PHY events */ |
1742 | static bool | |
5a6681e2 | 1743 | falcon_handle_global_event(struct ef4_channel *channel, ef4_qword_t *event) |
40641ed9 | 1744 | { |
5a6681e2 | 1745 | struct ef4_nic *efx = channel->efx; |
cef68bde | 1746 | struct falcon_nic_data *nic_data = efx->nic_data; |
40641ed9 | 1747 | |
5a6681e2 EC |
1748 | if (EF4_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) || |
1749 | EF4_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) || | |
1750 | EF4_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) | |
40641ed9 BH |
1751 | /* Ignored */ |
1752 | return true; | |
1753 | ||
5a6681e2 EC |
1754 | if ((ef4_nic_rev(efx) == EF4_REV_FALCON_B0) && |
1755 | EF4_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) { | |
cef68bde | 1756 | nic_data->xmac_poll_required = true; |
40641ed9 BH |
1757 | return true; |
1758 | } | |
1759 | ||
5a6681e2 EC |
1760 | if (ef4_nic_rev(efx) <= EF4_REV_FALCON_A1 ? |
1761 | EF4_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) : | |
1762 | EF4_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) { | |
40641ed9 BH |
1763 | netif_err(efx, rx_err, efx->net_dev, |
1764 | "channel %d seen global RX_RESET event. Resetting.\n", | |
1765 | channel->channel); | |
1766 | ||
1767 | atomic_inc(&efx->rx_reset); | |
5a6681e2 | 1768 | ef4_schedule_reset(efx, EF4_WORKAROUND_6555(efx) ? |
40641ed9 BH |
1769 | RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE); |
1770 | return true; | |
1771 | } | |
1772 | ||
1773 | return false; | |
1774 | } | |
1775 | ||
8c8661e4 BH |
1776 | /************************************************************************** |
1777 | * | |
1778 | * Falcon test code | |
1779 | * | |
1780 | **************************************************************************/ | |
1781 | ||
0aa3fbaa | 1782 | static int |
5a6681e2 | 1783 | falcon_read_nvram(struct ef4_nic *efx, struct falcon_nvconfig *nvconfig_out) |
8c8661e4 | 1784 | { |
4de92180 | 1785 | struct falcon_nic_data *nic_data = efx->nic_data; |
8c8661e4 | 1786 | struct falcon_nvconfig *nvconfig; |
ecd0a6f0 | 1787 | struct falcon_spi_device *spi; |
8c8661e4 BH |
1788 | void *region; |
1789 | int rc, magic_num, struct_ver; | |
1790 | __le16 *word, *limit; | |
1791 | u32 csum; | |
1792 | ||
ecd0a6f0 | 1793 | if (falcon_spi_present(&nic_data->spi_flash)) |
4de92180 | 1794 | spi = &nic_data->spi_flash; |
ecd0a6f0 | 1795 | else if (falcon_spi_present(&nic_data->spi_eeprom)) |
4de92180 BH |
1796 | spi = &nic_data->spi_eeprom; |
1797 | else | |
2f7f5730 BH |
1798 | return -EINVAL; |
1799 | ||
0a95f563 | 1800 | region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL); |
8c8661e4 BH |
1801 | if (!region) |
1802 | return -ENOMEM; | |
3e6c4538 | 1803 | nvconfig = region + FALCON_NVCONFIG_OFFSET; |
8c8661e4 | 1804 | |
4de92180 | 1805 | mutex_lock(&nic_data->spi_lock); |
76884835 | 1806 | rc = falcon_spi_read(efx, spi, 0, FALCON_NVCONFIG_END, NULL, region); |
4de92180 | 1807 | mutex_unlock(&nic_data->spi_lock); |
8c8661e4 | 1808 | if (rc) { |
62776d03 | 1809 | netif_err(efx, hw, efx->net_dev, "Failed to read %s\n", |
ecd0a6f0 | 1810 | falcon_spi_present(&nic_data->spi_flash) ? |
4de92180 | 1811 | "flash" : "EEPROM"); |
8c8661e4 BH |
1812 | rc = -EIO; |
1813 | goto out; | |
1814 | } | |
1815 | ||
1816 | magic_num = le16_to_cpu(nvconfig->board_magic_num); | |
1817 | struct_ver = le16_to_cpu(nvconfig->board_struct_ver); | |
1818 | ||
1819 | rc = -EINVAL; | |
3e6c4538 | 1820 | if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) { |
62776d03 BH |
1821 | netif_err(efx, hw, efx->net_dev, |
1822 | "NVRAM bad magic 0x%x\n", magic_num); | |
8c8661e4 BH |
1823 | goto out; |
1824 | } | |
1825 | if (struct_ver < 2) { | |
62776d03 BH |
1826 | netif_err(efx, hw, efx->net_dev, |
1827 | "NVRAM has ancient version 0x%x\n", struct_ver); | |
8c8661e4 BH |
1828 | goto out; |
1829 | } else if (struct_ver < 4) { | |
1830 | word = &nvconfig->board_magic_num; | |
1831 | limit = (__le16 *) (nvconfig + 1); | |
1832 | } else { | |
1833 | word = region; | |
0a95f563 | 1834 | limit = region + FALCON_NVCONFIG_END; |
8c8661e4 BH |
1835 | } |
1836 | for (csum = 0; word < limit; ++word) | |
1837 | csum += le16_to_cpu(*word); | |
1838 | ||
1839 | if (~csum & 0xffff) { | |
62776d03 BH |
1840 | netif_err(efx, hw, efx->net_dev, |
1841 | "NVRAM has incorrect checksum\n"); | |
8c8661e4 BH |
1842 | goto out; |
1843 | } | |
1844 | ||
1845 | rc = 0; | |
1846 | if (nvconfig_out) | |
1847 | memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig)); | |
1848 | ||
1849 | out: | |
1850 | kfree(region); | |
1851 | return rc; | |
1852 | } | |
1853 | ||
5a6681e2 | 1854 | static int falcon_test_nvram(struct ef4_nic *efx) |
0aa3fbaa BH |
1855 | { |
1856 | return falcon_read_nvram(efx, NULL); | |
1857 | } | |
1858 | ||
5a6681e2 | 1859 | static const struct ef4_farch_register_test falcon_b0_register_tests[] = { |
3e6c4538 | 1860 | { FR_AZ_ADR_REGION, |
5a6681e2 | 1861 | EF4_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) }, |
3e6c4538 | 1862 | { FR_AZ_RX_CFG, |
5a6681e2 | 1863 | EF4_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) }, |
3e6c4538 | 1864 | { FR_AZ_TX_CFG, |
5a6681e2 | 1865 | EF4_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1866 | { FR_AZ_TX_RESERVED, |
5a6681e2 | 1867 | EF4_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) }, |
3e6c4538 | 1868 | { FR_AB_MAC_CTRL, |
5a6681e2 | 1869 | EF4_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1870 | { FR_AZ_SRM_TX_DC_CFG, |
5a6681e2 | 1871 | EF4_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1872 | { FR_AZ_RX_DC_CFG, |
5a6681e2 | 1873 | EF4_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1874 | { FR_AZ_RX_DC_PF_WM, |
5a6681e2 | 1875 | EF4_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1876 | { FR_BZ_DP_CTRL, |
5a6681e2 | 1877 | EF4_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1878 | { FR_AB_GM_CFG2, |
5a6681e2 | 1879 | EF4_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1880 | { FR_AB_GMF_CFG0, |
5a6681e2 | 1881 | EF4_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1882 | { FR_AB_XM_GLB_CFG, |
5a6681e2 | 1883 | EF4_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1884 | { FR_AB_XM_TX_CFG, |
5a6681e2 | 1885 | EF4_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1886 | { FR_AB_XM_RX_CFG, |
5a6681e2 | 1887 | EF4_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1888 | { FR_AB_XM_RX_PARAM, |
5a6681e2 | 1889 | EF4_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1890 | { FR_AB_XM_FC, |
5a6681e2 | 1891 | EF4_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1892 | { FR_AB_XM_ADR_LO, |
5a6681e2 | 1893 | EF4_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1894 | { FR_AB_XX_SD_CTL, |
5a6681e2 | 1895 | EF4_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) }, |
8c8661e4 BH |
1896 | }; |
1897 | ||
d4f2cecc | 1898 | static int |
5a6681e2 | 1899 | falcon_b0_test_chip(struct ef4_nic *efx, struct ef4_self_tests *tests) |
152b6a62 | 1900 | { |
d4f2cecc BH |
1901 | enum reset_type reset_method = RESET_TYPE_INVISIBLE; |
1902 | int rc, rc2; | |
1903 | ||
1904 | mutex_lock(&efx->mac_lock); | |
1905 | if (efx->loopback_modes) { | |
1906 | /* We need the 312 clock from the PHY to test the XMAC | |
1907 | * registers, so move into XGMII loopback if available */ | |
1908 | if (efx->loopback_modes & (1 << LOOPBACK_XGMII)) | |
1909 | efx->loopback_mode = LOOPBACK_XGMII; | |
1910 | else | |
1911 | efx->loopback_mode = __ffs(efx->loopback_modes); | |
1912 | } | |
5a6681e2 | 1913 | __ef4_reconfigure_port(efx); |
d4f2cecc BH |
1914 | mutex_unlock(&efx->mac_lock); |
1915 | ||
5a6681e2 | 1916 | ef4_reset_down(efx, reset_method); |
d4f2cecc BH |
1917 | |
1918 | tests->registers = | |
5a6681e2 | 1919 | ef4_farch_test_registers(efx, falcon_b0_register_tests, |
86094f7f | 1920 | ARRAY_SIZE(falcon_b0_register_tests)) |
d4f2cecc BH |
1921 | ? -1 : 1; |
1922 | ||
1923 | rc = falcon_reset_hw(efx, reset_method); | |
5a6681e2 | 1924 | rc2 = ef4_reset_up(efx, reset_method, rc == 0); |
d4f2cecc | 1925 | return rc ? rc : rc2; |
152b6a62 BH |
1926 | } |
1927 | ||
8ceee660 BH |
1928 | /************************************************************************** |
1929 | * | |
1930 | * Device reset | |
1931 | * | |
1932 | ************************************************************************** | |
1933 | */ | |
1934 | ||
0e2a9c7c BH |
1935 | static enum reset_type falcon_map_reset_reason(enum reset_type reason) |
1936 | { | |
1937 | switch (reason) { | |
1938 | case RESET_TYPE_RX_RECOVERY: | |
3de82b91 | 1939 | case RESET_TYPE_DMA_ERROR: |
0e2a9c7c BH |
1940 | case RESET_TYPE_TX_SKIP: |
1941 | /* These can occasionally occur due to hardware bugs. | |
1942 | * We try to reset without disrupting the link. | |
1943 | */ | |
1944 | return RESET_TYPE_INVISIBLE; | |
1945 | default: | |
1946 | return RESET_TYPE_ALL; | |
1947 | } | |
1948 | } | |
1949 | ||
1950 | static int falcon_map_reset_flags(u32 *flags) | |
1951 | { | |
1952 | enum { | |
1953 | FALCON_RESET_INVISIBLE = (ETH_RESET_DMA | ETH_RESET_FILTER | | |
1954 | ETH_RESET_OFFLOAD | ETH_RESET_MAC), | |
1955 | FALCON_RESET_ALL = FALCON_RESET_INVISIBLE | ETH_RESET_PHY, | |
1956 | FALCON_RESET_WORLD = FALCON_RESET_ALL | ETH_RESET_IRQ, | |
1957 | }; | |
1958 | ||
1959 | if ((*flags & FALCON_RESET_WORLD) == FALCON_RESET_WORLD) { | |
1960 | *flags &= ~FALCON_RESET_WORLD; | |
1961 | return RESET_TYPE_WORLD; | |
1962 | } | |
1963 | ||
1964 | if ((*flags & FALCON_RESET_ALL) == FALCON_RESET_ALL) { | |
1965 | *flags &= ~FALCON_RESET_ALL; | |
1966 | return RESET_TYPE_ALL; | |
1967 | } | |
1968 | ||
1969 | if ((*flags & FALCON_RESET_INVISIBLE) == FALCON_RESET_INVISIBLE) { | |
1970 | *flags &= ~FALCON_RESET_INVISIBLE; | |
1971 | return RESET_TYPE_INVISIBLE; | |
1972 | } | |
1973 | ||
1974 | return -EINVAL; | |
1975 | } | |
1976 | ||
8ceee660 BH |
1977 | /* Resets NIC to known state. This routine must be called in process |
1978 | * context and is allowed to sleep. */ | |
5a6681e2 | 1979 | static int __falcon_reset_hw(struct ef4_nic *efx, enum reset_type method) |
8ceee660 BH |
1980 | { |
1981 | struct falcon_nic_data *nic_data = efx->nic_data; | |
5a6681e2 | 1982 | ef4_oword_t glb_ctl_reg_ker; |
8ceee660 BH |
1983 | int rc; |
1984 | ||
62776d03 BH |
1985 | netif_dbg(efx, hw, efx->net_dev, "performing %s hardware reset\n", |
1986 | RESET_TYPE(method)); | |
8ceee660 BH |
1987 | |
1988 | /* Initiate device reset */ | |
1989 | if (method == RESET_TYPE_WORLD) { | |
1990 | rc = pci_save_state(efx->pci_dev); | |
1991 | if (rc) { | |
62776d03 BH |
1992 | netif_err(efx, drv, efx->net_dev, |
1993 | "failed to backup PCI state of primary " | |
1994 | "function prior to hardware reset\n"); | |
8ceee660 BH |
1995 | goto fail1; |
1996 | } | |
5a6681e2 | 1997 | if (ef4_nic_is_dual_func(efx)) { |
8ceee660 BH |
1998 | rc = pci_save_state(nic_data->pci_dev2); |
1999 | if (rc) { | |
62776d03 BH |
2000 | netif_err(efx, drv, efx->net_dev, |
2001 | "failed to backup PCI state of " | |
2002 | "secondary function prior to " | |
2003 | "hardware reset\n"); | |
8ceee660 BH |
2004 | goto fail2; |
2005 | } | |
2006 | } | |
2007 | ||
5a6681e2 | 2008 | EF4_POPULATE_OWORD_2(glb_ctl_reg_ker, |
3e6c4538 BH |
2009 | FRF_AB_EXT_PHY_RST_DUR, |
2010 | FFE_AB_EXT_PHY_RST_DUR_10240US, | |
2011 | FRF_AB_SWRST, 1); | |
8ceee660 | 2012 | } else { |
5a6681e2 | 2013 | EF4_POPULATE_OWORD_7(glb_ctl_reg_ker, |
3e6c4538 BH |
2014 | /* exclude PHY from "invisible" reset */ |
2015 | FRF_AB_EXT_PHY_RST_CTL, | |
2016 | method == RESET_TYPE_INVISIBLE, | |
2017 | /* exclude EEPROM/flash and PCIe */ | |
2018 | FRF_AB_PCIE_CORE_RST_CTL, 1, | |
2019 | FRF_AB_PCIE_NSTKY_RST_CTL, 1, | |
2020 | FRF_AB_PCIE_SD_RST_CTL, 1, | |
2021 | FRF_AB_EE_RST_CTL, 1, | |
2022 | FRF_AB_EXT_PHY_RST_DUR, | |
2023 | FFE_AB_EXT_PHY_RST_DUR_10240US, | |
2024 | FRF_AB_SWRST, 1); | |
2025 | } | |
5a6681e2 | 2026 | ef4_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL); |
8ceee660 | 2027 | |
62776d03 | 2028 | netif_dbg(efx, hw, efx->net_dev, "waiting for hardware reset\n"); |
8ceee660 BH |
2029 | schedule_timeout_uninterruptible(HZ / 20); |
2030 | ||
2031 | /* Restore PCI configuration if needed */ | |
2032 | if (method == RESET_TYPE_WORLD) { | |
5a6681e2 | 2033 | if (ef4_nic_is_dual_func(efx)) |
1d3c16a8 JM |
2034 | pci_restore_state(nic_data->pci_dev2); |
2035 | pci_restore_state(efx->pci_dev); | |
62776d03 BH |
2036 | netif_dbg(efx, drv, efx->net_dev, |
2037 | "successfully restored PCI config\n"); | |
8ceee660 BH |
2038 | } |
2039 | ||
2040 | /* Assert that reset complete */ | |
5a6681e2 EC |
2041 | ef4_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL); |
2042 | if (EF4_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) { | |
8ceee660 | 2043 | rc = -ETIMEDOUT; |
62776d03 BH |
2044 | netif_err(efx, hw, efx->net_dev, |
2045 | "timed out waiting for hardware reset\n"); | |
1d3c16a8 | 2046 | goto fail3; |
8ceee660 | 2047 | } |
62776d03 | 2048 | netif_dbg(efx, hw, efx->net_dev, "hardware reset complete\n"); |
8ceee660 BH |
2049 | |
2050 | return 0; | |
2051 | ||
2052 | /* pci_save_state() and pci_restore_state() MUST be called in pairs */ | |
2053 | fail2: | |
8ceee660 BH |
2054 | pci_restore_state(efx->pci_dev); |
2055 | fail1: | |
1d3c16a8 | 2056 | fail3: |
8ceee660 BH |
2057 | return rc; |
2058 | } | |
2059 | ||
5a6681e2 | 2060 | static int falcon_reset_hw(struct ef4_nic *efx, enum reset_type method) |
4de92180 BH |
2061 | { |
2062 | struct falcon_nic_data *nic_data = efx->nic_data; | |
2063 | int rc; | |
2064 | ||
2065 | mutex_lock(&nic_data->spi_lock); | |
2066 | rc = __falcon_reset_hw(efx, method); | |
2067 | mutex_unlock(&nic_data->spi_lock); | |
2068 | ||
2069 | return rc; | |
2070 | } | |
2071 | ||
5a6681e2 | 2072 | static void falcon_monitor(struct ef4_nic *efx) |
fe75820b | 2073 | { |
fdaa9aed | 2074 | bool link_changed; |
fe75820b BH |
2075 | int rc; |
2076 | ||
fdaa9aed SH |
2077 | BUG_ON(!mutex_is_locked(&efx->mac_lock)); |
2078 | ||
fe75820b BH |
2079 | rc = falcon_board(efx)->type->monitor(efx); |
2080 | if (rc) { | |
62776d03 BH |
2081 | netif_err(efx, hw, efx->net_dev, |
2082 | "Board sensor %s; shutting down PHY\n", | |
2083 | (rc == -ERANGE) ? "reported fault" : "failed"); | |
fe75820b | 2084 | efx->phy_mode |= PHY_MODE_LOW_POWER; |
5a6681e2 | 2085 | rc = __ef4_reconfigure_port(efx); |
d3245b28 | 2086 | WARN_ON(rc); |
fe75820b | 2087 | } |
fdaa9aed SH |
2088 | |
2089 | if (LOOPBACK_INTERNAL(efx)) | |
2090 | link_changed = falcon_loopback_link_poll(efx); | |
2091 | else | |
2092 | link_changed = efx->phy_op->poll(efx); | |
2093 | ||
2094 | if (link_changed) { | |
2095 | falcon_stop_nic_stats(efx); | |
2096 | falcon_deconfigure_mac_wrapper(efx); | |
2097 | ||
8fbca791 | 2098 | falcon_reset_macs(efx); |
710b208d | 2099 | rc = falcon_reconfigure_xmac(efx); |
d3245b28 | 2100 | BUG_ON(rc); |
fdaa9aed SH |
2101 | |
2102 | falcon_start_nic_stats(efx); | |
2103 | ||
5a6681e2 | 2104 | ef4_link_status_changed(efx); |
fdaa9aed SH |
2105 | } |
2106 | ||
8fbca791 | 2107 | falcon_poll_xmac(efx); |
fe75820b BH |
2108 | } |
2109 | ||
8ceee660 BH |
2110 | /* Zeroes out the SRAM contents. This routine must be called in |
2111 | * process context and is allowed to sleep. | |
2112 | */ | |
5a6681e2 | 2113 | static int falcon_reset_sram(struct ef4_nic *efx) |
8ceee660 | 2114 | { |
5a6681e2 | 2115 | ef4_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker; |
8ceee660 BH |
2116 | int count; |
2117 | ||
2118 | /* Set the SRAM wake/sleep GPIO appropriately. */ | |
5a6681e2 EC |
2119 | ef4_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL); |
2120 | EF4_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1); | |
2121 | EF4_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1); | |
2122 | ef4_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL); | |
8ceee660 BH |
2123 | |
2124 | /* Initiate SRAM reset */ | |
5a6681e2 | 2125 | EF4_POPULATE_OWORD_2(srm_cfg_reg_ker, |
3e6c4538 BH |
2126 | FRF_AZ_SRM_INIT_EN, 1, |
2127 | FRF_AZ_SRM_NB_SZ, 0); | |
5a6681e2 | 2128 | ef4_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG); |
8ceee660 BH |
2129 | |
2130 | /* Wait for SRAM reset to complete */ | |
2131 | count = 0; | |
2132 | do { | |
62776d03 BH |
2133 | netif_dbg(efx, hw, efx->net_dev, |
2134 | "waiting for SRAM reset (attempt %d)...\n", count); | |
8ceee660 BH |
2135 | |
2136 | /* SRAM reset is slow; expect around 16ms */ | |
2137 | schedule_timeout_uninterruptible(HZ / 50); | |
2138 | ||
2139 | /* Check for reset complete */ | |
5a6681e2 EC |
2140 | ef4_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG); |
2141 | if (!EF4_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) { | |
62776d03 BH |
2142 | netif_dbg(efx, hw, efx->net_dev, |
2143 | "SRAM reset complete\n"); | |
8ceee660 BH |
2144 | |
2145 | return 0; | |
2146 | } | |
25985edc | 2147 | } while (++count < 20); /* wait up to 0.4 sec */ |
8ceee660 | 2148 | |
62776d03 | 2149 | netif_err(efx, hw, efx->net_dev, "timed out waiting for SRAM reset\n"); |
8ceee660 BH |
2150 | return -ETIMEDOUT; |
2151 | } | |
2152 | ||
5a6681e2 | 2153 | static void falcon_spi_device_init(struct ef4_nic *efx, |
ecd0a6f0 | 2154 | struct falcon_spi_device *spi_device, |
4a5b504d BH |
2155 | unsigned int device_id, u32 device_type) |
2156 | { | |
4a5b504d | 2157 | if (device_type != 0) { |
4a5b504d BH |
2158 | spi_device->device_id = device_id; |
2159 | spi_device->size = | |
2160 | 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE); | |
2161 | spi_device->addr_len = | |
2162 | SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN); | |
2163 | spi_device->munge_address = (spi_device->size == 1 << 9 && | |
2164 | spi_device->addr_len == 1); | |
f4150724 BH |
2165 | spi_device->erase_command = |
2166 | SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD); | |
2167 | spi_device->erase_size = | |
2168 | 1 << SPI_DEV_TYPE_FIELD(device_type, | |
2169 | SPI_DEV_TYPE_ERASE_SIZE); | |
4a5b504d BH |
2170 | spi_device->block_size = |
2171 | 1 << SPI_DEV_TYPE_FIELD(device_type, | |
2172 | SPI_DEV_TYPE_BLOCK_SIZE); | |
4a5b504d | 2173 | } else { |
4de92180 | 2174 | spi_device->size = 0; |
4a5b504d | 2175 | } |
4a5b504d BH |
2176 | } |
2177 | ||
8ceee660 | 2178 | /* Extract non-volatile configuration */ |
5a6681e2 | 2179 | static int falcon_probe_nvconfig(struct ef4_nic *efx) |
8ceee660 | 2180 | { |
4de92180 | 2181 | struct falcon_nic_data *nic_data = efx->nic_data; |
8ceee660 | 2182 | struct falcon_nvconfig *nvconfig; |
8ceee660 BH |
2183 | int rc; |
2184 | ||
8ceee660 | 2185 | nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL); |
4a5b504d BH |
2186 | if (!nvconfig) |
2187 | return -ENOMEM; | |
8ceee660 | 2188 | |
8c8661e4 | 2189 | rc = falcon_read_nvram(efx, nvconfig); |
6c88b0b6 | 2190 | if (rc) |
4de92180 | 2191 | goto out; |
6c88b0b6 BH |
2192 | |
2193 | efx->phy_type = nvconfig->board_v2.port0_phy_type; | |
2194 | efx->mdio.prtad = nvconfig->board_v2.port0_phy_addr; | |
2195 | ||
2196 | if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) { | |
4de92180 BH |
2197 | falcon_spi_device_init( |
2198 | efx, &nic_data->spi_flash, FFE_AB_SPI_DEVICE_FLASH, | |
6c88b0b6 BH |
2199 | le32_to_cpu(nvconfig->board_v3 |
2200 | .spi_device_type[FFE_AB_SPI_DEVICE_FLASH])); | |
4de92180 BH |
2201 | falcon_spi_device_init( |
2202 | efx, &nic_data->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM, | |
6c88b0b6 BH |
2203 | le32_to_cpu(nvconfig->board_v3 |
2204 | .spi_device_type[FFE_AB_SPI_DEVICE_EEPROM])); | |
8ceee660 BH |
2205 | } |
2206 | ||
8c8661e4 | 2207 | /* Read the MAC addresses */ |
cd84ff4d | 2208 | ether_addr_copy(efx->net_dev->perm_addr, nvconfig->mac_address[0]); |
8c8661e4 | 2209 | |
62776d03 BH |
2210 | netif_dbg(efx, probe, efx->net_dev, "PHY is %d phy_id %d\n", |
2211 | efx->phy_type, efx->mdio.prtad); | |
8ceee660 | 2212 | |
6c88b0b6 BH |
2213 | rc = falcon_probe_board(efx, |
2214 | le16_to_cpu(nvconfig->board_v2.board_revision)); | |
4de92180 | 2215 | out: |
8ceee660 BH |
2216 | kfree(nvconfig); |
2217 | return rc; | |
2218 | } | |
2219 | ||
5a6681e2 | 2220 | static int falcon_dimension_resources(struct ef4_nic *efx) |
28e47c49 BH |
2221 | { |
2222 | efx->rx_dc_base = 0x20000; | |
2223 | efx->tx_dc_base = 0x26000; | |
c15eed22 | 2224 | return 0; |
28e47c49 BH |
2225 | } |
2226 | ||
4a5b504d | 2227 | /* Probe all SPI devices on the NIC */ |
5a6681e2 | 2228 | static void falcon_probe_spi_devices(struct ef4_nic *efx) |
4a5b504d | 2229 | { |
4de92180 | 2230 | struct falcon_nic_data *nic_data = efx->nic_data; |
5a6681e2 | 2231 | ef4_oword_t nic_stat, gpio_ctl, ee_vpd_cfg; |
2f7f5730 | 2232 | int boot_dev; |
4a5b504d | 2233 | |
5a6681e2 EC |
2234 | ef4_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL); |
2235 | ef4_reado(efx, &nic_stat, FR_AB_NIC_STAT); | |
2236 | ef4_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0); | |
4a5b504d | 2237 | |
5a6681e2 EC |
2238 | if (EF4_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) { |
2239 | boot_dev = (EF4_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ? | |
3e6c4538 | 2240 | FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM); |
62776d03 BH |
2241 | netif_dbg(efx, probe, efx->net_dev, "Booted from %s\n", |
2242 | boot_dev == FFE_AB_SPI_DEVICE_FLASH ? | |
2243 | "flash" : "EEPROM"); | |
2f7f5730 BH |
2244 | } else { |
2245 | /* Disable VPD and set clock dividers to safe | |
2246 | * values for initial programming. */ | |
2247 | boot_dev = -1; | |
62776d03 BH |
2248 | netif_dbg(efx, probe, efx->net_dev, |
2249 | "Booted from internal ASIC settings;" | |
2250 | " setting SPI config\n"); | |
5a6681e2 | 2251 | EF4_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0, |
2f7f5730 | 2252 | /* 125 MHz / 7 ~= 20 MHz */ |
3e6c4538 | 2253 | FRF_AB_EE_SF_CLOCK_DIV, 7, |
2f7f5730 | 2254 | /* 125 MHz / 63 ~= 2 MHz */ |
3e6c4538 | 2255 | FRF_AB_EE_EE_CLOCK_DIV, 63); |
5a6681e2 | 2256 | ef4_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0); |
4a5b504d BH |
2257 | } |
2258 | ||
4de92180 BH |
2259 | mutex_init(&nic_data->spi_lock); |
2260 | ||
3e6c4538 | 2261 | if (boot_dev == FFE_AB_SPI_DEVICE_FLASH) |
4de92180 | 2262 | falcon_spi_device_init(efx, &nic_data->spi_flash, |
3e6c4538 | 2263 | FFE_AB_SPI_DEVICE_FLASH, |
2f7f5730 | 2264 | default_flash_type); |
3e6c4538 | 2265 | if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM) |
4de92180 | 2266 | falcon_spi_device_init(efx, &nic_data->spi_eeprom, |
3e6c4538 | 2267 | FFE_AB_SPI_DEVICE_EEPROM, |
2f7f5730 | 2268 | large_eeprom_type); |
4a5b504d BH |
2269 | } |
2270 | ||
5a6681e2 | 2271 | static unsigned int falcon_a1_mem_map_size(struct ef4_nic *efx) |
b105798f BH |
2272 | { |
2273 | return 0x20000; | |
2274 | } | |
2275 | ||
5a6681e2 | 2276 | static unsigned int falcon_b0_mem_map_size(struct ef4_nic *efx) |
b105798f BH |
2277 | { |
2278 | /* Map everything up to and including the RSS indirection table. | |
2279 | * The PCI core takes care of mapping the MSI-X tables. | |
2280 | */ | |
2281 | return FR_BZ_RX_INDIRECTION_TBL + | |
2282 | FR_BZ_RX_INDIRECTION_TBL_STEP * FR_BZ_RX_INDIRECTION_TBL_ROWS; | |
2283 | } | |
2284 | ||
5a6681e2 | 2285 | static int falcon_probe_nic(struct ef4_nic *efx) |
8ceee660 BH |
2286 | { |
2287 | struct falcon_nic_data *nic_data; | |
e775fb93 | 2288 | struct falcon_board *board; |
8ceee660 BH |
2289 | int rc; |
2290 | ||
0bcf4a64 BH |
2291 | efx->primary = efx; /* only one usable function per controller */ |
2292 | ||
8ceee660 BH |
2293 | /* Allocate storage for hardware specific data */ |
2294 | nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); | |
88c59425 BH |
2295 | if (!nic_data) |
2296 | return -ENOMEM; | |
5daab96d | 2297 | efx->nic_data = nic_data; |
8ceee660 | 2298 | |
57849460 BH |
2299 | rc = -ENODEV; |
2300 | ||
5a6681e2 | 2301 | if (ef4_farch_fpga_ver(efx) != 0) { |
62776d03 BH |
2302 | netif_err(efx, probe, efx->net_dev, |
2303 | "Falcon FPGA not supported\n"); | |
8ceee660 | 2304 | goto fail1; |
57849460 BH |
2305 | } |
2306 | ||
5a6681e2 EC |
2307 | if (ef4_nic_rev(efx) <= EF4_REV_FALCON_A1) { |
2308 | ef4_oword_t nic_stat; | |
57849460 BH |
2309 | struct pci_dev *dev; |
2310 | u8 pci_rev = efx->pci_dev->revision; | |
8ceee660 | 2311 | |
57849460 | 2312 | if ((pci_rev == 0xff) || (pci_rev == 0)) { |
62776d03 BH |
2313 | netif_err(efx, probe, efx->net_dev, |
2314 | "Falcon rev A0 not supported\n"); | |
57849460 BH |
2315 | goto fail1; |
2316 | } | |
5a6681e2 EC |
2317 | ef4_reado(efx, &nic_stat, FR_AB_NIC_STAT); |
2318 | if (EF4_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) { | |
62776d03 BH |
2319 | netif_err(efx, probe, efx->net_dev, |
2320 | "Falcon rev A1 1G not supported\n"); | |
57849460 BH |
2321 | goto fail1; |
2322 | } | |
5a6681e2 | 2323 | if (EF4_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) { |
62776d03 BH |
2324 | netif_err(efx, probe, efx->net_dev, |
2325 | "Falcon rev A1 PCI-X not supported\n"); | |
57849460 BH |
2326 | goto fail1; |
2327 | } | |
8ceee660 | 2328 | |
57849460 | 2329 | dev = pci_dev_get(efx->pci_dev); |
937383a5 BH |
2330 | while ((dev = pci_get_device(PCI_VENDOR_ID_SOLARFLARE, |
2331 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, | |
8ceee660 BH |
2332 | dev))) { |
2333 | if (dev->bus == efx->pci_dev->bus && | |
2334 | dev->devfn == efx->pci_dev->devfn + 1) { | |
2335 | nic_data->pci_dev2 = dev; | |
2336 | break; | |
2337 | } | |
2338 | } | |
2339 | if (!nic_data->pci_dev2) { | |
62776d03 BH |
2340 | netif_err(efx, probe, efx->net_dev, |
2341 | "failed to find secondary function\n"); | |
8ceee660 BH |
2342 | rc = -ENODEV; |
2343 | goto fail2; | |
2344 | } | |
2345 | } | |
2346 | ||
2347 | /* Now we can reset the NIC */ | |
4de92180 | 2348 | rc = __falcon_reset_hw(efx, RESET_TYPE_ALL); |
8ceee660 | 2349 | if (rc) { |
62776d03 | 2350 | netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n"); |
8ceee660 BH |
2351 | goto fail3; |
2352 | } | |
2353 | ||
2354 | /* Allocate memory for INT_KER */ | |
5a6681e2 | 2355 | rc = ef4_nic_alloc_buffer(efx, &efx->irq_status, sizeof(ef4_oword_t), |
0d19a540 | 2356 | GFP_KERNEL); |
8ceee660 BH |
2357 | if (rc) |
2358 | goto fail4; | |
2359 | BUG_ON(efx->irq_status.dma_addr & 0x0f); | |
2360 | ||
62776d03 BH |
2361 | netif_dbg(efx, probe, efx->net_dev, |
2362 | "INT_KER at %llx (virt %p phys %llx)\n", | |
2363 | (u64)efx->irq_status.dma_addr, | |
2364 | efx->irq_status.addr, | |
2365 | (u64)virt_to_phys(efx->irq_status.addr)); | |
8ceee660 | 2366 | |
4a5b504d BH |
2367 | falcon_probe_spi_devices(efx); |
2368 | ||
8ceee660 BH |
2369 | /* Read in the non-volatile configuration */ |
2370 | rc = falcon_probe_nvconfig(efx); | |
6c88b0b6 BH |
2371 | if (rc) { |
2372 | if (rc == -EINVAL) | |
2373 | netif_err(efx, probe, efx->net_dev, "NVRAM is invalid\n"); | |
8ceee660 | 2374 | goto fail5; |
6c88b0b6 | 2375 | } |
8ceee660 | 2376 | |
5a6681e2 EC |
2377 | efx->max_channels = (ef4_nic_rev(efx) <= EF4_REV_FALCON_A1 ? 4 : |
2378 | EF4_MAX_CHANNELS); | |
b0fbdae1 | 2379 | efx->max_tx_channels = efx->max_channels; |
cc180b69 | 2380 | efx->timer_quantum_ns = 4968; /* 621 cycles */ |
d95e329a BK |
2381 | efx->timer_max_ns = efx->type->timer_period_max * |
2382 | efx->timer_quantum_ns; | |
cc180b69 | 2383 | |
37b5a603 | 2384 | /* Initialise I2C adapter */ |
e775fb93 BH |
2385 | board = falcon_board(efx); |
2386 | board->i2c_adap.owner = THIS_MODULE; | |
2387 | board->i2c_data = falcon_i2c_bit_operations; | |
2388 | board->i2c_data.data = efx; | |
2389 | board->i2c_adap.algo_data = &board->i2c_data; | |
2390 | board->i2c_adap.dev.parent = &efx->pci_dev->dev; | |
2391 | strlcpy(board->i2c_adap.name, "SFC4000 GPIO", | |
2392 | sizeof(board->i2c_adap.name)); | |
2393 | rc = i2c_bit_add_bus(&board->i2c_adap); | |
37b5a603 BH |
2394 | if (rc) |
2395 | goto fail5; | |
2396 | ||
44838a44 | 2397 | rc = falcon_board(efx)->type->init(efx); |
278c0621 | 2398 | if (rc) { |
62776d03 BH |
2399 | netif_err(efx, probe, efx->net_dev, |
2400 | "failed to initialise board\n"); | |
278c0621 BH |
2401 | goto fail6; |
2402 | } | |
2403 | ||
55edc6e6 BH |
2404 | nic_data->stats_disable_count = 1; |
2405 | setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func, | |
2406 | (unsigned long)efx); | |
2407 | ||
8ceee660 BH |
2408 | return 0; |
2409 | ||
278c0621 | 2410 | fail6: |
bf51a8c5 | 2411 | i2c_del_adapter(&board->i2c_adap); |
e775fb93 | 2412 | memset(&board->i2c_adap, 0, sizeof(board->i2c_adap)); |
8ceee660 | 2413 | fail5: |
5a6681e2 | 2414 | ef4_nic_free_buffer(efx, &efx->irq_status); |
8ceee660 | 2415 | fail4: |
8ceee660 BH |
2416 | fail3: |
2417 | if (nic_data->pci_dev2) { | |
2418 | pci_dev_put(nic_data->pci_dev2); | |
2419 | nic_data->pci_dev2 = NULL; | |
2420 | } | |
2421 | fail2: | |
8ceee660 BH |
2422 | fail1: |
2423 | kfree(efx->nic_data); | |
2424 | return rc; | |
2425 | } | |
2426 | ||
5a6681e2 | 2427 | static void falcon_init_rx_cfg(struct ef4_nic *efx) |
56241ceb | 2428 | { |
56241ceb BH |
2429 | /* RX control FIFO thresholds (32 entries) */ |
2430 | const unsigned ctrl_xon_thr = 20; | |
2431 | const unsigned ctrl_xoff_thr = 25; | |
5a6681e2 | 2432 | ef4_oword_t reg; |
56241ceb | 2433 | |
5a6681e2 EC |
2434 | ef4_reado(efx, ®, FR_AZ_RX_CFG); |
2435 | if (ef4_nic_rev(efx) <= EF4_REV_FALCON_A1) { | |
85740cdf BH |
2436 | /* Data FIFO size is 5.5K. The RX DMA engine only |
2437 | * supports scattering for user-mode queues, but will | |
2438 | * split DMA writes at intervals of RX_USR_BUF_SIZE | |
2439 | * (32-byte units) even for kernel-mode queues. We | |
2440 | * set it to be so large that that never happens. | |
2441 | */ | |
5a6681e2 EC |
2442 | EF4_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0); |
2443 | EF4_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE, | |
85740cdf | 2444 | (3 * 4096) >> 5); |
5a6681e2 EC |
2445 | EF4_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, 512 >> 8); |
2446 | EF4_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, 2048 >> 8); | |
2447 | EF4_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr); | |
2448 | EF4_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr); | |
56241ceb | 2449 | } else { |
625b4514 | 2450 | /* Data FIFO size is 80K; register fields moved */ |
5a6681e2 EC |
2451 | EF4_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0); |
2452 | EF4_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE, | |
2453 | EF4_RX_USR_BUF_SIZE >> 5); | |
5fb6b06d | 2454 | /* Send XON and XOFF at ~3 * max MTU away from empty/full */ |
5a6681e2 EC |
2455 | EF4_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, 27648 >> 8); |
2456 | EF4_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, 54272 >> 8); | |
2457 | EF4_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr); | |
2458 | EF4_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr); | |
2459 | EF4_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1); | |
477e54eb BH |
2460 | |
2461 | /* Enable hash insertion. This is broken for the | |
2462 | * 'Falcon' hash so also select Toeplitz TCP/IPv4 and | |
2463 | * IPv4 hashes. */ | |
5a6681e2 EC |
2464 | EF4_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_INSRT_HDR, 1); |
2465 | EF4_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_ALG, 1); | |
2466 | EF4_SET_OWORD_FIELD(reg, FRF_BZ_RX_IP_HASH, 1); | |
56241ceb | 2467 | } |
4b0d29dc BH |
2468 | /* Always enable XOFF signal from RX FIFO. We enable |
2469 | * or disable transmission of pause frames at the MAC. */ | |
5a6681e2 EC |
2470 | EF4_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1); |
2471 | ef4_writeo(efx, ®, FR_AZ_RX_CFG); | |
56241ceb BH |
2472 | } |
2473 | ||
152b6a62 BH |
2474 | /* This call performs hardware-specific global initialisation, such as |
2475 | * defining the descriptor cache sizes and number of RSS channels. | |
2476 | * It does not set up any buffers, descriptor rings or event queues. | |
2477 | */ | |
5a6681e2 | 2478 | static int falcon_init_nic(struct ef4_nic *efx) |
152b6a62 | 2479 | { |
5a6681e2 | 2480 | ef4_oword_t temp; |
152b6a62 BH |
2481 | int rc; |
2482 | ||
2483 | /* Use on-chip SRAM */ | |
5a6681e2 EC |
2484 | ef4_reado(efx, &temp, FR_AB_NIC_STAT); |
2485 | EF4_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1); | |
2486 | ef4_writeo(efx, &temp, FR_AB_NIC_STAT); | |
152b6a62 | 2487 | |
152b6a62 BH |
2488 | rc = falcon_reset_sram(efx); |
2489 | if (rc) | |
2490 | return rc; | |
2491 | ||
2492 | /* Clear the parity enables on the TX data fifos as | |
2493 | * they produce false parity errors because of timing issues | |
2494 | */ | |
5a6681e2 EC |
2495 | if (EF4_WORKAROUND_5129(efx)) { |
2496 | ef4_reado(efx, &temp, FR_AZ_CSR_SPARE); | |
2497 | EF4_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0); | |
2498 | ef4_writeo(efx, &temp, FR_AZ_CSR_SPARE); | |
152b6a62 BH |
2499 | } |
2500 | ||
5a6681e2 EC |
2501 | if (EF4_WORKAROUND_7244(efx)) { |
2502 | ef4_reado(efx, &temp, FR_BZ_RX_FILTER_CTL); | |
2503 | EF4_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8); | |
2504 | EF4_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8); | |
2505 | EF4_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8); | |
2506 | EF4_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8); | |
2507 | ef4_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL); | |
8ceee660 | 2508 | } |
8ceee660 | 2509 | |
3e6c4538 | 2510 | /* XXX This is documented only for Falcon A0/A1 */ |
8ceee660 BH |
2511 | /* Setup RX. Wait for descriptor is broken and must |
2512 | * be disabled. RXDP recovery shouldn't be needed, but is. | |
2513 | */ | |
5a6681e2 EC |
2514 | ef4_reado(efx, &temp, FR_AA_RX_SELF_RST); |
2515 | EF4_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1); | |
2516 | EF4_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1); | |
2517 | if (EF4_WORKAROUND_5583(efx)) | |
2518 | EF4_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1); | |
2519 | ef4_writeo(efx, &temp, FR_AA_RX_SELF_RST); | |
8ceee660 | 2520 | |
8ceee660 BH |
2521 | /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16 |
2522 | * descriptors (which is bad). | |
2523 | */ | |
5a6681e2 EC |
2524 | ef4_reado(efx, &temp, FR_AZ_TX_CFG); |
2525 | EF4_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0); | |
2526 | ef4_writeo(efx, &temp, FR_AZ_TX_CFG); | |
8ceee660 | 2527 | |
56241ceb | 2528 | falcon_init_rx_cfg(efx); |
8ceee660 | 2529 | |
5a6681e2 | 2530 | if (ef4_nic_rev(efx) >= EF4_REV_FALCON_B0) { |
267c0157 | 2531 | falcon_b0_rx_push_rss_config(efx, false, efx->rx_indir_table); |
477e54eb BH |
2532 | |
2533 | /* Set destination of both TX and RX Flush events */ | |
5a6681e2 EC |
2534 | EF4_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0); |
2535 | ef4_writeo(efx, &temp, FR_BZ_DP_CTRL); | |
8ceee660 BH |
2536 | } |
2537 | ||
5a6681e2 | 2538 | ef4_farch_init_common(efx); |
152b6a62 | 2539 | |
8ceee660 BH |
2540 | return 0; |
2541 | } | |
2542 | ||
5a6681e2 | 2543 | static void falcon_remove_nic(struct ef4_nic *efx) |
8ceee660 BH |
2544 | { |
2545 | struct falcon_nic_data *nic_data = efx->nic_data; | |
e775fb93 | 2546 | struct falcon_board *board = falcon_board(efx); |
37b5a603 | 2547 | |
44838a44 | 2548 | board->type->fini(efx); |
278c0621 | 2549 | |
8c870379 | 2550 | /* Remove I2C adapter and clear it in preparation for a retry */ |
bf51a8c5 | 2551 | i2c_del_adapter(&board->i2c_adap); |
e775fb93 | 2552 | memset(&board->i2c_adap, 0, sizeof(board->i2c_adap)); |
8ceee660 | 2553 | |
5a6681e2 | 2554 | ef4_nic_free_buffer(efx, &efx->irq_status); |
8ceee660 | 2555 | |
4de92180 | 2556 | __falcon_reset_hw(efx, RESET_TYPE_ALL); |
8ceee660 BH |
2557 | |
2558 | /* Release the second function after the reset */ | |
2559 | if (nic_data->pci_dev2) { | |
2560 | pci_dev_put(nic_data->pci_dev2); | |
2561 | nic_data->pci_dev2 = NULL; | |
2562 | } | |
2563 | ||
2564 | /* Tear down the private nic state */ | |
2565 | kfree(efx->nic_data); | |
2566 | efx->nic_data = NULL; | |
2567 | } | |
2568 | ||
5a6681e2 | 2569 | static size_t falcon_describe_nic_stats(struct ef4_nic *efx, u8 *names) |
cd0ecc9a | 2570 | { |
5a6681e2 | 2571 | return ef4_nic_describe_stats(falcon_stat_desc, FALCON_STAT_COUNT, |
cd0ecc9a BH |
2572 | falcon_stat_mask, names); |
2573 | } | |
2574 | ||
5a6681e2 | 2575 | static size_t falcon_update_nic_stats(struct ef4_nic *efx, u64 *full_stats, |
cd0ecc9a | 2576 | struct rtnl_link_stats64 *core_stats) |
8ceee660 | 2577 | { |
55edc6e6 | 2578 | struct falcon_nic_data *nic_data = efx->nic_data; |
cd0ecc9a | 2579 | u64 *stats = nic_data->stats; |
5a6681e2 | 2580 | ef4_oword_t cnt; |
8ceee660 | 2581 | |
cd0ecc9a | 2582 | if (!nic_data->stats_disable_count) { |
5a6681e2 | 2583 | ef4_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP); |
cd0ecc9a | 2584 | stats[FALCON_STAT_rx_nodesc_drop_cnt] += |
5a6681e2 | 2585 | EF4_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT); |
cd0ecc9a BH |
2586 | |
2587 | if (nic_data->stats_pending && | |
2588 | FALCON_XMAC_STATS_DMA_FLAG(efx)) { | |
2589 | nic_data->stats_pending = false; | |
2590 | rmb(); /* read the done flag before the stats */ | |
5a6681e2 | 2591 | ef4_nic_update_stats( |
cd0ecc9a BH |
2592 | falcon_stat_desc, FALCON_STAT_COUNT, |
2593 | falcon_stat_mask, | |
2594 | stats, efx->stats_buffer.addr, true); | |
2595 | } | |
55edc6e6 | 2596 | |
cd0ecc9a | 2597 | /* Update derived statistic */ |
5a6681e2 | 2598 | ef4_update_diff_stat(&stats[FALCON_STAT_rx_bad_bytes], |
cd0ecc9a BH |
2599 | stats[FALCON_STAT_rx_bytes] - |
2600 | stats[FALCON_STAT_rx_good_bytes] - | |
2601 | stats[FALCON_STAT_rx_control] * 64); | |
5a6681e2 | 2602 | ef4_update_sw_stats(efx, stats); |
cd0ecc9a | 2603 | } |
55edc6e6 | 2604 | |
cd0ecc9a BH |
2605 | if (full_stats) |
2606 | memcpy(full_stats, stats, sizeof(u64) * FALCON_STAT_COUNT); | |
2607 | ||
2608 | if (core_stats) { | |
2609 | core_stats->rx_packets = stats[FALCON_STAT_rx_packets]; | |
2610 | core_stats->tx_packets = stats[FALCON_STAT_tx_packets]; | |
2611 | core_stats->rx_bytes = stats[FALCON_STAT_rx_bytes]; | |
2612 | core_stats->tx_bytes = stats[FALCON_STAT_tx_bytes]; | |
e4d112e4 EC |
2613 | core_stats->rx_dropped = stats[FALCON_STAT_rx_nodesc_drop_cnt] + |
2614 | stats[GENERIC_STAT_rx_nodesc_trunc] + | |
2615 | stats[GENERIC_STAT_rx_noskb_drops]; | |
cd0ecc9a BH |
2616 | core_stats->multicast = stats[FALCON_STAT_rx_multicast]; |
2617 | core_stats->rx_length_errors = | |
2618 | stats[FALCON_STAT_rx_gtjumbo] + | |
2619 | stats[FALCON_STAT_rx_length_error]; | |
2620 | core_stats->rx_crc_errors = stats[FALCON_STAT_rx_bad]; | |
2621 | core_stats->rx_frame_errors = stats[FALCON_STAT_rx_align_error]; | |
2622 | core_stats->rx_fifo_errors = stats[FALCON_STAT_rx_overflow]; | |
2623 | ||
2624 | core_stats->rx_errors = (core_stats->rx_length_errors + | |
2625 | core_stats->rx_crc_errors + | |
2626 | core_stats->rx_frame_errors + | |
2627 | stats[FALCON_STAT_rx_symbol_error]); | |
55edc6e6 | 2628 | } |
cd0ecc9a BH |
2629 | |
2630 | return FALCON_STAT_COUNT; | |
55edc6e6 BH |
2631 | } |
2632 | ||
5a6681e2 | 2633 | void falcon_start_nic_stats(struct ef4_nic *efx) |
55edc6e6 BH |
2634 | { |
2635 | struct falcon_nic_data *nic_data = efx->nic_data; | |
2636 | ||
2637 | spin_lock_bh(&efx->stats_lock); | |
2638 | if (--nic_data->stats_disable_count == 0) | |
2639 | falcon_stats_request(efx); | |
2640 | spin_unlock_bh(&efx->stats_lock); | |
2641 | } | |
2642 | ||
f8f3b5ae JC |
2643 | /* We don't acutally pull stats on falcon. Wait 10ms so that |
2644 | * they arrive when we call this just after start_stats | |
2645 | */ | |
5a6681e2 | 2646 | static void falcon_pull_nic_stats(struct ef4_nic *efx) |
f8f3b5ae JC |
2647 | { |
2648 | msleep(10); | |
2649 | } | |
2650 | ||
5a6681e2 | 2651 | void falcon_stop_nic_stats(struct ef4_nic *efx) |
55edc6e6 BH |
2652 | { |
2653 | struct falcon_nic_data *nic_data = efx->nic_data; | |
2654 | int i; | |
2655 | ||
2656 | might_sleep(); | |
2657 | ||
2658 | spin_lock_bh(&efx->stats_lock); | |
2659 | ++nic_data->stats_disable_count; | |
2660 | spin_unlock_bh(&efx->stats_lock); | |
2661 | ||
2662 | del_timer_sync(&nic_data->stats_timer); | |
2663 | ||
2664 | /* Wait enough time for the most recent transfer to | |
2665 | * complete. */ | |
2666 | for (i = 0; i < 4 && nic_data->stats_pending; i++) { | |
e5136124 | 2667 | if (FALCON_XMAC_STATS_DMA_FLAG(efx)) |
55edc6e6 BH |
2668 | break; |
2669 | msleep(1); | |
2670 | } | |
2671 | ||
2672 | spin_lock_bh(&efx->stats_lock); | |
2673 | falcon_stats_complete(efx); | |
2674 | spin_unlock_bh(&efx->stats_lock); | |
8ceee660 BH |
2675 | } |
2676 | ||
5a6681e2 | 2677 | static void falcon_set_id_led(struct ef4_nic *efx, enum ef4_led_mode mode) |
06629f07 BH |
2678 | { |
2679 | falcon_board(efx)->type->set_id_led(efx, mode); | |
2680 | } | |
2681 | ||
89c758fa BH |
2682 | /************************************************************************** |
2683 | * | |
2684 | * Wake on LAN | |
2685 | * | |
2686 | ************************************************************************** | |
2687 | */ | |
2688 | ||
5a6681e2 | 2689 | static void falcon_get_wol(struct ef4_nic *efx, struct ethtool_wolinfo *wol) |
89c758fa BH |
2690 | { |
2691 | wol->supported = 0; | |
2692 | wol->wolopts = 0; | |
2693 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
2694 | } | |
2695 | ||
5a6681e2 | 2696 | static int falcon_set_wol(struct ef4_nic *efx, u32 type) |
89c758fa BH |
2697 | { |
2698 | if (type != 0) | |
2699 | return -EINVAL; | |
2700 | return 0; | |
2701 | } | |
2702 | ||
8ceee660 BH |
2703 | /************************************************************************** |
2704 | * | |
754c653a | 2705 | * Revision-dependent attributes used by efx.c and nic.c |
8ceee660 BH |
2706 | * |
2707 | ************************************************************************** | |
2708 | */ | |
2709 | ||
5a6681e2 EC |
2710 | const struct ef4_nic_type falcon_a1_nic_type = { |
2711 | .mem_bar = EF4_MEM_BAR, | |
b105798f | 2712 | .mem_map_size = falcon_a1_mem_map_size, |
ef2b90ee BH |
2713 | .probe = falcon_probe_nic, |
2714 | .remove = falcon_remove_nic, | |
2715 | .init = falcon_init_nic, | |
28e47c49 | 2716 | .dimension_resources = falcon_dimension_resources, |
1840667a | 2717 | .fini = falcon_irq_ack_a1, |
ef2b90ee | 2718 | .monitor = falcon_monitor, |
0e2a9c7c BH |
2719 | .map_reset_reason = falcon_map_reset_reason, |
2720 | .map_reset_flags = falcon_map_reset_flags, | |
ef2b90ee BH |
2721 | .reset = falcon_reset_hw, |
2722 | .probe_port = falcon_probe_port, | |
2723 | .remove_port = falcon_remove_port, | |
40641ed9 | 2724 | .handle_global_event = falcon_handle_global_event, |
5a6681e2 | 2725 | .fini_dmaq = ef4_farch_fini_dmaq, |
ef2b90ee | 2726 | .prepare_flush = falcon_prepare_flush, |
5a6681e2 EC |
2727 | .finish_flush = ef4_port_dummy_op_void, |
2728 | .prepare_flr = ef4_port_dummy_op_void, | |
2729 | .finish_flr = ef4_farch_finish_flr, | |
cd0ecc9a | 2730 | .describe_stats = falcon_describe_nic_stats, |
ef2b90ee BH |
2731 | .update_stats = falcon_update_nic_stats, |
2732 | .start_stats = falcon_start_nic_stats, | |
f8f3b5ae | 2733 | .pull_stats = falcon_pull_nic_stats, |
ef2b90ee | 2734 | .stop_stats = falcon_stop_nic_stats, |
06629f07 | 2735 | .set_id_led = falcon_set_id_led, |
ef2b90ee | 2736 | .push_irq_moderation = falcon_push_irq_moderation, |
d3245b28 | 2737 | .reconfigure_port = falcon_reconfigure_port, |
9dd3a13b | 2738 | .prepare_enable_fc_tx = falcon_a1_prepare_enable_fc_tx, |
710b208d BH |
2739 | .reconfigure_mac = falcon_reconfigure_xmac, |
2740 | .check_mac_fault = falcon_xmac_check_fault, | |
89c758fa BH |
2741 | .get_wol = falcon_get_wol, |
2742 | .set_wol = falcon_set_wol, | |
5a6681e2 | 2743 | .resume_wol = ef4_port_dummy_op_void, |
0aa3fbaa | 2744 | .test_nvram = falcon_test_nvram, |
5a6681e2 EC |
2745 | .irq_enable_master = ef4_farch_irq_enable_master, |
2746 | .irq_test_generate = ef4_farch_irq_test_generate, | |
2747 | .irq_disable_non_ev = ef4_farch_irq_disable_master, | |
2748 | .irq_handle_msi = ef4_farch_msi_interrupt, | |
86094f7f | 2749 | .irq_handle_legacy = falcon_legacy_interrupt_a1, |
5a6681e2 EC |
2750 | .tx_probe = ef4_farch_tx_probe, |
2751 | .tx_init = ef4_farch_tx_init, | |
2752 | .tx_remove = ef4_farch_tx_remove, | |
2753 | .tx_write = ef4_farch_tx_write, | |
2754 | .tx_limit_len = ef4_farch_tx_limit_len, | |
267c0157 | 2755 | .rx_push_rss_config = dummy_rx_push_rss_config, |
5a6681e2 EC |
2756 | .rx_probe = ef4_farch_rx_probe, |
2757 | .rx_init = ef4_farch_rx_init, | |
2758 | .rx_remove = ef4_farch_rx_remove, | |
2759 | .rx_write = ef4_farch_rx_write, | |
2760 | .rx_defer_refill = ef4_farch_rx_defer_refill, | |
2761 | .ev_probe = ef4_farch_ev_probe, | |
2762 | .ev_init = ef4_farch_ev_init, | |
2763 | .ev_fini = ef4_farch_ev_fini, | |
2764 | .ev_remove = ef4_farch_ev_remove, | |
2765 | .ev_process = ef4_farch_ev_process, | |
2766 | .ev_read_ack = ef4_farch_ev_read_ack, | |
2767 | .ev_test_generate = ef4_farch_ev_test_generate, | |
b895d73e | 2768 | |
add72477 BH |
2769 | /* We don't expose the filter table on Falcon A1 as it is not |
2770 | * mapped into function 0, but these implementations still | |
2771 | * work with a degenerate case of all tables set to size 0. | |
2772 | */ | |
5a6681e2 EC |
2773 | .filter_table_probe = ef4_farch_filter_table_probe, |
2774 | .filter_table_restore = ef4_farch_filter_table_restore, | |
2775 | .filter_table_remove = ef4_farch_filter_table_remove, | |
2776 | .filter_insert = ef4_farch_filter_insert, | |
2777 | .filter_remove_safe = ef4_farch_filter_remove_safe, | |
2778 | .filter_get_safe = ef4_farch_filter_get_safe, | |
2779 | .filter_clear_rx = ef4_farch_filter_clear_rx, | |
2780 | .filter_count_rx_used = ef4_farch_filter_count_rx_used, | |
2781 | .filter_get_rx_id_limit = ef4_farch_filter_get_rx_id_limit, | |
2782 | .filter_get_rx_ids = ef4_farch_filter_get_rx_ids, | |
2783 | ||
2784 | #ifdef CONFIG_SFC_FALCON_MTD | |
45a3fd55 BH |
2785 | .mtd_probe = falcon_mtd_probe, |
2786 | .mtd_rename = falcon_mtd_rename, | |
2787 | .mtd_read = falcon_mtd_read, | |
2788 | .mtd_erase = falcon_mtd_erase, | |
2789 | .mtd_write = falcon_mtd_write, | |
2790 | .mtd_sync = falcon_mtd_sync, | |
2791 | #endif | |
2792 | ||
5a6681e2 | 2793 | .revision = EF4_REV_FALCON_A1, |
3e6c4538 BH |
2794 | .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER, |
2795 | .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER, | |
2796 | .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER, | |
2797 | .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER, | |
2798 | .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER, | |
6d51d307 | 2799 | .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), |
8ceee660 | 2800 | .rx_buffer_padding = 0x24, |
85740cdf | 2801 | .can_rx_scatter = false, |
5a6681e2 | 2802 | .max_interrupt_mode = EF4_INT_MODE_MSI, |
cc180b69 | 2803 | .timer_period_max = 1 << FRF_AB_TC_TIMER_VAL_WIDTH, |
c383b537 | 2804 | .offload_features = NETIF_F_IP_CSUM, |
8ceee660 BH |
2805 | }; |
2806 | ||
5a6681e2 EC |
2807 | const struct ef4_nic_type falcon_b0_nic_type = { |
2808 | .mem_bar = EF4_MEM_BAR, | |
b105798f | 2809 | .mem_map_size = falcon_b0_mem_map_size, |
ef2b90ee BH |
2810 | .probe = falcon_probe_nic, |
2811 | .remove = falcon_remove_nic, | |
2812 | .init = falcon_init_nic, | |
28e47c49 | 2813 | .dimension_resources = falcon_dimension_resources, |
5a6681e2 | 2814 | .fini = ef4_port_dummy_op_void, |
ef2b90ee | 2815 | .monitor = falcon_monitor, |
0e2a9c7c BH |
2816 | .map_reset_reason = falcon_map_reset_reason, |
2817 | .map_reset_flags = falcon_map_reset_flags, | |
ef2b90ee BH |
2818 | .reset = falcon_reset_hw, |
2819 | .probe_port = falcon_probe_port, | |
2820 | .remove_port = falcon_remove_port, | |
40641ed9 | 2821 | .handle_global_event = falcon_handle_global_event, |
5a6681e2 | 2822 | .fini_dmaq = ef4_farch_fini_dmaq, |
ef2b90ee | 2823 | .prepare_flush = falcon_prepare_flush, |
5a6681e2 EC |
2824 | .finish_flush = ef4_port_dummy_op_void, |
2825 | .prepare_flr = ef4_port_dummy_op_void, | |
2826 | .finish_flr = ef4_farch_finish_flr, | |
cd0ecc9a | 2827 | .describe_stats = falcon_describe_nic_stats, |
ef2b90ee BH |
2828 | .update_stats = falcon_update_nic_stats, |
2829 | .start_stats = falcon_start_nic_stats, | |
f8f3b5ae | 2830 | .pull_stats = falcon_pull_nic_stats, |
ef2b90ee | 2831 | .stop_stats = falcon_stop_nic_stats, |
06629f07 | 2832 | .set_id_led = falcon_set_id_led, |
ef2b90ee | 2833 | .push_irq_moderation = falcon_push_irq_moderation, |
d3245b28 | 2834 | .reconfigure_port = falcon_reconfigure_port, |
9dd3a13b | 2835 | .prepare_enable_fc_tx = falcon_b0_prepare_enable_fc_tx, |
710b208d BH |
2836 | .reconfigure_mac = falcon_reconfigure_xmac, |
2837 | .check_mac_fault = falcon_xmac_check_fault, | |
89c758fa BH |
2838 | .get_wol = falcon_get_wol, |
2839 | .set_wol = falcon_set_wol, | |
5a6681e2 | 2840 | .resume_wol = ef4_port_dummy_op_void, |
d4f2cecc | 2841 | .test_chip = falcon_b0_test_chip, |
0aa3fbaa | 2842 | .test_nvram = falcon_test_nvram, |
5a6681e2 EC |
2843 | .irq_enable_master = ef4_farch_irq_enable_master, |
2844 | .irq_test_generate = ef4_farch_irq_test_generate, | |
2845 | .irq_disable_non_ev = ef4_farch_irq_disable_master, | |
2846 | .irq_handle_msi = ef4_farch_msi_interrupt, | |
2847 | .irq_handle_legacy = ef4_farch_legacy_interrupt, | |
2848 | .tx_probe = ef4_farch_tx_probe, | |
2849 | .tx_init = ef4_farch_tx_init, | |
2850 | .tx_remove = ef4_farch_tx_remove, | |
2851 | .tx_write = ef4_farch_tx_write, | |
2852 | .tx_limit_len = ef4_farch_tx_limit_len, | |
d43050c0 | 2853 | .rx_push_rss_config = falcon_b0_rx_push_rss_config, |
5a6681e2 EC |
2854 | .rx_probe = ef4_farch_rx_probe, |
2855 | .rx_init = ef4_farch_rx_init, | |
2856 | .rx_remove = ef4_farch_rx_remove, | |
2857 | .rx_write = ef4_farch_rx_write, | |
2858 | .rx_defer_refill = ef4_farch_rx_defer_refill, | |
2859 | .ev_probe = ef4_farch_ev_probe, | |
2860 | .ev_init = ef4_farch_ev_init, | |
2861 | .ev_fini = ef4_farch_ev_fini, | |
2862 | .ev_remove = ef4_farch_ev_remove, | |
2863 | .ev_process = ef4_farch_ev_process, | |
2864 | .ev_read_ack = ef4_farch_ev_read_ack, | |
2865 | .ev_test_generate = ef4_farch_ev_test_generate, | |
2866 | .filter_table_probe = ef4_farch_filter_table_probe, | |
2867 | .filter_table_restore = ef4_farch_filter_table_restore, | |
2868 | .filter_table_remove = ef4_farch_filter_table_remove, | |
2869 | .filter_update_rx_scatter = ef4_farch_filter_update_rx_scatter, | |
2870 | .filter_insert = ef4_farch_filter_insert, | |
2871 | .filter_remove_safe = ef4_farch_filter_remove_safe, | |
2872 | .filter_get_safe = ef4_farch_filter_get_safe, | |
2873 | .filter_clear_rx = ef4_farch_filter_clear_rx, | |
2874 | .filter_count_rx_used = ef4_farch_filter_count_rx_used, | |
2875 | .filter_get_rx_id_limit = ef4_farch_filter_get_rx_id_limit, | |
2876 | .filter_get_rx_ids = ef4_farch_filter_get_rx_ids, | |
add72477 | 2877 | #ifdef CONFIG_RFS_ACCEL |
5a6681e2 EC |
2878 | .filter_rfs_insert = ef4_farch_filter_rfs_insert, |
2879 | .filter_rfs_expire_one = ef4_farch_filter_rfs_expire_one, | |
add72477 | 2880 | #endif |
5a6681e2 | 2881 | #ifdef CONFIG_SFC_FALCON_MTD |
45a3fd55 BH |
2882 | .mtd_probe = falcon_mtd_probe, |
2883 | .mtd_rename = falcon_mtd_rename, | |
2884 | .mtd_read = falcon_mtd_read, | |
2885 | .mtd_erase = falcon_mtd_erase, | |
2886 | .mtd_write = falcon_mtd_write, | |
2887 | .mtd_sync = falcon_mtd_sync, | |
2888 | #endif | |
b895d73e | 2889 | |
5a6681e2 | 2890 | .revision = EF4_REV_FALCON_B0, |
3e6c4538 BH |
2891 | .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL, |
2892 | .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL, | |
2893 | .buf_tbl_base = FR_BZ_BUF_FULL_TBL, | |
2894 | .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL, | |
2895 | .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR, | |
6d51d307 | 2896 | .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), |
43a3739d JC |
2897 | .rx_prefix_size = FS_BZ_RX_PREFIX_SIZE, |
2898 | .rx_hash_offset = FS_BZ_RX_PREFIX_HASH_OFST, | |
8ceee660 | 2899 | .rx_buffer_padding = 0, |
85740cdf | 2900 | .can_rx_scatter = true, |
5a6681e2 | 2901 | .max_interrupt_mode = EF4_INT_MODE_MSIX, |
cc180b69 | 2902 | .timer_period_max = 1 << FRF_AB_TC_TIMER_VAL_WIDTH, |
b4187e42 | 2903 | .offload_features = NETIF_F_IP_CSUM | NETIF_F_RXHASH | NETIF_F_NTUPLE, |
add72477 | 2904 | .max_rx_ip_filters = FR_BZ_RX_FILTER_TBL0_ROWS, |
8ceee660 | 2905 | }; |