Commit | Line | Data |
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8ceee660 | 1 | /**************************************************************************** |
f7a6d2c4 | 2 | * Driver for Solarflare network controllers and boards |
8ceee660 | 3 | * Copyright 2005-2006 Fen Systems Ltd. |
f7a6d2c4 | 4 | * Copyright 2006-2013 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #ifndef EFX_EFX_H | |
12 | #define EFX_EFX_H | |
13 | ||
14 | #include "net_driver.h" | |
64eebcfd | 15 | #include "filter.h" |
8ceee660 | 16 | |
6a350fdb | 17 | /* All controllers use BAR 0 for I/O space and BAR 2(&3) for memory */ |
02246a7f | 18 | /* All VFs use BAR 0/1 for memory */ |
dc803df8 | 19 | #define EFX_MEM_BAR 2 |
02246a7f | 20 | #define EFX_MEM_VF_BAR 0 |
dc803df8 | 21 | |
e340be92 SS |
22 | int efx_net_open(struct net_device *net_dev); |
23 | int efx_net_stop(struct net_device *net_dev); | |
24 | ||
8ceee660 | 25 | /* TX */ |
00aef986 JP |
26 | int efx_probe_tx_queue(struct efx_tx_queue *tx_queue); |
27 | void efx_remove_tx_queue(struct efx_tx_queue *tx_queue); | |
28 | void efx_init_tx_queue(struct efx_tx_queue *tx_queue); | |
29 | void efx_init_tx_queue_core_txq(struct efx_tx_queue *tx_queue); | |
30 | void efx_fini_tx_queue(struct efx_tx_queue *tx_queue); | |
31 | netdev_tx_t efx_hard_start_xmit(struct sk_buff *skb, | |
32 | struct net_device *net_dev); | |
33 | netdev_tx_t efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb); | |
34 | void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index); | |
a5fcf8a6 JP |
35 | int efx_setup_tc(struct net_device *net_dev, u32 handle, u32 chain_index, |
36 | __be16 proto, struct tc_to_netdev *tc); | |
00aef986 | 37 | unsigned int efx_tx_max_skb_descs(struct efx_nic *efx); |
183233be | 38 | extern unsigned int efx_piobuf_size; |
b0fbdae1 | 39 | extern bool efx_separate_tx_channels; |
8ceee660 BH |
40 | |
41 | /* RX */ | |
267c0157 | 42 | void efx_set_default_rx_indir_table(struct efx_nic *efx); |
00aef986 JP |
43 | void efx_rx_config_page_split(struct efx_nic *efx); |
44 | int efx_probe_rx_queue(struct efx_rx_queue *rx_queue); | |
45 | void efx_remove_rx_queue(struct efx_rx_queue *rx_queue); | |
46 | void efx_init_rx_queue(struct efx_rx_queue *rx_queue); | |
47 | void efx_fini_rx_queue(struct efx_rx_queue *rx_queue); | |
cce28794 | 48 | void efx_fast_push_rx_descriptors(struct efx_rx_queue *rx_queue, bool atomic); |
00aef986 JP |
49 | void efx_rx_slow_fill(unsigned long context); |
50 | void __efx_rx_packet(struct efx_channel *channel); | |
51 | void efx_rx_packet(struct efx_rx_queue *rx_queue, unsigned int index, | |
52 | unsigned int n_frags, unsigned int len, u16 flags); | |
ff734ef4 BH |
53 | static inline void efx_rx_flush_packet(struct efx_channel *channel) |
54 | { | |
85740cdf BH |
55 | if (channel->rx_pkt_n_frags) |
56 | __efx_rx_packet(channel); | |
ff734ef4 | 57 | } |
00aef986 | 58 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue); |
ecc910f5 SH |
59 | |
60 | #define EFX_MAX_DMAQ_SIZE 4096UL | |
61 | #define EFX_DEFAULT_DMAQ_SIZE 1024UL | |
62 | #define EFX_MIN_DMAQ_SIZE 512UL | |
63 | ||
64 | #define EFX_MAX_EVQ_SIZE 16384UL | |
65 | #define EFX_MIN_EVQ_SIZE 512UL | |
8ceee660 | 66 | |
7e6d06f0 BH |
67 | /* Maximum number of TCP segments we support for soft-TSO */ |
68 | #define EFX_TSO_MAX_SEGS 100 | |
69 | ||
70 | /* The smallest [rt]xq_entries that the driver supports. RX minimum | |
71 | * is a bit arbitrary. For TX, we must have space for at least 2 | |
72 | * TSO skbs. | |
73 | */ | |
74 | #define EFX_RXQ_MIN_ENT 128U | |
75 | #define EFX_TXQ_MIN_ENT(efx) (2 * efx_tx_max_skb_descs(efx)) | |
4642610c | 76 | |
a53d26eb BK |
77 | /* All EF10 architecture NICs steal one bit of the DMAQ size for various |
78 | * other purposes when counting TxQ entries, so we halve the queue size. | |
79 | */ | |
80 | #define EFX_TXQ_MAX_ENT(efx) (EFX_WORKAROUND_EF10(efx) ? \ | |
d9317aea BH |
81 | EFX_MAX_DMAQ_SIZE / 2 : EFX_MAX_DMAQ_SIZE) |
82 | ||
f1c2ef40 BK |
83 | static inline bool efx_rss_enabled(struct efx_nic *efx) |
84 | { | |
85 | return efx->rss_spread > 1; | |
86 | } | |
87 | ||
64eebcfd | 88 | /* Filters */ |
add72477 | 89 | |
0d322413 EC |
90 | void efx_mac_reconfigure(struct efx_nic *efx); |
91 | ||
add72477 BH |
92 | /** |
93 | * efx_filter_insert_filter - add or replace a filter | |
94 | * @efx: NIC in which to insert the filter | |
95 | * @spec: Specification for the filter | |
96 | * @replace_equal: Flag for whether the specified filter may replace an | |
97 | * existing filter with equal priority | |
98 | * | |
99 | * On success, return the filter ID. | |
100 | * On failure, return a negative error code. | |
101 | * | |
b883d0bd BH |
102 | * If existing filters have equal match values to the new filter spec, |
103 | * then the new filter might replace them or the function might fail, | |
104 | * as follows. | |
105 | * | |
106 | * 1. If the existing filters have lower priority, or @replace_equal | |
107 | * is set and they have equal priority, replace them. | |
108 | * | |
109 | * 2. If the existing filters have higher priority, return -%EPERM. | |
110 | * | |
111 | * 3. If !efx_filter_is_mc_recipient(@spec), or the NIC does not | |
112 | * support delivery to multiple recipients, return -%EEXIST. | |
113 | * | |
114 | * This implies that filters for multiple multicast recipients must | |
115 | * all be inserted with the same priority and @replace_equal = %false. | |
add72477 BH |
116 | */ |
117 | static inline s32 efx_filter_insert_filter(struct efx_nic *efx, | |
118 | struct efx_filter_spec *spec, | |
119 | bool replace_equal) | |
120 | { | |
121 | return efx->type->filter_insert(efx, spec, replace_equal); | |
122 | } | |
123 | ||
124 | /** | |
125 | * efx_filter_remove_id_safe - remove a filter by ID, carefully | |
126 | * @efx: NIC from which to remove the filter | |
127 | * @priority: Priority of filter, as passed to @efx_filter_insert_filter | |
128 | * @filter_id: ID of filter, as returned by @efx_filter_insert_filter | |
129 | * | |
130 | * This function will range-check @filter_id, so it is safe to call | |
131 | * with a value passed from userland. | |
132 | */ | |
133 | static inline int efx_filter_remove_id_safe(struct efx_nic *efx, | |
134 | enum efx_filter_priority priority, | |
135 | u32 filter_id) | |
136 | { | |
137 | return efx->type->filter_remove_safe(efx, priority, filter_id); | |
138 | } | |
139 | ||
140 | /** | |
141 | * efx_filter_get_filter_safe - retrieve a filter by ID, carefully | |
142 | * @efx: NIC from which to remove the filter | |
143 | * @priority: Priority of filter, as passed to @efx_filter_insert_filter | |
144 | * @filter_id: ID of filter, as returned by @efx_filter_insert_filter | |
145 | * @spec: Buffer in which to store filter specification | |
146 | * | |
147 | * This function will range-check @filter_id, so it is safe to call | |
148 | * with a value passed from userland. | |
149 | */ | |
150 | static inline int | |
151 | efx_filter_get_filter_safe(struct efx_nic *efx, | |
152 | enum efx_filter_priority priority, | |
153 | u32 filter_id, struct efx_filter_spec *spec) | |
154 | { | |
155 | return efx->type->filter_get_safe(efx, priority, filter_id, spec); | |
156 | } | |
157 | ||
add72477 BH |
158 | static inline u32 efx_filter_count_rx_used(struct efx_nic *efx, |
159 | enum efx_filter_priority priority) | |
160 | { | |
161 | return efx->type->filter_count_rx_used(efx, priority); | |
162 | } | |
163 | static inline u32 efx_filter_get_rx_id_limit(struct efx_nic *efx) | |
164 | { | |
165 | return efx->type->filter_get_rx_id_limit(efx); | |
166 | } | |
167 | static inline s32 efx_filter_get_rx_ids(struct efx_nic *efx, | |
168 | enum efx_filter_priority priority, | |
169 | u32 *buf, u32 size) | |
170 | { | |
171 | return efx->type->filter_get_rx_ids(efx, priority, buf, size); | |
172 | } | |
64d8ad6d | 173 | #ifdef CONFIG_RFS_ACCEL |
00aef986 JP |
174 | int efx_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb, |
175 | u16 rxq_index, u32 flow_id); | |
176 | bool __efx_filter_rfs_expire(struct efx_nic *efx, unsigned quota); | |
64d8ad6d BH |
177 | static inline void efx_filter_rfs_expire(struct efx_channel *channel) |
178 | { | |
179 | if (channel->rfs_filters_added >= 60 && | |
180 | __efx_filter_rfs_expire(channel->efx, 100)) | |
181 | channel->rfs_filters_added -= 60; | |
182 | } | |
183 | #define efx_filter_rfs_enabled() 1 | |
184 | #else | |
185 | static inline void efx_filter_rfs_expire(struct efx_channel *channel) {} | |
186 | #define efx_filter_rfs_enabled() 0 | |
187 | #endif | |
00aef986 | 188 | bool efx_filter_is_mc_recipient(const struct efx_filter_spec *spec); |
64eebcfd | 189 | |
8ceee660 | 190 | /* Channels */ |
00aef986 JP |
191 | int efx_channel_dummy_op_int(struct efx_channel *channel); |
192 | void efx_channel_dummy_op_void(struct efx_channel *channel); | |
193 | int efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries); | |
8ceee660 BH |
194 | |
195 | /* Ports */ | |
00aef986 JP |
196 | int efx_reconfigure_port(struct efx_nic *efx); |
197 | int __efx_reconfigure_port(struct efx_nic *efx); | |
8c8661e4 | 198 | |
f5e7adc3 | 199 | /* Ethtool support */ |
f5e7adc3 BH |
200 | extern const struct ethtool_ops efx_ethtool_ops; |
201 | ||
8c8661e4 | 202 | /* Reset handling */ |
00aef986 JP |
203 | int efx_reset(struct efx_nic *efx, enum reset_type method); |
204 | void efx_reset_down(struct efx_nic *efx, enum reset_type method); | |
205 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok); | |
206 | int efx_try_recovery(struct efx_nic *efx); | |
8ceee660 BH |
207 | |
208 | /* Global */ | |
00aef986 | 209 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type); |
539de7c5 BK |
210 | unsigned int efx_usecs_to_ticks(struct efx_nic *efx, unsigned int usecs); |
211 | unsigned int efx_ticks_to_usecs(struct efx_nic *efx, unsigned int ticks); | |
00aef986 JP |
212 | int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs, |
213 | unsigned int rx_usecs, bool rx_adaptive, | |
214 | bool rx_may_override_tx); | |
215 | void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs, | |
216 | unsigned int *rx_usecs, bool *rx_adaptive); | |
36763266 AR |
217 | void efx_stop_eventq(struct efx_channel *channel); |
218 | void efx_start_eventq(struct efx_channel *channel); | |
8ceee660 BH |
219 | |
220 | /* Dummy PHY ops for PHY drivers */ | |
00aef986 JP |
221 | int efx_port_dummy_op_int(struct efx_nic *efx); |
222 | void efx_port_dummy_op_void(struct efx_nic *efx); | |
8ceee660 | 223 | |
e4d112e4 EC |
224 | /* Update the generic software stats in the passed stats array */ |
225 | void efx_update_sw_stats(struct efx_nic *efx, u64 *stats); | |
226 | ||
f4150724 BH |
227 | /* MTD */ |
228 | #ifdef CONFIG_SFC_MTD | |
00aef986 JP |
229 | int efx_mtd_add(struct efx_nic *efx, struct efx_mtd_partition *parts, |
230 | size_t n_parts, size_t sizeof_part); | |
45a3fd55 BH |
231 | static inline int efx_mtd_probe(struct efx_nic *efx) |
232 | { | |
233 | return efx->type->mtd_probe(efx); | |
234 | } | |
00aef986 JP |
235 | void efx_mtd_rename(struct efx_nic *efx); |
236 | void efx_mtd_remove(struct efx_nic *efx); | |
f4150724 BH |
237 | #else |
238 | static inline int efx_mtd_probe(struct efx_nic *efx) { return 0; } | |
239 | static inline void efx_mtd_rename(struct efx_nic *efx) {} | |
240 | static inline void efx_mtd_remove(struct efx_nic *efx) {} | |
241 | #endif | |
8ceee660 | 242 | |
7fa8d547 SS |
243 | #ifdef CONFIG_SFC_SRIOV |
244 | static inline unsigned int efx_vf_size(struct efx_nic *efx) | |
245 | { | |
246 | return 1 << efx->vi_scale; | |
247 | } | |
248 | #endif | |
249 | ||
8ceee660 BH |
250 | static inline void efx_schedule_channel(struct efx_channel *channel) |
251 | { | |
62776d03 BH |
252 | netif_vdbg(channel->efx, intr, channel->efx->net_dev, |
253 | "channel %d scheduling NAPI poll on CPU%d\n", | |
254 | channel->channel, raw_smp_processor_id()); | |
8ceee660 | 255 | |
288379f0 | 256 | napi_schedule(&channel->napi_str); |
8ceee660 BH |
257 | } |
258 | ||
1646a6f3 BH |
259 | static inline void efx_schedule_channel_irq(struct efx_channel *channel) |
260 | { | |
dd40781e | 261 | channel->event_test_cpu = raw_smp_processor_id(); |
1646a6f3 BH |
262 | efx_schedule_channel(channel); |
263 | } | |
264 | ||
00aef986 JP |
265 | void efx_link_status_changed(struct efx_nic *efx); |
266 | void efx_link_set_advertising(struct efx_nic *efx, u32); | |
267 | void efx_link_set_wanted_fc(struct efx_nic *efx, u8); | |
fdaa9aed | 268 | |
c2f3b8e3 DP |
269 | static inline void efx_device_detach_sync(struct efx_nic *efx) |
270 | { | |
271 | struct net_device *dev = efx->net_dev; | |
272 | ||
273 | /* Lock/freeze all TX queues so that we can be sure the | |
274 | * TX scheduler is stopped when we're done and before | |
275 | * netif_device_present() becomes false. | |
276 | */ | |
35205b21 | 277 | netif_tx_lock_bh(dev); |
c2f3b8e3 | 278 | netif_device_detach(dev); |
35205b21 | 279 | netif_tx_unlock_bh(dev); |
c2f3b8e3 DP |
280 | } |
281 | ||
9c568fd8 PD |
282 | static inline void efx_device_attach_if_not_resetting(struct efx_nic *efx) |
283 | { | |
284 | if ((efx->state != STATE_DISABLED) && !efx->reset_pending) | |
285 | netif_device_attach(efx->net_dev); | |
286 | } | |
287 | ||
dd98708c EC |
288 | static inline bool efx_rwsem_assert_write_locked(struct rw_semaphore *sem) |
289 | { | |
290 | if (WARN_ON(down_read_trylock(sem))) { | |
291 | up_read(sem); | |
292 | return false; | |
293 | } | |
294 | return true; | |
295 | } | |
296 | ||
8ceee660 | 297 | #endif /* EFX_EFX_H */ |