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d2912cb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
9c517165 BH |
2 | /**************************************************************************** |
3 | * Driver for Solarflare network controllers and boards | |
d8d8ccf2 | 4 | * Copyright 2012-2017 Solarflare Communications Inc. |
9c517165 BH |
5 | */ |
6 | ||
7 | #ifndef EFX_EF10_REGS_H | |
8 | #define EFX_EF10_REGS_H | |
9 | ||
10 | /* EF10 hardware architecture definitions have a name prefix following | |
11 | * the format: | |
12 | * | |
13 | * E<type>_<min-rev><max-rev>_ | |
14 | * | |
15 | * The following <type> strings are used: | |
16 | * | |
17 | * MMIO register Host memory structure | |
18 | * ------------------------------------------------------------- | |
19 | * Address R | |
20 | * Bitfield RF SF | |
21 | * Enumerator FE SE | |
22 | * | |
23 | * <min-rev> is the first revision to which the definition applies: | |
24 | * | |
25 | * D: Huntington A0 | |
26 | * | |
27 | * If the definition has been changed or removed in later revisions | |
28 | * then <max-rev> is the last revision to which the definition applies; | |
29 | * otherwise it is "Z". | |
30 | */ | |
31 | ||
32 | /************************************************************************** | |
33 | * | |
34 | * EF10 registers and descriptors | |
35 | * | |
36 | ************************************************************************** | |
37 | */ | |
38 | ||
39 | /* BIU_HW_REV_ID_REG: */ | |
40 | #define ER_DZ_BIU_HW_REV_ID 0x00000000 | |
41 | #define ERF_DZ_HW_REV_ID_LBN 0 | |
42 | #define ERF_DZ_HW_REV_ID_WIDTH 32 | |
43 | ||
44 | /* BIU_MC_SFT_STATUS_REG: */ | |
45 | #define ER_DZ_BIU_MC_SFT_STATUS 0x00000010 | |
46 | #define ER_DZ_BIU_MC_SFT_STATUS_STEP 4 | |
47 | #define ER_DZ_BIU_MC_SFT_STATUS_ROWS 8 | |
48 | #define ERF_DZ_MC_SFT_STATUS_LBN 0 | |
49 | #define ERF_DZ_MC_SFT_STATUS_WIDTH 32 | |
50 | ||
51 | /* BIU_INT_ISR_REG: */ | |
52 | #define ER_DZ_BIU_INT_ISR 0x00000090 | |
53 | #define ERF_DZ_ISR_REG_LBN 0 | |
54 | #define ERF_DZ_ISR_REG_WIDTH 32 | |
55 | ||
56 | /* MC_DB_LWRD_REG: */ | |
57 | #define ER_DZ_MC_DB_LWRD 0x00000200 | |
58 | #define ERF_DZ_MC_DOORBELL_L_LBN 0 | |
59 | #define ERF_DZ_MC_DOORBELL_L_WIDTH 32 | |
60 | ||
61 | /* MC_DB_HWRD_REG: */ | |
62 | #define ER_DZ_MC_DB_HWRD 0x00000204 | |
63 | #define ERF_DZ_MC_DOORBELL_H_LBN 0 | |
64 | #define ERF_DZ_MC_DOORBELL_H_WIDTH 32 | |
65 | ||
66 | /* EVQ_RPTR_REG: */ | |
67 | #define ER_DZ_EVQ_RPTR 0x00000400 | |
68 | #define ER_DZ_EVQ_RPTR_STEP 8192 | |
69 | #define ER_DZ_EVQ_RPTR_ROWS 2048 | |
70 | #define ERF_DZ_EVQ_RPTR_VLD_LBN 15 | |
71 | #define ERF_DZ_EVQ_RPTR_VLD_WIDTH 1 | |
72 | #define ERF_DZ_EVQ_RPTR_LBN 0 | |
73 | #define ERF_DZ_EVQ_RPTR_WIDTH 15 | |
74 | ||
75 | /* EVQ_TMR_REG: */ | |
76 | #define ER_DZ_EVQ_TMR 0x00000420 | |
77 | #define ER_DZ_EVQ_TMR_STEP 8192 | |
78 | #define ER_DZ_EVQ_TMR_ROWS 2048 | |
d8d8ccf2 BK |
79 | #define ERF_FZ_TC_TMR_REL_VAL_LBN 16 |
80 | #define ERF_FZ_TC_TMR_REL_VAL_WIDTH 14 | |
9c517165 BH |
81 | #define ERF_DZ_TC_TIMER_MODE_LBN 14 |
82 | #define ERF_DZ_TC_TIMER_MODE_WIDTH 2 | |
83 | #define ERF_DZ_TC_TIMER_VAL_LBN 0 | |
84 | #define ERF_DZ_TC_TIMER_VAL_WIDTH 14 | |
85 | ||
86 | /* RX_DESC_UPD_REG: */ | |
87 | #define ER_DZ_RX_DESC_UPD 0x00000830 | |
88 | #define ER_DZ_RX_DESC_UPD_STEP 8192 | |
89 | #define ER_DZ_RX_DESC_UPD_ROWS 2048 | |
90 | #define ERF_DZ_RX_DESC_WPTR_LBN 0 | |
91 | #define ERF_DZ_RX_DESC_WPTR_WIDTH 12 | |
92 | ||
93 | /* TX_DESC_UPD_REG: */ | |
94 | #define ER_DZ_TX_DESC_UPD 0x00000a10 | |
95 | #define ER_DZ_TX_DESC_UPD_STEP 8192 | |
96 | #define ER_DZ_TX_DESC_UPD_ROWS 2048 | |
97 | #define ERF_DZ_RSVD_LBN 76 | |
98 | #define ERF_DZ_RSVD_WIDTH 20 | |
99 | #define ERF_DZ_TX_DESC_WPTR_LBN 64 | |
100 | #define ERF_DZ_TX_DESC_WPTR_WIDTH 12 | |
101 | #define ERF_DZ_TX_DESC_HWORD_LBN 32 | |
102 | #define ERF_DZ_TX_DESC_HWORD_WIDTH 32 | |
103 | #define ERF_DZ_TX_DESC_LWORD_LBN 0 | |
104 | #define ERF_DZ_TX_DESC_LWORD_WIDTH 32 | |
105 | ||
106 | /* DRIVER_EV */ | |
107 | #define ESF_DZ_DRV_CODE_LBN 60 | |
108 | #define ESF_DZ_DRV_CODE_WIDTH 4 | |
109 | #define ESF_DZ_DRV_SUB_CODE_LBN 56 | |
110 | #define ESF_DZ_DRV_SUB_CODE_WIDTH 4 | |
111 | #define ESE_DZ_DRV_TIMER_EV 3 | |
112 | #define ESE_DZ_DRV_START_UP_EV 2 | |
113 | #define ESE_DZ_DRV_WAKE_UP_EV 1 | |
114 | #define ESF_DZ_DRV_SUB_DATA_LBN 0 | |
115 | #define ESF_DZ_DRV_SUB_DATA_WIDTH 56 | |
116 | #define ESF_DZ_DRV_EVQ_ID_LBN 0 | |
117 | #define ESF_DZ_DRV_EVQ_ID_WIDTH 14 | |
118 | #define ESF_DZ_DRV_TMR_ID_LBN 0 | |
119 | #define ESF_DZ_DRV_TMR_ID_WIDTH 14 | |
120 | ||
121 | /* EVENT_ENTRY */ | |
122 | #define ESF_DZ_EV_CODE_LBN 60 | |
123 | #define ESF_DZ_EV_CODE_WIDTH 4 | |
124 | #define ESE_DZ_EV_CODE_MCDI_EV 12 | |
125 | #define ESE_DZ_EV_CODE_DRIVER_EV 5 | |
126 | #define ESE_DZ_EV_CODE_TX_EV 2 | |
127 | #define ESE_DZ_EV_CODE_RX_EV 0 | |
128 | #define ESE_DZ_OTHER other | |
129 | #define ESF_DZ_EV_DATA_LBN 0 | |
130 | #define ESF_DZ_EV_DATA_WIDTH 60 | |
131 | ||
132 | /* MC_EVENT */ | |
133 | #define ESF_DZ_MC_CODE_LBN 60 | |
134 | #define ESF_DZ_MC_CODE_WIDTH 4 | |
135 | #define ESF_DZ_MC_OVERRIDE_HOLDOFF_LBN 59 | |
136 | #define ESF_DZ_MC_OVERRIDE_HOLDOFF_WIDTH 1 | |
137 | #define ESF_DZ_MC_DROP_EVENT_LBN 58 | |
138 | #define ESF_DZ_MC_DROP_EVENT_WIDTH 1 | |
139 | #define ESF_DZ_MC_SOFT_LBN 0 | |
140 | #define ESF_DZ_MC_SOFT_WIDTH 58 | |
141 | ||
142 | /* RX_EVENT */ | |
143 | #define ESF_DZ_RX_CODE_LBN 60 | |
144 | #define ESF_DZ_RX_CODE_WIDTH 4 | |
145 | #define ESF_DZ_RX_OVERRIDE_HOLDOFF_LBN 59 | |
146 | #define ESF_DZ_RX_OVERRIDE_HOLDOFF_WIDTH 1 | |
147 | #define ESF_DZ_RX_DROP_EVENT_LBN 58 | |
148 | #define ESF_DZ_RX_DROP_EVENT_WIDTH 1 | |
e17705c4 EC |
149 | #define ESF_DD_RX_EV_RSVD2_LBN 54 |
150 | #define ESF_DD_RX_EV_RSVD2_WIDTH 4 | |
151 | #define ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_LBN 57 | |
152 | #define ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_WIDTH 1 | |
153 | #define ESF_EZ_RX_IP_INNER_CHKSUM_ERR_LBN 56 | |
154 | #define ESF_EZ_RX_IP_INNER_CHKSUM_ERR_WIDTH 1 | |
155 | #define ESF_EZ_RX_EV_RSVD2_LBN 54 | |
156 | #define ESF_EZ_RX_EV_RSVD2_WIDTH 2 | |
9c517165 BH |
157 | #define ESF_DZ_RX_EV_SOFT2_LBN 52 |
158 | #define ESF_DZ_RX_EV_SOFT2_WIDTH 2 | |
159 | #define ESF_DZ_RX_DSC_PTR_LBITS_LBN 48 | |
160 | #define ESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4 | |
d8d8ccf2 BK |
161 | #define ESF_DE_RX_L4_CLASS_LBN 45 |
162 | #define ESF_DE_RX_L4_CLASS_WIDTH 3 | |
163 | #define ESE_DE_L4_CLASS_RSVD7 7 | |
164 | #define ESE_DE_L4_CLASS_RSVD6 6 | |
165 | #define ESE_DE_L4_CLASS_RSVD5 5 | |
166 | #define ESE_DE_L4_CLASS_RSVD4 4 | |
167 | #define ESE_DE_L4_CLASS_RSVD3 3 | |
168 | #define ESE_DE_L4_CLASS_UDP 2 | |
169 | #define ESE_DE_L4_CLASS_TCP 1 | |
170 | #define ESE_DE_L4_CLASS_UNKNOWN 0 | |
171 | #define ESF_FZ_RX_FASTPD_INDCTR_LBN 47 | |
172 | #define ESF_FZ_RX_FASTPD_INDCTR_WIDTH 1 | |
173 | #define ESF_FZ_RX_L4_CLASS_LBN 45 | |
174 | #define ESF_FZ_RX_L4_CLASS_WIDTH 2 | |
175 | #define ESE_FZ_L4_CLASS_RSVD3 3 | |
176 | #define ESE_FZ_L4_CLASS_UDP 2 | |
177 | #define ESE_FZ_L4_CLASS_TCP 1 | |
178 | #define ESE_FZ_L4_CLASS_UNKNOWN 0 | |
9c517165 BH |
179 | #define ESF_DZ_RX_L3_CLASS_LBN 42 |
180 | #define ESF_DZ_RX_L3_CLASS_WIDTH 3 | |
181 | #define ESE_DZ_L3_CLASS_RSVD7 7 | |
182 | #define ESE_DZ_L3_CLASS_IP6_FRAG 6 | |
183 | #define ESE_DZ_L3_CLASS_ARP 5 | |
184 | #define ESE_DZ_L3_CLASS_IP4_FRAG 4 | |
185 | #define ESE_DZ_L3_CLASS_FCOE 3 | |
186 | #define ESE_DZ_L3_CLASS_IP6 2 | |
187 | #define ESE_DZ_L3_CLASS_IP4 1 | |
188 | #define ESE_DZ_L3_CLASS_UNKNOWN 0 | |
189 | #define ESF_DZ_RX_ETH_TAG_CLASS_LBN 39 | |
190 | #define ESF_DZ_RX_ETH_TAG_CLASS_WIDTH 3 | |
191 | #define ESE_DZ_ETH_TAG_CLASS_RSVD7 7 | |
192 | #define ESE_DZ_ETH_TAG_CLASS_RSVD6 6 | |
193 | #define ESE_DZ_ETH_TAG_CLASS_RSVD5 5 | |
194 | #define ESE_DZ_ETH_TAG_CLASS_RSVD4 4 | |
195 | #define ESE_DZ_ETH_TAG_CLASS_RSVD3 3 | |
196 | #define ESE_DZ_ETH_TAG_CLASS_VLAN2 2 | |
197 | #define ESE_DZ_ETH_TAG_CLASS_VLAN1 1 | |
198 | #define ESE_DZ_ETH_TAG_CLASS_NONE 0 | |
199 | #define ESF_DZ_RX_ETH_BASE_CLASS_LBN 36 | |
200 | #define ESF_DZ_RX_ETH_BASE_CLASS_WIDTH 3 | |
201 | #define ESE_DZ_ETH_BASE_CLASS_LLC_SNAP 2 | |
202 | #define ESE_DZ_ETH_BASE_CLASS_LLC 1 | |
203 | #define ESE_DZ_ETH_BASE_CLASS_ETH2 0 | |
204 | #define ESF_DZ_RX_MAC_CLASS_LBN 35 | |
205 | #define ESF_DZ_RX_MAC_CLASS_WIDTH 1 | |
206 | #define ESE_DZ_MAC_CLASS_MCAST 1 | |
207 | #define ESE_DZ_MAC_CLASS_UCAST 0 | |
e17705c4 EC |
208 | #define ESF_DD_RX_EV_SOFT1_LBN 32 |
209 | #define ESF_DD_RX_EV_SOFT1_WIDTH 3 | |
210 | #define ESF_EZ_RX_EV_SOFT1_LBN 34 | |
211 | #define ESF_EZ_RX_EV_SOFT1_WIDTH 1 | |
212 | #define ESF_EZ_RX_ENCAP_HDR_LBN 32 | |
213 | #define ESF_EZ_RX_ENCAP_HDR_WIDTH 2 | |
214 | #define ESE_EZ_ENCAP_HDR_GRE 2 | |
215 | #define ESE_EZ_ENCAP_HDR_VXLAN 1 | |
216 | #define ESE_EZ_ENCAP_HDR_NONE 0 | |
217 | #define ESF_DD_RX_EV_RSVD1_LBN 30 | |
218 | #define ESF_DD_RX_EV_RSVD1_WIDTH 2 | |
219 | #define ESF_EZ_RX_EV_RSVD1_LBN 31 | |
220 | #define ESF_EZ_RX_EV_RSVD1_WIDTH 1 | |
221 | #define ESF_EZ_RX_ABORT_LBN 30 | |
222 | #define ESF_EZ_RX_ABORT_WIDTH 1 | |
9c517165 BH |
223 | #define ESF_DZ_RX_ECC_ERR_LBN 29 |
224 | #define ESF_DZ_RX_ECC_ERR_WIDTH 1 | |
d8d8ccf2 BK |
225 | #define ESF_DZ_RX_TRUNC_ERR_LBN 29 |
226 | #define ESF_DZ_RX_TRUNC_ERR_WIDTH 1 | |
9c517165 BH |
227 | #define ESF_DZ_RX_CRC1_ERR_LBN 28 |
228 | #define ESF_DZ_RX_CRC1_ERR_WIDTH 1 | |
229 | #define ESF_DZ_RX_CRC0_ERR_LBN 27 | |
230 | #define ESF_DZ_RX_CRC0_ERR_WIDTH 1 | |
231 | #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN 26 | |
232 | #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_WIDTH 1 | |
233 | #define ESF_DZ_RX_IPCKSUM_ERR_LBN 25 | |
234 | #define ESF_DZ_RX_IPCKSUM_ERR_WIDTH 1 | |
235 | #define ESF_DZ_RX_ECRC_ERR_LBN 24 | |
236 | #define ESF_DZ_RX_ECRC_ERR_WIDTH 1 | |
237 | #define ESF_DZ_RX_QLABEL_LBN 16 | |
238 | #define ESF_DZ_RX_QLABEL_WIDTH 5 | |
239 | #define ESF_DZ_RX_PARSE_INCOMPLETE_LBN 15 | |
240 | #define ESF_DZ_RX_PARSE_INCOMPLETE_WIDTH 1 | |
241 | #define ESF_DZ_RX_CONT_LBN 14 | |
242 | #define ESF_DZ_RX_CONT_WIDTH 1 | |
243 | #define ESF_DZ_RX_BYTES_LBN 0 | |
244 | #define ESF_DZ_RX_BYTES_WIDTH 14 | |
245 | ||
246 | /* RX_KER_DESC */ | |
247 | #define ESF_DZ_RX_KER_RESERVED_LBN 62 | |
248 | #define ESF_DZ_RX_KER_RESERVED_WIDTH 2 | |
249 | #define ESF_DZ_RX_KER_BYTE_CNT_LBN 48 | |
250 | #define ESF_DZ_RX_KER_BYTE_CNT_WIDTH 14 | |
251 | #define ESF_DZ_RX_KER_BUF_ADDR_LBN 0 | |
252 | #define ESF_DZ_RX_KER_BUF_ADDR_WIDTH 48 | |
253 | ||
9c517165 BH |
254 | /* TX_CSUM_TSTAMP_DESC */ |
255 | #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 | |
256 | #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 | |
257 | #define ESF_DZ_TX_OPTION_TYPE_LBN 60 | |
258 | #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 | |
259 | #define ESE_DZ_TX_OPTION_DESC_TSO 7 | |
260 | #define ESE_DZ_TX_OPTION_DESC_VLAN 6 | |
261 | #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 | |
e17705c4 EC |
262 | #define ESF_DZ_TX_OPTION_TS_AT_TXDP_LBN 8 |
263 | #define ESF_DZ_TX_OPTION_TS_AT_TXDP_WIDTH 1 | |
264 | #define ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM_LBN 7 | |
265 | #define ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM_WIDTH 1 | |
266 | #define ESF_DZ_TX_OPTION_INNER_IP_CSUM_LBN 6 | |
267 | #define ESF_DZ_TX_OPTION_INNER_IP_CSUM_WIDTH 1 | |
9c517165 BH |
268 | #define ESF_DZ_TX_TIMESTAMP_LBN 5 |
269 | #define ESF_DZ_TX_TIMESTAMP_WIDTH 1 | |
270 | #define ESF_DZ_TX_OPTION_CRC_MODE_LBN 2 | |
271 | #define ESF_DZ_TX_OPTION_CRC_MODE_WIDTH 3 | |
272 | #define ESE_DZ_TX_OPTION_CRC_FCOIP_MPA 5 | |
273 | #define ESE_DZ_TX_OPTION_CRC_FCOIP_FCOE 4 | |
274 | #define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR_AND_PYLD 3 | |
275 | #define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR 2 | |
276 | #define ESE_DZ_TX_OPTION_CRC_FCOE 1 | |
277 | #define ESE_DZ_TX_OPTION_CRC_OFF 0 | |
278 | #define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_LBN 1 | |
279 | #define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_WIDTH 1 | |
280 | #define ESF_DZ_TX_OPTION_IP_CSUM_LBN 0 | |
281 | #define ESF_DZ_TX_OPTION_IP_CSUM_WIDTH 1 | |
282 | ||
283 | /* TX_EVENT */ | |
284 | #define ESF_DZ_TX_CODE_LBN 60 | |
285 | #define ESF_DZ_TX_CODE_WIDTH 4 | |
286 | #define ESF_DZ_TX_OVERRIDE_HOLDOFF_LBN 59 | |
287 | #define ESF_DZ_TX_OVERRIDE_HOLDOFF_WIDTH 1 | |
288 | #define ESF_DZ_TX_DROP_EVENT_LBN 58 | |
289 | #define ESF_DZ_TX_DROP_EVENT_WIDTH 1 | |
e17705c4 EC |
290 | #define ESF_DD_TX_EV_RSVD_LBN 48 |
291 | #define ESF_DD_TX_EV_RSVD_WIDTH 10 | |
292 | #define ESF_EZ_TCP_UDP_INNER_CHKSUM_ERR_LBN 57 | |
293 | #define ESF_EZ_TCP_UDP_INNER_CHKSUM_ERR_WIDTH 1 | |
294 | #define ESF_EZ_IP_INNER_CHKSUM_ERR_LBN 56 | |
295 | #define ESF_EZ_IP_INNER_CHKSUM_ERR_WIDTH 1 | |
296 | #define ESF_EZ_TX_EV_RSVD_LBN 48 | |
297 | #define ESF_EZ_TX_EV_RSVD_WIDTH 8 | |
9c517165 BH |
298 | #define ESF_DZ_TX_SOFT2_LBN 32 |
299 | #define ESF_DZ_TX_SOFT2_WIDTH 16 | |
e17705c4 EC |
300 | #define ESF_DD_TX_SOFT1_LBN 24 |
301 | #define ESF_DD_TX_SOFT1_WIDTH 8 | |
302 | #define ESF_EZ_TX_CAN_MERGE_LBN 31 | |
303 | #define ESF_EZ_TX_CAN_MERGE_WIDTH 1 | |
304 | #define ESF_EZ_TX_SOFT1_LBN 24 | |
305 | #define ESF_EZ_TX_SOFT1_WIDTH 7 | |
9c517165 BH |
306 | #define ESF_DZ_TX_QLABEL_LBN 16 |
307 | #define ESF_DZ_TX_QLABEL_WIDTH 5 | |
308 | #define ESF_DZ_TX_DESCR_INDX_LBN 0 | |
309 | #define ESF_DZ_TX_DESCR_INDX_WIDTH 16 | |
310 | ||
311 | /* TX_KER_DESC */ | |
312 | #define ESF_DZ_TX_KER_TYPE_LBN 63 | |
313 | #define ESF_DZ_TX_KER_TYPE_WIDTH 1 | |
314 | #define ESF_DZ_TX_KER_CONT_LBN 62 | |
315 | #define ESF_DZ_TX_KER_CONT_WIDTH 1 | |
316 | #define ESF_DZ_TX_KER_BYTE_CNT_LBN 48 | |
317 | #define ESF_DZ_TX_KER_BYTE_CNT_WIDTH 14 | |
318 | #define ESF_DZ_TX_KER_BUF_ADDR_LBN 0 | |
319 | #define ESF_DZ_TX_KER_BUF_ADDR_WIDTH 48 | |
320 | ||
321 | /* TX_PIO_DESC */ | |
322 | #define ESF_DZ_TX_PIO_TYPE_LBN 63 | |
323 | #define ESF_DZ_TX_PIO_TYPE_WIDTH 1 | |
324 | #define ESF_DZ_TX_PIO_OPT_LBN 60 | |
325 | #define ESF_DZ_TX_PIO_OPT_WIDTH 3 | |
ee45fd92 | 326 | #define ESE_DZ_TX_OPTION_DESC_PIO 1 |
9c517165 BH |
327 | #define ESF_DZ_TX_PIO_CONT_LBN 59 |
328 | #define ESF_DZ_TX_PIO_CONT_WIDTH 1 | |
329 | #define ESF_DZ_TX_PIO_BYTE_CNT_LBN 32 | |
330 | #define ESF_DZ_TX_PIO_BYTE_CNT_WIDTH 12 | |
331 | #define ESF_DZ_TX_PIO_BUF_ADDR_LBN 0 | |
332 | #define ESF_DZ_TX_PIO_BUF_ADDR_WIDTH 12 | |
333 | ||
334 | /* TX_TSO_DESC */ | |
335 | #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 | |
336 | #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 | |
337 | #define ESF_DZ_TX_OPTION_TYPE_LBN 60 | |
338 | #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 | |
339 | #define ESE_DZ_TX_OPTION_DESC_TSO 7 | |
340 | #define ESE_DZ_TX_OPTION_DESC_VLAN 6 | |
341 | #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 | |
e17705c4 EC |
342 | #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 |
343 | #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 | |
d8d8ccf2 BK |
344 | #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3 |
345 | #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 | |
e17705c4 EC |
346 | #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 |
347 | #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 | |
9c517165 BH |
348 | #define ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48 |
349 | #define ESF_DZ_TX_TSO_TCP_FLAGS_WIDTH 8 | |
350 | #define ESF_DZ_TX_TSO_IP_ID_LBN 32 | |
351 | #define ESF_DZ_TX_TSO_IP_ID_WIDTH 16 | |
352 | #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 | |
353 | #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 | |
354 | ||
d8d8ccf2 | 355 | /* TX_TSO_V2_DESC_A */ |
e17705c4 EC |
356 | #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 |
357 | #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 | |
358 | #define ESF_DZ_TX_OPTION_TYPE_LBN 60 | |
359 | #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 | |
360 | #define ESE_DZ_TX_OPTION_DESC_TSO 7 | |
361 | #define ESE_DZ_TX_OPTION_DESC_VLAN 6 | |
362 | #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 | |
363 | #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 | |
364 | #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 | |
365 | #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3 | |
366 | #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 | |
367 | #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 | |
368 | #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 | |
369 | #define ESF_DZ_TX_TSO_IP_ID_LBN 32 | |
370 | #define ESF_DZ_TX_TSO_IP_ID_WIDTH 16 | |
371 | #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 | |
372 | #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 | |
373 | ||
d8d8ccf2 | 374 | /* TX_TSO_V2_DESC_B */ |
e17705c4 EC |
375 | #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 |
376 | #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 | |
377 | #define ESF_DZ_TX_OPTION_TYPE_LBN 60 | |
378 | #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 | |
379 | #define ESE_DZ_TX_OPTION_DESC_TSO 7 | |
380 | #define ESE_DZ_TX_OPTION_DESC_VLAN 6 | |
381 | #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 | |
382 | #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 | |
383 | #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 | |
384 | #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3 | |
385 | #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 | |
386 | #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 | |
387 | #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 | |
e17705c4 EC |
388 | #define ESF_DZ_TX_TSO_TCP_MSS_LBN 32 |
389 | #define ESF_DZ_TX_TSO_TCP_MSS_WIDTH 16 | |
d8d8ccf2 BK |
390 | #define ESF_DZ_TX_TSO_OUTER_IPID_LBN 0 |
391 | #define ESF_DZ_TX_TSO_OUTER_IPID_WIDTH 16 | |
e17705c4 | 392 | |
9c517165 BH |
393 | /*************************************************************************/ |
394 | ||
395 | /* TX_DESC_UPD_REG: Transmit descriptor update register. | |
396 | * We may write just one dword of these registers. | |
397 | */ | |
398 | #define ER_DZ_TX_DESC_UPD_DWORD (ER_DZ_TX_DESC_UPD + 2 * 4) | |
399 | #define ERF_DZ_TX_DESC_WPTR_DWORD_LBN (ERF_DZ_TX_DESC_WPTR_LBN - 2 * 32) | |
400 | #define ERF_DZ_TX_DESC_WPTR_DWORD_WIDTH ERF_DZ_TX_DESC_WPTR_WIDTH | |
401 | ||
402 | /* The workaround for bug 35388 requires multiplexing writes through | |
403 | * the TX_DESC_UPD_DWORD address. | |
404 | * TX_DESC_UPD: 0ppppppppppp (bit 11 lost) | |
405 | * EVQ_RPTR: 1000hhhhhhhh, 1001llllllll (split into high and low bits) | |
406 | * EVQ_TMR: 11mmvvvvvvvv (bits 8:13 of value lost) | |
407 | */ | |
408 | #define ER_DD_EVQ_INDIRECT ER_DZ_TX_DESC_UPD_DWORD | |
409 | #define ERF_DD_EVQ_IND_RPTR_FLAGS_LBN 8 | |
410 | #define ERF_DD_EVQ_IND_RPTR_FLAGS_WIDTH 4 | |
411 | #define EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH 8 | |
412 | #define EFE_DD_EVQ_IND_RPTR_FLAGS_LOW 9 | |
413 | #define ERF_DD_EVQ_IND_RPTR_LBN 0 | |
414 | #define ERF_DD_EVQ_IND_RPTR_WIDTH 8 | |
415 | #define ERF_DD_EVQ_IND_TIMER_FLAGS_LBN 10 | |
416 | #define ERF_DD_EVQ_IND_TIMER_FLAGS_WIDTH 2 | |
417 | #define EFE_DD_EVQ_IND_TIMER_FLAGS 3 | |
418 | #define ERF_DD_EVQ_IND_TIMER_MODE_LBN 8 | |
419 | #define ERF_DD_EVQ_IND_TIMER_MODE_WIDTH 2 | |
420 | #define ERF_DD_EVQ_IND_TIMER_VAL_LBN 0 | |
421 | #define ERF_DD_EVQ_IND_TIMER_VAL_WIDTH 8 | |
422 | ||
423 | /* TX_PIOBUF | |
424 | * PIO buffer aperture (paged) | |
425 | */ | |
426 | #define ER_DZ_TX_PIOBUF 4096 | |
427 | #define ER_DZ_TX_PIOBUF_SIZE 2048 | |
428 | ||
429 | /* RX packet prefix */ | |
430 | #define ES_DZ_RX_PREFIX_HASH_OFST 0 | |
431 | #define ES_DZ_RX_PREFIX_VLAN1_OFST 4 | |
432 | #define ES_DZ_RX_PREFIX_VLAN2_OFST 6 | |
433 | #define ES_DZ_RX_PREFIX_PKTLEN_OFST 8 | |
434 | #define ES_DZ_RX_PREFIX_TSTAMP_OFST 10 | |
435 | #define ES_DZ_RX_PREFIX_SIZE 14 | |
436 | ||
437 | #endif /* EFX_EF10_REGS_H */ |