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sfc_ef100: TX path for EF100 NICs
[linux-block.git] / drivers / net / ethernet / sfc / ef100_nic.c
CommitLineData
51b35a45
EC		 1// SPDX-License-Identifier: GPL-2.0-only
2/****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation, incorporated herein by reference.
10 */
11
12#include "ef100_nic.h"
13#include "efx_common.h"
14#include "efx_channels.h"
15#include "io.h"
16#include "selftest.h"
17#include "ef100_regs.h"
18#include "mcdi.h"
19#include "mcdi_pcol.h"
20#include "mcdi_port_common.h"
21#include "mcdi_functions.h"
22#include "mcdi_filters.h"
23#include "ef100_rx.h"
24#include "ef100_tx.h"
25#include "ef100_netdev.h"
26
27#define EF100_MAX_VIS 4096
2200e6d9
EC		 28#define EF100_NUM_MCDI_BUFFERS 1
29#define MCDI_BUF_LEN (8 + MCDI_CTL_SDU_LEN_MAX)
51b35a45 30
c027f2a7
EC		 31#define EF100_RESET_PORT ((ETH_RESET_MAC | ETH_RESET_PHY) << ETH_RESET_SHARED_SHIFT)
32
51b35a45
EC		 33/* MCDI
34 */
2200e6d9
EC		 35static u8 *ef100_mcdi_buf(struct efx_nic *efx, u8 bufid, dma_addr_t *dma_addr)
36{
37 struct ef100_nic_data *nic_data = efx->nic_data;
38
39 if (dma_addr)
40 *dma_addr = nic_data->mcdi_buf.dma_addr +
41 bufid * ALIGN(MCDI_BUF_LEN, 256);
42 return nic_data->mcdi_buf.addr + bufid * ALIGN(MCDI_BUF_LEN, 256);
43}
44
51b35a45
EC		 45static int ef100_get_warm_boot_count(struct efx_nic *efx)
46{
47 efx_dword_t reg;
48
49 efx_readd(efx, &reg, efx_reg(efx, ER_GZ_MC_SFT_STATUS));
50
51 if (EFX_DWORD_FIELD(reg, EFX_DWORD_0) == 0xffffffff) {
52 netif_err(efx, hw, efx->net_dev, "Hardware unavailable\n");
53 efx->state = STATE_DISABLED;
54 return -ENETDOWN;
55 } else {
56 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
57 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
58 }
59}
60
2200e6d9
EC		 61static void ef100_mcdi_request(struct efx_nic *efx,
62 const efx_dword_t *hdr, size_t hdr_len,
63 const efx_dword_t *sdu, size_t sdu_len)
64{
65 dma_addr_t dma_addr;
66 u8 *pdu = ef100_mcdi_buf(efx, 0, &dma_addr);
67
68 memcpy(pdu, hdr, hdr_len);
69 memcpy(pdu + hdr_len, sdu, sdu_len);
70 wmb();
71
72 /* The hardware provides 'low' and 'high' (doorbell) registers
73 * for passing the 64-bit address of an MCDI request to
74 * firmware. However the dwords are swapped by firmware. The
75 * least significant bits of the doorbell are then 0 for all
76 * MCDI requests due to alignment.
77 */
78 _efx_writed(efx, cpu_to_le32((u64)dma_addr >> 32), efx_reg(efx, ER_GZ_MC_DB_LWRD));
79 _efx_writed(efx, cpu_to_le32((u32)dma_addr), efx_reg(efx, ER_GZ_MC_DB_HWRD));
80}
81
82static bool ef100_mcdi_poll_response(struct efx_nic *efx)
83{
84 const efx_dword_t hdr =
85 *(const efx_dword_t *)(ef100_mcdi_buf(efx, 0, NULL));
86
87 rmb();
88 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
89}
90
91static void ef100_mcdi_read_response(struct efx_nic *efx,
92 efx_dword_t *outbuf, size_t offset,
93 size_t outlen)
94{
95 const u8 *pdu = ef100_mcdi_buf(efx, 0, NULL);
96
97 memcpy(outbuf, pdu + offset, outlen);
98}
99
100static int ef100_mcdi_poll_reboot(struct efx_nic *efx)
101{
102 struct ef100_nic_data *nic_data = efx->nic_data;
103 int rc;
104
105 rc = ef100_get_warm_boot_count(efx);
106 if (rc < 0) {
107 /* The firmware is presumably in the process of
108 * rebooting. However, we are supposed to report each
109 * reboot just once, so we must only do that once we
110 * can read and store the updated warm boot count.
111 */
112 return 0;
113 }
114
115 if (rc == nic_data->warm_boot_count)
116 return 0;
117
118 nic_data->warm_boot_count = rc;
119
120 return -EIO;
121}
122
123static void ef100_mcdi_reboot_detected(struct efx_nic *efx)
124{
125}
126
f6573120
EC		 127/* MCDI calls
128 */
29ec1b27
EC		 129static int ef100_get_mac_address(struct efx_nic *efx, u8 *mac_address)
130{
131 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
132 size_t outlen;
133 int rc;
134
135 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
136
137 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
138 outbuf, sizeof(outbuf), &outlen);
139 if (rc)
140 return rc;
141 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
142 return -EIO;
143
144 ether_addr_copy(mac_address,
145 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
146 return 0;
147}
148
f6573120
EC		 149static int efx_ef100_init_datapath_caps(struct efx_nic *efx)
150{
d802b0ae 151 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V7_OUT_LEN);
f6573120
EC		 152 struct ef100_nic_data *nic_data = efx->nic_data;
153 u8 vi_window_mode;
154 size_t outlen;
155 int rc;
156
157 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
158
159 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
160 outbuf, sizeof(outbuf), &outlen);
161 if (rc)
162 return rc;
163 if (outlen < MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
164 netif_err(efx, drv, efx->net_dev,
165 "unable to read datapath firmware capabilities\n");
166 return -EIO;
167 }
168
169 nic_data->datapath_caps = MCDI_DWORD(outbuf,
170 GET_CAPABILITIES_OUT_FLAGS1);
171 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
172 GET_CAPABILITIES_V2_OUT_FLAGS2);
d802b0ae
EC		 173 if (outlen < MC_CMD_GET_CAPABILITIES_V7_OUT_LEN)
174 nic_data->datapath_caps3 = 0;
175 else
176 nic_data->datapath_caps3 = MCDI_DWORD(outbuf,
177 GET_CAPABILITIES_V7_OUT_FLAGS3);
f6573120
EC		 178
179 vi_window_mode = MCDI_BYTE(outbuf,
180 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
181 rc = efx_mcdi_window_mode_to_stride(efx, vi_window_mode);
182 if (rc)
183 return rc;
184
185 if (efx_ef100_has_cap(nic_data->datapath_caps2, TX_TSO_V3))
186 efx->net_dev->features |= NETIF_F_TSO | NETIF_F_TSO6;
187 efx->num_mac_stats = MCDI_WORD(outbuf,
188 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
189 netif_dbg(efx, probe, efx->net_dev,
190 "firmware reports num_mac_stats = %u\n",
191 efx->num_mac_stats);
192 return 0;
193}
194
51b35a45
EC		 195/* Event handling
196 */
197static int ef100_ev_probe(struct efx_channel *channel)
198{
199 /* Allocate an extra descriptor for the QMDA status completion entry */
200 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
201 (channel->eventq_mask + 2) *
202 sizeof(efx_qword_t),
203 GFP_KERNEL);
204}
205
965b549f
EC		 206static int ef100_ev_init(struct efx_channel *channel)
207{
208 struct ef100_nic_data *nic_data = channel->efx->nic_data;
209
210 /* initial phase is 0 */
211 clear_bit(channel->channel, nic_data->evq_phases);
212
213 return efx_mcdi_ev_init(channel, false, false);
214}
215
216static void ef100_ev_read_ack(struct efx_channel *channel)
217{
218 efx_dword_t evq_prime;
219
220 EFX_POPULATE_DWORD_2(evq_prime,
221 ERF_GZ_EVQ_ID, channel->channel,
222 ERF_GZ_IDX, channel->eventq_read_ptr &
223 channel->eventq_mask);
224
225 efx_writed(channel->efx, &evq_prime,
226 efx_reg(channel->efx, ER_GZ_EVQ_INT_PRIME));
227}
228
229static int ef100_ev_process(struct efx_channel *channel, int quota)
230{
5e4ef673
EC		 231 struct efx_nic *efx = channel->efx;
232 struct ef100_nic_data *nic_data;
233 bool evq_phase, old_evq_phase;
234 unsigned int read_ptr;
235 efx_qword_t *p_event;
236 int spent = 0;
237 bool ev_phase;
238 int ev_type;
239
240 if (unlikely(!channel->enabled))
241 return 0;
242
243 nic_data = efx->nic_data;
244 evq_phase = test_bit(channel->channel, nic_data->evq_phases);
245 old_evq_phase = evq_phase;
246 read_ptr = channel->eventq_read_ptr;
247 BUILD_BUG_ON(ESF_GZ_EV_RXPKTS_PHASE_LBN != ESF_GZ_EV_TXCMPL_PHASE_LBN);
248
249 while (spent < quota) {
250 p_event = efx_event(channel, read_ptr);
251
252 ev_phase = !!EFX_QWORD_FIELD(*p_event, ESF_GZ_EV_RXPKTS_PHASE);
253 if (ev_phase != evq_phase)
254 break;
255
256 netif_vdbg(efx, drv, efx->net_dev,
257 "processing event on %d " EFX_QWORD_FMT "\n",
258 channel->channel, EFX_QWORD_VAL(*p_event));
259
260 ev_type = EFX_QWORD_FIELD(*p_event, ESF_GZ_E_TYPE);
261
262 switch (ev_type) {
263 case ESE_GZ_EF100_EV_MCDI:
264 efx_mcdi_process_event(channel, p_event);
265 break;
d19a5372
EC		 266 case ESE_GZ_EF100_EV_TX_COMPLETION:
267 ef100_ev_tx(channel, p_event);
268 break;
5e4ef673
EC		 269 case ESE_GZ_EF100_EV_DRIVER:
270 netif_info(efx, drv, efx->net_dev,
271 "Driver initiated event " EFX_QWORD_FMT "\n",
272 EFX_QWORD_VAL(*p_event));
273 break;
274 default:
275 netif_info(efx, drv, efx->net_dev,
276 "Unhandled event " EFX_QWORD_FMT "\n",
277 EFX_QWORD_VAL(*p_event));
278 }
279
280 ++read_ptr;
281 if ((read_ptr & channel->eventq_mask) == 0)
282 evq_phase = !evq_phase;
283 }
284
285 channel->eventq_read_ptr = read_ptr;
286 if (evq_phase != old_evq_phase)
287 change_bit(channel->channel, nic_data->evq_phases);
288
289 return spent;
965b549f
EC		 290}
291
51b35a45
EC		 292static irqreturn_t ef100_msi_interrupt(int irq, void *dev_id)
293{
294 struct efx_msi_context *context = dev_id;
295 struct efx_nic *efx = context->efx;
296
297 netif_vdbg(efx, intr, efx->net_dev,
298 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
299
300 if (likely(READ_ONCE(efx->irq_soft_enabled))) {
301 /* Note test interrupts */
302 if (context->index == efx->irq_level)
303 efx->last_irq_cpu = raw_smp_processor_id();
304
305 /* Schedule processing of the channel */
306 efx_schedule_channel_irq(efx->channel[context->index]);
307 }
308
309 return IRQ_HANDLED;
310}
311
aa86a75f
EC		 312static int ef100_phy_probe(struct efx_nic *efx)
313{
99a23c11
EC		 314 struct efx_mcdi_phy_data *phy_data;
315 int rc;
316
317 /* Probe for the PHY */
aa86a75f
EC		 318 efx->phy_data = kzalloc(sizeof(struct efx_mcdi_phy_data), GFP_KERNEL);
319 if (!efx->phy_data)
320 return -ENOMEM;
321
99a23c11
EC		 322 rc = efx_mcdi_get_phy_cfg(efx, efx->phy_data);
323 if (rc)
324 return rc;
325
326 /* Populate driver and ethtool settings */
327 phy_data = efx->phy_data;
328 mcdi_to_ethtool_linkset(phy_data->media, phy_data->supported_cap,
329 efx->link_advertising);
330 efx->fec_config = mcdi_fec_caps_to_ethtool(phy_data->supported_cap,
331 false);
332
333 /* Default to Autonegotiated flow control if the PHY supports it */
334 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
335 if (phy_data->supported_cap & (1 << MC_CMD_PHY_CAP_AN_LBN))
336 efx->wanted_fc |= EFX_FC_AUTO;
337 efx_link_set_wanted_fc(efx, efx->wanted_fc);
338
339 /* Push settings to the PHY. Failure is not fatal, the user can try to
340 * fix it using ethtool.
341 */
342 rc = efx_mcdi_port_reconfigure(efx);
343 if (rc && rc != -EPERM)
344 netif_warn(efx, drv, efx->net_dev,
345 "could not initialise PHY settings\n");
346
aa86a75f
EC		 347 return 0;
348}
349
c027f2a7
EC		 350/* Other
351 */
99a23c11
EC		 352static int ef100_reconfigure_mac(struct efx_nic *efx, bool mtu_only)
353{
354 WARN_ON(!mutex_is_locked(&efx->mac_lock));
355
356 efx_mcdi_filter_sync_rx_mode(efx);
357
358 if (mtu_only && efx_has_cap(efx, SET_MAC_ENHANCED))
359 return efx_mcdi_set_mtu(efx);
360 return efx_mcdi_set_mac(efx);
361}
c027f2a7
EC		 362
363static enum reset_type ef100_map_reset_reason(enum reset_type reason)
364{
365 if (reason == RESET_TYPE_TX_WATCHDOG)
366 return reason;
367 return RESET_TYPE_DISABLE;
368}
369
370static int ef100_map_reset_flags(u32 *flags)
371{
372 /* Only perform a RESET_TYPE_ALL because we don't support MC_REBOOTs */
373 if ((*flags & EF100_RESET_PORT)) {
374 *flags &= ~EF100_RESET_PORT;
375 return RESET_TYPE_ALL;
376 }
377 if (*flags & ETH_RESET_MGMT) {
378 *flags &= ~ETH_RESET_MGMT;
379 return RESET_TYPE_DISABLE;
380 }
381
382 return -EINVAL;
383}
384
385static int ef100_reset(struct efx_nic *efx, enum reset_type reset_type)
386{
387 int rc;
388
389 dev_close(efx->net_dev);
390
391 if (reset_type == RESET_TYPE_TX_WATCHDOG) {
392 netif_device_attach(efx->net_dev);
393 __clear_bit(reset_type, &efx->reset_pending);
394 rc = dev_open(efx->net_dev, NULL);
395 } else if (reset_type == RESET_TYPE_ALL) {
4e5675bb
EC		 396 rc = efx_mcdi_reset(efx, reset_type);
397 if (rc)
398 return rc;
399
c027f2a7
EC		 400 netif_device_attach(efx->net_dev);
401
402 rc = dev_open(efx->net_dev, NULL);
403 } else {
404 rc = 1; /* Leave the device closed */
405 }
406 return rc;
407}
408
1c748843
EC		 409static int efx_ef100_get_phys_port_id(struct efx_nic *efx,
410 struct netdev_phys_item_id *ppid)
411{
412 struct ef100_nic_data *nic_data = efx->nic_data;
413
414 if (!is_valid_ether_addr(nic_data->port_id))
415 return -EOPNOTSUPP;
416
417 ppid->id_len = ETH_ALEN;
418 memcpy(ppid->id, nic_data->port_id, ppid->id_len);
419
420 return 0;
421}
422
965b549f
EC		 423static unsigned int ef100_check_caps(const struct efx_nic *efx,
424 u8 flag, u32 offset)
425{
f6573120
EC		 426 const struct ef100_nic_data *nic_data = efx->nic_data;
427
428 switch (offset) {
429 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_OFST:
430 return nic_data->datapath_caps & BIT_ULL(flag);
431 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_OFST:
432 return nic_data->datapath_caps2 & BIT_ULL(flag);
d802b0ae
EC		 433 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_OFST:
434 return nic_data->datapath_caps3 & BIT_ULL(flag);
f6573120
EC		 435 default:
436 return 0;
437 }
965b549f
EC		 438}
439
51b35a45
EC		 440/* NIC level access functions
441 */
d19a5372
EC		 442#define EF100_OFFLOAD_FEATURES (NETIF_F_HW_CSUM | \
443 NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_FRAGLIST | \
444 NETIF_F_TSO_ECN | NETIF_F_TSO_MANGLEID | NETIF_F_HW_VLAN_CTAG_TX)
445
51b35a45
EC		 446const struct efx_nic_type ef100_pf_nic_type = {
447 .revision = EFX_REV_EF100,
448 .is_vf = false,
449 .probe = ef100_probe_pf,
d19a5372 450 .offload_features = EF100_OFFLOAD_FEATURES,
51b35a45 451 .mcdi_max_ver = 2,
2200e6d9
EC		 452 .mcdi_request = ef100_mcdi_request,
453 .mcdi_poll_response = ef100_mcdi_poll_response,
454 .mcdi_read_response = ef100_mcdi_read_response,
455 .mcdi_poll_reboot = ef100_mcdi_poll_reboot,
456 .mcdi_reboot_detected = ef100_mcdi_reboot_detected,
51b35a45
EC		 457 .irq_enable_master = efx_port_dummy_op_void,
458 .irq_disable_non_ev = efx_port_dummy_op_void,
459 .push_irq_moderation = efx_channel_dummy_op_void,
460 .min_interrupt_mode = EFX_INT_MODE_MSIX,
c027f2a7
EC		 461 .map_reset_reason = ef100_map_reset_reason,
462 .map_reset_flags = ef100_map_reset_flags,
463 .reset = ef100_reset,
51b35a45 464
965b549f
EC		 465 .check_caps = ef100_check_caps,
466
51b35a45 467 .ev_probe = ef100_ev_probe,
965b549f
EC		 468 .ev_init = ef100_ev_init,
469 .ev_fini = efx_mcdi_ev_fini,
470 .ev_remove = efx_mcdi_ev_remove,
51b35a45 471 .irq_handle_msi = ef100_msi_interrupt,
965b549f
EC		 472 .ev_process = ef100_ev_process,
473 .ev_read_ack = ef100_ev_read_ack,
474 .tx_probe = ef100_tx_probe,
475 .tx_init = ef100_tx_init,
476 .tx_write = ef100_tx_write,
477 .tx_enqueue = ef100_enqueue_skb,
478 .rx_probe = efx_mcdi_rx_probe,
479 .rx_init = efx_mcdi_rx_init,
480 .rx_remove = efx_mcdi_rx_remove,
481 .rx_write = ef100_rx_write,
482 .rx_packet = __ef100_rx_packet,
51b35a45 483
1c748843
EC		 484 .get_phys_port_id = efx_ef100_get_phys_port_id,
485
99a23c11
EC		 486 .reconfigure_mac = ef100_reconfigure_mac,
487
51b35a45
EC		 488 /* Per-type bar/size configuration not used on ef100. Location of
489 * registers is defined by extended capabilities.
490 */
491 .mem_bar = NULL,
492 .mem_map_size = NULL,
493
494};
495
8e737145
EC		 496static int compare_versions(const char *a, const char *b)
497{
498 int a_major, a_minor, a_point, a_patch;
499 int b_major, b_minor, b_point, b_patch;
500 int a_matched, b_matched;
501
502 a_matched = sscanf(a, "%d.%d.%d.%d", &a_major, &a_minor, &a_point, &a_patch);
503 b_matched = sscanf(b, "%d.%d.%d.%d", &b_major, &b_minor, &b_point, &b_patch);
504
505 if (a_matched == 4 && b_matched != 4)
506 return +1;
507
508 if (a_matched != 4 && b_matched == 4)
509 return -1;
510
511 if (a_matched != 4 && b_matched != 4)
512 return 0;
513
514 if (a_major != b_major)
515 return a_major - b_major;
516
517 if (a_minor != b_minor)
518 return a_minor - b_minor;
519
520 if (a_point != b_point)
521 return a_point - b_point;
522
523 return a_patch - b_patch;
524}
525
adcfc348
EC		 526enum ef100_tlv_state_machine {
527 EF100_TLV_TYPE,
528 EF100_TLV_TYPE_CONT,
529 EF100_TLV_LENGTH,
530 EF100_TLV_VALUE
531};
532
533struct ef100_tlv_state {
534 enum ef100_tlv_state_machine state;
535 u64 value;
536 u32 value_offset;
537 u16 type;
538 u8 len;
539};
540
541static int ef100_tlv_feed(struct ef100_tlv_state *state, u8 byte)
542{
543 switch (state->state) {
544 case EF100_TLV_TYPE:
545 state->type = byte & 0x7f;
546 state->state = (byte & 0x80) ? EF100_TLV_TYPE_CONT
547 : EF100_TLV_LENGTH;
548 /* Clear ready to read in a new entry */
549 state->value = 0;
550 state->value_offset = 0;
551 return 0;
552 case EF100_TLV_TYPE_CONT:
553 state->type |= byte << 7;
554 state->state = EF100_TLV_LENGTH;
555 return 0;
556 case EF100_TLV_LENGTH:
557 state->len = byte;
558 /* We only handle TLVs that fit in a u64 */
559 if (state->len > sizeof(state->value))
560 return -EOPNOTSUPP;
561 /* len may be zero, implying a value of zero */
562 state->state = state->len ? EF100_TLV_VALUE : EF100_TLV_TYPE;
563 return 0;
564 case EF100_TLV_VALUE:
565 state->value |= ((u64)byte) << (state->value_offset * 8);
566 state->value_offset++;
567 if (state->value_offset >= state->len)
568 state->state = EF100_TLV_TYPE;
569 return 0;
570 default: /* state machine error, can't happen */
571 WARN_ON_ONCE(1);
572 return -EIO;
573 }
574}
575
576static int ef100_process_design_param(struct efx_nic *efx,
577 const struct ef100_tlv_state *reader)
578{
579 struct ef100_nic_data *nic_data = efx->nic_data;
580
581 switch (reader->type) {
582 case ESE_EF100_DP_GZ_PAD: /* padding, skip it */
583 return 0;
584 case ESE_EF100_DP_GZ_PARTIAL_TSTAMP_SUB_NANO_BITS:
585 /* Driver doesn't support timestamping yet, so we don't care */
586 return 0;
587 case ESE_EF100_DP_GZ_EVQ_UNSOL_CREDIT_SEQ_BITS:
588 /* Driver doesn't support unsolicited-event credits yet, so
589 * we don't care
590 */
591 return 0;
592 case ESE_EF100_DP_GZ_NMMU_GROUP_SIZE:
593 /* Driver doesn't manage the NMMU (so we don't care) */
594 return 0;
595 case ESE_EF100_DP_GZ_RX_L4_CSUM_PROTOCOLS:
596 /* Driver uses CHECKSUM_COMPLETE, so we don't care about
597 * protocol checksum validation
598 */
599 return 0;
600 case ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN:
601 nic_data->tso_max_hdr_len = min_t(u64, reader->value, 0xffff);
602 return 0;
603 case ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS:
604 /* We always put HDR_NUM_SEGS=1 in our TSO descriptors */
605 if (!reader->value) {
606 netif_err(efx, probe, efx->net_dev,
607 "TSO_MAX_HDR_NUM_SEGS < 1\n");
608 return -EOPNOTSUPP;
609 }
610 return 0;
611 case ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY:
612 case ESE_EF100_DP_GZ_TXQ_SIZE_GRANULARITY:
613 /* Our TXQ and RXQ sizes are always power-of-two and thus divisible by
614 * EFX_MIN_DMAQ_SIZE, so we just need to check that
615 * EFX_MIN_DMAQ_SIZE is divisible by GRANULARITY.
616 * This is very unlikely to fail.
617 */
618 if (EFX_MIN_DMAQ_SIZE % reader->value) {
619 netif_err(efx, probe, efx->net_dev,
620 "%s size granularity is %llu, can't guarantee safety\n",
621 reader->type == ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY ? "RXQ" : "TXQ",
622 reader->value);
623 return -EOPNOTSUPP;
624 }
625 return 0;
626 case ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN:
627 nic_data->tso_max_payload_len = min_t(u64, reader->value, GSO_MAX_SIZE);
628 efx->net_dev->gso_max_size = nic_data->tso_max_payload_len;
629 return 0;
630 case ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS:
631 nic_data->tso_max_payload_num_segs = min_t(u64, reader->value, 0xffff);
632 efx->net_dev->gso_max_segs = nic_data->tso_max_payload_num_segs;
633 return 0;
634 case ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES:
635 nic_data->tso_max_frames = min_t(u64, reader->value, 0xffff);
636 return 0;
637 case ESE_EF100_DP_GZ_COMPAT:
638 if (reader->value) {
639 netif_err(efx, probe, efx->net_dev,
640 "DP_COMPAT has unknown bits %#llx, driver not compatible with this hw\n",
641 reader->value);
642 return -EOPNOTSUPP;
643 }
644 return 0;
645 case ESE_EF100_DP_GZ_MEM2MEM_MAX_LEN:
646 /* Driver doesn't use mem2mem transfers */
647 return 0;
648 case ESE_EF100_DP_GZ_EVQ_TIMER_TICK_NANOS:
649 /* Driver doesn't currently use EVQ_TIMER */
650 return 0;
651 case ESE_EF100_DP_GZ_NMMU_PAGE_SIZES:
652 /* Driver doesn't manage the NMMU (so we don't care) */
653 return 0;
654 case ESE_EF100_DP_GZ_VI_STRIDES:
655 /* We never try to set the VI stride, and we don't rely on
656 * being able to find VIs past VI 0 until after we've learned
657 * the current stride from MC_CMD_GET_CAPABILITIES.
658 * So the value of this shouldn't matter.
659 */
660 if (reader->value != ESE_EF100_DP_GZ_VI_STRIDES_DEFAULT)
661 netif_dbg(efx, probe, efx->net_dev,
662 "NIC has other than default VI_STRIDES (mask "
663 "%#llx), early probing might use wrong one\n",
664 reader->value);
665 return 0;
666 case ESE_EF100_DP_GZ_RX_MAX_RUNT:
667 /* Driver doesn't look at L2_STATUS:LEN_ERR bit, so we don't
668 * care whether it indicates runt or overlength for any given
669 * packet, so we don't care about this parameter.
670 */
671 return 0;
672 default:
673 /* Host interface says "Drivers should ignore design parameters
674 * that they do not recognise."
675 */
676 netif_dbg(efx, probe, efx->net_dev,
677 "Ignoring unrecognised design parameter %u\n",
678 reader->type);
679 return 0;
680 }
681}
682
683static int ef100_check_design_params(struct efx_nic *efx)
684{
685 struct ef100_tlv_state reader = {};
686 u32 total_len, offset = 0;
687 efx_dword_t reg;
688 int rc = 0, i;
689 u32 data;
690
691 efx_readd(efx, &reg, ER_GZ_PARAMS_TLV_LEN);
692 total_len = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
693 netif_dbg(efx, probe, efx->net_dev, "%u bytes of design parameters\n",
694 total_len);
695 while (offset < total_len) {
696 efx_readd(efx, &reg, ER_GZ_PARAMS_TLV + offset);
697 data = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
698 for (i = 0; i < sizeof(data); i++) {
699 rc = ef100_tlv_feed(&reader, data);
700 /* Got a complete value? */
701 if (!rc && reader.state == EF100_TLV_TYPE)
702 rc = ef100_process_design_param(efx, &reader);
703 if (rc)
704 goto out;
705 data >>= 8;
706 offset++;
707 }
708 }
709 /* Check we didn't end halfway through a TLV entry, which could either
710 * mean that the TLV stream is truncated or just that it's corrupted
711 * and our state machine is out of sync.
712 */
713 if (reader.state != EF100_TLV_TYPE) {
714 if (reader.state == EF100_TLV_TYPE_CONT)
715 netif_err(efx, probe, efx->net_dev,
716 "truncated design parameter (incomplete type %u)\n",
717 reader.type);
718 else
719 netif_err(efx, probe, efx->net_dev,
720 "truncated design parameter %u\n",
721 reader.type);
722 rc = -EIO;
723 }
724out:
725 return rc;
726}
727
51b35a45
EC		 728/* NIC probe and remove
729 */
730static int ef100_probe_main(struct efx_nic *efx)
731{
732 unsigned int bar_size = resource_size(&efx->pci_dev->resource[efx->mem_bar]);
733 struct net_device *net_dev = efx->net_dev;
734 struct ef100_nic_data *nic_data;
8e737145 735 char fw_version[32];
51b35a45
EC		 736 int i, rc;
737
738 if (WARN_ON(bar_size == 0))
739 return -EIO;
740
741 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
742 if (!nic_data)
743 return -ENOMEM;
744 efx->nic_data = nic_data;
745 nic_data->efx = efx;
746 net_dev->features |= efx->type->offload_features;
747 net_dev->hw_features |= efx->type->offload_features;
748
adcfc348
EC		 749 /* Populate design-parameter defaults */
750 nic_data->tso_max_hdr_len = ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN_DEFAULT;
751 nic_data->tso_max_frames = ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES_DEFAULT;
752 nic_data->tso_max_payload_num_segs = ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS_DEFAULT;
753 nic_data->tso_max_payload_len = ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN_DEFAULT;
754 net_dev->gso_max_segs = ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS_DEFAULT;
755 /* Read design parameters */
756 rc = ef100_check_design_params(efx);
757 if (rc) {
758 netif_err(efx, probe, efx->net_dev,
759 "Unsupported design parameters\n");
760 goto fail;
761 }
762
2200e6d9
EC		 763 /* we assume later that we can copy from this buffer in dwords */
764 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
765
766 /* MCDI buffers must be 256 byte aligned. */
767 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, MCDI_BUF_LEN,
768 GFP_KERNEL);
769 if (rc)
770 goto fail;
771
51b35a45
EC		 772 /* Get the MC's warm boot count. In case it's rebooting right
773 * now, be prepared to retry.
774 */
775 i = 0;
776 for (;;) {
777 rc = ef100_get_warm_boot_count(efx);
778 if (rc >= 0)
779 break;
780 if (++i == 5)
781 goto fail;
782 ssleep(1);
783 }
784 nic_data->warm_boot_count = rc;
785
786 /* In case we're recovering from a crash (kexec), we want to
787 * cancel any outstanding request by the previous user of this
788 * function. We send a special message using the least
789 * significant bits of the 'high' (doorbell) register.
790 */
791 _efx_writed(efx, cpu_to_le32(1), efx_reg(efx, ER_GZ_MC_DB_HWRD));
792
793 /* Post-IO section. */
794
2200e6d9
EC		 795 rc = efx_mcdi_init(efx);
796 if (!rc && efx->mcdi->fn_flags &
797 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT)) {
798 netif_info(efx, probe, efx->net_dev,
799 "No network port on this PCI function");
800 rc = -ENODEV;
801 }
802 if (rc)
803 goto fail;
4e5675bb
EC		 804 /* Reset (most) configuration for this function */
805 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
806 if (rc)
807 goto fail;
808
f6573120
EC		 809 rc = efx_ef100_init_datapath_caps(efx);
810 if (rc < 0)
811 goto fail;
2200e6d9 812
51b35a45
EC		 813 efx->max_vis = EF100_MAX_VIS;
814
1c748843
EC		 815 rc = efx_mcdi_port_get_number(efx);
816 if (rc < 0)
817 goto fail;
818 efx->port_num = rc;
819
8e737145
EC		 820 efx_mcdi_print_fwver(efx, fw_version, sizeof(fw_version));
821 netif_dbg(efx, drv, efx->net_dev, "Firmware version %s\n", fw_version);
822
823 if (compare_versions(fw_version, "1.1.0.1000") < 0) {
824 netif_info(efx, drv, efx->net_dev, "Firmware uses old event descriptors\n");
825 rc = -EINVAL;
4496363b
EC		 826 goto fail;
827 }
828
829 if (efx_has_cap(efx, UNSOL_EV_CREDIT_SUPPORTED)) {
830 netif_info(efx, drv, efx->net_dev, "Firmware uses unsolicited-event credits\n");
831 rc = -EINVAL;
8e737145
EC		 832 goto fail;
833 }
834
aa86a75f
EC		 835 rc = ef100_phy_probe(efx);
836 if (rc)
837 goto fail;
838
51b35a45
EC		 839 rc = efx_init_channels(efx);
840 if (rc)
841 goto fail;
842
843 rc = ef100_register_netdev(efx);
844 if (rc)
845 goto fail;
846
847 return 0;
848fail:
849 return rc;
850}
851
852int ef100_probe_pf(struct efx_nic *efx)
853{
29ec1b27
EC		 854 struct net_device *net_dev = efx->net_dev;
855 struct ef100_nic_data *nic_data;
856 int rc = ef100_probe_main(efx);
857
858 if (rc)
859 goto fail;
860
861 nic_data = efx->nic_data;
862 rc = ef100_get_mac_address(efx, net_dev->perm_addr);
863 if (rc)
864 goto fail;
865 /* Assign MAC address */
866 memcpy(net_dev->dev_addr, net_dev->perm_addr, ETH_ALEN);
867 memcpy(nic_data->port_id, net_dev->perm_addr, ETH_ALEN);
868
869 return 0;
870
871fail:
872 return rc;
51b35a45
EC		 873}
874
875void ef100_remove(struct efx_nic *efx)
876{
877 struct ef100_nic_data *nic_data = efx->nic_data;
878
879 ef100_unregister_netdev(efx);
880 efx_fini_channels(efx);
881 kfree(efx->phy_data);
882 efx->phy_data = NULL;
2200e6d9
EC		 883 efx_mcdi_detach(efx);
884 efx_mcdi_fini(efx);
885 if (nic_data)
886 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
51b35a45
EC		 887 kfree(nic_data);
888 efx->nic_data = NULL;
889}
Linux 6.x block layer and io_uring tree(s)