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Merge git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-next
[linux-block.git] / drivers / net / ethernet / sfc / ef100_nic.c
CommitLineData
51b35a45
EC		 1// SPDX-License-Identifier: GPL-2.0-only
2/****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation, incorporated herein by reference.
10 */
11
12#include "ef100_nic.h"
13#include "efx_common.h"
14#include "efx_channels.h"
15#include "io.h"
16#include "selftest.h"
17#include "ef100_regs.h"
18#include "mcdi.h"
19#include "mcdi_pcol.h"
20#include "mcdi_port_common.h"
21#include "mcdi_functions.h"
22#include "mcdi_filters.h"
23#include "ef100_rx.h"
24#include "ef100_tx.h"
25#include "ef100_netdev.h"
26
27#define EF100_MAX_VIS 4096
2200e6d9
EC		 28#define EF100_NUM_MCDI_BUFFERS 1
29#define MCDI_BUF_LEN (8 + MCDI_CTL_SDU_LEN_MAX)
51b35a45 30
c027f2a7
EC		 31#define EF100_RESET_PORT ((ETH_RESET_MAC | ETH_RESET_PHY) << ETH_RESET_SHARED_SHIFT)
32
51b35a45
EC		 33/* MCDI
34 */
2200e6d9
EC		 35static u8 *ef100_mcdi_buf(struct efx_nic *efx, u8 bufid, dma_addr_t *dma_addr)
36{
37 struct ef100_nic_data *nic_data = efx->nic_data;
38
39 if (dma_addr)
40 *dma_addr = nic_data->mcdi_buf.dma_addr +
41 bufid * ALIGN(MCDI_BUF_LEN, 256);
42 return nic_data->mcdi_buf.addr + bufid * ALIGN(MCDI_BUF_LEN, 256);
43}
44
51b35a45
EC		 45static int ef100_get_warm_boot_count(struct efx_nic *efx)
46{
47 efx_dword_t reg;
48
49 efx_readd(efx, &reg, efx_reg(efx, ER_GZ_MC_SFT_STATUS));
50
51 if (EFX_DWORD_FIELD(reg, EFX_DWORD_0) == 0xffffffff) {
52 netif_err(efx, hw, efx->net_dev, "Hardware unavailable\n");
53 efx->state = STATE_DISABLED;
54 return -ENETDOWN;
55 } else {
56 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
57 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
58 }
59}
60
2200e6d9
EC		 61static void ef100_mcdi_request(struct efx_nic *efx,
62 const efx_dword_t *hdr, size_t hdr_len,
63 const efx_dword_t *sdu, size_t sdu_len)
64{
65 dma_addr_t dma_addr;
66 u8 *pdu = ef100_mcdi_buf(efx, 0, &dma_addr);
67
68 memcpy(pdu, hdr, hdr_len);
69 memcpy(pdu + hdr_len, sdu, sdu_len);
70 wmb();
71
72 /* The hardware provides 'low' and 'high' (doorbell) registers
73 * for passing the 64-bit address of an MCDI request to
74 * firmware. However the dwords are swapped by firmware. The
75 * least significant bits of the doorbell are then 0 for all
76 * MCDI requests due to alignment.
77 */
78 _efx_writed(efx, cpu_to_le32((u64)dma_addr >> 32), efx_reg(efx, ER_GZ_MC_DB_LWRD));
79 _efx_writed(efx, cpu_to_le32((u32)dma_addr), efx_reg(efx, ER_GZ_MC_DB_HWRD));
80}
81
82static bool ef100_mcdi_poll_response(struct efx_nic *efx)
83{
84 const efx_dword_t hdr =
85 *(const efx_dword_t *)(ef100_mcdi_buf(efx, 0, NULL));
86
87 rmb();
88 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
89}
90
91static void ef100_mcdi_read_response(struct efx_nic *efx,
92 efx_dword_t *outbuf, size_t offset,
93 size_t outlen)
94{
95 const u8 *pdu = ef100_mcdi_buf(efx, 0, NULL);
96
97 memcpy(outbuf, pdu + offset, outlen);
98}
99
100static int ef100_mcdi_poll_reboot(struct efx_nic *efx)
101{
102 struct ef100_nic_data *nic_data = efx->nic_data;
103 int rc;
104
105 rc = ef100_get_warm_boot_count(efx);
106 if (rc < 0) {
107 /* The firmware is presumably in the process of
108 * rebooting. However, we are supposed to report each
109 * reboot just once, so we must only do that once we
110 * can read and store the updated warm boot count.
111 */
112 return 0;
113 }
114
115 if (rc == nic_data->warm_boot_count)
116 return 0;
117
118 nic_data->warm_boot_count = rc;
119
120 return -EIO;
121}
122
123static void ef100_mcdi_reboot_detected(struct efx_nic *efx)
124{
125}
126
f6573120
EC		 127/* MCDI calls
128 */
29ec1b27
EC		 129static int ef100_get_mac_address(struct efx_nic *efx, u8 *mac_address)
130{
131 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
132 size_t outlen;
133 int rc;
134
135 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
136
137 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
138 outbuf, sizeof(outbuf), &outlen);
139 if (rc)
140 return rc;
141 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
142 return -EIO;
143
144 ether_addr_copy(mac_address,
145 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
146 return 0;
147}
148
f6573120
EC		 149static int efx_ef100_init_datapath_caps(struct efx_nic *efx)
150{
d802b0ae 151 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V7_OUT_LEN);
f6573120
EC		 152 struct ef100_nic_data *nic_data = efx->nic_data;
153 u8 vi_window_mode;
154 size_t outlen;
155 int rc;
156
157 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
158
159 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
160 outbuf, sizeof(outbuf), &outlen);
161 if (rc)
162 return rc;
163 if (outlen < MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
164 netif_err(efx, drv, efx->net_dev,
165 "unable to read datapath firmware capabilities\n");
166 return -EIO;
167 }
168
169 nic_data->datapath_caps = MCDI_DWORD(outbuf,
170 GET_CAPABILITIES_OUT_FLAGS1);
171 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
172 GET_CAPABILITIES_V2_OUT_FLAGS2);
d802b0ae
EC		 173 if (outlen < MC_CMD_GET_CAPABILITIES_V7_OUT_LEN)
174 nic_data->datapath_caps3 = 0;
175 else
176 nic_data->datapath_caps3 = MCDI_DWORD(outbuf,
177 GET_CAPABILITIES_V7_OUT_FLAGS3);
f6573120
EC		 178
179 vi_window_mode = MCDI_BYTE(outbuf,
180 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
181 rc = efx_mcdi_window_mode_to_stride(efx, vi_window_mode);
182 if (rc)
183 return rc;
184
185 if (efx_ef100_has_cap(nic_data->datapath_caps2, TX_TSO_V3))
186 efx->net_dev->features |= NETIF_F_TSO | NETIF_F_TSO6;
187 efx->num_mac_stats = MCDI_WORD(outbuf,
188 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
189 netif_dbg(efx, probe, efx->net_dev,
190 "firmware reports num_mac_stats = %u\n",
191 efx->num_mac_stats);
192 return 0;
193}
194
51b35a45
EC		 195/* Event handling
196 */
197static int ef100_ev_probe(struct efx_channel *channel)
198{
199 /* Allocate an extra descriptor for the QMDA status completion entry */
200 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
201 (channel->eventq_mask + 2) *
202 sizeof(efx_qword_t),
203 GFP_KERNEL);
204}
205
965b549f
EC		 206static int ef100_ev_init(struct efx_channel *channel)
207{
208 struct ef100_nic_data *nic_data = channel->efx->nic_data;
209
210 /* initial phase is 0 */
211 clear_bit(channel->channel, nic_data->evq_phases);
212
213 return efx_mcdi_ev_init(channel, false, false);
214}
215
216static void ef100_ev_read_ack(struct efx_channel *channel)
217{
218 efx_dword_t evq_prime;
219
220 EFX_POPULATE_DWORD_2(evq_prime,
221 ERF_GZ_EVQ_ID, channel->channel,
222 ERF_GZ_IDX, channel->eventq_read_ptr &
223 channel->eventq_mask);
224
225 efx_writed(channel->efx, &evq_prime,
226 efx_reg(channel->efx, ER_GZ_EVQ_INT_PRIME));
227}
228
229static int ef100_ev_process(struct efx_channel *channel, int quota)
230{
5e4ef673
EC		 231 struct efx_nic *efx = channel->efx;
232 struct ef100_nic_data *nic_data;
233 bool evq_phase, old_evq_phase;
234 unsigned int read_ptr;
235 efx_qword_t *p_event;
236 int spent = 0;
237 bool ev_phase;
238 int ev_type;
239
240 if (unlikely(!channel->enabled))
241 return 0;
242
243 nic_data = efx->nic_data;
244 evq_phase = test_bit(channel->channel, nic_data->evq_phases);
245 old_evq_phase = evq_phase;
246 read_ptr = channel->eventq_read_ptr;
247 BUILD_BUG_ON(ESF_GZ_EV_RXPKTS_PHASE_LBN != ESF_GZ_EV_TXCMPL_PHASE_LBN);
248
249 while (spent < quota) {
250 p_event = efx_event(channel, read_ptr);
251
252 ev_phase = !!EFX_QWORD_FIELD(*p_event, ESF_GZ_EV_RXPKTS_PHASE);
253 if (ev_phase != evq_phase)
254 break;
255
256 netif_vdbg(efx, drv, efx->net_dev,
257 "processing event on %d " EFX_QWORD_FMT "\n",
258 channel->channel, EFX_QWORD_VAL(*p_event));
259
260 ev_type = EFX_QWORD_FIELD(*p_event, ESF_GZ_E_TYPE);
261
262 switch (ev_type) {
8e57daf7
EC		 263 case ESE_GZ_EF100_EV_RX_PKTS:
264 efx_ef100_ev_rx(channel, p_event);
265 ++spent;
266 break;
5e4ef673
EC		 267 case ESE_GZ_EF100_EV_MCDI:
268 efx_mcdi_process_event(channel, p_event);
269 break;
d19a5372
EC		 270 case ESE_GZ_EF100_EV_TX_COMPLETION:
271 ef100_ev_tx(channel, p_event);
272 break;
5e4ef673
EC		 273 case ESE_GZ_EF100_EV_DRIVER:
274 netif_info(efx, drv, efx->net_dev,
275 "Driver initiated event " EFX_QWORD_FMT "\n",
276 EFX_QWORD_VAL(*p_event));
277 break;
278 default:
279 netif_info(efx, drv, efx->net_dev,
280 "Unhandled event " EFX_QWORD_FMT "\n",
281 EFX_QWORD_VAL(*p_event));
282 }
283
284 ++read_ptr;
285 if ((read_ptr & channel->eventq_mask) == 0)
286 evq_phase = !evq_phase;
287 }
288
289 channel->eventq_read_ptr = read_ptr;
290 if (evq_phase != old_evq_phase)
291 change_bit(channel->channel, nic_data->evq_phases);
292
293 return spent;
965b549f
EC		 294}
295
51b35a45
EC		 296static irqreturn_t ef100_msi_interrupt(int irq, void *dev_id)
297{
298 struct efx_msi_context *context = dev_id;
299 struct efx_nic *efx = context->efx;
300
301 netif_vdbg(efx, intr, efx->net_dev,
302 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
303
304 if (likely(READ_ONCE(efx->irq_soft_enabled))) {
305 /* Note test interrupts */
306 if (context->index == efx->irq_level)
307 efx->last_irq_cpu = raw_smp_processor_id();
308
309 /* Schedule processing of the channel */
310 efx_schedule_channel_irq(efx->channel[context->index]);
311 }
312
313 return IRQ_HANDLED;
314}
315
aa86a75f
EC		 316static int ef100_phy_probe(struct efx_nic *efx)
317{
99a23c11
EC		 318 struct efx_mcdi_phy_data *phy_data;
319 int rc;
320
321 /* Probe for the PHY */
aa86a75f
EC		 322 efx->phy_data = kzalloc(sizeof(struct efx_mcdi_phy_data), GFP_KERNEL);
323 if (!efx->phy_data)
324 return -ENOMEM;
325
99a23c11
EC		 326 rc = efx_mcdi_get_phy_cfg(efx, efx->phy_data);
327 if (rc)
328 return rc;
329
330 /* Populate driver and ethtool settings */
331 phy_data = efx->phy_data;
332 mcdi_to_ethtool_linkset(phy_data->media, phy_data->supported_cap,
333 efx->link_advertising);
334 efx->fec_config = mcdi_fec_caps_to_ethtool(phy_data->supported_cap,
335 false);
336
337 /* Default to Autonegotiated flow control if the PHY supports it */
338 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
339 if (phy_data->supported_cap & (1 << MC_CMD_PHY_CAP_AN_LBN))
340 efx->wanted_fc |= EFX_FC_AUTO;
341 efx_link_set_wanted_fc(efx, efx->wanted_fc);
342
343 /* Push settings to the PHY. Failure is not fatal, the user can try to
344 * fix it using ethtool.
345 */
346 rc = efx_mcdi_port_reconfigure(efx);
347 if (rc && rc != -EPERM)
348 netif_warn(efx, drv, efx->net_dev,
349 "could not initialise PHY settings\n");
350
aa86a75f
EC		 351 return 0;
352}
353
a9dc3d56
EC		 354static int ef100_filter_table_probe(struct efx_nic *efx)
355{
356 return efx_mcdi_filter_table_probe(efx, true);
357}
358
359static int ef100_filter_table_up(struct efx_nic *efx)
360{
361 int rc;
362
363 rc = efx_mcdi_filter_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
364 if (rc) {
365 efx_mcdi_filter_table_down(efx);
366 return rc;
367 }
368
369 rc = efx_mcdi_filter_add_vlan(efx, 0);
370 if (rc) {
371 efx_mcdi_filter_del_vlan(efx, EFX_FILTER_VID_UNSPEC);
372 efx_mcdi_filter_table_down(efx);
373 }
374
375 return rc;
376}
377
378static void ef100_filter_table_down(struct efx_nic *efx)
379{
380 efx_mcdi_filter_del_vlan(efx, 0);
381 efx_mcdi_filter_del_vlan(efx, EFX_FILTER_VID_UNSPEC);
382 efx_mcdi_filter_table_down(efx);
383}
384
c027f2a7
EC		 385/* Other
386 */
99a23c11
EC		 387static int ef100_reconfigure_mac(struct efx_nic *efx, bool mtu_only)
388{
389 WARN_ON(!mutex_is_locked(&efx->mac_lock));
390
391 efx_mcdi_filter_sync_rx_mode(efx);
392
393 if (mtu_only && efx_has_cap(efx, SET_MAC_ENHANCED))
394 return efx_mcdi_set_mtu(efx);
395 return efx_mcdi_set_mac(efx);
396}
c027f2a7
EC		 397
398static enum reset_type ef100_map_reset_reason(enum reset_type reason)
399{
400 if (reason == RESET_TYPE_TX_WATCHDOG)
401 return reason;
402 return RESET_TYPE_DISABLE;
403}
404
405static int ef100_map_reset_flags(u32 *flags)
406{
407 /* Only perform a RESET_TYPE_ALL because we don't support MC_REBOOTs */
408 if ((*flags & EF100_RESET_PORT)) {
409 *flags &= ~EF100_RESET_PORT;
410 return RESET_TYPE_ALL;
411 }
412 if (*flags & ETH_RESET_MGMT) {
413 *flags &= ~ETH_RESET_MGMT;
414 return RESET_TYPE_DISABLE;
415 }
416
417 return -EINVAL;
418}
419
420static int ef100_reset(struct efx_nic *efx, enum reset_type reset_type)
421{
422 int rc;
423
424 dev_close(efx->net_dev);
425
426 if (reset_type == RESET_TYPE_TX_WATCHDOG) {
427 netif_device_attach(efx->net_dev);
428 __clear_bit(reset_type, &efx->reset_pending);
429 rc = dev_open(efx->net_dev, NULL);
430 } else if (reset_type == RESET_TYPE_ALL) {
a9dc3d56
EC		 431 /* A RESET_TYPE_ALL will cause filters to be removed, so we remove filters
432 * and reprobe after reset to avoid removing filters twice
433 */
434 down_read(&efx->filter_sem);
435 ef100_filter_table_down(efx);
436 up_read(&efx->filter_sem);
4e5675bb
EC		 437 rc = efx_mcdi_reset(efx, reset_type);
438 if (rc)
439 return rc;
440
c027f2a7
EC		 441 netif_device_attach(efx->net_dev);
442
a9dc3d56
EC		 443 down_read(&efx->filter_sem);
444 rc = ef100_filter_table_up(efx);
445 up_read(&efx->filter_sem);
446 if (rc)
447 return rc;
448
c027f2a7
EC		 449 rc = dev_open(efx->net_dev, NULL);
450 } else {
451 rc = 1; /* Leave the device closed */
452 }
453 return rc;
454}
455
b593b6f1
EC		 456static void ef100_common_stat_mask(unsigned long *mask)
457{
458 __set_bit(EF100_STAT_port_rx_packets, mask);
459 __set_bit(EF100_STAT_port_tx_packets, mask);
460 __set_bit(EF100_STAT_port_rx_bytes, mask);
461 __set_bit(EF100_STAT_port_tx_bytes, mask);
462 __set_bit(EF100_STAT_port_rx_multicast, mask);
463 __set_bit(EF100_STAT_port_rx_bad, mask);
464 __set_bit(EF100_STAT_port_rx_align_error, mask);
465 __set_bit(EF100_STAT_port_rx_overflow, mask);
466}
467
468static void ef100_ethtool_stat_mask(unsigned long *mask)
469{
470 __set_bit(EF100_STAT_port_tx_pause, mask);
471 __set_bit(EF100_STAT_port_tx_unicast, mask);
472 __set_bit(EF100_STAT_port_tx_multicast, mask);
473 __set_bit(EF100_STAT_port_tx_broadcast, mask);
474 __set_bit(EF100_STAT_port_tx_lt64, mask);
475 __set_bit(EF100_STAT_port_tx_64, mask);
476 __set_bit(EF100_STAT_port_tx_65_to_127, mask);
477 __set_bit(EF100_STAT_port_tx_128_to_255, mask);
478 __set_bit(EF100_STAT_port_tx_256_to_511, mask);
479 __set_bit(EF100_STAT_port_tx_512_to_1023, mask);
480 __set_bit(EF100_STAT_port_tx_1024_to_15xx, mask);
481 __set_bit(EF100_STAT_port_tx_15xx_to_jumbo, mask);
482 __set_bit(EF100_STAT_port_rx_good, mask);
483 __set_bit(EF100_STAT_port_rx_pause, mask);
484 __set_bit(EF100_STAT_port_rx_unicast, mask);
485 __set_bit(EF100_STAT_port_rx_broadcast, mask);
486 __set_bit(EF100_STAT_port_rx_lt64, mask);
487 __set_bit(EF100_STAT_port_rx_64, mask);
488 __set_bit(EF100_STAT_port_rx_65_to_127, mask);
489 __set_bit(EF100_STAT_port_rx_128_to_255, mask);
490 __set_bit(EF100_STAT_port_rx_256_to_511, mask);
491 __set_bit(EF100_STAT_port_rx_512_to_1023, mask);
492 __set_bit(EF100_STAT_port_rx_1024_to_15xx, mask);
493 __set_bit(EF100_STAT_port_rx_15xx_to_jumbo, mask);
494 __set_bit(EF100_STAT_port_rx_gtjumbo, mask);
495 __set_bit(EF100_STAT_port_rx_bad_gtjumbo, mask);
496 __set_bit(EF100_STAT_port_rx_length_error, mask);
497 __set_bit(EF100_STAT_port_rx_nodesc_drops, mask);
498 __set_bit(GENERIC_STAT_rx_nodesc_trunc, mask);
499 __set_bit(GENERIC_STAT_rx_noskb_drops, mask);
500}
501
502#define EF100_DMA_STAT(ext_name, mcdi_name) \
503 [EF100_STAT_ ## ext_name] = \
504 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
505
506static const struct efx_hw_stat_desc ef100_stat_desc[EF100_STAT_COUNT] = {
507 EF100_DMA_STAT(port_tx_bytes, TX_BYTES),
508 EF100_DMA_STAT(port_tx_packets, TX_PKTS),
509 EF100_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
510 EF100_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
511 EF100_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
512 EF100_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
513 EF100_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
514 EF100_DMA_STAT(port_tx_64, TX_64_PKTS),
515 EF100_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
516 EF100_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
517 EF100_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
518 EF100_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
519 EF100_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
520 EF100_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
521 EF100_DMA_STAT(port_rx_bytes, RX_BYTES),
522 EF100_DMA_STAT(port_rx_packets, RX_PKTS),
523 EF100_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
524 EF100_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
525 EF100_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
526 EF100_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
527 EF100_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
528 EF100_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
529 EF100_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
530 EF100_DMA_STAT(port_rx_64, RX_64_PKTS),
531 EF100_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
532 EF100_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
533 EF100_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
534 EF100_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
535 EF100_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
536 EF100_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
537 EF100_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
538 EF100_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
539 EF100_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
540 EF100_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
541 EF100_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
542 EF100_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
543 EFX_GENERIC_SW_STAT(rx_nodesc_trunc),
544 EFX_GENERIC_SW_STAT(rx_noskb_drops),
545};
546
547static size_t ef100_describe_stats(struct efx_nic *efx, u8 *names)
548{
549 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {};
550
551 ef100_ethtool_stat_mask(mask);
552 return efx_nic_describe_stats(ef100_stat_desc, EF100_STAT_COUNT,
553 mask, names);
554}
555
556static size_t ef100_update_stats_common(struct efx_nic *efx, u64 *full_stats,
557 struct rtnl_link_stats64 *core_stats)
558{
559 struct ef100_nic_data *nic_data = efx->nic_data;
560 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {};
561 size_t stats_count = 0, index;
562 u64 *stats = nic_data->stats;
563
564 ef100_ethtool_stat_mask(mask);
565
566 if (full_stats) {
567 for_each_set_bit(index, mask, EF100_STAT_COUNT) {
568 if (ef100_stat_desc[index].name) {
569 *full_stats++ = stats[index];
570 ++stats_count;
571 }
572 }
573 }
574
575 if (!core_stats)
576 return stats_count;
577
578 core_stats->rx_packets = stats[EF100_STAT_port_rx_packets];
579 core_stats->tx_packets = stats[EF100_STAT_port_tx_packets];
580 core_stats->rx_bytes = stats[EF100_STAT_port_rx_bytes];
581 core_stats->tx_bytes = stats[EF100_STAT_port_tx_bytes];
582 core_stats->rx_dropped = stats[EF100_STAT_port_rx_nodesc_drops] +
583 stats[GENERIC_STAT_rx_nodesc_trunc] +
584 stats[GENERIC_STAT_rx_noskb_drops];
585 core_stats->multicast = stats[EF100_STAT_port_rx_multicast];
586 core_stats->rx_length_errors =
587 stats[EF100_STAT_port_rx_gtjumbo] +
588 stats[EF100_STAT_port_rx_length_error];
589 core_stats->rx_crc_errors = stats[EF100_STAT_port_rx_bad];
590 core_stats->rx_frame_errors =
591 stats[EF100_STAT_port_rx_align_error];
592 core_stats->rx_fifo_errors = stats[EF100_STAT_port_rx_overflow];
593 core_stats->rx_errors = (core_stats->rx_length_errors +
594 core_stats->rx_crc_errors +
595 core_stats->rx_frame_errors);
596
597 return stats_count;
598}
599
600static size_t ef100_update_stats(struct efx_nic *efx,
601 u64 *full_stats,
602 struct rtnl_link_stats64 *core_stats)
603{
604 __le64 *mc_stats = kmalloc(array_size(efx->num_mac_stats, sizeof(__le64)), GFP_ATOMIC);
605 struct ef100_nic_data *nic_data = efx->nic_data;
606 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {};
607 u64 *stats = nic_data->stats;
608
609 ef100_common_stat_mask(mask);
610 ef100_ethtool_stat_mask(mask);
611
612 efx_nic_copy_stats(efx, mc_stats);
613 efx_nic_update_stats(ef100_stat_desc, EF100_STAT_COUNT, mask,
614 stats, mc_stats, false);
615
616 kfree(mc_stats);
617
618 return ef100_update_stats_common(efx, full_stats, core_stats);
619}
620
1c748843
EC		 621static int efx_ef100_get_phys_port_id(struct efx_nic *efx,
622 struct netdev_phys_item_id *ppid)
623{
624 struct ef100_nic_data *nic_data = efx->nic_data;
625
626 if (!is_valid_ether_addr(nic_data->port_id))
627 return -EOPNOTSUPP;
628
629 ppid->id_len = ETH_ALEN;
630 memcpy(ppid->id, nic_data->port_id, ppid->id_len);
631
632 return 0;
633}
634
43c3df0d
EC		 635static int efx_ef100_irq_test_generate(struct efx_nic *efx)
636{
637 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
638
639 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
640
641 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
642 return efx_mcdi_rpc_quiet(efx, MC_CMD_TRIGGER_INTERRUPT,
643 inbuf, sizeof(inbuf), NULL, 0, NULL);
644}
645
646#define EFX_EF100_TEST 1
647
648static void efx_ef100_ev_test_generate(struct efx_channel *channel)
649{
650 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
651 struct efx_nic *efx = channel->efx;
652 efx_qword_t event;
653 int rc;
654
655 EFX_POPULATE_QWORD_2(event,
656 ESF_GZ_E_TYPE, ESE_GZ_EF100_EV_DRIVER,
657 ESF_GZ_DRIVER_DATA, EFX_EF100_TEST);
658
659 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
660
661 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
662 * already swapped the data to little-endian order.
663 */
664 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
665 sizeof(efx_qword_t));
666
667 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
668 NULL, 0, NULL);
669 if (rc && (rc != -ENETDOWN))
670 goto fail;
671
672 return;
673
674fail:
675 WARN_ON(true);
676 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
677}
678
965b549f
EC		 679static unsigned int ef100_check_caps(const struct efx_nic *efx,
680 u8 flag, u32 offset)
681{
f6573120
EC		 682 const struct ef100_nic_data *nic_data = efx->nic_data;
683
684 switch (offset) {
685 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_OFST:
686 return nic_data->datapath_caps & BIT_ULL(flag);
687 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_OFST:
688 return nic_data->datapath_caps2 & BIT_ULL(flag);
d802b0ae
EC		 689 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_OFST:
690 return nic_data->datapath_caps3 & BIT_ULL(flag);
f6573120
EC		 691 default:
692 return 0;
693 }
965b549f
EC		 694}
695
51b35a45
EC		 696/* NIC level access functions
697 */
8e57daf7 698#define EF100_OFFLOAD_FEATURES (NETIF_F_HW_CSUM | NETIF_F_RXCSUM | \
d19a5372 699 NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_FRAGLIST | \
8e57daf7
EC		 700 NETIF_F_RXHASH | NETIF_F_RXFCS | NETIF_F_TSO_ECN | NETIF_F_RXALL | \
701 NETIF_F_TSO_MANGLEID | NETIF_F_HW_VLAN_CTAG_TX)
d19a5372 702
51b35a45
EC		 703const struct efx_nic_type ef100_pf_nic_type = {
704 .revision = EFX_REV_EF100,
705 .is_vf = false,
706 .probe = ef100_probe_pf,
d19a5372 707 .offload_features = EF100_OFFLOAD_FEATURES,
51b35a45 708 .mcdi_max_ver = 2,
2200e6d9
EC		 709 .mcdi_request = ef100_mcdi_request,
710 .mcdi_poll_response = ef100_mcdi_poll_response,
711 .mcdi_read_response = ef100_mcdi_read_response,
712 .mcdi_poll_reboot = ef100_mcdi_poll_reboot,
713 .mcdi_reboot_detected = ef100_mcdi_reboot_detected,
51b35a45 714 .irq_enable_master = efx_port_dummy_op_void,
43c3df0d 715 .irq_test_generate = efx_ef100_irq_test_generate,
51b35a45
EC		 716 .irq_disable_non_ev = efx_port_dummy_op_void,
717 .push_irq_moderation = efx_channel_dummy_op_void,
718 .min_interrupt_mode = EFX_INT_MODE_MSIX,
c027f2a7
EC		 719 .map_reset_reason = ef100_map_reset_reason,
720 .map_reset_flags = ef100_map_reset_flags,
721 .reset = ef100_reset,
51b35a45 722
965b549f
EC		 723 .check_caps = ef100_check_caps,
724
51b35a45 725 .ev_probe = ef100_ev_probe,
965b549f
EC		 726 .ev_init = ef100_ev_init,
727 .ev_fini = efx_mcdi_ev_fini,
728 .ev_remove = efx_mcdi_ev_remove,
51b35a45 729 .irq_handle_msi = ef100_msi_interrupt,
965b549f
EC		 730 .ev_process = ef100_ev_process,
731 .ev_read_ack = ef100_ev_read_ack,
43c3df0d 732 .ev_test_generate = efx_ef100_ev_test_generate,
965b549f
EC		 733 .tx_probe = ef100_tx_probe,
734 .tx_init = ef100_tx_init,
735 .tx_write = ef100_tx_write,
736 .tx_enqueue = ef100_enqueue_skb,
737 .rx_probe = efx_mcdi_rx_probe,
738 .rx_init = efx_mcdi_rx_init,
739 .rx_remove = efx_mcdi_rx_remove,
740 .rx_write = ef100_rx_write,
741 .rx_packet = __ef100_rx_packet,
b780feac 742 .fini_dmaq = efx_fini_dmaq,
a9dc3d56
EC		 743 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS,
744 .filter_table_probe = ef100_filter_table_up,
745 .filter_table_restore = efx_mcdi_filter_table_restore,
746 .filter_table_remove = ef100_filter_table_down,
747 .filter_insert = efx_mcdi_filter_insert,
748 .filter_remove_safe = efx_mcdi_filter_remove_safe,
749 .filter_get_safe = efx_mcdi_filter_get_safe,
750 .filter_clear_rx = efx_mcdi_filter_clear_rx,
751 .filter_count_rx_used = efx_mcdi_filter_count_rx_used,
752 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit,
753 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids,
754#ifdef CONFIG_RFS_ACCEL
755 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one,
756#endif
51b35a45 757
1c748843
EC		 758 .get_phys_port_id = efx_ef100_get_phys_port_id,
759
8e57daf7
EC		 760 .rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN,
761 .rx_hash_offset = ESF_GZ_RX_PREFIX_RSS_HASH_LBN / 8,
762 .rx_ts_offset = ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN / 8,
763 .rx_hash_key_size = 40,
764 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config,
765 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config,
766 .rx_push_rss_context_config = efx_mcdi_rx_push_rss_context_config,
767 .rx_pull_rss_context_config = efx_mcdi_rx_pull_rss_context_config,
768 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts,
769
99a23c11 770 .reconfigure_mac = ef100_reconfigure_mac,
43c3df0d 771 .test_nvram = efx_new_mcdi_nvram_test_all,
b593b6f1
EC		 772 .describe_stats = ef100_describe_stats,
773 .start_stats = efx_mcdi_mac_start_stats,
774 .update_stats = ef100_update_stats,
775 .pull_stats = efx_mcdi_mac_pull_stats,
776 .stop_stats = efx_mcdi_mac_stop_stats,
99a23c11 777
51b35a45
EC		 778 /* Per-type bar/size configuration not used on ef100. Location of
779 * registers is defined by extended capabilities.
780 */
781 .mem_bar = NULL,
782 .mem_map_size = NULL,
783
784};
785
d61592a1
EC		 786const struct efx_nic_type ef100_vf_nic_type = {
787 .revision = EFX_REV_EF100,
788 .is_vf = true,
789 .probe = ef100_probe_vf,
790 .offload_features = EF100_OFFLOAD_FEATURES,
791 .mcdi_max_ver = 2,
792 .mcdi_request = ef100_mcdi_request,
793 .mcdi_poll_response = ef100_mcdi_poll_response,
794 .mcdi_read_response = ef100_mcdi_read_response,
795 .mcdi_poll_reboot = ef100_mcdi_poll_reboot,
796 .mcdi_reboot_detected = ef100_mcdi_reboot_detected,
797 .irq_enable_master = efx_port_dummy_op_void,
798 .irq_test_generate = efx_ef100_irq_test_generate,
799 .irq_disable_non_ev = efx_port_dummy_op_void,
800 .push_irq_moderation = efx_channel_dummy_op_void,
801 .min_interrupt_mode = EFX_INT_MODE_MSIX,
802 .map_reset_reason = ef100_map_reset_reason,
803 .map_reset_flags = ef100_map_reset_flags,
804 .reset = ef100_reset,
805 .check_caps = ef100_check_caps,
806 .ev_probe = ef100_ev_probe,
807 .ev_init = ef100_ev_init,
808 .ev_fini = efx_mcdi_ev_fini,
809 .ev_remove = efx_mcdi_ev_remove,
810 .irq_handle_msi = ef100_msi_interrupt,
811 .ev_process = ef100_ev_process,
812 .ev_read_ack = ef100_ev_read_ack,
813 .ev_test_generate = efx_ef100_ev_test_generate,
814 .tx_probe = ef100_tx_probe,
815 .tx_init = ef100_tx_init,
816 .tx_write = ef100_tx_write,
817 .tx_enqueue = ef100_enqueue_skb,
818 .rx_probe = efx_mcdi_rx_probe,
819 .rx_init = efx_mcdi_rx_init,
820 .rx_remove = efx_mcdi_rx_remove,
821 .rx_write = ef100_rx_write,
822 .rx_packet = __ef100_rx_packet,
823 .fini_dmaq = efx_fini_dmaq,
824 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS,
825 .filter_table_probe = ef100_filter_table_up,
826 .filter_table_restore = efx_mcdi_filter_table_restore,
827 .filter_table_remove = ef100_filter_table_down,
828 .filter_insert = efx_mcdi_filter_insert,
829 .filter_remove_safe = efx_mcdi_filter_remove_safe,
830 .filter_get_safe = efx_mcdi_filter_get_safe,
831 .filter_clear_rx = efx_mcdi_filter_clear_rx,
832 .filter_count_rx_used = efx_mcdi_filter_count_rx_used,
833 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit,
834 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids,
835 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one,
836
837 .rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN,
838 .rx_hash_offset = ESF_GZ_RX_PREFIX_RSS_HASH_LBN / 8,
839 .rx_ts_offset = ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN / 8,
840 .rx_hash_key_size = 40,
841 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config,
842 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config,
843 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts,
844
845 .reconfigure_mac = ef100_reconfigure_mac,
846 .test_nvram = efx_new_mcdi_nvram_test_all,
847 .describe_stats = ef100_describe_stats,
848 .start_stats = efx_mcdi_mac_start_stats,
849 .update_stats = ef100_update_stats,
850 .pull_stats = efx_mcdi_mac_pull_stats,
851 .stop_stats = efx_mcdi_mac_stop_stats,
852
853 .mem_bar = NULL,
854 .mem_map_size = NULL,
855
856};
857
8e737145
EC		 858static int compare_versions(const char *a, const char *b)
859{
860 int a_major, a_minor, a_point, a_patch;
861 int b_major, b_minor, b_point, b_patch;
862 int a_matched, b_matched;
863
864 a_matched = sscanf(a, "%d.%d.%d.%d", &a_major, &a_minor, &a_point, &a_patch);
865 b_matched = sscanf(b, "%d.%d.%d.%d", &b_major, &b_minor, &b_point, &b_patch);
866
867 if (a_matched == 4 && b_matched != 4)
868 return +1;
869
870 if (a_matched != 4 && b_matched == 4)
871 return -1;
872
873 if (a_matched != 4 && b_matched != 4)
874 return 0;
875
876 if (a_major != b_major)
877 return a_major - b_major;
878
879 if (a_minor != b_minor)
880 return a_minor - b_minor;
881
882 if (a_point != b_point)
883 return a_point - b_point;
884
885 return a_patch - b_patch;
886}
887
adcfc348
EC		 888enum ef100_tlv_state_machine {
889 EF100_TLV_TYPE,
890 EF100_TLV_TYPE_CONT,
891 EF100_TLV_LENGTH,
892 EF100_TLV_VALUE
893};
894
895struct ef100_tlv_state {
896 enum ef100_tlv_state_machine state;
897 u64 value;
898 u32 value_offset;
899 u16 type;
900 u8 len;
901};
902
903static int ef100_tlv_feed(struct ef100_tlv_state *state, u8 byte)
904{
905 switch (state->state) {
906 case EF100_TLV_TYPE:
907 state->type = byte & 0x7f;
908 state->state = (byte & 0x80) ? EF100_TLV_TYPE_CONT
909 : EF100_TLV_LENGTH;
910 /* Clear ready to read in a new entry */
911 state->value = 0;
912 state->value_offset = 0;
913 return 0;
914 case EF100_TLV_TYPE_CONT:
915 state->type |= byte << 7;
916 state->state = EF100_TLV_LENGTH;
917 return 0;
918 case EF100_TLV_LENGTH:
919 state->len = byte;
920 /* We only handle TLVs that fit in a u64 */
921 if (state->len > sizeof(state->value))
922 return -EOPNOTSUPP;
923 /* len may be zero, implying a value of zero */
924 state->state = state->len ? EF100_TLV_VALUE : EF100_TLV_TYPE;
925 return 0;
926 case EF100_TLV_VALUE:
927 state->value |= ((u64)byte) << (state->value_offset * 8);
928 state->value_offset++;
929 if (state->value_offset >= state->len)
930 state->state = EF100_TLV_TYPE;
931 return 0;
932 default: /* state machine error, can't happen */
933 WARN_ON_ONCE(1);
934 return -EIO;
935 }
936}
937
938static int ef100_process_design_param(struct efx_nic *efx,
939 const struct ef100_tlv_state *reader)
940{
941 struct ef100_nic_data *nic_data = efx->nic_data;
942
943 switch (reader->type) {
944 case ESE_EF100_DP_GZ_PAD: /* padding, skip it */
945 return 0;
946 case ESE_EF100_DP_GZ_PARTIAL_TSTAMP_SUB_NANO_BITS:
947 /* Driver doesn't support timestamping yet, so we don't care */
948 return 0;
949 case ESE_EF100_DP_GZ_EVQ_UNSOL_CREDIT_SEQ_BITS:
950 /* Driver doesn't support unsolicited-event credits yet, so
951 * we don't care
952 */
953 return 0;
954 case ESE_EF100_DP_GZ_NMMU_GROUP_SIZE:
955 /* Driver doesn't manage the NMMU (so we don't care) */
956 return 0;
957 case ESE_EF100_DP_GZ_RX_L4_CSUM_PROTOCOLS:
958 /* Driver uses CHECKSUM_COMPLETE, so we don't care about
959 * protocol checksum validation
960 */
961 return 0;
962 case ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN:
963 nic_data->tso_max_hdr_len = min_t(u64, reader->value, 0xffff);
964 return 0;
965 case ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS:
966 /* We always put HDR_NUM_SEGS=1 in our TSO descriptors */
967 if (!reader->value) {
968 netif_err(efx, probe, efx->net_dev,
969 "TSO_MAX_HDR_NUM_SEGS < 1\n");
970 return -EOPNOTSUPP;
971 }
972 return 0;
973 case ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY:
974 case ESE_EF100_DP_GZ_TXQ_SIZE_GRANULARITY:
975 /* Our TXQ and RXQ sizes are always power-of-two and thus divisible by
976 * EFX_MIN_DMAQ_SIZE, so we just need to check that
977 * EFX_MIN_DMAQ_SIZE is divisible by GRANULARITY.
978 * This is very unlikely to fail.
979 */
980 if (EFX_MIN_DMAQ_SIZE % reader->value) {
981 netif_err(efx, probe, efx->net_dev,
982 "%s size granularity is %llu, can't guarantee safety\n",
983 reader->type == ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY ? "RXQ" : "TXQ",
984 reader->value);
985 return -EOPNOTSUPP;
986 }
987 return 0;
988 case ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN:
989 nic_data->tso_max_payload_len = min_t(u64, reader->value, GSO_MAX_SIZE);
990 efx->net_dev->gso_max_size = nic_data->tso_max_payload_len;
991 return 0;
992 case ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS:
993 nic_data->tso_max_payload_num_segs = min_t(u64, reader->value, 0xffff);
994 efx->net_dev->gso_max_segs = nic_data->tso_max_payload_num_segs;
995 return 0;
996 case ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES:
997 nic_data->tso_max_frames = min_t(u64, reader->value, 0xffff);
998 return 0;
999 case ESE_EF100_DP_GZ_COMPAT:
1000 if (reader->value) {
1001 netif_err(efx, probe, efx->net_dev,
1002 "DP_COMPAT has unknown bits %#llx, driver not compatible with this hw\n",
1003 reader->value);
1004 return -EOPNOTSUPP;
1005 }
1006 return 0;
1007 case ESE_EF100_DP_GZ_MEM2MEM_MAX_LEN:
1008 /* Driver doesn't use mem2mem transfers */
1009 return 0;
1010 case ESE_EF100_DP_GZ_EVQ_TIMER_TICK_NANOS:
1011 /* Driver doesn't currently use EVQ_TIMER */
1012 return 0;
1013 case ESE_EF100_DP_GZ_NMMU_PAGE_SIZES:
1014 /* Driver doesn't manage the NMMU (so we don't care) */
1015 return 0;
1016 case ESE_EF100_DP_GZ_VI_STRIDES:
1017 /* We never try to set the VI stride, and we don't rely on
1018 * being able to find VIs past VI 0 until after we've learned
1019 * the current stride from MC_CMD_GET_CAPABILITIES.
1020 * So the value of this shouldn't matter.
1021 */
1022 if (reader->value != ESE_EF100_DP_GZ_VI_STRIDES_DEFAULT)
1023 netif_dbg(efx, probe, efx->net_dev,
1024 "NIC has other than default VI_STRIDES (mask "
1025 "%#llx), early probing might use wrong one\n",
1026 reader->value);
1027 return 0;
1028 case ESE_EF100_DP_GZ_RX_MAX_RUNT:
1029 /* Driver doesn't look at L2_STATUS:LEN_ERR bit, so we don't
1030 * care whether it indicates runt or overlength for any given
1031 * packet, so we don't care about this parameter.
1032 */
1033 return 0;
1034 default:
1035 /* Host interface says "Drivers should ignore design parameters
1036 * that they do not recognise."
1037 */
1038 netif_dbg(efx, probe, efx->net_dev,
1039 "Ignoring unrecognised design parameter %u\n",
1040 reader->type);
1041 return 0;
1042 }
1043}
1044
1045static int ef100_check_design_params(struct efx_nic *efx)
1046{
1047 struct ef100_tlv_state reader = {};
1048 u32 total_len, offset = 0;
1049 efx_dword_t reg;
1050 int rc = 0, i;
1051 u32 data;
1052
1053 efx_readd(efx, &reg, ER_GZ_PARAMS_TLV_LEN);
1054 total_len = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
1055 netif_dbg(efx, probe, efx->net_dev, "%u bytes of design parameters\n",
1056 total_len);
1057 while (offset < total_len) {
1058 efx_readd(efx, &reg, ER_GZ_PARAMS_TLV + offset);
1059 data = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
1060 for (i = 0; i < sizeof(data); i++) {
1061 rc = ef100_tlv_feed(&reader, data);
1062 /* Got a complete value? */
1063 if (!rc && reader.state == EF100_TLV_TYPE)
1064 rc = ef100_process_design_param(efx, &reader);
1065 if (rc)
1066 goto out;
1067 data >>= 8;
1068 offset++;
1069 }
1070 }
1071 /* Check we didn't end halfway through a TLV entry, which could either
1072 * mean that the TLV stream is truncated or just that it's corrupted
1073 * and our state machine is out of sync.
1074 */
1075 if (reader.state != EF100_TLV_TYPE) {
1076 if (reader.state == EF100_TLV_TYPE_CONT)
1077 netif_err(efx, probe, efx->net_dev,
1078 "truncated design parameter (incomplete type %u)\n",
1079 reader.type);
1080 else
1081 netif_err(efx, probe, efx->net_dev,
1082 "truncated design parameter %u\n",
1083 reader.type);
1084 rc = -EIO;
1085 }
1086out:
1087 return rc;
1088}
1089
51b35a45
EC		 1090/* NIC probe and remove
1091 */
1092static int ef100_probe_main(struct efx_nic *efx)
1093{
1094 unsigned int bar_size = resource_size(&efx->pci_dev->resource[efx->mem_bar]);
1095 struct net_device *net_dev = efx->net_dev;
1096 struct ef100_nic_data *nic_data;
8e737145 1097 char fw_version[32];
51b35a45
EC		 1098 int i, rc;
1099
1100 if (WARN_ON(bar_size == 0))
1101 return -EIO;
1102
1103 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
1104 if (!nic_data)
1105 return -ENOMEM;
1106 efx->nic_data = nic_data;
1107 nic_data->efx = efx;
1108 net_dev->features |= efx->type->offload_features;
1109 net_dev->hw_features |= efx->type->offload_features;
1110
adcfc348
EC		 1111 /* Populate design-parameter defaults */
1112 nic_data->tso_max_hdr_len = ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN_DEFAULT;
1113 nic_data->tso_max_frames = ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES_DEFAULT;
1114 nic_data->tso_max_payload_num_segs = ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS_DEFAULT;
1115 nic_data->tso_max_payload_len = ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN_DEFAULT;
1116 net_dev->gso_max_segs = ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS_DEFAULT;
1117 /* Read design parameters */
1118 rc = ef100_check_design_params(efx);
1119 if (rc) {
1120 netif_err(efx, probe, efx->net_dev,
1121 "Unsupported design parameters\n");
1122 goto fail;
1123 }
1124
2200e6d9
EC		 1125 /* we assume later that we can copy from this buffer in dwords */
1126 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
1127
1128 /* MCDI buffers must be 256 byte aligned. */
1129 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, MCDI_BUF_LEN,
1130 GFP_KERNEL);
1131 if (rc)
1132 goto fail;
1133
51b35a45
EC		 1134 /* Get the MC's warm boot count. In case it's rebooting right
1135 * now, be prepared to retry.
1136 */
1137 i = 0;
1138 for (;;) {
1139 rc = ef100_get_warm_boot_count(efx);
1140 if (rc >= 0)
1141 break;
1142 if (++i == 5)
1143 goto fail;
1144 ssleep(1);
1145 }
1146 nic_data->warm_boot_count = rc;
1147
1148 /* In case we're recovering from a crash (kexec), we want to
1149 * cancel any outstanding request by the previous user of this
1150 * function. We send a special message using the least
1151 * significant bits of the 'high' (doorbell) register.
1152 */
1153 _efx_writed(efx, cpu_to_le32(1), efx_reg(efx, ER_GZ_MC_DB_HWRD));
1154
1155 /* Post-IO section. */
1156
2200e6d9
EC		 1157 rc = efx_mcdi_init(efx);
1158 if (!rc && efx->mcdi->fn_flags &
1159 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT)) {
1160 netif_info(efx, probe, efx->net_dev,
1161 "No network port on this PCI function");
1162 rc = -ENODEV;
1163 }
1164 if (rc)
1165 goto fail;
4e5675bb
EC		 1166 /* Reset (most) configuration for this function */
1167 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
1168 if (rc)
1169 goto fail;
1170
ef2c57b9
EC		 1171 rc = efx_get_pf_index(efx, &nic_data->pf_index);
1172 if (rc)
1173 goto fail;
1174
f6573120
EC		 1175 rc = efx_ef100_init_datapath_caps(efx);
1176 if (rc < 0)
1177 goto fail;
2200e6d9 1178
51b35a45
EC		 1179 efx->max_vis = EF100_MAX_VIS;
1180
1c748843
EC		 1181 rc = efx_mcdi_port_get_number(efx);
1182 if (rc < 0)
1183 goto fail;
1184 efx->port_num = rc;
1185
8e737145
EC		 1186 efx_mcdi_print_fwver(efx, fw_version, sizeof(fw_version));
1187 netif_dbg(efx, drv, efx->net_dev, "Firmware version %s\n", fw_version);
1188
1189 if (compare_versions(fw_version, "1.1.0.1000") < 0) {
1190 netif_info(efx, drv, efx->net_dev, "Firmware uses old event descriptors\n");
1191 rc = -EINVAL;
4496363b
EC		 1192 goto fail;
1193 }
1194
1195 if (efx_has_cap(efx, UNSOL_EV_CREDIT_SUPPORTED)) {
1196 netif_info(efx, drv, efx->net_dev, "Firmware uses unsolicited-event credits\n");
1197 rc = -EINVAL;
8e737145
EC		 1198 goto fail;
1199 }
1200
aa86a75f
EC		 1201 rc = ef100_phy_probe(efx);
1202 if (rc)
1203 goto fail;
1204
51b35a45
EC		 1205 rc = efx_init_channels(efx);
1206 if (rc)
1207 goto fail;
1208
a9dc3d56
EC		 1209 down_write(&efx->filter_sem);
1210 rc = ef100_filter_table_probe(efx);
1211 up_write(&efx->filter_sem);
1212 if (rc)
1213 goto fail;
1214
8e57daf7
EC		 1215 netdev_rss_key_fill(efx->rss_context.rx_hash_key,
1216 sizeof(efx->rss_context.rx_hash_key));
1217
1218 /* Don't fail init if RSS setup doesn't work. */
1219 efx_mcdi_push_default_indir_table(efx, efx->n_rx_channels);
1220
51b35a45
EC		 1221 rc = ef100_register_netdev(efx);
1222 if (rc)
1223 goto fail;
1224
1225 return 0;
1226fail:
1227 return rc;
1228}
1229
1230int ef100_probe_pf(struct efx_nic *efx)
1231{
29ec1b27
EC		 1232 struct net_device *net_dev = efx->net_dev;
1233 struct ef100_nic_data *nic_data;
1234 int rc = ef100_probe_main(efx);
1235
1236 if (rc)
1237 goto fail;
1238
1239 nic_data = efx->nic_data;
1240 rc = ef100_get_mac_address(efx, net_dev->perm_addr);
1241 if (rc)
1242 goto fail;
1243 /* Assign MAC address */
1244 memcpy(net_dev->dev_addr, net_dev->perm_addr, ETH_ALEN);
1245 memcpy(nic_data->port_id, net_dev->perm_addr, ETH_ALEN);
1246
1247 return 0;
1248
1249fail:
1250 return rc;
51b35a45
EC		 1251}
1252
d61592a1
EC		 1253int ef100_probe_vf(struct efx_nic *efx)
1254{
1255 return ef100_probe_main(efx);
1256}
1257
51b35a45
EC		 1258void ef100_remove(struct efx_nic *efx)
1259{
1260 struct ef100_nic_data *nic_data = efx->nic_data;
1261
1262 ef100_unregister_netdev(efx);
a9dc3d56
EC		 1263
1264 down_write(&efx->filter_sem);
1265 efx_mcdi_filter_table_remove(efx);
1266 up_write(&efx->filter_sem);
51b35a45
EC		 1267 efx_fini_channels(efx);
1268 kfree(efx->phy_data);
1269 efx->phy_data = NULL;
2200e6d9
EC		 1270 efx_mcdi_detach(efx);
1271 efx_mcdi_fini(efx);
1272 if (nic_data)
1273 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
51b35a45
EC		 1274 kfree(nic_data);
1275 efx->nic_data = NULL;
1276}
Linux 6.x block layer and io_uring tree(s)