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net: phy: add driver for aquantia phy
[linux-2.6-block.git] / drivers / net / ethernet / sfc / ef10.c
CommitLineData
8127d661
BH		 1/****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10#include "net_driver.h"
11#include "ef10_regs.h"
12#include "io.h"
13#include "mcdi.h"
14#include "mcdi_pcol.h"
15#include "nic.h"
16#include "workarounds.h"
74cd60a4 17#include "selftest.h"
7fa8d547 18#include "ef10_sriov.h"
8127d661
BH		 19#include <linux/in.h>
20#include <linux/jhash.h>
21#include <linux/wait.h>
22#include <linux/workqueue.h>
23
24/* Hardware control for EF10 architecture including 'Huntington'. */
25
26#define EFX_EF10_DRVGEN_EV 7
27enum {
28 EFX_EF10_TEST = 1,
29 EFX_EF10_REFILL,
30};
31
32/* The reserved RSS context value */
33#define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
267c0157
JC		 34/* The maximum size of a shared RSS context */
35/* TODO: this should really be from the mcdi protocol export */
36#define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
8127d661
BH		 37
38/* The filter table(s) are managed by firmware and we have write-only
39 * access. When removing filters we must identify them to the
40 * firmware by a 64-bit handle, but this is too wide for Linux kernel
41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
42 * be able to tell in advance whether a requested insertion will
43 * replace an existing filter. Therefore we maintain a software hash
44 * table, which should be at least as large as the hardware hash
45 * table.
46 *
47 * Huntington has a single 8K filter table shared between all filter
48 * types and both ports.
49 */
50#define HUNT_FILTER_TBL_ROWS 8192
51
12fb0da4 52#define EFX_EF10_FILTER_ID_INVALID 0xffff
822b96f8
DP		 53struct efx_ef10_dev_addr {
54 u8 addr[ETH_ALEN];
55 u16 id;
56};
57
8127d661
BH		 58struct efx_ef10_filter_table {
59/* The RX match field masks supported by this fw & hw, in order of priority */
60 enum efx_filter_match_flags rx_match_flags[
61 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
62 unsigned int rx_match_count;
63
64 struct {
65 unsigned long spec; /* pointer to spec plus flag bits */
b59e6ef8
BH		 66/* BUSY flag indicates that an update is in progress. AUTO_OLD is
67 * used to mark and sweep MAC filters for the device address lists.
8127d661
BH		 68 */
69#define EFX_EF10_FILTER_FLAG_BUSY 1UL
b59e6ef8 70#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
8127d661
BH		 71#define EFX_EF10_FILTER_FLAGS 3UL
72 u64 handle; /* firmware handle */
73 } *entry;
74 wait_queue_head_t waitq;
75/* Shadow of net_device address lists, guarded by mac_lock */
b59e6ef8
BH		 76#define EFX_EF10_FILTER_DEV_UC_MAX 32
77#define EFX_EF10_FILTER_DEV_MC_MAX 256
822b96f8
DP		 78 struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
79 struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
12fb0da4
EC		 80 int dev_uc_count;
81 int dev_mc_count;
82/* Indices (like efx_ef10_dev_addr.id) for promisc/allmulti filters */
83 u16 ucdef_id;
84 u16 bcast_id;
85 u16 mcdef_id;
8127d661
BH		 86};
87
88/* An arbitrary search limit for the software hash table */
89#define EFX_EF10_FILTER_SEARCH_LIMIT 200
90
8127d661
BH		 91static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
92static void efx_ef10_filter_table_remove(struct efx_nic *efx);
93
94static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
95{
96 efx_dword_t reg;
97
98 efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
99 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
100 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
101}
102
103static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
104{
02246a7f
SS		 105 int bar;
106
107 bar = efx->type->mem_bar;
108 return resource_size(&efx->pci_dev->resource[bar]);
8127d661
BH		 109}
110
7a186f47
DP		 111static bool efx_ef10_is_vf(struct efx_nic *efx)
112{
113 return efx->type->is_vf;
114}
115
1cd9ecbb
DP		 116static int efx_ef10_get_pf_index(struct efx_nic *efx)
117{
118 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
119 struct efx_ef10_nic_data *nic_data = efx->nic_data;
120 size_t outlen;
121 int rc;
122
123 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
124 sizeof(outbuf), &outlen);
125 if (rc)
126 return rc;
127 if (outlen < sizeof(outbuf))
128 return -EIO;
129
130 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
131 return 0;
132}
133
88a37de6
SS		 134#ifdef CONFIG_SFC_SRIOV
135static int efx_ef10_get_vf_index(struct efx_nic *efx)
136{
137 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
138 struct efx_ef10_nic_data *nic_data = efx->nic_data;
139 size_t outlen;
140 int rc;
141
142 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
143 sizeof(outbuf), &outlen);
144 if (rc)
145 return rc;
146 if (outlen < sizeof(outbuf))
147 return -EIO;
148
149 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
150 return 0;
151}
152#endif
153
e5a2538a 154static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
8127d661
BH		 155{
156 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);
157 struct efx_ef10_nic_data *nic_data = efx->nic_data;
158 size_t outlen;
159 int rc;
160
161 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
162
163 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
164 outbuf, sizeof(outbuf), &outlen);
165 if (rc)
166 return rc;
e5a2538a
BH		 167 if (outlen < sizeof(outbuf)) {
168 netif_err(efx, drv, efx->net_dev,
169 "unable to read datapath firmware capabilities\n");
170 return -EIO;
171 }
172
173 nic_data->datapath_caps =
174 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
8127d661 175
8d9f9dd4
DP		 176 /* record the DPCPU firmware IDs to determine VEB vswitching support.
177 */
178 nic_data->rx_dpcpu_fw_id =
179 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
180 nic_data->tx_dpcpu_fw_id =
181 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
182
e5a2538a
BH		 183 if (!(nic_data->datapath_caps &
184 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) {
185 netif_err(efx, drv, efx->net_dev,
186 "current firmware does not support TSO\n");
187 return -ENODEV;
188 }
189
190 if (!(nic_data->datapath_caps &
191 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
192 netif_err(efx, probe, efx->net_dev,
193 "current firmware does not support an RX prefix\n");
194 return -ENODEV;
8127d661
BH		 195 }
196
197 return 0;
198}
199
200static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
201{
202 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
203 int rc;
204
205 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
206 outbuf, sizeof(outbuf), NULL);
207 if (rc)
208 return rc;
209 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
210 return rc > 0 ? rc : -ERANGE;
211}
212
0d5e0fbb 213static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
8127d661
BH		 214{
215 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
216 size_t outlen;
217 int rc;
218
219 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
220
221 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
222 outbuf, sizeof(outbuf), &outlen);
223 if (rc)
224 return rc;
225 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
226 return -EIO;
227
cd84ff4d
EC		 228 ether_addr_copy(mac_address,
229 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
8127d661
BH		 230 return 0;
231}
232
0d5e0fbb
DP		 233static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
234{
235 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
236 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
237 size_t outlen;
238 int num_addrs, rc;
239
240 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
241 EVB_PORT_ID_ASSIGNED);
242 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
243 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
244
245 if (rc)
246 return rc;
247 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
248 return -EIO;
249
250 num_addrs = MCDI_DWORD(outbuf,
251 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
252
253 WARN_ON(num_addrs != 1);
254
255 ether_addr_copy(mac_address,
256 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
257
258 return 0;
259}
260
0f5c0845
SS		 261static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
262 struct device_attribute *attr,
263 char *buf)
264{
265 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
266
267 return sprintf(buf, "%d\n",
268 ((efx->mcdi->fn_flags) &
269 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
270 ? 1 : 0);
271}
272
273static ssize_t efx_ef10_show_primary_flag(struct device *dev,
274 struct device_attribute *attr,
275 char *buf)
276{
277 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
278
279 return sprintf(buf, "%d\n",
280 ((efx->mcdi->fn_flags) &
281 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
282 ? 1 : 0);
283}
284
285static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
286 NULL);
287static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
288
8127d661
BH		 289static int efx_ef10_probe(struct efx_nic *efx)
290{
291 struct efx_ef10_nic_data *nic_data;
8be41320 292 struct net_device *net_dev = efx->net_dev;
8127d661
BH		 293 int i, rc;
294
aa3930ee
BH		 295 /* We can have one VI for each 8K region. However, until we
296 * use TX option descriptors we need two TX queues per channel.
8127d661
BH		 297 */
298 efx->max_channels =
299 min_t(unsigned int,
300 EFX_MAX_CHANNELS,
02246a7f 301 efx_ef10_mem_map_size(efx) /
8127d661 302 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
9fd3d3a4
EC		 303 if (WARN_ON(efx->max_channels == 0))
304 return -EIO;
8127d661
BH		 305
306 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
307 if (!nic_data)
308 return -ENOMEM;
309 efx->nic_data = nic_data;
310
75aba2a5
EC		 311 /* we assume later that we can copy from this buffer in dwords */
312 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
313
8127d661
BH		 314 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
315 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
316 if (rc)
317 goto fail1;
318
319 /* Get the MC's warm boot count. In case it's rebooting right
320 * now, be prepared to retry.
321 */
322 i = 0;
323 for (;;) {
324 rc = efx_ef10_get_warm_boot_count(efx);
325 if (rc >= 0)
326 break;
327 if (++i == 5)
328 goto fail2;
329 ssleep(1);
330 }
331 nic_data->warm_boot_count = rc;
332
333 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
334
45b2449e
DP		 335 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
336
8127d661
BH		 337 /* In case we're recovering from a crash (kexec), we want to
338 * cancel any outstanding request by the previous user of this
339 * function. We send a special message using the least
340 * significant bits of the 'high' (doorbell) register.
341 */
342 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
343
344 rc = efx_mcdi_init(efx);
345 if (rc)
346 goto fail2;
347
348 /* Reset (most) configuration for this function */
349 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
350 if (rc)
351 goto fail3;
352
353 /* Enable event logging */
354 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
355 if (rc)
356 goto fail3;
357
0f5c0845
SS		 358 rc = device_create_file(&efx->pci_dev->dev,
359 &dev_attr_link_control_flag);
1cd9ecbb
DP		 360 if (rc)
361 goto fail3;
362
0f5c0845
SS		 363 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
364 if (rc)
365 goto fail4;
366
367 rc = efx_ef10_get_pf_index(efx);
368 if (rc)
369 goto fail5;
370
e5a2538a 371 rc = efx_ef10_init_datapath_caps(efx);
8127d661 372 if (rc < 0)
0f5c0845 373 goto fail5;
8127d661
BH		 374
375 efx->rx_packet_len_offset =
376 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
377
8127d661
BH		 378 rc = efx_mcdi_port_get_number(efx);
379 if (rc < 0)
0f5c0845 380 goto fail5;
8127d661 381 efx->port_num = rc;
8be41320 382 net_dev->dev_port = rc;
8127d661 383
0d5e0fbb 384 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
8127d661 385 if (rc)
0f5c0845 386 goto fail5;
8127d661
BH		 387
388 rc = efx_ef10_get_sysclk_freq(efx);
389 if (rc < 0)
0f5c0845 390 goto fail5;
8127d661
BH		 391 efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
392
267d9d73
EC		 393 /* Check whether firmware supports bug 35388 workaround.
394 * First try to enable it, then if we get EPERM, just
395 * ask if it's already enabled
396 */
34ccfe6f 397 rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true, NULL);
c9012e00 398 if (rc == 0) {
8127d661 399 nic_data->workaround_35388 = true;
c9012e00 400 } else if (rc == -EPERM) {
267d9d73
EC		 401 unsigned int enabled;
402
403 rc = efx_mcdi_get_workarounds(efx, NULL, &enabled);
404 if (rc)
405 goto fail3;
406 nic_data->workaround_35388 = enabled &
407 MC_CMD_GET_WORKAROUNDS_OUT_BUG35388;
c9012e00 408 } else if (rc != -ENOSYS && rc != -ENOENT) {
0f5c0845 409 goto fail5;
c9012e00 410 }
8127d661
BH		 411 netif_dbg(efx, probe, efx->net_dev,
412 "workaround for bug 35388 is %sabled\n",
413 nic_data->workaround_35388 ? "en" : "dis");
414
415 rc = efx_mcdi_mon_probe(efx);
267d9d73 416 if (rc && rc != -EPERM)
0f5c0845 417 goto fail5;
8127d661 418
9aecda95
BH		 419 efx_ptp_probe(efx, NULL);
420
1d051e00
SS		 421#ifdef CONFIG_SFC_SRIOV
422 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
423 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
424 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
425
426 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
427 } else
428#endif
429 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
430
8127d661
BH		 431 return 0;
432
0f5c0845
SS		 433fail5:
434 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
435fail4:
436 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
8127d661
BH		 437fail3:
438 efx_mcdi_fini(efx);
439fail2:
440 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
441fail1:
442 kfree(nic_data);
443 efx->nic_data = NULL;
444 return rc;
445}
446
447static int efx_ef10_free_vis(struct efx_nic *efx)
448{
aa09a3da 449 MCDI_DECLARE_BUF_ERR(outbuf);
1e0b8120
EC		 450 size_t outlen;
451 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
452 outbuf, sizeof(outbuf), &outlen);
8127d661
BH		 453
454 /* -EALREADY means nothing to free, so ignore */
455 if (rc == -EALREADY)
456 rc = 0;
1e0b8120
EC		 457 if (rc)
458 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
459 rc);
8127d661
BH		 460 return rc;
461}
462
183233be
BH		 463#ifdef EFX_USE_PIO
464
465static void efx_ef10_free_piobufs(struct efx_nic *efx)
466{
467 struct efx_ef10_nic_data *nic_data = efx->nic_data;
468 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
469 unsigned int i;
470 int rc;
471
472 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
473
474 for (i = 0; i < nic_data->n_piobufs; i++) {
475 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
476 nic_data->piobuf_handle[i]);
477 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
478 NULL, 0, NULL);
479 WARN_ON(rc);
480 }
481
482 nic_data->n_piobufs = 0;
483}
484
485static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
486{
487 struct efx_ef10_nic_data *nic_data = efx->nic_data;
488 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
489 unsigned int i;
490 size_t outlen;
491 int rc = 0;
492
493 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
494
495 for (i = 0; i < n; i++) {
496 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
497 outbuf, sizeof(outbuf), &outlen);
498 if (rc)
499 break;
500 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
501 rc = -EIO;
502 break;
503 }
504 nic_data->piobuf_handle[i] =
505 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
506 netif_dbg(efx, probe, efx->net_dev,
507 "allocated PIO buffer %u handle %x\n", i,
508 nic_data->piobuf_handle[i]);
509 }
510
511 nic_data->n_piobufs = i;
512 if (rc)
513 efx_ef10_free_piobufs(efx);
514 return rc;
515}
516
517static int efx_ef10_link_piobufs(struct efx_nic *efx)
518{
519 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da
JC		 520 _MCDI_DECLARE_BUF(inbuf,
521 max(MC_CMD_LINK_PIOBUF_IN_LEN,
522 MC_CMD_UNLINK_PIOBUF_IN_LEN));
183233be
BH		 523 struct efx_channel *channel;
524 struct efx_tx_queue *tx_queue;
525 unsigned int offset, index;
526 int rc;
527
528 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
529 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
530
aa09a3da
JC		 531 memset(inbuf, 0, sizeof(inbuf));
532
183233be
BH		 533 /* Link a buffer to each VI in the write-combining mapping */
534 for (index = 0; index < nic_data->n_piobufs; ++index) {
535 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
536 nic_data->piobuf_handle[index]);
537 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
538 nic_data->pio_write_vi_base + index);
539 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
540 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
541 NULL, 0, NULL);
542 if (rc) {
543 netif_err(efx, drv, efx->net_dev,
544 "failed to link VI %u to PIO buffer %u (%d)\n",
545 nic_data->pio_write_vi_base + index, index,
546 rc);
547 goto fail;
548 }
549 netif_dbg(efx, probe, efx->net_dev,
550 "linked VI %u to PIO buffer %u\n",
551 nic_data->pio_write_vi_base + index, index);
552 }
553
554 /* Link a buffer to each TX queue */
555 efx_for_each_channel(channel, efx) {
556 efx_for_each_channel_tx_queue(tx_queue, channel) {
557 /* We assign the PIO buffers to queues in
558 * reverse order to allow for the following
559 * special case.
560 */
561 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
562 tx_queue->channel->channel - 1) *
563 efx_piobuf_size);
564 index = offset / ER_DZ_TX_PIOBUF_SIZE;
565 offset = offset % ER_DZ_TX_PIOBUF_SIZE;
566
567 /* When the host page size is 4K, the first
568 * host page in the WC mapping may be within
569 * the same VI page as the last TX queue. We
570 * can only link one buffer to each VI.
571 */
572 if (tx_queue->queue == nic_data->pio_write_vi_base) {
573 BUG_ON(index != 0);
574 rc = 0;
575 } else {
576 MCDI_SET_DWORD(inbuf,
577 LINK_PIOBUF_IN_PIOBUF_HANDLE,
578 nic_data->piobuf_handle[index]);
579 MCDI_SET_DWORD(inbuf,
580 LINK_PIOBUF_IN_TXQ_INSTANCE,
581 tx_queue->queue);
582 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
583 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
584 NULL, 0, NULL);
585 }
586
587 if (rc) {
588 /* This is non-fatal; the TX path just
589 * won't use PIO for this queue
590 */
591 netif_err(efx, drv, efx->net_dev,
592 "failed to link VI %u to PIO buffer %u (%d)\n",
593 tx_queue->queue, index, rc);
594 tx_queue->piobuf = NULL;
595 } else {
596 tx_queue->piobuf =
597 nic_data->pio_write_base +
598 index * EFX_VI_PAGE_SIZE + offset;
599 tx_queue->piobuf_offset = offset;
600 netif_dbg(efx, probe, efx->net_dev,
601 "linked VI %u to PIO buffer %u offset %x addr %p\n",
602 tx_queue->queue, index,
603 tx_queue->piobuf_offset,
604 tx_queue->piobuf);
605 }
606 }
607 }
608
609 return 0;
610
611fail:
612 while (index--) {
613 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
614 nic_data->pio_write_vi_base + index);
615 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
616 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
617 NULL, 0, NULL);
618 }
619 return rc;
620}
621
622#else /* !EFX_USE_PIO */
623
624static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
625{
626 return n == 0 ? 0 : -ENOBUFS;
627}
628
629static int efx_ef10_link_piobufs(struct efx_nic *efx)
630{
631 return 0;
632}
633
634static void efx_ef10_free_piobufs(struct efx_nic *efx)
635{
636}
637
638#endif /* EFX_USE_PIO */
639
8127d661
BH		 640static void efx_ef10_remove(struct efx_nic *efx)
641{
642 struct efx_ef10_nic_data *nic_data = efx->nic_data;
643 int rc;
644
f1122a34
SS		 645#ifdef CONFIG_SFC_SRIOV
646 struct efx_ef10_nic_data *nic_data_pf;
647 struct pci_dev *pci_dev_pf;
648 struct efx_nic *efx_pf;
649 struct ef10_vf *vf;
650
651 if (efx->pci_dev->is_virtfn) {
652 pci_dev_pf = efx->pci_dev->physfn;
653 if (pci_dev_pf) {
654 efx_pf = pci_get_drvdata(pci_dev_pf);
655 nic_data_pf = efx_pf->nic_data;
656 vf = nic_data_pf->vf + nic_data->vf_index;
657 vf->efx = NULL;
658 } else
659 netif_info(efx, drv, efx->net_dev,
660 "Could not get the PF id from VF\n");
661 }
662#endif
663
9aecda95
BH		 664 efx_ptp_remove(efx);
665
8127d661
BH		 666 efx_mcdi_mon_remove(efx);
667
8127d661
BH		 668 efx_ef10_rx_free_indir_table(efx);
669
183233be
BH		 670 if (nic_data->wc_membase)
671 iounmap(nic_data->wc_membase);
672
8127d661
BH		 673 rc = efx_ef10_free_vis(efx);
674 WARN_ON(rc != 0);
675
183233be
BH		 676 if (!nic_data->must_restore_piobufs)
677 efx_ef10_free_piobufs(efx);
678
0f5c0845
SS		 679 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
680 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
681
8127d661
BH		 682 efx_mcdi_fini(efx);
683 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
684 kfree(nic_data);
685}
686
88a37de6
SS		 687static int efx_ef10_probe_pf(struct efx_nic *efx)
688{
689 return efx_ef10_probe(efx);
690}
691
7a186f47
DP		 692int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
693{
694 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
695
696 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
697 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
698 NULL, 0, NULL);
699}
700
701int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
702{
703 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
704
705 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
706 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
707 NULL, 0, NULL);
708}
709
710int efx_ef10_vport_add_mac(struct efx_nic *efx,
711 unsigned int port_id, u8 *mac)
712{
713 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
714
715 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
716 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
717
718 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
719 sizeof(inbuf), NULL, 0, NULL);
720}
721
722int efx_ef10_vport_del_mac(struct efx_nic *efx,
723 unsigned int port_id, u8 *mac)
724{
725 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
726
727 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
728 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
729
730 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
731 sizeof(inbuf), NULL, 0, NULL);
732}
733
88a37de6
SS		 734#ifdef CONFIG_SFC_SRIOV
735static int efx_ef10_probe_vf(struct efx_nic *efx)
736{
737 int rc;
6598dad2
DP		 738 struct pci_dev *pci_dev_pf;
739
740 /* If the parent PF has no VF data structure, it doesn't know about this
741 * VF so fail probe. The VF needs to be re-created. This can happen
742 * if the PF driver is unloaded while the VF is assigned to a guest.
743 */
744 pci_dev_pf = efx->pci_dev->physfn;
745 if (pci_dev_pf) {
746 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
747 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
748
749 if (!nic_data_pf->vf) {
750 netif_info(efx, drv, efx->net_dev,
751 "The VF cannot link to its parent PF; "
752 "please destroy and re-create the VF\n");
753 return -EBUSY;
754 }
755 }
88a37de6
SS		 756
757 rc = efx_ef10_probe(efx);
758 if (rc)
759 return rc;
760
761 rc = efx_ef10_get_vf_index(efx);
762 if (rc)
763 goto fail;
764
f1122a34
SS		 765 if (efx->pci_dev->is_virtfn) {
766 if (efx->pci_dev->physfn) {
767 struct efx_nic *efx_pf =
768 pci_get_drvdata(efx->pci_dev->physfn);
769 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
770 struct efx_ef10_nic_data *nic_data = efx->nic_data;
771
772 nic_data_p->vf[nic_data->vf_index].efx = efx;
6598dad2
DP		 773 nic_data_p->vf[nic_data->vf_index].pci_dev =
774 efx->pci_dev;
f1122a34
SS		 775 } else
776 netif_info(efx, drv, efx->net_dev,
777 "Could not get the PF id from VF\n");
778 }
779
88a37de6
SS		 780 return 0;
781
782fail:
783 efx_ef10_remove(efx);
784 return rc;
785}
786#else
787static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
788{
789 return 0;
790}
791#endif
792
8127d661
BH		 793static int efx_ef10_alloc_vis(struct efx_nic *efx,
794 unsigned int min_vis, unsigned int max_vis)
795{
796 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
797 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
798 struct efx_ef10_nic_data *nic_data = efx->nic_data;
799 size_t outlen;
800 int rc;
801
802 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
803 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
804 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
805 outbuf, sizeof(outbuf), &outlen);
806 if (rc != 0)
807 return rc;
808
809 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
810 return -EIO;
811
812 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
813 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
814
815 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
816 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
817 return 0;
818}
819
183233be
BH		 820/* Note that the failure path of this function does not free
821 * resources, as this will be done by efx_ef10_remove().
822 */
8127d661
BH		 823static int efx_ef10_dimension_resources(struct efx_nic *efx)
824{
183233be
BH		 825 struct efx_ef10_nic_data *nic_data = efx->nic_data;
826 unsigned int uc_mem_map_size, wc_mem_map_size;
827 unsigned int min_vis, pio_write_vi_base, max_vis;
828 void __iomem *membase;
829 int rc;
830
831 min_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
8127d661 832
183233be
BH		 833#ifdef EFX_USE_PIO
834 /* Try to allocate PIO buffers if wanted and if the full
835 * number of PIO buffers would be sufficient to allocate one
836 * copy-buffer per TX channel. Failure is non-fatal, as there
837 * are only a small number of PIO buffers shared between all
838 * functions of the controller.
839 */
840 if (efx_piobuf_size != 0 &&
841 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
842 efx->n_tx_channels) {
843 unsigned int n_piobufs =
844 DIV_ROUND_UP(efx->n_tx_channels,
845 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
846
847 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
848 if (rc)
849 netif_err(efx, probe, efx->net_dev,
850 "failed to allocate PIO buffers (%d)\n", rc);
851 else
852 netif_dbg(efx, probe, efx->net_dev,
853 "allocated %u PIO buffers\n", n_piobufs);
854 }
855#else
856 nic_data->n_piobufs = 0;
857#endif
858
859 /* PIO buffers should be mapped with write-combining enabled,
860 * and we want to make single UC and WC mappings rather than
861 * several of each (in fact that's the only option if host
862 * page size is >4K). So we may allocate some extra VIs just
863 * for writing PIO buffers through.
52ad762b
DP		 864 *
865 * The UC mapping contains (min_vis - 1) complete VIs and the
866 * first half of the next VI. Then the WC mapping begins with
867 * the second half of this last VI.
183233be
BH		 868 */
869 uc_mem_map_size = PAGE_ALIGN((min_vis - 1) * EFX_VI_PAGE_SIZE +
870 ER_DZ_TX_PIOBUF);
871 if (nic_data->n_piobufs) {
52ad762b
DP		 872 /* pio_write_vi_base rounds down to give the number of complete
873 * VIs inside the UC mapping.
874 */
183233be
BH		 875 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
876 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
877 nic_data->n_piobufs) *
878 EFX_VI_PAGE_SIZE) -
879 uc_mem_map_size);
880 max_vis = pio_write_vi_base + nic_data->n_piobufs;
881 } else {
882 pio_write_vi_base = 0;
883 wc_mem_map_size = 0;
884 max_vis = min_vis;
885 }
886
887 /* In case the last attached driver failed to free VIs, do it now */
888 rc = efx_ef10_free_vis(efx);
889 if (rc != 0)
890 return rc;
891
892 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
893 if (rc != 0)
894 return rc;
895
896 /* If we didn't get enough VIs to map all the PIO buffers, free the
897 * PIO buffers
898 */
899 if (nic_data->n_piobufs &&
900 nic_data->n_allocated_vis <
901 pio_write_vi_base + nic_data->n_piobufs) {
902 netif_dbg(efx, probe, efx->net_dev,
903 "%u VIs are not sufficient to map %u PIO buffers\n",
904 nic_data->n_allocated_vis, nic_data->n_piobufs);
905 efx_ef10_free_piobufs(efx);
906 }
907
908 /* Shrink the original UC mapping of the memory BAR */
909 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
910 if (!membase) {
911 netif_err(efx, probe, efx->net_dev,
912 "could not shrink memory BAR to %x\n",
913 uc_mem_map_size);
914 return -ENOMEM;
915 }
916 iounmap(efx->membase);
917 efx->membase = membase;
918
919 /* Set up the WC mapping if needed */
920 if (wc_mem_map_size) {
921 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
922 uc_mem_map_size,
923 wc_mem_map_size);
924 if (!nic_data->wc_membase) {
925 netif_err(efx, probe, efx->net_dev,
926 "could not allocate WC mapping of size %x\n",
927 wc_mem_map_size);
928 return -ENOMEM;
929 }
930 nic_data->pio_write_vi_base = pio_write_vi_base;
931 nic_data->pio_write_base =
932 nic_data->wc_membase +
933 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
934 uc_mem_map_size);
935
936 rc = efx_ef10_link_piobufs(efx);
937 if (rc)
938 efx_ef10_free_piobufs(efx);
939 }
940
941 netif_dbg(efx, probe, efx->net_dev,
942 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
943 &efx->membase_phys, efx->membase, uc_mem_map_size,
944 nic_data->wc_membase, wc_mem_map_size);
945
946 return 0;
8127d661
BH		 947}
948
949static int efx_ef10_init_nic(struct efx_nic *efx)
950{
951 struct efx_ef10_nic_data *nic_data = efx->nic_data;
952 int rc;
953
a915ccc9
BH		 954 if (nic_data->must_check_datapath_caps) {
955 rc = efx_ef10_init_datapath_caps(efx);
956 if (rc)
957 return rc;
958 nic_data->must_check_datapath_caps = false;
959 }
960
8127d661
BH		 961 if (nic_data->must_realloc_vis) {
962 /* We cannot let the number of VIs change now */
963 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
964 nic_data->n_allocated_vis);
965 if (rc)
966 return rc;
967 nic_data->must_realloc_vis = false;
968 }
969
183233be
BH		 970 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
971 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
972 if (rc == 0) {
973 rc = efx_ef10_link_piobufs(efx);
974 if (rc)
975 efx_ef10_free_piobufs(efx);
976 }
977
978 /* Log an error on failure, but this is non-fatal */
979 if (rc)
980 netif_err(efx, drv, efx->net_dev,
981 "failed to restore PIO buffers (%d)\n", rc);
982 nic_data->must_restore_piobufs = false;
983 }
984
267c0157
JC		 985 /* don't fail init if RSS setup doesn't work */
986 efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table);
987
8127d661
BH		 988 return 0;
989}
990
3e336261
JC		 991static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
992{
993 struct efx_ef10_nic_data *nic_data = efx->nic_data;
994
995 /* All our allocations have been reset */
996 nic_data->must_realloc_vis = true;
997 nic_data->must_restore_filters = true;
998 nic_data->must_restore_piobufs = true;
999 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1000}
1001
087e9025
JC		 1002static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1003{
1004 if (reason == RESET_TYPE_MC_FAILURE)
1005 return RESET_TYPE_DATAPATH;
1006
1007 return efx_mcdi_map_reset_reason(reason);
1008}
1009
8127d661
BH		 1010static int efx_ef10_map_reset_flags(u32 *flags)
1011{
1012 enum {
1013 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1014 ETH_RESET_SHARED_SHIFT),
1015 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1016 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1017 ETH_RESET_PHY | ETH_RESET_MGMT) <<
1018 ETH_RESET_SHARED_SHIFT)
1019 };
1020
1021 /* We assume for now that our PCI function is permitted to
1022 * reset everything.
1023 */
1024
1025 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1026 *flags &= ~EF10_RESET_MC;
1027 return RESET_TYPE_WORLD;
1028 }
1029
1030 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1031 *flags &= ~EF10_RESET_PORT;
1032 return RESET_TYPE_ALL;
1033 }
1034
1035 /* no invisible reset implemented */
1036
1037 return -EINVAL;
1038}
1039
3e336261
JC		 1040static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1041{
1042 int rc = efx_mcdi_reset(efx, reset_type);
1043
1044 /* If it was a port reset, trigger reallocation of MC resources.
1045 * Note that on an MC reset nothing needs to be done now because we'll
1046 * detect the MC reset later and handle it then.
e283546c
EC		 1047 * For an FLR, we never get an MC reset event, but the MC has reset all
1048 * resources assigned to us, so we have to trigger reallocation now.
3e336261 1049 */
e283546c
EC		 1050 if ((reset_type == RESET_TYPE_ALL ||
1051 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
3e336261
JC		 1052 efx_ef10_reset_mc_allocations(efx);
1053 return rc;
1054}
1055
8127d661
BH		 1056#define EF10_DMA_STAT(ext_name, mcdi_name) \
1057 [EF10_STAT_ ## ext_name] = \
1058 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1059#define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1060 [EF10_STAT_ ## int_name] = \
1061 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1062#define EF10_OTHER_STAT(ext_name) \
1063 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
e4d112e4
EC		 1064#define GENERIC_SW_STAT(ext_name) \
1065 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
8127d661
BH		 1066
1067static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
e80ca013
DP		 1068 EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1069 EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1070 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1071 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1072 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1073 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1074 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1075 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1076 EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1077 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1078 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1079 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1080 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1081 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1082 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1083 EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1084 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1085 EF10_OTHER_STAT(port_rx_good_bytes),
1086 EF10_OTHER_STAT(port_rx_bad_bytes),
1087 EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1088 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1089 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1090 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1091 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1092 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1093 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1094 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1095 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1096 EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1097 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1098 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1099 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1100 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1101 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1102 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1103 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1104 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1105 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1106 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1107 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1108 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
e4d112e4
EC		 1109 GENERIC_SW_STAT(rx_nodesc_trunc),
1110 GENERIC_SW_STAT(rx_noskb_drops),
e80ca013
DP		 1111 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1112 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1113 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1114 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1115 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1116 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1117 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1118 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1119 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1120 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1121 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1122 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
3c36a2ad
DP		 1123 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1124 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1125 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1126 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1127 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1128 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1129 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1130 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1131 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1132 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1133 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1134 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1135 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1136 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1137 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1138 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1139 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1140 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
8127d661
BH		 1141};
1142
e80ca013
DP		 1143#define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1144 (1ULL << EF10_STAT_port_tx_packets) | \
1145 (1ULL << EF10_STAT_port_tx_pause) | \
1146 (1ULL << EF10_STAT_port_tx_unicast) | \
1147 (1ULL << EF10_STAT_port_tx_multicast) | \
1148 (1ULL << EF10_STAT_port_tx_broadcast) | \
1149 (1ULL << EF10_STAT_port_rx_bytes) | \
1150 (1ULL << \
1151 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1152 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1153 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1154 (1ULL << EF10_STAT_port_rx_packets) | \
1155 (1ULL << EF10_STAT_port_rx_good) | \
1156 (1ULL << EF10_STAT_port_rx_bad) | \
1157 (1ULL << EF10_STAT_port_rx_pause) | \
1158 (1ULL << EF10_STAT_port_rx_control) | \
1159 (1ULL << EF10_STAT_port_rx_unicast) | \
1160 (1ULL << EF10_STAT_port_rx_multicast) | \
1161 (1ULL << EF10_STAT_port_rx_broadcast) | \
1162 (1ULL << EF10_STAT_port_rx_lt64) | \
1163 (1ULL << EF10_STAT_port_rx_64) | \
1164 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1165 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1166 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1167 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1168 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1169 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1170 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1171 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1172 (1ULL << EF10_STAT_port_rx_overflow) | \
1173 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
e4d112e4
EC		 1174 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1175 (1ULL << GENERIC_STAT_rx_noskb_drops))
8127d661
BH		 1176
1177/* These statistics are only provided by the 10G MAC. For a 10G/40G
1178 * switchable port we do not expose these because they might not
1179 * include all the packets they should.
1180 */
e80ca013
DP		 1181#define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1182 (1ULL << EF10_STAT_port_tx_lt64) | \
1183 (1ULL << EF10_STAT_port_tx_64) | \
1184 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1185 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1186 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1187 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1188 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1189 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
8127d661
BH		 1190
1191/* These statistics are only provided by the 40G MAC. For a 10G/40G
1192 * switchable port we do expose these because the errors will otherwise
1193 * be silent.
1194 */
e80ca013
DP		 1195#define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1196 (1ULL << EF10_STAT_port_rx_length_error))
8127d661 1197
568d7a00
EC		 1198/* These statistics are only provided if the firmware supports the
1199 * capability PM_AND_RXDP_COUNTERS.
1200 */
1201#define HUNT_PM_AND_RXDP_STAT_MASK ( \
e80ca013
DP		 1202 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1203 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1204 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1205 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1206 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1207 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1208 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1209 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1210 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1211 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1212 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1213 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
568d7a00 1214
4bae913b 1215static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
8127d661 1216{
4bae913b 1217 u64 raw_mask = HUNT_COMMON_STAT_MASK;
8127d661 1218 u32 port_caps = efx_mcdi_phy_get_caps(efx);
568d7a00 1219 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661 1220
3c36a2ad
DP		 1221 if (!(efx->mcdi->fn_flags &
1222 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1223 return 0;
1224
8127d661 1225 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
4bae913b 1226 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
8127d661 1227 else
4bae913b 1228 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
568d7a00
EC		 1229
1230 if (nic_data->datapath_caps &
1231 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1232 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1233
4bae913b
EC		 1234 return raw_mask;
1235}
1236
1237static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1238{
d94619cd 1239 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3c36a2ad
DP		 1240 u64 raw_mask[2];
1241
1242 raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1243
d94619cd
DP		 1244 /* Only show vadaptor stats when EVB capability is present */
1245 if (nic_data->datapath_caps &
1246 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1247 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1248 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
1249 } else {
1250 raw_mask[1] = 0;
1251 }
4bae913b
EC		 1252
1253#if BITS_PER_LONG == 64
3c36a2ad
DP		 1254 mask[0] = raw_mask[0];
1255 mask[1] = raw_mask[1];
4bae913b 1256#else
3c36a2ad
DP		 1257 mask[0] = raw_mask[0] & 0xffffffff;
1258 mask[1] = raw_mask[0] >> 32;
1259 mask[2] = raw_mask[1] & 0xffffffff;
1260 mask[3] = raw_mask[1] >> 32;
4bae913b 1261#endif
8127d661
BH		 1262}
1263
1264static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1265{
4bae913b
EC		 1266 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1267
1268 efx_ef10_get_stat_mask(efx, mask);
8127d661 1269 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
4bae913b 1270 mask, names);
8127d661
BH		 1271}
1272
d7788196
DP		 1273static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1274 struct rtnl_link_stats64 *core_stats)
1275{
1276 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1277 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1278 u64 *stats = nic_data->stats;
1279 size_t stats_count = 0, index;
1280
1281 efx_ef10_get_stat_mask(efx, mask);
1282
1283 if (full_stats) {
1284 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1285 if (efx_ef10_stat_desc[index].name) {
1286 *full_stats++ = stats[index];
1287 ++stats_count;
1288 }
1289 }
1290 }
1291
1292 if (core_stats) {
0fc95fca
DP		 1293 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1294 stats[EF10_STAT_rx_multicast] +
1295 stats[EF10_STAT_rx_broadcast];
1296 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1297 stats[EF10_STAT_tx_multicast] +
1298 stats[EF10_STAT_tx_broadcast];
1299 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1300 stats[EF10_STAT_rx_multicast_bytes] +
1301 stats[EF10_STAT_rx_broadcast_bytes];
1302 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1303 stats[EF10_STAT_tx_multicast_bytes] +
1304 stats[EF10_STAT_tx_broadcast_bytes];
1305 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
d7788196 1306 stats[GENERIC_STAT_rx_noskb_drops];
0fc95fca
DP		 1307 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1308 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1309 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1310 core_stats->rx_errors = core_stats->rx_crc_errors;
1311 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
d7788196
DP		 1312 }
1313
1314 return stats_count;
1315}
1316
1317static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
8127d661
BH		 1318{
1319 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4bae913b 1320 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
8127d661
BH		 1321 __le64 generation_start, generation_end;
1322 u64 *stats = nic_data->stats;
1323 __le64 *dma_stats;
1324
4bae913b
EC		 1325 efx_ef10_get_stat_mask(efx, mask);
1326
8127d661
BH		 1327 dma_stats = efx->stats_buffer.addr;
1328 nic_data = efx->nic_data;
1329
1330 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1331 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1332 return 0;
1333 rmb();
4bae913b 1334 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
8127d661 1335 stats, efx->stats_buffer.addr, false);
d546a893 1336 rmb();
8127d661
BH		 1337 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1338 if (generation_end != generation_start)
1339 return -EAGAIN;
1340
1341 /* Update derived statistics */
e80ca013
DP		 1342 efx_nic_fix_nodesc_drop_stat(efx,
1343 &stats[EF10_STAT_port_rx_nodesc_drops]);
1344 stats[EF10_STAT_port_rx_good_bytes] =
1345 stats[EF10_STAT_port_rx_bytes] -
1346 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1347 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1348 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
e4d112e4 1349 efx_update_sw_stats(efx, stats);
8127d661
BH		 1350 return 0;
1351}
1352
1353
d7788196
DP		 1354static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1355 struct rtnl_link_stats64 *core_stats)
8127d661 1356{
8127d661
BH		 1357 int retry;
1358
1359 /* If we're unlucky enough to read statistics during the DMA, wait
1360 * up to 10ms for it to finish (typically takes <500us)
1361 */
1362 for (retry = 0; retry < 100; ++retry) {
d7788196 1363 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
8127d661
BH		 1364 break;
1365 udelay(100);
1366 }
1367
d7788196
DP		 1368 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1369}
8127d661 1370
d7788196
DP		 1371static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1372{
1373 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1374 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1375 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1376 __le64 generation_start, generation_end;
1377 u64 *stats = nic_data->stats;
1378 u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64);
1379 struct efx_buffer stats_buf;
1380 __le64 *dma_stats;
1381 int rc;
1382
f00bf230
DP		 1383 spin_unlock_bh(&efx->stats_lock);
1384
1385 if (in_interrupt()) {
1386 /* If in atomic context, cannot update stats. Just update the
1387 * software stats and return so the caller can continue.
1388 */
1389 spin_lock_bh(&efx->stats_lock);
1390 efx_update_sw_stats(efx, stats);
1391 return 0;
1392 }
1393
d7788196
DP		 1394 efx_ef10_get_stat_mask(efx, mask);
1395
1396 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
f00bf230
DP		 1397 if (rc) {
1398 spin_lock_bh(&efx->stats_lock);
d7788196 1399 return rc;
f00bf230 1400 }
d7788196
DP		 1401
1402 dma_stats = stats_buf.addr;
1403 dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID;
1404
1405 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1406 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
0fc95fca 1407 MAC_STATS_IN_DMA, 1);
d7788196
DP		 1408 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1409 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1410
6dd4859b
DP		 1411 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1412 NULL, 0, NULL);
d7788196 1413 spin_lock_bh(&efx->stats_lock);
6dd4859b
DP		 1414 if (rc) {
1415 /* Expect ENOENT if DMA queues have not been set up */
1416 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1417 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1418 sizeof(inbuf), NULL, 0, rc);
d7788196 1419 goto out;
6dd4859b 1420 }
d7788196
DP		 1421
1422 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
0fc95fca
DP		 1423 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1424 WARN_ON_ONCE(1);
d7788196 1425 goto out;
0fc95fca 1426 }
d7788196
DP		 1427 rmb();
1428 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1429 stats, stats_buf.addr, false);
1430 rmb();
1431 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1432 if (generation_end != generation_start) {
1433 rc = -EAGAIN;
1434 goto out;
8127d661
BH		 1435 }
1436
d7788196
DP		 1437 efx_update_sw_stats(efx, stats);
1438out:
1439 efx_nic_free_buffer(efx, &stats_buf);
1440 return rc;
1441}
1442
1443static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1444 struct rtnl_link_stats64 *core_stats)
1445{
1446 if (efx_ef10_try_update_nic_stats_vf(efx))
1447 return 0;
1448
1449 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
8127d661
BH		 1450}
1451
1452static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1453{
1454 struct efx_nic *efx = channel->efx;
1455 unsigned int mode, value;
1456 efx_dword_t timer_cmd;
1457
1458 if (channel->irq_moderation) {
1459 mode = 3;
1460 value = channel->irq_moderation - 1;
1461 } else {
1462 mode = 0;
1463 value = 0;
1464 }
1465
1466 if (EFX_EF10_WORKAROUND_35388(efx)) {
1467 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1468 EFE_DD_EVQ_IND_TIMER_FLAGS,
1469 ERF_DD_EVQ_IND_TIMER_MODE, mode,
1470 ERF_DD_EVQ_IND_TIMER_VAL, value);
1471 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1472 channel->channel);
1473 } else {
1474 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1475 ERF_DZ_TC_TIMER_VAL, value);
1476 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1477 channel->channel);
1478 }
1479}
1480
02246a7f
SS		 1481static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1482 struct ethtool_wolinfo *wol) {}
1483
1484static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1485{
1486 return -EOPNOTSUPP;
1487}
1488
8127d661
BH		 1489static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1490{
1491 wol->supported = 0;
1492 wol->wolopts = 0;
1493 memset(&wol->sopass, 0, sizeof(wol->sopass));
1494}
1495
1496static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1497{
1498 if (type != 0)
1499 return -EINVAL;
1500 return 0;
1501}
1502
1503static void efx_ef10_mcdi_request(struct efx_nic *efx,
1504 const efx_dword_t *hdr, size_t hdr_len,
1505 const efx_dword_t *sdu, size_t sdu_len)
1506{
1507 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1508 u8 *pdu = nic_data->mcdi_buf.addr;
1509
1510 memcpy(pdu, hdr, hdr_len);
1511 memcpy(pdu + hdr_len, sdu, sdu_len);
1512 wmb();
1513
1514 /* The hardware provides 'low' and 'high' (doorbell) registers
1515 * for passing the 64-bit address of an MCDI request to
1516 * firmware. However the dwords are swapped by firmware. The
1517 * least significant bits of the doorbell are then 0 for all
1518 * MCDI requests due to alignment.
1519 */
1520 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1521 ER_DZ_MC_DB_LWRD);
1522 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1523 ER_DZ_MC_DB_HWRD);
1524}
1525
1526static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1527{
1528 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1529 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1530
1531 rmb();
1532 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1533}
1534
1535static void
1536efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1537 size_t offset, size_t outlen)
1538{
1539 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1540 const u8 *pdu = nic_data->mcdi_buf.addr;
1541
1542 memcpy(outbuf, pdu + offset, outlen);
1543}
1544
1545static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1546{
1547 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1548 int rc;
1549
1550 rc = efx_ef10_get_warm_boot_count(efx);
1551 if (rc < 0) {
1552 /* The firmware is presumably in the process of
1553 * rebooting. However, we are supposed to report each
1554 * reboot just once, so we must only do that once we
1555 * can read and store the updated warm boot count.
1556 */
1557 return 0;
1558 }
1559
1560 if (rc == nic_data->warm_boot_count)
1561 return 0;
1562
1563 nic_data->warm_boot_count = rc;
1564
1565 /* All our allocations have been reset */
3e336261 1566 efx_ef10_reset_mc_allocations(efx);
8127d661 1567
6d8aaaf6
DP		 1568 /* Driver-created vswitches and vports must be re-created */
1569 nic_data->must_probe_vswitching = true;
1570 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1571
a915ccc9
BH		 1572 /* The datapath firmware might have been changed */
1573 nic_data->must_check_datapath_caps = true;
1574
869070c5
BH		 1575 /* MAC statistics have been cleared on the NIC; clear the local
1576 * statistic that we update with efx_update_diff_stat().
1577 */
e80ca013 1578 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
869070c5 1579
8127d661
BH		 1580 return -EIO;
1581}
1582
1583/* Handle an MSI interrupt
1584 *
1585 * Handle an MSI hardware interrupt. This routine schedules event
1586 * queue processing. No interrupt acknowledgement cycle is necessary.
1587 * Also, we never need to check that the interrupt is for us, since
1588 * MSI interrupts cannot be shared.
1589 */
1590static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
1591{
1592 struct efx_msi_context *context = dev_id;
1593 struct efx_nic *efx = context->efx;
1594
1595 netif_vdbg(efx, intr, efx->net_dev,
1596 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
1597
1598 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
1599 /* Note test interrupts */
1600 if (context->index == efx->irq_level)
1601 efx->last_irq_cpu = raw_smp_processor_id();
1602
1603 /* Schedule processing of the channel */
1604 efx_schedule_channel_irq(efx->channel[context->index]);
1605 }
1606
1607 return IRQ_HANDLED;
1608}
1609
1610static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
1611{
1612 struct efx_nic *efx = dev_id;
1613 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1614 struct efx_channel *channel;
1615 efx_dword_t reg;
1616 u32 queues;
1617
1618 /* Read the ISR which also ACKs the interrupts */
1619 efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
1620 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
1621
1622 if (queues == 0)
1623 return IRQ_NONE;
1624
1625 if (likely(soft_enabled)) {
1626 /* Note test interrupts */
1627 if (queues & (1U << efx->irq_level))
1628 efx->last_irq_cpu = raw_smp_processor_id();
1629
1630 efx_for_each_channel(channel, efx) {
1631 if (queues & 1)
1632 efx_schedule_channel_irq(channel);
1633 queues >>= 1;
1634 }
1635 }
1636
1637 netif_vdbg(efx, intr, efx->net_dev,
1638 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1639 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1640
1641 return IRQ_HANDLED;
1642}
1643
1644static void efx_ef10_irq_test_generate(struct efx_nic *efx)
1645{
1646 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
1647
1648 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
1649
1650 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
1651 (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
1652 inbuf, sizeof(inbuf), NULL, 0, NULL);
1653}
1654
1655static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
1656{
1657 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
1658 (tx_queue->ptr_mask + 1) *
1659 sizeof(efx_qword_t),
1660 GFP_KERNEL);
1661}
1662
1663/* This writes to the TX_DESC_WPTR and also pushes data */
1664static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
1665 const efx_qword_t *txd)
1666{
1667 unsigned int write_ptr;
1668 efx_oword_t reg;
1669
1670 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1671 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
1672 reg.qword[0] = *txd;
1673 efx_writeo_page(tx_queue->efx, &reg,
1674 ER_DZ_TX_DESC_UPD, tx_queue->queue);
1675}
1676
1677static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
1678{
1679 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1680 EFX_BUF_SIZE));
8127d661
BH		 1681 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
1682 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
1683 struct efx_channel *channel = tx_queue->channel;
1684 struct efx_nic *efx = tx_queue->efx;
45b2449e 1685 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da 1686 size_t inlen;
8127d661
BH		 1687 dma_addr_t dma_addr;
1688 efx_qword_t *txd;
1689 int rc;
1690 int i;
aa09a3da 1691 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
8127d661
BH		 1692
1693 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
1694 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
1695 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
1696 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
1697 MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
1698 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
1699 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
1700 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
45b2449e 1701 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 1702
1703 dma_addr = tx_queue->txd.buf.dma_addr;
1704
1705 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
1706 tx_queue->queue, entries, (u64)dma_addr);
1707
1708 for (i = 0; i < entries; ++i) {
1709 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
1710 dma_addr += EFX_BUF_SIZE;
1711 }
1712
1713 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
1714
1715 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
aa09a3da 1716 NULL, 0, NULL);
8127d661
BH		 1717 if (rc)
1718 goto fail;
1719
1720 /* A previous user of this TX queue might have set us up the
1721 * bomb by writing a descriptor to the TX push collector but
1722 * not the doorbell. (Each collector belongs to a port, not a
1723 * queue or function, so cannot easily be reset.) We must
1724 * attempt to push a no-op descriptor in its place.
1725 */
1726 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
1727 tx_queue->insert_count = 1;
1728 txd = efx_tx_desc(tx_queue, 0);
1729 EFX_POPULATE_QWORD_4(*txd,
1730 ESF_DZ_TX_DESC_IS_OPT, true,
1731 ESF_DZ_TX_OPTION_TYPE,
1732 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
1733 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
1734 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
1735 tx_queue->write_count = 1;
1736 wmb();
1737 efx_ef10_push_tx_desc(tx_queue, txd);
1738
1739 return;
1740
1741fail:
48ce5634
BH		 1742 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
1743 tx_queue->queue);
8127d661
BH		 1744}
1745
1746static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
1747{
1748 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
aa09a3da 1749 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 1750 struct efx_nic *efx = tx_queue->efx;
1751 size_t outlen;
1752 int rc;
1753
1754 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
1755 tx_queue->queue);
1756
1e0b8120 1757 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
8127d661
BH		 1758 outbuf, sizeof(outbuf), &outlen);
1759
1760 if (rc && rc != -EALREADY)
1761 goto fail;
1762
1763 return;
1764
1765fail:
1e0b8120
EC		 1766 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
1767 outbuf, outlen, rc);
8127d661
BH		 1768}
1769
1770static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
1771{
1772 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
1773}
1774
1775/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
1776static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
1777{
1778 unsigned int write_ptr;
1779 efx_dword_t reg;
1780
1781 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1782 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
1783 efx_writed_page(tx_queue->efx, &reg,
1784 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
1785}
1786
1787static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
1788{
1789 unsigned int old_write_count = tx_queue->write_count;
1790 struct efx_tx_buffer *buffer;
1791 unsigned int write_ptr;
1792 efx_qword_t *txd;
1793
1794 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
1795
1796 do {
1797 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1798 buffer = &tx_queue->buffer[write_ptr];
1799 txd = efx_tx_desc(tx_queue, write_ptr);
1800 ++tx_queue->write_count;
1801
1802 /* Create TX descriptor ring entry */
1803 if (buffer->flags & EFX_TX_BUF_OPTION) {
1804 *txd = buffer->option;
1805 } else {
1806 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
1807 EFX_POPULATE_QWORD_3(
1808 *txd,
1809 ESF_DZ_TX_KER_CONT,
1810 buffer->flags & EFX_TX_BUF_CONT,
1811 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
1812 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
1813 }
1814 } while (tx_queue->write_count != tx_queue->insert_count);
1815
1816 wmb(); /* Ensure descriptors are written before they are fetched */
1817
1818 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
1819 txd = efx_tx_desc(tx_queue,
1820 old_write_count & tx_queue->ptr_mask);
1821 efx_ef10_push_tx_desc(tx_queue, txd);
1822 ++tx_queue->pushes;
1823 } else {
1824 efx_ef10_notify_tx_desc(tx_queue);
1825 }
1826}
1827
267c0157
JC		 1828static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
1829 bool exclusive, unsigned *context_size)
8127d661
BH		 1830{
1831 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
1832 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
45b2449e 1833 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661
BH		 1834 size_t outlen;
1835 int rc;
267c0157
JC		 1836 u32 alloc_type = exclusive ?
1837 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
1838 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
1839 unsigned rss_spread = exclusive ?
1840 efx->rss_spread :
1841 min(rounddown_pow_of_two(efx->rss_spread),
1842 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
1843
1844 if (!exclusive && rss_spread == 1) {
1845 *context = EFX_EF10_RSS_CONTEXT_INVALID;
1846 if (context_size)
1847 *context_size = 1;
1848 return 0;
1849 }
8127d661
BH		 1850
1851 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
45b2449e 1852 nic_data->vport_id);
267c0157
JC		 1853 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
1854 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
8127d661
BH		 1855
1856 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
1857 outbuf, sizeof(outbuf), &outlen);
1858 if (rc != 0)
1859 return rc;
1860
1861 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
1862 return -EIO;
1863
1864 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
1865
267c0157
JC		 1866 if (context_size)
1867 *context_size = rss_spread;
1868
8127d661
BH		 1869 return 0;
1870}
1871
1872static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
1873{
1874 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
1875 int rc;
1876
1877 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
1878 context);
1879
1880 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
1881 NULL, 0, NULL);
1882 WARN_ON(rc != 0);
1883}
1884
267c0157
JC		 1885static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
1886 const u32 *rx_indir_table)
8127d661
BH		 1887{
1888 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
1889 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
1890 int i, rc;
1891
1892 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
1893 context);
1894 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1895 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
1896
1897 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
1898 MCDI_PTR(tablebuf,
1899 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
267c0157 1900 (u8) rx_indir_table[i];
8127d661
BH		 1901
1902 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
1903 sizeof(tablebuf), NULL, 0, NULL);
1904 if (rc != 0)
1905 return rc;
1906
1907 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
1908 context);
1909 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
1910 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
1911 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
1912 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
1913 efx->rx_hash_key[i];
1914
1915 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
1916 sizeof(keybuf), NULL, 0, NULL);
1917}
1918
1919static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
1920{
1921 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1922
1923 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
1924 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
1925 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1926}
1927
267c0157
JC		 1928static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
1929 unsigned *context_size)
8127d661 1930{
267c0157 1931 u32 new_rx_rss_context;
8127d661 1932 struct efx_ef10_nic_data *nic_data = efx->nic_data;
267c0157
JC		 1933 int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
1934 false, context_size);
1935
1936 if (rc != 0)
1937 return rc;
8127d661 1938
267c0157
JC		 1939 nic_data->rx_rss_context = new_rx_rss_context;
1940 nic_data->rx_rss_context_exclusive = false;
1941 efx_set_default_rx_indir_table(efx);
1942 return 0;
1943}
8127d661 1944
267c0157
JC		 1945static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
1946 const u32 *rx_indir_table)
1947{
1948 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1949 int rc;
1950 u32 new_rx_rss_context;
1951
1952 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
1953 !nic_data->rx_rss_context_exclusive) {
1954 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
1955 true, NULL);
1956 if (rc == -EOPNOTSUPP)
1957 return rc;
1958 else if (rc != 0)
1959 goto fail1;
1960 } else {
1961 new_rx_rss_context = nic_data->rx_rss_context;
8127d661
BH		 1962 }
1963
267c0157
JC		 1964 rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
1965 rx_indir_table);
8127d661 1966 if (rc != 0)
267c0157 1967 goto fail2;
8127d661 1968
267c0157
JC		 1969 if (nic_data->rx_rss_context != new_rx_rss_context)
1970 efx_ef10_rx_free_indir_table(efx);
1971 nic_data->rx_rss_context = new_rx_rss_context;
1972 nic_data->rx_rss_context_exclusive = true;
1973 if (rx_indir_table != efx->rx_indir_table)
1974 memcpy(efx->rx_indir_table, rx_indir_table,
1975 sizeof(efx->rx_indir_table));
1976 return 0;
8127d661 1977
267c0157
JC		 1978fail2:
1979 if (new_rx_rss_context != nic_data->rx_rss_context)
1980 efx_ef10_free_rss_context(efx, new_rx_rss_context);
1981fail1:
8127d661 1982 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
267c0157
JC		 1983 return rc;
1984}
1985
1986static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
1987 const u32 *rx_indir_table)
1988{
1989 int rc;
1990
1991 if (efx->rss_spread == 1)
1992 return 0;
1993
1994 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table);
1995
1996 if (rc == -ENOBUFS && !user) {
1997 unsigned context_size;
1998 bool mismatch = false;
1999 size_t i;
2000
2001 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2002 i++)
2003 mismatch = rx_indir_table[i] !=
2004 ethtool_rxfh_indir_default(i, efx->rss_spread);
2005
2006 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2007 if (rc == 0) {
2008 if (context_size != efx->rss_spread)
2009 netif_warn(efx, probe, efx->net_dev,
2010 "Could not allocate an exclusive RSS"
2011 " context; allocated a shared one of"
2012 " different size."
2013 " Wanted %u, got %u.\n",
2014 efx->rss_spread, context_size);
2015 else if (mismatch)
2016 netif_warn(efx, probe, efx->net_dev,
2017 "Could not allocate an exclusive RSS"
2018 " context; allocated a shared one but"
2019 " could not apply custom"
2020 " indirection.\n");
2021 else
2022 netif_info(efx, probe, efx->net_dev,
2023 "Could not allocate an exclusive RSS"
2024 " context; allocated a shared one.\n");
2025 }
2026 }
2027 return rc;
2028}
2029
2030static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2031 const u32 *rx_indir_table
2032 __attribute__ ((unused)))
2033{
2034 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2035
2036 if (user)
2037 return -EOPNOTSUPP;
2038 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2039 return 0;
2040 return efx_ef10_rx_push_shared_rss_config(efx, NULL);
8127d661
BH		 2041}
2042
2043static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
2044{
2045 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
2046 (rx_queue->ptr_mask + 1) *
2047 sizeof(efx_qword_t),
2048 GFP_KERNEL);
2049}
2050
2051static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
2052{
2053 MCDI_DECLARE_BUF(inbuf,
2054 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2055 EFX_BUF_SIZE));
8127d661
BH		 2056 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2057 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
2058 struct efx_nic *efx = rx_queue->efx;
45b2449e 2059 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da 2060 size_t inlen;
8127d661
BH		 2061 dma_addr_t dma_addr;
2062 int rc;
2063 int i;
aa09a3da 2064 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
8127d661
BH		 2065
2066 rx_queue->scatter_n = 0;
2067 rx_queue->scatter_len = 0;
2068
2069 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
2070 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
2071 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
2072 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
2073 efx_rx_queue_index(rx_queue));
bd9a265d
JC		 2074 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
2075 INIT_RXQ_IN_FLAG_PREFIX, 1,
2076 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
8127d661 2077 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
45b2449e 2078 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 2079
2080 dma_addr = rx_queue->rxd.buf.dma_addr;
2081
2082 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
2083 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
2084
2085 for (i = 0; i < entries; ++i) {
2086 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
2087 dma_addr += EFX_BUF_SIZE;
2088 }
2089
2090 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
2091
2092 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
aa09a3da 2093 NULL, 0, NULL);
48ce5634
BH		 2094 if (rc)
2095 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
2096 efx_rx_queue_index(rx_queue));
8127d661
BH		 2097}
2098
2099static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
2100{
2101 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
aa09a3da 2102 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 2103 struct efx_nic *efx = rx_queue->efx;
2104 size_t outlen;
2105 int rc;
2106
2107 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
2108 efx_rx_queue_index(rx_queue));
2109
1e0b8120 2110 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
8127d661
BH		 2111 outbuf, sizeof(outbuf), &outlen);
2112
2113 if (rc && rc != -EALREADY)
2114 goto fail;
2115
2116 return;
2117
2118fail:
1e0b8120
EC		 2119 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
2120 outbuf, outlen, rc);
8127d661
BH		 2121}
2122
2123static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
2124{
2125 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
2126}
2127
2128/* This creates an entry in the RX descriptor queue */
2129static inline void
2130efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2131{
2132 struct efx_rx_buffer *rx_buf;
2133 efx_qword_t *rxd;
2134
2135 rxd = efx_rx_desc(rx_queue, index);
2136 rx_buf = efx_rx_buffer(rx_queue, index);
2137 EFX_POPULATE_QWORD_2(*rxd,
2138 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2139 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2140}
2141
2142static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2143{
2144 struct efx_nic *efx = rx_queue->efx;
2145 unsigned int write_count;
2146 efx_dword_t reg;
2147
2148 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2149 write_count = rx_queue->added_count & ~7;
2150 if (rx_queue->notified_count == write_count)
2151 return;
2152
2153 do
2154 efx_ef10_build_rx_desc(
2155 rx_queue,
2156 rx_queue->notified_count & rx_queue->ptr_mask);
2157 while (++rx_queue->notified_count != write_count);
2158
2159 wmb();
2160 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
2161 write_count & rx_queue->ptr_mask);
2162 efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
2163 efx_rx_queue_index(rx_queue));
2164}
2165
2166static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
2167
2168static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
2169{
2170 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2171 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2172 efx_qword_t event;
2173
2174 EFX_POPULATE_QWORD_2(event,
2175 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2176 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
2177
2178 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2179
2180 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2181 * already swapped the data to little-endian order.
2182 */
2183 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2184 sizeof(efx_qword_t));
2185
2186 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
2187 inbuf, sizeof(inbuf), 0,
2188 efx_ef10_rx_defer_refill_complete, 0);
2189}
2190
2191static void
2192efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
2193 int rc, efx_dword_t *outbuf,
2194 size_t outlen_actual)
2195{
2196 /* nothing to do */
2197}
2198
2199static int efx_ef10_ev_probe(struct efx_channel *channel)
2200{
2201 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
2202 (channel->eventq_mask + 1) *
2203 sizeof(efx_qword_t),
2204 GFP_KERNEL);
2205}
2206
46e612b0
DP		 2207static void efx_ef10_ev_fini(struct efx_channel *channel)
2208{
2209 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
2210 MCDI_DECLARE_BUF_ERR(outbuf);
2211 struct efx_nic *efx = channel->efx;
2212 size_t outlen;
2213 int rc;
2214
2215 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
2216
2217 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
2218 outbuf, sizeof(outbuf), &outlen);
2219
2220 if (rc && rc != -EALREADY)
2221 goto fail;
2222
2223 return;
2224
2225fail:
2226 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
2227 outbuf, outlen, rc);
2228}
2229
8127d661
BH		 2230static int efx_ef10_ev_init(struct efx_channel *channel)
2231{
2232 MCDI_DECLARE_BUF(inbuf,
2233 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
2234 EFX_BUF_SIZE));
2235 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN);
2236 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
2237 struct efx_nic *efx = channel->efx;
2238 struct efx_ef10_nic_data *nic_data;
2239 bool supports_rx_merge;
2240 size_t inlen, outlen;
46e612b0 2241 unsigned int enabled, implemented;
8127d661
BH		 2242 dma_addr_t dma_addr;
2243 int rc;
2244 int i;
2245
2246 nic_data = efx->nic_data;
2247 supports_rx_merge =
2248 !!(nic_data->datapath_caps &
2249 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
2250
2251 /* Fill event queue with all ones (i.e. empty events) */
2252 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
2253
2254 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
2255 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
2256 /* INIT_EVQ expects index in vector table, not absolute */
2257 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
2258 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
2259 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
2260 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
2261 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
2262 INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge);
2263 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
2264 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
2265 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
2266 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
2267 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
2268 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
2269 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
2270
2271 dma_addr = channel->eventq.buf.dma_addr;
2272 for (i = 0; i < entries; ++i) {
2273 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
2274 dma_addr += EFX_BUF_SIZE;
2275 }
2276
2277 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
2278
2279 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
2280 outbuf, sizeof(outbuf), &outlen);
8127d661 2281 /* IRQ return is ignored */
46e612b0
DP		 2282 if (channel->channel || rc)
2283 return rc;
8127d661 2284
46e612b0
DP		 2285 /* Successfully created event queue on channel 0 */
2286 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
832dc9ed
EC		 2287 if (rc == -ENOSYS) {
2288 /* GET_WORKAROUNDS was implemented before the bug26807
2289 * workaround, thus the latter must be unavailable in this fw
2290 */
2291 nic_data->workaround_26807 = false;
2292 rc = 0;
2293 } else if (rc) {
8127d661 2294 goto fail;
832dc9ed
EC		 2295 } else {
2296 nic_data->workaround_26807 =
2297 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
2298
2299 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
2300 !nic_data->workaround_26807) {
5a55a72a
DP		 2301 unsigned int flags;
2302
34ccfe6f
DP		 2303 rc = efx_mcdi_set_workaround(efx,
2304 MC_CMD_WORKAROUND_BUG26807,
5a55a72a
DP		 2305 true, &flags);
2306
2307 if (!rc) {
2308 if (flags &
2309 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
2310 netif_info(efx, drv, efx->net_dev,
2311 "other functions on NIC have been reset\n");
2312 /* MC's boot count has incremented */
2313 ++nic_data->warm_boot_count;
2314 }
832dc9ed 2315 nic_data->workaround_26807 = true;
5a55a72a 2316 } else if (rc == -EPERM) {
832dc9ed 2317 rc = 0;
5a55a72a 2318 }
832dc9ed 2319 }
46e612b0
DP		 2320 }
2321
2322 if (!rc)
2323 return 0;
8127d661
BH		 2324
2325fail:
46e612b0
DP		 2326 efx_ef10_ev_fini(channel);
2327 return rc;
8127d661
BH		 2328}
2329
2330static void efx_ef10_ev_remove(struct efx_channel *channel)
2331{
2332 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
2333}
2334
2335static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
2336 unsigned int rx_queue_label)
2337{
2338 struct efx_nic *efx = rx_queue->efx;
2339
2340 netif_info(efx, hw, efx->net_dev,
2341 "rx event arrived on queue %d labeled as queue %u\n",
2342 efx_rx_queue_index(rx_queue), rx_queue_label);
2343
2344 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2345}
2346
2347static void
2348efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
2349 unsigned int actual, unsigned int expected)
2350{
2351 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
2352 struct efx_nic *efx = rx_queue->efx;
2353
2354 netif_info(efx, hw, efx->net_dev,
2355 "dropped %d events (index=%d expected=%d)\n",
2356 dropped, actual, expected);
2357
2358 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2359}
2360
2361/* partially received RX was aborted. clean up. */
2362static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
2363{
2364 unsigned int rx_desc_ptr;
2365
8127d661
BH		 2366 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
2367 "scattered RX aborted (dropping %u buffers)\n",
2368 rx_queue->scatter_n);
2369
2370 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
2371
2372 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
2373 0, EFX_RX_PKT_DISCARD);
2374
2375 rx_queue->removed_count += rx_queue->scatter_n;
2376 rx_queue->scatter_n = 0;
2377 rx_queue->scatter_len = 0;
2378 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
2379}
2380
2381static int efx_ef10_handle_rx_event(struct efx_channel *channel,
2382 const efx_qword_t *event)
2383{
2384 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
2385 unsigned int n_descs, n_packets, i;
2386 struct efx_nic *efx = channel->efx;
2387 struct efx_rx_queue *rx_queue;
2388 bool rx_cont;
2389 u16 flags = 0;
2390
2391 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2392 return 0;
2393
2394 /* Basic packet information */
2395 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
2396 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
2397 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
2398 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
2399 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
2400
48ce5634
BH		 2401 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
2402 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
2403 EFX_QWORD_FMT "\n",
2404 EFX_QWORD_VAL(*event));
8127d661
BH		 2405
2406 rx_queue = efx_channel_get_rx_queue(channel);
2407
2408 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
2409 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
2410
2411 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
2412 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2413
2414 if (n_descs != rx_queue->scatter_n + 1) {
92a04168
BH		 2415 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2416
8127d661
BH		 2417 /* detect rx abort */
2418 if (unlikely(n_descs == rx_queue->scatter_n)) {
48ce5634
BH		 2419 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
2420 netdev_WARN(efx->net_dev,
2421 "invalid RX abort: scatter_n=%u event="
2422 EFX_QWORD_FMT "\n",
2423 rx_queue->scatter_n,
2424 EFX_QWORD_VAL(*event));
8127d661
BH		 2425 efx_ef10_handle_rx_abort(rx_queue);
2426 return 0;
2427 }
2428
92a04168
BH		 2429 /* Check that RX completion merging is valid, i.e.
2430 * the current firmware supports it and this is a
2431 * non-scattered packet.
2432 */
2433 if (!(nic_data->datapath_caps &
2434 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
2435 rx_queue->scatter_n != 0 || rx_cont) {
8127d661
BH		 2436 efx_ef10_handle_rx_bad_lbits(
2437 rx_queue, next_ptr_lbits,
2438 (rx_queue->removed_count +
2439 rx_queue->scatter_n + 1) &
2440 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2441 return 0;
2442 }
2443
2444 /* Merged completion for multiple non-scattered packets */
2445 rx_queue->scatter_n = 1;
2446 rx_queue->scatter_len = 0;
2447 n_packets = n_descs;
2448 ++channel->n_rx_merge_events;
2449 channel->n_rx_merge_packets += n_packets;
2450 flags |= EFX_RX_PKT_PREFIX_LEN;
2451 } else {
2452 ++rx_queue->scatter_n;
2453 rx_queue->scatter_len += rx_bytes;
2454 if (rx_cont)
2455 return 0;
2456 n_packets = 1;
2457 }
2458
2459 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
2460 flags |= EFX_RX_PKT_DISCARD;
2461
2462 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
2463 channel->n_rx_ip_hdr_chksum_err += n_packets;
2464 } else if (unlikely(EFX_QWORD_FIELD(*event,
2465 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
2466 channel->n_rx_tcp_udp_chksum_err += n_packets;
2467 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
2468 rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
2469 flags |= EFX_RX_PKT_CSUMMED;
2470 }
2471
2472 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
2473 flags |= EFX_RX_PKT_TCP;
2474
2475 channel->irq_mod_score += 2 * n_packets;
2476
2477 /* Handle received packet(s) */
2478 for (i = 0; i < n_packets; i++) {
2479 efx_rx_packet(rx_queue,
2480 rx_queue->removed_count & rx_queue->ptr_mask,
2481 rx_queue->scatter_n, rx_queue->scatter_len,
2482 flags);
2483 rx_queue->removed_count += rx_queue->scatter_n;
2484 }
2485
2486 rx_queue->scatter_n = 0;
2487 rx_queue->scatter_len = 0;
2488
2489 return n_packets;
2490}
2491
2492static int
2493efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
2494{
2495 struct efx_nic *efx = channel->efx;
2496 struct efx_tx_queue *tx_queue;
2497 unsigned int tx_ev_desc_ptr;
2498 unsigned int tx_ev_q_label;
2499 int tx_descs = 0;
2500
2501 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2502 return 0;
2503
2504 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
2505 return 0;
2506
2507 /* Transmit completion */
2508 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
2509 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
2510 tx_queue = efx_channel_get_tx_queue(channel,
2511 tx_ev_q_label % EFX_TXQ_TYPES);
2512 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
2513 tx_queue->ptr_mask);
2514 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
2515
2516 return tx_descs;
2517}
2518
2519static void
2520efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
2521{
2522 struct efx_nic *efx = channel->efx;
2523 int subcode;
2524
2525 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
2526
2527 switch (subcode) {
2528 case ESE_DZ_DRV_TIMER_EV:
2529 case ESE_DZ_DRV_WAKE_UP_EV:
2530 break;
2531 case ESE_DZ_DRV_START_UP_EV:
2532 /* event queue init complete. ok. */
2533 break;
2534 default:
2535 netif_err(efx, hw, efx->net_dev,
2536 "channel %d unknown driver event type %d"
2537 " (data " EFX_QWORD_FMT ")\n",
2538 channel->channel, subcode,
2539 EFX_QWORD_VAL(*event));
2540
2541 }
2542}
2543
2544static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
2545 efx_qword_t *event)
2546{
2547 struct efx_nic *efx = channel->efx;
2548 u32 subcode;
2549
2550 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
2551
2552 switch (subcode) {
2553 case EFX_EF10_TEST:
2554 channel->event_test_cpu = raw_smp_processor_id();
2555 break;
2556 case EFX_EF10_REFILL:
2557 /* The queue must be empty, so we won't receive any rx
2558 * events, so efx_process_channel() won't refill the
2559 * queue. Refill it here
2560 */
cce28794 2561 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
8127d661
BH		 2562 break;
2563 default:
2564 netif_err(efx, hw, efx->net_dev,
2565 "channel %d unknown driver event type %u"
2566 " (data " EFX_QWORD_FMT ")\n",
2567 channel->channel, (unsigned) subcode,
2568 EFX_QWORD_VAL(*event));
2569 }
2570}
2571
2572static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
2573{
2574 struct efx_nic *efx = channel->efx;
2575 efx_qword_t event, *p_event;
2576 unsigned int read_ptr;
2577 int ev_code;
2578 int tx_descs = 0;
2579 int spent = 0;
2580
75363a46
EB		 2581 if (quota <= 0)
2582 return spent;
2583
8127d661
BH		 2584 read_ptr = channel->eventq_read_ptr;
2585
2586 for (;;) {
2587 p_event = efx_event(channel, read_ptr);
2588 event = *p_event;
2589
2590 if (!efx_event_present(&event))
2591 break;
2592
2593 EFX_SET_QWORD(*p_event);
2594
2595 ++read_ptr;
2596
2597 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
2598
2599 netif_vdbg(efx, drv, efx->net_dev,
2600 "processing event on %d " EFX_QWORD_FMT "\n",
2601 channel->channel, EFX_QWORD_VAL(event));
2602
2603 switch (ev_code) {
2604 case ESE_DZ_EV_CODE_MCDI_EV:
2605 efx_mcdi_process_event(channel, &event);
2606 break;
2607 case ESE_DZ_EV_CODE_RX_EV:
2608 spent += efx_ef10_handle_rx_event(channel, &event);
2609 if (spent >= quota) {
2610 /* XXX can we split a merged event to
2611 * avoid going over-quota?
2612 */
2613 spent = quota;
2614 goto out;
2615 }
2616 break;
2617 case ESE_DZ_EV_CODE_TX_EV:
2618 tx_descs += efx_ef10_handle_tx_event(channel, &event);
2619 if (tx_descs > efx->txq_entries) {
2620 spent = quota;
2621 goto out;
2622 } else if (++spent == quota) {
2623 goto out;
2624 }
2625 break;
2626 case ESE_DZ_EV_CODE_DRIVER_EV:
2627 efx_ef10_handle_driver_event(channel, &event);
2628 if (++spent == quota)
2629 goto out;
2630 break;
2631 case EFX_EF10_DRVGEN_EV:
2632 efx_ef10_handle_driver_generated_event(channel, &event);
2633 break;
2634 default:
2635 netif_err(efx, hw, efx->net_dev,
2636 "channel %d unknown event type %d"
2637 " (data " EFX_QWORD_FMT ")\n",
2638 channel->channel, ev_code,
2639 EFX_QWORD_VAL(event));
2640 }
2641 }
2642
2643out:
2644 channel->eventq_read_ptr = read_ptr;
2645 return spent;
2646}
2647
2648static void efx_ef10_ev_read_ack(struct efx_channel *channel)
2649{
2650 struct efx_nic *efx = channel->efx;
2651 efx_dword_t rptr;
2652
2653 if (EFX_EF10_WORKAROUND_35388(efx)) {
2654 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
2655 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
2656 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
2657 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
2658
2659 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2660 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
2661 ERF_DD_EVQ_IND_RPTR,
2662 (channel->eventq_read_ptr &
2663 channel->eventq_mask) >>
2664 ERF_DD_EVQ_IND_RPTR_WIDTH);
2665 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2666 channel->channel);
2667 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2668 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
2669 ERF_DD_EVQ_IND_RPTR,
2670 channel->eventq_read_ptr &
2671 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
2672 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2673 channel->channel);
2674 } else {
2675 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
2676 channel->eventq_read_ptr &
2677 channel->eventq_mask);
2678 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
2679 }
2680}
2681
2682static void efx_ef10_ev_test_generate(struct efx_channel *channel)
2683{
2684 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2685 struct efx_nic *efx = channel->efx;
2686 efx_qword_t event;
2687 int rc;
2688
2689 EFX_POPULATE_QWORD_2(event,
2690 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2691 ESF_DZ_EV_DATA, EFX_EF10_TEST);
2692
2693 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2694
2695 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2696 * already swapped the data to little-endian order.
2697 */
2698 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2699 sizeof(efx_qword_t));
2700
2701 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
2702 NULL, 0, NULL);
2703 if (rc != 0)
2704 goto fail;
2705
2706 return;
2707
2708fail:
2709 WARN_ON(true);
2710 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2711}
2712
2713void efx_ef10_handle_drain_event(struct efx_nic *efx)
2714{
2715 if (atomic_dec_and_test(&efx->active_queues))
2716 wake_up(&efx->flush_wq);
2717
2718 WARN_ON(atomic_read(&efx->active_queues) < 0);
2719}
2720
2721static int efx_ef10_fini_dmaq(struct efx_nic *efx)
2722{
2723 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2724 struct efx_channel *channel;
2725 struct efx_tx_queue *tx_queue;
2726 struct efx_rx_queue *rx_queue;
2727 int pending;
2728
2729 /* If the MC has just rebooted, the TX/RX queues will have already been
2730 * torn down, but efx->active_queues needs to be set to zero.
2731 */
2732 if (nic_data->must_realloc_vis) {
2733 atomic_set(&efx->active_queues, 0);
2734 return 0;
2735 }
2736
2737 /* Do not attempt to write to the NIC during EEH recovery */
2738 if (efx->state != STATE_RECOVERY) {
2739 efx_for_each_channel(channel, efx) {
2740 efx_for_each_channel_rx_queue(rx_queue, channel)
2741 efx_ef10_rx_fini(rx_queue);
2742 efx_for_each_channel_tx_queue(tx_queue, channel)
2743 efx_ef10_tx_fini(tx_queue);
2744 }
2745
2746 wait_event_timeout(efx->flush_wq,
2747 atomic_read(&efx->active_queues) == 0,
2748 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
2749 pending = atomic_read(&efx->active_queues);
2750 if (pending) {
2751 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
2752 pending);
2753 return -ETIMEDOUT;
2754 }
2755 }
2756
2757 return 0;
2758}
2759
e283546c
EC		 2760static void efx_ef10_prepare_flr(struct efx_nic *efx)
2761{
2762 atomic_set(&efx->active_queues, 0);
2763}
2764
8127d661
BH		 2765static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
2766 const struct efx_filter_spec *right)
2767{
2768 if ((left->match_flags ^ right->match_flags) |
2769 ((left->flags ^ right->flags) &
2770 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
2771 return false;
2772
2773 return memcmp(&left->outer_vid, &right->outer_vid,
2774 sizeof(struct efx_filter_spec) -
2775 offsetof(struct efx_filter_spec, outer_vid)) == 0;
2776}
2777
2778static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
2779{
2780 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
2781 return jhash2((const u32 *)&spec->outer_vid,
2782 (sizeof(struct efx_filter_spec) -
2783 offsetof(struct efx_filter_spec, outer_vid)) / 4,
2784 0);
2785 /* XXX should we randomise the initval? */
2786}
2787
2788/* Decide whether a filter should be exclusive or else should allow
2789 * delivery to additional recipients. Currently we decide that
2790 * filters for specific local unicast MAC and IP addresses are
2791 * exclusive.
2792 */
2793static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
2794{
2795 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
2796 !is_multicast_ether_addr(spec->loc_mac))
2797 return true;
2798
2799 if ((spec->match_flags &
2800 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
2801 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
2802 if (spec->ether_type == htons(ETH_P_IP) &&
2803 !ipv4_is_multicast(spec->loc_host[0]))
2804 return true;
2805 if (spec->ether_type == htons(ETH_P_IPV6) &&
2806 ((const u8 *)spec->loc_host)[0] != 0xff)
2807 return true;
2808 }
2809
2810 return false;
2811}
2812
2813static struct efx_filter_spec *
2814efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
2815 unsigned int filter_idx)
2816{
2817 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
2818 ~EFX_EF10_FILTER_FLAGS);
2819}
2820
2821static unsigned int
2822efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
2823 unsigned int filter_idx)
2824{
2825 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
2826}
2827
2828static void
2829efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
2830 unsigned int filter_idx,
2831 const struct efx_filter_spec *spec,
2832 unsigned int flags)
2833{
2834 table->entry[filter_idx].spec = (unsigned long)spec | flags;
2835}
2836
2837static void efx_ef10_filter_push_prep(struct efx_nic *efx,
2838 const struct efx_filter_spec *spec,
2839 efx_dword_t *inbuf, u64 handle,
2840 bool replacing)
2841{
2842 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2843
2844 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
2845
2846 if (replacing) {
2847 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2848 MC_CMD_FILTER_OP_IN_OP_REPLACE);
2849 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
2850 } else {
2851 u32 match_fields = 0;
2852
2853 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2854 efx_ef10_filter_is_exclusive(spec) ?
2855 MC_CMD_FILTER_OP_IN_OP_INSERT :
2856 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
2857
2858 /* Convert match flags and values. Unlike almost
2859 * everything else in MCDI, these fields are in
2860 * network byte order.
2861 */
2862 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
2863 match_fields |=
2864 is_multicast_ether_addr(spec->loc_mac) ?
2865 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
2866 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
2867#define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
2868 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
2869 match_fields |= \
2870 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
2871 mcdi_field ## _LBN; \
2872 BUILD_BUG_ON( \
2873 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
2874 sizeof(spec->gen_field)); \
2875 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
2876 &spec->gen_field, sizeof(spec->gen_field)); \
2877 }
2878 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
2879 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
2880 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
2881 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
2882 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
2883 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
2884 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
2885 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
2886 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
2887 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
2888#undef COPY_FIELD
2889 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
2890 match_fields);
2891 }
2892
45b2449e 2893 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 2894 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
2895 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2896 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
2897 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
e3d36293 2898 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
8127d661
BH		 2899 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
2900 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
a0bc3487
BH		 2901 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
2902 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2903 0 : spec->dmaq_id);
8127d661
BH		 2904 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
2905 (spec->flags & EFX_FILTER_FLAG_RX_RSS) ?
2906 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
2907 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
2908 if (spec->flags & EFX_FILTER_FLAG_RX_RSS)
2909 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
2910 spec->rss_context !=
2911 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
2912 spec->rss_context : nic_data->rx_rss_context);
2913}
2914
2915static int efx_ef10_filter_push(struct efx_nic *efx,
2916 const struct efx_filter_spec *spec,
2917 u64 *handle, bool replacing)
2918{
2919 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2920 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
2921 int rc;
2922
2923 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
2924 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2925 outbuf, sizeof(outbuf), NULL);
2926 if (rc == 0)
2927 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
065e64c4
BH		 2928 if (rc == -ENOSPC)
2929 rc = -EBUSY; /* to match efx_farch_filter_insert() */
8127d661
BH		 2930 return rc;
2931}
2932
2933static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table,
2934 enum efx_filter_match_flags match_flags)
2935{
2936 unsigned int match_pri;
2937
2938 for (match_pri = 0;
2939 match_pri < table->rx_match_count;
2940 match_pri++)
2941 if (table->rx_match_flags[match_pri] == match_flags)
2942 return match_pri;
2943
2944 return -EPROTONOSUPPORT;
2945}
2946
2947static s32 efx_ef10_filter_insert(struct efx_nic *efx,
2948 struct efx_filter_spec *spec,
2949 bool replace_equal)
2950{
2951 struct efx_ef10_filter_table *table = efx->filter_state;
2952 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
2953 struct efx_filter_spec *saved_spec;
2954 unsigned int match_pri, hash;
2955 unsigned int priv_flags;
2956 bool replacing = false;
2957 int ins_index = -1;
2958 DEFINE_WAIT(wait);
2959 bool is_mc_recip;
2960 s32 rc;
2961
2962 /* For now, only support RX filters */
2963 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
2964 EFX_FILTER_FLAG_RX)
2965 return -EINVAL;
2966
2967 rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags);
2968 if (rc < 0)
2969 return rc;
2970 match_pri = rc;
2971
2972 hash = efx_ef10_filter_hash(spec);
2973 is_mc_recip = efx_filter_is_mc_recipient(spec);
2974 if (is_mc_recip)
2975 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
2976
2977 /* Find any existing filters with the same match tuple or
2978 * else a free slot to insert at. If any of them are busy,
2979 * we have to wait and retry.
2980 */
2981 for (;;) {
2982 unsigned int depth = 1;
2983 unsigned int i;
2984
2985 spin_lock_bh(&efx->filter_lock);
2986
2987 for (;;) {
2988 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2989 saved_spec = efx_ef10_filter_entry_spec(table, i);
2990
2991 if (!saved_spec) {
2992 if (ins_index < 0)
2993 ins_index = i;
2994 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
2995 if (table->entry[i].spec &
2996 EFX_EF10_FILTER_FLAG_BUSY)
2997 break;
2998 if (spec->priority < saved_spec->priority &&
7665d1ab 2999 spec->priority != EFX_FILTER_PRI_AUTO) {
8127d661
BH		 3000 rc = -EPERM;
3001 goto out_unlock;
3002 }
3003 if (!is_mc_recip) {
3004 /* This is the only one */
3005 if (spec->priority ==
3006 saved_spec->priority &&
3007 !replace_equal) {
3008 rc = -EEXIST;
3009 goto out_unlock;
3010 }
3011 ins_index = i;
3012 goto found;
3013 } else if (spec->priority >
3014 saved_spec->priority ||
3015 (spec->priority ==
3016 saved_spec->priority &&
3017 replace_equal)) {
3018 if (ins_index < 0)
3019 ins_index = i;
3020 else
3021 __set_bit(depth, mc_rem_map);
3022 }
3023 }
3024
3025 /* Once we reach the maximum search depth, use
3026 * the first suitable slot or return -EBUSY if
3027 * there was none
3028 */
3029 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3030 if (ins_index < 0) {
3031 rc = -EBUSY;
3032 goto out_unlock;
3033 }
3034 goto found;
3035 }
3036
3037 ++depth;
3038 }
3039
3040 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3041 spin_unlock_bh(&efx->filter_lock);
3042 schedule();
3043 }
3044
3045found:
3046 /* Create a software table entry if necessary, and mark it
3047 * busy. We might yet fail to insert, but any attempt to
3048 * insert a conflicting filter while we're waiting for the
3049 * firmware must find the busy entry.
3050 */
3051 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3052 if (saved_spec) {
7665d1ab
BH		 3053 if (spec->priority == EFX_FILTER_PRI_AUTO &&
3054 saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
8127d661 3055 /* Just make sure it won't be removed */
7665d1ab
BH		 3056 if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
3057 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 3058 table->entry[ins_index].spec &=
b59e6ef8 3059 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
8127d661
BH		 3060 rc = ins_index;
3061 goto out_unlock;
3062 }
3063 replacing = true;
3064 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
3065 } else {
3066 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3067 if (!saved_spec) {
3068 rc = -ENOMEM;
3069 goto out_unlock;
3070 }
3071 *saved_spec = *spec;
3072 priv_flags = 0;
3073 }
3074 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3075 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
3076
3077 /* Mark lower-priority multicast recipients busy prior to removal */
3078 if (is_mc_recip) {
3079 unsigned int depth, i;
3080
3081 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3082 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3083 if (test_bit(depth, mc_rem_map))
3084 table->entry[i].spec |=
3085 EFX_EF10_FILTER_FLAG_BUSY;
3086 }
3087 }
3088
3089 spin_unlock_bh(&efx->filter_lock);
3090
3091 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
3092 replacing);
3093
3094 /* Finalise the software table entry */
3095 spin_lock_bh(&efx->filter_lock);
3096 if (rc == 0) {
3097 if (replacing) {
3098 /* Update the fields that may differ */
7665d1ab
BH		 3099 if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
3100 saved_spec->flags |=
3101 EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 3102 saved_spec->priority = spec->priority;
7665d1ab 3103 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661
BH		 3104 saved_spec->flags |= spec->flags;
3105 saved_spec->rss_context = spec->rss_context;
3106 saved_spec->dmaq_id = spec->dmaq_id;
3107 }
3108 } else if (!replacing) {
3109 kfree(saved_spec);
3110 saved_spec = NULL;
3111 }
3112 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
3113
3114 /* Remove and finalise entries for lower-priority multicast
3115 * recipients
3116 */
3117 if (is_mc_recip) {
3118 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3119 unsigned int depth, i;
3120
3121 memset(inbuf, 0, sizeof(inbuf));
3122
3123 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3124 if (!test_bit(depth, mc_rem_map))
3125 continue;
3126
3127 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3128 saved_spec = efx_ef10_filter_entry_spec(table, i);
3129 priv_flags = efx_ef10_filter_entry_flags(table, i);
3130
3131 if (rc == 0) {
3132 spin_unlock_bh(&efx->filter_lock);
3133 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3134 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3135 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3136 table->entry[i].handle);
3137 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3138 inbuf, sizeof(inbuf),
3139 NULL, 0, NULL);
3140 spin_lock_bh(&efx->filter_lock);
3141 }
3142
3143 if (rc == 0) {
3144 kfree(saved_spec);
3145 saved_spec = NULL;
3146 priv_flags = 0;
3147 } else {
3148 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
3149 }
3150 efx_ef10_filter_set_entry(table, i, saved_spec,
3151 priv_flags);
3152 }
3153 }
3154
3155 /* If successful, return the inserted filter ID */
3156 if (rc == 0)
3157 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
3158
3159 wake_up_all(&table->waitq);
3160out_unlock:
3161 spin_unlock_bh(&efx->filter_lock);
3162 finish_wait(&table->waitq, &wait);
3163 return rc;
3164}
3165
9fd8095d 3166static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
8127d661
BH		 3167{
3168 /* no need to do anything here on EF10 */
3169}
3170
3171/* Remove a filter.
b59e6ef8
BH		 3172 * If !by_index, remove by ID
3173 * If by_index, remove by index
8127d661
BH		 3174 * Filter ID may come from userland and must be range-checked.
3175 */
3176static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
fbd79120 3177 unsigned int priority_mask,
b59e6ef8 3178 u32 filter_id, bool by_index)
8127d661
BH		 3179{
3180 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3181 struct efx_ef10_filter_table *table = efx->filter_state;
3182 MCDI_DECLARE_BUF(inbuf,
3183 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3184 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3185 struct efx_filter_spec *spec;
3186 DEFINE_WAIT(wait);
3187 int rc;
3188
3189 /* Find the software table entry and mark it busy. Don't
3190 * remove it yet; any attempt to update while we're waiting
3191 * for the firmware must find the busy entry.
3192 */
3193 for (;;) {
3194 spin_lock_bh(&efx->filter_lock);
3195 if (!(table->entry[filter_idx].spec &
3196 EFX_EF10_FILTER_FLAG_BUSY))
3197 break;
3198 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3199 spin_unlock_bh(&efx->filter_lock);
3200 schedule();
3201 }
7665d1ab 3202
8127d661 3203 spec = efx_ef10_filter_entry_spec(table, filter_idx);
7665d1ab 3204 if (!spec ||
b59e6ef8 3205 (!by_index &&
8127d661
BH		 3206 efx_ef10_filter_rx_match_pri(table, spec->match_flags) !=
3207 filter_id / HUNT_FILTER_TBL_ROWS)) {
3208 rc = -ENOENT;
3209 goto out_unlock;
3210 }
7665d1ab
BH		 3211
3212 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
fbd79120 3213 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
7665d1ab
BH		 3214 /* Just remove flags */
3215 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
b59e6ef8 3216 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
7665d1ab
BH		 3217 rc = 0;
3218 goto out_unlock;
3219 }
3220
fbd79120 3221 if (!(priority_mask & (1U << spec->priority))) {
7665d1ab
BH		 3222 rc = -ENOENT;
3223 goto out_unlock;
3224 }
3225
8127d661
BH		 3226 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3227 spin_unlock_bh(&efx->filter_lock);
3228
7665d1ab 3229 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
b59e6ef8 3230 /* Reset to an automatic filter */
8127d661
BH		 3231
3232 struct efx_filter_spec new_spec = *spec;
3233
7665d1ab 3234 new_spec.priority = EFX_FILTER_PRI_AUTO;
8127d661 3235 new_spec.flags = (EFX_FILTER_FLAG_RX |
7665d1ab 3236 EFX_FILTER_FLAG_RX_RSS);
8127d661
BH		 3237 new_spec.dmaq_id = 0;
3238 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
3239 rc = efx_ef10_filter_push(efx, &new_spec,
3240 &table->entry[filter_idx].handle,
3241 true);
3242
3243 spin_lock_bh(&efx->filter_lock);
3244 if (rc == 0)
3245 *spec = new_spec;
3246 } else {
3247 /* Really remove the filter */
3248
3249 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3250 efx_ef10_filter_is_exclusive(spec) ?
3251 MC_CMD_FILTER_OP_IN_OP_REMOVE :
3252 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3253 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3254 table->entry[filter_idx].handle);
3255 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3256 inbuf, sizeof(inbuf), NULL, 0, NULL);
3257
3258 spin_lock_bh(&efx->filter_lock);
3259 if (rc == 0) {
3260 kfree(spec);
3261 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3262 }
3263 }
7665d1ab 3264
8127d661
BH		 3265 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3266 wake_up_all(&table->waitq);
3267out_unlock:
3268 spin_unlock_bh(&efx->filter_lock);
3269 finish_wait(&table->waitq, &wait);
3270 return rc;
3271}
3272
3273static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
3274 enum efx_filter_priority priority,
3275 u32 filter_id)
3276{
fbd79120
BH		 3277 return efx_ef10_filter_remove_internal(efx, 1U << priority,
3278 filter_id, false);
8127d661
BH		 3279}
3280
12fb0da4
EC		 3281static u32 efx_ef10_filter_get_unsafe_id(struct efx_nic *efx, u32 filter_id)
3282{
3283 return filter_id % HUNT_FILTER_TBL_ROWS;
3284}
3285
3286static int efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
3287 enum efx_filter_priority priority,
3288 u32 filter_id)
3289{
3290 return efx_ef10_filter_remove_internal(efx, 1U << priority,
3291 filter_id, true);
3292}
3293
8127d661
BH		 3294static int efx_ef10_filter_get_safe(struct efx_nic *efx,
3295 enum efx_filter_priority priority,
3296 u32 filter_id, struct efx_filter_spec *spec)
3297{
3298 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3299 struct efx_ef10_filter_table *table = efx->filter_state;
3300 const struct efx_filter_spec *saved_spec;
3301 int rc;
3302
3303 spin_lock_bh(&efx->filter_lock);
3304 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
3305 if (saved_spec && saved_spec->priority == priority &&
3306 efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) ==
3307 filter_id / HUNT_FILTER_TBL_ROWS) {
3308 *spec = *saved_spec;
3309 rc = 0;
3310 } else {
3311 rc = -ENOENT;
3312 }
3313 spin_unlock_bh(&efx->filter_lock);
3314 return rc;
3315}
3316
fbd79120 3317static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
8127d661
BH		 3318 enum efx_filter_priority priority)
3319{
fbd79120
BH		 3320 unsigned int priority_mask;
3321 unsigned int i;
3322 int rc;
3323
3324 priority_mask = (((1U << (priority + 1)) - 1) &
3325 ~(1U << EFX_FILTER_PRI_AUTO));
3326
3327 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3328 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
3329 i, true);
3330 if (rc && rc != -ENOENT)
3331 return rc;
3332 }
3333
3334 return 0;
8127d661
BH		 3335}
3336
3337static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
3338 enum efx_filter_priority priority)
3339{
3340 struct efx_ef10_filter_table *table = efx->filter_state;
3341 unsigned int filter_idx;
3342 s32 count = 0;
3343
3344 spin_lock_bh(&efx->filter_lock);
3345 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3346 if (table->entry[filter_idx].spec &&
3347 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
3348 priority)
3349 ++count;
3350 }
3351 spin_unlock_bh(&efx->filter_lock);
3352 return count;
3353}
3354
3355static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
3356{
3357 struct efx_ef10_filter_table *table = efx->filter_state;
3358
3359 return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
3360}
3361
3362static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
3363 enum efx_filter_priority priority,
3364 u32 *buf, u32 size)
3365{
3366 struct efx_ef10_filter_table *table = efx->filter_state;
3367 struct efx_filter_spec *spec;
3368 unsigned int filter_idx;
3369 s32 count = 0;
3370
3371 spin_lock_bh(&efx->filter_lock);
3372 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3373 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3374 if (spec && spec->priority == priority) {
3375 if (count == size) {
3376 count = -EMSGSIZE;
3377 break;
3378 }
3379 buf[count++] = (efx_ef10_filter_rx_match_pri(
3380 table, spec->match_flags) *
3381 HUNT_FILTER_TBL_ROWS +
3382 filter_idx);
3383 }
3384 }
3385 spin_unlock_bh(&efx->filter_lock);
3386 return count;
3387}
3388
3389#ifdef CONFIG_RFS_ACCEL
3390
3391static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
3392
3393static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
3394 struct efx_filter_spec *spec)
3395{
3396 struct efx_ef10_filter_table *table = efx->filter_state;
3397 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3398 struct efx_filter_spec *saved_spec;
3399 unsigned int hash, i, depth = 1;
3400 bool replacing = false;
3401 int ins_index = -1;
3402 u64 cookie;
3403 s32 rc;
3404
3405 /* Must be an RX filter without RSS and not for a multicast
3406 * destination address (RFS only works for connected sockets).
3407 * These restrictions allow us to pass only a tiny amount of
3408 * data through to the completion function.
3409 */
3410 EFX_WARN_ON_PARANOID(spec->flags !=
3411 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
3412 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
3413 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
3414
3415 hash = efx_ef10_filter_hash(spec);
3416
3417 spin_lock_bh(&efx->filter_lock);
3418
3419 /* Find any existing filter with the same match tuple or else
3420 * a free slot to insert at. If an existing filter is busy,
3421 * we have to give up.
3422 */
3423 for (;;) {
3424 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3425 saved_spec = efx_ef10_filter_entry_spec(table, i);
3426
3427 if (!saved_spec) {
3428 if (ins_index < 0)
3429 ins_index = i;
3430 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3431 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
3432 rc = -EBUSY;
3433 goto fail_unlock;
3434 }
8127d661
BH		 3435 if (spec->priority < saved_spec->priority) {
3436 rc = -EPERM;
3437 goto fail_unlock;
3438 }
3439 ins_index = i;
3440 break;
3441 }
3442
3443 /* Once we reach the maximum search depth, use the
3444 * first suitable slot or return -EBUSY if there was
3445 * none
3446 */
3447 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3448 if (ins_index < 0) {
3449 rc = -EBUSY;
3450 goto fail_unlock;
3451 }
3452 break;
3453 }
3454
3455 ++depth;
3456 }
3457
3458 /* Create a software table entry if necessary, and mark it
3459 * busy. We might yet fail to insert, but any attempt to
3460 * insert a conflicting filter while we're waiting for the
3461 * firmware must find the busy entry.
3462 */
3463 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3464 if (saved_spec) {
3465 replacing = true;
3466 } else {
3467 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3468 if (!saved_spec) {
3469 rc = -ENOMEM;
3470 goto fail_unlock;
3471 }
3472 *saved_spec = *spec;
3473 }
3474 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3475 EFX_EF10_FILTER_FLAG_BUSY);
3476
3477 spin_unlock_bh(&efx->filter_lock);
3478
3479 /* Pack up the variables needed on completion */
3480 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
3481
3482 efx_ef10_filter_push_prep(efx, spec, inbuf,
3483 table->entry[ins_index].handle, replacing);
3484 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3485 MC_CMD_FILTER_OP_OUT_LEN,
3486 efx_ef10_filter_rfs_insert_complete, cookie);
3487
3488 return ins_index;
3489
3490fail_unlock:
3491 spin_unlock_bh(&efx->filter_lock);
3492 return rc;
3493}
3494
3495static void
3496efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
3497 int rc, efx_dword_t *outbuf,
3498 size_t outlen_actual)
3499{
3500 struct efx_ef10_filter_table *table = efx->filter_state;
3501 unsigned int ins_index, dmaq_id;
3502 struct efx_filter_spec *spec;
3503 bool replacing;
3504
3505 /* Unpack the cookie */
3506 replacing = cookie >> 31;
3507 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
3508 dmaq_id = cookie & 0xffff;
3509
3510 spin_lock_bh(&efx->filter_lock);
3511 spec = efx_ef10_filter_entry_spec(table, ins_index);
3512 if (rc == 0) {
3513 table->entry[ins_index].handle =
3514 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3515 if (replacing)
3516 spec->dmaq_id = dmaq_id;
3517 } else if (!replacing) {
3518 kfree(spec);
3519 spec = NULL;
3520 }
3521 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
3522 spin_unlock_bh(&efx->filter_lock);
3523
3524 wake_up_all(&table->waitq);
3525}
3526
3527static void
3528efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3529 unsigned long filter_idx,
3530 int rc, efx_dword_t *outbuf,
3531 size_t outlen_actual);
3532
3533static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
3534 unsigned int filter_idx)
3535{
3536 struct efx_ef10_filter_table *table = efx->filter_state;
3537 struct efx_filter_spec *spec =
3538 efx_ef10_filter_entry_spec(table, filter_idx);
3539 MCDI_DECLARE_BUF(inbuf,
3540 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3541 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3542
3543 if (!spec ||
3544 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
3545 spec->priority != EFX_FILTER_PRI_HINT ||
3546 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
3547 flow_id, filter_idx))
3548 return false;
3549
3550 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3551 MC_CMD_FILTER_OP_IN_OP_REMOVE);
3552 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3553 table->entry[filter_idx].handle);
3554 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
3555 efx_ef10_filter_rfs_expire_complete, filter_idx))
3556 return false;
3557
3558 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3559 return true;
3560}
3561
3562static void
3563efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3564 unsigned long filter_idx,
3565 int rc, efx_dword_t *outbuf,
3566 size_t outlen_actual)
3567{
3568 struct efx_ef10_filter_table *table = efx->filter_state;
3569 struct efx_filter_spec *spec =
3570 efx_ef10_filter_entry_spec(table, filter_idx);
3571
3572 spin_lock_bh(&efx->filter_lock);
3573 if (rc == 0) {
3574 kfree(spec);
3575 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3576 }
3577 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3578 wake_up_all(&table->waitq);
3579 spin_unlock_bh(&efx->filter_lock);
3580}
3581
3582#endif /* CONFIG_RFS_ACCEL */
3583
3584static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
3585{
3586 int match_flags = 0;
3587
3588#define MAP_FLAG(gen_flag, mcdi_field) { \
3589 u32 old_mcdi_flags = mcdi_flags; \
3590 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3591 mcdi_field ## _LBN); \
3592 if (mcdi_flags != old_mcdi_flags) \
3593 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
3594 }
3595 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
3596 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
3597 MAP_FLAG(REM_HOST, SRC_IP);
3598 MAP_FLAG(LOC_HOST, DST_IP);
3599 MAP_FLAG(REM_MAC, SRC_MAC);
3600 MAP_FLAG(REM_PORT, SRC_PORT);
3601 MAP_FLAG(LOC_MAC, DST_MAC);
3602 MAP_FLAG(LOC_PORT, DST_PORT);
3603 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
3604 MAP_FLAG(INNER_VID, INNER_VLAN);
3605 MAP_FLAG(OUTER_VID, OUTER_VLAN);
3606 MAP_FLAG(IP_PROTO, IP_PROTO);
3607#undef MAP_FLAG
3608
3609 /* Did we map them all? */
3610 if (mcdi_flags)
3611 return -EINVAL;
3612
3613 return match_flags;
3614}
3615
3616static int efx_ef10_filter_table_probe(struct efx_nic *efx)
3617{
3618 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
3619 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
3620 unsigned int pd_match_pri, pd_match_count;
3621 struct efx_ef10_filter_table *table;
3622 size_t outlen;
3623 int rc;
3624
3625 table = kzalloc(sizeof(*table), GFP_KERNEL);
3626 if (!table)
3627 return -ENOMEM;
3628
3629 /* Find out which RX filter types are supported, and their priorities */
3630 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
3631 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
3632 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
3633 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
3634 &outlen);
3635 if (rc)
3636 goto fail;
3637 pd_match_count = MCDI_VAR_ARRAY_LEN(
3638 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
3639 table->rx_match_count = 0;
3640
3641 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
3642 u32 mcdi_flags =
3643 MCDI_ARRAY_DWORD(
3644 outbuf,
3645 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
3646 pd_match_pri);
3647 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
3648 if (rc < 0) {
3649 netif_dbg(efx, probe, efx->net_dev,
3650 "%s: fw flags %#x pri %u not supported in driver\n",
3651 __func__, mcdi_flags, pd_match_pri);
3652 } else {
3653 netif_dbg(efx, probe, efx->net_dev,
3654 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
3655 __func__, mcdi_flags, pd_match_pri,
3656 rc, table->rx_match_count);
3657 table->rx_match_flags[table->rx_match_count++] = rc;
3658 }
3659 }
3660
3661 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
3662 if (!table->entry) {
3663 rc = -ENOMEM;
3664 goto fail;
3665 }
3666
12fb0da4
EC		 3667 table->ucdef_id = EFX_EF10_FILTER_ID_INVALID;
3668 table->bcast_id = EFX_EF10_FILTER_ID_INVALID;
3669 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID;
3670
8127d661
BH		 3671 efx->filter_state = table;
3672 init_waitqueue_head(&table->waitq);
3673 return 0;
3674
3675fail:
3676 kfree(table);
3677 return rc;
3678}
3679
0d322413
EC		 3680/* Caller must hold efx->filter_sem for read if race against
3681 * efx_ef10_filter_table_remove() is possible
3682 */
8127d661
BH		 3683static void efx_ef10_filter_table_restore(struct efx_nic *efx)
3684{
3685 struct efx_ef10_filter_table *table = efx->filter_state;
3686 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3687 struct efx_filter_spec *spec;
3688 unsigned int filter_idx;
3689 bool failed = false;
3690 int rc;
3691
0d322413
EC		 3692 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
3693
8127d661
BH		 3694 if (!nic_data->must_restore_filters)
3695 return;
3696
0d322413
EC		 3697 if (!table)
3698 return;
3699
8127d661
BH		 3700 spin_lock_bh(&efx->filter_lock);
3701
3702 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3703 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3704 if (!spec)
3705 continue;
3706
3707 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3708 spin_unlock_bh(&efx->filter_lock);
3709
3710 rc = efx_ef10_filter_push(efx, spec,
3711 &table->entry[filter_idx].handle,
3712 false);
3713 if (rc)
3714 failed = true;
3715
3716 spin_lock_bh(&efx->filter_lock);
3717 if (rc) {
3718 kfree(spec);
3719 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3720 } else {
3721 table->entry[filter_idx].spec &=
3722 ~EFX_EF10_FILTER_FLAG_BUSY;
3723 }
3724 }
3725
3726 spin_unlock_bh(&efx->filter_lock);
3727
3728 if (failed)
3729 netif_err(efx, hw, efx->net_dev,
3730 "unable to restore all filters\n");
3731 else
3732 nic_data->must_restore_filters = false;
3733}
3734
0d322413 3735/* Caller must hold efx->filter_sem for write */
8127d661
BH		 3736static void efx_ef10_filter_table_remove(struct efx_nic *efx)
3737{
3738 struct efx_ef10_filter_table *table = efx->filter_state;
3739 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3740 struct efx_filter_spec *spec;
3741 unsigned int filter_idx;
3742 int rc;
3743
0d322413
EC		 3744 efx->filter_state = NULL;
3745 if (!table)
3746 return;
3747
8127d661
BH		 3748 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3749 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3750 if (!spec)
3751 continue;
3752
3753 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3754 efx_ef10_filter_is_exclusive(spec) ?
3755 MC_CMD_FILTER_OP_IN_OP_REMOVE :
3756 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3757 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3758 table->entry[filter_idx].handle);
3759 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3760 NULL, 0, NULL);
48ce5634
BH		 3761 if (rc)
3762 netdev_WARN(efx->net_dev,
3763 "filter_idx=%#x handle=%#llx\n",
3764 filter_idx,
3765 table->entry[filter_idx].handle);
8127d661
BH		 3766 kfree(spec);
3767 }
3768
3769 vfree(table->entry);
3770 kfree(table);
3771}
3772
12fb0da4
EC		 3773#define EFX_EF10_FILTER_DO_MARK_OLD(id) \
3774 if (id != EFX_EF10_FILTER_ID_INVALID) { \
3775 filter_idx = efx_ef10_filter_get_unsafe_id(efx, id); \
3776 WARN_ON(!table->entry[filter_idx].spec); \
3777 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD; \
3778 }
822b96f8 3779static void efx_ef10_filter_mark_old(struct efx_nic *efx)
8127d661
BH		 3780{
3781 struct efx_ef10_filter_table *table = efx->filter_state;
822b96f8 3782 unsigned int filter_idx, i;
8127d661 3783
0d322413
EC		 3784 if (!table)
3785 return;
3786
8127d661
BH		 3787 /* Mark old filters that may need to be removed */
3788 spin_lock_bh(&efx->filter_lock);
12fb0da4
EC		 3789 for (i = 0; i < table->dev_uc_count; i++)
3790 EFX_EF10_FILTER_DO_MARK_OLD(table->dev_uc_list[i].id);
3791 for (i = 0; i < table->dev_mc_count; i++)
3792 EFX_EF10_FILTER_DO_MARK_OLD(table->dev_mc_list[i].id);
3793 EFX_EF10_FILTER_DO_MARK_OLD(table->ucdef_id);
3794 EFX_EF10_FILTER_DO_MARK_OLD(table->bcast_id);
3795 EFX_EF10_FILTER_DO_MARK_OLD(table->mcdef_id);
8127d661 3796 spin_unlock_bh(&efx->filter_lock);
822b96f8 3797}
12fb0da4 3798#undef EFX_EF10_FILTER_DO_MARK_OLD
822b96f8
DP		 3799
3800static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx, bool *promisc)
3801{
3802 struct efx_ef10_filter_table *table = efx->filter_state;
3803 struct net_device *net_dev = efx->net_dev;
3804 struct netdev_hw_addr *uc;
12fb0da4 3805 int addr_count;
822b96f8 3806 unsigned int i;
8127d661 3807
12fb0da4
EC		 3808 table->ucdef_id = EFX_EF10_FILTER_ID_INVALID;
3809 addr_count = netdev_uc_count(net_dev);
3810 if (net_dev->flags & IFF_PROMISC)
822b96f8 3811 *promisc = true;
12fb0da4 3812 table->dev_uc_count = 1 + addr_count;
822b96f8
DP		 3813 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
3814 i = 1;
3815 netdev_for_each_uc_addr(uc, net_dev) {
12fb0da4
EC		 3816 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
3817 *promisc = true;
3818 break;
3819 }
822b96f8 3820 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
12fb0da4 3821 table->dev_uc_list[i].id = EFX_EF10_FILTER_ID_INVALID;
822b96f8
DP		 3822 i++;
3823 }
3824}
3825
3826static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx, bool *promisc)
3827{
3828 struct efx_ef10_filter_table *table = efx->filter_state;
3829 struct net_device *net_dev = efx->net_dev;
3830 struct netdev_hw_addr *mc;
ab8b1f7c 3831 unsigned int i, addr_count;
822b96f8 3832
12fb0da4
EC		 3833 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID;
3834 table->bcast_id = EFX_EF10_FILTER_ID_INVALID;
ab8b1f7c 3835 if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI))
822b96f8 3836 *promisc = true;
ab8b1f7c 3837
12fb0da4
EC		 3838 addr_count = netdev_mc_count(net_dev);
3839 i = 0;
ab8b1f7c 3840 netdev_for_each_mc_addr(mc, net_dev) {
12fb0da4
EC		 3841 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
3842 *promisc = true;
3843 break;
3844 }
ab8b1f7c 3845 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
12fb0da4 3846 table->dev_mc_list[i].id = EFX_EF10_FILTER_ID_INVALID;
ab8b1f7c 3847 i++;
8127d661 3848 }
12fb0da4
EC		 3849
3850 table->dev_mc_count = i;
822b96f8 3851}
8127d661 3852
12fb0da4
EC		 3853static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
3854 bool multicast, bool rollback)
822b96f8
DP		 3855{
3856 struct efx_ef10_filter_table *table = efx->filter_state;
3857 struct efx_ef10_dev_addr *addr_list;
3858 struct efx_filter_spec spec;
12fb0da4
EC		 3859 u8 baddr[ETH_ALEN];
3860 unsigned int i, j;
3861 int addr_count;
822b96f8
DP		 3862 int rc;
3863
3864 if (multicast) {
3865 addr_list = table->dev_mc_list;
12fb0da4 3866 addr_count = table->dev_mc_count;
822b96f8
DP		 3867 } else {
3868 addr_list = table->dev_uc_list;
12fb0da4 3869 addr_count = table->dev_uc_count;
8127d661
BH		 3870 }
3871
822b96f8 3872 /* Insert/renew filters */
12fb0da4 3873 for (i = 0; i < addr_count; i++) {
b6f568e2
JC		 3874 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3875 EFX_FILTER_FLAG_RX_RSS,
3876 0);
3877 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
822b96f8 3878 addr_list[i].addr);
b6f568e2
JC		 3879 rc = efx_ef10_filter_insert(efx, &spec, true);
3880 if (rc < 0) {
12fb0da4
EC		 3881 if (rollback) {
3882 netif_info(efx, drv, efx->net_dev,
3883 "efx_ef10_filter_insert failed rc=%d\n",
3884 rc);
3885 /* Fall back to promiscuous */
3886 for (j = 0; j < i; j++) {
3887 if (addr_list[j].id == EFX_EF10_FILTER_ID_INVALID)
3888 continue;
3889 efx_ef10_filter_remove_unsafe(
3890 efx, EFX_FILTER_PRI_AUTO,
3891 addr_list[j].id);
3892 addr_list[j].id = EFX_EF10_FILTER_ID_INVALID;
3893 }
3894 return rc;
3895 } else {
3896 /* mark as not inserted, and carry on */
3897 rc = EFX_EF10_FILTER_ID_INVALID;
822b96f8 3898 }
8127d661 3899 }
12fb0da4 3900 addr_list[i].id = efx_ef10_filter_get_unsafe_id(efx, rc);
8127d661 3901 }
822b96f8 3902
12fb0da4
EC		 3903 if (multicast && rollback) {
3904 /* Also need an Ethernet broadcast filter */
7665d1ab
BH		 3905 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3906 EFX_FILTER_FLAG_RX_RSS,
8127d661 3907 0);
12fb0da4
EC		 3908 eth_broadcast_addr(baddr);
3909 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, baddr);
8127d661 3910 rc = efx_ef10_filter_insert(efx, &spec, true);
12fb0da4 3911 if (rc < 0) {
822b96f8 3912 netif_warn(efx, drv, efx->net_dev,
12fb0da4
EC		 3913 "Broadcast filter insert failed rc=%d\n", rc);
3914 /* Fall back to promiscuous */
3915 for (j = 0; j < i; j++) {
3916 if (addr_list[j].id == EFX_EF10_FILTER_ID_INVALID)
3917 continue;
3918 efx_ef10_filter_remove_unsafe(
3919 efx, EFX_FILTER_PRI_AUTO,
3920 addr_list[j].id);
3921 addr_list[j].id = EFX_EF10_FILTER_ID_INVALID;
3922 }
3923 return rc;
3924 } else {
3925 table->bcast_id = efx_ef10_filter_get_unsafe_id(efx, rc);
3926 }
8127d661 3927 }
12fb0da4
EC		 3928
3929 return 0;
3930}
3931
3932static int efx_ef10_filter_insert_def(struct efx_nic *efx, bool multicast,
3933 bool rollback)
3934{
3935 struct efx_ef10_filter_table *table = efx->filter_state;
3936 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3937 struct efx_filter_spec spec;
3938 u8 baddr[ETH_ALEN];
3939 int rc;
3940
3941 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3942 EFX_FILTER_FLAG_RX_RSS,
3943 0);
3944
3945 if (multicast)
3946 efx_filter_set_mc_def(&spec);
3947 else
3948 efx_filter_set_uc_def(&spec);
3949
3950 rc = efx_ef10_filter_insert(efx, &spec, true);
3951 if (rc < 0) {
3952 netif_warn(efx, drv, efx->net_dev,
3953 "%scast mismatch filter insert failed rc=%d\n",
3954 multicast ? "Multi" : "Uni", rc);
3955 } else if (multicast) {
3956 table->mcdef_id = efx_ef10_filter_get_unsafe_id(efx, rc);
3957 if (!nic_data->workaround_26807) {
3958 /* Also need an Ethernet broadcast filter */
3959 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3960 EFX_FILTER_FLAG_RX_RSS,
3961 0);
3962 eth_broadcast_addr(baddr);
3963 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
3964 baddr);
3965 rc = efx_ef10_filter_insert(efx, &spec, true);
3966 if (rc < 0) {
3967 netif_warn(efx, drv, efx->net_dev,
3968 "Broadcast filter insert failed rc=%d\n",
3969 rc);
3970 if (rollback) {
3971 /* Roll back the mc_def filter */
3972 efx_ef10_filter_remove_unsafe(
3973 efx, EFX_FILTER_PRI_AUTO,
3974 table->mcdef_id);
3975 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID;
3976 return rc;
3977 }
3978 } else {
3979 table->bcast_id = efx_ef10_filter_get_unsafe_id(efx, rc);
3980 }
3981 }
3982 rc = 0;
3983 } else {
3984 table->ucdef_id = rc;
3985 rc = 0;
3986 }
3987 return rc;
822b96f8
DP		 3988}
3989
3990/* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD
3991 * flag or removes these filters, we don't need to hold the filter_lock while
3992 * scanning for these filters.
3993 */
3994static void efx_ef10_filter_remove_old(struct efx_nic *efx)
3995{
3996 struct efx_ef10_filter_table *table = efx->filter_state;
3997 bool remove_failed = false;
3998 int i;
8127d661 3999
8127d661
BH		 4000 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4001 if (ACCESS_ONCE(table->entry[i].spec) &
b59e6ef8 4002 EFX_EF10_FILTER_FLAG_AUTO_OLD) {
7665d1ab 4003 if (efx_ef10_filter_remove_internal(
fbd79120
BH		 4004 efx, 1U << EFX_FILTER_PRI_AUTO,
4005 i, true) < 0)
8127d661
BH		 4006 remove_failed = true;
4007 }
4008 }
4009 WARN_ON(remove_failed);
4010}
4011
7a186f47
DP		 4012static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
4013{
4014 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4015 u8 mac_old[ETH_ALEN];
4016 int rc, rc2;
4017
4018 /* Only reconfigure a PF-created vport */
4019 if (is_zero_ether_addr(nic_data->vport_mac))
4020 return 0;
4021
4022 efx_device_detach_sync(efx);
4023 efx_net_stop(efx->net_dev);
4024 down_write(&efx->filter_sem);
4025 efx_ef10_filter_table_remove(efx);
4026 up_write(&efx->filter_sem);
4027
4028 rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
4029 if (rc)
4030 goto restore_filters;
4031
4032 ether_addr_copy(mac_old, nic_data->vport_mac);
4033 rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
4034 nic_data->vport_mac);
4035 if (rc)
4036 goto restore_vadaptor;
4037
4038 rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
4039 efx->net_dev->dev_addr);
4040 if (!rc) {
4041 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
4042 } else {
4043 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
4044 if (rc2) {
4045 /* Failed to add original MAC, so clear vport_mac */
4046 eth_zero_addr(nic_data->vport_mac);
4047 goto reset_nic;
4048 }
4049 }
4050
4051restore_vadaptor:
4052 rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
4053 if (rc2)
4054 goto reset_nic;
4055restore_filters:
4056 down_write(&efx->filter_sem);
4057 rc2 = efx_ef10_filter_table_probe(efx);
4058 up_write(&efx->filter_sem);
4059 if (rc2)
4060 goto reset_nic;
4061
4062 rc2 = efx_net_open(efx->net_dev);
4063 if (rc2)
4064 goto reset_nic;
4065
4066 netif_device_attach(efx->net_dev);
4067
4068 return rc;
4069
4070reset_nic:
4071 netif_err(efx, drv, efx->net_dev,
4072 "Failed to restore when changing MAC address - scheduling reset\n");
4073 efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
4074
4075 return rc ? rc : rc2;
4076}
4077
822b96f8
DP		 4078/* Caller must hold efx->filter_sem for read if race against
4079 * efx_ef10_filter_table_remove() is possible
4080 */
4081static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
4082{
4083 struct efx_ef10_filter_table *table = efx->filter_state;
ab8b1f7c 4084 struct efx_ef10_nic_data *nic_data = efx->nic_data;
822b96f8
DP		 4085 struct net_device *net_dev = efx->net_dev;
4086 bool uc_promisc = false, mc_promisc = false;
4087
4088 if (!efx_dev_registered(efx))
4089 return;
4090
4091 if (!table)
4092 return;
4093
4094 efx_ef10_filter_mark_old(efx);
4095
4096 /* Copy/convert the address lists; add the primary station
4097 * address and broadcast address
4098 */
4099 netif_addr_lock_bh(net_dev);
4100 efx_ef10_filter_uc_addr_list(efx, &uc_promisc);
4101 efx_ef10_filter_mc_addr_list(efx, &mc_promisc);
4102 netif_addr_unlock_bh(net_dev);
4103
12fb0da4
EC		 4104 /* Insert/renew unicast filters */
4105 if (uc_promisc) {
4106 efx_ef10_filter_insert_def(efx, false, false);
4107 efx_ef10_filter_insert_addr_list(efx, false, false);
4108 } else {
4109 /* If any of the filters failed to insert, fall back to
4110 * promiscuous mode - add in the uc_def filter. But keep
4111 * our individual unicast filters.
4112 */
4113 if (efx_ef10_filter_insert_addr_list(efx, false, false))
4114 efx_ef10_filter_insert_def(efx, false, false);
4115 }
ab8b1f7c 4116
12fb0da4 4117 /* Insert/renew multicast filters */
ab8b1f7c
DP		 4118 /* If changing promiscuous state with cascaded multicast filters, remove
4119 * old filters first, so that packets are dropped rather than duplicated
4120 */
4121 if (nic_data->workaround_26807 && efx->mc_promisc != mc_promisc)
4122 efx_ef10_filter_remove_old(efx);
12fb0da4
EC		 4123 if (mc_promisc) {
4124 if (nic_data->workaround_26807) {
4125 /* If we failed to insert promiscuous filters, rollback
4126 * and fall back to individual multicast filters
4127 */
4128 if (efx_ef10_filter_insert_def(efx, true, true)) {
4129 /* Changing promisc state, so remove old filters */
4130 efx_ef10_filter_remove_old(efx);
4131 efx_ef10_filter_insert_addr_list(efx, true, false);
4132 }
4133 } else {
4134 /* If we failed to insert promiscuous filters, don't
4135 * rollback. Regardless, also insert the mc_list
4136 */
4137 efx_ef10_filter_insert_def(efx, true, false);
4138 efx_ef10_filter_insert_addr_list(efx, true, false);
4139 }
4140 } else {
4141 /* If any filters failed to insert, rollback and fall back to
4142 * promiscuous mode - mc_def filter and maybe broadcast. If
4143 * that fails, roll back again and insert as many of our
4144 * individual multicast filters as we can.
4145 */
4146 if (efx_ef10_filter_insert_addr_list(efx, true, true)) {
4147 /* Changing promisc state, so remove old filters */
4148 if (nic_data->workaround_26807)
4149 efx_ef10_filter_remove_old(efx);
4150 if (efx_ef10_filter_insert_def(efx, true, true))
4151 efx_ef10_filter_insert_addr_list(efx, true, false);
4152 }
4153 }
822b96f8
DP		 4154
4155 efx_ef10_filter_remove_old(efx);
ab8b1f7c 4156 efx->mc_promisc = mc_promisc;
822b96f8
DP		 4157}
4158
910c8789
SS		 4159static int efx_ef10_set_mac_address(struct efx_nic *efx)
4160{
4161 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
4162 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4163 bool was_enabled = efx->port_enabled;
4164 int rc;
4165
4166 efx_device_detach_sync(efx);
4167 efx_net_stop(efx->net_dev);
4168 down_write(&efx->filter_sem);
4169 efx_ef10_filter_table_remove(efx);
4170
4171 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
4172 efx->net_dev->dev_addr);
4173 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
4174 nic_data->vport_id);
535a6177
DP		 4175 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
4176 sizeof(inbuf), NULL, 0, NULL);
910c8789
SS		 4177
4178 efx_ef10_filter_table_probe(efx);
4179 up_write(&efx->filter_sem);
4180 if (was_enabled)
4181 efx_net_open(efx->net_dev);
4182 netif_device_attach(efx->net_dev);
4183
9e9f665a
DP		 4184#ifdef CONFIG_SFC_SRIOV
4185 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
910c8789
SS		 4186 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
4187
9e9f665a
DP		 4188 if (rc == -EPERM) {
4189 struct efx_nic *efx_pf;
910c8789 4190
9e9f665a
DP		 4191 /* Switch to PF and change MAC address on vport */
4192 efx_pf = pci_get_drvdata(pci_dev_pf);
910c8789 4193
9e9f665a
DP		 4194 rc = efx_ef10_sriov_set_vf_mac(efx_pf,
4195 nic_data->vf_index,
4196 efx->net_dev->dev_addr);
4197 } else if (!rc) {
910c8789
SS		 4198 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
4199 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
4200 unsigned int i;
4201
9e9f665a
DP		 4202 /* MAC address successfully changed by VF (with MAC
4203 * spoofing) so update the parent PF if possible.
4204 */
910c8789
SS		 4205 for (i = 0; i < efx_pf->vf_count; ++i) {
4206 struct ef10_vf *vf = nic_data->vf + i;
4207
4208 if (vf->efx == efx) {
4209 ether_addr_copy(vf->mac,
4210 efx->net_dev->dev_addr);
4211 return 0;
4212 }
4213 }
4214 }
9e9f665a 4215 } else
910c8789 4216#endif
9e9f665a
DP		 4217 if (rc == -EPERM) {
4218 netif_err(efx, drv, efx->net_dev,
4219 "Cannot change MAC address; use sfboot to enable"
4220 " mac-spoofing on this interface\n");
7a186f47
DP		 4221 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
4222 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
4223 * fall-back to the method of changing the MAC address on the
4224 * vport. This only applies to PFs because such versions of
4225 * MCFW do not support VFs.
4226 */
4227 rc = efx_ef10_vport_set_mac_address(efx);
535a6177
DP		 4228 } else {
4229 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
4230 sizeof(inbuf), NULL, 0, rc);
9e9f665a
DP		 4231 }
4232
910c8789
SS		 4233 return rc;
4234}
4235
8127d661
BH		 4236static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
4237{
4238 efx_ef10_filter_sync_rx_mode(efx);
4239
4240 return efx_mcdi_set_mac(efx);
4241}
4242
862f894c
SS		 4243static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
4244{
4245 efx_ef10_filter_sync_rx_mode(efx);
4246
4247 return 0;
4248}
4249
74cd60a4
JC		 4250static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
4251{
4252 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
4253
4254 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
4255 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
4256 NULL, 0, NULL);
4257}
4258
4259/* MC BISTs follow a different poll mechanism to phy BISTs.
4260 * The BIST is done in the poll handler on the MC, and the MCDI command
4261 * will block until the BIST is done.
4262 */
4263static int efx_ef10_poll_bist(struct efx_nic *efx)
4264{
4265 int rc;
4266 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
4267 size_t outlen;
4268 u32 result;
4269
4270 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
4271 outbuf, sizeof(outbuf), &outlen);
4272 if (rc != 0)
4273 return rc;
4274
4275 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
4276 return -EIO;
4277
4278 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
4279 switch (result) {
4280 case MC_CMD_POLL_BIST_PASSED:
4281 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
4282 return 0;
4283 case MC_CMD_POLL_BIST_TIMEOUT:
4284 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
4285 return -EIO;
4286 case MC_CMD_POLL_BIST_FAILED:
4287 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
4288 return -EIO;
4289 default:
4290 netif_err(efx, hw, efx->net_dev,
4291 "BIST returned unknown result %u", result);
4292 return -EIO;
4293 }
4294}
4295
4296static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
4297{
4298 int rc;
4299
4300 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
4301
4302 rc = efx_ef10_start_bist(efx, bist_type);
4303 if (rc != 0)
4304 return rc;
4305
4306 return efx_ef10_poll_bist(efx);
4307}
4308
4309static int
4310efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
4311{
4312 int rc, rc2;
4313
4314 efx_reset_down(efx, RESET_TYPE_WORLD);
4315
4316 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
4317 NULL, 0, NULL, 0, NULL);
4318 if (rc != 0)
4319 goto out;
4320
4321 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
4322 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
4323
4324 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
4325
4326out:
4327 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
4328 return rc ? rc : rc2;
4329}
4330
8127d661
BH		 4331#ifdef CONFIG_SFC_MTD
4332
4333struct efx_ef10_nvram_type_info {
4334 u16 type, type_mask;
4335 u8 port;
4336 const char *name;
4337};
4338
4339static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
4340 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
4341 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
4342 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
4343 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
4344 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
4345 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
4346 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
4347 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
4348 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
a84f3bf9 4349 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
8127d661
BH		 4350 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
4351};
4352
4353static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
4354 struct efx_mcdi_mtd_partition *part,
4355 unsigned int type)
4356{
4357 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
4358 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
4359 const struct efx_ef10_nvram_type_info *info;
4360 size_t size, erase_size, outlen;
4361 bool protected;
4362 int rc;
4363
4364 for (info = efx_ef10_nvram_types; ; info++) {
4365 if (info ==
4366 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
4367 return -ENODEV;
4368 if ((type & ~info->type_mask) == info->type)
4369 break;
4370 }
4371 if (info->port != efx_port_num(efx))
4372 return -ENODEV;
4373
4374 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
4375 if (rc)
4376 return rc;
4377 if (protected)
4378 return -ENODEV; /* hide it */
4379
4380 part->nvram_type = type;
4381
4382 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
4383 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
4384 outbuf, sizeof(outbuf), &outlen);
4385 if (rc)
4386 return rc;
4387 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
4388 return -EIO;
4389 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
4390 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
4391 part->fw_subtype = MCDI_DWORD(outbuf,
4392 NVRAM_METADATA_OUT_SUBTYPE);
4393
4394 part->common.dev_type_name = "EF10 NVRAM manager";
4395 part->common.type_name = info->name;
4396
4397 part->common.mtd.type = MTD_NORFLASH;
4398 part->common.mtd.flags = MTD_CAP_NORFLASH;
4399 part->common.mtd.size = size;
4400 part->common.mtd.erasesize = erase_size;
4401
4402 return 0;
4403}
4404
4405static int efx_ef10_mtd_probe(struct efx_nic *efx)
4406{
4407 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
4408 struct efx_mcdi_mtd_partition *parts;
4409 size_t outlen, n_parts_total, i, n_parts;
4410 unsigned int type;
4411 int rc;
4412
4413 ASSERT_RTNL();
4414
4415 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
4416 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
4417 outbuf, sizeof(outbuf), &outlen);
4418 if (rc)
4419 return rc;
4420 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
4421 return -EIO;
4422
4423 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
4424 if (n_parts_total >
4425 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
4426 return -EIO;
4427
4428 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
4429 if (!parts)
4430 return -ENOMEM;
4431
4432 n_parts = 0;
4433 for (i = 0; i < n_parts_total; i++) {
4434 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
4435 i);
4436 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
4437 if (rc == 0)
4438 n_parts++;
4439 else if (rc != -ENODEV)
4440 goto fail;
4441 }
4442
4443 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
4444fail:
4445 if (rc)
4446 kfree(parts);
4447 return rc;
4448}
4449
4450#endif /* CONFIG_SFC_MTD */
4451
4452static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
4453{
4454 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
4455}
4456
02246a7f
SS		 4457static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
4458 u32 host_time) {}
4459
bd9a265d
JC		 4460static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
4461 bool temp)
4462{
4463 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
4464 int rc;
4465
4466 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
4467 channel->sync_events_state == SYNC_EVENTS_VALID ||
4468 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
4469 return 0;
4470 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
4471
4472 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
4473 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
4474 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
4475 channel->channel);
4476
4477 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
4478 inbuf, sizeof(inbuf), NULL, 0, NULL);
4479
4480 if (rc != 0)
4481 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
4482 SYNC_EVENTS_DISABLED;
4483
4484 return rc;
4485}
4486
4487static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
4488 bool temp)
4489{
4490 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
4491 int rc;
4492
4493 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
4494 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
4495 return 0;
4496 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
4497 channel->sync_events_state = SYNC_EVENTS_DISABLED;
4498 return 0;
4499 }
4500 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
4501 SYNC_EVENTS_DISABLED;
4502
4503 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
4504 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
4505 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
4506 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
4507 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
4508 channel->channel);
4509
4510 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
4511 inbuf, sizeof(inbuf), NULL, 0, NULL);
4512
4513 return rc;
4514}
4515
4516static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
4517 bool temp)
4518{
4519 int (*set)(struct efx_channel *channel, bool temp);
4520 struct efx_channel *channel;
4521
4522 set = en ?
4523 efx_ef10_rx_enable_timestamping :
4524 efx_ef10_rx_disable_timestamping;
4525
4526 efx_for_each_channel(channel, efx) {
4527 int rc = set(channel, temp);
4528 if (en && rc != 0) {
4529 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
4530 return rc;
4531 }
4532 }
4533
4534 return 0;
4535}
4536
02246a7f
SS		 4537static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
4538 struct hwtstamp_config *init)
4539{
4540 return -EOPNOTSUPP;
4541}
4542
bd9a265d
JC		 4543static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
4544 struct hwtstamp_config *init)
4545{
4546 int rc;
4547
4548 switch (init->rx_filter) {
4549 case HWTSTAMP_FILTER_NONE:
4550 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
4551 /* if TX timestamping is still requested then leave PTP on */
4552 return efx_ptp_change_mode(efx,
4553 init->tx_type != HWTSTAMP_TX_OFF, 0);
4554 case HWTSTAMP_FILTER_ALL:
4555 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4556 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4557 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4558 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4559 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4560 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4561 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4562 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4563 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4564 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4565 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4566 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4567 init->rx_filter = HWTSTAMP_FILTER_ALL;
4568 rc = efx_ptp_change_mode(efx, true, 0);
4569 if (!rc)
4570 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
4571 if (rc)
4572 efx_ptp_change_mode(efx, false, 0);
4573 return rc;
4574 default:
4575 return -ERANGE;
4576 }
4577}
4578
02246a7f 4579const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
6f7f8aa6 4580 .is_vf = true,
02246a7f
SS		 4581 .mem_bar = EFX_MEM_VF_BAR,
4582 .mem_map_size = efx_ef10_mem_map_size,
4583 .probe = efx_ef10_probe_vf,
4584 .remove = efx_ef10_remove,
4585 .dimension_resources = efx_ef10_dimension_resources,
4586 .init = efx_ef10_init_nic,
4587 .fini = efx_port_dummy_op_void,
087e9025 4588 .map_reset_reason = efx_ef10_map_reset_reason,
02246a7f
SS		 4589 .map_reset_flags = efx_ef10_map_reset_flags,
4590 .reset = efx_ef10_reset,
4591 .probe_port = efx_mcdi_port_probe,
4592 .remove_port = efx_mcdi_port_remove,
4593 .fini_dmaq = efx_ef10_fini_dmaq,
4594 .prepare_flr = efx_ef10_prepare_flr,
4595 .finish_flr = efx_port_dummy_op_void,
4596 .describe_stats = efx_ef10_describe_stats,
d7788196 4597 .update_stats = efx_ef10_update_stats_vf,
02246a7f
SS		 4598 .start_stats = efx_port_dummy_op_void,
4599 .pull_stats = efx_port_dummy_op_void,
4600 .stop_stats = efx_port_dummy_op_void,
4601 .set_id_led = efx_mcdi_set_id_led,
4602 .push_irq_moderation = efx_ef10_push_irq_moderation,
862f894c 4603 .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
02246a7f
SS		 4604 .check_mac_fault = efx_mcdi_mac_check_fault,
4605 .reconfigure_port = efx_mcdi_port_reconfigure,
4606 .get_wol = efx_ef10_get_wol_vf,
4607 .set_wol = efx_ef10_set_wol_vf,
4608 .resume_wol = efx_port_dummy_op_void,
4609 .mcdi_request = efx_ef10_mcdi_request,
4610 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4611 .mcdi_read_response = efx_ef10_mcdi_read_response,
4612 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
4613 .irq_enable_master = efx_port_dummy_op_void,
4614 .irq_test_generate = efx_ef10_irq_test_generate,
4615 .irq_disable_non_ev = efx_port_dummy_op_void,
4616 .irq_handle_msi = efx_ef10_msi_interrupt,
4617 .irq_handle_legacy = efx_ef10_legacy_interrupt,
4618 .tx_probe = efx_ef10_tx_probe,
4619 .tx_init = efx_ef10_tx_init,
4620 .tx_remove = efx_ef10_tx_remove,
4621 .tx_write = efx_ef10_tx_write,
267c0157 4622 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
02246a7f
SS		 4623 .rx_probe = efx_ef10_rx_probe,
4624 .rx_init = efx_ef10_rx_init,
4625 .rx_remove = efx_ef10_rx_remove,
4626 .rx_write = efx_ef10_rx_write,
4627 .rx_defer_refill = efx_ef10_rx_defer_refill,
4628 .ev_probe = efx_ef10_ev_probe,
4629 .ev_init = efx_ef10_ev_init,
4630 .ev_fini = efx_ef10_ev_fini,
4631 .ev_remove = efx_ef10_ev_remove,
4632 .ev_process = efx_ef10_ev_process,
4633 .ev_read_ack = efx_ef10_ev_read_ack,
4634 .ev_test_generate = efx_ef10_ev_test_generate,
4635 .filter_table_probe = efx_ef10_filter_table_probe,
4636 .filter_table_restore = efx_ef10_filter_table_restore,
4637 .filter_table_remove = efx_ef10_filter_table_remove,
4638 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
4639 .filter_insert = efx_ef10_filter_insert,
4640 .filter_remove_safe = efx_ef10_filter_remove_safe,
4641 .filter_get_safe = efx_ef10_filter_get_safe,
4642 .filter_clear_rx = efx_ef10_filter_clear_rx,
4643 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
4644 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
4645 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
4646#ifdef CONFIG_RFS_ACCEL
4647 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
4648 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
4649#endif
4650#ifdef CONFIG_SFC_MTD
4651 .mtd_probe = efx_port_dummy_op_int,
4652#endif
4653 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
4654 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
4655#ifdef CONFIG_SFC_SRIOV
7b8c7b54
SS		 4656 .vswitching_probe = efx_ef10_vswitching_probe_vf,
4657 .vswitching_restore = efx_ef10_vswitching_restore_vf,
4658 .vswitching_remove = efx_ef10_vswitching_remove_vf,
1d051e00 4659 .sriov_get_phys_port_id = efx_ef10_sriov_get_phys_port_id,
02246a7f 4660#endif
0d5e0fbb 4661 .get_mac_address = efx_ef10_get_mac_address_vf,
910c8789 4662 .set_mac_address = efx_ef10_set_mac_address,
0d5e0fbb 4663
02246a7f
SS		 4664 .revision = EFX_REV_HUNT_A0,
4665 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4666 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4667 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
4668 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
4669 .can_rx_scatter = true,
4670 .always_rx_scatter = true,
4671 .max_interrupt_mode = EFX_INT_MODE_MSIX,
4672 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4673 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4674 NETIF_F_RXHASH | NETIF_F_NTUPLE),
4675 .mcdi_max_ver = 2,
4676 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
4677 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4678 1 << HWTSTAMP_FILTER_ALL,
4679};
4680
8127d661 4681const struct efx_nic_type efx_hunt_a0_nic_type = {
6f7f8aa6 4682 .is_vf = false,
02246a7f 4683 .mem_bar = EFX_MEM_BAR,
8127d661 4684 .mem_map_size = efx_ef10_mem_map_size,
02246a7f 4685 .probe = efx_ef10_probe_pf,
8127d661
BH		 4686 .remove = efx_ef10_remove,
4687 .dimension_resources = efx_ef10_dimension_resources,
4688 .init = efx_ef10_init_nic,
4689 .fini = efx_port_dummy_op_void,
087e9025 4690 .map_reset_reason = efx_ef10_map_reset_reason,
8127d661 4691 .map_reset_flags = efx_ef10_map_reset_flags,
3e336261 4692 .reset = efx_ef10_reset,
8127d661
BH		 4693 .probe_port = efx_mcdi_port_probe,
4694 .remove_port = efx_mcdi_port_remove,
4695 .fini_dmaq = efx_ef10_fini_dmaq,
e283546c
EC		 4696 .prepare_flr = efx_ef10_prepare_flr,
4697 .finish_flr = efx_port_dummy_op_void,
8127d661 4698 .describe_stats = efx_ef10_describe_stats,
d7788196 4699 .update_stats = efx_ef10_update_stats_pf,
8127d661 4700 .start_stats = efx_mcdi_mac_start_stats,
f8f3b5ae 4701 .pull_stats = efx_mcdi_mac_pull_stats,
8127d661
BH		 4702 .stop_stats = efx_mcdi_mac_stop_stats,
4703 .set_id_led = efx_mcdi_set_id_led,
4704 .push_irq_moderation = efx_ef10_push_irq_moderation,
4705 .reconfigure_mac = efx_ef10_mac_reconfigure,
4706 .check_mac_fault = efx_mcdi_mac_check_fault,
4707 .reconfigure_port = efx_mcdi_port_reconfigure,
4708 .get_wol = efx_ef10_get_wol,
4709 .set_wol = efx_ef10_set_wol,
4710 .resume_wol = efx_port_dummy_op_void,
74cd60a4 4711 .test_chip = efx_ef10_test_chip,
8127d661
BH		 4712 .test_nvram = efx_mcdi_nvram_test_all,
4713 .mcdi_request = efx_ef10_mcdi_request,
4714 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4715 .mcdi_read_response = efx_ef10_mcdi_read_response,
4716 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
4717 .irq_enable_master = efx_port_dummy_op_void,
4718 .irq_test_generate = efx_ef10_irq_test_generate,
4719 .irq_disable_non_ev = efx_port_dummy_op_void,
4720 .irq_handle_msi = efx_ef10_msi_interrupt,
4721 .irq_handle_legacy = efx_ef10_legacy_interrupt,
4722 .tx_probe = efx_ef10_tx_probe,
4723 .tx_init = efx_ef10_tx_init,
4724 .tx_remove = efx_ef10_tx_remove,
4725 .tx_write = efx_ef10_tx_write,
267c0157 4726 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
8127d661
BH		 4727 .rx_probe = efx_ef10_rx_probe,
4728 .rx_init = efx_ef10_rx_init,
4729 .rx_remove = efx_ef10_rx_remove,
4730 .rx_write = efx_ef10_rx_write,
4731 .rx_defer_refill = efx_ef10_rx_defer_refill,
4732 .ev_probe = efx_ef10_ev_probe,
4733 .ev_init = efx_ef10_ev_init,
4734 .ev_fini = efx_ef10_ev_fini,
4735 .ev_remove = efx_ef10_ev_remove,
4736 .ev_process = efx_ef10_ev_process,
4737 .ev_read_ack = efx_ef10_ev_read_ack,
4738 .ev_test_generate = efx_ef10_ev_test_generate,
4739 .filter_table_probe = efx_ef10_filter_table_probe,
4740 .filter_table_restore = efx_ef10_filter_table_restore,
4741 .filter_table_remove = efx_ef10_filter_table_remove,
4742 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
4743 .filter_insert = efx_ef10_filter_insert,
4744 .filter_remove_safe = efx_ef10_filter_remove_safe,
4745 .filter_get_safe = efx_ef10_filter_get_safe,
4746 .filter_clear_rx = efx_ef10_filter_clear_rx,
4747 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
4748 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
4749 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
4750#ifdef CONFIG_RFS_ACCEL
4751 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
4752 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
4753#endif
4754#ifdef CONFIG_SFC_MTD
4755 .mtd_probe = efx_ef10_mtd_probe,
4756 .mtd_rename = efx_mcdi_mtd_rename,
4757 .mtd_read = efx_mcdi_mtd_read,
4758 .mtd_erase = efx_mcdi_mtd_erase,
4759 .mtd_write = efx_mcdi_mtd_write,
4760 .mtd_sync = efx_mcdi_mtd_sync,
4761#endif
4762 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
bd9a265d
JC		 4763 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
4764 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
7fa8d547 4765#ifdef CONFIG_SFC_SRIOV
834e23dd 4766 .sriov_configure = efx_ef10_sriov_configure,
d98a4ffe
SS		 4767 .sriov_init = efx_ef10_sriov_init,
4768 .sriov_fini = efx_ef10_sriov_fini,
d98a4ffe
SS		 4769 .sriov_wanted = efx_ef10_sriov_wanted,
4770 .sriov_reset = efx_ef10_sriov_reset,
7fa8d547
SS		 4771 .sriov_flr = efx_ef10_sriov_flr,
4772 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
4773 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
4774 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
4775 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
4392dc69 4776 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
7b8c7b54
SS		 4777 .vswitching_probe = efx_ef10_vswitching_probe_pf,
4778 .vswitching_restore = efx_ef10_vswitching_restore_pf,
4779 .vswitching_remove = efx_ef10_vswitching_remove_pf,
7fa8d547 4780#endif
0d5e0fbb 4781 .get_mac_address = efx_ef10_get_mac_address_pf,
910c8789 4782 .set_mac_address = efx_ef10_set_mac_address,
8127d661
BH		 4783
4784 .revision = EFX_REV_HUNT_A0,
4785 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4786 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4787 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
bd9a265d 4788 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
8127d661
BH		 4789 .can_rx_scatter = true,
4790 .always_rx_scatter = true,
4791 .max_interrupt_mode = EFX_INT_MODE_MSIX,
4792 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4793 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4794 NETIF_F_RXHASH | NETIF_F_NTUPLE),
4795 .mcdi_max_ver = 2,
4796 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
bd9a265d
JC		 4797 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4798 1 << HWTSTAMP_FILTER_ALL,
8127d661 4799};
Linux 6.x block layer and io_uring tree(s)