projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
sfc: explain that "attached" VFs only refer to Xen
[linux-2.6-block.git] / drivers / net / ethernet / sfc / ef10.c
CommitLineData
d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
8127d661
BH		 2/****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2012-2013 Solarflare Communications Inc.
8127d661
BH		 5 */
6
7#include "net_driver.h"
1751cc36 8#include "rx_common.h"
51b35a45 9#include "tx_common.h"
8127d661
BH		 10#include "ef10_regs.h"
11#include "io.h"
12#include "mcdi.h"
13#include "mcdi_pcol.h"
83d00531 14#include "mcdi_port.h"
e1253f39 15#include "mcdi_port_common.h"
37a5f9dc 16#include "mcdi_functions.h"
8127d661 17#include "nic.h"
00aaf7e5 18#include "mcdi_filters.h"
8127d661 19#include "workarounds.h"
74cd60a4 20#include "selftest.h"
7fa8d547 21#include "ef10_sriov.h"
8127d661
BH		 22#include <linux/in.h>
23#include <linux/jhash.h>
24#include <linux/wait.h>
25#include <linux/workqueue.h>
205a55f4 26#include <net/udp_tunnel.h>
8127d661
BH		 27
28/* Hardware control for EF10 architecture including 'Huntington'. */
29
30#define EFX_EF10_DRVGEN_EV 7
31enum {
32 EFX_EF10_TEST = 1,
33 EFX_EF10_REFILL,
34};
dc3273e0 35
34813fe2
AR		 36/* VLAN list entry */
37struct efx_ef10_vlan {
38 struct list_head list;
39 u16 vid;
40};
41
e5fbd977 42static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading);
205a55f4 43static const struct udp_tunnel_nic_info efx_ef10_udp_tunnels;
8127d661
BH		 44
45static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
46{
47 efx_dword_t reg;
48
49 efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
50 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
51 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
52}
53
03714bbb
EC		 54/* On all EF10s up to and including SFC9220 (Medford1), all PFs use BAR 0 for
55 * I/O space and BAR 2(&3) for memory. On SFC9250 (Medford2), there is no I/O
56 * bar; PFs use BAR 0/1 for memory.
57 */
58static unsigned int efx_ef10_pf_mem_bar(struct efx_nic *efx)
59{
60 switch (efx->pci_dev->device) {
61 case 0x0b03: /* SFC9250 PF */
62 return 0;
63 default:
64 return 2;
65 }
66}
67
68/* All VFs use BAR 0/1 for memory */
69static unsigned int efx_ef10_vf_mem_bar(struct efx_nic *efx)
70{
71 return 0;
72}
73
8127d661
BH		 74static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
75{
02246a7f
SS		 76 int bar;
77
03714bbb 78 bar = efx->type->mem_bar(efx);
02246a7f 79 return resource_size(&efx->pci_dev->resource[bar]);
8127d661
BH		 80}
81
7a186f47
DP		 82static bool efx_ef10_is_vf(struct efx_nic *efx)
83{
84 return efx->type->is_vf;
85}
86
88a37de6
SS		 87#ifdef CONFIG_SFC_SRIOV
88static int efx_ef10_get_vf_index(struct efx_nic *efx)
89{
90 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
91 struct efx_ef10_nic_data *nic_data = efx->nic_data;
92 size_t outlen;
93 int rc;
94
95 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
96 sizeof(outbuf), &outlen);
97 if (rc)
98 return rc;
99 if (outlen < sizeof(outbuf))
100 return -EIO;
101
102 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
103 return 0;
104}
105#endif
106
e5a2538a 107static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
8127d661 108{
c1be4821 109 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V4_OUT_LEN);
8127d661
BH		 110 struct efx_ef10_nic_data *nic_data = efx->nic_data;
111 size_t outlen;
112 int rc;
113
114 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
115
116 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
117 outbuf, sizeof(outbuf), &outlen);
118 if (rc)
119 return rc;
ca889a05 120 if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
e5a2538a
BH		 121 netif_err(efx, drv, efx->net_dev,
122 "unable to read datapath firmware capabilities\n");
123 return -EIO;
124 }
125
126 nic_data->datapath_caps =
127 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
8127d661 128
c634700f 129 if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) {
ca889a05
BK		 130 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
131 GET_CAPABILITIES_V2_OUT_FLAGS2);
c634700f
EC		 132 nic_data->piobuf_size = MCDI_WORD(outbuf,
133 GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF);
134 } else {
ca889a05 135 nic_data->datapath_caps2 = 0;
c634700f
EC		 136 nic_data->piobuf_size = ER_DZ_TX_PIOBUF_SIZE;
137 }
ca889a05 138
8d9f9dd4
DP		 139 /* record the DPCPU firmware IDs to determine VEB vswitching support.
140 */
141 nic_data->rx_dpcpu_fw_id =
142 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
143 nic_data->tx_dpcpu_fw_id =
144 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
145
e5a2538a
BH		 146 if (!(nic_data->datapath_caps &
147 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
148 netif_err(efx, probe, efx->net_dev,
149 "current firmware does not support an RX prefix\n");
150 return -ENODEV;
8127d661
BH		 151 }
152
71827443
EC		 153 if (outlen >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) {
154 u8 vi_window_mode = MCDI_BYTE(outbuf,
155 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
156
190c736a
AM		 157 rc = efx_mcdi_window_mode_to_stride(efx, vi_window_mode);
158 if (rc)
159 return rc;
71827443
EC		 160 } else {
161 /* keep default VI stride */
162 netif_dbg(efx, probe, efx->net_dev,
163 "firmware did not report VI window mode, assuming vi_stride = %u\n",
164 efx->vi_stride);
165 }
166
c1be4821
EC		 167 if (outlen >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
168 efx->num_mac_stats = MCDI_WORD(outbuf,
169 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
170 netif_dbg(efx, probe, efx->net_dev,
171 "firmware reports num_mac_stats = %u\n",
172 efx->num_mac_stats);
173 } else {
174 /* leave num_mac_stats as the default value, MC_CMD_MAC_NSTATS */
175 netif_dbg(efx, probe, efx->net_dev,
176 "firmware did not report num_mac_stats, assuming %u\n",
177 efx->num_mac_stats);
178 }
179
8127d661
BH		 180 return 0;
181}
182
50663fe1
MH		 183static void efx_ef10_read_licensed_features(struct efx_nic *efx)
184{
185 MCDI_DECLARE_BUF(inbuf, MC_CMD_LICENSING_V3_IN_LEN);
186 MCDI_DECLARE_BUF(outbuf, MC_CMD_LICENSING_V3_OUT_LEN);
187 struct efx_ef10_nic_data *nic_data = efx->nic_data;
188 size_t outlen;
189 int rc;
190
191 MCDI_SET_DWORD(inbuf, LICENSING_V3_IN_OP,
192 MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE);
193 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_LICENSING_V3, inbuf, sizeof(inbuf),
194 outbuf, sizeof(outbuf), &outlen);
195 if (rc || (outlen < MC_CMD_LICENSING_V3_OUT_LEN))
196 return;
197
198 nic_data->licensed_features = MCDI_QWORD(outbuf,
199 LICENSING_V3_OUT_LICENSED_FEATURES);
200}
201
8127d661
BH		 202static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
203{
204 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
205 int rc;
206
207 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
208 outbuf, sizeof(outbuf), NULL);
209 if (rc)
210 return rc;
211 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
212 return rc > 0 ? rc : -ERANGE;
213}
214
d95e329a
BK		 215static int efx_ef10_get_timer_workarounds(struct efx_nic *efx)
216{
217 struct efx_ef10_nic_data *nic_data = efx->nic_data;
218 unsigned int implemented;
219 unsigned int enabled;
220 int rc;
221
222 nic_data->workaround_35388 = false;
223 nic_data->workaround_61265 = false;
224
225 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
226
227 if (rc == -ENOSYS) {
228 /* Firmware without GET_WORKAROUNDS - not a problem. */
229 rc = 0;
230 } else if (rc == 0) {
231 /* Bug61265 workaround is always enabled if implemented. */
232 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265)
233 nic_data->workaround_61265 = true;
234
235 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
236 nic_data->workaround_35388 = true;
237 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
238 /* Workaround is implemented but not enabled.
239 * Try to enable it.
240 */
241 rc = efx_mcdi_set_workaround(efx,
242 MC_CMD_WORKAROUND_BUG35388,
243 true, NULL);
244 if (rc == 0)
245 nic_data->workaround_35388 = true;
246 /* If we failed to set the workaround just carry on. */
247 rc = 0;
248 }
249 }
250
251 netif_dbg(efx, probe, efx->net_dev,
252 "workaround for bug 35388 is %sabled\n",
253 nic_data->workaround_35388 ? "en" : "dis");
254 netif_dbg(efx, probe, efx->net_dev,
255 "workaround for bug 61265 is %sabled\n",
256 nic_data->workaround_61265 ? "en" : "dis");
257
258 return rc;
259}
260
261static void efx_ef10_process_timer_config(struct efx_nic *efx,
262 const efx_dword_t *data)
263{
264 unsigned int max_count;
265
266 if (EFX_EF10_WORKAROUND_61265(efx)) {
267 efx->timer_quantum_ns = MCDI_DWORD(data,
268 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS);
269 efx->timer_max_ns = MCDI_DWORD(data,
270 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS);
271 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
272 efx->timer_quantum_ns = MCDI_DWORD(data,
273 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT);
274 max_count = MCDI_DWORD(data,
275 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT);
276 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
277 } else {
278 efx->timer_quantum_ns = MCDI_DWORD(data,
279 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT);
280 max_count = MCDI_DWORD(data,
281 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT);
282 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
283 }
284
285 netif_dbg(efx, probe, efx->net_dev,
286 "got timer properties from MC: quantum %u ns; max %u ns\n",
287 efx->timer_quantum_ns, efx->timer_max_ns);
288}
289
290static int efx_ef10_get_timer_config(struct efx_nic *efx)
291{
292 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN);
293 int rc;
294
295 rc = efx_ef10_get_timer_workarounds(efx);
296 if (rc)
297 return rc;
298
299 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0,
300 outbuf, sizeof(outbuf), NULL);
301
302 if (rc == 0) {
303 efx_ef10_process_timer_config(efx, outbuf);
304 } else if (rc == -ENOSYS || rc == -EPERM) {
305 /* Not available - fall back to Huntington defaults. */
306 unsigned int quantum;
307
308 rc = efx_ef10_get_sysclk_freq(efx);
309 if (rc < 0)
310 return rc;
311
312 quantum = 1536000 / rc; /* 1536 cycles */
313 efx->timer_quantum_ns = quantum;
314 efx->timer_max_ns = efx->type->timer_period_max * quantum;
315 rc = 0;
316 } else {
317 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES,
318 MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN,
319 NULL, 0, rc);
320 }
321
322 return rc;
323}
324
0d5e0fbb 325static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
8127d661
BH		 326{
327 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
328 size_t outlen;
329 int rc;
330
331 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
332
333 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
334 outbuf, sizeof(outbuf), &outlen);
335 if (rc)
336 return rc;
337 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
338 return -EIO;
339
cd84ff4d
EC		 340 ether_addr_copy(mac_address,
341 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
8127d661
BH		 342 return 0;
343}
344
0d5e0fbb
DP		 345static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
346{
347 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
348 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
349 size_t outlen;
350 int num_addrs, rc;
351
352 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
353 EVB_PORT_ID_ASSIGNED);
354 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
355 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
356
357 if (rc)
358 return rc;
359 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
360 return -EIO;
361
362 num_addrs = MCDI_DWORD(outbuf,
363 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
364
365 WARN_ON(num_addrs != 1);
366
367 ether_addr_copy(mac_address,
368 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
369
370 return 0;
371}
372
0f5c0845
SS		 373static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
374 struct device_attribute *attr,
375 char *buf)
376{
3e03a8ba 377 struct efx_nic *efx = dev_get_drvdata(dev);
0f5c0845
SS		 378
379 return sprintf(buf, "%d\n",
380 ((efx->mcdi->fn_flags) &
381 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
382 ? 1 : 0);
383}
384
385static ssize_t efx_ef10_show_primary_flag(struct device *dev,
386 struct device_attribute *attr,
387 char *buf)
388{
3e03a8ba 389 struct efx_nic *efx = dev_get_drvdata(dev);
0f5c0845
SS		 390
391 return sprintf(buf, "%d\n",
392 ((efx->mcdi->fn_flags) &
393 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
394 ? 1 : 0);
395}
396
34813fe2
AR		 397static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid)
398{
399 struct efx_ef10_nic_data *nic_data = efx->nic_data;
400 struct efx_ef10_vlan *vlan;
401
402 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
403
404 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
405 if (vlan->vid == vid)
406 return vlan;
407 }
408
409 return NULL;
410}
411
412static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid)
413{
414 struct efx_ef10_nic_data *nic_data = efx->nic_data;
415 struct efx_ef10_vlan *vlan;
416 int rc;
417
418 mutex_lock(&nic_data->vlan_lock);
419
420 vlan = efx_ef10_find_vlan(efx, vid);
421 if (vlan) {
4a53ea8a
AR		 422 /* We add VID 0 on init. 8021q adds it on module init
423 * for all interfaces with VLAN filtring feature.
424 */
425 if (vid == 0)
426 goto done_unlock;
34813fe2
AR		 427 netif_warn(efx, drv, efx->net_dev,
428 "VLAN %u already added\n", vid);
429 rc = -EALREADY;
430 goto fail_exist;
431 }
432
433 rc = -ENOMEM;
434 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
435 if (!vlan)
436 goto fail_alloc;
437
438 vlan->vid = vid;
439
440 list_add_tail(&vlan->list, &nic_data->vlan_list);
441
442 if (efx->filter_state) {
443 mutex_lock(&efx->mac_lock);
444 down_write(&efx->filter_sem);
90c914d2 445 rc = efx_mcdi_filter_add_vlan(efx, vlan->vid);
34813fe2
AR		 446 up_write(&efx->filter_sem);
447 mutex_unlock(&efx->mac_lock);
448 if (rc)
449 goto fail_filter_add_vlan;
450 }
451
4a53ea8a 452done_unlock:
34813fe2
AR		 453 mutex_unlock(&nic_data->vlan_lock);
454 return 0;
455
456fail_filter_add_vlan:
457 list_del(&vlan->list);
458 kfree(vlan);
459fail_alloc:
460fail_exist:
461 mutex_unlock(&nic_data->vlan_lock);
462 return rc;
463}
464
465static void efx_ef10_del_vlan_internal(struct efx_nic *efx,
466 struct efx_ef10_vlan *vlan)
467{
468 struct efx_ef10_nic_data *nic_data = efx->nic_data;
469
470 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
471
472 if (efx->filter_state) {
473 down_write(&efx->filter_sem);
90c914d2 474 efx_mcdi_filter_del_vlan(efx, vlan->vid);
34813fe2
AR		 475 up_write(&efx->filter_sem);
476 }
477
478 list_del(&vlan->list);
479 kfree(vlan);
480}
481
4a53ea8a
AR		 482static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid)
483{
484 struct efx_ef10_nic_data *nic_data = efx->nic_data;
485 struct efx_ef10_vlan *vlan;
486 int rc = 0;
487
488 /* 8021q removes VID 0 on module unload for all interfaces
489 * with VLAN filtering feature. We need to keep it to receive
490 * untagged traffic.
491 */
492 if (vid == 0)
493 return 0;
494
495 mutex_lock(&nic_data->vlan_lock);
496
497 vlan = efx_ef10_find_vlan(efx, vid);
498 if (!vlan) {
499 netif_err(efx, drv, efx->net_dev,
500 "VLAN %u to be deleted not found\n", vid);
501 rc = -ENOENT;
502 } else {
503 efx_ef10_del_vlan_internal(efx, vlan);
504 }
505
506 mutex_unlock(&nic_data->vlan_lock);
507
508 return rc;
509}
510
34813fe2
AR		 511static void efx_ef10_cleanup_vlans(struct efx_nic *efx)
512{
513 struct efx_ef10_nic_data *nic_data = efx->nic_data;
514 struct efx_ef10_vlan *vlan, *next_vlan;
515
516 mutex_lock(&nic_data->vlan_lock);
517 list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list)
518 efx_ef10_del_vlan_internal(efx, vlan);
519 mutex_unlock(&nic_data->vlan_lock);
520}
521
0f5c0845
SS		 522static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
523 NULL);
524static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
525
8127d661
BH		 526static int efx_ef10_probe(struct efx_nic *efx)
527{
528 struct efx_ef10_nic_data *nic_data;
529 int i, rc;
530
8127d661
BH		 531 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
532 if (!nic_data)
533 return -ENOMEM;
534 efx->nic_data = nic_data;
535
75aba2a5
EC		 536 /* we assume later that we can copy from this buffer in dwords */
537 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
538
8127d661
BH		 539 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
540 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
541 if (rc)
542 goto fail1;
543
544 /* Get the MC's warm boot count. In case it's rebooting right
545 * now, be prepared to retry.
546 */
547 i = 0;
548 for (;;) {
549 rc = efx_ef10_get_warm_boot_count(efx);
550 if (rc >= 0)
551 break;
552 if (++i == 5)
553 goto fail2;
554 ssleep(1);
555 }
556 nic_data->warm_boot_count = rc;
557
8127d661
BH		 558 /* In case we're recovering from a crash (kexec), we want to
559 * cancel any outstanding request by the previous user of this
560 * function. We send a special message using the least
561 * significant bits of the 'high' (doorbell) register.
562 */
563 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
564
565 rc = efx_mcdi_init(efx);
566 if (rc)
567 goto fail2;
568
e5fbd977 569 mutex_init(&nic_data->udp_tunnels_lock);
205a55f4
JK		 570 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i)
571 nic_data->udp_tunnels[i].type =
572 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID;
e5fbd977 573
8127d661
BH		 574 /* Reset (most) configuration for this function */
575 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
576 if (rc)
577 goto fail3;
578
579 /* Enable event logging */
580 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
581 if (rc)
582 goto fail3;
583
0f5c0845
SS		 584 rc = device_create_file(&efx->pci_dev->dev,
585 &dev_attr_link_control_flag);
1cd9ecbb
DP		 586 if (rc)
587 goto fail3;
588
0f5c0845
SS		 589 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
590 if (rc)
591 goto fail4;
592
31482310 593 rc = efx_get_pf_index(efx, &nic_data->pf_index);
0f5c0845
SS		 594 if (rc)
595 goto fail5;
596
e5a2538a 597 rc = efx_ef10_init_datapath_caps(efx);
8127d661 598 if (rc < 0)
0f5c0845 599 goto fail5;
8127d661 600
50663fe1
MH		 601 efx_ef10_read_licensed_features(efx);
602
71827443 603 /* We can have one VI for each vi_stride-byte region.
85d43fdb
EC		 604 * However, until we use TX option descriptors we need up to four
605 * TX queues per channel for different checksumming combinations.
71827443 606 */
85d43fdb
EC		 607 if (nic_data->datapath_caps &
608 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))
609 efx->tx_queues_per_channel = 4;
610 else
611 efx->tx_queues_per_channel = 2;
de5f32e2
EC		 612 efx->max_vis = efx_ef10_mem_map_size(efx) / efx->vi_stride;
613 if (!efx->max_vis) {
614 netif_err(efx, drv, efx->net_dev, "error determining max VIs\n");
615 rc = -EIO;
616 goto fail5;
617 }
618 efx->max_channels = min_t(unsigned int, EFX_MAX_CHANNELS,
f9cac93e 619 efx->max_vis / efx->tx_queues_per_channel);
71827443
EC		 620 efx->max_tx_channels = efx->max_channels;
621 if (WARN_ON(efx->max_channels == 0)) {
622 rc = -EIO;
623 goto fail5;
624 }
625
8127d661
BH		 626 efx->rx_packet_len_offset =
627 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
628
6978729f
EC		 629 if (nic_data->datapath_caps &
630 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN))
631 efx->net_dev->hw_features |= NETIF_F_RXFCS;
632
8127d661
BH		 633 rc = efx_mcdi_port_get_number(efx);
634 if (rc < 0)
0f5c0845 635 goto fail5;
8127d661
BH		 636 efx->port_num = rc;
637
0d5e0fbb 638 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
8127d661 639 if (rc)
0f5c0845 640 goto fail5;
8127d661 641
d95e329a 642 rc = efx_ef10_get_timer_config(efx);
8127d661 643 if (rc < 0)
0f5c0845 644 goto fail5;
8127d661 645
8127d661 646 rc = efx_mcdi_mon_probe(efx);
267d9d73 647 if (rc && rc != -EPERM)
0f5c0845 648 goto fail5;
8127d661 649
23418dc1 650 efx_ptp_defer_probe_with_channel(efx);
9aecda95 651
1d051e00
SS		 652#ifdef CONFIG_SFC_SRIOV
653 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
654 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
655 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
656
657 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
658 } else
659#endif
660 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
661
34813fe2
AR		 662 INIT_LIST_HEAD(&nic_data->vlan_list);
663 mutex_init(&nic_data->vlan_lock);
664
665 /* Add unspecified VID to support VLAN filtering being disabled */
666 rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
667 if (rc)
668 goto fail_add_vid_unspec;
669
4a53ea8a
AR		 670 /* If VLAN filtering is enabled, we need VID 0 to get untagged
671 * traffic. It is added automatically if 8021q module is loaded,
672 * but we can't rely on it since module may be not loaded.
673 */
674 rc = efx_ef10_add_vlan(efx, 0);
675 if (rc)
676 goto fail_add_vid_0;
677
205a55f4
JK		 678 if (nic_data->datapath_caps &
679 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) &&
680 efx->mcdi->fn_flags &
681 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED))
682 efx->net_dev->udp_tunnel_nic_info = &efx_ef10_udp_tunnels;
683
8127d661
BH		 684 return 0;
685
4a53ea8a
AR		 686fail_add_vid_0:
687 efx_ef10_cleanup_vlans(efx);
34813fe2
AR		 688fail_add_vid_unspec:
689 mutex_destroy(&nic_data->vlan_lock);
690 efx_ptp_remove(efx);
691 efx_mcdi_mon_remove(efx);
0f5c0845
SS		 692fail5:
693 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
694fail4:
695 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
8127d661 696fail3:
e5fbd977
JC		 697 efx_mcdi_detach(efx);
698
699 mutex_lock(&nic_data->udp_tunnels_lock);
700 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels));
701 (void)efx_ef10_set_udp_tnl_ports(efx, true);
702 mutex_unlock(&nic_data->udp_tunnels_lock);
703 mutex_destroy(&nic_data->udp_tunnels_lock);
704
8127d661
BH		 705 efx_mcdi_fini(efx);
706fail2:
707 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
708fail1:
709 kfree(nic_data);
710 efx->nic_data = NULL;
711 return rc;
712}
713
183233be
BH		 714#ifdef EFX_USE_PIO
715
716static void efx_ef10_free_piobufs(struct efx_nic *efx)
717{
718 struct efx_ef10_nic_data *nic_data = efx->nic_data;
719 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
720 unsigned int i;
721 int rc;
722
723 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
724
725 for (i = 0; i < nic_data->n_piobufs; i++) {
726 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
727 nic_data->piobuf_handle[i]);
728 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
729 NULL, 0, NULL);
730 WARN_ON(rc);
731 }
732
733 nic_data->n_piobufs = 0;
734}
735
736static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
737{
738 struct efx_ef10_nic_data *nic_data = efx->nic_data;
739 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
740 unsigned int i;
741 size_t outlen;
742 int rc = 0;
743
744 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
745
746 for (i = 0; i < n; i++) {
09a04204
BK		 747 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
748 outbuf, sizeof(outbuf), &outlen);
749 if (rc) {
750 /* Don't display the MC error if we didn't have space
751 * for a VF.
752 */
753 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
754 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
755 0, outbuf, outlen, rc);
183233be 756 break;
09a04204 757 }
183233be
BH		 758 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
759 rc = -EIO;
760 break;
761 }
762 nic_data->piobuf_handle[i] =
763 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
764 netif_dbg(efx, probe, efx->net_dev,
765 "allocated PIO buffer %u handle %x\n", i,
766 nic_data->piobuf_handle[i]);
767 }
768
769 nic_data->n_piobufs = i;
770 if (rc)
771 efx_ef10_free_piobufs(efx);
772 return rc;
773}
774
775static int efx_ef10_link_piobufs(struct efx_nic *efx)
776{
777 struct efx_ef10_nic_data *nic_data = efx->nic_data;
d0346b03 778 MCDI_DECLARE_BUF(inbuf, MC_CMD_LINK_PIOBUF_IN_LEN);
183233be
BH		 779 struct efx_channel *channel;
780 struct efx_tx_queue *tx_queue;
781 unsigned int offset, index;
782 int rc;
783
784 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
785 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
786
787 /* Link a buffer to each VI in the write-combining mapping */
788 for (index = 0; index < nic_data->n_piobufs; ++index) {
789 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
790 nic_data->piobuf_handle[index]);
791 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
792 nic_data->pio_write_vi_base + index);
793 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
794 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
795 NULL, 0, NULL);
796 if (rc) {
797 netif_err(efx, drv, efx->net_dev,
798 "failed to link VI %u to PIO buffer %u (%d)\n",
799 nic_data->pio_write_vi_base + index, index,
800 rc);
801 goto fail;
802 }
803 netif_dbg(efx, probe, efx->net_dev,
804 "linked VI %u to PIO buffer %u\n",
805 nic_data->pio_write_vi_base + index, index);
806 }
807
808 /* Link a buffer to each TX queue */
809 efx_for_each_channel(channel, efx) {
2935e3c3
EC		 810 /* Extra channels, even those with TXQs (PTP), do not require
811 * PIO resources.
812 */
3990a8ff
CM		 813 if (!channel->type->want_pio ||
814 channel->channel >= efx->xdp_channel_offset)
2935e3c3 815 continue;
3990a8ff 816
183233be
BH		 817 efx_for_each_channel_tx_queue(tx_queue, channel) {
818 /* We assign the PIO buffers to queues in
819 * reverse order to allow for the following
820 * special case.
821 */
822 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
823 tx_queue->channel->channel - 1) *
824 efx_piobuf_size);
c634700f
EC		 825 index = offset / nic_data->piobuf_size;
826 offset = offset % nic_data->piobuf_size;
183233be
BH		 827
828 /* When the host page size is 4K, the first
829 * host page in the WC mapping may be within
830 * the same VI page as the last TX queue. We
831 * can only link one buffer to each VI.
832 */
833 if (tx_queue->queue == nic_data->pio_write_vi_base) {
834 BUG_ON(index != 0);
835 rc = 0;
836 } else {
837 MCDI_SET_DWORD(inbuf,
838 LINK_PIOBUF_IN_PIOBUF_HANDLE,
839 nic_data->piobuf_handle[index]);
840 MCDI_SET_DWORD(inbuf,
841 LINK_PIOBUF_IN_TXQ_INSTANCE,
842 tx_queue->queue);
843 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
844 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
845 NULL, 0, NULL);
846 }
847
848 if (rc) {
849 /* This is non-fatal; the TX path just
850 * won't use PIO for this queue
851 */
852 netif_err(efx, drv, efx->net_dev,
853 "failed to link VI %u to PIO buffer %u (%d)\n",
854 tx_queue->queue, index, rc);
855 tx_queue->piobuf = NULL;
856 } else {
857 tx_queue->piobuf =
858 nic_data->pio_write_base +
71827443 859 index * efx->vi_stride + offset;
183233be
BH		 860 tx_queue->piobuf_offset = offset;
861 netif_dbg(efx, probe, efx->net_dev,
862 "linked VI %u to PIO buffer %u offset %x addr %p\n",
863 tx_queue->queue, index,
864 tx_queue->piobuf_offset,
865 tx_queue->piobuf);
866 }
867 }
868 }
869
870 return 0;
871
872fail:
d0346b03
EC		 873 /* inbuf was defined for MC_CMD_LINK_PIOBUF. We can use the same
874 * buffer for MC_CMD_UNLINK_PIOBUF because it's shorter.
875 */
876 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_IN_LEN < MC_CMD_UNLINK_PIOBUF_IN_LEN);
183233be
BH		 877 while (index--) {
878 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
879 nic_data->pio_write_vi_base + index);
880 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
881 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
882 NULL, 0, NULL);
883 }
884 return rc;
885}
886
c0795bf6
EC		 887static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
888{
889 struct efx_channel *channel;
890 struct efx_tx_queue *tx_queue;
891
892 /* All our existing PIO buffers went away */
893 efx_for_each_channel(channel, efx)
894 efx_for_each_channel_tx_queue(tx_queue, channel)
895 tx_queue->piobuf = NULL;
896}
897
183233be
BH		 898#else /* !EFX_USE_PIO */
899
900static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
901{
902 return n == 0 ? 0 : -ENOBUFS;
903}
904
905static int efx_ef10_link_piobufs(struct efx_nic *efx)
906{
907 return 0;
908}
909
910static void efx_ef10_free_piobufs(struct efx_nic *efx)
911{
912}
913
c0795bf6
EC		 914static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
915{
916}
917
183233be
BH		 918#endif /* EFX_USE_PIO */
919
8127d661
BH		 920static void efx_ef10_remove(struct efx_nic *efx)
921{
922 struct efx_ef10_nic_data *nic_data = efx->nic_data;
923 int rc;
924
f1122a34
SS		 925#ifdef CONFIG_SFC_SRIOV
926 struct efx_ef10_nic_data *nic_data_pf;
927 struct pci_dev *pci_dev_pf;
928 struct efx_nic *efx_pf;
929 struct ef10_vf *vf;
930
931 if (efx->pci_dev->is_virtfn) {
932 pci_dev_pf = efx->pci_dev->physfn;
933 if (pci_dev_pf) {
934 efx_pf = pci_get_drvdata(pci_dev_pf);
935 nic_data_pf = efx_pf->nic_data;
936 vf = nic_data_pf->vf + nic_data->vf_index;
937 vf->efx = NULL;
938 } else
939 netif_info(efx, drv, efx->net_dev,
940 "Could not get the PF id from VF\n");
941 }
942#endif
943
34813fe2
AR		 944 efx_ef10_cleanup_vlans(efx);
945 mutex_destroy(&nic_data->vlan_lock);
946
9aecda95
BH		 947 efx_ptp_remove(efx);
948
8127d661
BH		 949 efx_mcdi_mon_remove(efx);
950
90c914d2 951 efx_mcdi_rx_free_indir_table(efx);
8127d661 952
183233be
BH		 953 if (nic_data->wc_membase)
954 iounmap(nic_data->wc_membase);
955
37a5f9dc 956 rc = efx_mcdi_free_vis(efx);
8127d661
BH		 957 WARN_ON(rc != 0);
958
183233be
BH		 959 if (!nic_data->must_restore_piobufs)
960 efx_ef10_free_piobufs(efx);
961
0f5c0845
SS		 962 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
963 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
964
e5fbd977
JC		 965 efx_mcdi_detach(efx);
966
967 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels));
968 mutex_lock(&nic_data->udp_tunnels_lock);
969 (void)efx_ef10_set_udp_tnl_ports(efx, true);
970 mutex_unlock(&nic_data->udp_tunnels_lock);
971
972 mutex_destroy(&nic_data->udp_tunnels_lock);
973
8127d661
BH		 974 efx_mcdi_fini(efx);
975 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
976 kfree(nic_data);
977}
978
88a37de6
SS		 979static int efx_ef10_probe_pf(struct efx_nic *efx)
980{
981 return efx_ef10_probe(efx);
982}
983
38d27f38
AR		 984int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id,
985 u32 *port_flags, u32 *vadaptor_flags,
986 unsigned int *vlan_tags)
987{
988 struct efx_ef10_nic_data *nic_data = efx->nic_data;
989 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN);
990 MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN);
991 size_t outlen;
992 int rc;
993
994 if (nic_data->datapath_caps &
995 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) {
996 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID,
997 port_id);
998
999 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf),
1000 outbuf, sizeof(outbuf), &outlen);
1001 if (rc)
1002 return rc;
1003
1004 if (outlen < sizeof(outbuf)) {
1005 rc = -EIO;
1006 return rc;
1007 }
1008 }
1009
1010 if (port_flags)
1011 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS);
1012 if (vadaptor_flags)
1013 *vadaptor_flags =
1014 MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS);
1015 if (vlan_tags)
1016 *vlan_tags =
1017 MCDI_DWORD(outbuf,
1018 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS);
1019
1020 return 0;
1021}
1022
7a186f47
DP		 1023int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
1024{
1025 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
1026
1027 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
1028 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
1029 NULL, 0, NULL);
1030}
1031
1032int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
1033{
1034 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
1035
1036 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
1037 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
1038 NULL, 0, NULL);
1039}
1040
1041int efx_ef10_vport_add_mac(struct efx_nic *efx,
1042 unsigned int port_id, u8 *mac)
1043{
1044 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
1045
1046 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
1047 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
1048
1049 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
1050 sizeof(inbuf), NULL, 0, NULL);
1051}
1052
1053int efx_ef10_vport_del_mac(struct efx_nic *efx,
1054 unsigned int port_id, u8 *mac)
1055{
1056 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
1057
1058 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
1059 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
1060
1061 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
1062 sizeof(inbuf), NULL, 0, NULL);
1063}
1064
88a37de6
SS		 1065#ifdef CONFIG_SFC_SRIOV
1066static int efx_ef10_probe_vf(struct efx_nic *efx)
1067{
1068 int rc;
6598dad2
DP		 1069 struct pci_dev *pci_dev_pf;
1070
1071 /* If the parent PF has no VF data structure, it doesn't know about this
1072 * VF so fail probe. The VF needs to be re-created. This can happen
9a022e76
ÍH		 1073 * if the PF driver was unloaded while any VF was assigned to a guest
1074 * (using Xen, only).
6598dad2
DP		 1075 */
1076 pci_dev_pf = efx->pci_dev->physfn;
1077 if (pci_dev_pf) {
1078 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
1079 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
1080
1081 if (!nic_data_pf->vf) {
1082 netif_info(efx, drv, efx->net_dev,
1083 "The VF cannot link to its parent PF; "
1084 "please destroy and re-create the VF\n");
1085 return -EBUSY;
1086 }
1087 }
88a37de6
SS		 1088
1089 rc = efx_ef10_probe(efx);
1090 if (rc)
1091 return rc;
1092
1093 rc = efx_ef10_get_vf_index(efx);
1094 if (rc)
1095 goto fail;
1096
f1122a34
SS		 1097 if (efx->pci_dev->is_virtfn) {
1098 if (efx->pci_dev->physfn) {
1099 struct efx_nic *efx_pf =
1100 pci_get_drvdata(efx->pci_dev->physfn);
1101 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
1102 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1103
1104 nic_data_p->vf[nic_data->vf_index].efx = efx;
6598dad2
DP		 1105 nic_data_p->vf[nic_data->vf_index].pci_dev =
1106 efx->pci_dev;
f1122a34
SS		 1107 } else
1108 netif_info(efx, drv, efx->net_dev,
1109 "Could not get the PF id from VF\n");
1110 }
1111
88a37de6
SS		 1112 return 0;
1113
1114fail:
1115 efx_ef10_remove(efx);
1116 return rc;
1117}
1118#else
1119static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
1120{
1121 return 0;
1122}
1123#endif
1124
8127d661
BH		 1125static int efx_ef10_alloc_vis(struct efx_nic *efx,
1126 unsigned int min_vis, unsigned int max_vis)
1127{
8127d661 1128 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661 1129
37a5f9dc
AM		 1130 return efx_mcdi_alloc_vis(efx, min_vis, max_vis, &nic_data->vi_base,
1131 &nic_data->n_allocated_vis);
8127d661
BH		 1132}
1133
183233be
BH		 1134/* Note that the failure path of this function does not free
1135 * resources, as this will be done by efx_ef10_remove().
1136 */
8127d661
BH		 1137static int efx_ef10_dimension_resources(struct efx_nic *efx)
1138{
f9cac93e
EC		 1139 unsigned int min_vis = max_t(unsigned int, efx->tx_queues_per_channel,
1140 efx_separate_tx_channels ? 2 : 1);
1141 unsigned int channel_vis, pio_write_vi_base, max_vis;
183233be
BH		 1142 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1143 unsigned int uc_mem_map_size, wc_mem_map_size;
183233be
BH		 1144 void __iomem *membase;
1145 int rc;
1146
2935e3c3 1147 channel_vis = max(efx->n_channels,
3990a8ff 1148 ((efx->n_tx_channels + efx->n_extra_tx_channels) *
f9cac93e 1149 efx->tx_queues_per_channel) +
3990a8ff 1150 efx->n_xdp_channels * efx->xdp_tx_per_channel);
de5f32e2
EC		 1151 if (efx->max_vis && efx->max_vis < channel_vis) {
1152 netif_dbg(efx, drv, efx->net_dev,
1153 "Reducing channel VIs from %u to %u\n",
1154 channel_vis, efx->max_vis);
1155 channel_vis = efx->max_vis;
1156 }
8127d661 1157
183233be
BH		 1158#ifdef EFX_USE_PIO
1159 /* Try to allocate PIO buffers if wanted and if the full
1160 * number of PIO buffers would be sufficient to allocate one
1161 * copy-buffer per TX channel. Failure is non-fatal, as there
1162 * are only a small number of PIO buffers shared between all
1163 * functions of the controller.
1164 */
1165 if (efx_piobuf_size != 0 &&
c634700f 1166 nic_data->piobuf_size / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
183233be
BH		 1167 efx->n_tx_channels) {
1168 unsigned int n_piobufs =
1169 DIV_ROUND_UP(efx->n_tx_channels,
c634700f 1170 nic_data->piobuf_size / efx_piobuf_size);
183233be
BH		 1171
1172 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
6eacfb54
TP		 1173 if (rc == -ENOSPC)
1174 netif_dbg(efx, probe, efx->net_dev,
1175 "out of PIO buffers; cannot allocate more\n");
1176 else if (rc == -EPERM)
1177 netif_dbg(efx, probe, efx->net_dev,
1178 "not permitted to allocate PIO buffers\n");
1179 else if (rc)
183233be
BH		 1180 netif_err(efx, probe, efx->net_dev,
1181 "failed to allocate PIO buffers (%d)\n", rc);
1182 else
1183 netif_dbg(efx, probe, efx->net_dev,
1184 "allocated %u PIO buffers\n", n_piobufs);
1185 }
1186#else
1187 nic_data->n_piobufs = 0;
1188#endif
1189
1190 /* PIO buffers should be mapped with write-combining enabled,
1191 * and we want to make single UC and WC mappings rather than
1192 * several of each (in fact that's the only option if host
1193 * page size is >4K). So we may allocate some extra VIs just
1194 * for writing PIO buffers through.
52ad762b 1195 *
b0fbdae1 1196 * The UC mapping contains (channel_vis - 1) complete VIs and the
71827443
EC		 1197 * first 4K of the next VI. Then the WC mapping begins with
1198 * the remainder of this last VI.
183233be 1199 */
71827443 1200 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * efx->vi_stride +
183233be
BH		 1201 ER_DZ_TX_PIOBUF);
1202 if (nic_data->n_piobufs) {
52ad762b
DP		 1203 /* pio_write_vi_base rounds down to give the number of complete
1204 * VIs inside the UC mapping.
1205 */
71827443 1206 pio_write_vi_base = uc_mem_map_size / efx->vi_stride;
183233be
BH		 1207 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
1208 nic_data->n_piobufs) *
71827443 1209 efx->vi_stride) -
183233be
BH		 1210 uc_mem_map_size);
1211 max_vis = pio_write_vi_base + nic_data->n_piobufs;
1212 } else {
1213 pio_write_vi_base = 0;
1214 wc_mem_map_size = 0;
b0fbdae1 1215 max_vis = channel_vis;
183233be
BH		 1216 }
1217
1218 /* In case the last attached driver failed to free VIs, do it now */
37a5f9dc 1219 rc = efx_mcdi_free_vis(efx);
183233be
BH		 1220 if (rc != 0)
1221 return rc;
1222
1223 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
1224 if (rc != 0)
1225 return rc;
1226
b0fbdae1
SS		 1227 if (nic_data->n_allocated_vis < channel_vis) {
1228 netif_info(efx, drv, efx->net_dev,
1229 "Could not allocate enough VIs to satisfy RSS"
1230 " requirements. Performance may not be optimal.\n");
1231 /* We didn't get the VIs to populate our channels.
1232 * We could keep what we got but then we'd have more
1233 * interrupts than we need.
1234 * Instead calculate new max_channels and restart
1235 */
1236 efx->max_channels = nic_data->n_allocated_vis;
1237 efx->max_tx_channels =
f9cac93e 1238 nic_data->n_allocated_vis / efx->tx_queues_per_channel;
b0fbdae1 1239
37a5f9dc 1240 efx_mcdi_free_vis(efx);
b0fbdae1
SS		 1241 return -EAGAIN;
1242 }
1243
183233be
BH		 1244 /* If we didn't get enough VIs to map all the PIO buffers, free the
1245 * PIO buffers
1246 */
1247 if (nic_data->n_piobufs &&
1248 nic_data->n_allocated_vis <
1249 pio_write_vi_base + nic_data->n_piobufs) {
1250 netif_dbg(efx, probe, efx->net_dev,
1251 "%u VIs are not sufficient to map %u PIO buffers\n",
1252 nic_data->n_allocated_vis, nic_data->n_piobufs);
1253 efx_ef10_free_piobufs(efx);
1254 }
1255
1256 /* Shrink the original UC mapping of the memory BAR */
4bdc0d67 1257 membase = ioremap(efx->membase_phys, uc_mem_map_size);
183233be
BH		 1258 if (!membase) {
1259 netif_err(efx, probe, efx->net_dev,
1260 "could not shrink memory BAR to %x\n",
1261 uc_mem_map_size);
1262 return -ENOMEM;
1263 }
1264 iounmap(efx->membase);
1265 efx->membase = membase;
1266
1267 /* Set up the WC mapping if needed */
1268 if (wc_mem_map_size) {
1269 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
1270 uc_mem_map_size,
1271 wc_mem_map_size);
1272 if (!nic_data->wc_membase) {
1273 netif_err(efx, probe, efx->net_dev,
1274 "could not allocate WC mapping of size %x\n",
1275 wc_mem_map_size);
1276 return -ENOMEM;
1277 }
1278 nic_data->pio_write_vi_base = pio_write_vi_base;
1279 nic_data->pio_write_base =
1280 nic_data->wc_membase +
71827443 1281 (pio_write_vi_base * efx->vi_stride + ER_DZ_TX_PIOBUF -
183233be
BH		 1282 uc_mem_map_size);
1283
1284 rc = efx_ef10_link_piobufs(efx);
1285 if (rc)
1286 efx_ef10_free_piobufs(efx);
1287 }
1288
1289 netif_dbg(efx, probe, efx->net_dev,
1290 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
1291 &efx->membase_phys, efx->membase, uc_mem_map_size,
1292 nic_data->wc_membase, wc_mem_map_size);
1293
1294 return 0;
8127d661
BH		 1295}
1296
d3142c19
EC		 1297static void efx_ef10_fini_nic(struct efx_nic *efx)
1298{
1299 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1300
1301 kfree(nic_data->mc_stats);
1302 nic_data->mc_stats = NULL;
1303}
1304
8127d661
BH		 1305static int efx_ef10_init_nic(struct efx_nic *efx)
1306{
1307 struct efx_ef10_nic_data *nic_data = efx->nic_data;
24b2c375 1308 netdev_features_t hw_enc_features = 0;
8127d661
BH		 1309 int rc;
1310
a915ccc9
BH		 1311 if (nic_data->must_check_datapath_caps) {
1312 rc = efx_ef10_init_datapath_caps(efx);
1313 if (rc)
1314 return rc;
1315 nic_data->must_check_datapath_caps = false;
1316 }
1317
e4fe938c 1318 if (efx->must_realloc_vis) {
8127d661
BH		 1319 /* We cannot let the number of VIs change now */
1320 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
1321 nic_data->n_allocated_vis);
1322 if (rc)
1323 return rc;
e4fe938c 1324 efx->must_realloc_vis = false;
8127d661
BH		 1325 }
1326
d3142c19
EC		 1327 nic_data->mc_stats = kmalloc(efx->num_mac_stats * sizeof(__le64),
1328 GFP_KERNEL);
1329 if (!nic_data->mc_stats)
1330 return -ENOMEM;
1331
183233be
BH		 1332 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
1333 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
1334 if (rc == 0) {
1335 rc = efx_ef10_link_piobufs(efx);
1336 if (rc)
1337 efx_ef10_free_piobufs(efx);
1338 }
1339
6eacfb54
TP		 1340 /* Log an error on failure, but this is non-fatal.
1341 * Permission errors are less important - we've presumably
1342 * had the PIO buffer licence removed.
1343 */
1344 if (rc == -EPERM)
1345 netif_dbg(efx, drv, efx->net_dev,
1346 "not permitted to restore PIO buffers\n");
1347 else if (rc)
183233be
BH		 1348 netif_err(efx, drv, efx->net_dev,
1349 "failed to restore PIO buffers (%d)\n", rc);
1350 nic_data->must_restore_piobufs = false;
1351 }
1352
24b2c375
EC		 1353 /* add encapsulated checksum offload features */
1354 if (efx_has_cap(efx, VXLAN_NVGRE) && !efx_ef10_is_vf(efx))
1355 hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1356 /* add encapsulated TSO features */
1357 if (efx_has_cap(efx, TX_TSO_V2_ENCAP)) {
1358 netdev_features_t encap_tso_features;
1359
1360 encap_tso_features = NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
1361 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM;
1362
1363 hw_enc_features |= encap_tso_features | NETIF_F_TSO;
1364 efx->net_dev->features |= encap_tso_features;
1365 }
1366 efx->net_dev->hw_enc_features = hw_enc_features;
1367
267c0157 1368 /* don't fail init if RSS setup doesn't work */
42356d9a
EC		 1369 rc = efx->type->rx_push_rss_config(efx, false,
1370 efx->rss_context.rx_indir_table, NULL);
267c0157 1371
8127d661
BH		 1372 return 0;
1373}
1374
90c914d2 1375static void efx_ef10_table_reset_mc_allocations(struct efx_nic *efx)
3e336261
JC		 1376{
1377 struct efx_ef10_nic_data *nic_data = efx->nic_data;
774ad031
DP		 1378#ifdef CONFIG_SFC_SRIOV
1379 unsigned int i;
1380#endif
3e336261
JC		 1381
1382 /* All our allocations have been reset */
e4fe938c
EC		 1383 efx->must_realloc_vis = true;
1384 efx_mcdi_filter_table_reset_mc_allocations(efx);
3e336261 1385 nic_data->must_restore_piobufs = true;
c0795bf6 1386 efx_ef10_forget_old_piobufs(efx);
f7226e0f 1387 efx->rss_context.context_id = EFX_MCDI_RSS_CONTEXT_INVALID;
774ad031
DP		 1388
1389 /* Driver-created vswitches and vports must be re-created */
1390 nic_data->must_probe_vswitching = true;
dfcabb07 1391 efx->vport_id = EVB_PORT_ID_ASSIGNED;
774ad031
DP		 1392#ifdef CONFIG_SFC_SRIOV
1393 if (nic_data->vf)
1394 for (i = 0; i < efx->vf_count; i++)
1395 nic_data->vf[i].vport_id = 0;
1396#endif
3e336261
JC		 1397}
1398
087e9025
JC		 1399static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1400{
1401 if (reason == RESET_TYPE_MC_FAILURE)
1402 return RESET_TYPE_DATAPATH;
1403
1404 return efx_mcdi_map_reset_reason(reason);
1405}
1406
8127d661
BH		 1407static int efx_ef10_map_reset_flags(u32 *flags)
1408{
1409 enum {
1410 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1411 ETH_RESET_SHARED_SHIFT),
1412 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1413 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1414 ETH_RESET_PHY | ETH_RESET_MGMT) <<
1415 ETH_RESET_SHARED_SHIFT)
1416 };
1417
1418 /* We assume for now that our PCI function is permitted to
1419 * reset everything.
1420 */
1421
1422 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1423 *flags &= ~EF10_RESET_MC;
1424 return RESET_TYPE_WORLD;
1425 }
1426
1427 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1428 *flags &= ~EF10_RESET_PORT;
1429 return RESET_TYPE_ALL;
1430 }
1431
1432 /* no invisible reset implemented */
1433
1434 return -EINVAL;
1435}
1436
3e336261
JC		 1437static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1438{
1439 int rc = efx_mcdi_reset(efx, reset_type);
1440
27324820
DP		 1441 /* Unprivileged functions return -EPERM, but need to return success
1442 * here so that the datapath is brought back up.
1443 */
1444 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1445 rc = 0;
1446
3e336261
JC		 1447 /* If it was a port reset, trigger reallocation of MC resources.
1448 * Note that on an MC reset nothing needs to be done now because we'll
1449 * detect the MC reset later and handle it then.
e283546c
EC		 1450 * For an FLR, we never get an MC reset event, but the MC has reset all
1451 * resources assigned to us, so we have to trigger reallocation now.
3e336261 1452 */
e283546c
EC		 1453 if ((reset_type == RESET_TYPE_ALL ||
1454 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
90c914d2 1455 efx_ef10_table_reset_mc_allocations(efx);
3e336261
JC		 1456 return rc;
1457}
1458
8127d661
BH		 1459#define EF10_DMA_STAT(ext_name, mcdi_name) \
1460 [EF10_STAT_ ## ext_name] = \
1461 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1462#define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1463 [EF10_STAT_ ## int_name] = \
1464 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1465#define EF10_OTHER_STAT(ext_name) \
1466 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1467
1468static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
e80ca013
DP		 1469 EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1470 EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1471 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1472 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1473 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1474 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1475 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1476 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1477 EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1478 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1479 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1480 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1481 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1482 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1483 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1484 EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1485 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1486 EF10_OTHER_STAT(port_rx_good_bytes),
1487 EF10_OTHER_STAT(port_rx_bad_bytes),
1488 EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1489 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1490 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1491 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1492 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1493 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1494 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1495 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1496 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1497 EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1498 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1499 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1500 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1501 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1502 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1503 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1504 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1505 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1506 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1507 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1508 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1509 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
9043f48f
EC		 1510 EFX_GENERIC_SW_STAT(rx_nodesc_trunc),
1511 EFX_GENERIC_SW_STAT(rx_noskb_drops),
e80ca013
DP		 1512 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1513 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1514 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1515 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1516 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1517 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1518 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1519 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1520 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1521 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1522 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1523 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
3c36a2ad
DP		 1524 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1525 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1526 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1527 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1528 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1529 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1530 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1531 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1532 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1533 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1534 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1535 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1536 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1537 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1538 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1539 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1540 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1541 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
f411b54d
EC		 1542 EF10_DMA_STAT(fec_uncorrected_errors, FEC_UNCORRECTED_ERRORS),
1543 EF10_DMA_STAT(fec_corrected_errors, FEC_CORRECTED_ERRORS),
1544 EF10_DMA_STAT(fec_corrected_symbols_lane0, FEC_CORRECTED_SYMBOLS_LANE0),
1545 EF10_DMA_STAT(fec_corrected_symbols_lane1, FEC_CORRECTED_SYMBOLS_LANE1),
1546 EF10_DMA_STAT(fec_corrected_symbols_lane2, FEC_CORRECTED_SYMBOLS_LANE2),
1547 EF10_DMA_STAT(fec_corrected_symbols_lane3, FEC_CORRECTED_SYMBOLS_LANE3),
2c0b6ee8
BK		 1548 EF10_DMA_STAT(ctpio_vi_busy_fallback, CTPIO_VI_BUSY_FALLBACK),
1549 EF10_DMA_STAT(ctpio_long_write_success, CTPIO_LONG_WRITE_SUCCESS),
1550 EF10_DMA_STAT(ctpio_missing_dbell_fail, CTPIO_MISSING_DBELL_FAIL),
1551 EF10_DMA_STAT(ctpio_overflow_fail, CTPIO_OVERFLOW_FAIL),
1552 EF10_DMA_STAT(ctpio_underflow_fail, CTPIO_UNDERFLOW_FAIL),
1553 EF10_DMA_STAT(ctpio_timeout_fail, CTPIO_TIMEOUT_FAIL),
1554 EF10_DMA_STAT(ctpio_noncontig_wr_fail, CTPIO_NONCONTIG_WR_FAIL),
1555 EF10_DMA_STAT(ctpio_frm_clobber_fail, CTPIO_FRM_CLOBBER_FAIL),
1556 EF10_DMA_STAT(ctpio_invalid_wr_fail, CTPIO_INVALID_WR_FAIL),
1557 EF10_DMA_STAT(ctpio_vi_clobber_fallback, CTPIO_VI_CLOBBER_FALLBACK),
1558 EF10_DMA_STAT(ctpio_unqualified_fallback, CTPIO_UNQUALIFIED_FALLBACK),
1559 EF10_DMA_STAT(ctpio_runt_fallback, CTPIO_RUNT_FALLBACK),
1560 EF10_DMA_STAT(ctpio_success, CTPIO_SUCCESS),
1561 EF10_DMA_STAT(ctpio_fallback, CTPIO_FALLBACK),
1562 EF10_DMA_STAT(ctpio_poison, CTPIO_POISON),
1563 EF10_DMA_STAT(ctpio_erase, CTPIO_ERASE),
8127d661
BH		 1564};
1565
e80ca013
DP		 1566#define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1567 (1ULL << EF10_STAT_port_tx_packets) | \
1568 (1ULL << EF10_STAT_port_tx_pause) | \
1569 (1ULL << EF10_STAT_port_tx_unicast) | \
1570 (1ULL << EF10_STAT_port_tx_multicast) | \
1571 (1ULL << EF10_STAT_port_tx_broadcast) | \
1572 (1ULL << EF10_STAT_port_rx_bytes) | \
1573 (1ULL << \
1574 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1575 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1576 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1577 (1ULL << EF10_STAT_port_rx_packets) | \
1578 (1ULL << EF10_STAT_port_rx_good) | \
1579 (1ULL << EF10_STAT_port_rx_bad) | \
1580 (1ULL << EF10_STAT_port_rx_pause) | \
1581 (1ULL << EF10_STAT_port_rx_control) | \
1582 (1ULL << EF10_STAT_port_rx_unicast) | \
1583 (1ULL << EF10_STAT_port_rx_multicast) | \
1584 (1ULL << EF10_STAT_port_rx_broadcast) | \
1585 (1ULL << EF10_STAT_port_rx_lt64) | \
1586 (1ULL << EF10_STAT_port_rx_64) | \
1587 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1588 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1589 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1590 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1591 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1592 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1593 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1594 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1595 (1ULL << EF10_STAT_port_rx_overflow) | \
1596 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
e4d112e4
EC		 1597 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1598 (1ULL << GENERIC_STAT_rx_noskb_drops))
8127d661 1599
69b365c3
EC		 1600/* On 7000 series NICs, these statistics are only provided by the 10G MAC.
1601 * For a 10G/40G switchable port we do not expose these because they might
1602 * not include all the packets they should.
1603 * On 8000 series NICs these statistics are always provided.
8127d661 1604 */
e80ca013
DP		 1605#define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1606 (1ULL << EF10_STAT_port_tx_lt64) | \
1607 (1ULL << EF10_STAT_port_tx_64) | \
1608 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1609 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1610 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1611 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1612 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1613 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
8127d661
BH		 1614
1615/* These statistics are only provided by the 40G MAC. For a 10G/40G
1616 * switchable port we do expose these because the errors will otherwise
1617 * be silent.
1618 */
e80ca013
DP		 1619#define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1620 (1ULL << EF10_STAT_port_rx_length_error))
8127d661 1621
568d7a00
EC		 1622/* These statistics are only provided if the firmware supports the
1623 * capability PM_AND_RXDP_COUNTERS.
1624 */
1625#define HUNT_PM_AND_RXDP_STAT_MASK ( \
e80ca013
DP		 1626 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1627 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1628 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1629 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1630 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1631 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1632 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1633 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1634 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1635 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1636 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1637 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
568d7a00 1638
f411b54d
EC		 1639/* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V2,
1640 * indicated by returning a value >= MC_CMD_MAC_NSTATS_V2 in
1641 * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS.
1642 * These bits are in the second u64 of the raw mask.
1643 */
1644#define EF10_FEC_STAT_MASK ( \
1645 (1ULL << (EF10_STAT_fec_uncorrected_errors - 64)) | \
1646 (1ULL << (EF10_STAT_fec_corrected_errors - 64)) | \
1647 (1ULL << (EF10_STAT_fec_corrected_symbols_lane0 - 64)) | \
1648 (1ULL << (EF10_STAT_fec_corrected_symbols_lane1 - 64)) | \
1649 (1ULL << (EF10_STAT_fec_corrected_symbols_lane2 - 64)) | \
1650 (1ULL << (EF10_STAT_fec_corrected_symbols_lane3 - 64)))
1651
2c0b6ee8
BK		 1652/* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V3,
1653 * indicated by returning a value >= MC_CMD_MAC_NSTATS_V3 in
1654 * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS.
1655 * These bits are in the second u64 of the raw mask.
1656 */
1657#define EF10_CTPIO_STAT_MASK ( \
2c0b6ee8
BK		 1658 (1ULL << (EF10_STAT_ctpio_vi_busy_fallback - 64)) | \
1659 (1ULL << (EF10_STAT_ctpio_long_write_success - 64)) | \
1660 (1ULL << (EF10_STAT_ctpio_missing_dbell_fail - 64)) | \
1661 (1ULL << (EF10_STAT_ctpio_overflow_fail - 64)) | \
1662 (1ULL << (EF10_STAT_ctpio_underflow_fail - 64)) | \
1663 (1ULL << (EF10_STAT_ctpio_timeout_fail - 64)) | \
1664 (1ULL << (EF10_STAT_ctpio_noncontig_wr_fail - 64)) | \
1665 (1ULL << (EF10_STAT_ctpio_frm_clobber_fail - 64)) | \
1666 (1ULL << (EF10_STAT_ctpio_invalid_wr_fail - 64)) | \
1667 (1ULL << (EF10_STAT_ctpio_vi_clobber_fallback - 64)) | \
1668 (1ULL << (EF10_STAT_ctpio_unqualified_fallback - 64)) | \
1669 (1ULL << (EF10_STAT_ctpio_runt_fallback - 64)) | \
1670 (1ULL << (EF10_STAT_ctpio_success - 64)) | \
1671 (1ULL << (EF10_STAT_ctpio_fallback - 64)) | \
1672 (1ULL << (EF10_STAT_ctpio_poison - 64)) | \
1673 (1ULL << (EF10_STAT_ctpio_erase - 64)))
1674
4bae913b 1675static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
8127d661 1676{
4bae913b 1677 u64 raw_mask = HUNT_COMMON_STAT_MASK;
8127d661 1678 u32 port_caps = efx_mcdi_phy_get_caps(efx);
568d7a00 1679 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661 1680
3c36a2ad
DP		 1681 if (!(efx->mcdi->fn_flags &
1682 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1683 return 0;
1684
69b365c3 1685 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) {
4bae913b 1686 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
69b365c3
EC		 1687 /* 8000 series have everything even at 40G */
1688 if (nic_data->datapath_caps2 &
1689 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN))
1690 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1691 } else {
4bae913b 1692 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
69b365c3 1693 }
568d7a00
EC		 1694
1695 if (nic_data->datapath_caps &
1696 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1697 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1698
4bae913b
EC		 1699 return raw_mask;
1700}
1701
1702static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1703{
d94619cd 1704 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3c36a2ad
DP		 1705 u64 raw_mask[2];
1706
1707 raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1708
d94619cd
DP		 1709 /* Only show vadaptor stats when EVB capability is present */
1710 if (nic_data->datapath_caps &
1711 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1712 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
f411b54d 1713 raw_mask[1] = (1ULL << (EF10_STAT_V1_COUNT - 64)) - 1;
d94619cd
DP		 1714 } else {
1715 raw_mask[1] = 0;
1716 }
f411b54d
EC		 1717 /* Only show FEC stats when NIC supports MC_CMD_MAC_STATS_V2 */
1718 if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V2)
1719 raw_mask[1] |= EF10_FEC_STAT_MASK;
4bae913b 1720
2c0b6ee8
BK		 1721 /* CTPIO stats appear in V3. Only show them on devices that actually
1722 * support CTPIO. Although this driver doesn't use CTPIO others might,
1723 * and we may be reporting the stats for the underlying port.
1724 */
1725 if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V3 &&
1726 (nic_data->datapath_caps2 &
1727 (1 << MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN)))
1728 raw_mask[1] |= EF10_CTPIO_STAT_MASK;
1729
4bae913b 1730#if BITS_PER_LONG == 64
e70c70c3 1731 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2);
3c36a2ad
DP		 1732 mask[0] = raw_mask[0];
1733 mask[1] = raw_mask[1];
4bae913b 1734#else
e70c70c3 1735 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3);
3c36a2ad
DP		 1736 mask[0] = raw_mask[0] & 0xffffffff;
1737 mask[1] = raw_mask[0] >> 32;
1738 mask[2] = raw_mask[1] & 0xffffffff;
4bae913b 1739#endif
8127d661
BH		 1740}
1741
1742static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1743{
4bae913b
EC		 1744 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1745
1746 efx_ef10_get_stat_mask(efx, mask);
8127d661 1747 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
4bae913b 1748 mask, names);
8127d661
BH		 1749}
1750
cab351be
JK		 1751static void efx_ef10_get_fec_stats(struct efx_nic *efx,
1752 struct ethtool_fec_stats *fec_stats)
1753{
1754 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1755 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1756 u64 *stats = nic_data->stats;
1757
1758 efx_ef10_get_stat_mask(efx, mask);
1759 if (test_bit(EF10_STAT_fec_corrected_errors, mask))
1760 fec_stats->corrected_blocks.total =
1761 stats[EF10_STAT_fec_corrected_errors];
1762 if (test_bit(EF10_STAT_fec_uncorrected_errors, mask))
1763 fec_stats->uncorrectable_blocks.total =
1764 stats[EF10_STAT_fec_uncorrected_errors];
1765}
1766
d7788196
DP		 1767static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1768 struct rtnl_link_stats64 *core_stats)
1769{
1770 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1771 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1772 u64 *stats = nic_data->stats;
1773 size_t stats_count = 0, index;
1774
1775 efx_ef10_get_stat_mask(efx, mask);
1776
1777 if (full_stats) {
1778 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1779 if (efx_ef10_stat_desc[index].name) {
1780 *full_stats++ = stats[index];
1781 ++stats_count;
1782 }
1783 }
1784 }
1785
fbe4307e
BK		 1786 if (!core_stats)
1787 return stats_count;
1788
1789 if (nic_data->datapath_caps &
1790 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1791 /* Use vadaptor stats. */
0fc95fca
DP		 1792 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1793 stats[EF10_STAT_rx_multicast] +
1794 stats[EF10_STAT_rx_broadcast];
1795 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1796 stats[EF10_STAT_tx_multicast] +
1797 stats[EF10_STAT_tx_broadcast];
1798 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1799 stats[EF10_STAT_rx_multicast_bytes] +
1800 stats[EF10_STAT_rx_broadcast_bytes];
1801 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1802 stats[EF10_STAT_tx_multicast_bytes] +
1803 stats[EF10_STAT_tx_broadcast_bytes];
1804 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
d7788196 1805 stats[GENERIC_STAT_rx_noskb_drops];
0fc95fca
DP		 1806 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1807 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1808 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1809 core_stats->rx_errors = core_stats->rx_crc_errors;
1810 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
fbe4307e
BK		 1811 } else {
1812 /* Use port stats. */
1813 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1814 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1815 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1816 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1817 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1818 stats[GENERIC_STAT_rx_nodesc_trunc] +
1819 stats[GENERIC_STAT_rx_noskb_drops];
1820 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1821 core_stats->rx_length_errors =
1822 stats[EF10_STAT_port_rx_gtjumbo] +
1823 stats[EF10_STAT_port_rx_length_error];
1824 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1825 core_stats->rx_frame_errors =
1826 stats[EF10_STAT_port_rx_align_error];
1827 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1828 core_stats->rx_errors = (core_stats->rx_length_errors +
1829 core_stats->rx_crc_errors +
1830 core_stats->rx_frame_errors);
d7788196
DP		 1831 }
1832
1833 return stats_count;
1834}
1835
d3142c19
EC		 1836static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1837 struct rtnl_link_stats64 *core_stats)
8127d661
BH		 1838{
1839 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4bae913b 1840 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
8127d661 1841 u64 *stats = nic_data->stats;
8127d661 1842
4bae913b
EC		 1843 efx_ef10_get_stat_mask(efx, mask);
1844
d3142c19
EC		 1845 efx_nic_copy_stats(efx, nic_data->mc_stats);
1846 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
1847 mask, stats, nic_data->mc_stats, false);
8127d661
BH		 1848
1849 /* Update derived statistics */
e80ca013
DP		 1850 efx_nic_fix_nodesc_drop_stat(efx,
1851 &stats[EF10_STAT_port_rx_nodesc_drops]);
d3142c19
EC		 1852 /* MC Firmware reads RX_BYTES and RX_GOOD_BYTES from the MAC.
1853 * It then calculates RX_BAD_BYTES and DMAs it to us with RX_BYTES.
1854 * We report these as port_rx_ stats. We are not given RX_GOOD_BYTES.
1855 * Here we calculate port_rx_good_bytes.
1856 */
e80ca013
DP		 1857 stats[EF10_STAT_port_rx_good_bytes] =
1858 stats[EF10_STAT_port_rx_bytes] -
1859 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
d3142c19
EC		 1860
1861 /* The asynchronous reads used to calculate RX_BAD_BYTES in
1862 * MC Firmware are done such that we should not see an increase in
1863 * RX_BAD_BYTES when a good packet has arrived. Unfortunately this
1864 * does mean that the stat can decrease at times. Here we do not
1865 * update the stat unless it has increased or has gone to zero
1866 * (In the case of the NIC rebooting).
1867 * Please see Bug 33781 for a discussion of why things work this way.
1868 */
e80ca013
DP		 1869 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1870 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
e4d112e4 1871 efx_update_sw_stats(efx, stats);
8127d661 1872
d7788196
DP		 1873 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1874}
8127d661 1875
d7788196 1876static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
efd7ed0f 1877 __must_hold(&efx->stats_lock)
d7788196
DP		 1878{
1879 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1880 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1881 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1882 __le64 generation_start, generation_end;
1883 u64 *stats = nic_data->stats;
c1be4821 1884 u32 dma_len = efx->num_mac_stats * sizeof(u64);
d7788196
DP		 1885 struct efx_buffer stats_buf;
1886 __le64 *dma_stats;
1887 int rc;
1888
f00bf230
DP		 1889 spin_unlock_bh(&efx->stats_lock);
1890
d7788196
DP		 1891 efx_ef10_get_stat_mask(efx, mask);
1892
caa241f0 1893 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_KERNEL);
f00bf230
DP		 1894 if (rc) {
1895 spin_lock_bh(&efx->stats_lock);
d7788196 1896 return rc;
f00bf230 1897 }
d7788196
DP		 1898
1899 dma_stats = stats_buf.addr;
c1be4821 1900 dma_stats[efx->num_mac_stats - 1] = EFX_MC_STATS_GENERATION_INVALID;
d7788196
DP		 1901
1902 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1903 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
0fc95fca 1904 MAC_STATS_IN_DMA, 1);
d7788196
DP		 1905 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1906 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1907
6dd4859b
DP		 1908 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1909 NULL, 0, NULL);
d7788196 1910 spin_lock_bh(&efx->stats_lock);
6dd4859b
DP		 1911 if (rc) {
1912 /* Expect ENOENT if DMA queues have not been set up */
1913 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1914 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1915 sizeof(inbuf), NULL, 0, rc);
d7788196 1916 goto out;
6dd4859b 1917 }
d7788196 1918
c1be4821 1919 generation_end = dma_stats[efx->num_mac_stats - 1];
0fc95fca
DP		 1920 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1921 WARN_ON_ONCE(1);
d7788196 1922 goto out;
0fc95fca 1923 }
d7788196
DP		 1924 rmb();
1925 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1926 stats, stats_buf.addr, false);
1927 rmb();
1928 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1929 if (generation_end != generation_start) {
1930 rc = -EAGAIN;
1931 goto out;
8127d661
BH		 1932 }
1933
d7788196
DP		 1934 efx_update_sw_stats(efx, stats);
1935out:
1936 efx_nic_free_buffer(efx, &stats_buf);
1937 return rc;
1938}
1939
1940static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1941 struct rtnl_link_stats64 *core_stats)
1942{
1943 if (efx_ef10_try_update_nic_stats_vf(efx))
1944 return 0;
1945
1946 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
8127d661
BH		 1947}
1948
623b9988
EC		 1949static size_t efx_ef10_update_stats_atomic_vf(struct efx_nic *efx, u64 *full_stats,
1950 struct rtnl_link_stats64 *core_stats)
1951{
1952 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1953
1954 /* In atomic context, cannot update HW stats. Just update the
1955 * software stats and return so the caller can continue.
1956 */
1957 efx_update_sw_stats(efx, nic_data->stats);
1958 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1959}
1960
8127d661
BH		 1961static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1962{
1963 struct efx_nic *efx = channel->efx;
539de7c5 1964 unsigned int mode, usecs;
8127d661
BH		 1965 efx_dword_t timer_cmd;
1966
539de7c5 1967 if (channel->irq_moderation_us) {
8127d661 1968 mode = 3;
539de7c5 1969 usecs = channel->irq_moderation_us;
8127d661
BH		 1970 } else {
1971 mode = 0;
539de7c5 1972 usecs = 0;
8127d661
BH		 1973 }
1974
539de7c5
BK		 1975 if (EFX_EF10_WORKAROUND_61265(efx)) {
1976 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN);
1977 unsigned int ns = usecs * 1000;
1978
1979 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE,
1980 channel->channel);
1981 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns);
1982 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns);
1983 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode);
1984
1985 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR,
1986 inbuf, sizeof(inbuf), 0, NULL, 0);
1987 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
1988 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1989
8127d661
BH		 1990 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1991 EFE_DD_EVQ_IND_TIMER_FLAGS,
1992 ERF_DD_EVQ_IND_TIMER_MODE, mode,
539de7c5 1993 ERF_DD_EVQ_IND_TIMER_VAL, ticks);
8127d661
BH		 1994 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1995 channel->channel);
1996 } else {
539de7c5
BK		 1997 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1998
0bc959a9
BK		 1999 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
2000 ERF_DZ_TC_TIMER_VAL, ticks,
2001 ERF_FZ_TC_TMR_REL_VAL, ticks);
8127d661
BH		 2002 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
2003 channel->channel);
2004 }
2005}
2006
02246a7f
SS		 2007static void efx_ef10_get_wol_vf(struct efx_nic *efx,
2008 struct ethtool_wolinfo *wol) {}
2009
2010static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
2011{
2012 return -EOPNOTSUPP;
2013}
2014
8127d661
BH		 2015static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
2016{
2017 wol->supported = 0;
2018 wol->wolopts = 0;
2019 memset(&wol->sopass, 0, sizeof(wol->sopass));
2020}
2021
2022static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
2023{
2024 if (type != 0)
2025 return -EINVAL;
2026 return 0;
2027}
2028
2029static void efx_ef10_mcdi_request(struct efx_nic *efx,
2030 const efx_dword_t *hdr, size_t hdr_len,
2031 const efx_dword_t *sdu, size_t sdu_len)
2032{
2033 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2034 u8 *pdu = nic_data->mcdi_buf.addr;
2035
2036 memcpy(pdu, hdr, hdr_len);
2037 memcpy(pdu + hdr_len, sdu, sdu_len);
2038 wmb();
2039
2040 /* The hardware provides 'low' and 'high' (doorbell) registers
2041 * for passing the 64-bit address of an MCDI request to
2042 * firmware. However the dwords are swapped by firmware. The
2043 * least significant bits of the doorbell are then 0 for all
2044 * MCDI requests due to alignment.
2045 */
2046 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
2047 ER_DZ_MC_DB_LWRD);
2048 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
2049 ER_DZ_MC_DB_HWRD);
2050}
2051
2052static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
2053{
2054 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2055 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
2056
2057 rmb();
2058 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
2059}
2060
2061static void
2062efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
2063 size_t offset, size_t outlen)
2064{
2065 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2066 const u8 *pdu = nic_data->mcdi_buf.addr;
2067
2068 memcpy(outbuf, pdu + offset, outlen);
2069}
2070
c577e59e
DP		 2071static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
2072{
2073 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2074
2075 /* All our allocations have been reset */
90c914d2 2076 efx_ef10_table_reset_mc_allocations(efx);
c577e59e
DP		 2077
2078 /* The datapath firmware might have been changed */
2079 nic_data->must_check_datapath_caps = true;
2080
2081 /* MAC statistics have been cleared on the NIC; clear the local
2082 * statistic that we update with efx_update_diff_stat().
2083 */
2084 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
2085}
2086
8127d661
BH		 2087static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
2088{
2089 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2090 int rc;
2091
2092 rc = efx_ef10_get_warm_boot_count(efx);
2093 if (rc < 0) {
2094 /* The firmware is presumably in the process of
2095 * rebooting. However, we are supposed to report each
2096 * reboot just once, so we must only do that once we
2097 * can read and store the updated warm boot count.
2098 */
2099 return 0;
2100 }
2101
2102 if (rc == nic_data->warm_boot_count)
2103 return 0;
2104
2105 nic_data->warm_boot_count = rc;
c577e59e 2106 efx_ef10_mcdi_reboot_detected(efx);
869070c5 2107
8127d661
BH		 2108 return -EIO;
2109}
2110
2111/* Handle an MSI interrupt
2112 *
2113 * Handle an MSI hardware interrupt. This routine schedules event
2114 * queue processing. No interrupt acknowledgement cycle is necessary.
2115 * Also, we never need to check that the interrupt is for us, since
2116 * MSI interrupts cannot be shared.
2117 */
2118static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
2119{
2120 struct efx_msi_context *context = dev_id;
2121 struct efx_nic *efx = context->efx;
2122
2123 netif_vdbg(efx, intr, efx->net_dev,
2124 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
2125
6aa7de05 2126 if (likely(READ_ONCE(efx->irq_soft_enabled))) {
8127d661
BH		 2127 /* Note test interrupts */
2128 if (context->index == efx->irq_level)
2129 efx->last_irq_cpu = raw_smp_processor_id();
2130
2131 /* Schedule processing of the channel */
2132 efx_schedule_channel_irq(efx->channel[context->index]);
2133 }
2134
2135 return IRQ_HANDLED;
2136}
2137
2138static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
2139{
2140 struct efx_nic *efx = dev_id;
6aa7de05 2141 bool soft_enabled = READ_ONCE(efx->irq_soft_enabled);
8127d661
BH		 2142 struct efx_channel *channel;
2143 efx_dword_t reg;
2144 u32 queues;
2145
2146 /* Read the ISR which also ACKs the interrupts */
2147 efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
2148 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
2149
2150 if (queues == 0)
2151 return IRQ_NONE;
2152
2153 if (likely(soft_enabled)) {
2154 /* Note test interrupts */
2155 if (queues & (1U << efx->irq_level))
2156 efx->last_irq_cpu = raw_smp_processor_id();
2157
2158 efx_for_each_channel(channel, efx) {
2159 if (queues & 1)
2160 efx_schedule_channel_irq(channel);
2161 queues >>= 1;
2162 }
2163 }
2164
2165 netif_vdbg(efx, intr, efx->net_dev,
2166 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
2167 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
2168
2169 return IRQ_HANDLED;
2170}
2171
942e298e 2172static int efx_ef10_irq_test_generate(struct efx_nic *efx)
8127d661
BH		 2173{
2174 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
2175
942e298e
JC		 2176 if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true,
2177 NULL) == 0)
2178 return -ENOTSUPP;
2179
8127d661
BH		 2180 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
2181
2182 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
942e298e 2183 return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
8127d661
BH		 2184 inbuf, sizeof(inbuf), NULL, 0, NULL);
2185}
2186
2187static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
2188{
85d43fdb
EC		 2189 /* low two bits of label are what we want for type */
2190 BUILD_BUG_ON((EFX_TXQ_TYPE_OUTER_CSUM | EFX_TXQ_TYPE_INNER_CSUM) != 3);
2191 tx_queue->type = tx_queue->label & 3;
8127d661
BH		 2192 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
2193 (tx_queue->ptr_mask + 1) *
2194 sizeof(efx_qword_t),
2195 GFP_KERNEL);
2196}
2197
2198/* This writes to the TX_DESC_WPTR and also pushes data */
2199static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
2200 const efx_qword_t *txd)
2201{
2202 unsigned int write_ptr;
2203 efx_oword_t reg;
2204
2205 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2206 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
2207 reg.qword[0] = *txd;
2208 efx_writeo_page(tx_queue->efx, &reg,
2209 ER_DZ_TX_DESC_UPD, tx_queue->queue);
2210}
2211
e9117e50
BK		 2212/* Add Firmware-Assisted TSO v2 option descriptors to a queue.
2213 */
1679c72c
EC		 2214int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue, struct sk_buff *skb,
2215 bool *data_mapped)
e9117e50
BK		 2216{
2217 struct efx_tx_buffer *buffer;
0ce8df66
EC		 2218 u16 inner_ipv4_id = 0;
2219 u16 outer_ipv4_id = 0;
e9117e50
BK		 2220 struct tcphdr *tcp;
2221 struct iphdr *ip;
0ce8df66 2222 u16 ip_tot_len;
e9117e50
BK		 2223 u32 seqnum;
2224 u32 mss;
2225
e01b16a7 2226 EFX_WARN_ON_ONCE_PARANOID(tx_queue->tso_version != 2);
e9117e50
BK		 2227
2228 mss = skb_shinfo(skb)->gso_size;
2229
2230 if (unlikely(mss < 4)) {
2231 WARN_ONCE(1, "MSS of %u is too small for TSO v2\n", mss);
2232 return -EINVAL;
2233 }
2234
0ce8df66
EC		 2235 if (skb->encapsulation) {
2236 if (!tx_queue->tso_encap)
2237 return -EINVAL;
2238 ip = ip_hdr(skb);
2239 if (ip->version == 4)
2240 outer_ipv4_id = ntohs(ip->id);
2241
2242 ip = inner_ip_hdr(skb);
2243 tcp = inner_tcp_hdr(skb);
2244 } else {
2245 ip = ip_hdr(skb);
2246 tcp = tcp_hdr(skb);
2247 }
2248
2249 /* 8000-series EF10 hardware requires that IP Total Length be
2250 * greater than or equal to the value it will have in each segment
2251 * (which is at most mss + 208 + TCP header length), but also less
2252 * than (0x10000 - inner_network_header). Otherwise the TCP
2253 * checksum calculation will be broken for encapsulated packets.
2254 * We fill in ip->tot_len with 0xff30, which should satisfy the
2255 * first requirement unless the MSS is ridiculously large (which
2256 * should be impossible as the driver max MTU is 9216); it is
2257 * guaranteed to satisfy the second as we only attempt TSO if
2258 * inner_network_header <= 208.
2259 */
2260 ip_tot_len = -EFX_TSO2_MAX_HDRLEN;
2261 EFX_WARN_ON_ONCE_PARANOID(mss + EFX_TSO2_MAX_HDRLEN +
2262 (tcp->doff << 2u) > ip_tot_len);
2263
e9117e50 2264 if (ip->version == 4) {
0ce8df66 2265 ip->tot_len = htons(ip_tot_len);
e9117e50 2266 ip->check = 0;
0ce8df66 2267 inner_ipv4_id = ntohs(ip->id);
e9117e50 2268 } else {
0ce8df66 2269 ((struct ipv6hdr *)ip)->payload_len = htons(ip_tot_len);
e9117e50
BK		 2270 }
2271
e9117e50
BK		 2272 seqnum = ntohl(tcp->seq);
2273
2274 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2275
2276 buffer->flags = EFX_TX_BUF_OPTION;
2277 buffer->len = 0;
2278 buffer->unmap_len = 0;
2279 EFX_POPULATE_QWORD_5(buffer->option,
2280 ESF_DZ_TX_DESC_IS_OPT, 1,
2281 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2282 ESF_DZ_TX_TSO_OPTION_TYPE,
2283 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
0ce8df66 2284 ESF_DZ_TX_TSO_IP_ID, inner_ipv4_id,
e9117e50
BK		 2285 ESF_DZ_TX_TSO_TCP_SEQNO, seqnum
2286 );
2287 ++tx_queue->insert_count;
2288
2289 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2290
2291 buffer->flags = EFX_TX_BUF_OPTION;
2292 buffer->len = 0;
2293 buffer->unmap_len = 0;
0ce8df66 2294 EFX_POPULATE_QWORD_5(buffer->option,
e9117e50
BK		 2295 ESF_DZ_TX_DESC_IS_OPT, 1,
2296 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2297 ESF_DZ_TX_TSO_OPTION_TYPE,
2298 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
0ce8df66 2299 ESF_DZ_TX_TSO_OUTER_IPID, outer_ipv4_id,
e9117e50
BK		 2300 ESF_DZ_TX_TSO_TCP_MSS, mss
2301 );
2302 ++tx_queue->insert_count;
2303
2304 return 0;
2305}
2306
46d1efd8
EC		 2307static u32 efx_ef10_tso_versions(struct efx_nic *efx)
2308{
2309 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2310 u32 tso_versions = 0;
2311
2312 if (nic_data->datapath_caps &
2313 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))
2314 tso_versions |= BIT(1);
2315 if (nic_data->datapath_caps2 &
2316 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))
2317 tso_versions |= BIT(2);
2318 return tso_versions;
2319}
2320
8127d661
BH		 2321static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
2322{
044588b9 2323 bool csum_offload = tx_queue->type & EFX_TXQ_TYPE_OUTER_CSUM;
85d43fdb 2324 bool inner_csum = tx_queue->type & EFX_TXQ_TYPE_INNER_CSUM;
8127d661
BH		 2325 struct efx_channel *channel = tx_queue->channel;
2326 struct efx_nic *efx = tx_queue->efx;
8ee4c907 2327 struct efx_ef10_nic_data *nic_data;
8127d661
BH		 2328 efx_qword_t *txd;
2329 int rc;
8ee4c907
AM		 2330
2331 nic_data = efx->nic_data;
8127d661 2332
50663fe1
MH		 2333 /* Only attempt to enable TX timestamping if we have the license for it,
2334 * otherwise TXQ init will fail
2335 */
2336 if (!(nic_data->licensed_features &
6aa47c87 2337 (1 << LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN))) {
50663fe1 2338 tx_queue->timestamping = false;
6aa47c87
MH		 2339 /* Disable sync events on this channel. */
2340 if (efx->type->ptp_set_ts_sync_events)
2341 efx->type->ptp_set_ts_sync_events(efx, false, false);
2342 }
50663fe1 2343
e9117e50
BK		 2344 /* TSOv2 is a limited resource that can only be configured on a limited
2345 * number of queues. TSO without checksum offload is not really a thing,
2346 * so we only enable it for those queues.
3990a8ff
CM		 2347 * TSOv2 cannot be used with Hardware timestamping, and is never needed
2348 * for XDP tx.
e9117e50 2349 */
1679c72c
EC		 2350 if (efx_has_cap(efx, TX_TSO_V2)) {
2351 if ((csum_offload || inner_csum) &&
2352 !tx_queue->timestamping && !tx_queue->xdp_tx) {
2353 tx_queue->tso_version = 2;
2354 netif_dbg(efx, hw, efx->net_dev, "Using TSOv2 for channel %u\n",
2355 channel->channel);
2356 }
2357 } else if (efx_has_cap(efx, TX_TSO)) {
2358 tx_queue->tso_version = 1;
e9117e50
BK		 2359 }
2360
1679c72c 2361 rc = efx_mcdi_tx_init(tx_queue);
8ee4c907
AM		 2362 if (rc)
2363 goto fail;
8127d661
BH		 2364
2365 /* A previous user of this TX queue might have set us up the
2366 * bomb by writing a descriptor to the TX push collector but
2367 * not the doorbell. (Each collector belongs to a port, not a
2368 * queue or function, so cannot easily be reset.) We must
2369 * attempt to push a no-op descriptor in its place.
2370 */
2371 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
2372 tx_queue->insert_count = 1;
2373 txd = efx_tx_desc(tx_queue, 0);
85d43fdb 2374 EFX_POPULATE_QWORD_7(*txd,
8127d661
BH		 2375 ESF_DZ_TX_DESC_IS_OPT, true,
2376 ESF_DZ_TX_OPTION_TYPE,
2377 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
2378 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
1679c72c 2379 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload && tx_queue->tso_version != 2,
85d43fdb 2380 ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM, inner_csum,
1679c72c 2381 ESF_DZ_TX_OPTION_INNER_IP_CSUM, inner_csum && tx_queue->tso_version != 2,
b9b603d4 2382 ESF_DZ_TX_TIMESTAMP, tx_queue->timestamping);
8127d661 2383 tx_queue->write_count = 1;
93171b14 2384
0ce8df66
EC		 2385 if (tx_queue->tso_version == 2 && efx_has_cap(efx, TX_TSO_V2_ENCAP))
2386 tx_queue->tso_encap = true;
2387
8127d661
BH		 2388 wmb();
2389 efx_ef10_push_tx_desc(tx_queue, txd);
2390
2391 return;
2392
2393fail:
48ce5634
BH		 2394 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
2395 tx_queue->queue);
8127d661
BH		 2396}
2397
8127d661
BH		 2398/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
2399static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
2400{
2401 unsigned int write_ptr;
2402 efx_dword_t reg;
2403
2404 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2405 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
2406 efx_writed_page(tx_queue->efx, &reg,
2407 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
2408}
2409
e9117e50
BK		 2410#define EFX_EF10_MAX_TX_DESCRIPTOR_LEN 0x3fff
2411
2412static unsigned int efx_ef10_tx_limit_len(struct efx_tx_queue *tx_queue,
2413 dma_addr_t dma_addr, unsigned int len)
2414{
2415 if (len > EFX_EF10_MAX_TX_DESCRIPTOR_LEN) {
2416 /* If we need to break across multiple descriptors we should
2417 * stop at a page boundary. This assumes the length limit is
2418 * greater than the page size.
2419 */
2420 dma_addr_t end = dma_addr + EFX_EF10_MAX_TX_DESCRIPTOR_LEN;
2421
2422 BUILD_BUG_ON(EFX_EF10_MAX_TX_DESCRIPTOR_LEN < EFX_PAGE_SIZE);
2423 len = (end & (~(EFX_PAGE_SIZE - 1))) - dma_addr;
2424 }
2425
2426 return len;
2427}
2428
8127d661
BH		 2429static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
2430{
2431 unsigned int old_write_count = tx_queue->write_count;
2432 struct efx_tx_buffer *buffer;
2433 unsigned int write_ptr;
2434 efx_qword_t *txd;
2435
1c0544d2 2436 tx_queue->xmit_pending = false;
b2663a4f
MH		 2437 if (unlikely(tx_queue->write_count == tx_queue->insert_count))
2438 return;
8127d661
BH		 2439
2440 do {
2441 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2442 buffer = &tx_queue->buffer[write_ptr];
2443 txd = efx_tx_desc(tx_queue, write_ptr);
2444 ++tx_queue->write_count;
2445
2446 /* Create TX descriptor ring entry */
2447 if (buffer->flags & EFX_TX_BUF_OPTION) {
2448 *txd = buffer->option;
de1deff9
EC		 2449 if (EFX_QWORD_FIELD(*txd, ESF_DZ_TX_OPTION_TYPE) == 1)
2450 /* PIO descriptor */
2451 tx_queue->packet_write_count = tx_queue->write_count;
8127d661 2452 } else {
de1deff9 2453 tx_queue->packet_write_count = tx_queue->write_count;
8127d661
BH		 2454 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
2455 EFX_POPULATE_QWORD_3(
2456 *txd,
2457 ESF_DZ_TX_KER_CONT,
2458 buffer->flags & EFX_TX_BUF_CONT,
2459 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
2460 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
2461 }
2462 } while (tx_queue->write_count != tx_queue->insert_count);
2463
2464 wmb(); /* Ensure descriptors are written before they are fetched */
2465
2466 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
2467 txd = efx_tx_desc(tx_queue,
2468 old_write_count & tx_queue->ptr_mask);
2469 efx_ef10_push_tx_desc(tx_queue, txd);
2470 ++tx_queue->pushes;
2471 } else {
2472 efx_ef10_notify_tx_desc(tx_queue);
2473 }
2474}
2475
fd14e5fd
EC		 2476static int efx_ef10_probe_multicast_chaining(struct efx_nic *efx)
2477{
2478 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2479 unsigned int enabled, implemented;
2480 bool want_workaround_26807;
2481 int rc;
2482
2483 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
2484 if (rc == -ENOSYS) {
2485 /* GET_WORKAROUNDS was implemented before this workaround,
2486 * thus it must be unavailable in this firmware.
2487 */
2488 nic_data->workaround_26807 = false;
2489 return 0;
2490 }
2491 if (rc)
2492 return rc;
2493 want_workaround_26807 =
2494 implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807;
2495 nic_data->workaround_26807 =
2496 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
2497
2498 if (want_workaround_26807 && !nic_data->workaround_26807) {
2499 unsigned int flags;
2500
2501 rc = efx_mcdi_set_workaround(efx,
2502 MC_CMD_WORKAROUND_BUG26807,
2503 true, &flags);
2504 if (!rc) {
2505 if (flags &
2506 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
2507 netif_info(efx, drv, efx->net_dev,
2508 "other functions on NIC have been reset\n");
2509
2510 /* With MCFW v4.6.x and earlier, the
2511 * boot count will have incremented,
2512 * so re-read the warm_boot_count
2513 * value now to ensure this function
2514 * doesn't think it has changed next
2515 * time it checks.
2516 */
2517 rc = efx_ef10_get_warm_boot_count(efx);
2518 if (rc >= 0) {
2519 nic_data->warm_boot_count = rc;
2520 rc = 0;
2521 }
2522 }
2523 nic_data->workaround_26807 = true;
2524 } else if (rc == -EPERM) {
2525 rc = 0;
2526 }
2527 }
2528 return rc;
2529}
2530
2531static int efx_ef10_filter_table_probe(struct efx_nic *efx)
2532{
2533 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2534 int rc = efx_ef10_probe_multicast_chaining(efx);
ed02112c 2535 struct efx_mcdi_filter_vlan *vlan;
fd14e5fd
EC		 2536
2537 if (rc)
2538 return rc;
2539 rc = efx_mcdi_filter_table_probe(efx, nic_data->workaround_26807);
2540
2541 if (rc)
2542 return rc;
2543
ed02112c
EC		 2544 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
2545 rc = efx_mcdi_filter_add_vlan(efx, vlan->vid);
2546 if (rc)
2547 goto fail_add_vlan;
2548 }
fd14e5fd 2549 return 0;
ed02112c
EC		 2550
2551fail_add_vlan:
2552 efx_mcdi_filter_table_remove(efx);
2553 return rc;
fd14e5fd
EC		 2554}
2555
8127d661
BH		 2556/* This creates an entry in the RX descriptor queue */
2557static inline void
2558efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
a33a4c73 2559{
8127d661
BH		 2560 struct efx_rx_buffer *rx_buf;
2561 efx_qword_t *rxd;
a33a4c73 2562
8127d661
BH		 2563 rxd = efx_rx_desc(rx_queue, index);
2564 rx_buf = efx_rx_buffer(rx_queue, index);
2565 EFX_POPULATE_QWORD_2(*rxd,
2566 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2567 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
a33a4c73
EC		 2568}
2569
8127d661 2570static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
a33a4c73 2571{
8127d661
BH		 2572 struct efx_nic *efx = rx_queue->efx;
2573 unsigned int write_count;
2574 efx_dword_t reg;
a33a4c73 2575
8127d661
BH		 2576 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2577 write_count = rx_queue->added_count & ~7;
2578 if (rx_queue->notified_count == write_count)
a33a4c73 2579 return;
8127d661 2580
8127d661
BH		 2581 do
2582 efx_ef10_build_rx_desc(
2583 rx_queue,
2584 rx_queue->notified_count & rx_queue->ptr_mask);
2585 while (++rx_queue->notified_count != write_count);
dcb4123c 2586
8127d661
BH		 2587 wmb();
2588 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
2589 write_count & rx_queue->ptr_mask);
2590 efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
2591 efx_rx_queue_index(rx_queue));
2592}
8127d661 2593
8127d661 2594static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
8127d661 2595
8127d661
BH		 2596static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
2597{
2598 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2599 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2600 efx_qword_t event;
8127d661 2601
8127d661
BH		 2602 EFX_POPULATE_QWORD_2(event,
2603 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2604 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
8127d661 2605
8127d661 2606 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
267c0157 2607
8127d661
BH		 2608 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2609 * already swapped the data to little-endian order.
2610 */
2611 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2612 sizeof(efx_qword_t));
a33a4c73 2613
8127d661
BH		 2614 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
2615 inbuf, sizeof(inbuf), 0,
2616 efx_ef10_rx_defer_refill_complete, 0);
8127d661
BH		 2617}
2618
8127d661
BH		 2619static void
2620efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
2621 int rc, efx_dword_t *outbuf,
2622 size_t outlen_actual)
8127d661 2623{
8127d661 2624 /* nothing to do */
8127d661
BH		 2625}
2626
8127d661 2627static int efx_ef10_ev_init(struct efx_channel *channel)
8127d661 2628{
8127d661
BH		 2629 struct efx_nic *efx = channel->efx;
2630 struct efx_ef10_nic_data *nic_data;
4438b587 2631 bool use_v2, cut_thru;
8127d661 2632
8127d661 2633 nic_data = efx->nic_data;
4438b587
AM		 2634 use_v2 = nic_data->datapath_caps2 &
2635 1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN;
2636 cut_thru = !(nic_data->datapath_caps &
2637 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
fd14e5fd 2638 return efx_mcdi_ev_init(channel, cut_thru, use_v2);
267c0157 2639}
8127d661 2640
8127d661
BH		 2641static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
2642 unsigned int rx_queue_label)
267c0157 2643{
8127d661 2644 struct efx_nic *efx = rx_queue->efx;
267c0157 2645
8127d661
BH		 2646 netif_info(efx, hw, efx->net_dev,
2647 "rx event arrived on queue %d labeled as queue %u\n",
2648 efx_rx_queue_index(rx_queue), rx_queue_label);
8127d661 2649
8127d661 2650 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
267c0157
JC		 2651}
2652
8127d661
BH		 2653static void
2654efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
2655 unsigned int actual, unsigned int expected)
42356d9a 2656{
8127d661
BH		 2657 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
2658 struct efx_nic *efx = rx_queue->efx;
42356d9a 2659
8127d661
BH		 2660 netif_info(efx, hw, efx->net_dev,
2661 "dropped %d events (index=%d expected=%d)\n",
2662 dropped, actual, expected);
42356d9a 2663
8127d661 2664 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
42356d9a
EC		 2665}
2666
8127d661
BH		 2667/* partially received RX was aborted. clean up. */
2668static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
a707d188 2669{
8127d661 2670 unsigned int rx_desc_ptr;
a707d188 2671
8127d661
BH		 2672 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
2673 "scattered RX aborted (dropping %u buffers)\n",
2674 rx_queue->scatter_n);
a707d188 2675
8127d661 2676 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
a707d188 2677
8127d661
BH		 2678 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
2679 0, EFX_RX_PKT_DISCARD);
e0a65e3c 2680
8127d661
BH		 2681 rx_queue->removed_count += rx_queue->scatter_n;
2682 rx_queue->scatter_n = 0;
2683 rx_queue->scatter_len = 0;
2684 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
42356d9a
EC		 2685}
2686
a0ee3541
JC		 2687static u16 efx_ef10_handle_rx_event_errors(struct efx_channel *channel,
2688 unsigned int n_packets,
2689 unsigned int rx_encap_hdr,
2690 unsigned int rx_l3_class,
2691 unsigned int rx_l4_class,
2692 const efx_qword_t *event)
42356d9a 2693{
a0ee3541 2694 struct efx_nic *efx = channel->efx;
6978729f 2695 bool handled = false;
e0a65e3c 2696
a0ee3541 2697 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)) {
6978729f
EC		 2698 if (!(efx->net_dev->features & NETIF_F_RXALL)) {
2699 if (!efx->loopback_selftest)
2700 channel->n_rx_eth_crc_err += n_packets;
2701 return EFX_RX_PKT_DISCARD;
2702 }
2703 handled = true;
42356d9a 2704 }
a0ee3541
JC		 2705 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR)) {
2706 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
2707 rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
2708 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
2709 rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
2710 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
2711 netdev_WARN(efx->net_dev,
2712 "invalid class for RX_IPCKSUM_ERR: event="
2713 EFX_QWORD_FMT "\n",
2714 EFX_QWORD_VAL(*event));
2715 if (!efx->loopback_selftest)
2716 *(rx_encap_hdr ?
2717 &channel->n_rx_outer_ip_hdr_chksum_err :
2718 &channel->n_rx_ip_hdr_chksum_err) += n_packets;
267c0157 2719 return 0;
267c0157 2720 }
a0ee3541
JC		 2721 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
2722 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
2723 ((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
2724 rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
d8d8ccf2
BK		 2725 (rx_l4_class != ESE_FZ_L4_CLASS_TCP &&
2726 rx_l4_class != ESE_FZ_L4_CLASS_UDP))))
a0ee3541
JC		 2727 netdev_WARN(efx->net_dev,
2728 "invalid class for RX_TCPUDP_CKSUM_ERR: event="
2729 EFX_QWORD_FMT "\n",
2730 EFX_QWORD_VAL(*event));
2731 if (!efx->loopback_selftest)
2732 *(rx_encap_hdr ?
2733 &channel->n_rx_outer_tcp_udp_chksum_err :
2734 &channel->n_rx_tcp_udp_chksum_err) += n_packets;
267c0157 2735 return 0;
a0ee3541
JC		 2736 }
2737 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_IP_INNER_CHKSUM_ERR)) {
2738 if (unlikely(!rx_encap_hdr))
2739 netdev_WARN(efx->net_dev,
2740 "invalid encapsulation type for RX_IP_INNER_CHKSUM_ERR: event="
2741 EFX_QWORD_FMT "\n",
2742 EFX_QWORD_VAL(*event));
2743 else if (unlikely(rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
2744 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
2745 rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
2746 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
2747 netdev_WARN(efx->net_dev,
2748 "invalid class for RX_IP_INNER_CHKSUM_ERR: event="
2749 EFX_QWORD_FMT "\n",
2750 EFX_QWORD_VAL(*event));
2751 if (!efx->loopback_selftest)
2752 channel->n_rx_inner_ip_hdr_chksum_err += n_packets;
2753 return 0;
2754 }
2755 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR)) {
2756 if (unlikely(!rx_encap_hdr))
2757 netdev_WARN(efx->net_dev,
2758 "invalid encapsulation type for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
2759 EFX_QWORD_FMT "\n",
2760 EFX_QWORD_VAL(*event));
2761 else if (unlikely((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
2762 rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
d8d8ccf2
BK		 2763 (rx_l4_class != ESE_FZ_L4_CLASS_TCP &&
2764 rx_l4_class != ESE_FZ_L4_CLASS_UDP)))
a0ee3541
JC		 2765 netdev_WARN(efx->net_dev,
2766 "invalid class for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
2767 EFX_QWORD_FMT "\n",
2768 EFX_QWORD_VAL(*event));
2769 if (!efx->loopback_selftest)
2770 channel->n_rx_inner_tcp_udp_chksum_err += n_packets;
2771 return 0;
2772 }
8127d661 2773
6978729f 2774 WARN_ON(!handled); /* No error bits were recognised */
a0ee3541 2775 return 0;
8127d661
BH		 2776}
2777
8127d661
BH		 2778static int efx_ef10_handle_rx_event(struct efx_channel *channel,
2779 const efx_qword_t *event)
8127d661 2780{
a0ee3541
JC		 2781 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label;
2782 unsigned int rx_l3_class, rx_l4_class, rx_encap_hdr;
8127d661
BH		 2783 unsigned int n_descs, n_packets, i;
2784 struct efx_nic *efx = channel->efx;
45b2449e 2785 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661 2786 struct efx_rx_queue *rx_queue;
a0ee3541 2787 efx_qword_t errors;
8127d661
BH		 2788 bool rx_cont;
2789 u16 flags = 0;
8127d661 2790
6aa7de05 2791 if (unlikely(READ_ONCE(efx->reset_pending)))
8127d661 2792 return 0;
8127d661 2793
8127d661
BH		 2794 /* Basic packet information */
2795 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
2796 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
2797 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
a0ee3541 2798 rx_l3_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L3_CLASS);
d8d8ccf2 2799 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_FZ_RX_L4_CLASS);
8127d661 2800 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
a0ee3541
JC		 2801 rx_encap_hdr =
2802 nic_data->datapath_caps &
2803 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) ?
2804 EFX_QWORD_FIELD(*event, ESF_EZ_RX_ENCAP_HDR) :
2805 ESE_EZ_ENCAP_HDR_NONE;
8127d661 2806
48ce5634
BH		 2807 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
2808 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
2809 EFX_QWORD_FMT "\n",
2810 EFX_QWORD_VAL(*event));
8127d661 2811
8127d661 2812 rx_queue = efx_channel_get_rx_queue(channel);
8127d661 2813
8127d661
BH		 2814 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
2815 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
8127d661 2816
8127d661
BH		 2817 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
2818 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
8127d661 2819
8127d661 2820 if (n_descs != rx_queue->scatter_n + 1) {
92a04168 2821 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661 2822
8127d661
BH		 2823 /* detect rx abort */
2824 if (unlikely(n_descs == rx_queue->scatter_n)) {
48ce5634
BH		 2825 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
2826 netdev_WARN(efx->net_dev,
2827 "invalid RX abort: scatter_n=%u event="
2828 EFX_QWORD_FMT "\n",
2829 rx_queue->scatter_n,
2830 EFX_QWORD_VAL(*event));
8127d661
BH		 2831 efx_ef10_handle_rx_abort(rx_queue);
2832 return 0;
2833 }
8127d661 2834
92a04168
BH		 2835 /* Check that RX completion merging is valid, i.e.
2836 * the current firmware supports it and this is a
2837 * non-scattered packet.
2838 */
2839 if (!(nic_data->datapath_caps &
2840 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
2841 rx_queue->scatter_n != 0 || rx_cont) {
8127d661
BH		 2842 efx_ef10_handle_rx_bad_lbits(
2843 rx_queue, next_ptr_lbits,
2844 (rx_queue->removed_count +
2845 rx_queue->scatter_n + 1) &
2846 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2847 return 0;
2848 }
8127d661 2849
8127d661
BH		 2850 /* Merged completion for multiple non-scattered packets */
2851 rx_queue->scatter_n = 1;
2852 rx_queue->scatter_len = 0;
2853 n_packets = n_descs;
2854 ++channel->n_rx_merge_events;
2855 channel->n_rx_merge_packets += n_packets;
2856 flags |= EFX_RX_PKT_PREFIX_LEN;
8127d661 2857 } else {
8127d661
BH		 2858 ++rx_queue->scatter_n;
2859 rx_queue->scatter_len += rx_bytes;
2860 if (rx_cont)
2861 return 0;
2862 n_packets = 1;
8127d661 2863 }
7665d1ab 2864
a0ee3541
JC		 2865 EFX_POPULATE_QWORD_5(errors, ESF_DZ_RX_ECRC_ERR, 1,
2866 ESF_DZ_RX_IPCKSUM_ERR, 1,
2867 ESF_DZ_RX_TCPUDP_CKSUM_ERR, 1,
2868 ESF_EZ_RX_IP_INNER_CHKSUM_ERR, 1,
2869 ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR, 1);
2870 EFX_AND_QWORD(errors, *event, errors);
2871 if (unlikely(!EFX_QWORD_IS_ZERO(errors))) {
2872 flags |= efx_ef10_handle_rx_event_errors(channel, n_packets,
90d2ea9f 2873 rx_encap_hdr,
a0ee3541 2874 rx_l3_class, rx_l4_class,
90d2ea9f 2875 event);
8127d661 2876 } else {
d8d8ccf2
BK		 2877 bool tcpudp = rx_l4_class == ESE_FZ_L4_CLASS_TCP ||
2878 rx_l4_class == ESE_FZ_L4_CLASS_UDP;
8127d661 2879
da50ae2e
JC		 2880 switch (rx_encap_hdr) {
2881 case ESE_EZ_ENCAP_HDR_VXLAN: /* VxLAN or GENEVE */
2882 flags |= EFX_RX_PKT_CSUMMED; /* outer UDP csum */
2883 if (tcpudp)
2884 flags |= EFX_RX_PKT_CSUM_LEVEL; /* inner L4 */
2885 break;
2886 case ESE_EZ_ENCAP_HDR_GRE:
2887 case ESE_EZ_ENCAP_HDR_NONE:
2888 if (tcpudp)
2889 flags |= EFX_RX_PKT_CSUMMED;
2890 break;
2891 default:
2892 netdev_WARN(efx->net_dev,
2893 "unknown encapsulation type: event="
2894 EFX_QWORD_FMT "\n",
2895 EFX_QWORD_VAL(*event));
2896 }
8127d661 2897 }
8127d661 2898
d8d8ccf2 2899 if (rx_l4_class == ESE_FZ_L4_CLASS_TCP)
8127d661 2900 flags |= EFX_RX_PKT_TCP;
8127d661 2901
8127d661 2902 channel->irq_mod_score += 2 * n_packets;
8127d661 2903
8127d661
BH		 2904 /* Handle received packet(s) */
2905 for (i = 0; i < n_packets; i++) {
2906 efx_rx_packet(rx_queue,
2907 rx_queue->removed_count & rx_queue->ptr_mask,
2908 rx_queue->scatter_n, rx_queue->scatter_len,
2909 flags);
2910 rx_queue->removed_count += rx_queue->scatter_n;
8127d661 2911 }
8127d661 2912
8127d661
BH		 2913 rx_queue->scatter_n = 0;
2914 rx_queue->scatter_len = 0;
8127d661 2915
8127d661 2916 return n_packets;
8127d661
BH		 2917}
2918
b9b603d4 2919static u32 efx_ef10_extract_event_ts(efx_qword_t *event)
8127d661 2920{
b9b603d4 2921 u32 tstamp;
8127d661 2922
b9b603d4
MH		 2923 tstamp = EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI);
2924 tstamp <<= 16;
2925 tstamp |= EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO);
8127d661 2926
b9b603d4 2927 return tstamp;
8127d661
BH		 2928}
2929
5227eccc 2930static void
8127d661 2931efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
34813fe2 2932{
8127d661
BH		 2933 struct efx_nic *efx = channel->efx;
2934 struct efx_tx_queue *tx_queue;
2935 unsigned int tx_ev_desc_ptr;
2936 unsigned int tx_ev_q_label;
b9b603d4
MH		 2937 unsigned int tx_ev_type;
2938 u64 ts_part;
34813fe2 2939
6aa7de05 2940 if (unlikely(READ_ONCE(efx->reset_pending)))
34813fe2
AR		 2941 return;
2942
8127d661 2943 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
34813fe2
AR		 2944 return;
2945
b9b603d4 2946 /* Get the transmit queue */
8127d661 2947 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
172e269e 2948 tx_queue = channel->tx_queue + (tx_ev_q_label % EFX_MAX_TXQ_PER_CHANNEL);
34813fe2 2949
b9b603d4
MH		 2950 if (!tx_queue->timestamping) {
2951 /* Transmit completion */
2952 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
2953 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
2954 return;
7ac0dd9d
AR		 2955 }
2956
b9b603d4 2957 /* Transmit timestamps are only available for 8XXX series. They result
3b4f06c7
TZ		 2958 * in up to three events per packet. These occur in order, and are:
2959 * - the normal completion event (may be omitted)
b9b603d4
MH		 2960 * - the low part of the timestamp
2961 * - the high part of the timestamp
2962 *
3b4f06c7
TZ		 2963 * It's possible for multiple completion events to appear before the
2964 * corresponding timestamps. So we can for example get:
2965 * COMP N
2966 * COMP N+1
2967 * TS_LO N
2968 * TS_HI N
2969 * TS_LO N+1
2970 * TS_HI N+1
2971 *
2972 * In addition it's also possible for the adjacent completions to be
2973 * merged, so we may not see COMP N above. As such, the completion
2974 * events are not very useful here.
2975 *
b9b603d4
MH		 2976 * Each part of the timestamp is itself split across two 16 bit
2977 * fields in the event.
2978 */
2979 tx_ev_type = EFX_QWORD_FIELD(*event, ESF_EZ_TX_SOFT1);
8127d661 2980
b9b603d4
MH		 2981 switch (tx_ev_type) {
2982 case TX_TIMESTAMP_EVENT_TX_EV_COMPLETION:
3b4f06c7 2983 /* Ignore this event - see above. */
b9b603d4 2984 break;
9b410801 2985
b9b603d4
MH		 2986 case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO:
2987 ts_part = efx_ef10_extract_event_ts(event);
2988 tx_queue->completed_timestamp_minor = ts_part;
2989 break;
9b410801 2990
b9b603d4
MH		 2991 case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI:
2992 ts_part = efx_ef10_extract_event_ts(event);
2993 tx_queue->completed_timestamp_major = ts_part;
9b410801 2994
3b4f06c7 2995 efx_xmit_done_single(tx_queue);
b9b603d4 2996 break;
9b410801 2997
b9b603d4
MH		 2998 default:
2999 netif_err(efx, hw, efx->net_dev,
3000 "channel %d unknown tx event type %d (data "
3001 EFX_QWORD_FMT ")\n",
3002 channel->channel, tx_ev_type,
3003 EFX_QWORD_VAL(*event));
3004 break;
e4478ad1 3005 }
8127d661 3006}
e4478ad1 3007
8127d661
BH		 3008static void
3009efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
3010{
3011 struct efx_nic *efx = channel->efx;
3012 int subcode;
8127d661 3013
8127d661 3014 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
12fb0da4 3015
8127d661
BH		 3016 switch (subcode) {
3017 case ESE_DZ_DRV_TIMER_EV:
3018 case ESE_DZ_DRV_WAKE_UP_EV:
3019 break;
3020 case ESE_DZ_DRV_START_UP_EV:
3021 /* event queue init complete. ok. */
3022 break;
3023 default:
3024 netif_err(efx, hw, efx->net_dev,
3025 "channel %d unknown driver event type %d"
3026 " (data " EFX_QWORD_FMT ")\n",
3027 channel->channel, subcode,
3028 EFX_QWORD_VAL(*event));
34813fe2 3029
34813fe2 3030 }
8127d661
BH		 3031}
3032
8127d661
BH		 3033static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
3034 efx_qword_t *event)
8127d661 3035{
8127d661
BH		 3036 struct efx_nic *efx = channel->efx;
3037 u32 subcode;
8127d661 3038
8127d661 3039 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
8127d661 3040
8127d661
BH		 3041 switch (subcode) {
3042 case EFX_EF10_TEST:
3043 channel->event_test_cpu = raw_smp_processor_id();
3044 break;
3045 case EFX_EF10_REFILL:
3046 /* The queue must be empty, so we won't receive any rx
3047 * events, so efx_process_channel() won't refill the
3048 * queue. Refill it here
3049 */
cce28794 3050 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
8127d661
BH		 3051 break;
3052 default:
3053 netif_err(efx, hw, efx->net_dev,
3054 "channel %d unknown driver event type %u"
3055 " (data " EFX_QWORD_FMT ")\n",
3056 channel->channel, (unsigned) subcode,
3057 EFX_QWORD_VAL(*event));
3058 }
3059}
2d3d4ec0 3060
8127d661
BH		 3061static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
3062{
3063 struct efx_nic *efx = channel->efx;
3064 efx_qword_t event, *p_event;
3065 unsigned int read_ptr;
3066 int ev_code;
8127d661 3067 int spent = 0;
2d3d4ec0 3068
75363a46
EB		 3069 if (quota <= 0)
3070 return spent;
8127d661 3071
8127d661 3072 read_ptr = channel->eventq_read_ptr;
8127d661 3073
8127d661
BH		 3074 for (;;) {
3075 p_event = efx_event(channel, read_ptr);
3076 event = *p_event;
2d3d4ec0 3077
8127d661
BH		 3078 if (!efx_event_present(&event))
3079 break;
8127d661 3080
8127d661 3081 EFX_SET_QWORD(*p_event);
8127d661 3082
8127d661 3083 ++read_ptr;
dd98708c 3084
8127d661 3085 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
0d322413 3086
8127d661
BH		 3087 netif_vdbg(efx, drv, efx->net_dev,
3088 "processing event on %d " EFX_QWORD_FMT "\n",
3089 channel->channel, EFX_QWORD_VAL(event));
8127d661 3090
8127d661
BH		 3091 switch (ev_code) {
3092 case ESE_DZ_EV_CODE_MCDI_EV:
3093 efx_mcdi_process_event(channel, &event);
3094 break;
3095 case ESE_DZ_EV_CODE_RX_EV:
3096 spent += efx_ef10_handle_rx_event(channel, &event);
3097 if (spent >= quota) {
3098 /* XXX can we split a merged event to
3099 * avoid going over-quota?
3100 */
3101 spent = quota;
3102 goto out;
3103 }
3104 break;
3105 case ESE_DZ_EV_CODE_TX_EV:
5227eccc 3106 efx_ef10_handle_tx_event(channel, &event);
8127d661
BH		 3107 break;
3108 case ESE_DZ_EV_CODE_DRIVER_EV:
3109 efx_ef10_handle_driver_event(channel, &event);
3110 if (++spent == quota)
3111 goto out;
3112 break;
3113 case EFX_EF10_DRVGEN_EV:
3114 efx_ef10_handle_driver_generated_event(channel, &event);
3115 break;
3116 default:
3117 netif_err(efx, hw, efx->net_dev,
3118 "channel %d unknown event type %d"
3119 " (data " EFX_QWORD_FMT ")\n",
3120 channel->channel, ev_code,
3121 EFX_QWORD_VAL(event));
3122 }
8127d661
BH		 3123 }
3124
8127d661
BH		 3125out:
3126 channel->eventq_read_ptr = read_ptr;
3127 return spent;
8127d661
BH		 3128}
3129
8127d661 3130static void efx_ef10_ev_read_ack(struct efx_channel *channel)
6a37958b 3131{
8127d661
BH		 3132 struct efx_nic *efx = channel->efx;
3133 efx_dword_t rptr;
6a37958b 3134
8127d661
BH		 3135 if (EFX_EF10_WORKAROUND_35388(efx)) {
3136 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
3137 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
3138 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
3139 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
c2bebe37 3140
8127d661
BH		 3141 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3142 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
3143 ERF_DD_EVQ_IND_RPTR,
3144 (channel->eventq_read_ptr &
3145 channel->eventq_mask) >>
3146 ERF_DD_EVQ_IND_RPTR_WIDTH);
3147 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3148 channel->channel);
3149 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3150 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
3151 ERF_DD_EVQ_IND_RPTR,
3152 channel->eventq_read_ptr &
3153 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
3154 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3155 channel->channel);
3156 } else {
3157 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
3158 channel->eventq_read_ptr &
3159 channel->eventq_mask);
3160 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
e65a5109 3161 }
6a37958b
AR		 3162}
3163
8127d661 3164static void efx_ef10_ev_test_generate(struct efx_channel *channel)
8127d661 3165{
8127d661
BH		 3166 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3167 struct efx_nic *efx = channel->efx;
3168 efx_qword_t event;
3169 int rc;
8127d661 3170
8127d661
BH		 3171 EFX_POPULATE_QWORD_2(event,
3172 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3173 ESF_DZ_EV_DATA, EFX_EF10_TEST);
b3a3c03c 3174
8127d661 3175 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
b3a3c03c 3176
8127d661
BH		 3177 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3178 * already swapped the data to little-endian order.
3179 */
3180 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3181 sizeof(efx_qword_t));
822b96f8 3182
8127d661
BH		 3183 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
3184 NULL, 0, NULL);
3185 if (rc != 0)
3186 goto fail;
8127d661 3187
8127d661 3188 return;
c70d6815 3189
8127d661
BH		 3190fail:
3191 WARN_ON(true);
3192 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
822b96f8
DP		 3193}
3194
e283546c 3195static void efx_ef10_prepare_flr(struct efx_nic *efx)
822b96f8 3196{
e283546c 3197 atomic_set(&efx->active_queues, 0);
8127d661
BH		 3198}
3199
7a186f47
DP		 3200static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
3201{
3202 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3203 u8 mac_old[ETH_ALEN];
3204 int rc, rc2;
3205
3206 /* Only reconfigure a PF-created vport */
3207 if (is_zero_ether_addr(nic_data->vport_mac))
3208 return 0;
3209
3210 efx_device_detach_sync(efx);
3211 efx_net_stop(efx->net_dev);
3212 down_write(&efx->filter_sem);
6c77065b 3213 efx_mcdi_filter_table_remove(efx);
7a186f47
DP		 3214 up_write(&efx->filter_sem);
3215
dfcabb07 3216 rc = efx_ef10_vadaptor_free(efx, efx->vport_id);
7a186f47
DP		 3217 if (rc)
3218 goto restore_filters;
3219
3220 ether_addr_copy(mac_old, nic_data->vport_mac);
dfcabb07 3221 rc = efx_ef10_vport_del_mac(efx, efx->vport_id,
7a186f47
DP		 3222 nic_data->vport_mac);
3223 if (rc)
3224 goto restore_vadaptor;
3225
dfcabb07 3226 rc = efx_ef10_vport_add_mac(efx, efx->vport_id,
7a186f47
DP		 3227 efx->net_dev->dev_addr);
3228 if (!rc) {
3229 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
3230 } else {
dfcabb07 3231 rc2 = efx_ef10_vport_add_mac(efx, efx->vport_id, mac_old);
7a186f47
DP		 3232 if (rc2) {
3233 /* Failed to add original MAC, so clear vport_mac */
3234 eth_zero_addr(nic_data->vport_mac);
3235 goto reset_nic;
3236 }
3237 }
3238
3239restore_vadaptor:
dfcabb07 3240 rc2 = efx_ef10_vadaptor_alloc(efx, efx->vport_id);
7a186f47
DP		 3241 if (rc2)
3242 goto reset_nic;
3243restore_filters:
3244 down_write(&efx->filter_sem);
fd14e5fd 3245 rc2 = efx_ef10_filter_table_probe(efx);
7a186f47
DP		 3246 up_write(&efx->filter_sem);
3247 if (rc2)
3248 goto reset_nic;
3249
3250 rc2 = efx_net_open(efx->net_dev);
3251 if (rc2)
3252 goto reset_nic;
3253
9c568fd8 3254 efx_device_attach_if_not_resetting(efx);
7a186f47
DP		 3255
3256 return rc;
3257
3258reset_nic:
3259 netif_err(efx, drv, efx->net_dev,
3260 "Failed to restore when changing MAC address - scheduling reset\n");
3261 efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
3262
3263 return rc ? rc : rc2;
3264}
3265
910c8789
SS		 3266static int efx_ef10_set_mac_address(struct efx_nic *efx)
3267{
3268 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
910c8789
SS		 3269 bool was_enabled = efx->port_enabled;
3270 int rc;
3271
3272 efx_device_detach_sync(efx);
3273 efx_net_stop(efx->net_dev);
d248953a
MH		 3274
3275 mutex_lock(&efx->mac_lock);
910c8789 3276 down_write(&efx->filter_sem);
90c914d2 3277 efx_mcdi_filter_table_remove(efx);
910c8789
SS		 3278
3279 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
3280 efx->net_dev->dev_addr);
3281 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
dfcabb07 3282 efx->vport_id);
535a6177
DP		 3283 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
3284 sizeof(inbuf), NULL, 0, NULL);
910c8789 3285
fd14e5fd 3286 efx_ef10_filter_table_probe(efx);
910c8789 3287 up_write(&efx->filter_sem);
d248953a
MH		 3288 mutex_unlock(&efx->mac_lock);
3289
910c8789
SS		 3290 if (was_enabled)
3291 efx_net_open(efx->net_dev);
9c568fd8 3292 efx_device_attach_if_not_resetting(efx);
910c8789 3293
9e9f665a
DP		 3294#ifdef CONFIG_SFC_SRIOV
3295 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
b113cabd 3296 struct efx_ef10_nic_data *nic_data = efx->nic_data;
910c8789
SS		 3297 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
3298
9e9f665a
DP		 3299 if (rc == -EPERM) {
3300 struct efx_nic *efx_pf;
910c8789 3301
9e9f665a
DP		 3302 /* Switch to PF and change MAC address on vport */
3303 efx_pf = pci_get_drvdata(pci_dev_pf);
910c8789 3304
9e9f665a
DP		 3305 rc = efx_ef10_sriov_set_vf_mac(efx_pf,
3306 nic_data->vf_index,
3307 efx->net_dev->dev_addr);
3308 } else if (!rc) {
910c8789
SS		 3309 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
3310 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
3311 unsigned int i;
3312
9e9f665a
DP		 3313 /* MAC address successfully changed by VF (with MAC
3314 * spoofing) so update the parent PF if possible.
3315 */
910c8789
SS		 3316 for (i = 0; i < efx_pf->vf_count; ++i) {
3317 struct ef10_vf *vf = nic_data->vf + i;
3318
3319 if (vf->efx == efx) {
3320 ether_addr_copy(vf->mac,
3321 efx->net_dev->dev_addr);
3322 return 0;
3323 }
3324 }
3325 }
9e9f665a 3326 } else
910c8789 3327#endif
9e9f665a
DP		 3328 if (rc == -EPERM) {
3329 netif_err(efx, drv, efx->net_dev,
3330 "Cannot change MAC address; use sfboot to enable"
3331 " mac-spoofing on this interface\n");
7a186f47
DP		 3332 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
3333 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
3334 * fall-back to the method of changing the MAC address on the
3335 * vport. This only applies to PFs because such versions of
3336 * MCFW do not support VFs.
3337 */
3338 rc = efx_ef10_vport_set_mac_address(efx);
cbad52e9 3339 } else if (rc) {
535a6177
DP		 3340 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
3341 sizeof(inbuf), NULL, 0, rc);
9e9f665a
DP		 3342 }
3343
910c8789
SS		 3344 return rc;
3345}
3346
af3c38d3 3347static int efx_ef10_mac_reconfigure(struct efx_nic *efx, bool mtu_only)
8127d661 3348{
af3c38d3 3349 WARN_ON(!mutex_is_locked(&efx->mac_lock));
8127d661 3350
90c914d2 3351 efx_mcdi_filter_sync_rx_mode(efx);
862f894c 3352
af3c38d3
EC		 3353 if (mtu_only && efx_has_cap(efx, SET_MAC_ENHANCED))
3354 return efx_mcdi_set_mtu(efx);
3355 return efx_mcdi_set_mac(efx);
862f894c
SS		 3356}
3357
74cd60a4
JC		 3358static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
3359{
3360 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
3361
3362 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
3363 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
3364 NULL, 0, NULL);
3365}
3366
3367/* MC BISTs follow a different poll mechanism to phy BISTs.
3368 * The BIST is done in the poll handler on the MC, and the MCDI command
3369 * will block until the BIST is done.
3370 */
3371static int efx_ef10_poll_bist(struct efx_nic *efx)
3372{
3373 int rc;
3374 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
3375 size_t outlen;
3376 u32 result;
3377
3378 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
3379 outbuf, sizeof(outbuf), &outlen);
3380 if (rc != 0)
3381 return rc;
3382
3383 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
3384 return -EIO;
3385
3386 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
3387 switch (result) {
3388 case MC_CMD_POLL_BIST_PASSED:
3389 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
3390 return 0;
3391 case MC_CMD_POLL_BIST_TIMEOUT:
3392 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
3393 return -EIO;
3394 case MC_CMD_POLL_BIST_FAILED:
3395 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
3396 return -EIO;
3397 default:
3398 netif_err(efx, hw, efx->net_dev,
3399 "BIST returned unknown result %u", result);
3400 return -EIO;
3401 }
3402}
3403
3404static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
3405{
3406 int rc;
3407
3408 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
3409
3410 rc = efx_ef10_start_bist(efx, bist_type);
3411 if (rc != 0)
3412 return rc;
3413
3414 return efx_ef10_poll_bist(efx);
3415}
3416
3417static int
3418efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
3419{
3420 int rc, rc2;
3421
3422 efx_reset_down(efx, RESET_TYPE_WORLD);
3423
3424 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
3425 NULL, 0, NULL, 0, NULL);
3426 if (rc != 0)
3427 goto out;
3428
3429 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
3430 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
3431
3432 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
3433
3434out:
27324820
DP		 3435 if (rc == -EPERM)
3436 rc = 0;
74cd60a4
JC		 3437 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
3438 return rc ? rc : rc2;
3439}
3440
8127d661
BH		 3441#ifdef CONFIG_SFC_MTD
3442
3443struct efx_ef10_nvram_type_info {
3444 u16 type, type_mask;
3445 u8 port;
3446 const char *name;
3447};
3448
3449static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
3450 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
3451 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
3452 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
3453 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
3454 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
3455 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
3456 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
3457 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
3458 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
a84f3bf9 3459 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
8127d661 3460 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
cea0604d
EC		 3461 { NVRAM_PARTITION_TYPE_MUM_FIRMWARE, 0, 0, "sfc_mumfw" },
3462 { NVRAM_PARTITION_TYPE_EXPANSION_UEFI, 0, 0, "sfc_uefi" },
5fb1beec
BK		 3463 { NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS, 0, 0, "sfc_dynamic_cfg_dflt" },
3464 { NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS, 0, 0, "sfc_exp_rom_cfg_dflt" },
3465 { NVRAM_PARTITION_TYPE_STATUS, 0, 0, "sfc_status" },
b9ad6de5
PF		 3466 { NVRAM_PARTITION_TYPE_BUNDLE, 0, 0, "sfc_bundle" },
3467 { NVRAM_PARTITION_TYPE_BUNDLE_METADATA, 0, 0, "sfc_bundle_metadata" },
8127d661 3468};
33664635 3469#define EF10_NVRAM_PARTITION_COUNT ARRAY_SIZE(efx_ef10_nvram_types)
8127d661
BH		 3470
3471static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
3472 struct efx_mcdi_mtd_partition *part,
33664635
EC		 3473 unsigned int type,
3474 unsigned long *found)
8127d661
BH		 3475{
3476 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
3477 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
3478 const struct efx_ef10_nvram_type_info *info;
3479 size_t size, erase_size, outlen;
33664635 3480 int type_idx = 0;
8127d661
BH		 3481 bool protected;
3482 int rc;
3483
33664635
EC		 3484 for (type_idx = 0; ; type_idx++) {
3485 if (type_idx == EF10_NVRAM_PARTITION_COUNT)
8127d661 3486 return -ENODEV;
33664635 3487 info = efx_ef10_nvram_types + type_idx;
8127d661
BH		 3488 if ((type & ~info->type_mask) == info->type)
3489 break;
3490 }
3491 if (info->port != efx_port_num(efx))
3492 return -ENODEV;
3493
3494 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
3495 if (rc)
3496 return rc;
5fb1beec
BK		 3497 if (protected &&
3498 (type != NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS &&
3499 type != NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS))
3500 /* Hide protected partitions that don't provide defaults. */
3501 return -ENODEV;
3502
8127d661 3503 if (protected)
5fb1beec
BK		 3504 /* Protected partitions are read only. */
3505 erase_size = 0;
8127d661 3506
33664635
EC		 3507 /* If we've already exposed a partition of this type, hide this
3508 * duplicate. All operations on MTDs are keyed by the type anyway,
3509 * so we can't act on the duplicate.
3510 */
3511 if (__test_and_set_bit(type_idx, found))
3512 return -EEXIST;
3513
8127d661
BH		 3514 part->nvram_type = type;
3515
3516 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
3517 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
3518 outbuf, sizeof(outbuf), &outlen);
3519 if (rc)
3520 return rc;
3521 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
3522 return -EIO;
3523 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
3524 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
3525 part->fw_subtype = MCDI_DWORD(outbuf,
3526 NVRAM_METADATA_OUT_SUBTYPE);
3527
3528 part->common.dev_type_name = "EF10 NVRAM manager";
3529 part->common.type_name = info->name;
3530
3531 part->common.mtd.type = MTD_NORFLASH;
3532 part->common.mtd.flags = MTD_CAP_NORFLASH;
3533 part->common.mtd.size = size;
3534 part->common.mtd.erasesize = erase_size;
cea0604d
EC		 3535 /* sfc_status is read-only */
3536 if (!erase_size)
3537 part->common.mtd.flags |= MTD_NO_ERASE;
8127d661
BH		 3538
3539 return 0;
3540}
3541
3542static int efx_ef10_mtd_probe(struct efx_nic *efx)
3543{
3544 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
c6528542 3545 DECLARE_BITMAP(found, EF10_NVRAM_PARTITION_COUNT) = { 0 };
8127d661
BH		 3546 struct efx_mcdi_mtd_partition *parts;
3547 size_t outlen, n_parts_total, i, n_parts;
3548 unsigned int type;
3549 int rc;
3550
3551 ASSERT_RTNL();
3552
3553 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
3554 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
3555 outbuf, sizeof(outbuf), &outlen);
3556 if (rc)
3557 return rc;
3558 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
3559 return -EIO;
3560
3561 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
3562 if (n_parts_total >
3563 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
3564 return -EIO;
3565
3566 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
3567 if (!parts)
3568 return -ENOMEM;
3569
3570 n_parts = 0;
3571 for (i = 0; i < n_parts_total; i++) {
3572 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
3573 i);
33664635
EC		 3574 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type,
3575 found);
3576 if (rc == -EEXIST || rc == -ENODEV)
3577 continue;
3578 if (rc)
8127d661 3579 goto fail;
33664635 3580 n_parts++;
8127d661
BH		 3581 }
3582
3583 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
3584fail:
3585 if (rc)
3586 kfree(parts);
3587 return rc;
3588}
3589
3590#endif /* CONFIG_SFC_MTD */
3591
3592static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
3593{
3594 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
3595}
3596
02246a7f
SS		 3597static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
3598 u32 host_time) {}
3599
bd9a265d
JC		 3600static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
3601 bool temp)
3602{
3603 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
3604 int rc;
3605
3606 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
3607 channel->sync_events_state == SYNC_EVENTS_VALID ||
3608 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
3609 return 0;
3610 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
3611
3612 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
3613 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
3614 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
3615 channel->channel);
3616
3617 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
3618 inbuf, sizeof(inbuf), NULL, 0, NULL);
3619
3620 if (rc != 0)
3621 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
3622 SYNC_EVENTS_DISABLED;
3623
3624 return rc;
3625}
3626
3627static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
3628 bool temp)
3629{
3630 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
3631 int rc;
3632
3633 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
3634 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
3635 return 0;
3636 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
3637 channel->sync_events_state = SYNC_EVENTS_DISABLED;
3638 return 0;
3639 }
3640 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
3641 SYNC_EVENTS_DISABLED;
3642
3643 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
3644 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
3645 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
3646 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
3647 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
3648 channel->channel);
3649
3650 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
3651 inbuf, sizeof(inbuf), NULL, 0, NULL);
3652
3653 return rc;
3654}
3655
3656static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
3657 bool temp)
3658{
3659 int (*set)(struct efx_channel *channel, bool temp);
3660 struct efx_channel *channel;
3661
3662 set = en ?
3663 efx_ef10_rx_enable_timestamping :
3664 efx_ef10_rx_disable_timestamping;
3665
2935e3c3
EC		 3666 channel = efx_ptp_channel(efx);
3667 if (channel) {
bd9a265d
JC		 3668 int rc = set(channel, temp);
3669 if (en && rc != 0) {
3670 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
3671 return rc;
3672 }
3673 }
3674
3675 return 0;
3676}
3677
02246a7f
SS		 3678static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
3679 struct hwtstamp_config *init)
3680{
3681 return -EOPNOTSUPP;
3682}
3683
bd9a265d
JC		 3684static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
3685 struct hwtstamp_config *init)
3686{
3687 int rc;
3688
3689 switch (init->rx_filter) {
3690 case HWTSTAMP_FILTER_NONE:
3691 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
3692 /* if TX timestamping is still requested then leave PTP on */
3693 return efx_ptp_change_mode(efx,
3694 init->tx_type != HWTSTAMP_TX_OFF, 0);
3695 case HWTSTAMP_FILTER_ALL:
3696 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3697 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3698 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3699 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3700 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3701 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3702 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3703 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3704 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3705 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3706 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3707 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
e3412575 3708 case HWTSTAMP_FILTER_NTP_ALL:
bd9a265d
JC		 3709 init->rx_filter = HWTSTAMP_FILTER_ALL;
3710 rc = efx_ptp_change_mode(efx, true, 0);
3711 if (!rc)
3712 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
3713 if (rc)
3714 efx_ptp_change_mode(efx, false, 0);
3715 return rc;
3716 default:
3717 return -ERANGE;
3718 }
3719}
3720
08a7b29b
BK		 3721static int efx_ef10_get_phys_port_id(struct efx_nic *efx,
3722 struct netdev_phys_item_id *ppid)
3723{
3724 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3725
3726 if (!is_valid_ether_addr(nic_data->port_id))
3727 return -EOPNOTSUPP;
3728
3729 ppid->id_len = ETH_ALEN;
3730 memcpy(ppid->id, nic_data->port_id, ppid->id_len);
3731
3732 return 0;
3733}
3734
4a53ea8a
AR		 3735static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid)
3736{
3737 if (proto != htons(ETH_P_8021Q))
3738 return -EINVAL;
3739
3740 return efx_ef10_add_vlan(efx, vid);
3741}
3742
3743static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid)
3744{
3745 if (proto != htons(ETH_P_8021Q))
3746 return -EINVAL;
3747
3748 return efx_ef10_del_vlan(efx, vid);
3749}
3750
e5fbd977
JC		 3751/* We rely on the MCDI wiping out our TX rings if it made any changes to the
3752 * ports table, ensuring that any TSO descriptors that were made on a now-
3753 * removed tunnel port will be blown away and won't break things when we try
3754 * to transmit them using the new ports table.
3755 */
3756static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading)
3757{
3758 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3759 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX);
3760 MCDI_DECLARE_BUF(outbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN);
3761 bool will_reset = false;
3762 size_t num_entries = 0;
3763 size_t inlen, outlen;
3764 size_t i;
3765 int rc;
3766 efx_dword_t flags_and_num_entries;
3767
3768 WARN_ON(!mutex_is_locked(&nic_data->udp_tunnels_lock));
3769
3770 nic_data->udp_tunnels_dirty = false;
3771
3772 if (!(nic_data->datapath_caps &
3773 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) {
9c568fd8 3774 efx_device_attach_if_not_resetting(efx);
e5fbd977
JC		 3775 return 0;
3776 }
3777
3778 BUILD_BUG_ON(ARRAY_SIZE(nic_data->udp_tunnels) >
3779 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM);
3780
3781 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) {
205a55f4
JK		 3782 if (nic_data->udp_tunnels[i].type !=
3783 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID) {
e5fbd977
JC		 3784 efx_dword_t entry;
3785
3786 EFX_POPULATE_DWORD_2(entry,
3787 TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT,
3788 ntohs(nic_data->udp_tunnels[i].port),
3789 TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL,
3790 nic_data->udp_tunnels[i].type);
3791 *_MCDI_ARRAY_DWORD(inbuf,
3792 SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES,
3793 num_entries++) = entry;
3794 }
3795 }
3796
3797 BUILD_BUG_ON((MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST -
3798 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST) * 8 !=
3799 EFX_WORD_1_LBN);
3800 BUILD_BUG_ON(MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN * 8 !=
3801 EFX_WORD_1_WIDTH);
3802 EFX_POPULATE_DWORD_2(flags_and_num_entries,
3803 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING,
3804 !!unloading,
3805 EFX_WORD_1, num_entries);
3806 *_MCDI_DWORD(inbuf, SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS) =
3807 flags_and_num_entries;
3808
3809 inlen = MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num_entries);
3810
3811 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS,
3812 inbuf, inlen, outbuf, sizeof(outbuf), &outlen);
3813 if (rc == -EIO) {
3814 /* Most likely the MC rebooted due to another function also
3815 * setting its tunnel port list. Mark the tunnel port list as
3816 * dirty, so it will be pushed upon coming up from the reboot.
3817 */
3818 nic_data->udp_tunnels_dirty = true;
3819 return 0;
3820 }
3821
3822 if (rc) {
3823 /* expected not available on unprivileged functions */
3824 if (rc != -EPERM)
3825 netif_warn(efx, drv, efx->net_dev,
3826 "Unable to set UDP tunnel ports; rc=%d.\n", rc);
3827 } else if (MCDI_DWORD(outbuf, SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS) &
3828 (1 << MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN)) {
3829 netif_info(efx, drv, efx->net_dev,
3830 "Rebooting MC due to UDP tunnel port list change\n");
3831 will_reset = true;
3832 if (unloading)
3833 /* Delay for the MC reset to complete. This will make
3834 * unloading other functions a bit smoother. This is a
3835 * race, but the other unload will work whichever way
3836 * it goes, this just avoids an unnecessary error
3837 * message.
3838 */
3839 msleep(100);
3840 }
3841 if (!will_reset && !unloading) {
3842 /* The caller will have detached, relying on the MC reset to
3843 * trigger a re-attach. Since there won't be an MC reset, we
3844 * have to do the attach ourselves.
3845 */
9c568fd8 3846 efx_device_attach_if_not_resetting(efx);
e5fbd977
JC		 3847 }
3848
3849 return rc;
3850}
3851
3852static int efx_ef10_udp_tnl_push_ports(struct efx_nic *efx)
3853{
3854 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3855 int rc = 0;
3856
3857 mutex_lock(&nic_data->udp_tunnels_lock);
3858 if (nic_data->udp_tunnels_dirty) {
3859 /* Make sure all TX are stopped while we modify the table, else
3860 * we might race against an efx_features_check().
3861 */
3862 efx_device_detach_sync(efx);
3863 rc = efx_ef10_set_udp_tnl_ports(efx, false);
3864 }
3865 mutex_unlock(&nic_data->udp_tunnels_lock);
3866 return rc;
3867}
3868
205a55f4
JK		 3869static int efx_ef10_udp_tnl_set_port(struct net_device *dev,
3870 unsigned int table, unsigned int entry,
3871 struct udp_tunnel_info *ti)
e5fbd977 3872{
205a55f4
JK		 3873 struct efx_nic *efx = netdev_priv(dev);
3874 struct efx_ef10_nic_data *nic_data;
3875 int efx_tunnel_type, rc;
e5fbd977 3876
205a55f4
JK		 3877 if (ti->type == UDP_TUNNEL_TYPE_VXLAN)
3878 efx_tunnel_type = TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN;
3879 else
3880 efx_tunnel_type = TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE;
e5fbd977 3881
205a55f4 3882 nic_data = efx->nic_data;
e5fbd977
JC		 3883 if (!(nic_data->datapath_caps &
3884 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
205a55f4 3885 return -EOPNOTSUPP;
e5fbd977
JC		 3886
3887 mutex_lock(&nic_data->udp_tunnels_lock);
3888 /* Make sure all TX are stopped while we add to the table, else we
3889 * might race against an efx_features_check().
3890 */
3891 efx_device_detach_sync(efx);
205a55f4
JK		 3892 nic_data->udp_tunnels[entry].type = efx_tunnel_type;
3893 nic_data->udp_tunnels[entry].port = ti->port;
3894 rc = efx_ef10_set_udp_tnl_ports(efx, false);
e5fbd977 3895 mutex_unlock(&nic_data->udp_tunnels_lock);
205a55f4 3896
e5fbd977
JC		 3897 return rc;
3898}
3899
3900/* Called under the TX lock with the TX queue running, hence no-one can be
3901 * in the middle of updating the UDP tunnels table. However, they could
3902 * have tried and failed the MCDI, in which case they'll have set the dirty
3903 * flag before dropping their locks.
3904 */
3905static bool efx_ef10_udp_tnl_has_port(struct efx_nic *efx, __be16 port)
3906{
3907 struct efx_ef10_nic_data *nic_data = efx->nic_data;
205a55f4 3908 size_t i;
e5fbd977
JC		 3909
3910 if (!(nic_data->datapath_caps &
3911 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
3912 return false;
3913
3914 if (nic_data->udp_tunnels_dirty)
3915 /* SW table may not match HW state, so just assume we can't
3916 * use any UDP tunnel offloads.
3917 */
3918 return false;
3919
205a55f4
JK		 3920 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i)
3921 if (nic_data->udp_tunnels[i].type !=
3922 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID &&
3923 nic_data->udp_tunnels[i].port == port)
3924 return true;
3925
3926 return false;
e5fbd977
JC		 3927}
3928
205a55f4
JK		 3929static int efx_ef10_udp_tnl_unset_port(struct net_device *dev,
3930 unsigned int table, unsigned int entry,
3931 struct udp_tunnel_info *ti)
e5fbd977 3932{
205a55f4
JK		 3933 struct efx_nic *efx = netdev_priv(dev);
3934 struct efx_ef10_nic_data *nic_data;
e5fbd977
JC		 3935 int rc;
3936
205a55f4 3937 nic_data = efx->nic_data;
e5fbd977
JC		 3938
3939 mutex_lock(&nic_data->udp_tunnels_lock);
3940 /* Make sure all TX are stopped while we remove from the table, else we
3941 * might race against an efx_features_check().
3942 */
3943 efx_device_detach_sync(efx);
205a55f4
JK		 3944 nic_data->udp_tunnels[entry].type = TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID;
3945 nic_data->udp_tunnels[entry].port = 0;
3946 rc = efx_ef10_set_udp_tnl_ports(efx, false);
e5fbd977 3947 mutex_unlock(&nic_data->udp_tunnels_lock);
205a55f4 3948
e5fbd977
JC		 3949 return rc;
3950}
3951
205a55f4
JK		 3952static const struct udp_tunnel_nic_info efx_ef10_udp_tunnels = {
3953 .set_port = efx_ef10_udp_tnl_set_port,
3954 .unset_port = efx_ef10_udp_tnl_unset_port,
3955 .flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP,
3956 .tables = {
3957 {
3958 .n_entries = 16,
3959 .tunnel_types = UDP_TUNNEL_TYPE_VXLAN |
3960 UDP_TUNNEL_TYPE_GENEVE,
3961 },
3962 },
3963};
3964
9b46132c
EC		 3965/* EF10 may have multiple datapath firmware variants within a
3966 * single version. Report which variants are running.
3967 */
3968static size_t efx_ef10_print_additional_fwver(struct efx_nic *efx, char *buf,
3969 size_t len)
3970{
3971 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3972
3973 return scnprintf(buf, len, " rx%x tx%x",
3974 nic_data->rx_dpcpu_fw_id,
3975 nic_data->tx_dpcpu_fw_id);
3976}
3977
be904b85
TZ		 3978static unsigned int ef10_check_caps(const struct efx_nic *efx,
3979 u8 flag,
3980 u32 offset)
3981{
3982 const struct efx_ef10_nic_data *nic_data = efx->nic_data;
3983
3984 switch (offset) {
3985 case(MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST):
3986 return nic_data->datapath_caps & BIT_ULL(flag);
3987 case(MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_OFST):
3988 return nic_data->datapath_caps2 & BIT_ULL(flag);
3989 default:
3990 return 0;
3991 }
3992}
3993
100a9db5
AR		 3994#define EF10_OFFLOAD_FEATURES \
3995 (NETIF_F_IP_CSUM | \
4a53ea8a 3996 NETIF_F_HW_VLAN_CTAG_FILTER | \
100a9db5
AR		 3997 NETIF_F_IPV6_CSUM | \
3998 NETIF_F_RXHASH | \
3999 NETIF_F_NTUPLE)
4000
02246a7f 4001const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
6f7f8aa6 4002 .is_vf = true,
03714bbb 4003 .mem_bar = efx_ef10_vf_mem_bar,
02246a7f
SS		 4004 .mem_map_size = efx_ef10_mem_map_size,
4005 .probe = efx_ef10_probe_vf,
4006 .remove = efx_ef10_remove,
4007 .dimension_resources = efx_ef10_dimension_resources,
4008 .init = efx_ef10_init_nic,
d3142c19 4009 .fini = efx_ef10_fini_nic,
087e9025 4010 .map_reset_reason = efx_ef10_map_reset_reason,
02246a7f
SS		 4011 .map_reset_flags = efx_ef10_map_reset_flags,
4012 .reset = efx_ef10_reset,
4013 .probe_port = efx_mcdi_port_probe,
4014 .remove_port = efx_mcdi_port_remove,
d700fe01 4015 .fini_dmaq = efx_fini_dmaq,
02246a7f
SS		 4016 .prepare_flr = efx_ef10_prepare_flr,
4017 .finish_flr = efx_port_dummy_op_void,
4018 .describe_stats = efx_ef10_describe_stats,
d7788196 4019 .update_stats = efx_ef10_update_stats_vf,
623b9988 4020 .update_stats_atomic = efx_ef10_update_stats_atomic_vf,
02246a7f
SS		 4021 .start_stats = efx_port_dummy_op_void,
4022 .pull_stats = efx_port_dummy_op_void,
4023 .stop_stats = efx_port_dummy_op_void,
02246a7f 4024 .push_irq_moderation = efx_ef10_push_irq_moderation,
af3c38d3 4025 .reconfigure_mac = efx_ef10_mac_reconfigure,
02246a7f
SS		 4026 .check_mac_fault = efx_mcdi_mac_check_fault,
4027 .reconfigure_port = efx_mcdi_port_reconfigure,
4028 .get_wol = efx_ef10_get_wol_vf,
4029 .set_wol = efx_ef10_set_wol_vf,
4030 .resume_wol = efx_port_dummy_op_void,
4031 .mcdi_request = efx_ef10_mcdi_request,
4032 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4033 .mcdi_read_response = efx_ef10_mcdi_read_response,
4034 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
c577e59e 4035 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
02246a7f
SS		 4036 .irq_enable_master = efx_port_dummy_op_void,
4037 .irq_test_generate = efx_ef10_irq_test_generate,
4038 .irq_disable_non_ev = efx_port_dummy_op_void,
4039 .irq_handle_msi = efx_ef10_msi_interrupt,
4040 .irq_handle_legacy = efx_ef10_legacy_interrupt,
4041 .tx_probe = efx_ef10_tx_probe,
4042 .tx_init = efx_ef10_tx_init,
8ee4c907 4043 .tx_remove = efx_mcdi_tx_remove,
02246a7f 4044 .tx_write = efx_ef10_tx_write,
e9117e50 4045 .tx_limit_len = efx_ef10_tx_limit_len,
51b35a45 4046 .tx_enqueue = __efx_enqueue_skb,
90c914d2
AM		 4047 .rx_push_rss_config = efx_mcdi_vf_rx_push_rss_config,
4048 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config,
8da92642
AM		 4049 .rx_probe = efx_mcdi_rx_probe,
4050 .rx_init = efx_mcdi_rx_init,
4051 .rx_remove = efx_mcdi_rx_remove,
02246a7f
SS		 4052 .rx_write = efx_ef10_rx_write,
4053 .rx_defer_refill = efx_ef10_rx_defer_refill,
51b35a45 4054 .rx_packet = __efx_rx_packet,
4438b587 4055 .ev_probe = efx_mcdi_ev_probe,
02246a7f 4056 .ev_init = efx_ef10_ev_init,
4438b587
AM		 4057 .ev_fini = efx_mcdi_ev_fini,
4058 .ev_remove = efx_mcdi_ev_remove,
02246a7f
SS		 4059 .ev_process = efx_ef10_ev_process,
4060 .ev_read_ack = efx_ef10_ev_read_ack,
4061 .ev_test_generate = efx_ef10_ev_test_generate,
fd14e5fd 4062 .filter_table_probe = efx_ef10_filter_table_probe,
90c914d2
AM		 4063 .filter_table_restore = efx_mcdi_filter_table_restore,
4064 .filter_table_remove = efx_mcdi_filter_table_remove,
4065 .filter_update_rx_scatter = efx_mcdi_update_rx_scatter,
4066 .filter_insert = efx_mcdi_filter_insert,
4067 .filter_remove_safe = efx_mcdi_filter_remove_safe,
4068 .filter_get_safe = efx_mcdi_filter_get_safe,
4069 .filter_clear_rx = efx_mcdi_filter_clear_rx,
4070 .filter_count_rx_used = efx_mcdi_filter_count_rx_used,
4071 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit,
4072 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids,
02246a7f 4073#ifdef CONFIG_RFS_ACCEL
90c914d2 4074 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one,
02246a7f
SS		 4075#endif
4076#ifdef CONFIG_SFC_MTD
4077 .mtd_probe = efx_port_dummy_op_int,
4078#endif
4079 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
4080 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
4a53ea8a
AR		 4081 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
4082 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
02246a7f 4083#ifdef CONFIG_SFC_SRIOV
7b8c7b54
SS		 4084 .vswitching_probe = efx_ef10_vswitching_probe_vf,
4085 .vswitching_restore = efx_ef10_vswitching_restore_vf,
4086 .vswitching_remove = efx_ef10_vswitching_remove_vf,
02246a7f 4087#endif
0d5e0fbb 4088 .get_mac_address = efx_ef10_get_mac_address_vf,
910c8789 4089 .set_mac_address = efx_ef10_set_mac_address,
0d5e0fbb 4090
08a7b29b 4091 .get_phys_port_id = efx_ef10_get_phys_port_id,
02246a7f
SS		 4092 .revision = EFX_REV_HUNT_A0,
4093 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4094 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4095 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
4096 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
4097 .can_rx_scatter = true,
4098 .always_rx_scatter = true,
6f9f6ec2 4099 .min_interrupt_mode = EFX_INT_MODE_MSIX,
02246a7f 4100 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
100a9db5 4101 .offload_features = EF10_OFFLOAD_FEATURES,
02246a7f 4102 .mcdi_max_ver = 2,
90c914d2 4103 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS,
02246a7f
SS		 4104 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4105 1 << HWTSTAMP_FILTER_ALL,
f74d1995 4106 .rx_hash_key_size = 40,
be904b85 4107 .check_caps = ef10_check_caps,
9b46132c 4108 .print_additional_fwver = efx_ef10_print_additional_fwver,
51b35a45 4109 .sensor_event = efx_mcdi_sensor_event,
02246a7f
SS		 4110};
4111
8127d661 4112const struct efx_nic_type efx_hunt_a0_nic_type = {
6f7f8aa6 4113 .is_vf = false,
03714bbb 4114 .mem_bar = efx_ef10_pf_mem_bar,
8127d661 4115 .mem_map_size = efx_ef10_mem_map_size,
02246a7f 4116 .probe = efx_ef10_probe_pf,
8127d661
BH		 4117 .remove = efx_ef10_remove,
4118 .dimension_resources = efx_ef10_dimension_resources,
4119 .init = efx_ef10_init_nic,
d3142c19 4120 .fini = efx_ef10_fini_nic,
087e9025 4121 .map_reset_reason = efx_ef10_map_reset_reason,
8127d661 4122 .map_reset_flags = efx_ef10_map_reset_flags,
3e336261 4123 .reset = efx_ef10_reset,
8127d661
BH		 4124 .probe_port = efx_mcdi_port_probe,
4125 .remove_port = efx_mcdi_port_remove,
d700fe01 4126 .fini_dmaq = efx_fini_dmaq,
e283546c
EC		 4127 .prepare_flr = efx_ef10_prepare_flr,
4128 .finish_flr = efx_port_dummy_op_void,
8127d661 4129 .describe_stats = efx_ef10_describe_stats,
d7788196 4130 .update_stats = efx_ef10_update_stats_pf,
8127d661 4131 .start_stats = efx_mcdi_mac_start_stats,
f8f3b5ae 4132 .pull_stats = efx_mcdi_mac_pull_stats,
8127d661 4133 .stop_stats = efx_mcdi_mac_stop_stats,
8127d661
BH		 4134 .push_irq_moderation = efx_ef10_push_irq_moderation,
4135 .reconfigure_mac = efx_ef10_mac_reconfigure,
4136 .check_mac_fault = efx_mcdi_mac_check_fault,
4137 .reconfigure_port = efx_mcdi_port_reconfigure,
4138 .get_wol = efx_ef10_get_wol,
4139 .set_wol = efx_ef10_set_wol,
4140 .resume_wol = efx_port_dummy_op_void,
cab351be 4141 .get_fec_stats = efx_ef10_get_fec_stats,
74cd60a4 4142 .test_chip = efx_ef10_test_chip,
8127d661
BH		 4143 .test_nvram = efx_mcdi_nvram_test_all,
4144 .mcdi_request = efx_ef10_mcdi_request,
4145 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4146 .mcdi_read_response = efx_ef10_mcdi_read_response,
4147 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
c577e59e 4148 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
8127d661
BH		 4149 .irq_enable_master = efx_port_dummy_op_void,
4150 .irq_test_generate = efx_ef10_irq_test_generate,
4151 .irq_disable_non_ev = efx_port_dummy_op_void,
4152 .irq_handle_msi = efx_ef10_msi_interrupt,
4153 .irq_handle_legacy = efx_ef10_legacy_interrupt,
4154 .tx_probe = efx_ef10_tx_probe,
4155 .tx_init = efx_ef10_tx_init,
8ee4c907 4156 .tx_remove = efx_mcdi_tx_remove,
8127d661 4157 .tx_write = efx_ef10_tx_write,
e9117e50 4158 .tx_limit_len = efx_ef10_tx_limit_len,
51b35a45 4159 .tx_enqueue = __efx_enqueue_skb,
90c914d2
AM		 4160 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config,
4161 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config,
4162 .rx_push_rss_context_config = efx_mcdi_rx_push_rss_context_config,
4163 .rx_pull_rss_context_config = efx_mcdi_rx_pull_rss_context_config,
4164 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts,
8da92642
AM		 4165 .rx_probe = efx_mcdi_rx_probe,
4166 .rx_init = efx_mcdi_rx_init,
4167 .rx_remove = efx_mcdi_rx_remove,
8127d661
BH		 4168 .rx_write = efx_ef10_rx_write,
4169 .rx_defer_refill = efx_ef10_rx_defer_refill,
51b35a45 4170 .rx_packet = __efx_rx_packet,
4438b587 4171 .ev_probe = efx_mcdi_ev_probe,
8127d661 4172 .ev_init = efx_ef10_ev_init,
4438b587
AM		 4173 .ev_fini = efx_mcdi_ev_fini,
4174 .ev_remove = efx_mcdi_ev_remove,
8127d661
BH		 4175 .ev_process = efx_ef10_ev_process,
4176 .ev_read_ack = efx_ef10_ev_read_ack,
4177 .ev_test_generate = efx_ef10_ev_test_generate,
fd14e5fd 4178 .filter_table_probe = efx_ef10_filter_table_probe,
90c914d2
AM		 4179 .filter_table_restore = efx_mcdi_filter_table_restore,
4180 .filter_table_remove = efx_mcdi_filter_table_remove,
4181 .filter_update_rx_scatter = efx_mcdi_update_rx_scatter,
4182 .filter_insert = efx_mcdi_filter_insert,
4183 .filter_remove_safe = efx_mcdi_filter_remove_safe,
4184 .filter_get_safe = efx_mcdi_filter_get_safe,
4185 .filter_clear_rx = efx_mcdi_filter_clear_rx,
4186 .filter_count_rx_used = efx_mcdi_filter_count_rx_used,
4187 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit,
4188 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids,
8127d661 4189#ifdef CONFIG_RFS_ACCEL
90c914d2 4190 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one,
8127d661
BH		 4191#endif
4192#ifdef CONFIG_SFC_MTD
4193 .mtd_probe = efx_ef10_mtd_probe,
4194 .mtd_rename = efx_mcdi_mtd_rename,
4195 .mtd_read = efx_mcdi_mtd_read,
4196 .mtd_erase = efx_mcdi_mtd_erase,
4197 .mtd_write = efx_mcdi_mtd_write,
4198 .mtd_sync = efx_mcdi_mtd_sync,
4199#endif
4200 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
bd9a265d
JC		 4201 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
4202 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
4a53ea8a
AR		 4203 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
4204 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
e5fbd977 4205 .udp_tnl_push_ports = efx_ef10_udp_tnl_push_ports,
e5fbd977 4206 .udp_tnl_has_port = efx_ef10_udp_tnl_has_port,
7fa8d547 4207#ifdef CONFIG_SFC_SRIOV
834e23dd 4208 .sriov_configure = efx_ef10_sriov_configure,
d98a4ffe
SS		 4209 .sriov_init = efx_ef10_sriov_init,
4210 .sriov_fini = efx_ef10_sriov_fini,
d98a4ffe
SS		 4211 .sriov_wanted = efx_ef10_sriov_wanted,
4212 .sriov_reset = efx_ef10_sriov_reset,
7fa8d547
SS		 4213 .sriov_flr = efx_ef10_sriov_flr,
4214 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
4215 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
4216 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
4217 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
4392dc69 4218 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
7b8c7b54
SS		 4219 .vswitching_probe = efx_ef10_vswitching_probe_pf,
4220 .vswitching_restore = efx_ef10_vswitching_restore_pf,
4221 .vswitching_remove = efx_ef10_vswitching_remove_pf,
7fa8d547 4222#endif
0d5e0fbb 4223 .get_mac_address = efx_ef10_get_mac_address_pf,
910c8789 4224 .set_mac_address = efx_ef10_set_mac_address,
46d1efd8 4225 .tso_versions = efx_ef10_tso_versions,
8127d661 4226
08a7b29b 4227 .get_phys_port_id = efx_ef10_get_phys_port_id,
8127d661
BH		 4228 .revision = EFX_REV_HUNT_A0,
4229 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4230 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4231 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
bd9a265d 4232 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
8127d661
BH		 4233 .can_rx_scatter = true,
4234 .always_rx_scatter = true,
de1deff9 4235 .option_descriptors = true,
6f9f6ec2 4236 .min_interrupt_mode = EFX_INT_MODE_LEGACY,
8127d661 4237 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
100a9db5 4238 .offload_features = EF10_OFFLOAD_FEATURES,
8127d661 4239 .mcdi_max_ver = 2,
90c914d2 4240 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS,
bd9a265d
JC		 4241 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4242 1 << HWTSTAMP_FILTER_ALL,
f74d1995 4243 .rx_hash_key_size = 40,
be904b85 4244 .check_caps = ef10_check_caps,
9b46132c 4245 .print_additional_fwver = efx_ef10_print_additional_fwver,
51b35a45 4246 .sensor_event = efx_mcdi_sensor_event,
8127d661 4247};
Linux 6.x block layer and io_uring tree(s)