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sfc: Associate primary and secondary functions of controller
[linux-2.6-block.git] / drivers / net / ethernet / sfc / ef10.c
CommitLineData
8127d661
BH		 1/****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10#include "net_driver.h"
11#include "ef10_regs.h"
12#include "io.h"
13#include "mcdi.h"
14#include "mcdi_pcol.h"
15#include "nic.h"
16#include "workarounds.h"
74cd60a4 17#include "selftest.h"
8127d661
BH		 18#include <linux/in.h>
19#include <linux/jhash.h>
20#include <linux/wait.h>
21#include <linux/workqueue.h>
22
23/* Hardware control for EF10 architecture including 'Huntington'. */
24
25#define EFX_EF10_DRVGEN_EV 7
26enum {
27 EFX_EF10_TEST = 1,
28 EFX_EF10_REFILL,
29};
30
31/* The reserved RSS context value */
32#define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
33
34/* The filter table(s) are managed by firmware and we have write-only
35 * access. When removing filters we must identify them to the
36 * firmware by a 64-bit handle, but this is too wide for Linux kernel
37 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
38 * be able to tell in advance whether a requested insertion will
39 * replace an existing filter. Therefore we maintain a software hash
40 * table, which should be at least as large as the hardware hash
41 * table.
42 *
43 * Huntington has a single 8K filter table shared between all filter
44 * types and both ports.
45 */
46#define HUNT_FILTER_TBL_ROWS 8192
47
48struct efx_ef10_filter_table {
49/* The RX match field masks supported by this fw & hw, in order of priority */
50 enum efx_filter_match_flags rx_match_flags[
51 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
52 unsigned int rx_match_count;
53
54 struct {
55 unsigned long spec; /* pointer to spec plus flag bits */
56/* BUSY flag indicates that an update is in progress. STACK_OLD is
57 * used to mark and sweep stack-owned MAC filters.
58 */
59#define EFX_EF10_FILTER_FLAG_BUSY 1UL
60#define EFX_EF10_FILTER_FLAG_STACK_OLD 2UL
61#define EFX_EF10_FILTER_FLAGS 3UL
62 u64 handle; /* firmware handle */
63 } *entry;
64 wait_queue_head_t waitq;
65/* Shadow of net_device address lists, guarded by mac_lock */
66#define EFX_EF10_FILTER_STACK_UC_MAX 32
67#define EFX_EF10_FILTER_STACK_MC_MAX 256
68 struct {
69 u8 addr[ETH_ALEN];
70 u16 id;
71 } stack_uc_list[EFX_EF10_FILTER_STACK_UC_MAX],
72 stack_mc_list[EFX_EF10_FILTER_STACK_MC_MAX];
73 int stack_uc_count; /* negative for PROMISC */
74 int stack_mc_count; /* negative for PROMISC/ALLMULTI */
75};
76
77/* An arbitrary search limit for the software hash table */
78#define EFX_EF10_FILTER_SEARCH_LIMIT 200
79
80static void efx_ef10_rx_push_indir_table(struct efx_nic *efx);
81static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
82static void efx_ef10_filter_table_remove(struct efx_nic *efx);
83
84static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
85{
86 efx_dword_t reg;
87
88 efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
89 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
90 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
91}
92
93static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
94{
95 return resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]);
96}
97
e5a2538a 98static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
8127d661
BH		 99{
100 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);
101 struct efx_ef10_nic_data *nic_data = efx->nic_data;
102 size_t outlen;
103 int rc;
104
105 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
106
107 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
108 outbuf, sizeof(outbuf), &outlen);
109 if (rc)
110 return rc;
e5a2538a
BH		 111 if (outlen < sizeof(outbuf)) {
112 netif_err(efx, drv, efx->net_dev,
113 "unable to read datapath firmware capabilities\n");
114 return -EIO;
115 }
116
117 nic_data->datapath_caps =
118 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
8127d661 119
e5a2538a
BH		 120 if (!(nic_data->datapath_caps &
121 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) {
122 netif_err(efx, drv, efx->net_dev,
123 "current firmware does not support TSO\n");
124 return -ENODEV;
125 }
126
127 if (!(nic_data->datapath_caps &
128 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
129 netif_err(efx, probe, efx->net_dev,
130 "current firmware does not support an RX prefix\n");
131 return -ENODEV;
8127d661
BH		 132 }
133
134 return 0;
135}
136
137static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
138{
139 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
140 int rc;
141
142 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
143 outbuf, sizeof(outbuf), NULL);
144 if (rc)
145 return rc;
146 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
147 return rc > 0 ? rc : -ERANGE;
148}
149
150static int efx_ef10_get_mac_address(struct efx_nic *efx, u8 *mac_address)
151{
152 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
153 size_t outlen;
154 int rc;
155
156 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
157
158 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
159 outbuf, sizeof(outbuf), &outlen);
160 if (rc)
161 return rc;
162 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
163 return -EIO;
164
165 memcpy(mac_address,
166 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE), ETH_ALEN);
167 return 0;
168}
169
170static int efx_ef10_probe(struct efx_nic *efx)
171{
172 struct efx_ef10_nic_data *nic_data;
173 int i, rc;
174
175 /* We can have one VI for each 8K region. However we need
176 * multiple TX queues per channel.
177 */
178 efx->max_channels =
179 min_t(unsigned int,
180 EFX_MAX_CHANNELS,
181 resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]) /
182 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
183 BUG_ON(efx->max_channels == 0);
184
185 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
186 if (!nic_data)
187 return -ENOMEM;
188 efx->nic_data = nic_data;
189
190 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
191 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
192 if (rc)
193 goto fail1;
194
195 /* Get the MC's warm boot count. In case it's rebooting right
196 * now, be prepared to retry.
197 */
198 i = 0;
199 for (;;) {
200 rc = efx_ef10_get_warm_boot_count(efx);
201 if (rc >= 0)
202 break;
203 if (++i == 5)
204 goto fail2;
205 ssleep(1);
206 }
207 nic_data->warm_boot_count = rc;
208
209 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
210
211 /* In case we're recovering from a crash (kexec), we want to
212 * cancel any outstanding request by the previous user of this
213 * function. We send a special message using the least
214 * significant bits of the 'high' (doorbell) register.
215 */
216 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
217
218 rc = efx_mcdi_init(efx);
219 if (rc)
220 goto fail2;
221
222 /* Reset (most) configuration for this function */
223 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
224 if (rc)
225 goto fail3;
226
227 /* Enable event logging */
228 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
229 if (rc)
230 goto fail3;
231
e5a2538a 232 rc = efx_ef10_init_datapath_caps(efx);
8127d661
BH		 233 if (rc < 0)
234 goto fail3;
235
236 efx->rx_packet_len_offset =
237 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
238
8127d661
BH		 239 rc = efx_mcdi_port_get_number(efx);
240 if (rc < 0)
241 goto fail3;
242 efx->port_num = rc;
243
244 rc = efx_ef10_get_mac_address(efx, efx->net_dev->perm_addr);
245 if (rc)
246 goto fail3;
247
248 rc = efx_ef10_get_sysclk_freq(efx);
249 if (rc < 0)
250 goto fail3;
251 efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
252
253 /* Check whether firmware supports bug 35388 workaround */
254 rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true);
255 if (rc == 0)
256 nic_data->workaround_35388 = true;
257 else if (rc != -ENOSYS && rc != -ENOENT)
258 goto fail3;
259 netif_dbg(efx, probe, efx->net_dev,
260 "workaround for bug 35388 is %sabled\n",
261 nic_data->workaround_35388 ? "en" : "dis");
262
263 rc = efx_mcdi_mon_probe(efx);
264 if (rc)
265 goto fail3;
266
8127d661
BH		 267 return 0;
268
269fail3:
270 efx_mcdi_fini(efx);
271fail2:
272 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
273fail1:
274 kfree(nic_data);
275 efx->nic_data = NULL;
276 return rc;
277}
278
279static int efx_ef10_free_vis(struct efx_nic *efx)
280{
1e0b8120
EC		 281 MCDI_DECLARE_BUF_OUT_OR_ERR(outbuf, 0);
282 size_t outlen;
283 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
284 outbuf, sizeof(outbuf), &outlen);
8127d661
BH		 285
286 /* -EALREADY means nothing to free, so ignore */
287 if (rc == -EALREADY)
288 rc = 0;
1e0b8120
EC		 289 if (rc)
290 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
291 rc);
8127d661
BH		 292 return rc;
293}
294
183233be
BH		 295#ifdef EFX_USE_PIO
296
297static void efx_ef10_free_piobufs(struct efx_nic *efx)
298{
299 struct efx_ef10_nic_data *nic_data = efx->nic_data;
300 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
301 unsigned int i;
302 int rc;
303
304 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
305
306 for (i = 0; i < nic_data->n_piobufs; i++) {
307 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
308 nic_data->piobuf_handle[i]);
309 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
310 NULL, 0, NULL);
311 WARN_ON(rc);
312 }
313
314 nic_data->n_piobufs = 0;
315}
316
317static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
318{
319 struct efx_ef10_nic_data *nic_data = efx->nic_data;
320 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
321 unsigned int i;
322 size_t outlen;
323 int rc = 0;
324
325 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
326
327 for (i = 0; i < n; i++) {
328 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
329 outbuf, sizeof(outbuf), &outlen);
330 if (rc)
331 break;
332 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
333 rc = -EIO;
334 break;
335 }
336 nic_data->piobuf_handle[i] =
337 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
338 netif_dbg(efx, probe, efx->net_dev,
339 "allocated PIO buffer %u handle %x\n", i,
340 nic_data->piobuf_handle[i]);
341 }
342
343 nic_data->n_piobufs = i;
344 if (rc)
345 efx_ef10_free_piobufs(efx);
346 return rc;
347}
348
349static int efx_ef10_link_piobufs(struct efx_nic *efx)
350{
351 struct efx_ef10_nic_data *nic_data = efx->nic_data;
352 MCDI_DECLARE_BUF(inbuf,
353 max(MC_CMD_LINK_PIOBUF_IN_LEN,
354 MC_CMD_UNLINK_PIOBUF_IN_LEN));
355 struct efx_channel *channel;
356 struct efx_tx_queue *tx_queue;
357 unsigned int offset, index;
358 int rc;
359
360 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
361 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
362
363 /* Link a buffer to each VI in the write-combining mapping */
364 for (index = 0; index < nic_data->n_piobufs; ++index) {
365 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
366 nic_data->piobuf_handle[index]);
367 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
368 nic_data->pio_write_vi_base + index);
369 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
370 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
371 NULL, 0, NULL);
372 if (rc) {
373 netif_err(efx, drv, efx->net_dev,
374 "failed to link VI %u to PIO buffer %u (%d)\n",
375 nic_data->pio_write_vi_base + index, index,
376 rc);
377 goto fail;
378 }
379 netif_dbg(efx, probe, efx->net_dev,
380 "linked VI %u to PIO buffer %u\n",
381 nic_data->pio_write_vi_base + index, index);
382 }
383
384 /* Link a buffer to each TX queue */
385 efx_for_each_channel(channel, efx) {
386 efx_for_each_channel_tx_queue(tx_queue, channel) {
387 /* We assign the PIO buffers to queues in
388 * reverse order to allow for the following
389 * special case.
390 */
391 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
392 tx_queue->channel->channel - 1) *
393 efx_piobuf_size);
394 index = offset / ER_DZ_TX_PIOBUF_SIZE;
395 offset = offset % ER_DZ_TX_PIOBUF_SIZE;
396
397 /* When the host page size is 4K, the first
398 * host page in the WC mapping may be within
399 * the same VI page as the last TX queue. We
400 * can only link one buffer to each VI.
401 */
402 if (tx_queue->queue == nic_data->pio_write_vi_base) {
403 BUG_ON(index != 0);
404 rc = 0;
405 } else {
406 MCDI_SET_DWORD(inbuf,
407 LINK_PIOBUF_IN_PIOBUF_HANDLE,
408 nic_data->piobuf_handle[index]);
409 MCDI_SET_DWORD(inbuf,
410 LINK_PIOBUF_IN_TXQ_INSTANCE,
411 tx_queue->queue);
412 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
413 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
414 NULL, 0, NULL);
415 }
416
417 if (rc) {
418 /* This is non-fatal; the TX path just
419 * won't use PIO for this queue
420 */
421 netif_err(efx, drv, efx->net_dev,
422 "failed to link VI %u to PIO buffer %u (%d)\n",
423 tx_queue->queue, index, rc);
424 tx_queue->piobuf = NULL;
425 } else {
426 tx_queue->piobuf =
427 nic_data->pio_write_base +
428 index * EFX_VI_PAGE_SIZE + offset;
429 tx_queue->piobuf_offset = offset;
430 netif_dbg(efx, probe, efx->net_dev,
431 "linked VI %u to PIO buffer %u offset %x addr %p\n",
432 tx_queue->queue, index,
433 tx_queue->piobuf_offset,
434 tx_queue->piobuf);
435 }
436 }
437 }
438
439 return 0;
440
441fail:
442 while (index--) {
443 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
444 nic_data->pio_write_vi_base + index);
445 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
446 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
447 NULL, 0, NULL);
448 }
449 return rc;
450}
451
452#else /* !EFX_USE_PIO */
453
454static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
455{
456 return n == 0 ? 0 : -ENOBUFS;
457}
458
459static int efx_ef10_link_piobufs(struct efx_nic *efx)
460{
461 return 0;
462}
463
464static void efx_ef10_free_piobufs(struct efx_nic *efx)
465{
466}
467
468#endif /* EFX_USE_PIO */
469
8127d661
BH		 470static void efx_ef10_remove(struct efx_nic *efx)
471{
472 struct efx_ef10_nic_data *nic_data = efx->nic_data;
473 int rc;
474
475 efx_mcdi_mon_remove(efx);
476
477 /* This needs to be after efx_ptp_remove_channel() with no filters */
478 efx_ef10_rx_free_indir_table(efx);
479
183233be
BH		 480 if (nic_data->wc_membase)
481 iounmap(nic_data->wc_membase);
482
8127d661
BH		 483 rc = efx_ef10_free_vis(efx);
484 WARN_ON(rc != 0);
485
183233be
BH		 486 if (!nic_data->must_restore_piobufs)
487 efx_ef10_free_piobufs(efx);
488
8127d661
BH		 489 efx_mcdi_fini(efx);
490 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
491 kfree(nic_data);
492}
493
494static int efx_ef10_alloc_vis(struct efx_nic *efx,
495 unsigned int min_vis, unsigned int max_vis)
496{
497 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
498 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
499 struct efx_ef10_nic_data *nic_data = efx->nic_data;
500 size_t outlen;
501 int rc;
502
503 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
504 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
505 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
506 outbuf, sizeof(outbuf), &outlen);
507 if (rc != 0)
508 return rc;
509
510 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
511 return -EIO;
512
513 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
514 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
515
516 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
517 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
518 return 0;
519}
520
183233be
BH		 521/* Note that the failure path of this function does not free
522 * resources, as this will be done by efx_ef10_remove().
523 */
8127d661
BH		 524static int efx_ef10_dimension_resources(struct efx_nic *efx)
525{
183233be
BH		 526 struct efx_ef10_nic_data *nic_data = efx->nic_data;
527 unsigned int uc_mem_map_size, wc_mem_map_size;
528 unsigned int min_vis, pio_write_vi_base, max_vis;
529 void __iomem *membase;
530 int rc;
531
532 min_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
8127d661 533
183233be
BH		 534#ifdef EFX_USE_PIO
535 /* Try to allocate PIO buffers if wanted and if the full
536 * number of PIO buffers would be sufficient to allocate one
537 * copy-buffer per TX channel. Failure is non-fatal, as there
538 * are only a small number of PIO buffers shared between all
539 * functions of the controller.
540 */
541 if (efx_piobuf_size != 0 &&
542 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
543 efx->n_tx_channels) {
544 unsigned int n_piobufs =
545 DIV_ROUND_UP(efx->n_tx_channels,
546 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
547
548 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
549 if (rc)
550 netif_err(efx, probe, efx->net_dev,
551 "failed to allocate PIO buffers (%d)\n", rc);
552 else
553 netif_dbg(efx, probe, efx->net_dev,
554 "allocated %u PIO buffers\n", n_piobufs);
555 }
556#else
557 nic_data->n_piobufs = 0;
558#endif
559
560 /* PIO buffers should be mapped with write-combining enabled,
561 * and we want to make single UC and WC mappings rather than
562 * several of each (in fact that's the only option if host
563 * page size is >4K). So we may allocate some extra VIs just
564 * for writing PIO buffers through.
565 */
566 uc_mem_map_size = PAGE_ALIGN((min_vis - 1) * EFX_VI_PAGE_SIZE +
567 ER_DZ_TX_PIOBUF);
568 if (nic_data->n_piobufs) {
569 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
570 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
571 nic_data->n_piobufs) *
572 EFX_VI_PAGE_SIZE) -
573 uc_mem_map_size);
574 max_vis = pio_write_vi_base + nic_data->n_piobufs;
575 } else {
576 pio_write_vi_base = 0;
577 wc_mem_map_size = 0;
578 max_vis = min_vis;
579 }
580
581 /* In case the last attached driver failed to free VIs, do it now */
582 rc = efx_ef10_free_vis(efx);
583 if (rc != 0)
584 return rc;
585
586 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
587 if (rc != 0)
588 return rc;
589
590 /* If we didn't get enough VIs to map all the PIO buffers, free the
591 * PIO buffers
592 */
593 if (nic_data->n_piobufs &&
594 nic_data->n_allocated_vis <
595 pio_write_vi_base + nic_data->n_piobufs) {
596 netif_dbg(efx, probe, efx->net_dev,
597 "%u VIs are not sufficient to map %u PIO buffers\n",
598 nic_data->n_allocated_vis, nic_data->n_piobufs);
599 efx_ef10_free_piobufs(efx);
600 }
601
602 /* Shrink the original UC mapping of the memory BAR */
603 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
604 if (!membase) {
605 netif_err(efx, probe, efx->net_dev,
606 "could not shrink memory BAR to %x\n",
607 uc_mem_map_size);
608 return -ENOMEM;
609 }
610 iounmap(efx->membase);
611 efx->membase = membase;
612
613 /* Set up the WC mapping if needed */
614 if (wc_mem_map_size) {
615 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
616 uc_mem_map_size,
617 wc_mem_map_size);
618 if (!nic_data->wc_membase) {
619 netif_err(efx, probe, efx->net_dev,
620 "could not allocate WC mapping of size %x\n",
621 wc_mem_map_size);
622 return -ENOMEM;
623 }
624 nic_data->pio_write_vi_base = pio_write_vi_base;
625 nic_data->pio_write_base =
626 nic_data->wc_membase +
627 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
628 uc_mem_map_size);
629
630 rc = efx_ef10_link_piobufs(efx);
631 if (rc)
632 efx_ef10_free_piobufs(efx);
633 }
634
635 netif_dbg(efx, probe, efx->net_dev,
636 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
637 &efx->membase_phys, efx->membase, uc_mem_map_size,
638 nic_data->wc_membase, wc_mem_map_size);
639
640 return 0;
8127d661
BH		 641}
642
643static int efx_ef10_init_nic(struct efx_nic *efx)
644{
645 struct efx_ef10_nic_data *nic_data = efx->nic_data;
646 int rc;
647
a915ccc9
BH		 648 if (nic_data->must_check_datapath_caps) {
649 rc = efx_ef10_init_datapath_caps(efx);
650 if (rc)
651 return rc;
652 nic_data->must_check_datapath_caps = false;
653 }
654
8127d661
BH		 655 if (nic_data->must_realloc_vis) {
656 /* We cannot let the number of VIs change now */
657 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
658 nic_data->n_allocated_vis);
659 if (rc)
660 return rc;
661 nic_data->must_realloc_vis = false;
662 }
663
183233be
BH		 664 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
665 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
666 if (rc == 0) {
667 rc = efx_ef10_link_piobufs(efx);
668 if (rc)
669 efx_ef10_free_piobufs(efx);
670 }
671
672 /* Log an error on failure, but this is non-fatal */
673 if (rc)
674 netif_err(efx, drv, efx->net_dev,
675 "failed to restore PIO buffers (%d)\n", rc);
676 nic_data->must_restore_piobufs = false;
677 }
678
8127d661
BH		 679 efx_ef10_rx_push_indir_table(efx);
680 return 0;
681}
682
683static int efx_ef10_map_reset_flags(u32 *flags)
684{
685 enum {
686 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
687 ETH_RESET_SHARED_SHIFT),
688 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
689 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
690 ETH_RESET_PHY | ETH_RESET_MGMT) <<
691 ETH_RESET_SHARED_SHIFT)
692 };
693
694 /* We assume for now that our PCI function is permitted to
695 * reset everything.
696 */
697
698 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
699 *flags &= ~EF10_RESET_MC;
700 return RESET_TYPE_WORLD;
701 }
702
703 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
704 *flags &= ~EF10_RESET_PORT;
705 return RESET_TYPE_ALL;
706 }
707
708 /* no invisible reset implemented */
709
710 return -EINVAL;
711}
712
713#define EF10_DMA_STAT(ext_name, mcdi_name) \
714 [EF10_STAT_ ## ext_name] = \
715 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
716#define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
717 [EF10_STAT_ ## int_name] = \
718 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
719#define EF10_OTHER_STAT(ext_name) \
720 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
721
722static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
723 EF10_DMA_STAT(tx_bytes, TX_BYTES),
724 EF10_DMA_STAT(tx_packets, TX_PKTS),
725 EF10_DMA_STAT(tx_pause, TX_PAUSE_PKTS),
726 EF10_DMA_STAT(tx_control, TX_CONTROL_PKTS),
727 EF10_DMA_STAT(tx_unicast, TX_UNICAST_PKTS),
728 EF10_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS),
729 EF10_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS),
730 EF10_DMA_STAT(tx_lt64, TX_LT64_PKTS),
731 EF10_DMA_STAT(tx_64, TX_64_PKTS),
732 EF10_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS),
733 EF10_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS),
734 EF10_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS),
735 EF10_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS),
736 EF10_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
737 EF10_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
738 EF10_DMA_STAT(rx_bytes, RX_BYTES),
739 EF10_DMA_INVIS_STAT(rx_bytes_minus_good_bytes, RX_BAD_BYTES),
740 EF10_OTHER_STAT(rx_good_bytes),
741 EF10_OTHER_STAT(rx_bad_bytes),
742 EF10_DMA_STAT(rx_packets, RX_PKTS),
743 EF10_DMA_STAT(rx_good, RX_GOOD_PKTS),
744 EF10_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS),
745 EF10_DMA_STAT(rx_pause, RX_PAUSE_PKTS),
746 EF10_DMA_STAT(rx_control, RX_CONTROL_PKTS),
747 EF10_DMA_STAT(rx_unicast, RX_UNICAST_PKTS),
748 EF10_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS),
749 EF10_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS),
750 EF10_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS),
751 EF10_DMA_STAT(rx_64, RX_64_PKTS),
752 EF10_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS),
753 EF10_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS),
754 EF10_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS),
755 EF10_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS),
756 EF10_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
757 EF10_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
758 EF10_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS),
759 EF10_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS),
760 EF10_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS),
761 EF10_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
762 EF10_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
763 EF10_DMA_STAT(rx_nodesc_drops, RX_NODESC_DROPS),
568d7a00
EC		 764 EF10_DMA_STAT(rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
765 EF10_DMA_STAT(rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
766 EF10_DMA_STAT(rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
767 EF10_DMA_STAT(rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
768 EF10_DMA_STAT(rx_pm_trunc_qbb, PM_TRUNC_QBB),
769 EF10_DMA_STAT(rx_pm_discard_qbb, PM_DISCARD_QBB),
770 EF10_DMA_STAT(rx_pm_discard_mapping, PM_DISCARD_MAPPING),
771 EF10_DMA_STAT(rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
772 EF10_DMA_STAT(rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
773 EF10_DMA_STAT(rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
774 EF10_DMA_STAT(rx_dp_emerg_fetch, RXDP_EMERGENCY_FETCH_CONDITIONS),
775 EF10_DMA_STAT(rx_dp_emerg_wait, RXDP_EMERGENCY_WAIT_CONDITIONS),
8127d661
BH		 776};
777
778#define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_tx_bytes) | \
779 (1ULL << EF10_STAT_tx_packets) | \
780 (1ULL << EF10_STAT_tx_pause) | \
781 (1ULL << EF10_STAT_tx_unicast) | \
782 (1ULL << EF10_STAT_tx_multicast) | \
783 (1ULL << EF10_STAT_tx_broadcast) | \
784 (1ULL << EF10_STAT_rx_bytes) | \
785 (1ULL << EF10_STAT_rx_bytes_minus_good_bytes) | \
786 (1ULL << EF10_STAT_rx_good_bytes) | \
787 (1ULL << EF10_STAT_rx_bad_bytes) | \
788 (1ULL << EF10_STAT_rx_packets) | \
789 (1ULL << EF10_STAT_rx_good) | \
790 (1ULL << EF10_STAT_rx_bad) | \
791 (1ULL << EF10_STAT_rx_pause) | \
792 (1ULL << EF10_STAT_rx_control) | \
793 (1ULL << EF10_STAT_rx_unicast) | \
794 (1ULL << EF10_STAT_rx_multicast) | \
795 (1ULL << EF10_STAT_rx_broadcast) | \
796 (1ULL << EF10_STAT_rx_lt64) | \
797 (1ULL << EF10_STAT_rx_64) | \
798 (1ULL << EF10_STAT_rx_65_to_127) | \
799 (1ULL << EF10_STAT_rx_128_to_255) | \
800 (1ULL << EF10_STAT_rx_256_to_511) | \
801 (1ULL << EF10_STAT_rx_512_to_1023) | \
802 (1ULL << EF10_STAT_rx_1024_to_15xx) | \
803 (1ULL << EF10_STAT_rx_15xx_to_jumbo) | \
804 (1ULL << EF10_STAT_rx_gtjumbo) | \
805 (1ULL << EF10_STAT_rx_bad_gtjumbo) | \
806 (1ULL << EF10_STAT_rx_overflow) | \
807 (1ULL << EF10_STAT_rx_nodesc_drops))
808
809/* These statistics are only provided by the 10G MAC. For a 10G/40G
810 * switchable port we do not expose these because they might not
811 * include all the packets they should.
812 */
813#define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_tx_control) | \
814 (1ULL << EF10_STAT_tx_lt64) | \
815 (1ULL << EF10_STAT_tx_64) | \
816 (1ULL << EF10_STAT_tx_65_to_127) | \
817 (1ULL << EF10_STAT_tx_128_to_255) | \
818 (1ULL << EF10_STAT_tx_256_to_511) | \
819 (1ULL << EF10_STAT_tx_512_to_1023) | \
820 (1ULL << EF10_STAT_tx_1024_to_15xx) | \
821 (1ULL << EF10_STAT_tx_15xx_to_jumbo))
822
823/* These statistics are only provided by the 40G MAC. For a 10G/40G
824 * switchable port we do expose these because the errors will otherwise
825 * be silent.
826 */
827#define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_rx_align_error) | \
828 (1ULL << EF10_STAT_rx_length_error))
829
568d7a00
EC		 830/* These statistics are only provided if the firmware supports the
831 * capability PM_AND_RXDP_COUNTERS.
832 */
833#define HUNT_PM_AND_RXDP_STAT_MASK ( \
834 (1ULL << EF10_STAT_rx_pm_trunc_bb_overflow) | \
835 (1ULL << EF10_STAT_rx_pm_discard_bb_overflow) | \
836 (1ULL << EF10_STAT_rx_pm_trunc_vfifo_full) | \
837 (1ULL << EF10_STAT_rx_pm_discard_vfifo_full) | \
838 (1ULL << EF10_STAT_rx_pm_trunc_qbb) | \
839 (1ULL << EF10_STAT_rx_pm_discard_qbb) | \
840 (1ULL << EF10_STAT_rx_pm_discard_mapping) | \
841 (1ULL << EF10_STAT_rx_dp_q_disabled_packets) | \
842 (1ULL << EF10_STAT_rx_dp_di_dropped_packets) | \
843 (1ULL << EF10_STAT_rx_dp_streaming_packets) | \
844 (1ULL << EF10_STAT_rx_dp_emerg_fetch) | \
845 (1ULL << EF10_STAT_rx_dp_emerg_wait))
846
4bae913b 847static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
8127d661 848{
4bae913b 849 u64 raw_mask = HUNT_COMMON_STAT_MASK;
8127d661 850 u32 port_caps = efx_mcdi_phy_get_caps(efx);
568d7a00 851 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661
BH		 852
853 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
4bae913b 854 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
8127d661 855 else
4bae913b 856 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
568d7a00
EC		 857
858 if (nic_data->datapath_caps &
859 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
860 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
861
4bae913b
EC		 862 return raw_mask;
863}
864
865static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
866{
867 u64 raw_mask = efx_ef10_raw_stat_mask(efx);
868
869#if BITS_PER_LONG == 64
870 mask[0] = raw_mask;
871#else
872 mask[0] = raw_mask & 0xffffffff;
873 mask[1] = raw_mask >> 32;
874#endif
8127d661
BH		 875}
876
877static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
878{
4bae913b
EC		 879 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
880
881 efx_ef10_get_stat_mask(efx, mask);
8127d661 882 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
4bae913b 883 mask, names);
8127d661
BH		 884}
885
886static int efx_ef10_try_update_nic_stats(struct efx_nic *efx)
887{
888 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4bae913b 889 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
8127d661
BH		 890 __le64 generation_start, generation_end;
891 u64 *stats = nic_data->stats;
892 __le64 *dma_stats;
893
4bae913b
EC		 894 efx_ef10_get_stat_mask(efx, mask);
895
8127d661
BH		 896 dma_stats = efx->stats_buffer.addr;
897 nic_data = efx->nic_data;
898
899 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
900 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
901 return 0;
902 rmb();
4bae913b 903 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
8127d661 904 stats, efx->stats_buffer.addr, false);
d546a893 905 rmb();
8127d661
BH		 906 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
907 if (generation_end != generation_start)
908 return -EAGAIN;
909
910 /* Update derived statistics */
f8f3b5ae 911 efx_nic_fix_nodesc_drop_stat(efx, &stats[EF10_STAT_rx_nodesc_drops]);
8127d661
BH		 912 stats[EF10_STAT_rx_good_bytes] =
913 stats[EF10_STAT_rx_bytes] -
914 stats[EF10_STAT_rx_bytes_minus_good_bytes];
915 efx_update_diff_stat(&stats[EF10_STAT_rx_bad_bytes],
916 stats[EF10_STAT_rx_bytes_minus_good_bytes]);
917
918 return 0;
919}
920
921
922static size_t efx_ef10_update_stats(struct efx_nic *efx, u64 *full_stats,
923 struct rtnl_link_stats64 *core_stats)
924{
4bae913b 925 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
8127d661
BH		 926 struct efx_ef10_nic_data *nic_data = efx->nic_data;
927 u64 *stats = nic_data->stats;
928 size_t stats_count = 0, index;
929 int retry;
930
4bae913b
EC		 931 efx_ef10_get_stat_mask(efx, mask);
932
8127d661
BH		 933 /* If we're unlucky enough to read statistics during the DMA, wait
934 * up to 10ms for it to finish (typically takes <500us)
935 */
936 for (retry = 0; retry < 100; ++retry) {
937 if (efx_ef10_try_update_nic_stats(efx) == 0)
938 break;
939 udelay(100);
940 }
941
942 if (full_stats) {
943 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
944 if (efx_ef10_stat_desc[index].name) {
945 *full_stats++ = stats[index];
946 ++stats_count;
947 }
948 }
949 }
950
951 if (core_stats) {
952 core_stats->rx_packets = stats[EF10_STAT_rx_packets];
953 core_stats->tx_packets = stats[EF10_STAT_tx_packets];
954 core_stats->rx_bytes = stats[EF10_STAT_rx_bytes];
955 core_stats->tx_bytes = stats[EF10_STAT_tx_bytes];
956 core_stats->rx_dropped = stats[EF10_STAT_rx_nodesc_drops];
957 core_stats->multicast = stats[EF10_STAT_rx_multicast];
958 core_stats->rx_length_errors =
959 stats[EF10_STAT_rx_gtjumbo] +
960 stats[EF10_STAT_rx_length_error];
961 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
962 core_stats->rx_frame_errors = stats[EF10_STAT_rx_align_error];
963 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
964 core_stats->rx_errors = (core_stats->rx_length_errors +
965 core_stats->rx_crc_errors +
966 core_stats->rx_frame_errors);
967 }
968
969 return stats_count;
970}
971
972static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
973{
974 struct efx_nic *efx = channel->efx;
975 unsigned int mode, value;
976 efx_dword_t timer_cmd;
977
978 if (channel->irq_moderation) {
979 mode = 3;
980 value = channel->irq_moderation - 1;
981 } else {
982 mode = 0;
983 value = 0;
984 }
985
986 if (EFX_EF10_WORKAROUND_35388(efx)) {
987 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
988 EFE_DD_EVQ_IND_TIMER_FLAGS,
989 ERF_DD_EVQ_IND_TIMER_MODE, mode,
990 ERF_DD_EVQ_IND_TIMER_VAL, value);
991 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
992 channel->channel);
993 } else {
994 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
995 ERF_DZ_TC_TIMER_VAL, value);
996 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
997 channel->channel);
998 }
999}
1000
1001static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1002{
1003 wol->supported = 0;
1004 wol->wolopts = 0;
1005 memset(&wol->sopass, 0, sizeof(wol->sopass));
1006}
1007
1008static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1009{
1010 if (type != 0)
1011 return -EINVAL;
1012 return 0;
1013}
1014
1015static void efx_ef10_mcdi_request(struct efx_nic *efx,
1016 const efx_dword_t *hdr, size_t hdr_len,
1017 const efx_dword_t *sdu, size_t sdu_len)
1018{
1019 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1020 u8 *pdu = nic_data->mcdi_buf.addr;
1021
1022 memcpy(pdu, hdr, hdr_len);
1023 memcpy(pdu + hdr_len, sdu, sdu_len);
1024 wmb();
1025
1026 /* The hardware provides 'low' and 'high' (doorbell) registers
1027 * for passing the 64-bit address of an MCDI request to
1028 * firmware. However the dwords are swapped by firmware. The
1029 * least significant bits of the doorbell are then 0 for all
1030 * MCDI requests due to alignment.
1031 */
1032 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1033 ER_DZ_MC_DB_LWRD);
1034 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1035 ER_DZ_MC_DB_HWRD);
1036}
1037
1038static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1039{
1040 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1041 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1042
1043 rmb();
1044 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1045}
1046
1047static void
1048efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1049 size_t offset, size_t outlen)
1050{
1051 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1052 const u8 *pdu = nic_data->mcdi_buf.addr;
1053
1054 memcpy(outbuf, pdu + offset, outlen);
1055}
1056
1057static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1058{
1059 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1060 int rc;
1061
1062 rc = efx_ef10_get_warm_boot_count(efx);
1063 if (rc < 0) {
1064 /* The firmware is presumably in the process of
1065 * rebooting. However, we are supposed to report each
1066 * reboot just once, so we must only do that once we
1067 * can read and store the updated warm boot count.
1068 */
1069 return 0;
1070 }
1071
1072 if (rc == nic_data->warm_boot_count)
1073 return 0;
1074
1075 nic_data->warm_boot_count = rc;
1076
1077 /* All our allocations have been reset */
1078 nic_data->must_realloc_vis = true;
1079 nic_data->must_restore_filters = true;
183233be 1080 nic_data->must_restore_piobufs = true;
8127d661
BH		 1081 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1082
a915ccc9
BH		 1083 /* The datapath firmware might have been changed */
1084 nic_data->must_check_datapath_caps = true;
1085
869070c5
BH		 1086 /* MAC statistics have been cleared on the NIC; clear the local
1087 * statistic that we update with efx_update_diff_stat().
1088 */
1089 nic_data->stats[EF10_STAT_rx_bad_bytes] = 0;
1090
8127d661
BH		 1091 return -EIO;
1092}
1093
1094/* Handle an MSI interrupt
1095 *
1096 * Handle an MSI hardware interrupt. This routine schedules event
1097 * queue processing. No interrupt acknowledgement cycle is necessary.
1098 * Also, we never need to check that the interrupt is for us, since
1099 * MSI interrupts cannot be shared.
1100 */
1101static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
1102{
1103 struct efx_msi_context *context = dev_id;
1104 struct efx_nic *efx = context->efx;
1105
1106 netif_vdbg(efx, intr, efx->net_dev,
1107 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
1108
1109 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
1110 /* Note test interrupts */
1111 if (context->index == efx->irq_level)
1112 efx->last_irq_cpu = raw_smp_processor_id();
1113
1114 /* Schedule processing of the channel */
1115 efx_schedule_channel_irq(efx->channel[context->index]);
1116 }
1117
1118 return IRQ_HANDLED;
1119}
1120
1121static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
1122{
1123 struct efx_nic *efx = dev_id;
1124 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1125 struct efx_channel *channel;
1126 efx_dword_t reg;
1127 u32 queues;
1128
1129 /* Read the ISR which also ACKs the interrupts */
1130 efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
1131 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
1132
1133 if (queues == 0)
1134 return IRQ_NONE;
1135
1136 if (likely(soft_enabled)) {
1137 /* Note test interrupts */
1138 if (queues & (1U << efx->irq_level))
1139 efx->last_irq_cpu = raw_smp_processor_id();
1140
1141 efx_for_each_channel(channel, efx) {
1142 if (queues & 1)
1143 efx_schedule_channel_irq(channel);
1144 queues >>= 1;
1145 }
1146 }
1147
1148 netif_vdbg(efx, intr, efx->net_dev,
1149 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1150 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1151
1152 return IRQ_HANDLED;
1153}
1154
1155static void efx_ef10_irq_test_generate(struct efx_nic *efx)
1156{
1157 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
1158
1159 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
1160
1161 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
1162 (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
1163 inbuf, sizeof(inbuf), NULL, 0, NULL);
1164}
1165
1166static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
1167{
1168 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
1169 (tx_queue->ptr_mask + 1) *
1170 sizeof(efx_qword_t),
1171 GFP_KERNEL);
1172}
1173
1174/* This writes to the TX_DESC_WPTR and also pushes data */
1175static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
1176 const efx_qword_t *txd)
1177{
1178 unsigned int write_ptr;
1179 efx_oword_t reg;
1180
1181 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1182 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
1183 reg.qword[0] = *txd;
1184 efx_writeo_page(tx_queue->efx, &reg,
1185 ER_DZ_TX_DESC_UPD, tx_queue->queue);
1186}
1187
1188static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
1189{
1190 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1191 EFX_BUF_SIZE));
1192 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_TXQ_OUT_LEN);
1193 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
1194 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
1195 struct efx_channel *channel = tx_queue->channel;
1196 struct efx_nic *efx = tx_queue->efx;
1197 size_t inlen, outlen;
1198 dma_addr_t dma_addr;
1199 efx_qword_t *txd;
1200 int rc;
1201 int i;
1202
1203 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
1204 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
1205 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
1206 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
1207 MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
1208 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
1209 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
1210 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
1211 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1212
1213 dma_addr = tx_queue->txd.buf.dma_addr;
1214
1215 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
1216 tx_queue->queue, entries, (u64)dma_addr);
1217
1218 for (i = 0; i < entries; ++i) {
1219 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
1220 dma_addr += EFX_BUF_SIZE;
1221 }
1222
1223 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
1224
1225 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
1226 outbuf, sizeof(outbuf), &outlen);
1227 if (rc)
1228 goto fail;
1229
1230 /* A previous user of this TX queue might have set us up the
1231 * bomb by writing a descriptor to the TX push collector but
1232 * not the doorbell. (Each collector belongs to a port, not a
1233 * queue or function, so cannot easily be reset.) We must
1234 * attempt to push a no-op descriptor in its place.
1235 */
1236 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
1237 tx_queue->insert_count = 1;
1238 txd = efx_tx_desc(tx_queue, 0);
1239 EFX_POPULATE_QWORD_4(*txd,
1240 ESF_DZ_TX_DESC_IS_OPT, true,
1241 ESF_DZ_TX_OPTION_TYPE,
1242 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
1243 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
1244 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
1245 tx_queue->write_count = 1;
1246 wmb();
1247 efx_ef10_push_tx_desc(tx_queue, txd);
1248
1249 return;
1250
1251fail:
1252 WARN_ON(true);
8127d661
BH		 1253}
1254
1255static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
1256{
1257 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
1258 MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_TXQ_OUT_LEN);
1259 struct efx_nic *efx = tx_queue->efx;
1260 size_t outlen;
1261 int rc;
1262
1263 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
1264 tx_queue->queue);
1265
1e0b8120 1266 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
8127d661
BH		 1267 outbuf, sizeof(outbuf), &outlen);
1268
1269 if (rc && rc != -EALREADY)
1270 goto fail;
1271
1272 return;
1273
1274fail:
1e0b8120
EC		 1275 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
1276 outbuf, outlen, rc);
8127d661
BH		 1277}
1278
1279static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
1280{
1281 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
1282}
1283
1284/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
1285static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
1286{
1287 unsigned int write_ptr;
1288 efx_dword_t reg;
1289
1290 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1291 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
1292 efx_writed_page(tx_queue->efx, &reg,
1293 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
1294}
1295
1296static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
1297{
1298 unsigned int old_write_count = tx_queue->write_count;
1299 struct efx_tx_buffer *buffer;
1300 unsigned int write_ptr;
1301 efx_qword_t *txd;
1302
1303 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
1304
1305 do {
1306 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1307 buffer = &tx_queue->buffer[write_ptr];
1308 txd = efx_tx_desc(tx_queue, write_ptr);
1309 ++tx_queue->write_count;
1310
1311 /* Create TX descriptor ring entry */
1312 if (buffer->flags & EFX_TX_BUF_OPTION) {
1313 *txd = buffer->option;
1314 } else {
1315 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
1316 EFX_POPULATE_QWORD_3(
1317 *txd,
1318 ESF_DZ_TX_KER_CONT,
1319 buffer->flags & EFX_TX_BUF_CONT,
1320 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
1321 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
1322 }
1323 } while (tx_queue->write_count != tx_queue->insert_count);
1324
1325 wmb(); /* Ensure descriptors are written before they are fetched */
1326
1327 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
1328 txd = efx_tx_desc(tx_queue,
1329 old_write_count & tx_queue->ptr_mask);
1330 efx_ef10_push_tx_desc(tx_queue, txd);
1331 ++tx_queue->pushes;
1332 } else {
1333 efx_ef10_notify_tx_desc(tx_queue);
1334 }
1335}
1336
1337static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context)
1338{
1339 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
1340 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
1341 size_t outlen;
1342 int rc;
1343
1344 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
1345 EVB_PORT_ID_ASSIGNED);
1346 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE,
1347 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE);
1348 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES,
1349 EFX_MAX_CHANNELS);
1350
1351 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
1352 outbuf, sizeof(outbuf), &outlen);
1353 if (rc != 0)
1354 return rc;
1355
1356 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
1357 return -EIO;
1358
1359 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
1360
1361 return 0;
1362}
1363
1364static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
1365{
1366 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
1367 int rc;
1368
1369 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
1370 context);
1371
1372 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
1373 NULL, 0, NULL);
1374 WARN_ON(rc != 0);
1375}
1376
1377static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context)
1378{
1379 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
1380 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
1381 int i, rc;
1382
1383 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
1384 context);
1385 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1386 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
1387
1388 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
1389 MCDI_PTR(tablebuf,
1390 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
1391 (u8) efx->rx_indir_table[i];
1392
1393 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
1394 sizeof(tablebuf), NULL, 0, NULL);
1395 if (rc != 0)
1396 return rc;
1397
1398 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
1399 context);
1400 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
1401 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
1402 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
1403 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
1404 efx->rx_hash_key[i];
1405
1406 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
1407 sizeof(keybuf), NULL, 0, NULL);
1408}
1409
1410static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
1411{
1412 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1413
1414 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
1415 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
1416 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1417}
1418
1419static void efx_ef10_rx_push_indir_table(struct efx_nic *efx)
1420{
1421 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1422 int rc;
1423
1424 netif_dbg(efx, drv, efx->net_dev, "pushing RX indirection table\n");
1425
1426 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID) {
1427 rc = efx_ef10_alloc_rss_context(efx, &nic_data->rx_rss_context);
1428 if (rc != 0)
1429 goto fail;
1430 }
1431
1432 rc = efx_ef10_populate_rss_table(efx, nic_data->rx_rss_context);
1433 if (rc != 0)
1434 goto fail;
1435
1436 return;
1437
1438fail:
1439 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
1440}
1441
1442static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
1443{
1444 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
1445 (rx_queue->ptr_mask + 1) *
1446 sizeof(efx_qword_t),
1447 GFP_KERNEL);
1448}
1449
1450static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
1451{
1452 MCDI_DECLARE_BUF(inbuf,
1453 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1454 EFX_BUF_SIZE));
1455 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_RXQ_OUT_LEN);
1456 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
1457 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
1458 struct efx_nic *efx = rx_queue->efx;
1459 size_t inlen, outlen;
1460 dma_addr_t dma_addr;
1461 int rc;
1462 int i;
1463
1464 rx_queue->scatter_n = 0;
1465 rx_queue->scatter_len = 0;
1466
1467 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
1468 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
1469 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
1470 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
1471 efx_rx_queue_index(rx_queue));
bd9a265d
JC		 1472 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
1473 INIT_RXQ_IN_FLAG_PREFIX, 1,
1474 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
8127d661
BH		 1475 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
1476 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1477
1478 dma_addr = rx_queue->rxd.buf.dma_addr;
1479
1480 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
1481 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
1482
1483 for (i = 0; i < entries; ++i) {
1484 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
1485 dma_addr += EFX_BUF_SIZE;
1486 }
1487
1488 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
1489
1490 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
1491 outbuf, sizeof(outbuf), &outlen);
1e0b8120 1492 WARN_ON(rc);
8127d661
BH		 1493
1494 return;
8127d661
BH		 1495}
1496
1497static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
1498{
1499 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
1500 MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_RXQ_OUT_LEN);
1501 struct efx_nic *efx = rx_queue->efx;
1502 size_t outlen;
1503 int rc;
1504
1505 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
1506 efx_rx_queue_index(rx_queue));
1507
1e0b8120 1508 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
8127d661
BH		 1509 outbuf, sizeof(outbuf), &outlen);
1510
1511 if (rc && rc != -EALREADY)
1512 goto fail;
1513
1514 return;
1515
1516fail:
1e0b8120
EC		 1517 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
1518 outbuf, outlen, rc);
8127d661
BH		 1519}
1520
1521static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
1522{
1523 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
1524}
1525
1526/* This creates an entry in the RX descriptor queue */
1527static inline void
1528efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
1529{
1530 struct efx_rx_buffer *rx_buf;
1531 efx_qword_t *rxd;
1532
1533 rxd = efx_rx_desc(rx_queue, index);
1534 rx_buf = efx_rx_buffer(rx_queue, index);
1535 EFX_POPULATE_QWORD_2(*rxd,
1536 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
1537 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
1538}
1539
1540static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
1541{
1542 struct efx_nic *efx = rx_queue->efx;
1543 unsigned int write_count;
1544 efx_dword_t reg;
1545
1546 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
1547 write_count = rx_queue->added_count & ~7;
1548 if (rx_queue->notified_count == write_count)
1549 return;
1550
1551 do
1552 efx_ef10_build_rx_desc(
1553 rx_queue,
1554 rx_queue->notified_count & rx_queue->ptr_mask);
1555 while (++rx_queue->notified_count != write_count);
1556
1557 wmb();
1558 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
1559 write_count & rx_queue->ptr_mask);
1560 efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
1561 efx_rx_queue_index(rx_queue));
1562}
1563
1564static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
1565
1566static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
1567{
1568 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
1569 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
1570 efx_qword_t event;
1571
1572 EFX_POPULATE_QWORD_2(event,
1573 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
1574 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
1575
1576 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
1577
1578 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
1579 * already swapped the data to little-endian order.
1580 */
1581 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
1582 sizeof(efx_qword_t));
1583
1584 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
1585 inbuf, sizeof(inbuf), 0,
1586 efx_ef10_rx_defer_refill_complete, 0);
1587}
1588
1589static void
1590efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
1591 int rc, efx_dword_t *outbuf,
1592 size_t outlen_actual)
1593{
1594 /* nothing to do */
1595}
1596
1597static int efx_ef10_ev_probe(struct efx_channel *channel)
1598{
1599 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
1600 (channel->eventq_mask + 1) *
1601 sizeof(efx_qword_t),
1602 GFP_KERNEL);
1603}
1604
1605static int efx_ef10_ev_init(struct efx_channel *channel)
1606{
1607 MCDI_DECLARE_BUF(inbuf,
1608 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
1609 EFX_BUF_SIZE));
1610 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN);
1611 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
1612 struct efx_nic *efx = channel->efx;
1613 struct efx_ef10_nic_data *nic_data;
1614 bool supports_rx_merge;
1615 size_t inlen, outlen;
1616 dma_addr_t dma_addr;
1617 int rc;
1618 int i;
1619
1620 nic_data = efx->nic_data;
1621 supports_rx_merge =
1622 !!(nic_data->datapath_caps &
1623 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
1624
1625 /* Fill event queue with all ones (i.e. empty events) */
1626 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
1627
1628 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
1629 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
1630 /* INIT_EVQ expects index in vector table, not absolute */
1631 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
1632 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
1633 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
1634 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
1635 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
1636 INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge);
1637 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
1638 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
1639 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
1640 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
1641 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
1642 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
1643 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
1644
1645 dma_addr = channel->eventq.buf.dma_addr;
1646 for (i = 0; i < entries; ++i) {
1647 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
1648 dma_addr += EFX_BUF_SIZE;
1649 }
1650
1651 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
1652
1653 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
1654 outbuf, sizeof(outbuf), &outlen);
8127d661 1655 /* IRQ return is ignored */
8127d661
BH		 1656 return rc;
1657}
1658
1659static void efx_ef10_ev_fini(struct efx_channel *channel)
1660{
1661 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
1662 MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_EVQ_OUT_LEN);
1663 struct efx_nic *efx = channel->efx;
1664 size_t outlen;
1665 int rc;
1666
1667 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
1668
1e0b8120 1669 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
8127d661
BH		 1670 outbuf, sizeof(outbuf), &outlen);
1671
1672 if (rc && rc != -EALREADY)
1673 goto fail;
1674
1675 return;
1676
1677fail:
1e0b8120
EC		 1678 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
1679 outbuf, outlen, rc);
8127d661
BH		 1680}
1681
1682static void efx_ef10_ev_remove(struct efx_channel *channel)
1683{
1684 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
1685}
1686
1687static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
1688 unsigned int rx_queue_label)
1689{
1690 struct efx_nic *efx = rx_queue->efx;
1691
1692 netif_info(efx, hw, efx->net_dev,
1693 "rx event arrived on queue %d labeled as queue %u\n",
1694 efx_rx_queue_index(rx_queue), rx_queue_label);
1695
1696 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1697}
1698
1699static void
1700efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
1701 unsigned int actual, unsigned int expected)
1702{
1703 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
1704 struct efx_nic *efx = rx_queue->efx;
1705
1706 netif_info(efx, hw, efx->net_dev,
1707 "dropped %d events (index=%d expected=%d)\n",
1708 dropped, actual, expected);
1709
1710 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1711}
1712
1713/* partially received RX was aborted. clean up. */
1714static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
1715{
1716 unsigned int rx_desc_ptr;
1717
1718 WARN_ON(rx_queue->scatter_n == 0);
1719
1720 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
1721 "scattered RX aborted (dropping %u buffers)\n",
1722 rx_queue->scatter_n);
1723
1724 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
1725
1726 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
1727 0, EFX_RX_PKT_DISCARD);
1728
1729 rx_queue->removed_count += rx_queue->scatter_n;
1730 rx_queue->scatter_n = 0;
1731 rx_queue->scatter_len = 0;
1732 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
1733}
1734
1735static int efx_ef10_handle_rx_event(struct efx_channel *channel,
1736 const efx_qword_t *event)
1737{
1738 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
1739 unsigned int n_descs, n_packets, i;
1740 struct efx_nic *efx = channel->efx;
1741 struct efx_rx_queue *rx_queue;
1742 bool rx_cont;
1743 u16 flags = 0;
1744
1745 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
1746 return 0;
1747
1748 /* Basic packet information */
1749 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
1750 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
1751 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
1752 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
1753 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
1754
1755 WARN_ON(EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT));
1756
1757 rx_queue = efx_channel_get_rx_queue(channel);
1758
1759 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
1760 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
1761
1762 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
1763 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
1764
1765 if (n_descs != rx_queue->scatter_n + 1) {
92a04168
BH		 1766 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1767
8127d661
BH		 1768 /* detect rx abort */
1769 if (unlikely(n_descs == rx_queue->scatter_n)) {
1770 WARN_ON(rx_bytes != 0);
1771 efx_ef10_handle_rx_abort(rx_queue);
1772 return 0;
1773 }
1774
92a04168
BH		 1775 /* Check that RX completion merging is valid, i.e.
1776 * the current firmware supports it and this is a
1777 * non-scattered packet.
1778 */
1779 if (!(nic_data->datapath_caps &
1780 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
1781 rx_queue->scatter_n != 0 || rx_cont) {
8127d661
BH		 1782 efx_ef10_handle_rx_bad_lbits(
1783 rx_queue, next_ptr_lbits,
1784 (rx_queue->removed_count +
1785 rx_queue->scatter_n + 1) &
1786 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
1787 return 0;
1788 }
1789
1790 /* Merged completion for multiple non-scattered packets */
1791 rx_queue->scatter_n = 1;
1792 rx_queue->scatter_len = 0;
1793 n_packets = n_descs;
1794 ++channel->n_rx_merge_events;
1795 channel->n_rx_merge_packets += n_packets;
1796 flags |= EFX_RX_PKT_PREFIX_LEN;
1797 } else {
1798 ++rx_queue->scatter_n;
1799 rx_queue->scatter_len += rx_bytes;
1800 if (rx_cont)
1801 return 0;
1802 n_packets = 1;
1803 }
1804
1805 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
1806 flags |= EFX_RX_PKT_DISCARD;
1807
1808 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
1809 channel->n_rx_ip_hdr_chksum_err += n_packets;
1810 } else if (unlikely(EFX_QWORD_FIELD(*event,
1811 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
1812 channel->n_rx_tcp_udp_chksum_err += n_packets;
1813 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
1814 rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
1815 flags |= EFX_RX_PKT_CSUMMED;
1816 }
1817
1818 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
1819 flags |= EFX_RX_PKT_TCP;
1820
1821 channel->irq_mod_score += 2 * n_packets;
1822
1823 /* Handle received packet(s) */
1824 for (i = 0; i < n_packets; i++) {
1825 efx_rx_packet(rx_queue,
1826 rx_queue->removed_count & rx_queue->ptr_mask,
1827 rx_queue->scatter_n, rx_queue->scatter_len,
1828 flags);
1829 rx_queue->removed_count += rx_queue->scatter_n;
1830 }
1831
1832 rx_queue->scatter_n = 0;
1833 rx_queue->scatter_len = 0;
1834
1835 return n_packets;
1836}
1837
1838static int
1839efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
1840{
1841 struct efx_nic *efx = channel->efx;
1842 struct efx_tx_queue *tx_queue;
1843 unsigned int tx_ev_desc_ptr;
1844 unsigned int tx_ev_q_label;
1845 int tx_descs = 0;
1846
1847 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
1848 return 0;
1849
1850 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
1851 return 0;
1852
1853 /* Transmit completion */
1854 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
1855 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
1856 tx_queue = efx_channel_get_tx_queue(channel,
1857 tx_ev_q_label % EFX_TXQ_TYPES);
1858 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
1859 tx_queue->ptr_mask);
1860 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
1861
1862 return tx_descs;
1863}
1864
1865static void
1866efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
1867{
1868 struct efx_nic *efx = channel->efx;
1869 int subcode;
1870
1871 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
1872
1873 switch (subcode) {
1874 case ESE_DZ_DRV_TIMER_EV:
1875 case ESE_DZ_DRV_WAKE_UP_EV:
1876 break;
1877 case ESE_DZ_DRV_START_UP_EV:
1878 /* event queue init complete. ok. */
1879 break;
1880 default:
1881 netif_err(efx, hw, efx->net_dev,
1882 "channel %d unknown driver event type %d"
1883 " (data " EFX_QWORD_FMT ")\n",
1884 channel->channel, subcode,
1885 EFX_QWORD_VAL(*event));
1886
1887 }
1888}
1889
1890static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
1891 efx_qword_t *event)
1892{
1893 struct efx_nic *efx = channel->efx;
1894 u32 subcode;
1895
1896 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
1897
1898 switch (subcode) {
1899 case EFX_EF10_TEST:
1900 channel->event_test_cpu = raw_smp_processor_id();
1901 break;
1902 case EFX_EF10_REFILL:
1903 /* The queue must be empty, so we won't receive any rx
1904 * events, so efx_process_channel() won't refill the
1905 * queue. Refill it here
1906 */
cce28794 1907 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
8127d661
BH		 1908 break;
1909 default:
1910 netif_err(efx, hw, efx->net_dev,
1911 "channel %d unknown driver event type %u"
1912 " (data " EFX_QWORD_FMT ")\n",
1913 channel->channel, (unsigned) subcode,
1914 EFX_QWORD_VAL(*event));
1915 }
1916}
1917
1918static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
1919{
1920 struct efx_nic *efx = channel->efx;
1921 efx_qword_t event, *p_event;
1922 unsigned int read_ptr;
1923 int ev_code;
1924 int tx_descs = 0;
1925 int spent = 0;
1926
1927 read_ptr = channel->eventq_read_ptr;
1928
1929 for (;;) {
1930 p_event = efx_event(channel, read_ptr);
1931 event = *p_event;
1932
1933 if (!efx_event_present(&event))
1934 break;
1935
1936 EFX_SET_QWORD(*p_event);
1937
1938 ++read_ptr;
1939
1940 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
1941
1942 netif_vdbg(efx, drv, efx->net_dev,
1943 "processing event on %d " EFX_QWORD_FMT "\n",
1944 channel->channel, EFX_QWORD_VAL(event));
1945
1946 switch (ev_code) {
1947 case ESE_DZ_EV_CODE_MCDI_EV:
1948 efx_mcdi_process_event(channel, &event);
1949 break;
1950 case ESE_DZ_EV_CODE_RX_EV:
1951 spent += efx_ef10_handle_rx_event(channel, &event);
1952 if (spent >= quota) {
1953 /* XXX can we split a merged event to
1954 * avoid going over-quota?
1955 */
1956 spent = quota;
1957 goto out;
1958 }
1959 break;
1960 case ESE_DZ_EV_CODE_TX_EV:
1961 tx_descs += efx_ef10_handle_tx_event(channel, &event);
1962 if (tx_descs > efx->txq_entries) {
1963 spent = quota;
1964 goto out;
1965 } else if (++spent == quota) {
1966 goto out;
1967 }
1968 break;
1969 case ESE_DZ_EV_CODE_DRIVER_EV:
1970 efx_ef10_handle_driver_event(channel, &event);
1971 if (++spent == quota)
1972 goto out;
1973 break;
1974 case EFX_EF10_DRVGEN_EV:
1975 efx_ef10_handle_driver_generated_event(channel, &event);
1976 break;
1977 default:
1978 netif_err(efx, hw, efx->net_dev,
1979 "channel %d unknown event type %d"
1980 " (data " EFX_QWORD_FMT ")\n",
1981 channel->channel, ev_code,
1982 EFX_QWORD_VAL(event));
1983 }
1984 }
1985
1986out:
1987 channel->eventq_read_ptr = read_ptr;
1988 return spent;
1989}
1990
1991static void efx_ef10_ev_read_ack(struct efx_channel *channel)
1992{
1993 struct efx_nic *efx = channel->efx;
1994 efx_dword_t rptr;
1995
1996 if (EFX_EF10_WORKAROUND_35388(efx)) {
1997 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
1998 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
1999 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
2000 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
2001
2002 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2003 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
2004 ERF_DD_EVQ_IND_RPTR,
2005 (channel->eventq_read_ptr &
2006 channel->eventq_mask) >>
2007 ERF_DD_EVQ_IND_RPTR_WIDTH);
2008 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2009 channel->channel);
2010 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2011 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
2012 ERF_DD_EVQ_IND_RPTR,
2013 channel->eventq_read_ptr &
2014 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
2015 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2016 channel->channel);
2017 } else {
2018 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
2019 channel->eventq_read_ptr &
2020 channel->eventq_mask);
2021 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
2022 }
2023}
2024
2025static void efx_ef10_ev_test_generate(struct efx_channel *channel)
2026{
2027 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2028 struct efx_nic *efx = channel->efx;
2029 efx_qword_t event;
2030 int rc;
2031
2032 EFX_POPULATE_QWORD_2(event,
2033 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2034 ESF_DZ_EV_DATA, EFX_EF10_TEST);
2035
2036 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2037
2038 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2039 * already swapped the data to little-endian order.
2040 */
2041 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2042 sizeof(efx_qword_t));
2043
2044 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
2045 NULL, 0, NULL);
2046 if (rc != 0)
2047 goto fail;
2048
2049 return;
2050
2051fail:
2052 WARN_ON(true);
2053 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2054}
2055
2056void efx_ef10_handle_drain_event(struct efx_nic *efx)
2057{
2058 if (atomic_dec_and_test(&efx->active_queues))
2059 wake_up(&efx->flush_wq);
2060
2061 WARN_ON(atomic_read(&efx->active_queues) < 0);
2062}
2063
2064static int efx_ef10_fini_dmaq(struct efx_nic *efx)
2065{
2066 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2067 struct efx_channel *channel;
2068 struct efx_tx_queue *tx_queue;
2069 struct efx_rx_queue *rx_queue;
2070 int pending;
2071
2072 /* If the MC has just rebooted, the TX/RX queues will have already been
2073 * torn down, but efx->active_queues needs to be set to zero.
2074 */
2075 if (nic_data->must_realloc_vis) {
2076 atomic_set(&efx->active_queues, 0);
2077 return 0;
2078 }
2079
2080 /* Do not attempt to write to the NIC during EEH recovery */
2081 if (efx->state != STATE_RECOVERY) {
2082 efx_for_each_channel(channel, efx) {
2083 efx_for_each_channel_rx_queue(rx_queue, channel)
2084 efx_ef10_rx_fini(rx_queue);
2085 efx_for_each_channel_tx_queue(tx_queue, channel)
2086 efx_ef10_tx_fini(tx_queue);
2087 }
2088
2089 wait_event_timeout(efx->flush_wq,
2090 atomic_read(&efx->active_queues) == 0,
2091 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
2092 pending = atomic_read(&efx->active_queues);
2093 if (pending) {
2094 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
2095 pending);
2096 return -ETIMEDOUT;
2097 }
2098 }
2099
2100 return 0;
2101}
2102
2103static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
2104 const struct efx_filter_spec *right)
2105{
2106 if ((left->match_flags ^ right->match_flags) |
2107 ((left->flags ^ right->flags) &
2108 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
2109 return false;
2110
2111 return memcmp(&left->outer_vid, &right->outer_vid,
2112 sizeof(struct efx_filter_spec) -
2113 offsetof(struct efx_filter_spec, outer_vid)) == 0;
2114}
2115
2116static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
2117{
2118 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
2119 return jhash2((const u32 *)&spec->outer_vid,
2120 (sizeof(struct efx_filter_spec) -
2121 offsetof(struct efx_filter_spec, outer_vid)) / 4,
2122 0);
2123 /* XXX should we randomise the initval? */
2124}
2125
2126/* Decide whether a filter should be exclusive or else should allow
2127 * delivery to additional recipients. Currently we decide that
2128 * filters for specific local unicast MAC and IP addresses are
2129 * exclusive.
2130 */
2131static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
2132{
2133 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
2134 !is_multicast_ether_addr(spec->loc_mac))
2135 return true;
2136
2137 if ((spec->match_flags &
2138 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
2139 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
2140 if (spec->ether_type == htons(ETH_P_IP) &&
2141 !ipv4_is_multicast(spec->loc_host[0]))
2142 return true;
2143 if (spec->ether_type == htons(ETH_P_IPV6) &&
2144 ((const u8 *)spec->loc_host)[0] != 0xff)
2145 return true;
2146 }
2147
2148 return false;
2149}
2150
2151static struct efx_filter_spec *
2152efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
2153 unsigned int filter_idx)
2154{
2155 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
2156 ~EFX_EF10_FILTER_FLAGS);
2157}
2158
2159static unsigned int
2160efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
2161 unsigned int filter_idx)
2162{
2163 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
2164}
2165
2166static void
2167efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
2168 unsigned int filter_idx,
2169 const struct efx_filter_spec *spec,
2170 unsigned int flags)
2171{
2172 table->entry[filter_idx].spec = (unsigned long)spec | flags;
2173}
2174
2175static void efx_ef10_filter_push_prep(struct efx_nic *efx,
2176 const struct efx_filter_spec *spec,
2177 efx_dword_t *inbuf, u64 handle,
2178 bool replacing)
2179{
2180 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2181
2182 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
2183
2184 if (replacing) {
2185 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2186 MC_CMD_FILTER_OP_IN_OP_REPLACE);
2187 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
2188 } else {
2189 u32 match_fields = 0;
2190
2191 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2192 efx_ef10_filter_is_exclusive(spec) ?
2193 MC_CMD_FILTER_OP_IN_OP_INSERT :
2194 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
2195
2196 /* Convert match flags and values. Unlike almost
2197 * everything else in MCDI, these fields are in
2198 * network byte order.
2199 */
2200 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
2201 match_fields |=
2202 is_multicast_ether_addr(spec->loc_mac) ?
2203 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
2204 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
2205#define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
2206 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
2207 match_fields |= \
2208 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
2209 mcdi_field ## _LBN; \
2210 BUILD_BUG_ON( \
2211 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
2212 sizeof(spec->gen_field)); \
2213 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
2214 &spec->gen_field, sizeof(spec->gen_field)); \
2215 }
2216 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
2217 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
2218 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
2219 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
2220 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
2221 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
2222 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
2223 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
2224 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
2225 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
2226#undef COPY_FIELD
2227 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
2228 match_fields);
2229 }
2230
2231 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
2232 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
2233 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2234 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
2235 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
2236 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
2237 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
2238 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE, spec->dmaq_id);
2239 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
2240 (spec->flags & EFX_FILTER_FLAG_RX_RSS) ?
2241 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
2242 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
2243 if (spec->flags & EFX_FILTER_FLAG_RX_RSS)
2244 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
2245 spec->rss_context !=
2246 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
2247 spec->rss_context : nic_data->rx_rss_context);
2248}
2249
2250static int efx_ef10_filter_push(struct efx_nic *efx,
2251 const struct efx_filter_spec *spec,
2252 u64 *handle, bool replacing)
2253{
2254 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2255 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
2256 int rc;
2257
2258 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
2259 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2260 outbuf, sizeof(outbuf), NULL);
2261 if (rc == 0)
2262 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
065e64c4
BH		 2263 if (rc == -ENOSPC)
2264 rc = -EBUSY; /* to match efx_farch_filter_insert() */
8127d661
BH		 2265 return rc;
2266}
2267
2268static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table,
2269 enum efx_filter_match_flags match_flags)
2270{
2271 unsigned int match_pri;
2272
2273 for (match_pri = 0;
2274 match_pri < table->rx_match_count;
2275 match_pri++)
2276 if (table->rx_match_flags[match_pri] == match_flags)
2277 return match_pri;
2278
2279 return -EPROTONOSUPPORT;
2280}
2281
2282static s32 efx_ef10_filter_insert(struct efx_nic *efx,
2283 struct efx_filter_spec *spec,
2284 bool replace_equal)
2285{
2286 struct efx_ef10_filter_table *table = efx->filter_state;
2287 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
2288 struct efx_filter_spec *saved_spec;
2289 unsigned int match_pri, hash;
2290 unsigned int priv_flags;
2291 bool replacing = false;
2292 int ins_index = -1;
2293 DEFINE_WAIT(wait);
2294 bool is_mc_recip;
2295 s32 rc;
2296
2297 /* For now, only support RX filters */
2298 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
2299 EFX_FILTER_FLAG_RX)
2300 return -EINVAL;
2301
2302 rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags);
2303 if (rc < 0)
2304 return rc;
2305 match_pri = rc;
2306
2307 hash = efx_ef10_filter_hash(spec);
2308 is_mc_recip = efx_filter_is_mc_recipient(spec);
2309 if (is_mc_recip)
2310 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
2311
2312 /* Find any existing filters with the same match tuple or
2313 * else a free slot to insert at. If any of them are busy,
2314 * we have to wait and retry.
2315 */
2316 for (;;) {
2317 unsigned int depth = 1;
2318 unsigned int i;
2319
2320 spin_lock_bh(&efx->filter_lock);
2321
2322 for (;;) {
2323 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2324 saved_spec = efx_ef10_filter_entry_spec(table, i);
2325
2326 if (!saved_spec) {
2327 if (ins_index < 0)
2328 ins_index = i;
2329 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
2330 if (table->entry[i].spec &
2331 EFX_EF10_FILTER_FLAG_BUSY)
2332 break;
2333 if (spec->priority < saved_spec->priority &&
2334 !(saved_spec->priority ==
2335 EFX_FILTER_PRI_REQUIRED &&
2336 saved_spec->flags &
2337 EFX_FILTER_FLAG_RX_STACK)) {
2338 rc = -EPERM;
2339 goto out_unlock;
2340 }
2341 if (!is_mc_recip) {
2342 /* This is the only one */
2343 if (spec->priority ==
2344 saved_spec->priority &&
2345 !replace_equal) {
2346 rc = -EEXIST;
2347 goto out_unlock;
2348 }
2349 ins_index = i;
2350 goto found;
2351 } else if (spec->priority >
2352 saved_spec->priority ||
2353 (spec->priority ==
2354 saved_spec->priority &&
2355 replace_equal)) {
2356 if (ins_index < 0)
2357 ins_index = i;
2358 else
2359 __set_bit(depth, mc_rem_map);
2360 }
2361 }
2362
2363 /* Once we reach the maximum search depth, use
2364 * the first suitable slot or return -EBUSY if
2365 * there was none
2366 */
2367 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
2368 if (ins_index < 0) {
2369 rc = -EBUSY;
2370 goto out_unlock;
2371 }
2372 goto found;
2373 }
2374
2375 ++depth;
2376 }
2377
2378 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
2379 spin_unlock_bh(&efx->filter_lock);
2380 schedule();
2381 }
2382
2383found:
2384 /* Create a software table entry if necessary, and mark it
2385 * busy. We might yet fail to insert, but any attempt to
2386 * insert a conflicting filter while we're waiting for the
2387 * firmware must find the busy entry.
2388 */
2389 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
2390 if (saved_spec) {
2391 if (spec->flags & EFX_FILTER_FLAG_RX_STACK) {
2392 /* Just make sure it won't be removed */
2393 saved_spec->flags |= EFX_FILTER_FLAG_RX_STACK;
2394 table->entry[ins_index].spec &=
2395 ~EFX_EF10_FILTER_FLAG_STACK_OLD;
2396 rc = ins_index;
2397 goto out_unlock;
2398 }
2399 replacing = true;
2400 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
2401 } else {
2402 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
2403 if (!saved_spec) {
2404 rc = -ENOMEM;
2405 goto out_unlock;
2406 }
2407 *saved_spec = *spec;
2408 priv_flags = 0;
2409 }
2410 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
2411 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
2412
2413 /* Mark lower-priority multicast recipients busy prior to removal */
2414 if (is_mc_recip) {
2415 unsigned int depth, i;
2416
2417 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
2418 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2419 if (test_bit(depth, mc_rem_map))
2420 table->entry[i].spec |=
2421 EFX_EF10_FILTER_FLAG_BUSY;
2422 }
2423 }
2424
2425 spin_unlock_bh(&efx->filter_lock);
2426
2427 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
2428 replacing);
2429
2430 /* Finalise the software table entry */
2431 spin_lock_bh(&efx->filter_lock);
2432 if (rc == 0) {
2433 if (replacing) {
2434 /* Update the fields that may differ */
2435 saved_spec->priority = spec->priority;
2436 saved_spec->flags &= EFX_FILTER_FLAG_RX_STACK;
2437 saved_spec->flags |= spec->flags;
2438 saved_spec->rss_context = spec->rss_context;
2439 saved_spec->dmaq_id = spec->dmaq_id;
2440 }
2441 } else if (!replacing) {
2442 kfree(saved_spec);
2443 saved_spec = NULL;
2444 }
2445 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
2446
2447 /* Remove and finalise entries for lower-priority multicast
2448 * recipients
2449 */
2450 if (is_mc_recip) {
2451 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2452 unsigned int depth, i;
2453
2454 memset(inbuf, 0, sizeof(inbuf));
2455
2456 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
2457 if (!test_bit(depth, mc_rem_map))
2458 continue;
2459
2460 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2461 saved_spec = efx_ef10_filter_entry_spec(table, i);
2462 priv_flags = efx_ef10_filter_entry_flags(table, i);
2463
2464 if (rc == 0) {
2465 spin_unlock_bh(&efx->filter_lock);
2466 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2467 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2468 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2469 table->entry[i].handle);
2470 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
2471 inbuf, sizeof(inbuf),
2472 NULL, 0, NULL);
2473 spin_lock_bh(&efx->filter_lock);
2474 }
2475
2476 if (rc == 0) {
2477 kfree(saved_spec);
2478 saved_spec = NULL;
2479 priv_flags = 0;
2480 } else {
2481 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
2482 }
2483 efx_ef10_filter_set_entry(table, i, saved_spec,
2484 priv_flags);
2485 }
2486 }
2487
2488 /* If successful, return the inserted filter ID */
2489 if (rc == 0)
2490 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
2491
2492 wake_up_all(&table->waitq);
2493out_unlock:
2494 spin_unlock_bh(&efx->filter_lock);
2495 finish_wait(&table->waitq, &wait);
2496 return rc;
2497}
2498
9fd8095d 2499static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
8127d661
BH		 2500{
2501 /* no need to do anything here on EF10 */
2502}
2503
2504/* Remove a filter.
2505 * If !stack_requested, remove by ID
2506 * If stack_requested, remove by index
2507 * Filter ID may come from userland and must be range-checked.
2508 */
2509static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
2510 enum efx_filter_priority priority,
2511 u32 filter_id, bool stack_requested)
2512{
2513 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
2514 struct efx_ef10_filter_table *table = efx->filter_state;
2515 MCDI_DECLARE_BUF(inbuf,
2516 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
2517 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
2518 struct efx_filter_spec *spec;
2519 DEFINE_WAIT(wait);
2520 int rc;
2521
2522 /* Find the software table entry and mark it busy. Don't
2523 * remove it yet; any attempt to update while we're waiting
2524 * for the firmware must find the busy entry.
2525 */
2526 for (;;) {
2527 spin_lock_bh(&efx->filter_lock);
2528 if (!(table->entry[filter_idx].spec &
2529 EFX_EF10_FILTER_FLAG_BUSY))
2530 break;
2531 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
2532 spin_unlock_bh(&efx->filter_lock);
2533 schedule();
2534 }
2535 spec = efx_ef10_filter_entry_spec(table, filter_idx);
2536 if (!spec || spec->priority > priority ||
2537 (!stack_requested &&
2538 efx_ef10_filter_rx_match_pri(table, spec->match_flags) !=
2539 filter_id / HUNT_FILTER_TBL_ROWS)) {
2540 rc = -ENOENT;
2541 goto out_unlock;
2542 }
2543 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2544 spin_unlock_bh(&efx->filter_lock);
2545
2546 if (spec->flags & EFX_FILTER_FLAG_RX_STACK && !stack_requested) {
2547 /* Reset steering of a stack-owned filter */
2548
2549 struct efx_filter_spec new_spec = *spec;
2550
2551 new_spec.priority = EFX_FILTER_PRI_REQUIRED;
2552 new_spec.flags = (EFX_FILTER_FLAG_RX |
2553 EFX_FILTER_FLAG_RX_RSS |
2554 EFX_FILTER_FLAG_RX_STACK);
2555 new_spec.dmaq_id = 0;
2556 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
2557 rc = efx_ef10_filter_push(efx, &new_spec,
2558 &table->entry[filter_idx].handle,
2559 true);
2560
2561 spin_lock_bh(&efx->filter_lock);
2562 if (rc == 0)
2563 *spec = new_spec;
2564 } else {
2565 /* Really remove the filter */
2566
2567 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2568 efx_ef10_filter_is_exclusive(spec) ?
2569 MC_CMD_FILTER_OP_IN_OP_REMOVE :
2570 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2571 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2572 table->entry[filter_idx].handle);
2573 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
2574 inbuf, sizeof(inbuf), NULL, 0, NULL);
2575
2576 spin_lock_bh(&efx->filter_lock);
2577 if (rc == 0) {
2578 kfree(spec);
2579 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
2580 }
2581 }
2582 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
2583 wake_up_all(&table->waitq);
2584out_unlock:
2585 spin_unlock_bh(&efx->filter_lock);
2586 finish_wait(&table->waitq, &wait);
2587 return rc;
2588}
2589
2590static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
2591 enum efx_filter_priority priority,
2592 u32 filter_id)
2593{
2594 return efx_ef10_filter_remove_internal(efx, priority, filter_id, false);
2595}
2596
2597static int efx_ef10_filter_get_safe(struct efx_nic *efx,
2598 enum efx_filter_priority priority,
2599 u32 filter_id, struct efx_filter_spec *spec)
2600{
2601 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
2602 struct efx_ef10_filter_table *table = efx->filter_state;
2603 const struct efx_filter_spec *saved_spec;
2604 int rc;
2605
2606 spin_lock_bh(&efx->filter_lock);
2607 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
2608 if (saved_spec && saved_spec->priority == priority &&
2609 efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) ==
2610 filter_id / HUNT_FILTER_TBL_ROWS) {
2611 *spec = *saved_spec;
2612 rc = 0;
2613 } else {
2614 rc = -ENOENT;
2615 }
2616 spin_unlock_bh(&efx->filter_lock);
2617 return rc;
2618}
2619
2620static void efx_ef10_filter_clear_rx(struct efx_nic *efx,
2621 enum efx_filter_priority priority)
2622{
2623 /* TODO */
2624}
2625
2626static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
2627 enum efx_filter_priority priority)
2628{
2629 struct efx_ef10_filter_table *table = efx->filter_state;
2630 unsigned int filter_idx;
2631 s32 count = 0;
2632
2633 spin_lock_bh(&efx->filter_lock);
2634 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2635 if (table->entry[filter_idx].spec &&
2636 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
2637 priority)
2638 ++count;
2639 }
2640 spin_unlock_bh(&efx->filter_lock);
2641 return count;
2642}
2643
2644static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
2645{
2646 struct efx_ef10_filter_table *table = efx->filter_state;
2647
2648 return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
2649}
2650
2651static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
2652 enum efx_filter_priority priority,
2653 u32 *buf, u32 size)
2654{
2655 struct efx_ef10_filter_table *table = efx->filter_state;
2656 struct efx_filter_spec *spec;
2657 unsigned int filter_idx;
2658 s32 count = 0;
2659
2660 spin_lock_bh(&efx->filter_lock);
2661 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2662 spec = efx_ef10_filter_entry_spec(table, filter_idx);
2663 if (spec && spec->priority == priority) {
2664 if (count == size) {
2665 count = -EMSGSIZE;
2666 break;
2667 }
2668 buf[count++] = (efx_ef10_filter_rx_match_pri(
2669 table, spec->match_flags) *
2670 HUNT_FILTER_TBL_ROWS +
2671 filter_idx);
2672 }
2673 }
2674 spin_unlock_bh(&efx->filter_lock);
2675 return count;
2676}
2677
2678#ifdef CONFIG_RFS_ACCEL
2679
2680static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
2681
2682static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
2683 struct efx_filter_spec *spec)
2684{
2685 struct efx_ef10_filter_table *table = efx->filter_state;
2686 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2687 struct efx_filter_spec *saved_spec;
2688 unsigned int hash, i, depth = 1;
2689 bool replacing = false;
2690 int ins_index = -1;
2691 u64 cookie;
2692 s32 rc;
2693
2694 /* Must be an RX filter without RSS and not for a multicast
2695 * destination address (RFS only works for connected sockets).
2696 * These restrictions allow us to pass only a tiny amount of
2697 * data through to the completion function.
2698 */
2699 EFX_WARN_ON_PARANOID(spec->flags !=
2700 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
2701 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
2702 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
2703
2704 hash = efx_ef10_filter_hash(spec);
2705
2706 spin_lock_bh(&efx->filter_lock);
2707
2708 /* Find any existing filter with the same match tuple or else
2709 * a free slot to insert at. If an existing filter is busy,
2710 * we have to give up.
2711 */
2712 for (;;) {
2713 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2714 saved_spec = efx_ef10_filter_entry_spec(table, i);
2715
2716 if (!saved_spec) {
2717 if (ins_index < 0)
2718 ins_index = i;
2719 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
2720 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
2721 rc = -EBUSY;
2722 goto fail_unlock;
2723 }
2724 EFX_WARN_ON_PARANOID(saved_spec->flags &
2725 EFX_FILTER_FLAG_RX_STACK);
2726 if (spec->priority < saved_spec->priority) {
2727 rc = -EPERM;
2728 goto fail_unlock;
2729 }
2730 ins_index = i;
2731 break;
2732 }
2733
2734 /* Once we reach the maximum search depth, use the
2735 * first suitable slot or return -EBUSY if there was
2736 * none
2737 */
2738 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
2739 if (ins_index < 0) {
2740 rc = -EBUSY;
2741 goto fail_unlock;
2742 }
2743 break;
2744 }
2745
2746 ++depth;
2747 }
2748
2749 /* Create a software table entry if necessary, and mark it
2750 * busy. We might yet fail to insert, but any attempt to
2751 * insert a conflicting filter while we're waiting for the
2752 * firmware must find the busy entry.
2753 */
2754 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
2755 if (saved_spec) {
2756 replacing = true;
2757 } else {
2758 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
2759 if (!saved_spec) {
2760 rc = -ENOMEM;
2761 goto fail_unlock;
2762 }
2763 *saved_spec = *spec;
2764 }
2765 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
2766 EFX_EF10_FILTER_FLAG_BUSY);
2767
2768 spin_unlock_bh(&efx->filter_lock);
2769
2770 /* Pack up the variables needed on completion */
2771 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
2772
2773 efx_ef10_filter_push_prep(efx, spec, inbuf,
2774 table->entry[ins_index].handle, replacing);
2775 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2776 MC_CMD_FILTER_OP_OUT_LEN,
2777 efx_ef10_filter_rfs_insert_complete, cookie);
2778
2779 return ins_index;
2780
2781fail_unlock:
2782 spin_unlock_bh(&efx->filter_lock);
2783 return rc;
2784}
2785
2786static void
2787efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
2788 int rc, efx_dword_t *outbuf,
2789 size_t outlen_actual)
2790{
2791 struct efx_ef10_filter_table *table = efx->filter_state;
2792 unsigned int ins_index, dmaq_id;
2793 struct efx_filter_spec *spec;
2794 bool replacing;
2795
2796 /* Unpack the cookie */
2797 replacing = cookie >> 31;
2798 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
2799 dmaq_id = cookie & 0xffff;
2800
2801 spin_lock_bh(&efx->filter_lock);
2802 spec = efx_ef10_filter_entry_spec(table, ins_index);
2803 if (rc == 0) {
2804 table->entry[ins_index].handle =
2805 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
2806 if (replacing)
2807 spec->dmaq_id = dmaq_id;
2808 } else if (!replacing) {
2809 kfree(spec);
2810 spec = NULL;
2811 }
2812 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
2813 spin_unlock_bh(&efx->filter_lock);
2814
2815 wake_up_all(&table->waitq);
2816}
2817
2818static void
2819efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
2820 unsigned long filter_idx,
2821 int rc, efx_dword_t *outbuf,
2822 size_t outlen_actual);
2823
2824static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
2825 unsigned int filter_idx)
2826{
2827 struct efx_ef10_filter_table *table = efx->filter_state;
2828 struct efx_filter_spec *spec =
2829 efx_ef10_filter_entry_spec(table, filter_idx);
2830 MCDI_DECLARE_BUF(inbuf,
2831 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
2832 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
2833
2834 if (!spec ||
2835 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
2836 spec->priority != EFX_FILTER_PRI_HINT ||
2837 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
2838 flow_id, filter_idx))
2839 return false;
2840
2841 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2842 MC_CMD_FILTER_OP_IN_OP_REMOVE);
2843 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2844 table->entry[filter_idx].handle);
2845 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
2846 efx_ef10_filter_rfs_expire_complete, filter_idx))
2847 return false;
2848
2849 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2850 return true;
2851}
2852
2853static void
2854efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
2855 unsigned long filter_idx,
2856 int rc, efx_dword_t *outbuf,
2857 size_t outlen_actual)
2858{
2859 struct efx_ef10_filter_table *table = efx->filter_state;
2860 struct efx_filter_spec *spec =
2861 efx_ef10_filter_entry_spec(table, filter_idx);
2862
2863 spin_lock_bh(&efx->filter_lock);
2864 if (rc == 0) {
2865 kfree(spec);
2866 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
2867 }
2868 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
2869 wake_up_all(&table->waitq);
2870 spin_unlock_bh(&efx->filter_lock);
2871}
2872
2873#endif /* CONFIG_RFS_ACCEL */
2874
2875static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
2876{
2877 int match_flags = 0;
2878
2879#define MAP_FLAG(gen_flag, mcdi_field) { \
2880 u32 old_mcdi_flags = mcdi_flags; \
2881 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
2882 mcdi_field ## _LBN); \
2883 if (mcdi_flags != old_mcdi_flags) \
2884 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
2885 }
2886 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
2887 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
2888 MAP_FLAG(REM_HOST, SRC_IP);
2889 MAP_FLAG(LOC_HOST, DST_IP);
2890 MAP_FLAG(REM_MAC, SRC_MAC);
2891 MAP_FLAG(REM_PORT, SRC_PORT);
2892 MAP_FLAG(LOC_MAC, DST_MAC);
2893 MAP_FLAG(LOC_PORT, DST_PORT);
2894 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
2895 MAP_FLAG(INNER_VID, INNER_VLAN);
2896 MAP_FLAG(OUTER_VID, OUTER_VLAN);
2897 MAP_FLAG(IP_PROTO, IP_PROTO);
2898#undef MAP_FLAG
2899
2900 /* Did we map them all? */
2901 if (mcdi_flags)
2902 return -EINVAL;
2903
2904 return match_flags;
2905}
2906
2907static int efx_ef10_filter_table_probe(struct efx_nic *efx)
2908{
2909 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
2910 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
2911 unsigned int pd_match_pri, pd_match_count;
2912 struct efx_ef10_filter_table *table;
2913 size_t outlen;
2914 int rc;
2915
2916 table = kzalloc(sizeof(*table), GFP_KERNEL);
2917 if (!table)
2918 return -ENOMEM;
2919
2920 /* Find out which RX filter types are supported, and their priorities */
2921 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
2922 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
2923 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
2924 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
2925 &outlen);
2926 if (rc)
2927 goto fail;
2928 pd_match_count = MCDI_VAR_ARRAY_LEN(
2929 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
2930 table->rx_match_count = 0;
2931
2932 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
2933 u32 mcdi_flags =
2934 MCDI_ARRAY_DWORD(
2935 outbuf,
2936 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
2937 pd_match_pri);
2938 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
2939 if (rc < 0) {
2940 netif_dbg(efx, probe, efx->net_dev,
2941 "%s: fw flags %#x pri %u not supported in driver\n",
2942 __func__, mcdi_flags, pd_match_pri);
2943 } else {
2944 netif_dbg(efx, probe, efx->net_dev,
2945 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
2946 __func__, mcdi_flags, pd_match_pri,
2947 rc, table->rx_match_count);
2948 table->rx_match_flags[table->rx_match_count++] = rc;
2949 }
2950 }
2951
2952 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
2953 if (!table->entry) {
2954 rc = -ENOMEM;
2955 goto fail;
2956 }
2957
2958 efx->filter_state = table;
2959 init_waitqueue_head(&table->waitq);
2960 return 0;
2961
2962fail:
2963 kfree(table);
2964 return rc;
2965}
2966
2967static void efx_ef10_filter_table_restore(struct efx_nic *efx)
2968{
2969 struct efx_ef10_filter_table *table = efx->filter_state;
2970 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2971 struct efx_filter_spec *spec;
2972 unsigned int filter_idx;
2973 bool failed = false;
2974 int rc;
2975
2976 if (!nic_data->must_restore_filters)
2977 return;
2978
2979 spin_lock_bh(&efx->filter_lock);
2980
2981 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2982 spec = efx_ef10_filter_entry_spec(table, filter_idx);
2983 if (!spec)
2984 continue;
2985
2986 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2987 spin_unlock_bh(&efx->filter_lock);
2988
2989 rc = efx_ef10_filter_push(efx, spec,
2990 &table->entry[filter_idx].handle,
2991 false);
2992 if (rc)
2993 failed = true;
2994
2995 spin_lock_bh(&efx->filter_lock);
2996 if (rc) {
2997 kfree(spec);
2998 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
2999 } else {
3000 table->entry[filter_idx].spec &=
3001 ~EFX_EF10_FILTER_FLAG_BUSY;
3002 }
3003 }
3004
3005 spin_unlock_bh(&efx->filter_lock);
3006
3007 if (failed)
3008 netif_err(efx, hw, efx->net_dev,
3009 "unable to restore all filters\n");
3010 else
3011 nic_data->must_restore_filters = false;
3012}
3013
3014static void efx_ef10_filter_table_remove(struct efx_nic *efx)
3015{
3016 struct efx_ef10_filter_table *table = efx->filter_state;
3017 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3018 struct efx_filter_spec *spec;
3019 unsigned int filter_idx;
3020 int rc;
3021
3022 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3023 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3024 if (!spec)
3025 continue;
3026
3027 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3028 efx_ef10_filter_is_exclusive(spec) ?
3029 MC_CMD_FILTER_OP_IN_OP_REMOVE :
3030 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3031 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3032 table->entry[filter_idx].handle);
3033 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3034 NULL, 0, NULL);
3035
3036 WARN_ON(rc != 0);
3037 kfree(spec);
3038 }
3039
3040 vfree(table->entry);
3041 kfree(table);
3042}
3043
3044static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
3045{
3046 struct efx_ef10_filter_table *table = efx->filter_state;
3047 struct net_device *net_dev = efx->net_dev;
3048 struct efx_filter_spec spec;
3049 bool remove_failed = false;
3050 struct netdev_hw_addr *uc;
3051 struct netdev_hw_addr *mc;
3052 unsigned int filter_idx;
3053 int i, n, rc;
3054
3055 if (!efx_dev_registered(efx))
3056 return;
3057
3058 /* Mark old filters that may need to be removed */
3059 spin_lock_bh(&efx->filter_lock);
3060 n = table->stack_uc_count < 0 ? 1 : table->stack_uc_count;
3061 for (i = 0; i < n; i++) {
3062 filter_idx = table->stack_uc_list[i].id % HUNT_FILTER_TBL_ROWS;
3063 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_STACK_OLD;
3064 }
3065 n = table->stack_mc_count < 0 ? 1 : table->stack_mc_count;
3066 for (i = 0; i < n; i++) {
3067 filter_idx = table->stack_mc_list[i].id % HUNT_FILTER_TBL_ROWS;
3068 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_STACK_OLD;
3069 }
3070 spin_unlock_bh(&efx->filter_lock);
3071
3072 /* Copy/convert the address lists; add the primary station
3073 * address and broadcast address
3074 */
3075 netif_addr_lock_bh(net_dev);
3076 if (net_dev->flags & IFF_PROMISC ||
3077 netdev_uc_count(net_dev) >= EFX_EF10_FILTER_STACK_UC_MAX) {
3078 table->stack_uc_count = -1;
3079 } else {
3080 table->stack_uc_count = 1 + netdev_uc_count(net_dev);
3081 memcpy(table->stack_uc_list[0].addr, net_dev->dev_addr,
3082 ETH_ALEN);
3083 i = 1;
3084 netdev_for_each_uc_addr(uc, net_dev) {
3085 memcpy(table->stack_uc_list[i].addr,
3086 uc->addr, ETH_ALEN);
3087 i++;
3088 }
3089 }
3090 if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI) ||
3091 netdev_mc_count(net_dev) >= EFX_EF10_FILTER_STACK_MC_MAX) {
3092 table->stack_mc_count = -1;
3093 } else {
3094 table->stack_mc_count = 1 + netdev_mc_count(net_dev);
3095 eth_broadcast_addr(table->stack_mc_list[0].addr);
3096 i = 1;
3097 netdev_for_each_mc_addr(mc, net_dev) {
3098 memcpy(table->stack_mc_list[i].addr,
3099 mc->addr, ETH_ALEN);
3100 i++;
3101 }
3102 }
3103 netif_addr_unlock_bh(net_dev);
3104
3105 /* Insert/renew unicast filters */
3106 if (table->stack_uc_count >= 0) {
3107 for (i = 0; i < table->stack_uc_count; i++) {
3108 efx_filter_init_rx(&spec, EFX_FILTER_PRI_REQUIRED,
3109 EFX_FILTER_FLAG_RX_RSS |
3110 EFX_FILTER_FLAG_RX_STACK,
3111 0);
3112 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
3113 table->stack_uc_list[i].addr);
3114 rc = efx_ef10_filter_insert(efx, &spec, true);
3115 if (rc < 0) {
3116 /* Fall back to unicast-promisc */
3117 while (i--)
3118 efx_ef10_filter_remove_safe(
3119 efx, EFX_FILTER_PRI_REQUIRED,
3120 table->stack_uc_list[i].id);
3121 table->stack_uc_count = -1;
3122 break;
3123 }
3124 table->stack_uc_list[i].id = rc;
3125 }
3126 }
3127 if (table->stack_uc_count < 0) {
3128 efx_filter_init_rx(&spec, EFX_FILTER_PRI_REQUIRED,
3129 EFX_FILTER_FLAG_RX_RSS |
3130 EFX_FILTER_FLAG_RX_STACK,
3131 0);
3132 efx_filter_set_uc_def(&spec);
3133 rc = efx_ef10_filter_insert(efx, &spec, true);
3134 if (rc < 0) {
3135 WARN_ON(1);
3136 table->stack_uc_count = 0;
3137 } else {
3138 table->stack_uc_list[0].id = rc;
3139 }
3140 }
3141
3142 /* Insert/renew multicast filters */
3143 if (table->stack_mc_count >= 0) {
3144 for (i = 0; i < table->stack_mc_count; i++) {
3145 efx_filter_init_rx(&spec, EFX_FILTER_PRI_REQUIRED,
3146 EFX_FILTER_FLAG_RX_RSS |
3147 EFX_FILTER_FLAG_RX_STACK,
3148 0);
3149 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
3150 table->stack_mc_list[i].addr);
3151 rc = efx_ef10_filter_insert(efx, &spec, true);
3152 if (rc < 0) {
3153 /* Fall back to multicast-promisc */
3154 while (i--)
3155 efx_ef10_filter_remove_safe(
3156 efx, EFX_FILTER_PRI_REQUIRED,
3157 table->stack_mc_list[i].id);
3158 table->stack_mc_count = -1;
3159 break;
3160 }
3161 table->stack_mc_list[i].id = rc;
3162 }
3163 }
3164 if (table->stack_mc_count < 0) {
3165 efx_filter_init_rx(&spec, EFX_FILTER_PRI_REQUIRED,
3166 EFX_FILTER_FLAG_RX_RSS |
3167 EFX_FILTER_FLAG_RX_STACK,
3168 0);
3169 efx_filter_set_mc_def(&spec);
3170 rc = efx_ef10_filter_insert(efx, &spec, true);
3171 if (rc < 0) {
3172 WARN_ON(1);
3173 table->stack_mc_count = 0;
3174 } else {
3175 table->stack_mc_list[0].id = rc;
3176 }
3177 }
3178
3179 /* Remove filters that weren't renewed. Since nothing else
3180 * changes the STACK_OLD flag or removes these filters, we
3181 * don't need to hold the filter_lock while scanning for
3182 * these filters.
3183 */
3184 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3185 if (ACCESS_ONCE(table->entry[i].spec) &
3186 EFX_EF10_FILTER_FLAG_STACK_OLD) {
3187 if (efx_ef10_filter_remove_internal(efx,
3188 EFX_FILTER_PRI_REQUIRED,
3189 i, true) < 0)
3190 remove_failed = true;
3191 }
3192 }
3193 WARN_ON(remove_failed);
3194}
3195
3196static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
3197{
3198 efx_ef10_filter_sync_rx_mode(efx);
3199
3200 return efx_mcdi_set_mac(efx);
3201}
3202
74cd60a4
JC		 3203static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
3204{
3205 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
3206
3207 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
3208 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
3209 NULL, 0, NULL);
3210}
3211
3212/* MC BISTs follow a different poll mechanism to phy BISTs.
3213 * The BIST is done in the poll handler on the MC, and the MCDI command
3214 * will block until the BIST is done.
3215 */
3216static int efx_ef10_poll_bist(struct efx_nic *efx)
3217{
3218 int rc;
3219 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
3220 size_t outlen;
3221 u32 result;
3222
3223 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
3224 outbuf, sizeof(outbuf), &outlen);
3225 if (rc != 0)
3226 return rc;
3227
3228 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
3229 return -EIO;
3230
3231 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
3232 switch (result) {
3233 case MC_CMD_POLL_BIST_PASSED:
3234 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
3235 return 0;
3236 case MC_CMD_POLL_BIST_TIMEOUT:
3237 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
3238 return -EIO;
3239 case MC_CMD_POLL_BIST_FAILED:
3240 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
3241 return -EIO;
3242 default:
3243 netif_err(efx, hw, efx->net_dev,
3244 "BIST returned unknown result %u", result);
3245 return -EIO;
3246 }
3247}
3248
3249static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
3250{
3251 int rc;
3252
3253 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
3254
3255 rc = efx_ef10_start_bist(efx, bist_type);
3256 if (rc != 0)
3257 return rc;
3258
3259 return efx_ef10_poll_bist(efx);
3260}
3261
3262static int
3263efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
3264{
3265 int rc, rc2;
3266
3267 efx_reset_down(efx, RESET_TYPE_WORLD);
3268
3269 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
3270 NULL, 0, NULL, 0, NULL);
3271 if (rc != 0)
3272 goto out;
3273
3274 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
3275 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
3276
3277 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
3278
3279out:
3280 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
3281 return rc ? rc : rc2;
3282}
3283
8127d661
BH		 3284#ifdef CONFIG_SFC_MTD
3285
3286struct efx_ef10_nvram_type_info {
3287 u16 type, type_mask;
3288 u8 port;
3289 const char *name;
3290};
3291
3292static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
3293 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
3294 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
3295 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
3296 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
3297 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
3298 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
3299 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
3300 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
3301 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
a84f3bf9 3302 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
8127d661
BH		 3303 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
3304};
3305
3306static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
3307 struct efx_mcdi_mtd_partition *part,
3308 unsigned int type)
3309{
3310 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
3311 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
3312 const struct efx_ef10_nvram_type_info *info;
3313 size_t size, erase_size, outlen;
3314 bool protected;
3315 int rc;
3316
3317 for (info = efx_ef10_nvram_types; ; info++) {
3318 if (info ==
3319 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
3320 return -ENODEV;
3321 if ((type & ~info->type_mask) == info->type)
3322 break;
3323 }
3324 if (info->port != efx_port_num(efx))
3325 return -ENODEV;
3326
3327 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
3328 if (rc)
3329 return rc;
3330 if (protected)
3331 return -ENODEV; /* hide it */
3332
3333 part->nvram_type = type;
3334
3335 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
3336 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
3337 outbuf, sizeof(outbuf), &outlen);
3338 if (rc)
3339 return rc;
3340 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
3341 return -EIO;
3342 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
3343 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
3344 part->fw_subtype = MCDI_DWORD(outbuf,
3345 NVRAM_METADATA_OUT_SUBTYPE);
3346
3347 part->common.dev_type_name = "EF10 NVRAM manager";
3348 part->common.type_name = info->name;
3349
3350 part->common.mtd.type = MTD_NORFLASH;
3351 part->common.mtd.flags = MTD_CAP_NORFLASH;
3352 part->common.mtd.size = size;
3353 part->common.mtd.erasesize = erase_size;
3354
3355 return 0;
3356}
3357
3358static int efx_ef10_mtd_probe(struct efx_nic *efx)
3359{
3360 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
3361 struct efx_mcdi_mtd_partition *parts;
3362 size_t outlen, n_parts_total, i, n_parts;
3363 unsigned int type;
3364 int rc;
3365
3366 ASSERT_RTNL();
3367
3368 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
3369 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
3370 outbuf, sizeof(outbuf), &outlen);
3371 if (rc)
3372 return rc;
3373 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
3374 return -EIO;
3375
3376 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
3377 if (n_parts_total >
3378 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
3379 return -EIO;
3380
3381 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
3382 if (!parts)
3383 return -ENOMEM;
3384
3385 n_parts = 0;
3386 for (i = 0; i < n_parts_total; i++) {
3387 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
3388 i);
3389 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
3390 if (rc == 0)
3391 n_parts++;
3392 else if (rc != -ENODEV)
3393 goto fail;
3394 }
3395
3396 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
3397fail:
3398 if (rc)
3399 kfree(parts);
3400 return rc;
3401}
3402
3403#endif /* CONFIG_SFC_MTD */
3404
3405static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
3406{
3407 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
3408}
3409
bd9a265d
JC		 3410static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
3411 bool temp)
3412{
3413 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
3414 int rc;
3415
3416 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
3417 channel->sync_events_state == SYNC_EVENTS_VALID ||
3418 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
3419 return 0;
3420 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
3421
3422 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
3423 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
3424 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
3425 channel->channel);
3426
3427 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
3428 inbuf, sizeof(inbuf), NULL, 0, NULL);
3429
3430 if (rc != 0)
3431 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
3432 SYNC_EVENTS_DISABLED;
3433
3434 return rc;
3435}
3436
3437static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
3438 bool temp)
3439{
3440 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
3441 int rc;
3442
3443 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
3444 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
3445 return 0;
3446 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
3447 channel->sync_events_state = SYNC_EVENTS_DISABLED;
3448 return 0;
3449 }
3450 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
3451 SYNC_EVENTS_DISABLED;
3452
3453 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
3454 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
3455 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
3456 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
3457 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
3458 channel->channel);
3459
3460 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
3461 inbuf, sizeof(inbuf), NULL, 0, NULL);
3462
3463 return rc;
3464}
3465
3466static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
3467 bool temp)
3468{
3469 int (*set)(struct efx_channel *channel, bool temp);
3470 struct efx_channel *channel;
3471
3472 set = en ?
3473 efx_ef10_rx_enable_timestamping :
3474 efx_ef10_rx_disable_timestamping;
3475
3476 efx_for_each_channel(channel, efx) {
3477 int rc = set(channel, temp);
3478 if (en && rc != 0) {
3479 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
3480 return rc;
3481 }
3482 }
3483
3484 return 0;
3485}
3486
3487static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
3488 struct hwtstamp_config *init)
3489{
3490 int rc;
3491
3492 switch (init->rx_filter) {
3493 case HWTSTAMP_FILTER_NONE:
3494 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
3495 /* if TX timestamping is still requested then leave PTP on */
3496 return efx_ptp_change_mode(efx,
3497 init->tx_type != HWTSTAMP_TX_OFF, 0);
3498 case HWTSTAMP_FILTER_ALL:
3499 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3500 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3501 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3502 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3503 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3504 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3505 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3506 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3507 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3508 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3509 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3510 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3511 init->rx_filter = HWTSTAMP_FILTER_ALL;
3512 rc = efx_ptp_change_mode(efx, true, 0);
3513 if (!rc)
3514 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
3515 if (rc)
3516 efx_ptp_change_mode(efx, false, 0);
3517 return rc;
3518 default:
3519 return -ERANGE;
3520 }
3521}
3522
8127d661
BH		 3523const struct efx_nic_type efx_hunt_a0_nic_type = {
3524 .mem_map_size = efx_ef10_mem_map_size,
3525 .probe = efx_ef10_probe,
3526 .remove = efx_ef10_remove,
3527 .dimension_resources = efx_ef10_dimension_resources,
3528 .init = efx_ef10_init_nic,
3529 .fini = efx_port_dummy_op_void,
3530 .map_reset_reason = efx_mcdi_map_reset_reason,
3531 .map_reset_flags = efx_ef10_map_reset_flags,
3532 .reset = efx_mcdi_reset,
3533 .probe_port = efx_mcdi_port_probe,
3534 .remove_port = efx_mcdi_port_remove,
3535 .fini_dmaq = efx_ef10_fini_dmaq,
3536 .describe_stats = efx_ef10_describe_stats,
3537 .update_stats = efx_ef10_update_stats,
3538 .start_stats = efx_mcdi_mac_start_stats,
f8f3b5ae 3539 .pull_stats = efx_mcdi_mac_pull_stats,
8127d661
BH		 3540 .stop_stats = efx_mcdi_mac_stop_stats,
3541 .set_id_led = efx_mcdi_set_id_led,
3542 .push_irq_moderation = efx_ef10_push_irq_moderation,
3543 .reconfigure_mac = efx_ef10_mac_reconfigure,
3544 .check_mac_fault = efx_mcdi_mac_check_fault,
3545 .reconfigure_port = efx_mcdi_port_reconfigure,
3546 .get_wol = efx_ef10_get_wol,
3547 .set_wol = efx_ef10_set_wol,
3548 .resume_wol = efx_port_dummy_op_void,
74cd60a4 3549 .test_chip = efx_ef10_test_chip,
8127d661
BH		 3550 .test_nvram = efx_mcdi_nvram_test_all,
3551 .mcdi_request = efx_ef10_mcdi_request,
3552 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
3553 .mcdi_read_response = efx_ef10_mcdi_read_response,
3554 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
3555 .irq_enable_master = efx_port_dummy_op_void,
3556 .irq_test_generate = efx_ef10_irq_test_generate,
3557 .irq_disable_non_ev = efx_port_dummy_op_void,
3558 .irq_handle_msi = efx_ef10_msi_interrupt,
3559 .irq_handle_legacy = efx_ef10_legacy_interrupt,
3560 .tx_probe = efx_ef10_tx_probe,
3561 .tx_init = efx_ef10_tx_init,
3562 .tx_remove = efx_ef10_tx_remove,
3563 .tx_write = efx_ef10_tx_write,
3564 .rx_push_indir_table = efx_ef10_rx_push_indir_table,
3565 .rx_probe = efx_ef10_rx_probe,
3566 .rx_init = efx_ef10_rx_init,
3567 .rx_remove = efx_ef10_rx_remove,
3568 .rx_write = efx_ef10_rx_write,
3569 .rx_defer_refill = efx_ef10_rx_defer_refill,
3570 .ev_probe = efx_ef10_ev_probe,
3571 .ev_init = efx_ef10_ev_init,
3572 .ev_fini = efx_ef10_ev_fini,
3573 .ev_remove = efx_ef10_ev_remove,
3574 .ev_process = efx_ef10_ev_process,
3575 .ev_read_ack = efx_ef10_ev_read_ack,
3576 .ev_test_generate = efx_ef10_ev_test_generate,
3577 .filter_table_probe = efx_ef10_filter_table_probe,
3578 .filter_table_restore = efx_ef10_filter_table_restore,
3579 .filter_table_remove = efx_ef10_filter_table_remove,
3580 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
3581 .filter_insert = efx_ef10_filter_insert,
3582 .filter_remove_safe = efx_ef10_filter_remove_safe,
3583 .filter_get_safe = efx_ef10_filter_get_safe,
3584 .filter_clear_rx = efx_ef10_filter_clear_rx,
3585 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
3586 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
3587 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
3588#ifdef CONFIG_RFS_ACCEL
3589 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
3590 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
3591#endif
3592#ifdef CONFIG_SFC_MTD
3593 .mtd_probe = efx_ef10_mtd_probe,
3594 .mtd_rename = efx_mcdi_mtd_rename,
3595 .mtd_read = efx_mcdi_mtd_read,
3596 .mtd_erase = efx_mcdi_mtd_erase,
3597 .mtd_write = efx_mcdi_mtd_write,
3598 .mtd_sync = efx_mcdi_mtd_sync,
3599#endif
3600 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
bd9a265d
JC		 3601 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
3602 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
8127d661
BH		 3603
3604 .revision = EFX_REV_HUNT_A0,
3605 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
3606 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
3607 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
bd9a265d 3608 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
8127d661
BH		 3609 .can_rx_scatter = true,
3610 .always_rx_scatter = true,
3611 .max_interrupt_mode = EFX_INT_MODE_MSIX,
3612 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
3613 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3614 NETIF_F_RXHASH | NETIF_F_NTUPLE),
3615 .mcdi_max_ver = 2,
3616 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
bd9a265d
JC		 3617 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
3618 1 << HWTSTAMP_FILTER_ALL,
8127d661 3619};
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