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Merge branch 'sched-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6-block.git] / drivers / net / ethernet / samsung / sxgbe / sxgbe_common.h
CommitLineData
1edb9ca6
SR		 1/* 10G controller driver for Samsung SoCs
2 *
3 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Author: Siva Reddy Kallam <siva.kallam@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __SXGBE_COMMON_H__
14#define __SXGBE_COMMON_H__
15
16/* forward references */
17struct sxgbe_desc_ops;
18struct sxgbe_dma_ops;
19struct sxgbe_mtl_ops;
20
21#define SXGBE_RESOURCE_NAME "sam_sxgbeeth"
22#define DRV_MODULE_VERSION "November_2013"
23
24/* MAX HW feature words */
25#define SXGBE_HW_WORDS 3
26
27#define SXGBE_RX_COE_NONE 0
28
29/* CSR Frequency Access Defines*/
30#define SXGBE_CSR_F_150M 150000000
31#define SXGBE_CSR_F_250M 250000000
32#define SXGBE_CSR_F_300M 300000000
33#define SXGBE_CSR_F_350M 350000000
34#define SXGBE_CSR_F_400M 400000000
35#define SXGBE_CSR_F_500M 500000000
36
37/* pause time */
38#define SXGBE_PAUSE_TIME 0x200
39
40/* tx queues */
41#define SXGBE_TX_QUEUES 8
42#define SXGBE_RX_QUEUES 16
43
44/* Calculated based how much time does it take to fill 256KB Rx memory
45 * at 10Gb speed at 156MHz clock rate and considered little less then
46 * the actual value.
47 */
48#define SXGBE_MAX_DMA_RIWT 0x70
49#define SXGBE_MIN_DMA_RIWT 0x01
50
51/* Tx coalesce parameters */
52#define SXGBE_COAL_TX_TIMER 40000
53#define SXGBE_MAX_COAL_TX_TICK 100000
54#define SXGBE_TX_MAX_FRAMES 512
55#define SXGBE_TX_FRAMES 128
56
57/* SXGBE TX FIFO is 8K, Rx FIFO is 16K */
58#define BUF_SIZE_16KiB 16384
59#define BUF_SIZE_8KiB 8192
60#define BUF_SIZE_4KiB 4096
61#define BUF_SIZE_2KiB 2048
62
63#define SXGBE_DEFAULT_LIT_LS 0x3E8
64#define SXGBE_DEFAULT_TWT_LS 0x0
65
66/* Flow Control defines */
67#define SXGBE_FLOW_OFF 0
68#define SXGBE_FLOW_RX 1
69#define SXGBE_FLOW_TX 2
70#define SXGBE_FLOW_AUTO (SXGBE_FLOW_TX | SXGBE_FLOW_RX)
71
72#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
73
74/* errors */
75#define RX_GMII_ERR 0x01
76#define RX_WATCHDOG_ERR 0x02
77#define RX_CRC_ERR 0x03
78#define RX_GAINT_ERR 0x04
79#define RX_IP_HDR_ERR 0x05
80#define RX_PAYLOAD_ERR 0x06
81#define RX_OVERFLOW_ERR 0x07
82
83/* pkt type */
84#define RX_LEN_PKT 0x00
85#define RX_MACCTL_PKT 0x01
86#define RX_DCBCTL_PKT 0x02
87#define RX_ARP_PKT 0x03
88#define RX_OAM_PKT 0x04
89#define RX_UNTAG_PKT 0x05
90#define RX_OTHER_PKT 0x07
91#define RX_SVLAN_PKT 0x08
92#define RX_CVLAN_PKT 0x09
93#define RX_DVLAN_OCVLAN_ICVLAN_PKT 0x0A
94#define RX_DVLAN_OSVLAN_ISVLAN_PKT 0x0B
95#define RX_DVLAN_OSVLAN_ICVLAN_PKT 0x0C
96#define RX_DVLAN_OCVLAN_ISVLAN_PKT 0x0D
97
98#define RX_NOT_IP_PKT 0x00
99#define RX_IPV4_TCP_PKT 0x01
100#define RX_IPV4_UDP_PKT 0x02
101#define RX_IPV4_ICMP_PKT 0x03
102#define RX_IPV4_UNKNOWN_PKT 0x07
103#define RX_IPV6_TCP_PKT 0x09
104#define RX_IPV6_UDP_PKT 0x0A
105#define RX_IPV6_ICMP_PKT 0x0B
106#define RX_IPV6_UNKNOWN_PKT 0x0F
107
108#define RX_NO_PTP 0x00
109#define RX_PTP_SYNC 0x01
110#define RX_PTP_FOLLOW_UP 0x02
111#define RX_PTP_DELAY_REQ 0x03
112#define RX_PTP_DELAY_RESP 0x04
113#define RX_PTP_PDELAY_REQ 0x05
114#define RX_PTP_PDELAY_RESP 0x06
115#define RX_PTP_PDELAY_FOLLOW_UP 0x07
116#define RX_PTP_ANNOUNCE 0x08
117#define RX_PTP_MGMT 0x09
118#define RX_PTP_SIGNAL 0x0A
119#define RX_PTP_RESV_MSG 0x0F
120
acc18c14
G		 121/* EEE-LPI mode flags*/
122#define TX_ENTRY_LPI_MODE 0x10
123#define TX_EXIT_LPI_MODE 0x20
124#define RX_ENTRY_LPI_MODE 0x40
125#define RX_EXIT_LPI_MODE 0x80
126
127/* EEE-LPI Interrupt status flag */
128#define LPI_INT_STATUS BIT(5)
129
130/* EEE-LPI Default timer values */
131#define LPI_LINK_STATUS_TIMER 0x3E8
132#define LPI_MAC_WAIT_TIMER 0x00
133
134/* EEE-LPI Control and status definitions */
135#define LPI_CTRL_STATUS_TXA BIT(19)
136#define LPI_CTRL_STATUS_PLSDIS BIT(18)
137#define LPI_CTRL_STATUS_PLS BIT(17)
138#define LPI_CTRL_STATUS_LPIEN BIT(16)
139#define LPI_CTRL_STATUS_TXRSTP BIT(11)
140#define LPI_CTRL_STATUS_RXRSTP BIT(10)
141#define LPI_CTRL_STATUS_RLPIST BIT(9)
142#define LPI_CTRL_STATUS_TLPIST BIT(8)
143#define LPI_CTRL_STATUS_RLPIEX BIT(3)
144#define LPI_CTRL_STATUS_RLPIEN BIT(2)
145#define LPI_CTRL_STATUS_TLPIEX BIT(1)
146#define LPI_CTRL_STATUS_TLPIEN BIT(0)
147
1edb9ca6
SR		 148enum dma_irq_status {
149 tx_hard_error = BIT(0),
150 tx_bump_tc = BIT(1),
151 handle_tx = BIT(2),
152 rx_hard_error = BIT(3),
153 rx_bump_tc = BIT(4),
154 handle_rx = BIT(5),
155};
156
157#define NETIF_F_HW_VLAN_ALL (NETIF_F_HW_VLAN_CTAG_RX | \
158 NETIF_F_HW_VLAN_STAG_RX | \
159 NETIF_F_HW_VLAN_CTAG_TX | \
160 NETIF_F_HW_VLAN_STAG_TX | \
161 NETIF_F_HW_VLAN_CTAG_FILTER | \
162 NETIF_F_HW_VLAN_STAG_FILTER)
163
164/* MMC control defines */
165#define SXGBE_MMC_CTRL_CNT_FRZ 0x00000008
166
167/* SXGBE HW ADDR regs */
168#define SXGBE_ADDR_HIGH(reg) (((reg > 15) ? 0x00000800 : 0x00000040) + \
169 (reg * 8))
170#define SXGBE_ADDR_LOW(reg) (((reg > 15) ? 0x00000804 : 0x00000044) + \
171 (reg * 8))
172#define SXGBE_MAX_PERFECT_ADDRESSES 32 /* Maximum unicast perfect filtering */
173#define SXGBE_FRAME_FILTER 0x00000004 /* Frame Filter */
174
175/* SXGBE Frame Filter defines */
176#define SXGBE_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */
177#define SXGBE_FRAME_FILTER_HUC 0x00000002 /* Hash Unicast */
178#define SXGBE_FRAME_FILTER_HMC 0x00000004 /* Hash Multicast */
179#define SXGBE_FRAME_FILTER_DAIF 0x00000008 /* DA Inverse Filtering */
180#define SXGBE_FRAME_FILTER_PM 0x00000010 /* Pass all multicast */
181#define SXGBE_FRAME_FILTER_DBF 0x00000020 /* Disable Broadcast frames */
182#define SXGBE_FRAME_FILTER_SAIF 0x00000100 /* Inverse Filtering */
183#define SXGBE_FRAME_FILTER_SAF 0x00000200 /* Source Address Filter */
184#define SXGBE_FRAME_FILTER_HPF 0x00000400 /* Hash or perfect Filter */
185#define SXGBE_FRAME_FILTER_RA 0x80000000 /* Receive all mode */
186
187#define SXGBE_HASH_TABLE_SIZE 64
188#define SXGBE_HASH_HIGH 0x00000008 /* Multicast Hash Table High */
189#define SXGBE_HASH_LOW 0x0000000c /* Multicast Hash Table Low */
190
191#define SXGBE_HI_REG_AE 0x80000000
192
193/* Minimum and maximum MTU */
194#define MIN_MTU 68
195#define MAX_MTU 9000
196
197#define SXGBE_FOR_EACH_QUEUE(max_queues, queue_num) \
198 for (queue_num = 0; queue_num < max_queues; queue_num++)
199
25f72a74
VP		 200#define DRV_VERSION "1.0.0"
201
202#define SXGBE_MAX_RX_CHANNELS 16
203#define SXGBE_MAX_TX_CHANNELS 16
204
205#define START_MAC_REG_OFFSET 0x0000
206#define MAX_MAC_REG_OFFSET 0x0DFC
207#define START_MTL_REG_OFFSET 0x1000
208#define MAX_MTL_REG_OFFSET 0x18FC
209#define START_DMA_REG_OFFSET 0x3000
210#define MAX_DMA_REG_OFFSET 0x38FC
211
212#define REG_SPACE_SIZE 0x2000
213
1edb9ca6
SR		 214/* sxgbe statistics counters */
215struct sxgbe_extra_stats {
216 /* TX/RX IRQ events */
217 unsigned long tx_underflow_irq;
218 unsigned long tx_process_stopped_irq;
219 unsigned long tx_ctxt_desc_err;
220 unsigned long tx_threshold;
221 unsigned long rx_threshold;
222 unsigned long tx_pkt_n;
223 unsigned long rx_pkt_n;
224 unsigned long normal_irq_n;
225 unsigned long tx_normal_irq_n;
226 unsigned long rx_normal_irq_n;
227 unsigned long napi_poll;
228 unsigned long tx_clean;
229 unsigned long tx_reset_ic_bit;
230 unsigned long rx_process_stopped_irq;
231 unsigned long rx_underflow_irq;
232
233 /* Bus access errors */
234 unsigned long fatal_bus_error_irq;
235 unsigned long tx_read_transfer_err;
236 unsigned long tx_write_transfer_err;
237 unsigned long tx_desc_access_err;
238 unsigned long tx_buffer_access_err;
239 unsigned long tx_data_transfer_err;
240 unsigned long rx_read_transfer_err;
241 unsigned long rx_write_transfer_err;
242 unsigned long rx_desc_access_err;
243 unsigned long rx_buffer_access_err;
244 unsigned long rx_data_transfer_err;
245
acc18c14
G		 246 /* EEE-LPI stats */
247 unsigned long tx_lpi_entry_n;
248 unsigned long tx_lpi_exit_n;
249 unsigned long rx_lpi_entry_n;
250 unsigned long rx_lpi_exit_n;
251 unsigned long eee_wakeup_error_n;
252
1edb9ca6
SR		 253 /* RX specific */
254 /* L2 error */
255 unsigned long rx_code_gmii_err;
256 unsigned long rx_watchdog_err;
257 unsigned long rx_crc_err;
258 unsigned long rx_gaint_pkt_err;
259 unsigned long ip_hdr_err;
260 unsigned long ip_payload_err;
261 unsigned long overflow_error;
262
263 /* L2 Pkt type */
264 unsigned long len_pkt;
265 unsigned long mac_ctl_pkt;
266 unsigned long dcb_ctl_pkt;
267 unsigned long arp_pkt;
268 unsigned long oam_pkt;
269 unsigned long untag_okt;
270 unsigned long other_pkt;
271 unsigned long svlan_tag_pkt;
272 unsigned long cvlan_tag_pkt;
273 unsigned long dvlan_ocvlan_icvlan_pkt;
274 unsigned long dvlan_osvlan_isvlan_pkt;
275 unsigned long dvlan_osvlan_icvlan_pkt;
276 unsigned long dvan_ocvlan_icvlan_pkt;
277
278 /* L3/L4 Pkt type */
279 unsigned long not_ip_pkt;
280 unsigned long ip4_tcp_pkt;
281 unsigned long ip4_udp_pkt;
282 unsigned long ip4_icmp_pkt;
283 unsigned long ip4_unknown_pkt;
284 unsigned long ip6_tcp_pkt;
285 unsigned long ip6_udp_pkt;
286 unsigned long ip6_icmp_pkt;
287 unsigned long ip6_unknown_pkt;
288
289 /* Filter specific */
290 unsigned long vlan_filter_match;
291 unsigned long sa_filter_fail;
292 unsigned long da_filter_fail;
293 unsigned long hash_filter_pass;
294 unsigned long l3_filter_match;
295 unsigned long l4_filter_match;
296
297 /* RX context specific */
298 unsigned long timestamp_dropped;
299 unsigned long rx_msg_type_no_ptp;
300 unsigned long rx_ptp_type_sync;
301 unsigned long rx_ptp_type_follow_up;
302 unsigned long rx_ptp_type_delay_req;
303 unsigned long rx_ptp_type_delay_resp;
304 unsigned long rx_ptp_type_pdelay_req;
305 unsigned long rx_ptp_type_pdelay_resp;
306 unsigned long rx_ptp_type_pdelay_follow_up;
307 unsigned long rx_ptp_announce;
308 unsigned long rx_ptp_mgmt;
309 unsigned long rx_ptp_signal;
310 unsigned long rx_ptp_resv_msg_type;
311};
312
313struct mac_link {
314 int port;
315 int duplex;
316 int speed;
317};
318
319struct mii_regs {
320 unsigned int addr; /* MII Address */
321 unsigned int data; /* MII Data */
322};
323
324struct sxgbe_core_ops {
325 /* MAC core initialization */
326 void (*core_init)(void __iomem *ioaddr);
327 /* Dump MAC registers */
328 void (*dump_regs)(void __iomem *ioaddr);
329 /* Handle extra events on specific interrupts hw dependent */
330 int (*host_irq_status)(void __iomem *ioaddr,
331 struct sxgbe_extra_stats *x);
332 /* Set power management mode (e.g. magic frame) */
333 void (*pmt)(void __iomem *ioaddr, unsigned long mode);
334 /* Set/Get Unicast MAC addresses */
335 void (*set_umac_addr)(void __iomem *ioaddr, unsigned char *addr,
336 unsigned int reg_n);
337 void (*get_umac_addr)(void __iomem *ioaddr, unsigned char *addr,
338 unsigned int reg_n);
339 void (*enable_rx)(void __iomem *ioaddr, bool enable);
340 void (*enable_tx)(void __iomem *ioaddr, bool enable);
341
342 /* controller version specific operations */
343 int (*get_controller_version)(void __iomem *ioaddr);
344
345 /* If supported then get the optional core features */
346 unsigned int (*get_hw_feature)(void __iomem *ioaddr,
347 unsigned char feature_index);
348 /* adjust SXGBE speed */
349 void (*set_speed)(void __iomem *ioaddr, unsigned char speed);
acc18c14
G		 350
351 /* EEE-LPI specific operations */
352 void (*set_eee_mode)(void __iomem *ioaddr);
353 void (*reset_eee_mode)(void __iomem *ioaddr);
354 void (*set_eee_timer)(void __iomem *ioaddr, const int ls,
355 const int tw);
356 void (*set_eee_pls)(void __iomem *ioaddr, const int link);
8f7807ae
VP		 357
358 /* Enable disable checksum offload operations */
359 void (*enable_rx_csum)(void __iomem *ioaddr);
360 void (*disable_rx_csum)(void __iomem *ioaddr);
325b94f7
BA		 361 void (*enable_rxqueue)(void __iomem *ioaddr, int queue_num);
362 void (*disable_rxqueue)(void __iomem *ioaddr, int queue_num);
1edb9ca6
SR		 363};
364
365const struct sxgbe_core_ops *sxgbe_get_core_ops(void);
366
367struct sxgbe_ops {
368 const struct sxgbe_core_ops *mac;
369 const struct sxgbe_desc_ops *desc;
370 const struct sxgbe_dma_ops *dma;
371 const struct sxgbe_mtl_ops *mtl;
372 struct mii_regs mii; /* MII register Addresses */
373 struct mac_link link;
374 unsigned int ctrl_uid;
375 unsigned int ctrl_id;
376};
377
378/* SXGBE private data structures */
379struct sxgbe_tx_queue {
380 unsigned int irq_no;
381 struct sxgbe_priv_data *priv_ptr;
382 struct sxgbe_tx_norm_desc *dma_tx;
383 dma_addr_t dma_tx_phy;
384 dma_addr_t *tx_skbuff_dma;
385 struct sk_buff **tx_skbuff;
386 struct timer_list txtimer;
387 spinlock_t tx_lock; /* lock for tx queues */
388 unsigned int cur_tx;
389 unsigned int dirty_tx;
390 u32 tx_count_frames;
391 u32 tx_coal_frames;
392 u32 tx_coal_timer;
393 int hwts_tx_en;
1051125d 394 u16 prev_mss;
1edb9ca6
SR		 395 u8 queue_no;
396};
397
398struct sxgbe_rx_queue {
399 struct sxgbe_priv_data *priv_ptr;
400 struct sxgbe_rx_norm_desc *dma_rx;
401 struct sk_buff **rx_skbuff;
402 unsigned int cur_rx;
403 unsigned int dirty_rx;
404 unsigned int irq_no;
405 u32 rx_riwt;
406 dma_addr_t *rx_skbuff_dma;
407 dma_addr_t dma_rx_phy;
408 u8 queue_no;
409};
410
411/* SXGBE HW capabilities */
412struct sxgbe_hw_features {
413 /****** CAP [0] *******/
414 unsigned int pmt_remote_wake_up;
415 unsigned int pmt_magic_frame;
416 /* IEEE 1588-2008 */
417 unsigned int atime_stamp;
418
acc18c14
G		 419 unsigned int eee;
420
1edb9ca6
SR		 421 unsigned int tx_csum_offload;
422 unsigned int rx_csum_offload;
423 unsigned int multi_macaddr;
424 unsigned int tstamp_srcselect;
425 unsigned int sa_vlan_insert;
426
427 /****** CAP [1] *******/
428 unsigned int rxfifo_size;
429 unsigned int txfifo_size;
430 unsigned int atstmap_hword;
431 unsigned int dcb_enable;
432 unsigned int splithead_enable;
433 unsigned int tcpseg_offload;
434 unsigned int debug_mem;
435 unsigned int rss_enable;
436 unsigned int hash_tsize;
437 unsigned int l3l4_filer_size;
438
439 /* This value is in bytes and
440 * as mentioned in HW features
441 * of SXGBE data book
442 */
443 unsigned int rx_mtl_qsize;
444 unsigned int tx_mtl_qsize;
445
446 /****** CAP [2] *******/
447 /* TX and RX number of channels */
448 unsigned int rx_mtl_queues;
449 unsigned int tx_mtl_queues;
450 unsigned int rx_dma_channels;
451 unsigned int tx_dma_channels;
452 unsigned int pps_output_count;
453 unsigned int aux_input_count;
454};
455
456struct sxgbe_priv_data {
457 /* DMA descriptos */
458 struct sxgbe_tx_queue *txq[SXGBE_TX_QUEUES];
459 struct sxgbe_rx_queue *rxq[SXGBE_RX_QUEUES];
460 u8 cur_rx_qnum;
461
462 unsigned int dma_tx_size;
463 unsigned int dma_rx_size;
464 unsigned int dma_buf_sz;
465 u32 rx_riwt;
466
467 struct napi_struct napi;
468
469 void __iomem *ioaddr;
470 struct net_device *dev;
471 struct device *device;
472 struct sxgbe_ops *hw; /* sxgbe specific ops */
473 int no_csum_insertion;
474 int irq;
8f7807ae 475 int rxcsum_insertion;
1edb9ca6
SR		 476 spinlock_t stats_lock; /* lock for tx/rx statatics */
477
478 struct phy_device *phydev;
479 int oldlink;
480 int speed;
481 int oldduplex;
482 struct mii_bus *mii;
483 int mii_irq[PHY_MAX_ADDR];
484 u8 rx_pause;
485 u8 tx_pause;
486
487 struct sxgbe_extra_stats xstats;
488 struct sxgbe_plat_data *plat;
489 struct sxgbe_hw_features hw_cap;
490
491 u32 msg_enable;
492
493 struct clk *sxgbe_clk;
494 int clk_csr;
495 unsigned int mode;
496 unsigned int default_addend;
497
498 /* advanced time stamp support */
499 u32 adv_ts;
500 int use_riwt;
25f72a74 501 struct ptp_clock *ptp_clock;
1edb9ca6
SR		 502
503 /* tc control */
504 int tx_tc;
505 int rx_tc;
acc18c14
G		 506 /* EEE-LPI specific members */
507 struct timer_list eee_ctrl_timer;
508 bool tx_path_in_lpi_mode;
509 int lpi_irq;
510 int eee_enabled;
511 int eee_active;
512 int tx_lpi_timer;
1edb9ca6
SR		 513};
514
515/* Function prototypes */
516struct sxgbe_priv_data *sxgbe_drv_probe(struct device *device,
517 struct sxgbe_plat_data *plat_dat,
518 void __iomem *addr);
519int sxgbe_drv_remove(struct net_device *ndev);
520void sxgbe_set_ethtool_ops(struct net_device *netdev);
521int sxgbe_mdio_unregister(struct net_device *ndev);
522int sxgbe_mdio_register(struct net_device *ndev);
523int sxgbe_register_platform(void);
524void sxgbe_unregister_platform(void);
525
526#ifdef CONFIG_PM
527int sxgbe_suspend(struct net_device *ndev);
528int sxgbe_resume(struct net_device *ndev);
529int sxgbe_freeze(struct net_device *ndev);
530int sxgbe_restore(struct net_device *ndev);
531#endif /* CONFIG_PM */
532
533const struct sxgbe_mtl_ops *sxgbe_get_mtl_ops(void);
534
acc18c14
G		 535void sxgbe_disable_eee_mode(struct sxgbe_priv_data * const priv);
536bool sxgbe_eee_init(struct sxgbe_priv_data * const priv);
1edb9ca6 537#endif /* __SXGBE_COMMON_H__ */
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