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sh_eth: fix NULL pointer dereference in sh_eth_ring_format()
[linux-2.6-block.git] / drivers / net / ethernet / renesas / sh_eth.c
CommitLineData
128296fc 1/* SuperH Ethernet device driver
86a74ff2 2 *
966d6dbb 3 * Copyright (C) 2014 Renesas Electronics Corporation
f0e81fec 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
b356e978 5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
b2b14d2f 6 * Copyright (C) 2013-2016 Cogent Embedded, Inc.
702eca02 7 * Copyright (C) 2014 Codethink Limited
86a74ff2
NI		 8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
86a74ff2
NI		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 */
21
0654011d
YS		 22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
6a27cded 25#include <linux/interrupt.h>
86a74ff2
NI		 26#include <linux/dma-mapping.h>
27#include <linux/etherdevice.h>
28#include <linux/delay.h>
29#include <linux/platform_device.h>
30#include <linux/mdio-bitbang.h>
31#include <linux/netdevice.h>
b356e978
SS		 32#include <linux/of.h>
33#include <linux/of_device.h>
34#include <linux/of_irq.h>
35#include <linux/of_net.h>
86a74ff2
NI		 36#include <linux/phy.h>
37#include <linux/cache.h>
38#include <linux/io.h>
bcd5149d 39#include <linux/pm_runtime.h>
5a0e3ad6 40#include <linux/slab.h>
dc19e4e5 41#include <linux/ethtool.h>
fdb37a7f 42#include <linux/if_vlan.h>
f0e81fec 43#include <linux/clk.h>
d4fa0e35 44#include <linux/sh_eth.h>
702eca02 45#include <linux/of_mdio.h>
86a74ff2
NI		 46
47#include "sh_eth.h"
48
dc19e4e5
NI		 49#define SH_ETH_DEF_MSG_ENABLE \
50 (NETIF_MSG_LINK | \
51 NETIF_MSG_TIMER | \
52 NETIF_MSG_RX_ERR| \
53 NETIF_MSG_TX_ERR)
54
2274d375
SS		 55#define SH_ETH_OFFSET_INVALID ((u16)~0)
56
3365711d
BH		 57#define SH_ETH_OFFSET_DEFAULTS \
58 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
59
c0013f6f 60static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 61 SH_ETH_OFFSET_DEFAULTS,
62
c0013f6f
SS		 63 [EDSR] = 0x0000,
64 [EDMR] = 0x0400,
65 [EDTRR] = 0x0408,
66 [EDRRR] = 0x0410,
67 [EESR] = 0x0428,
68 [EESIPR] = 0x0430,
69 [TDLAR] = 0x0010,
70 [TDFAR] = 0x0014,
71 [TDFXR] = 0x0018,
72 [TDFFR] = 0x001c,
73 [RDLAR] = 0x0030,
74 [RDFAR] = 0x0034,
75 [RDFXR] = 0x0038,
76 [RDFFR] = 0x003c,
77 [TRSCER] = 0x0438,
78 [RMFCR] = 0x0440,
79 [TFTR] = 0x0448,
80 [FDR] = 0x0450,
81 [RMCR] = 0x0458,
82 [RPADIR] = 0x0460,
83 [FCFTR] = 0x0468,
84 [CSMR] = 0x04E4,
85
86 [ECMR] = 0x0500,
87 [ECSR] = 0x0510,
88 [ECSIPR] = 0x0518,
89 [PIR] = 0x0520,
90 [PSR] = 0x0528,
91 [PIPR] = 0x052c,
92 [RFLR] = 0x0508,
93 [APR] = 0x0554,
94 [MPR] = 0x0558,
95 [PFTCR] = 0x055c,
96 [PFRCR] = 0x0560,
97 [TPAUSER] = 0x0564,
98 [GECMR] = 0x05b0,
99 [BCULR] = 0x05b4,
100 [MAHR] = 0x05c0,
101 [MALR] = 0x05c8,
102 [TROCR] = 0x0700,
103 [CDCR] = 0x0708,
104 [LCCR] = 0x0710,
105 [CEFCR] = 0x0740,
106 [FRECR] = 0x0748,
107 [TSFRCR] = 0x0750,
108 [TLFRCR] = 0x0758,
109 [RFCR] = 0x0760,
110 [CERCR] = 0x0768,
111 [CEECR] = 0x0770,
112 [MAFCR] = 0x0778,
113 [RMII_MII] = 0x0790,
114
115 [ARSTR] = 0x0000,
116 [TSU_CTRST] = 0x0004,
117 [TSU_FWEN0] = 0x0010,
118 [TSU_FWEN1] = 0x0014,
119 [TSU_FCM] = 0x0018,
120 [TSU_BSYSL0] = 0x0020,
121 [TSU_BSYSL1] = 0x0024,
122 [TSU_PRISL0] = 0x0028,
123 [TSU_PRISL1] = 0x002c,
124 [TSU_FWSL0] = 0x0030,
125 [TSU_FWSL1] = 0x0034,
126 [TSU_FWSLC] = 0x0038,
127 [TSU_QTAG0] = 0x0040,
128 [TSU_QTAG1] = 0x0044,
129 [TSU_FWSR] = 0x0050,
130 [TSU_FWINMK] = 0x0054,
131 [TSU_ADQT0] = 0x0048,
132 [TSU_ADQT1] = 0x004c,
133 [TSU_VTAG0] = 0x0058,
134 [TSU_VTAG1] = 0x005c,
135 [TSU_ADSBSY] = 0x0060,
136 [TSU_TEN] = 0x0064,
137 [TSU_POST1] = 0x0070,
138 [TSU_POST2] = 0x0074,
139 [TSU_POST3] = 0x0078,
140 [TSU_POST4] = 0x007c,
141 [TSU_ADRH0] = 0x0100,
c0013f6f
SS		 142
143 [TXNLCR0] = 0x0080,
144 [TXALCR0] = 0x0084,
145 [RXNLCR0] = 0x0088,
146 [RXALCR0] = 0x008c,
147 [FWNLCR0] = 0x0090,
148 [FWALCR0] = 0x0094,
149 [TXNLCR1] = 0x00a0,
150 [TXALCR1] = 0x00a0,
151 [RXNLCR1] = 0x00a8,
152 [RXALCR1] = 0x00ac,
153 [FWNLCR1] = 0x00b0,
154 [FWALCR1] = 0x00b4,
155};
156
db893473 157static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 158 SH_ETH_OFFSET_DEFAULTS,
159
db893473
SH		 160 [EDSR] = 0x0000,
161 [EDMR] = 0x0400,
162 [EDTRR] = 0x0408,
163 [EDRRR] = 0x0410,
164 [EESR] = 0x0428,
165 [EESIPR] = 0x0430,
166 [TDLAR] = 0x0010,
167 [TDFAR] = 0x0014,
168 [TDFXR] = 0x0018,
169 [TDFFR] = 0x001c,
170 [RDLAR] = 0x0030,
171 [RDFAR] = 0x0034,
172 [RDFXR] = 0x0038,
173 [RDFFR] = 0x003c,
174 [TRSCER] = 0x0438,
175 [RMFCR] = 0x0440,
176 [TFTR] = 0x0448,
177 [FDR] = 0x0450,
178 [RMCR] = 0x0458,
179 [RPADIR] = 0x0460,
180 [FCFTR] = 0x0468,
181 [CSMR] = 0x04E4,
182
183 [ECMR] = 0x0500,
184 [RFLR] = 0x0508,
185 [ECSR] = 0x0510,
186 [ECSIPR] = 0x0518,
187 [PIR] = 0x0520,
188 [APR] = 0x0554,
189 [MPR] = 0x0558,
190 [PFTCR] = 0x055c,
191 [PFRCR] = 0x0560,
192 [TPAUSER] = 0x0564,
193 [MAHR] = 0x05c0,
194 [MALR] = 0x05c8,
195 [CEFCR] = 0x0740,
196 [FRECR] = 0x0748,
197 [TSFRCR] = 0x0750,
198 [TLFRCR] = 0x0758,
199 [RFCR] = 0x0760,
200 [MAFCR] = 0x0778,
201
202 [ARSTR] = 0x0000,
203 [TSU_CTRST] = 0x0004,
204 [TSU_VTAG0] = 0x0058,
205 [TSU_ADSBSY] = 0x0060,
206 [TSU_TEN] = 0x0064,
207 [TSU_ADRH0] = 0x0100,
db893473
SH		 208
209 [TXNLCR0] = 0x0080,
210 [TXALCR0] = 0x0084,
211 [RXNLCR0] = 0x0088,
212 [RXALCR0] = 0x008C,
213};
214
a3f109bd 215static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 216 SH_ETH_OFFSET_DEFAULTS,
217
a3f109bd
SS		 218 [ECMR] = 0x0300,
219 [RFLR] = 0x0308,
220 [ECSR] = 0x0310,
221 [ECSIPR] = 0x0318,
222 [PIR] = 0x0320,
223 [PSR] = 0x0328,
224 [RDMLR] = 0x0340,
225 [IPGR] = 0x0350,
226 [APR] = 0x0354,
227 [MPR] = 0x0358,
228 [RFCF] = 0x0360,
229 [TPAUSER] = 0x0364,
230 [TPAUSECR] = 0x0368,
231 [MAHR] = 0x03c0,
232 [MALR] = 0x03c8,
233 [TROCR] = 0x03d0,
234 [CDCR] = 0x03d4,
235 [LCCR] = 0x03d8,
236 [CNDCR] = 0x03dc,
237 [CEFCR] = 0x03e4,
238 [FRECR] = 0x03e8,
239 [TSFRCR] = 0x03ec,
240 [TLFRCR] = 0x03f0,
241 [RFCR] = 0x03f4,
242 [MAFCR] = 0x03f8,
243
244 [EDMR] = 0x0200,
245 [EDTRR] = 0x0208,
246 [EDRRR] = 0x0210,
247 [TDLAR] = 0x0218,
248 [RDLAR] = 0x0220,
249 [EESR] = 0x0228,
250 [EESIPR] = 0x0230,
251 [TRSCER] = 0x0238,
252 [RMFCR] = 0x0240,
253 [TFTR] = 0x0248,
254 [FDR] = 0x0250,
255 [RMCR] = 0x0258,
256 [TFUCR] = 0x0264,
257 [RFOCR] = 0x0268,
55754f19 258 [RMIIMODE] = 0x026c,
a3f109bd
SS		 259 [FCFTR] = 0x0270,
260 [TRIMD] = 0x027c,
261};
262
c0013f6f 263static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 264 SH_ETH_OFFSET_DEFAULTS,
265
c0013f6f
SS		 266 [ECMR] = 0x0100,
267 [RFLR] = 0x0108,
268 [ECSR] = 0x0110,
269 [ECSIPR] = 0x0118,
270 [PIR] = 0x0120,
271 [PSR] = 0x0128,
272 [RDMLR] = 0x0140,
273 [IPGR] = 0x0150,
274 [APR] = 0x0154,
275 [MPR] = 0x0158,
276 [TPAUSER] = 0x0164,
277 [RFCF] = 0x0160,
278 [TPAUSECR] = 0x0168,
279 [BCFRR] = 0x016c,
280 [MAHR] = 0x01c0,
281 [MALR] = 0x01c8,
282 [TROCR] = 0x01d0,
283 [CDCR] = 0x01d4,
284 [LCCR] = 0x01d8,
285 [CNDCR] = 0x01dc,
286 [CEFCR] = 0x01e4,
287 [FRECR] = 0x01e8,
288 [TSFRCR] = 0x01ec,
289 [TLFRCR] = 0x01f0,
290 [RFCR] = 0x01f4,
291 [MAFCR] = 0x01f8,
292 [RTRATE] = 0x01fc,
293
294 [EDMR] = 0x0000,
295 [EDTRR] = 0x0008,
296 [EDRRR] = 0x0010,
297 [TDLAR] = 0x0018,
298 [RDLAR] = 0x0020,
299 [EESR] = 0x0028,
300 [EESIPR] = 0x0030,
301 [TRSCER] = 0x0038,
302 [RMFCR] = 0x0040,
303 [TFTR] = 0x0048,
304 [FDR] = 0x0050,
305 [RMCR] = 0x0058,
306 [TFUCR] = 0x0064,
307 [RFOCR] = 0x0068,
308 [FCFTR] = 0x0070,
309 [RPADIR] = 0x0078,
310 [TRIMD] = 0x007c,
311 [RBWAR] = 0x00c8,
312 [RDFAR] = 0x00cc,
313 [TBRAR] = 0x00d4,
314 [TDFAR] = 0x00d8,
315};
316
317static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 318 SH_ETH_OFFSET_DEFAULTS,
319
d8b0426a
SS		 320 [EDMR] = 0x0000,
321 [EDTRR] = 0x0004,
322 [EDRRR] = 0x0008,
323 [TDLAR] = 0x000c,
324 [RDLAR] = 0x0010,
325 [EESR] = 0x0014,
326 [EESIPR] = 0x0018,
327 [TRSCER] = 0x001c,
328 [RMFCR] = 0x0020,
329 [TFTR] = 0x0024,
330 [FDR] = 0x0028,
331 [RMCR] = 0x002c,
332 [EDOCR] = 0x0030,
333 [FCFTR] = 0x0034,
334 [RPADIR] = 0x0038,
335 [TRIMD] = 0x003c,
336 [RBWAR] = 0x0040,
337 [RDFAR] = 0x0044,
338 [TBRAR] = 0x004c,
339 [TDFAR] = 0x0050,
340
c0013f6f
SS		 341 [ECMR] = 0x0160,
342 [ECSR] = 0x0164,
343 [ECSIPR] = 0x0168,
344 [PIR] = 0x016c,
345 [MAHR] = 0x0170,
346 [MALR] = 0x0174,
347 [RFLR] = 0x0178,
348 [PSR] = 0x017c,
349 [TROCR] = 0x0180,
350 [CDCR] = 0x0184,
351 [LCCR] = 0x0188,
352 [CNDCR] = 0x018c,
353 [CEFCR] = 0x0194,
354 [FRECR] = 0x0198,
355 [TSFRCR] = 0x019c,
356 [TLFRCR] = 0x01a0,
357 [RFCR] = 0x01a4,
358 [MAFCR] = 0x01a8,
359 [IPGR] = 0x01b4,
360 [APR] = 0x01b8,
361 [MPR] = 0x01bc,
362 [TPAUSER] = 0x01c4,
363 [BCFR] = 0x01cc,
364
365 [ARSTR] = 0x0000,
366 [TSU_CTRST] = 0x0004,
367 [TSU_FWEN0] = 0x0010,
368 [TSU_FWEN1] = 0x0014,
369 [TSU_FCM] = 0x0018,
370 [TSU_BSYSL0] = 0x0020,
371 [TSU_BSYSL1] = 0x0024,
372 [TSU_PRISL0] = 0x0028,
373 [TSU_PRISL1] = 0x002c,
374 [TSU_FWSL0] = 0x0030,
375 [TSU_FWSL1] = 0x0034,
376 [TSU_FWSLC] = 0x0038,
377 [TSU_QTAGM0] = 0x0040,
378 [TSU_QTAGM1] = 0x0044,
379 [TSU_ADQT0] = 0x0048,
380 [TSU_ADQT1] = 0x004c,
381 [TSU_FWSR] = 0x0050,
382 [TSU_FWINMK] = 0x0054,
383 [TSU_ADSBSY] = 0x0060,
384 [TSU_TEN] = 0x0064,
385 [TSU_POST1] = 0x0070,
386 [TSU_POST2] = 0x0074,
387 [TSU_POST3] = 0x0078,
388 [TSU_POST4] = 0x007c,
389
390 [TXNLCR0] = 0x0080,
391 [TXALCR0] = 0x0084,
392 [RXNLCR0] = 0x0088,
393 [RXALCR0] = 0x008c,
394 [FWNLCR0] = 0x0090,
395 [FWALCR0] = 0x0094,
396 [TXNLCR1] = 0x00a0,
397 [TXALCR1] = 0x00a0,
398 [RXNLCR1] = 0x00a8,
399 [RXALCR1] = 0x00ac,
400 [FWNLCR1] = 0x00b0,
401 [FWALCR1] = 0x00b4,
402
403 [TSU_ADRH0] = 0x0100,
c0013f6f
SS		 404};
405
740c7f31
BH		 406static void sh_eth_rcv_snd_disable(struct net_device *ndev);
407static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
408
2274d375
SS		 409static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
410{
411 struct sh_eth_private *mdp = netdev_priv(ndev);
412 u16 offset = mdp->reg_offset[enum_index];
413
414 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
415 return;
416
417 iowrite32(data, mdp->addr + offset);
418}
419
420static u32 sh_eth_read(struct net_device *ndev, int enum_index)
421{
422 struct sh_eth_private *mdp = netdev_priv(ndev);
423 u16 offset = mdp->reg_offset[enum_index];
424
425 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
426 return ~0U;
427
428 return ioread32(mdp->addr + offset);
429}
430
b2b14d2f
SS		 431static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
432 u32 set)
433{
434 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
435 enum_index);
436}
437
504c8ca5 438static bool sh_eth_is_gether(struct sh_eth_private *mdp)
dabdde9e 439{
504c8ca5 440 return mdp->reg_offset == sh_eth_offset_gigabit;
dabdde9e
NI		 441}
442
db893473
SH		 443static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
444{
445 return mdp->reg_offset == sh_eth_offset_fast_rz;
446}
447
8e994402 448static void sh_eth_select_mii(struct net_device *ndev)
5e7a76be
NI		 449{
450 u32 value = 0x0;
451 struct sh_eth_private *mdp = netdev_priv(ndev);
452
453 switch (mdp->phy_interface) {
454 case PHY_INTERFACE_MODE_GMII:
455 value = 0x2;
456 break;
457 case PHY_INTERFACE_MODE_MII:
458 value = 0x1;
459 break;
460 case PHY_INTERFACE_MODE_RMII:
461 value = 0x0;
462 break;
463 default:
f75f14ec
SS		 464 netdev_warn(ndev,
465 "PHY interface mode was not setup. Set to MII.\n");
5e7a76be
NI		 466 value = 0x1;
467 break;
468 }
469
470 sh_eth_write(ndev, value, RMII_MII);
471}
5e7a76be 472
8e994402 473static void sh_eth_set_duplex(struct net_device *ndev)
65ac8851
YS		 474{
475 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851 476
b2b14d2f 477 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
65ac8851
YS		 478}
479
99f84be6
GU		 480static void sh_eth_chip_reset(struct net_device *ndev)
481{
482 struct sh_eth_private *mdp = netdev_priv(ndev);
483
484 /* reset device */
485 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
486 mdelay(1);
487}
488
a0f48be3
GU		 489static void sh_eth_set_rate_gether(struct net_device *ndev)
490{
491 struct sh_eth_private *mdp = netdev_priv(ndev);
492
493 switch (mdp->speed) {
494 case 10: /* 10BASE */
495 sh_eth_write(ndev, GECMR_10, GECMR);
496 break;
497 case 100:/* 100BASE */
498 sh_eth_write(ndev, GECMR_100, GECMR);
499 break;
500 case 1000: /* 1000BASE */
501 sh_eth_write(ndev, GECMR_1000, GECMR);
502 break;
a0f48be3
GU		 503 }
504}
505
99f84be6
GU		 506#ifdef CONFIG_OF
507/* R7S72100 */
508static struct sh_eth_cpu_data r7s72100_data = {
509 .chip_reset = sh_eth_chip_reset,
510 .set_duplex = sh_eth_set_duplex,
511
512 .register_type = SH_ETH_REG_FAST_RZ,
513
514 .ecsr_value = ECSR_ICD,
515 .ecsipr_value = ECSIPR_ICDIP,
516 .eesipr_value = 0xff7f009f,
517
518 .tx_check = EESR_TC1 | EESR_FTC,
519 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
520 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
521 EESR_TDE | EESR_ECI,
522 .fdr_value = 0x0000070f,
523
524 .no_psr = 1,
525 .apr = 1,
526 .mpr = 1,
527 .tpauser = 1,
528 .hw_swap = 1,
529 .rpadir = 1,
530 .rpadir_value = 2 << 16,
531 .no_trimd = 1,
532 .no_ade = 1,
533 .hw_crc = 1,
534 .tsu = 1,
535 .shift_rd0 = 1,
536};
a0f48be3
GU		 537
538static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
539{
540 struct sh_eth_private *mdp = netdev_priv(ndev);
541
542 /* reset device */
543 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
544 mdelay(1);
545
546 sh_eth_select_mii(ndev);
547}
548
549/* R8A7740 */
550static struct sh_eth_cpu_data r8a7740_data = {
551 .chip_reset = sh_eth_chip_reset_r8a7740,
552 .set_duplex = sh_eth_set_duplex,
553 .set_rate = sh_eth_set_rate_gether,
554
555 .register_type = SH_ETH_REG_GIGABIT,
556
557 .ecsr_value = ECSR_ICD | ECSR_MPD,
558 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
559 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
560
561 .tx_check = EESR_TC1 | EESR_FTC,
562 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
563 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
564 EESR_TDE | EESR_ECI,
565 .fdr_value = 0x0000070f,
566
567 .apr = 1,
568 .mpr = 1,
569 .tpauser = 1,
570 .bculr = 1,
571 .hw_swap = 1,
572 .rpadir = 1,
573 .rpadir_value = 2 << 16,
574 .no_trimd = 1,
575 .no_ade = 1,
576 .tsu = 1,
577 .select_mii = 1,
578 .shift_rd0 = 1,
579};
99f84be6 580
04b0ed2a 581/* There is CPU dependent code */
589ebdef 582static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
65ac8851
YS		 583{
584 struct sh_eth_private *mdp = netdev_priv(ndev);
d0418bb7 585
a3f109bd
SS		 586 switch (mdp->speed) {
587 case 10: /* 10BASE */
b2b14d2f 588 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
a3f109bd
SS		 589 break;
590 case 100:/* 100BASE */
b2b14d2f 591 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
a3f109bd 592 break;
a3f109bd
SS		 593 }
594}
595
674853b2 596/* R8A7778/9 */
589ebdef 597static struct sh_eth_cpu_data r8a777x_data = {
a3f109bd 598 .set_duplex = sh_eth_set_duplex,
589ebdef 599 .set_rate = sh_eth_set_rate_r8a777x,
a3f109bd 600
a3153d8c
SS		 601 .register_type = SH_ETH_REG_FAST_RCAR,
602
a3f109bd
SS		 603 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
604 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
605 .eesipr_value = 0x01ff009f,
606
607 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 608 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
609 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
610 EESR_ECI,
d407bc02 611 .fdr_value = 0x00000f0f,
a3f109bd
SS		 612
613 .apr = 1,
614 .mpr = 1,
615 .tpauser = 1,
616 .hw_swap = 1,
617};
a3f109bd 618
94a12b15
SS		 619/* R8A7790/1 */
620static struct sh_eth_cpu_data r8a779x_data = {
e18dbf7e
SH		 621 .set_duplex = sh_eth_set_duplex,
622 .set_rate = sh_eth_set_rate_r8a777x,
623
a3153d8c
SS		 624 .register_type = SH_ETH_REG_FAST_RCAR,
625
e18dbf7e
SH		 626 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
627 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
628 .eesipr_value = 0x01ff009f,
629
630 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ba361cb3
LP		 631 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
632 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
633 EESR_ECI,
d407bc02 634 .fdr_value = 0x00000f0f,
e18dbf7e 635
01fbd3f5
GU		 636 .trscer_err_mask = DESC_I_RINT8,
637
e18dbf7e
SH		 638 .apr = 1,
639 .mpr = 1,
640 .tpauser = 1,
641 .hw_swap = 1,
642 .rmiimode = 1,
643};
c74a2248 644#endif /* CONFIG_OF */
e18dbf7e 645
9c3beaab 646static void sh_eth_set_rate_sh7724(struct net_device *ndev)
a3f109bd
SS		 647{
648 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 649
650 switch (mdp->speed) {
651 case 10: /* 10BASE */
b2b14d2f 652 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
65ac8851
YS		 653 break;
654 case 100:/* 100BASE */
b2b14d2f 655 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
65ac8851 656 break;
65ac8851
YS		 657 }
658}
659
660/* SH7724 */
9c3beaab 661static struct sh_eth_cpu_data sh7724_data = {
65ac8851 662 .set_duplex = sh_eth_set_duplex,
9c3beaab 663 .set_rate = sh_eth_set_rate_sh7724,
65ac8851 664
a3153d8c
SS		 665 .register_type = SH_ETH_REG_FAST_SH4,
666
65ac8851
YS		 667 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
668 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
a80c3de7 669 .eesipr_value = 0x01ff009f,
65ac8851
YS		 670
671 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 672 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
673 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
674 EESR_ECI,
65ac8851
YS		 675
676 .apr = 1,
677 .mpr = 1,
678 .tpauser = 1,
679 .hw_swap = 1,
503914cf
MD		 680 .rpadir = 1,
681 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 682};
5cee1d37 683
24549e2a 684static void sh_eth_set_rate_sh7757(struct net_device *ndev)
f29a3d04
YS		 685{
686 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 687
688 switch (mdp->speed) {
689 case 10: /* 10BASE */
4a55530f 690 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 691 break;
692 case 100:/* 100BASE */
4a55530f 693 sh_eth_write(ndev, 1, RTRATE);
f29a3d04 694 break;
f29a3d04
YS		 695 }
696}
697
698/* SH7757 */
24549e2a
SS		 699static struct sh_eth_cpu_data sh7757_data = {
700 .set_duplex = sh_eth_set_duplex,
701 .set_rate = sh_eth_set_rate_sh7757,
f29a3d04 702
a3153d8c
SS		 703 .register_type = SH_ETH_REG_FAST_SH4,
704
f29a3d04 705 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
f29a3d04
YS		 706
707 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 708 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
709 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
710 EESR_ECI,
f29a3d04 711
5b3dfd13 712 .irq_flags = IRQF_SHARED,
f29a3d04
YS		 713 .apr = 1,
714 .mpr = 1,
715 .tpauser = 1,
716 .hw_swap = 1,
717 .no_ade = 1,
2e98e797
YS		 718 .rpadir = 1,
719 .rpadir_value = 2 << 16,
6b4b4fea 720 .rtrate = 1,
f29a3d04 721};
65ac8851 722
e403d295 723#define SH_GIGA_ETH_BASE 0xfee00000UL
8fcd4961
YS		 724#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
725#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
726static void sh_eth_chip_reset_giga(struct net_device *ndev)
727{
728 int i;
0799c2d6 729 u32 mahr[2], malr[2];
8fcd4961
YS		 730
731 /* save MAHR and MALR */
732 for (i = 0; i < 2; i++) {
ae70644d
YS		 733 malr[i] = ioread32((void *)GIGA_MALR(i));
734 mahr[i] = ioread32((void *)GIGA_MAHR(i));
8fcd4961
YS		 735 }
736
737 /* reset device */
ae70644d 738 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
8fcd4961
YS		 739 mdelay(1);
740
741 /* restore MAHR and MALR */
742 for (i = 0; i < 2; i++) {
ae70644d
YS		 743 iowrite32(malr[i], (void *)GIGA_MALR(i));
744 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
8fcd4961
YS		 745 }
746}
747
8fcd4961
YS		 748static void sh_eth_set_rate_giga(struct net_device *ndev)
749{
750 struct sh_eth_private *mdp = netdev_priv(ndev);
751
752 switch (mdp->speed) {
753 case 10: /* 10BASE */
754 sh_eth_write(ndev, 0x00000000, GECMR);
755 break;
756 case 100:/* 100BASE */
757 sh_eth_write(ndev, 0x00000010, GECMR);
758 break;
759 case 1000: /* 1000BASE */
760 sh_eth_write(ndev, 0x00000020, GECMR);
761 break;
8fcd4961
YS		 762 }
763}
764
765/* SH7757(GETHERC) */
24549e2a 766static struct sh_eth_cpu_data sh7757_data_giga = {
8fcd4961 767 .chip_reset = sh_eth_chip_reset_giga,
04b0ed2a 768 .set_duplex = sh_eth_set_duplex,
8fcd4961
YS		 769 .set_rate = sh_eth_set_rate_giga,
770
a3153d8c
SS		 771 .register_type = SH_ETH_REG_GIGABIT,
772
8fcd4961
YS		 773 .ecsr_value = ECSR_ICD | ECSR_MPD,
774 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
775 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
776
777 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 778 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
779 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
780 EESR_TDE | EESR_ECI,
8fcd4961 781 .fdr_value = 0x0000072f,
8fcd4961 782
5b3dfd13 783 .irq_flags = IRQF_SHARED,
8fcd4961
YS		 784 .apr = 1,
785 .mpr = 1,
786 .tpauser = 1,
787 .bculr = 1,
788 .hw_swap = 1,
789 .rpadir = 1,
790 .rpadir_value = 2 << 16,
791 .no_trimd = 1,
792 .no_ade = 1,
3acbc971 793 .tsu = 1,
8fcd4961
YS		 794};
795
f5d12767
SS		 796/* SH7734 */
797static struct sh_eth_cpu_data sh7734_data = {
380af9e3
YS		 798 .chip_reset = sh_eth_chip_reset,
799 .set_duplex = sh_eth_set_duplex,
f5d12767
SS		 800 .set_rate = sh_eth_set_rate_gether,
801
a3153d8c
SS		 802 .register_type = SH_ETH_REG_GIGABIT,
803
f5d12767
SS		 804 .ecsr_value = ECSR_ICD | ECSR_MPD,
805 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
806 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
807
808 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 809 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
810 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
811 EESR_TDE | EESR_ECI,
f5d12767
SS		 812
813 .apr = 1,
814 .mpr = 1,
815 .tpauser = 1,
816 .bculr = 1,
817 .hw_swap = 1,
818 .no_trimd = 1,
819 .no_ade = 1,
820 .tsu = 1,
821 .hw_crc = 1,
822 .select_mii = 1,
823};
824
825/* SH7763 */
826static struct sh_eth_cpu_data sh7763_data = {
827 .chip_reset = sh_eth_chip_reset,
828 .set_duplex = sh_eth_set_duplex,
829 .set_rate = sh_eth_set_rate_gether,
380af9e3 830
a3153d8c
SS		 831 .register_type = SH_ETH_REG_GIGABIT,
832
380af9e3
YS		 833 .ecsr_value = ECSR_ICD | ECSR_MPD,
834 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
835 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
836
837 .tx_check = EESR_TC1 | EESR_FTC,
128296fc
SS		 838 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
839 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
380af9e3 840 EESR_ECI,
380af9e3
YS		 841
842 .apr = 1,
843 .mpr = 1,
844 .tpauser = 1,
845 .bculr = 1,
846 .hw_swap = 1,
380af9e3
YS		 847 .no_trimd = 1,
848 .no_ade = 1,
4986b996 849 .tsu = 1,
5b3dfd13 850 .irq_flags = IRQF_SHARED,
380af9e3
YS		 851};
852
c18a79ab 853static struct sh_eth_cpu_data sh7619_data = {
a3153d8c
SS		 854 .register_type = SH_ETH_REG_FAST_SH3_SH2,
855
380af9e3
YS		 856 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
857
858 .apr = 1,
859 .mpr = 1,
860 .tpauser = 1,
861 .hw_swap = 1,
862};
7bbe150d
SS		 863
864static struct sh_eth_cpu_data sh771x_data = {
a3153d8c
SS		 865 .register_type = SH_ETH_REG_FAST_SH3_SH2,
866
380af9e3 867 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
4986b996 868 .tsu = 1,
380af9e3 869};
380af9e3
YS		 870
871static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
872{
873 if (!cd->ecsr_value)
874 cd->ecsr_value = DEFAULT_ECSR_INIT;
875
876 if (!cd->ecsipr_value)
877 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
878
879 if (!cd->fcftr_value)
128296fc 880 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
380af9e3
YS		 881 DEFAULT_FIFO_F_D_RFD;
882
883 if (!cd->fdr_value)
884 cd->fdr_value = DEFAULT_FDR_INIT;
885
380af9e3
YS		 886 if (!cd->tx_check)
887 cd->tx_check = DEFAULT_TX_CHECK;
888
889 if (!cd->eesr_err_check)
890 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
b284fbe3
NI		 891
892 if (!cd->trscer_err_mask)
893 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
380af9e3
YS		 894}
895
5cee1d37
NI		 896static int sh_eth_check_reset(struct net_device *ndev)
897{
898 int ret = 0;
899 int cnt = 100;
900
901 while (cnt > 0) {
902 if (!(sh_eth_read(ndev, EDMR) & 0x3))
903 break;
904 mdelay(1);
905 cnt--;
906 }
9f8c4265 907 if (cnt <= 0) {
f75f14ec 908 netdev_err(ndev, "Device reset failed\n");
5cee1d37
NI		 909 ret = -ETIMEDOUT;
910 }
911 return ret;
380af9e3 912}
dabdde9e
NI		 913
914static int sh_eth_reset(struct net_device *ndev)
915{
916 struct sh_eth_private *mdp = netdev_priv(ndev);
917 int ret = 0;
918
db893473 919 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
dabdde9e 920 sh_eth_write(ndev, EDSR_ENALL, EDSR);
b2b14d2f 921 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
dabdde9e
NI		 922
923 ret = sh_eth_check_reset(ndev);
924 if (ret)
f738a13d 925 return ret;
dabdde9e
NI		 926
927 /* Table Init */
928 sh_eth_write(ndev, 0x0, TDLAR);
929 sh_eth_write(ndev, 0x0, TDFAR);
930 sh_eth_write(ndev, 0x0, TDFXR);
931 sh_eth_write(ndev, 0x0, TDFFR);
932 sh_eth_write(ndev, 0x0, RDLAR);
933 sh_eth_write(ndev, 0x0, RDFAR);
934 sh_eth_write(ndev, 0x0, RDFXR);
935 sh_eth_write(ndev, 0x0, RDFFR);
936
937 /* Reset HW CRC register */
938 if (mdp->cd->hw_crc)
939 sh_eth_write(ndev, 0x0, CSMR);
940
941 /* Select MII mode */
942 if (mdp->cd->select_mii)
943 sh_eth_select_mii(ndev);
944 } else {
b2b14d2f 945 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
dabdde9e 946 mdelay(3);
b2b14d2f 947 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
dabdde9e
NI		 948 }
949
dabdde9e
NI		 950 return ret;
951}
380af9e3 952
380af9e3
YS		 953static void sh_eth_set_receive_align(struct sk_buff *skb)
954{
4d6a949c 955 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
380af9e3 956
380af9e3 957 if (reserve)
4d6a949c 958 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
380af9e3 959}
380af9e3 960
128296fc 961/* Program the hardware MAC address from dev->dev_addr. */
86a74ff2
NI		 962static void update_mac_address(struct net_device *ndev)
963{
4a55530f 964 sh_eth_write(ndev,
128296fc
SS		 965 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
966 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
4a55530f 967 sh_eth_write(ndev,
128296fc 968 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 969}
970
128296fc 971/* Get MAC address from SuperH MAC address register
86a74ff2
NI		 972 *
973 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
974 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
975 * When you want use this device, you must set MAC address in bootloader.
976 *
977 */
748031f9 978static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 979{
748031f9 980 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
d458cdf7 981 memcpy(ndev->dev_addr, mac, ETH_ALEN);
748031f9 982 } else {
37742f02
SS		 983 u32 mahr = sh_eth_read(ndev, MAHR);
984 u32 malr = sh_eth_read(ndev, MALR);
985
986 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
987 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
988 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
989 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
990 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
991 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
748031f9 992 }
86a74ff2
NI		 993}
994
0799c2d6 995static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
c5ed5368 996{
db893473 997 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
c5ed5368
YS		 998 return EDTRR_TRNS_GETHER;
999 else
1000 return EDTRR_TRNS_ETHER;
1001}
1002
86a74ff2 1003struct bb_info {
ae70644d 1004 void (*set_gate)(void *addr);
86a74ff2 1005 struct mdiobb_ctrl ctrl;
ae70644d 1006 void *addr;
86a74ff2
NI		 1007};
1008
39b4b06b 1009static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
86a74ff2
NI		 1010{
1011 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
78fa3c5c 1012 u32 pir;
b3017e6a
YS		 1013
1014 if (bitbang->set_gate)
1015 bitbang->set_gate(bitbang->addr);
1016
78fa3c5c 1017 pir = ioread32(bitbang->addr);
39b4b06b 1018 if (set)
78fa3c5c 1019 pir |= mask;
86a74ff2 1020 else
78fa3c5c
SS		 1021 pir &= ~mask;
1022 iowrite32(pir, bitbang->addr);
39b4b06b
SS		 1023}
1024
1025/* Data I/O pin control */
1026static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1027{
1028 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
86a74ff2
NI		 1029}
1030
1031/* Set bit data*/
1032static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1033{
39b4b06b 1034 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
86a74ff2
NI		 1035}
1036
1037/* Get bit data*/
1038static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1039{
1040 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1041
1042 if (bitbang->set_gate)
1043 bitbang->set_gate(bitbang->addr);
1044
78fa3c5c 1045 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
86a74ff2
NI		 1046}
1047
1048/* MDC pin control */
1049static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1050{
39b4b06b 1051 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
86a74ff2
NI		 1052}
1053
1054/* mdio bus control struct */
1055static struct mdiobb_ops bb_ops = {
1056 .owner = THIS_MODULE,
1057 .set_mdc = sh_mdc_ctrl,
1058 .set_mdio_dir = sh_mmd_ctrl,
1059 .set_mdio_data = sh_set_mdio,
1060 .get_mdio_data = sh_get_mdio,
1061};
1062
86a74ff2
NI		 1063/* free skb and descriptor buffer */
1064static void sh_eth_ring_free(struct net_device *ndev)
1065{
1066 struct sh_eth_private *mdp = netdev_priv(ndev);
8e03a5e7 1067 int ringsize, i;
86a74ff2
NI		 1068
1069 /* Free Rx skb ringbuffer */
1070 if (mdp->rx_skbuff) {
179d80af
SS		 1071 for (i = 0; i < mdp->num_rx_ring; i++)
1072 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 1073 }
1074 kfree(mdp->rx_skbuff);
91c77550 1075 mdp->rx_skbuff = NULL;
86a74ff2
NI		 1076
1077 /* Free Tx skb ringbuffer */
1078 if (mdp->tx_skbuff) {
179d80af
SS		 1079 for (i = 0; i < mdp->num_tx_ring; i++)
1080 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 1081 }
1082 kfree(mdp->tx_skbuff);
91c77550 1083 mdp->tx_skbuff = NULL;
8e03a5e7
SS		 1084
1085 if (mdp->rx_ring) {
1086 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1087 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1088 mdp->rx_desc_dma);
1089 mdp->rx_ring = NULL;
1090 }
1091
1092 if (mdp->tx_ring) {
1093 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1094 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1095 mdp->tx_desc_dma);
1096 mdp->tx_ring = NULL;
1097 }
86a74ff2
NI		 1098}
1099
1100/* format skb and descriptor buffer */
1101static void sh_eth_ring_format(struct net_device *ndev)
1102{
1103 struct sh_eth_private *mdp = netdev_priv(ndev);
1104 int i;
1105 struct sk_buff *skb;
1106 struct sh_eth_rxdesc *rxdesc = NULL;
1107 struct sh_eth_txdesc *txdesc = NULL;
525b8075
YS		 1108 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1109 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
cb368595 1110 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
52b9fa36 1111 dma_addr_t dma_addr;
5cbf20c7 1112 u32 buf_len;
86a74ff2 1113
128296fc
SS		 1114 mdp->cur_rx = 0;
1115 mdp->cur_tx = 0;
1116 mdp->dirty_rx = 0;
1117 mdp->dirty_tx = 0;
86a74ff2
NI		 1118
1119 memset(mdp->rx_ring, 0, rx_ringsize);
1120
1121 /* build Rx ring buffer */
525b8075 1122 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1123 /* skb */
1124 mdp->rx_skbuff[i] = NULL;
4d6a949c 1125 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1126 if (skb == NULL)
1127 break;
380af9e3
YS		 1128 sh_eth_set_receive_align(skb);
1129
86a74ff2
NI		 1130 /* RX descriptor */
1131 rxdesc = &mdp->rx_ring[i];
ab857916 1132 /* The size of the buffer is a multiple of 32 bytes. */
5cbf20c7 1133 buf_len = ALIGN(mdp->rx_buf_sz, 32);
7cf72477 1134 rxdesc->len = cpu_to_le32(buf_len << 16);
5cbf20c7 1135 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
52b9fa36
BH		 1136 DMA_FROM_DEVICE);
1137 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1138 kfree_skb(skb);
1139 break;
1140 }
1141 mdp->rx_skbuff[i] = skb;
7cf72477
SS		 1142 rxdesc->addr = cpu_to_le32(dma_addr);
1143 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
86a74ff2 1144
b0ca2a21
NI		 1145 /* Rx descriptor address set */
1146 if (i == 0) {
4a55530f 1147 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
db893473
SH		 1148 if (sh_eth_is_gether(mdp) ||
1149 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1150 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 1151 }
86a74ff2
NI		 1152 }
1153
525b8075 1154 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
86a74ff2
NI		 1155
1156 /* Mark the last entry as wrapping the ring. */
c1b7fca6
SS		 1157 if (rxdesc)
1158 rxdesc->status |= cpu_to_le32(RD_RDLE);
86a74ff2
NI		 1159
1160 memset(mdp->tx_ring, 0, tx_ringsize);
1161
1162 /* build Tx ring buffer */
525b8075 1163 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1164 mdp->tx_skbuff[i] = NULL;
1165 txdesc = &mdp->tx_ring[i];
7cf72477
SS		 1166 txdesc->status = cpu_to_le32(TD_TFP);
1167 txdesc->len = cpu_to_le32(0);
b0ca2a21 1168 if (i == 0) {
71557a37 1169 /* Tx descriptor address set */
4a55530f 1170 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
db893473
SH		 1171 if (sh_eth_is_gether(mdp) ||
1172 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1173 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 1174 }
86a74ff2
NI		 1175 }
1176
7cf72477 1177 txdesc->status |= cpu_to_le32(TD_TDLE);
86a74ff2
NI		 1178}
1179
1180/* Get skb and descriptor buffer */
1181static int sh_eth_ring_init(struct net_device *ndev)
1182{
1183 struct sh_eth_private *mdp = netdev_priv(ndev);
91d80683 1184 int rx_ringsize, tx_ringsize;
86a74ff2 1185
128296fc 1186 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
86a74ff2
NI		 1187 * card needs room to do 8 byte alignment, +2 so we can reserve
1188 * the first 2 bytes, and +16 gets room for the status word from the
1189 * card.
1190 */
1191 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1192 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 1193 if (mdp->cd->rpadir)
1194 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 1195
1196 /* Allocate RX and TX skb rings */
2c94e856
SS		 1197 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1198 GFP_KERNEL);
91d80683
SS		 1199 if (!mdp->rx_skbuff)
1200 return -ENOMEM;
86a74ff2 1201
2c94e856
SS		 1202 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1203 GFP_KERNEL);
91d80683 1204 if (!mdp->tx_skbuff)
8e03a5e7 1205 goto ring_free;
86a74ff2
NI		 1206
1207 /* Allocate all Rx descriptors. */
525b8075 1208 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
86a74ff2 1209 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
d0320f75 1210 GFP_KERNEL);
91d80683 1211 if (!mdp->rx_ring)
8e03a5e7 1212 goto ring_free;
86a74ff2
NI		 1213
1214 mdp->dirty_rx = 0;
1215
1216 /* Allocate all Tx descriptors. */
525b8075 1217 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
86a74ff2 1218 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
d0320f75 1219 GFP_KERNEL);
91d80683 1220 if (!mdp->tx_ring)
8e03a5e7 1221 goto ring_free;
91d80683 1222 return 0;
86a74ff2 1223
8e03a5e7
SS		 1224ring_free:
1225 /* Free Rx and Tx skb ring buffer and DMA buffer */
86a74ff2
NI		 1226 sh_eth_ring_free(ndev);
1227
91d80683 1228 return -ENOMEM;
86a74ff2
NI		 1229}
1230
525b8075 1231static int sh_eth_dev_init(struct net_device *ndev, bool start)
86a74ff2
NI		 1232{
1233 int ret = 0;
1234 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1235
1236 /* Soft Reset */
5cee1d37
NI		 1237 ret = sh_eth_reset(ndev);
1238 if (ret)
f738a13d 1239 return ret;
86a74ff2 1240
55754f19
SH		 1241 if (mdp->cd->rmiimode)
1242 sh_eth_write(ndev, 0x1, RMIIMODE);
1243
b0ca2a21
NI		 1244 /* Descriptor format */
1245 sh_eth_ring_format(ndev);
380af9e3 1246 if (mdp->cd->rpadir)
4a55530f 1247 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 1248
1249 /* all sh_eth int mask */
4a55530f 1250 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 1251
10b9194f 1252#if defined(__LITTLE_ENDIAN)
380af9e3 1253 if (mdp->cd->hw_swap)
4a55530f 1254 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 1255 else
b0ca2a21 1256#endif
4a55530f 1257 sh_eth_write(ndev, 0, EDMR);
86a74ff2 1258
b0ca2a21 1259 /* FIFO size set */
4a55530f
YS		 1260 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1261 sh_eth_write(ndev, 0, TFTR);
86a74ff2 1262
530aa2d0
BD		 1263 /* Frame recv control (enable multiple-packets per rx irq) */
1264 sh_eth_write(ndev, RMCR_RNC, RMCR);
86a74ff2 1265
b284fbe3 1266 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
86a74ff2 1267
380af9e3 1268 if (mdp->cd->bculr)
4a55530f 1269 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 1270
4a55530f 1271 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 1272
380af9e3 1273 if (!mdp->cd->no_trimd)
4a55530f 1274 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 1275
b0ca2a21 1276 /* Recv frame limit set register */
fdb37a7f
YS		 1277 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1278 RFLR);
86a74ff2 1279
b2b14d2f 1280 sh_eth_modify(ndev, EESR, 0, 0);
283e38db
BH		 1281 if (start) {
1282 mdp->irq_enabled = true;
525b8075 1283 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
283e38db 1284 }
86a74ff2
NI		 1285
1286 /* PAUSE Prohibition */
bffa731f
SS		 1287 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1288 ECMR_TE | ECMR_RE, ECMR);
b0ca2a21 1289
380af9e3
YS		 1290 if (mdp->cd->set_rate)
1291 mdp->cd->set_rate(ndev);
1292
b0ca2a21 1293 /* E-MAC Status Register clear */
4a55530f 1294 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 1295
1296 /* E-MAC Interrupt Enable register */
525b8075
YS		 1297 if (start)
1298 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 1299
1300 /* Set MAC address */
1301 update_mac_address(ndev);
1302
1303 /* mask reset */
380af9e3 1304 if (mdp->cd->apr)
4a55530f 1305 sh_eth_write(ndev, APR_AP, APR);
380af9e3 1306 if (mdp->cd->mpr)
4a55530f 1307 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 1308 if (mdp->cd->tpauser)
4a55530f 1309 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 1310
525b8075
YS		 1311 if (start) {
1312 /* Setting the Rx mode will start the Rx process. */
1313 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2 1314
525b8075
YS		 1315 netif_start_queue(ndev);
1316 }
86a74ff2
NI		 1317
1318 return ret;
1319}
1320
740c7f31
BH		 1321static void sh_eth_dev_exit(struct net_device *ndev)
1322{
1323 struct sh_eth_private *mdp = netdev_priv(ndev);
1324 int i;
1325
1326 /* Deactivate all TX descriptors, so DMA should stop at next
1327 * packet boundary if it's currently running
1328 */
1329 for (i = 0; i < mdp->num_tx_ring; i++)
7cf72477 1330 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
740c7f31
BH		 1331
1332 /* Disable TX FIFO egress to MAC */
1333 sh_eth_rcv_snd_disable(ndev);
1334
1335 /* Stop RX DMA at next packet boundary */
1336 sh_eth_write(ndev, 0, EDRRR);
1337
1338 /* Aside from TX DMA, we can't tell when the hardware is
1339 * really stopped, so we need to reset to make sure.
1340 * Before doing that, wait for long enough to *probably*
1341 * finish transmitting the last packet and poll stats.
1342 */
1343 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1344 sh_eth_get_stats(ndev);
1345 sh_eth_reset(ndev);
a14c7d15
GU		 1346
1347 /* Set MAC address again */
1348 update_mac_address(ndev);
740c7f31
BH		 1349}
1350
86a74ff2
NI		 1351/* free Tx skb function */
1352static int sh_eth_txfree(struct net_device *ndev)
1353{
1354 struct sh_eth_private *mdp = netdev_priv(ndev);
1355 struct sh_eth_txdesc *txdesc;
128296fc 1356 int free_num = 0;
86a74ff2
NI		 1357 int entry = 0;
1358
1359 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
525b8075 1360 entry = mdp->dirty_tx % mdp->num_tx_ring;
86a74ff2 1361 txdesc = &mdp->tx_ring[entry];
7cf72477 1362 if (txdesc->status & cpu_to_le32(TD_TACT))
86a74ff2 1363 break;
7d7355f5 1364 /* TACT bit must be checked before all the following reads */
f32bfb9a 1365 dma_rmb();
e5fd13f4
BH		 1366 netif_info(mdp, tx_done, ndev,
1367 "tx entry %d status 0x%08x\n",
7cf72477 1368 entry, le32_to_cpu(txdesc->status));
86a74ff2
NI		 1369 /* Free the original skb. */
1370 if (mdp->tx_skbuff[entry]) {
7cf72477
SS		 1371 dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr),
1372 le32_to_cpu(txdesc->len) >> 16,
5cbf20c7 1373 DMA_TO_DEVICE);
86a74ff2
NI		 1374 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1375 mdp->tx_skbuff[entry] = NULL;
128296fc 1376 free_num++;
86a74ff2 1377 }
7cf72477 1378 txdesc->status = cpu_to_le32(TD_TFP);
525b8075 1379 if (entry >= mdp->num_tx_ring - 1)
7cf72477 1380 txdesc->status |= cpu_to_le32(TD_TDLE);
86a74ff2 1381
bb7d92e3 1382 ndev->stats.tx_packets++;
7cf72477 1383 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
86a74ff2 1384 }
128296fc 1385 return free_num;
86a74ff2
NI		 1386}
1387
1388/* Packet receive function */
3719109d 1389static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
86a74ff2
NI		 1390{
1391 struct sh_eth_private *mdp = netdev_priv(ndev);
1392 struct sh_eth_rxdesc *rxdesc;
1393
525b8075
YS		 1394 int entry = mdp->cur_rx % mdp->num_rx_ring;
1395 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
319cd520 1396 int limit;
86a74ff2
NI		 1397 struct sk_buff *skb;
1398 u16 pkt_len = 0;
380af9e3 1399 u32 desc_status;
cb368595 1400 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
52b9fa36 1401 dma_addr_t dma_addr;
5cbf20c7 1402 u32 buf_len;
86a74ff2 1403
319cd520
MK		 1404 boguscnt = min(boguscnt, *quota);
1405 limit = boguscnt;
86a74ff2 1406 rxdesc = &mdp->rx_ring[entry];
7cf72477 1407 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
7d7355f5 1408 /* RACT bit must be checked before all the following reads */
f32bfb9a 1409 dma_rmb();
7cf72477
SS		 1410 desc_status = le32_to_cpu(rxdesc->status);
1411 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
86a74ff2
NI		 1412
1413 if (--boguscnt < 0)
1414 break;
1415
e5fd13f4
BH		 1416 netif_info(mdp, rx_status, ndev,
1417 "rx entry %d status 0x%08x len %d\n",
1418 entry, desc_status, pkt_len);
1419
86a74ff2 1420 if (!(desc_status & RDFEND))
bb7d92e3 1421 ndev->stats.rx_length_errors++;
86a74ff2 1422
128296fc 1423 /* In case of almost all GETHER/ETHERs, the Receive Frame State
dd019897 1424 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
9b4a6364
BH		 1425 * bit 0. However, in case of the R8A7740 and R7S72100
1426 * the RFS bits are from bit 25 to bit 16. So, the
db893473 1427 * driver needs right shifting by 16.
dd019897 1428 */
ac8025a6
SS		 1429 if (mdp->cd->shift_rd0)
1430 desc_status >>= 16;
dd019897 1431
248be83d 1432 skb = mdp->rx_skbuff[entry];
86a74ff2
NI		 1433 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1434 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
bb7d92e3 1435 ndev->stats.rx_errors++;
86a74ff2 1436 if (desc_status & RD_RFS1)
bb7d92e3 1437 ndev->stats.rx_crc_errors++;
86a74ff2 1438 if (desc_status & RD_RFS2)
bb7d92e3 1439 ndev->stats.rx_frame_errors++;
86a74ff2 1440 if (desc_status & RD_RFS3)
bb7d92e3 1441 ndev->stats.rx_length_errors++;
86a74ff2 1442 if (desc_status & RD_RFS4)
bb7d92e3 1443 ndev->stats.rx_length_errors++;
86a74ff2 1444 if (desc_status & RD_RFS6)
bb7d92e3 1445 ndev->stats.rx_missed_errors++;
86a74ff2 1446 if (desc_status & RD_RFS10)
bb7d92e3 1447 ndev->stats.rx_over_errors++;
248be83d 1448 } else if (skb) {
7cf72477 1449 dma_addr = le32_to_cpu(rxdesc->addr);
380af9e3
YS		 1450 if (!mdp->cd->hw_swap)
1451 sh_eth_soft_swap(
1299653a 1452 phys_to_virt(ALIGN(dma_addr, 4)),
380af9e3 1453 pkt_len + 2);
86a74ff2 1454 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 1455 if (mdp->cd->rpadir)
1456 skb_reserve(skb, NET_IP_ALIGN);
1299653a 1457 dma_unmap_single(&ndev->dev, dma_addr,
ab857916 1458 ALIGN(mdp->rx_buf_sz, 32),
52b9fa36 1459 DMA_FROM_DEVICE);
86a74ff2
NI		 1460 skb_put(skb, pkt_len);
1461 skb->protocol = eth_type_trans(skb, ndev);
a8e9fd0f 1462 netif_receive_skb(skb);
bb7d92e3
ED		 1463 ndev->stats.rx_packets++;
1464 ndev->stats.rx_bytes += pkt_len;
25b77ad7
BH		 1465 if (desc_status & RD_RFS8)
1466 ndev->stats.multicast++;
86a74ff2 1467 }
525b8075 1468 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
862df497 1469 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 1470 }
1471
1472 /* Refill the Rx ring buffers. */
1473 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
525b8075 1474 entry = mdp->dirty_rx % mdp->num_rx_ring;
86a74ff2 1475 rxdesc = &mdp->rx_ring[entry];
ab857916 1476 /* The size of the buffer is 32 byte boundary. */
5cbf20c7 1477 buf_len = ALIGN(mdp->rx_buf_sz, 32);
7cf72477 1478 rxdesc->len = cpu_to_le32(buf_len << 16);
b0ca2a21 1479
86a74ff2 1480 if (mdp->rx_skbuff[entry] == NULL) {
4d6a949c 1481 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1482 if (skb == NULL)
1483 break; /* Better luck next round. */
380af9e3 1484 sh_eth_set_receive_align(skb);
52b9fa36 1485 dma_addr = dma_map_single(&ndev->dev, skb->data,
5cbf20c7 1486 buf_len, DMA_FROM_DEVICE);
52b9fa36
BH		 1487 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1488 kfree_skb(skb);
1489 break;
1490 }
1491 mdp->rx_skbuff[entry] = skb;
380af9e3 1492
bc8acf2c 1493 skb_checksum_none_assert(skb);
7cf72477 1494 rxdesc->addr = cpu_to_le32(dma_addr);
86a74ff2 1495 }
f32bfb9a 1496 dma_wmb(); /* RACT bit must be set after all the above writes */
525b8075 1497 if (entry >= mdp->num_rx_ring - 1)
86a74ff2 1498 rxdesc->status |=
7cf72477 1499 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
86a74ff2 1500 else
7cf72477 1501 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
86a74ff2
NI		 1502 }
1503
1504 /* Restart Rx engine if stopped. */
1505 /* If we don't need to check status, don't. -KDU */
79fba9f5 1506 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
a18e08bd 1507 /* fix the values for the next receiving if RDE is set */
3365711d
BH		 1508 if (intr_status & EESR_RDE &&
1509 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
128296fc
SS		 1510 u32 count = (sh_eth_read(ndev, RDFAR) -
1511 sh_eth_read(ndev, RDLAR)) >> 4;
1512
1513 mdp->cur_rx = count;
1514 mdp->dirty_rx = count;
1515 }
4a55530f 1516 sh_eth_write(ndev, EDRRR_R, EDRRR);
79fba9f5 1517 }
86a74ff2 1518
319cd520
MK		 1519 *quota -= limit - boguscnt - 1;
1520
4f809cea 1521 return *quota <= 0;
86a74ff2
NI		 1522}
1523
4a55530f 1524static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 1525{
1526 /* disable tx and rx */
b2b14d2f 1527 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
dc19e4e5
NI		 1528}
1529
4a55530f 1530static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 1531{
1532 /* enable tx and rx */
b2b14d2f 1533 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
dc19e4e5
NI		 1534}
1535
86a74ff2 1536/* error control function */
0799c2d6 1537static void sh_eth_error(struct net_device *ndev, u32 intr_status)
86a74ff2
NI		 1538{
1539 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1540 u32 felic_stat;
380af9e3
YS		 1541 u32 link_stat;
1542 u32 mask;
86a74ff2
NI		 1543
1544 if (intr_status & EESR_ECI) {
4a55530f
YS		 1545 felic_stat = sh_eth_read(ndev, ECSR);
1546 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
86a74ff2 1547 if (felic_stat & ECSR_ICD)
bb7d92e3 1548 ndev->stats.tx_carrier_errors++;
86a74ff2
NI		 1549 if (felic_stat & ECSR_LCHNG) {
1550 /* Link Changed */
4923576b 1551 if (mdp->cd->no_psr || mdp->no_ether_link) {
1e1b812b 1552 goto ignore_link;
380af9e3 1553 } else {
4a55530f 1554 link_stat = (sh_eth_read(ndev, PSR));
4923576b
YS		 1555 if (mdp->ether_link_active_low)
1556 link_stat = ~link_stat;
380af9e3 1557 }
128296fc 1558 if (!(link_stat & PHY_ST_LINK)) {
4a55530f 1559 sh_eth_rcv_snd_disable(ndev);
128296fc 1560 } else {
86a74ff2 1561 /* Link Up */
b2b14d2f 1562 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, 0);
128296fc 1563 /* clear int */
b2b14d2f
SS		 1564 sh_eth_modify(ndev, ECSR, 0, 0);
1565 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI,
1566 DMAC_M_ECI);
86a74ff2 1567 /* enable tx and rx */
4a55530f 1568 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1569 }
1570 }
1571 }
1572
1e1b812b 1573ignore_link:
86a74ff2 1574 if (intr_status & EESR_TWB) {
4eb313a7
SS		 1575 /* Unused write back interrupt */
1576 if (intr_status & EESR_TABT) { /* Transmit Abort int */
bb7d92e3 1577 ndev->stats.tx_aborted_errors++;
8d5009f6 1578 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
4eb313a7 1579 }
86a74ff2
NI		 1580 }
1581
1582 if (intr_status & EESR_RABT) {
1583 /* Receive Abort int */
1584 if (intr_status & EESR_RFRMER) {
1585 /* Receive Frame Overflow int */
bb7d92e3 1586 ndev->stats.rx_frame_errors++;
86a74ff2
NI		 1587 }
1588 }
380af9e3 1589
dc19e4e5
NI		 1590 if (intr_status & EESR_TDE) {
1591 /* Transmit Descriptor Empty int */
bb7d92e3 1592 ndev->stats.tx_fifo_errors++;
8d5009f6 1593 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
dc19e4e5
NI		 1594 }
1595
1596 if (intr_status & EESR_TFE) {
1597 /* FIFO under flow */
bb7d92e3 1598 ndev->stats.tx_fifo_errors++;
8d5009f6 1599 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1600 }
1601
1602 if (intr_status & EESR_RDE) {
1603 /* Receive Descriptor Empty int */
bb7d92e3 1604 ndev->stats.rx_over_errors++;
86a74ff2 1605 }
dc19e4e5 1606
86a74ff2
NI		 1607 if (intr_status & EESR_RFE) {
1608 /* Receive FIFO Overflow int */
bb7d92e3 1609 ndev->stats.rx_fifo_errors++;
dc19e4e5
NI		 1610 }
1611
1612 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1613 /* Address Error */
bb7d92e3 1614 ndev->stats.tx_fifo_errors++;
8d5009f6 1615 netif_err(mdp, tx_err, ndev, "Address Error\n");
86a74ff2 1616 }
380af9e3
YS		 1617
1618 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1619 if (mdp->cd->no_ade)
1620 mask &= ~EESR_ADE;
1621 if (intr_status & mask) {
86a74ff2 1622 /* Tx error */
4a55530f 1623 u32 edtrr = sh_eth_read(ndev, EDTRR);
090d560f 1624
86a74ff2 1625 /* dmesg */
da246855
SS		 1626 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1627 intr_status, mdp->cur_tx, mdp->dirty_tx,
1628 (u32)ndev->state, edtrr);
86a74ff2
NI		 1629 /* dirty buffer free */
1630 sh_eth_txfree(ndev);
1631
1632 /* SH7712 BUG */
c5ed5368 1633 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
86a74ff2 1634 /* tx dma start */
c5ed5368 1635 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
86a74ff2
NI		 1636 }
1637 /* wakeup */
1638 netif_wake_queue(ndev);
1639 }
1640}
1641
1642static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1643{
1644 struct net_device *ndev = netdev;
1645 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1646 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1647 irqreturn_t ret = IRQ_NONE;
0799c2d6 1648 u32 intr_status, intr_enable;
86a74ff2 1649
86a74ff2
NI		 1650 spin_lock(&mdp->lock);
1651
3893b273 1652 /* Get interrupt status */
4a55530f 1653 intr_status = sh_eth_read(ndev, EESR);
3893b273
SS		 1654 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1655 * enabled since it's the one that comes thru regardless of the mask,
1656 * and we need to fully handle it in sh_eth_error() in order to quench
1657 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1658 */
3719109d
SS		 1659 intr_enable = sh_eth_read(ndev, EESIPR);
1660 intr_status &= intr_enable | DMAC_M_ECI;
1661 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
0e0fde3c 1662 ret = IRQ_HANDLED;
3719109d 1663 else
283e38db
BH		 1664 goto out;
1665
1666 if (!likely(mdp->irq_enabled)) {
1667 sh_eth_write(ndev, 0, EESIPR);
1668 goto out;
1669 }
86a74ff2 1670
3719109d
SS		 1671 if (intr_status & EESR_RX_CHECK) {
1672 if (napi_schedule_prep(&mdp->napi)) {
1673 /* Mask Rx interrupts */
1674 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1675 EESIPR);
1676 __napi_schedule(&mdp->napi);
1677 } else {
da246855 1678 netdev_warn(ndev,
0799c2d6 1679 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
da246855 1680 intr_status, intr_enable);
3719109d
SS		 1681 }
1682 }
86a74ff2 1683
b0ca2a21 1684 /* Tx Check */
380af9e3 1685 if (intr_status & cd->tx_check) {
3719109d
SS		 1686 /* Clear Tx interrupts */
1687 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1688
86a74ff2
NI		 1689 sh_eth_txfree(ndev);
1690 netif_wake_queue(ndev);
1691 }
1692
3719109d
SS		 1693 if (intr_status & cd->eesr_err_check) {
1694 /* Clear error interrupts */
1695 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1696
86a74ff2 1697 sh_eth_error(ndev, intr_status);
3719109d 1698 }
86a74ff2 1699
283e38db 1700out:
86a74ff2
NI		 1701 spin_unlock(&mdp->lock);
1702
0e0fde3c 1703 return ret;
86a74ff2
NI		 1704}
1705
3719109d
SS		 1706static int sh_eth_poll(struct napi_struct *napi, int budget)
1707{
1708 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1709 napi);
1710 struct net_device *ndev = napi->dev;
1711 int quota = budget;
0799c2d6 1712 u32 intr_status;
3719109d
SS		 1713
1714 for (;;) {
1715 intr_status = sh_eth_read(ndev, EESR);
1716 if (!(intr_status & EESR_RX_CHECK))
1717 break;
1718 /* Clear Rx interrupts */
1719 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1720
1721 if (sh_eth_rx(ndev, intr_status, &quota))
1722 goto out;
1723 }
1724
1725 napi_complete(napi);
1726
1727 /* Reenable Rx interrupts */
283e38db
BH		 1728 if (mdp->irq_enabled)
1729 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
3719109d
SS		 1730out:
1731 return budget - quota;
1732}
1733
86a74ff2
NI		 1734/* PHY state control function */
1735static void sh_eth_adjust_link(struct net_device *ndev)
1736{
1737 struct sh_eth_private *mdp = netdev_priv(ndev);
1738 struct phy_device *phydev = mdp->phydev;
86a74ff2
NI		 1739 int new_state = 0;
1740
3340d2aa 1741 if (phydev->link) {
86a74ff2
NI		 1742 if (phydev->duplex != mdp->duplex) {
1743 new_state = 1;
1744 mdp->duplex = phydev->duplex;
380af9e3
YS		 1745 if (mdp->cd->set_duplex)
1746 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1747 }
1748
1749 if (phydev->speed != mdp->speed) {
1750 new_state = 1;
1751 mdp->speed = phydev->speed;
380af9e3
YS		 1752 if (mdp->cd->set_rate)
1753 mdp->cd->set_rate(ndev);
86a74ff2 1754 }
3340d2aa 1755 if (!mdp->link) {
b2b14d2f 1756 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
86a74ff2
NI		 1757 new_state = 1;
1758 mdp->link = phydev->link;
1e1b812b
SS		 1759 if (mdp->cd->no_psr || mdp->no_ether_link)
1760 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1761 }
1762 } else if (mdp->link) {
1763 new_state = 1;
3340d2aa 1764 mdp->link = 0;
86a74ff2
NI		 1765 mdp->speed = 0;
1766 mdp->duplex = -1;
1e1b812b
SS		 1767 if (mdp->cd->no_psr || mdp->no_ether_link)
1768 sh_eth_rcv_snd_disable(ndev);
86a74ff2
NI		 1769 }
1770
dc19e4e5 1771 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1772 phy_print_status(phydev);
1773}
1774
1775/* PHY init function */
1776static int sh_eth_phy_init(struct net_device *ndev)
1777{
702eca02 1778 struct device_node *np = ndev->dev.parent->of_node;
86a74ff2 1779 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1780 struct phy_device *phydev = NULL;
1781
3340d2aa 1782 mdp->link = 0;
86a74ff2
NI		 1783 mdp->speed = 0;
1784 mdp->duplex = -1;
1785
1786 /* Try connect to PHY */
702eca02
BD		 1787 if (np) {
1788 struct device_node *pn;
1789
1790 pn = of_parse_phandle(np, "phy-handle", 0);
1791 phydev = of_phy_connect(ndev, pn,
1792 sh_eth_adjust_link, 0,
1793 mdp->phy_interface);
1794
1795 if (!phydev)
1796 phydev = ERR_PTR(-ENOENT);
1797 } else {
1798 char phy_id[MII_BUS_ID_SIZE + 3];
1799
1800 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1801 mdp->mii_bus->id, mdp->phy_id);
1802
1803 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1804 mdp->phy_interface);
1805 }
1806
86a74ff2 1807 if (IS_ERR(phydev)) {
da246855 1808 netdev_err(ndev, "failed to connect PHY\n");
86a74ff2
NI		 1809 return PTR_ERR(phydev);
1810 }
380af9e3 1811
2220943a 1812 phy_attached_info(phydev);
86a74ff2
NI		 1813
1814 mdp->phydev = phydev;
1815
1816 return 0;
1817}
1818
1819/* PHY control start function */
1820static int sh_eth_phy_start(struct net_device *ndev)
1821{
1822 struct sh_eth_private *mdp = netdev_priv(ndev);
1823 int ret;
1824
1825 ret = sh_eth_phy_init(ndev);
1826 if (ret)
1827 return ret;
1828
86a74ff2
NI		 1829 phy_start(mdp->phydev);
1830
1831 return 0;
1832}
1833
dc19e4e5 1834static int sh_eth_get_settings(struct net_device *ndev,
128296fc 1835 struct ethtool_cmd *ecmd)
dc19e4e5
NI		 1836{
1837 struct sh_eth_private *mdp = netdev_priv(ndev);
1838 unsigned long flags;
1839 int ret;
1840
4f9dce23
BH		 1841 if (!mdp->phydev)
1842 return -ENODEV;
1843
dc19e4e5
NI		 1844 spin_lock_irqsave(&mdp->lock, flags);
1845 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1846 spin_unlock_irqrestore(&mdp->lock, flags);
1847
1848 return ret;
1849}
1850
1851static int sh_eth_set_settings(struct net_device *ndev,
128296fc 1852 struct ethtool_cmd *ecmd)
dc19e4e5
NI		 1853{
1854 struct sh_eth_private *mdp = netdev_priv(ndev);
1855 unsigned long flags;
1856 int ret;
dc19e4e5 1857
4f9dce23
BH		 1858 if (!mdp->phydev)
1859 return -ENODEV;
1860
dc19e4e5
NI		 1861 spin_lock_irqsave(&mdp->lock, flags);
1862
1863 /* disable tx and rx */
4a55530f 1864 sh_eth_rcv_snd_disable(ndev);
dc19e4e5
NI		 1865
1866 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1867 if (ret)
1868 goto error_exit;
1869
1870 if (ecmd->duplex == DUPLEX_FULL)
1871 mdp->duplex = 1;
1872 else
1873 mdp->duplex = 0;
1874
1875 if (mdp->cd->set_duplex)
1876 mdp->cd->set_duplex(ndev);
1877
1878error_exit:
1879 mdelay(1);
1880
1881 /* enable tx and rx */
4a55530f 1882 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 1883
1884 spin_unlock_irqrestore(&mdp->lock, flags);
1885
1886 return ret;
1887}
1888
6b4b4fea
BH		 1889/* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1890 * version must be bumped as well. Just adding registers up to that
1891 * limit is fine, as long as the existing register indices don't
1892 * change.
1893 */
1894#define SH_ETH_REG_DUMP_VERSION 1
1895#define SH_ETH_REG_DUMP_MAX_REGS 256
1896
1897static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1898{
1899 struct sh_eth_private *mdp = netdev_priv(ndev);
1900 struct sh_eth_cpu_data *cd = mdp->cd;
1901 u32 *valid_map;
1902 size_t len;
1903
1904 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1905
1906 /* Dump starts with a bitmap that tells ethtool which
1907 * registers are defined for this chip.
1908 */
1909 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1910 if (buf) {
1911 valid_map = buf;
1912 buf += len;
1913 } else {
1914 valid_map = NULL;
1915 }
1916
1917 /* Add a register to the dump, if it has a defined offset.
1918 * This automatically skips most undefined registers, but for
1919 * some it is also necessary to check a capability flag in
1920 * struct sh_eth_cpu_data.
1921 */
1922#define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1923#define add_reg_from(reg, read_expr) do { \
1924 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
1925 if (buf) { \
1926 mark_reg_valid(reg); \
1927 *buf++ = read_expr; \
1928 } \
1929 ++len; \
1930 } \
1931 } while (0)
1932#define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1933#define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
1934
1935 add_reg(EDSR);
1936 add_reg(EDMR);
1937 add_reg(EDTRR);
1938 add_reg(EDRRR);
1939 add_reg(EESR);
1940 add_reg(EESIPR);
1941 add_reg(TDLAR);
1942 add_reg(TDFAR);
1943 add_reg(TDFXR);
1944 add_reg(TDFFR);
1945 add_reg(RDLAR);
1946 add_reg(RDFAR);
1947 add_reg(RDFXR);
1948 add_reg(RDFFR);
1949 add_reg(TRSCER);
1950 add_reg(RMFCR);
1951 add_reg(TFTR);
1952 add_reg(FDR);
1953 add_reg(RMCR);
1954 add_reg(TFUCR);
1955 add_reg(RFOCR);
1956 if (cd->rmiimode)
1957 add_reg(RMIIMODE);
1958 add_reg(FCFTR);
1959 if (cd->rpadir)
1960 add_reg(RPADIR);
1961 if (!cd->no_trimd)
1962 add_reg(TRIMD);
1963 add_reg(ECMR);
1964 add_reg(ECSR);
1965 add_reg(ECSIPR);
1966 add_reg(PIR);
1967 if (!cd->no_psr)
1968 add_reg(PSR);
1969 add_reg(RDMLR);
1970 add_reg(RFLR);
1971 add_reg(IPGR);
1972 if (cd->apr)
1973 add_reg(APR);
1974 if (cd->mpr)
1975 add_reg(MPR);
1976 add_reg(RFCR);
1977 add_reg(RFCF);
1978 if (cd->tpauser)
1979 add_reg(TPAUSER);
1980 add_reg(TPAUSECR);
1981 add_reg(GECMR);
1982 if (cd->bculr)
1983 add_reg(BCULR);
1984 add_reg(MAHR);
1985 add_reg(MALR);
1986 add_reg(TROCR);
1987 add_reg(CDCR);
1988 add_reg(LCCR);
1989 add_reg(CNDCR);
1990 add_reg(CEFCR);
1991 add_reg(FRECR);
1992 add_reg(TSFRCR);
1993 add_reg(TLFRCR);
1994 add_reg(CERCR);
1995 add_reg(CEECR);
1996 add_reg(MAFCR);
1997 if (cd->rtrate)
1998 add_reg(RTRATE);
1999 if (cd->hw_crc)
2000 add_reg(CSMR);
2001 if (cd->select_mii)
2002 add_reg(RMII_MII);
2003 add_reg(ARSTR);
2004 if (cd->tsu) {
2005 add_tsu_reg(TSU_CTRST);
2006 add_tsu_reg(TSU_FWEN0);
2007 add_tsu_reg(TSU_FWEN1);
2008 add_tsu_reg(TSU_FCM);
2009 add_tsu_reg(TSU_BSYSL0);
2010 add_tsu_reg(TSU_BSYSL1);
2011 add_tsu_reg(TSU_PRISL0);
2012 add_tsu_reg(TSU_PRISL1);
2013 add_tsu_reg(TSU_FWSL0);
2014 add_tsu_reg(TSU_FWSL1);
2015 add_tsu_reg(TSU_FWSLC);
2016 add_tsu_reg(TSU_QTAG0);
2017 add_tsu_reg(TSU_QTAG1);
2018 add_tsu_reg(TSU_QTAGM0);
2019 add_tsu_reg(TSU_QTAGM1);
2020 add_tsu_reg(TSU_FWSR);
2021 add_tsu_reg(TSU_FWINMK);
2022 add_tsu_reg(TSU_ADQT0);
2023 add_tsu_reg(TSU_ADQT1);
2024 add_tsu_reg(TSU_VTAG0);
2025 add_tsu_reg(TSU_VTAG1);
2026 add_tsu_reg(TSU_ADSBSY);
2027 add_tsu_reg(TSU_TEN);
2028 add_tsu_reg(TSU_POST1);
2029 add_tsu_reg(TSU_POST2);
2030 add_tsu_reg(TSU_POST3);
2031 add_tsu_reg(TSU_POST4);
2032 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2033 /* This is the start of a table, not just a single
2034 * register.
2035 */
2036 if (buf) {
2037 unsigned int i;
2038
2039 mark_reg_valid(TSU_ADRH0);
2040 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2041 *buf++ = ioread32(
2042 mdp->tsu_addr +
2043 mdp->reg_offset[TSU_ADRH0] +
2044 i * 4);
2045 }
2046 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2047 }
2048 }
2049
2050#undef mark_reg_valid
2051#undef add_reg_from
2052#undef add_reg
2053#undef add_tsu_reg
2054
2055 return len * 4;
2056}
2057
2058static int sh_eth_get_regs_len(struct net_device *ndev)
2059{
2060 return __sh_eth_get_regs(ndev, NULL);
2061}
2062
2063static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2064 void *buf)
2065{
2066 struct sh_eth_private *mdp = netdev_priv(ndev);
2067
2068 regs->version = SH_ETH_REG_DUMP_VERSION;
2069
2070 pm_runtime_get_sync(&mdp->pdev->dev);
2071 __sh_eth_get_regs(ndev, buf);
2072 pm_runtime_put_sync(&mdp->pdev->dev);
2073}
2074
dc19e4e5
NI		 2075static int sh_eth_nway_reset(struct net_device *ndev)
2076{
2077 struct sh_eth_private *mdp = netdev_priv(ndev);
2078 unsigned long flags;
2079 int ret;
2080
4f9dce23
BH		 2081 if (!mdp->phydev)
2082 return -ENODEV;
2083
dc19e4e5
NI		 2084 spin_lock_irqsave(&mdp->lock, flags);
2085 ret = phy_start_aneg(mdp->phydev);
2086 spin_unlock_irqrestore(&mdp->lock, flags);
2087
2088 return ret;
2089}
2090
2091static u32 sh_eth_get_msglevel(struct net_device *ndev)
2092{
2093 struct sh_eth_private *mdp = netdev_priv(ndev);
2094 return mdp->msg_enable;
2095}
2096
2097static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2098{
2099 struct sh_eth_private *mdp = netdev_priv(ndev);
2100 mdp->msg_enable = value;
2101}
2102
2103static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2104 "rx_current", "tx_current",
2105 "rx_dirty", "tx_dirty",
2106};
2107#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2108
2109static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2110{
2111 switch (sset) {
2112 case ETH_SS_STATS:
2113 return SH_ETH_STATS_LEN;
2114 default:
2115 return -EOPNOTSUPP;
2116 }
2117}
2118
2119static void sh_eth_get_ethtool_stats(struct net_device *ndev,
128296fc 2120 struct ethtool_stats *stats, u64 *data)
dc19e4e5
NI		 2121{
2122 struct sh_eth_private *mdp = netdev_priv(ndev);
2123 int i = 0;
2124
2125 /* device-specific stats */
2126 data[i++] = mdp->cur_rx;
2127 data[i++] = mdp->cur_tx;
2128 data[i++] = mdp->dirty_rx;
2129 data[i++] = mdp->dirty_tx;
2130}
2131
2132static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2133{
2134 switch (stringset) {
2135 case ETH_SS_STATS:
2136 memcpy(data, *sh_eth_gstrings_stats,
128296fc 2137 sizeof(sh_eth_gstrings_stats));
dc19e4e5
NI		 2138 break;
2139 }
2140}
2141
525b8075
YS		 2142static void sh_eth_get_ringparam(struct net_device *ndev,
2143 struct ethtool_ringparam *ring)
2144{
2145 struct sh_eth_private *mdp = netdev_priv(ndev);
2146
2147 ring->rx_max_pending = RX_RING_MAX;
2148 ring->tx_max_pending = TX_RING_MAX;
2149 ring->rx_pending = mdp->num_rx_ring;
2150 ring->tx_pending = mdp->num_tx_ring;
2151}
2152
2153static int sh_eth_set_ringparam(struct net_device *ndev,
2154 struct ethtool_ringparam *ring)
2155{
2156 struct sh_eth_private *mdp = netdev_priv(ndev);
2157 int ret;
2158
2159 if (ring->tx_pending > TX_RING_MAX ||
2160 ring->rx_pending > RX_RING_MAX ||
2161 ring->tx_pending < TX_RING_MIN ||
2162 ring->rx_pending < RX_RING_MIN)
2163 return -EINVAL;
2164 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2165 return -EINVAL;
2166
2167 if (netif_running(ndev)) {
bd888916 2168 netif_device_detach(ndev);
525b8075 2169 netif_tx_disable(ndev);
283e38db
BH		 2170
2171 /* Serialise with the interrupt handler and NAPI, then
2172 * disable interrupts. We have to clear the
2173 * irq_enabled flag first to ensure that interrupts
2174 * won't be re-enabled.
2175 */
2176 mdp->irq_enabled = false;
525b8075 2177 synchronize_irq(ndev->irq);
283e38db 2178 napi_synchronize(&mdp->napi);
525b8075 2179 sh_eth_write(ndev, 0x0000, EESIPR);
525b8075 2180
740c7f31 2181 sh_eth_dev_exit(ndev);
525b8075 2182
8e03a5e7 2183 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
084236d8 2184 sh_eth_ring_free(ndev);
084236d8 2185 }
525b8075
YS		 2186
2187 /* Set new parameters */
2188 mdp->num_rx_ring = ring->rx_pending;
2189 mdp->num_tx_ring = ring->tx_pending;
2190
525b8075 2191 if (netif_running(ndev)) {
084236d8
BH		 2192 ret = sh_eth_ring_init(ndev);
2193 if (ret < 0) {
2194 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2195 __func__);
2196 return ret;
2197 }
2198 ret = sh_eth_dev_init(ndev, false);
2199 if (ret < 0) {
2200 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2201 __func__);
2202 return ret;
2203 }
2204
283e38db 2205 mdp->irq_enabled = true;
525b8075
YS		 2206 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2207 /* Setting the Rx mode will start the Rx process. */
2208 sh_eth_write(ndev, EDRRR_R, EDRRR);
bd888916 2209 netif_device_attach(ndev);
525b8075
YS		 2210 }
2211
2212 return 0;
2213}
2214
9b07be4b 2215static const struct ethtool_ops sh_eth_ethtool_ops = {
dc19e4e5
NI		 2216 .get_settings = sh_eth_get_settings,
2217 .set_settings = sh_eth_set_settings,
6b4b4fea
BH		 2218 .get_regs_len = sh_eth_get_regs_len,
2219 .get_regs = sh_eth_get_regs,
9b07be4b 2220 .nway_reset = sh_eth_nway_reset,
dc19e4e5
NI		 2221 .get_msglevel = sh_eth_get_msglevel,
2222 .set_msglevel = sh_eth_set_msglevel,
9b07be4b 2223 .get_link = ethtool_op_get_link,
dc19e4e5
NI		 2224 .get_strings = sh_eth_get_strings,
2225 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2226 .get_sset_count = sh_eth_get_sset_count,
525b8075
YS		 2227 .get_ringparam = sh_eth_get_ringparam,
2228 .set_ringparam = sh_eth_set_ringparam,
dc19e4e5
NI		 2229};
2230
86a74ff2
NI		 2231/* network device open function */
2232static int sh_eth_open(struct net_device *ndev)
2233{
2234 int ret = 0;
2235 struct sh_eth_private *mdp = netdev_priv(ndev);
2236
bcd5149d
MD		 2237 pm_runtime_get_sync(&mdp->pdev->dev);
2238
d2779e99
SS		 2239 napi_enable(&mdp->napi);
2240
a0607fd3 2241 ret = request_irq(ndev->irq, sh_eth_interrupt,
5b3dfd13 2242 mdp->cd->irq_flags, ndev->name, ndev);
86a74ff2 2243 if (ret) {
da246855 2244 netdev_err(ndev, "Can not assign IRQ number\n");
d2779e99 2245 goto out_napi_off;
86a74ff2
NI		 2246 }
2247
2248 /* Descriptor set */
2249 ret = sh_eth_ring_init(ndev);
2250 if (ret)
2251 goto out_free_irq;
2252
2253 /* device init */
525b8075 2254 ret = sh_eth_dev_init(ndev, true);
86a74ff2
NI		 2255 if (ret)
2256 goto out_free_irq;
2257
2258 /* PHY control start*/
2259 ret = sh_eth_phy_start(ndev);
2260 if (ret)
2261 goto out_free_irq;
2262
7fa2955f
MK		 2263 mdp->is_opened = 1;
2264
86a74ff2
NI		 2265 return ret;
2266
2267out_free_irq:
2268 free_irq(ndev->irq, ndev);
d2779e99
SS		 2269out_napi_off:
2270 napi_disable(&mdp->napi);
bcd5149d 2271 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 2272 return ret;
2273}
2274
2275/* Timeout function */
2276static void sh_eth_tx_timeout(struct net_device *ndev)
2277{
2278 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2279 struct sh_eth_rxdesc *rxdesc;
2280 int i;
2281
2282 netif_stop_queue(ndev);
2283
8d5009f6
SS		 2284 netif_err(mdp, timer, ndev,
2285 "transmit timed out, status %8.8x, resetting...\n",
0799c2d6 2286 sh_eth_read(ndev, EESR));
86a74ff2
NI		 2287
2288 /* tx_errors count up */
bb7d92e3 2289 ndev->stats.tx_errors++;
86a74ff2 2290
86a74ff2 2291 /* Free all the skbuffs in the Rx queue. */
525b8075 2292 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2 2293 rxdesc = &mdp->rx_ring[i];
7cf72477
SS		 2294 rxdesc->status = cpu_to_le32(0);
2295 rxdesc->addr = cpu_to_le32(0xBADF00D0);
179d80af 2296 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 2297 mdp->rx_skbuff[i] = NULL;
2298 }
525b8075 2299 for (i = 0; i < mdp->num_tx_ring; i++) {
179d80af 2300 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 2301 mdp->tx_skbuff[i] = NULL;
2302 }
2303
2304 /* device init */
525b8075 2305 sh_eth_dev_init(ndev, true);
86a74ff2
NI		 2306}
2307
2308/* Packet transmit function */
2309static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2310{
2311 struct sh_eth_private *mdp = netdev_priv(ndev);
2312 struct sh_eth_txdesc *txdesc;
1299653a 2313 dma_addr_t dma_addr;
86a74ff2 2314 u32 entry;
fb5e2f9b 2315 unsigned long flags;
86a74ff2
NI		 2316
2317 spin_lock_irqsave(&mdp->lock, flags);
525b8075 2318 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
86a74ff2 2319 if (!sh_eth_txfree(ndev)) {
8d5009f6 2320 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
86a74ff2
NI		 2321 netif_stop_queue(ndev);
2322 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 2323 return NETDEV_TX_BUSY;
86a74ff2
NI		 2324 }
2325 }
2326 spin_unlock_irqrestore(&mdp->lock, flags);
2327
dacc73e0 2328 if (skb_put_padto(skb, ETH_ZLEN))
eebfb643
BH		 2329 return NETDEV_TX_OK;
2330
525b8075 2331 entry = mdp->cur_tx % mdp->num_tx_ring;
86a74ff2
NI		 2332 mdp->tx_skbuff[entry] = skb;
2333 txdesc = &mdp->tx_ring[entry];
86a74ff2 2334 /* soft swap. */
380af9e3 2335 if (!mdp->cd->hw_swap)
3e230993 2336 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
1299653a
SS		 2337 dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2338 DMA_TO_DEVICE);
2339 if (dma_mapping_error(&ndev->dev, dma_addr)) {
aa3933b8
BH		 2340 kfree_skb(skb);
2341 return NETDEV_TX_OK;
2342 }
7cf72477
SS		 2343 txdesc->addr = cpu_to_le32(dma_addr);
2344 txdesc->len = cpu_to_le32(skb->len << 16);
86a74ff2 2345
f32bfb9a 2346 dma_wmb(); /* TACT bit must be set after all the above writes */
525b8075 2347 if (entry >= mdp->num_tx_ring - 1)
7cf72477 2348 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
86a74ff2 2349 else
7cf72477 2350 txdesc->status |= cpu_to_le32(TD_TACT);
86a74ff2
NI		 2351
2352 mdp->cur_tx++;
2353
c5ed5368
YS		 2354 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2355 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
b0ca2a21 2356
6ed10654 2357 return NETDEV_TX_OK;
86a74ff2
NI		 2358}
2359
4398f9c8
BH		 2360/* The statistics registers have write-clear behaviour, which means we
2361 * will lose any increment between the read and write. We mitigate
2362 * this by only clearing when we read a non-zero value, so we will
2363 * never falsely report a total of zero.
2364 */
2365static void
2366sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2367{
2368 u32 delta = sh_eth_read(ndev, reg);
2369
2370 if (delta) {
2371 *stat += delta;
2372 sh_eth_write(ndev, 0, reg);
2373 }
2374}
2375
7fa2955f
MK		 2376static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2377{
2378 struct sh_eth_private *mdp = netdev_priv(ndev);
2379
2380 if (sh_eth_is_rz_fast_ether(mdp))
2381 return &ndev->stats;
2382
2383 if (!mdp->is_opened)
2384 return &ndev->stats;
2385
4398f9c8
BH		 2386 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2387 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2388 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
7fa2955f
MK		 2389
2390 if (sh_eth_is_gether(mdp)) {
4398f9c8
BH		 2391 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2392 CERCR);
2393 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2394 CEECR);
7fa2955f 2395 } else {
4398f9c8
BH		 2396 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2397 CNDCR);
7fa2955f
MK		 2398 }
2399
2400 return &ndev->stats;
2401}
2402
86a74ff2
NI		 2403/* device close function */
2404static int sh_eth_close(struct net_device *ndev)
2405{
2406 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2407
2408 netif_stop_queue(ndev);
2409
283e38db
BH		 2410 /* Serialise with the interrupt handler and NAPI, then disable
2411 * interrupts. We have to clear the irq_enabled flag first to
2412 * ensure that interrupts won't be re-enabled.
2413 */
2414 mdp->irq_enabled = false;
2415 synchronize_irq(ndev->irq);
2416 napi_disable(&mdp->napi);
4a55530f 2417 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2 2418
740c7f31 2419 sh_eth_dev_exit(ndev);
86a74ff2
NI		 2420
2421 /* PHY Disconnect */
2422 if (mdp->phydev) {
2423 phy_stop(mdp->phydev);
2424 phy_disconnect(mdp->phydev);
4f9dce23 2425 mdp->phydev = NULL;
86a74ff2
NI		 2426 }
2427
2428 free_irq(ndev->irq, ndev);
2429
8e03a5e7 2430 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
86a74ff2
NI		 2431 sh_eth_ring_free(ndev);
2432
bcd5149d
MD		 2433 pm_runtime_put_sync(&mdp->pdev->dev);
2434
7fa2955f 2435 mdp->is_opened = 0;
bcd5149d 2436
7fa2955f 2437 return 0;
86a74ff2
NI		 2438}
2439
bb7d92e3 2440/* ioctl to device function */
128296fc 2441static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
86a74ff2
NI		 2442{
2443 struct sh_eth_private *mdp = netdev_priv(ndev);
2444 struct phy_device *phydev = mdp->phydev;
2445
2446 if (!netif_running(ndev))
2447 return -EINVAL;
2448
2449 if (!phydev)
2450 return -ENODEV;
2451
28b04113 2452 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 2453}
2454
6743fe6d
YS		 2455/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2456static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2457 int entry)
2458{
2459 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2460}
2461
2462static u32 sh_eth_tsu_get_post_mask(int entry)
2463{
2464 return 0x0f << (28 - ((entry % 8) * 4));
2465}
2466
2467static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2468{
2469 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2470}
2471
2472static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2473 int entry)
2474{
2475 struct sh_eth_private *mdp = netdev_priv(ndev);
2476 u32 tmp;
2477 void *reg_offset;
2478
2479 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2480 tmp = ioread32(reg_offset);
2481 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2482}
2483
2484static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2485 int entry)
2486{
2487 struct sh_eth_private *mdp = netdev_priv(ndev);
2488 u32 post_mask, ref_mask, tmp;
2489 void *reg_offset;
2490
2491 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2492 post_mask = sh_eth_tsu_get_post_mask(entry);
2493 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2494
2495 tmp = ioread32(reg_offset);
2496 iowrite32(tmp & ~post_mask, reg_offset);
2497
2498 /* If other port enables, the function returns "true" */
2499 return tmp & ref_mask;
2500}
2501
2502static int sh_eth_tsu_busy(struct net_device *ndev)
2503{
2504 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2505 struct sh_eth_private *mdp = netdev_priv(ndev);
2506
2507 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2508 udelay(10);
2509 timeout--;
2510 if (timeout <= 0) {
da246855 2511 netdev_err(ndev, "%s: timeout\n", __func__);
6743fe6d
YS		 2512 return -ETIMEDOUT;
2513 }
2514 }
2515
2516 return 0;
2517}
2518
2519static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2520 const u8 *addr)
2521{
2522 u32 val;
2523
2524 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2525 iowrite32(val, reg);
2526 if (sh_eth_tsu_busy(ndev) < 0)
2527 return -EBUSY;
2528
2529 val = addr[4] << 8 | addr[5];
2530 iowrite32(val, reg + 4);
2531 if (sh_eth_tsu_busy(ndev) < 0)
2532 return -EBUSY;
2533
2534 return 0;
2535}
2536
2537static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2538{
2539 u32 val;
2540
2541 val = ioread32(reg);
2542 addr[0] = (val >> 24) & 0xff;
2543 addr[1] = (val >> 16) & 0xff;
2544 addr[2] = (val >> 8) & 0xff;
2545 addr[3] = val & 0xff;
2546 val = ioread32(reg + 4);
2547 addr[4] = (val >> 8) & 0xff;
2548 addr[5] = val & 0xff;
2549}
2550
2551
2552static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2553{
2554 struct sh_eth_private *mdp = netdev_priv(ndev);
2555 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2556 int i;
2557 u8 c_addr[ETH_ALEN];
2558
2559 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2560 sh_eth_tsu_read_entry(reg_offset, c_addr);
c4bde29c 2561 if (ether_addr_equal(addr, c_addr))
6743fe6d
YS		 2562 return i;
2563 }
2564
2565 return -ENOENT;
2566}
2567
2568static int sh_eth_tsu_find_empty(struct net_device *ndev)
2569{
2570 u8 blank[ETH_ALEN];
2571 int entry;
2572
2573 memset(blank, 0, sizeof(blank));
2574 entry = sh_eth_tsu_find_entry(ndev, blank);
2575 return (entry < 0) ? -ENOMEM : entry;
2576}
2577
2578static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2579 int entry)
2580{
2581 struct sh_eth_private *mdp = netdev_priv(ndev);
2582 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2583 int ret;
2584 u8 blank[ETH_ALEN];
2585
2586 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2587 ~(1 << (31 - entry)), TSU_TEN);
2588
2589 memset(blank, 0, sizeof(blank));
2590 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2591 if (ret < 0)
2592 return ret;
2593 return 0;
2594}
2595
2596static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2597{
2598 struct sh_eth_private *mdp = netdev_priv(ndev);
2599 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2600 int i, ret;
2601
2602 if (!mdp->cd->tsu)
2603 return 0;
2604
2605 i = sh_eth_tsu_find_entry(ndev, addr);
2606 if (i < 0) {
2607 /* No entry found, create one */
2608 i = sh_eth_tsu_find_empty(ndev);
2609 if (i < 0)
2610 return -ENOMEM;
2611 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2612 if (ret < 0)
2613 return ret;
2614
2615 /* Enable the entry */
2616 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2617 (1 << (31 - i)), TSU_TEN);
2618 }
2619
2620 /* Entry found or created, enable POST */
2621 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2622
2623 return 0;
2624}
2625
2626static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2627{
2628 struct sh_eth_private *mdp = netdev_priv(ndev);
2629 int i, ret;
2630
2631 if (!mdp->cd->tsu)
2632 return 0;
2633
2634 i = sh_eth_tsu_find_entry(ndev, addr);
2635 if (i) {
2636 /* Entry found */
2637 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2638 goto done;
2639
2640 /* Disable the entry if both ports was disabled */
2641 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2642 if (ret < 0)
2643 return ret;
2644 }
2645done:
2646 return 0;
2647}
2648
2649static int sh_eth_tsu_purge_all(struct net_device *ndev)
2650{
2651 struct sh_eth_private *mdp = netdev_priv(ndev);
2652 int i, ret;
2653
b37feed7 2654 if (!mdp->cd->tsu)
6743fe6d
YS		 2655 return 0;
2656
2657 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2658 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2659 continue;
2660
2661 /* Disable the entry if both ports was disabled */
2662 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2663 if (ret < 0)
2664 return ret;
2665 }
2666
2667 return 0;
2668}
2669
2670static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2671{
2672 struct sh_eth_private *mdp = netdev_priv(ndev);
2673 u8 addr[ETH_ALEN];
2674 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2675 int i;
2676
b37feed7 2677 if (!mdp->cd->tsu)
6743fe6d
YS		 2678 return;
2679
2680 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2681 sh_eth_tsu_read_entry(reg_offset, addr);
2682 if (is_multicast_ether_addr(addr))
2683 sh_eth_tsu_del_entry(ndev, addr);
2684 }
2685}
2686
b37feed7
BH		 2687/* Update promiscuous flag and multicast filter */
2688static void sh_eth_set_rx_mode(struct net_device *ndev)
86a74ff2 2689{
6743fe6d
YS		 2690 struct sh_eth_private *mdp = netdev_priv(ndev);
2691 u32 ecmr_bits;
2692 int mcast_all = 0;
2693 unsigned long flags;
2694
2695 spin_lock_irqsave(&mdp->lock, flags);
128296fc 2696 /* Initial condition is MCT = 1, PRM = 0.
6743fe6d
YS		 2697 * Depending on ndev->flags, set PRM or clear MCT
2698 */
b37feed7
BH		 2699 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2700 if (mdp->cd->tsu)
2701 ecmr_bits |= ECMR_MCT;
6743fe6d
YS		 2702
2703 if (!(ndev->flags & IFF_MULTICAST)) {
2704 sh_eth_tsu_purge_mcast(ndev);
2705 mcast_all = 1;
2706 }
2707 if (ndev->flags & IFF_ALLMULTI) {
2708 sh_eth_tsu_purge_mcast(ndev);
2709 ecmr_bits &= ~ECMR_MCT;
2710 mcast_all = 1;
2711 }
2712
86a74ff2 2713 if (ndev->flags & IFF_PROMISC) {
6743fe6d
YS		 2714 sh_eth_tsu_purge_all(ndev);
2715 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2716 } else if (mdp->cd->tsu) {
2717 struct netdev_hw_addr *ha;
2718 netdev_for_each_mc_addr(ha, ndev) {
2719 if (mcast_all && is_multicast_ether_addr(ha->addr))
2720 continue;
2721
2722 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2723 if (!mcast_all) {
2724 sh_eth_tsu_purge_mcast(ndev);
2725 ecmr_bits &= ~ECMR_MCT;
2726 mcast_all = 1;
2727 }
2728 }
2729 }
86a74ff2 2730 }
6743fe6d
YS		 2731
2732 /* update the ethernet mode */
2733 sh_eth_write(ndev, ecmr_bits, ECMR);
2734
2735 spin_unlock_irqrestore(&mdp->lock, flags);
86a74ff2 2736}
71cc7c37
YS		 2737
2738static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2739{
2740 if (!mdp->port)
2741 return TSU_VTAG0;
2742 else
2743 return TSU_VTAG1;
2744}
2745
80d5c368
PM		 2746static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2747 __be16 proto, u16 vid)
71cc7c37
YS		 2748{
2749 struct sh_eth_private *mdp = netdev_priv(ndev);
2750 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2751
2752 if (unlikely(!mdp->cd->tsu))
2753 return -EPERM;
2754
2755 /* No filtering if vid = 0 */
2756 if (!vid)
2757 return 0;
2758
2759 mdp->vlan_num_ids++;
2760
128296fc 2761 /* The controller has one VLAN tag HW filter. So, if the filter is
71cc7c37
YS		 2762 * already enabled, the driver disables it and the filte
2763 */
2764 if (mdp->vlan_num_ids > 1) {
2765 /* disable VLAN filter */
2766 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2767 return 0;
2768 }
2769
2770 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2771 vtag_reg_index);
2772
2773 return 0;
2774}
2775
80d5c368
PM		 2776static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2777 __be16 proto, u16 vid)
71cc7c37
YS		 2778{
2779 struct sh_eth_private *mdp = netdev_priv(ndev);
2780 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2781
2782 if (unlikely(!mdp->cd->tsu))
2783 return -EPERM;
2784
2785 /* No filtering if vid = 0 */
2786 if (!vid)
2787 return 0;
2788
2789 mdp->vlan_num_ids--;
2790 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2791
2792 return 0;
2793}
86a74ff2
NI		 2794
2795/* SuperH's TSU register init function */
4a55530f 2796static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 2797{
db893473
SH		 2798 if (sh_eth_is_rz_fast_ether(mdp)) {
2799 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2800 return;
2801 }
2802
4a55530f
YS		 2803 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2804 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2805 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2806 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2807 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2808 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2809 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2810 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2811 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2812 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
c5ed5368
YS		 2813 if (sh_eth_is_gether(mdp)) {
2814 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2815 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2816 } else {
2817 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2818 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2819 }
4a55530f
YS		 2820 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2821 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2822 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2823 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2824 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2825 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2826 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 2827}
2828
2829/* MDIO bus release function */
bd920ff5 2830static int sh_mdio_release(struct sh_eth_private *mdp)
86a74ff2 2831{
86a74ff2 2832 /* unregister mdio bus */
bd920ff5 2833 mdiobus_unregister(mdp->mii_bus);
86a74ff2
NI		 2834
2835 /* free bitbang info */
bd920ff5 2836 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2837
2838 return 0;
2839}
2840
2841/* MDIO bus init function */
bd920ff5 2842static int sh_mdio_init(struct sh_eth_private *mdp,
b3017e6a 2843 struct sh_eth_plat_data *pd)
86a74ff2 2844{
e7f4dc35 2845 int ret;
86a74ff2 2846 struct bb_info *bitbang;
bd920ff5 2847 struct platform_device *pdev = mdp->pdev;
aa8d4225 2848 struct device *dev = &mdp->pdev->dev;
86a74ff2
NI		 2849
2850 /* create bit control struct for PHY */
aa8d4225 2851 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
f738a13d
LP		 2852 if (!bitbang)
2853 return -ENOMEM;
86a74ff2
NI		 2854
2855 /* bitbang init */
ae70644d 2856 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
b3017e6a 2857 bitbang->set_gate = pd->set_mdio_gate;
86a74ff2
NI		 2858 bitbang->ctrl.ops = &bb_ops;
2859
c2e07b3a 2860 /* MII controller setting */
86a74ff2 2861 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
f738a13d
LP		 2862 if (!mdp->mii_bus)
2863 return -ENOMEM;
86a74ff2
NI		 2864
2865 /* Hook up MII support for ethtool */
2866 mdp->mii_bus->name = "sh_mii";
a5bd6060 2867 mdp->mii_bus->parent = dev;
5278fb54 2868 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
bd920ff5 2869 pdev->name, pdev->id);
86a74ff2 2870
bd920ff5
LP		 2871 /* register MDIO bus */
2872 if (dev->of_node) {
2873 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
702eca02 2874 } else {
702eca02
BD		 2875 if (pd->phy_irq > 0)
2876 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2877
2878 ret = mdiobus_register(mdp->mii_bus);
2879 }
2880
86a74ff2 2881 if (ret)
d5e07e69 2882 goto out_free_bus;
86a74ff2 2883
86a74ff2
NI		 2884 return 0;
2885
86a74ff2 2886out_free_bus:
298cf9be 2887 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2888 return ret;
2889}
2890
4a55530f
YS		 2891static const u16 *sh_eth_get_register_offset(int register_type)
2892{
2893 const u16 *reg_offset = NULL;
2894
2895 switch (register_type) {
2896 case SH_ETH_REG_GIGABIT:
2897 reg_offset = sh_eth_offset_gigabit;
2898 break;
db893473
SH		 2899 case SH_ETH_REG_FAST_RZ:
2900 reg_offset = sh_eth_offset_fast_rz;
2901 break;
a3f109bd
SS		 2902 case SH_ETH_REG_FAST_RCAR:
2903 reg_offset = sh_eth_offset_fast_rcar;
2904 break;
4a55530f
YS		 2905 case SH_ETH_REG_FAST_SH4:
2906 reg_offset = sh_eth_offset_fast_sh4;
2907 break;
2908 case SH_ETH_REG_FAST_SH3_SH2:
2909 reg_offset = sh_eth_offset_fast_sh3_sh2;
2910 break;
4a55530f
YS		 2911 }
2912
2913 return reg_offset;
2914}
2915
8f728d79 2916static const struct net_device_ops sh_eth_netdev_ops = {
ebf84eaa
AB		 2917 .ndo_open = sh_eth_open,
2918 .ndo_stop = sh_eth_close,
2919 .ndo_start_xmit = sh_eth_start_xmit,
2920 .ndo_get_stats = sh_eth_get_stats,
b37feed7 2921 .ndo_set_rx_mode = sh_eth_set_rx_mode,
ebf84eaa
AB		 2922 .ndo_tx_timeout = sh_eth_tx_timeout,
2923 .ndo_do_ioctl = sh_eth_do_ioctl,
2924 .ndo_validate_addr = eth_validate_addr,
2925 .ndo_set_mac_address = eth_mac_addr,
2926 .ndo_change_mtu = eth_change_mtu,
2927};
2928
8f728d79
SS		 2929static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2930 .ndo_open = sh_eth_open,
2931 .ndo_stop = sh_eth_close,
2932 .ndo_start_xmit = sh_eth_start_xmit,
2933 .ndo_get_stats = sh_eth_get_stats,
b37feed7 2934 .ndo_set_rx_mode = sh_eth_set_rx_mode,
8f728d79
SS		 2935 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2936 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2937 .ndo_tx_timeout = sh_eth_tx_timeout,
2938 .ndo_do_ioctl = sh_eth_do_ioctl,
2939 .ndo_validate_addr = eth_validate_addr,
2940 .ndo_set_mac_address = eth_mac_addr,
2941 .ndo_change_mtu = eth_change_mtu,
2942};
2943
b356e978
SS		 2944#ifdef CONFIG_OF
2945static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2946{
2947 struct device_node *np = dev->of_node;
2948 struct sh_eth_plat_data *pdata;
b356e978
SS		 2949 const char *mac_addr;
2950
2951 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2952 if (!pdata)
2953 return NULL;
2954
2955 pdata->phy_interface = of_get_phy_mode(np);
2956
b356e978
SS		 2957 mac_addr = of_get_mac_address(np);
2958 if (mac_addr)
2959 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2960
2961 pdata->no_ether_link =
2962 of_property_read_bool(np, "renesas,no-ether-link");
2963 pdata->ether_link_active_low =
2964 of_property_read_bool(np, "renesas,ether-link-active-low");
2965
2966 return pdata;
2967}
2968
2969static const struct of_device_id sh_eth_match_table[] = {
2970 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2971 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2972 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2973 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2974 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
9488e1e5 2975 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
0f76b9d8 2976 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
b356e978
SS		 2977 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2978 { }
2979};
2980MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2981#else
2982static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2983{
2984 return NULL;
2985}
2986#endif
2987
86a74ff2
NI		 2988static int sh_eth_drv_probe(struct platform_device *pdev)
2989{
9c38657c 2990 int ret, devno = 0;
86a74ff2
NI		 2991 struct resource *res;
2992 struct net_device *ndev = NULL;
ec0d7551 2993 struct sh_eth_private *mdp = NULL;
0b76b862 2994 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
afe391ad 2995 const struct platform_device_id *id = platform_get_device_id(pdev);
86a74ff2
NI		 2996
2997 /* get base addr */
2998 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
86a74ff2
NI		 2999
3000 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
f738a13d
LP		 3001 if (!ndev)
3002 return -ENOMEM;
86a74ff2 3003
b5893a08
BD		 3004 pm_runtime_enable(&pdev->dev);
3005 pm_runtime_get_sync(&pdev->dev);
3006
86a74ff2
NI		 3007 devno = pdev->id;
3008 if (devno < 0)
3009 devno = 0;
3010
3011 ndev->dma = -1;
cc3c080d 3012 ret = platform_get_irq(pdev, 0);
7a468ac6 3013 if (ret < 0)
86a74ff2 3014 goto out_release;
cc3c080d 3015 ndev->irq = ret;
86a74ff2
NI		 3016
3017 SET_NETDEV_DEV(ndev, &pdev->dev);
3018
86a74ff2 3019 mdp = netdev_priv(ndev);
525b8075
YS		 3020 mdp->num_tx_ring = TX_RING_SIZE;
3021 mdp->num_rx_ring = RX_RING_SIZE;
d5e07e69
SS		 3022 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3023 if (IS_ERR(mdp->addr)) {
3024 ret = PTR_ERR(mdp->addr);
ae70644d
YS		 3025 goto out_release;
3026 }
3027
c960804f
VB		 3028 ndev->base_addr = res->start;
3029
86a74ff2 3030 spin_lock_init(&mdp->lock);
bcd5149d 3031 mdp->pdev = pdev;
86a74ff2 3032
b356e978
SS		 3033 if (pdev->dev.of_node)
3034 pd = sh_eth_parse_dt(&pdev->dev);
3b4c5cbf
SS		 3035 if (!pd) {
3036 dev_err(&pdev->dev, "no platform data\n");
3037 ret = -EINVAL;
3038 goto out_release;
3039 }
3040
86a74ff2 3041 /* get PHY ID */
71557a37 3042 mdp->phy_id = pd->phy;
e47c9052 3043 mdp->phy_interface = pd->phy_interface;
4923576b
YS		 3044 mdp->no_ether_link = pd->no_ether_link;
3045 mdp->ether_link_active_low = pd->ether_link_active_low;
86a74ff2 3046
380af9e3 3047 /* set cpu data */
42a67c9b 3048 if (id)
b356e978 3049 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
42a67c9b
WS		 3050 else
3051 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
b356e978 3052
a3153d8c 3053 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
264be2f5
SS		 3054 if (!mdp->reg_offset) {
3055 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3056 mdp->cd->register_type);
3057 ret = -EINVAL;
3058 goto out_release;
3059 }
380af9e3
YS		 3060 sh_eth_set_default_cpu_data(mdp->cd);
3061
86a74ff2 3062 /* set function */
8f728d79
SS		 3063 if (mdp->cd->tsu)
3064 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3065 else
3066 ndev->netdev_ops = &sh_eth_netdev_ops;
7ad24ea4 3067 ndev->ethtool_ops = &sh_eth_ethtool_ops;
86a74ff2
NI		 3068 ndev->watchdog_timeo = TX_TIMEOUT;
3069
dc19e4e5
NI		 3070 /* debug message level */
3071 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 3072
3073 /* read and set MAC address */
748031f9 3074 read_mac_address(ndev, pd->mac_addr);
ff6e7228
SS		 3075 if (!is_valid_ether_addr(ndev->dev_addr)) {
3076 dev_warn(&pdev->dev,
3077 "no valid MAC address supplied, using a random one.\n");
3078 eth_hw_addr_random(ndev);
3079 }
86a74ff2 3080
6ba88021
YS		 3081 /* ioremap the TSU registers */
3082 if (mdp->cd->tsu) {
3083 struct resource *rtsu;
3084 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
d5e07e69
SS		 3085 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3086 if (IS_ERR(mdp->tsu_addr)) {
3087 ret = PTR_ERR(mdp->tsu_addr);
fc0c0900
SS		 3088 goto out_release;
3089 }
6743fe6d 3090 mdp->port = devno % 2;
f646968f 3091 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
6ba88021
YS		 3092 }
3093
150647fb
YS		 3094 /* initialize first or needed device */
3095 if (!devno || pd->needs_init) {
380af9e3
YS		 3096 if (mdp->cd->chip_reset)
3097 mdp->cd->chip_reset(ndev);
86a74ff2 3098
4986b996
YS		 3099 if (mdp->cd->tsu) {
3100 /* TSU init (Init only)*/
3101 sh_eth_tsu_init(mdp);
3102 }
86a74ff2
NI		 3103 }
3104
966d6dbb
HN		 3105 if (mdp->cd->rmiimode)
3106 sh_eth_write(ndev, 0x1, RMIIMODE);
3107
daacf03f
LP		 3108 /* MDIO bus init */
3109 ret = sh_mdio_init(mdp, pd);
3110 if (ret) {
3111 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3112 goto out_release;
3113 }
3114
3719109d
SS		 3115 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3116
86a74ff2
NI		 3117 /* network device register */
3118 ret = register_netdev(ndev);
3119 if (ret)
3719109d 3120 goto out_napi_del;
86a74ff2 3121
25985edc 3122 /* print device information */
f75f14ec
SS		 3123 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3124 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2 3125
b5893a08 3126 pm_runtime_put(&pdev->dev);
86a74ff2
NI		 3127 platform_set_drvdata(pdev, ndev);
3128
3129 return ret;
3130
3719109d
SS		 3131out_napi_del:
3132 netif_napi_del(&mdp->napi);
daacf03f 3133 sh_mdio_release(mdp);
3719109d 3134
86a74ff2
NI		 3135out_release:
3136 /* net_dev free */
3137 if (ndev)
3138 free_netdev(ndev);
3139
b5893a08
BD		 3140 pm_runtime_put(&pdev->dev);
3141 pm_runtime_disable(&pdev->dev);
86a74ff2
NI		 3142 return ret;
3143}
3144
3145static int sh_eth_drv_remove(struct platform_device *pdev)
3146{
3147 struct net_device *ndev = platform_get_drvdata(pdev);
3719109d 3148 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 3149
86a74ff2 3150 unregister_netdev(ndev);
3719109d 3151 netif_napi_del(&mdp->napi);
daacf03f 3152 sh_mdio_release(mdp);
bcd5149d 3153 pm_runtime_disable(&pdev->dev);
86a74ff2 3154 free_netdev(ndev);
86a74ff2
NI		 3155
3156 return 0;
3157}
3158
540ad1b8 3159#ifdef CONFIG_PM
b71af046
MU		 3160#ifdef CONFIG_PM_SLEEP
3161static int sh_eth_suspend(struct device *dev)
3162{
3163 struct net_device *ndev = dev_get_drvdata(dev);
3164 int ret = 0;
3165
3166 if (netif_running(ndev)) {
3167 netif_device_detach(ndev);
3168 ret = sh_eth_close(ndev);
3169 }
3170
3171 return ret;
3172}
3173
3174static int sh_eth_resume(struct device *dev)
3175{
3176 struct net_device *ndev = dev_get_drvdata(dev);
3177 int ret = 0;
3178
3179 if (netif_running(ndev)) {
3180 ret = sh_eth_open(ndev);
3181 if (ret < 0)
3182 return ret;
3183 netif_device_attach(ndev);
3184 }
3185
3186 return ret;
3187}
3188#endif
3189
bcd5149d
MD		 3190static int sh_eth_runtime_nop(struct device *dev)
3191{
128296fc 3192 /* Runtime PM callback shared between ->runtime_suspend()
bcd5149d
MD		 3193 * and ->runtime_resume(). Simply returns success.
3194 *
3195 * This driver re-initializes all registers after
3196 * pm_runtime_get_sync() anyway so there is no need
3197 * to save and restore registers here.
3198 */
3199 return 0;
3200}
3201
540ad1b8 3202static const struct dev_pm_ops sh_eth_dev_pm_ops = {
b71af046 3203 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
e7d7e898 3204 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
bcd5149d 3205};
540ad1b8
NI		 3206#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3207#else
3208#define SH_ETH_PM_OPS NULL
3209#endif
bcd5149d 3210
afe391ad 3211static struct platform_device_id sh_eth_id_table[] = {
c18a79ab 3212 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
7bbe150d 3213 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
9c3beaab 3214 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
f5d12767 3215 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
24549e2a
SS		 3216 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3217 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
f5d12767 3218 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
afe391ad
SS		 3219 { }
3220};
3221MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3222
86a74ff2
NI		 3223static struct platform_driver sh_eth_driver = {
3224 .probe = sh_eth_drv_probe,
3225 .remove = sh_eth_drv_remove,
afe391ad 3226 .id_table = sh_eth_id_table,
86a74ff2
NI		 3227 .driver = {
3228 .name = CARDNAME,
540ad1b8 3229 .pm = SH_ETH_PM_OPS,
b356e978 3230 .of_match_table = of_match_ptr(sh_eth_match_table),
86a74ff2
NI		 3231 },
3232};
3233
db62f684 3234module_platform_driver(sh_eth_driver);
86a74ff2
NI		 3235
3236MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3237MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3238MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)