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Revert "sh_eth: Enable Rx descriptor word 0 shift for r8a7790"
[linux-2.6-block.git] / drivers / net / ethernet / renesas / sh_eth.c
CommitLineData
128296fc 1/* SuperH Ethernet device driver
86a74ff2 2 *
966d6dbb 3 * Copyright (C) 2014 Renesas Electronics Corporation
f0e81fec 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
b356e978
SS		 5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013-2014 Cogent Embedded, Inc.
702eca02 7 * Copyright (C) 2014 Codethink Limited
86a74ff2
NI		 8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
86a74ff2
NI		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 */
21
0654011d
YS		 22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
6a27cded 25#include <linux/interrupt.h>
86a74ff2
NI		 26#include <linux/dma-mapping.h>
27#include <linux/etherdevice.h>
28#include <linux/delay.h>
29#include <linux/platform_device.h>
30#include <linux/mdio-bitbang.h>
31#include <linux/netdevice.h>
b356e978
SS		 32#include <linux/of.h>
33#include <linux/of_device.h>
34#include <linux/of_irq.h>
35#include <linux/of_net.h>
86a74ff2
NI		 36#include <linux/phy.h>
37#include <linux/cache.h>
38#include <linux/io.h>
bcd5149d 39#include <linux/pm_runtime.h>
5a0e3ad6 40#include <linux/slab.h>
dc19e4e5 41#include <linux/ethtool.h>
fdb37a7f 42#include <linux/if_vlan.h>
f0e81fec 43#include <linux/clk.h>
d4fa0e35 44#include <linux/sh_eth.h>
702eca02 45#include <linux/of_mdio.h>
86a74ff2
NI		 46
47#include "sh_eth.h"
48
dc19e4e5
NI		 49#define SH_ETH_DEF_MSG_ENABLE \
50 (NETIF_MSG_LINK | \
51 NETIF_MSG_TIMER | \
52 NETIF_MSG_RX_ERR| \
53 NETIF_MSG_TX_ERR)
54
c0013f6f
SS		 55static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
56 [EDSR] = 0x0000,
57 [EDMR] = 0x0400,
58 [EDTRR] = 0x0408,
59 [EDRRR] = 0x0410,
60 [EESR] = 0x0428,
61 [EESIPR] = 0x0430,
62 [TDLAR] = 0x0010,
63 [TDFAR] = 0x0014,
64 [TDFXR] = 0x0018,
65 [TDFFR] = 0x001c,
66 [RDLAR] = 0x0030,
67 [RDFAR] = 0x0034,
68 [RDFXR] = 0x0038,
69 [RDFFR] = 0x003c,
70 [TRSCER] = 0x0438,
71 [RMFCR] = 0x0440,
72 [TFTR] = 0x0448,
73 [FDR] = 0x0450,
74 [RMCR] = 0x0458,
75 [RPADIR] = 0x0460,
76 [FCFTR] = 0x0468,
77 [CSMR] = 0x04E4,
78
79 [ECMR] = 0x0500,
80 [ECSR] = 0x0510,
81 [ECSIPR] = 0x0518,
82 [PIR] = 0x0520,
83 [PSR] = 0x0528,
84 [PIPR] = 0x052c,
85 [RFLR] = 0x0508,
86 [APR] = 0x0554,
87 [MPR] = 0x0558,
88 [PFTCR] = 0x055c,
89 [PFRCR] = 0x0560,
90 [TPAUSER] = 0x0564,
91 [GECMR] = 0x05b0,
92 [BCULR] = 0x05b4,
93 [MAHR] = 0x05c0,
94 [MALR] = 0x05c8,
95 [TROCR] = 0x0700,
96 [CDCR] = 0x0708,
97 [LCCR] = 0x0710,
98 [CEFCR] = 0x0740,
99 [FRECR] = 0x0748,
100 [TSFRCR] = 0x0750,
101 [TLFRCR] = 0x0758,
102 [RFCR] = 0x0760,
103 [CERCR] = 0x0768,
104 [CEECR] = 0x0770,
105 [MAFCR] = 0x0778,
106 [RMII_MII] = 0x0790,
107
108 [ARSTR] = 0x0000,
109 [TSU_CTRST] = 0x0004,
110 [TSU_FWEN0] = 0x0010,
111 [TSU_FWEN1] = 0x0014,
112 [TSU_FCM] = 0x0018,
113 [TSU_BSYSL0] = 0x0020,
114 [TSU_BSYSL1] = 0x0024,
115 [TSU_PRISL0] = 0x0028,
116 [TSU_PRISL1] = 0x002c,
117 [TSU_FWSL0] = 0x0030,
118 [TSU_FWSL1] = 0x0034,
119 [TSU_FWSLC] = 0x0038,
120 [TSU_QTAG0] = 0x0040,
121 [TSU_QTAG1] = 0x0044,
122 [TSU_FWSR] = 0x0050,
123 [TSU_FWINMK] = 0x0054,
124 [TSU_ADQT0] = 0x0048,
125 [TSU_ADQT1] = 0x004c,
126 [TSU_VTAG0] = 0x0058,
127 [TSU_VTAG1] = 0x005c,
128 [TSU_ADSBSY] = 0x0060,
129 [TSU_TEN] = 0x0064,
130 [TSU_POST1] = 0x0070,
131 [TSU_POST2] = 0x0074,
132 [TSU_POST3] = 0x0078,
133 [TSU_POST4] = 0x007c,
134 [TSU_ADRH0] = 0x0100,
135 [TSU_ADRL0] = 0x0104,
136 [TSU_ADRH31] = 0x01f8,
137 [TSU_ADRL31] = 0x01fc,
138
139 [TXNLCR0] = 0x0080,
140 [TXALCR0] = 0x0084,
141 [RXNLCR0] = 0x0088,
142 [RXALCR0] = 0x008c,
143 [FWNLCR0] = 0x0090,
144 [FWALCR0] = 0x0094,
145 [TXNLCR1] = 0x00a0,
146 [TXALCR1] = 0x00a0,
147 [RXNLCR1] = 0x00a8,
148 [RXALCR1] = 0x00ac,
149 [FWNLCR1] = 0x00b0,
150 [FWALCR1] = 0x00b4,
151};
152
db893473
SH		 153static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
154 [EDSR] = 0x0000,
155 [EDMR] = 0x0400,
156 [EDTRR] = 0x0408,
157 [EDRRR] = 0x0410,
158 [EESR] = 0x0428,
159 [EESIPR] = 0x0430,
160 [TDLAR] = 0x0010,
161 [TDFAR] = 0x0014,
162 [TDFXR] = 0x0018,
163 [TDFFR] = 0x001c,
164 [RDLAR] = 0x0030,
165 [RDFAR] = 0x0034,
166 [RDFXR] = 0x0038,
167 [RDFFR] = 0x003c,
168 [TRSCER] = 0x0438,
169 [RMFCR] = 0x0440,
170 [TFTR] = 0x0448,
171 [FDR] = 0x0450,
172 [RMCR] = 0x0458,
173 [RPADIR] = 0x0460,
174 [FCFTR] = 0x0468,
175 [CSMR] = 0x04E4,
176
177 [ECMR] = 0x0500,
178 [RFLR] = 0x0508,
179 [ECSR] = 0x0510,
180 [ECSIPR] = 0x0518,
181 [PIR] = 0x0520,
182 [APR] = 0x0554,
183 [MPR] = 0x0558,
184 [PFTCR] = 0x055c,
185 [PFRCR] = 0x0560,
186 [TPAUSER] = 0x0564,
187 [MAHR] = 0x05c0,
188 [MALR] = 0x05c8,
189 [CEFCR] = 0x0740,
190 [FRECR] = 0x0748,
191 [TSFRCR] = 0x0750,
192 [TLFRCR] = 0x0758,
193 [RFCR] = 0x0760,
194 [MAFCR] = 0x0778,
195
196 [ARSTR] = 0x0000,
197 [TSU_CTRST] = 0x0004,
198 [TSU_VTAG0] = 0x0058,
199 [TSU_ADSBSY] = 0x0060,
200 [TSU_TEN] = 0x0064,
201 [TSU_ADRH0] = 0x0100,
202 [TSU_ADRL0] = 0x0104,
203 [TSU_ADRH31] = 0x01f8,
204 [TSU_ADRL31] = 0x01fc,
205
206 [TXNLCR0] = 0x0080,
207 [TXALCR0] = 0x0084,
208 [RXNLCR0] = 0x0088,
209 [RXALCR0] = 0x008C,
210};
211
a3f109bd
SS		 212static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
213 [ECMR] = 0x0300,
214 [RFLR] = 0x0308,
215 [ECSR] = 0x0310,
216 [ECSIPR] = 0x0318,
217 [PIR] = 0x0320,
218 [PSR] = 0x0328,
219 [RDMLR] = 0x0340,
220 [IPGR] = 0x0350,
221 [APR] = 0x0354,
222 [MPR] = 0x0358,
223 [RFCF] = 0x0360,
224 [TPAUSER] = 0x0364,
225 [TPAUSECR] = 0x0368,
226 [MAHR] = 0x03c0,
227 [MALR] = 0x03c8,
228 [TROCR] = 0x03d0,
229 [CDCR] = 0x03d4,
230 [LCCR] = 0x03d8,
231 [CNDCR] = 0x03dc,
232 [CEFCR] = 0x03e4,
233 [FRECR] = 0x03e8,
234 [TSFRCR] = 0x03ec,
235 [TLFRCR] = 0x03f0,
236 [RFCR] = 0x03f4,
237 [MAFCR] = 0x03f8,
238
239 [EDMR] = 0x0200,
240 [EDTRR] = 0x0208,
241 [EDRRR] = 0x0210,
242 [TDLAR] = 0x0218,
243 [RDLAR] = 0x0220,
244 [EESR] = 0x0228,
245 [EESIPR] = 0x0230,
246 [TRSCER] = 0x0238,
247 [RMFCR] = 0x0240,
248 [TFTR] = 0x0248,
249 [FDR] = 0x0250,
250 [RMCR] = 0x0258,
251 [TFUCR] = 0x0264,
252 [RFOCR] = 0x0268,
55754f19 253 [RMIIMODE] = 0x026c,
a3f109bd
SS		 254 [FCFTR] = 0x0270,
255 [TRIMD] = 0x027c,
256};
257
c0013f6f
SS		 258static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
259 [ECMR] = 0x0100,
260 [RFLR] = 0x0108,
261 [ECSR] = 0x0110,
262 [ECSIPR] = 0x0118,
263 [PIR] = 0x0120,
264 [PSR] = 0x0128,
265 [RDMLR] = 0x0140,
266 [IPGR] = 0x0150,
267 [APR] = 0x0154,
268 [MPR] = 0x0158,
269 [TPAUSER] = 0x0164,
270 [RFCF] = 0x0160,
271 [TPAUSECR] = 0x0168,
272 [BCFRR] = 0x016c,
273 [MAHR] = 0x01c0,
274 [MALR] = 0x01c8,
275 [TROCR] = 0x01d0,
276 [CDCR] = 0x01d4,
277 [LCCR] = 0x01d8,
278 [CNDCR] = 0x01dc,
279 [CEFCR] = 0x01e4,
280 [FRECR] = 0x01e8,
281 [TSFRCR] = 0x01ec,
282 [TLFRCR] = 0x01f0,
283 [RFCR] = 0x01f4,
284 [MAFCR] = 0x01f8,
285 [RTRATE] = 0x01fc,
286
287 [EDMR] = 0x0000,
288 [EDTRR] = 0x0008,
289 [EDRRR] = 0x0010,
290 [TDLAR] = 0x0018,
291 [RDLAR] = 0x0020,
292 [EESR] = 0x0028,
293 [EESIPR] = 0x0030,
294 [TRSCER] = 0x0038,
295 [RMFCR] = 0x0040,
296 [TFTR] = 0x0048,
297 [FDR] = 0x0050,
298 [RMCR] = 0x0058,
299 [TFUCR] = 0x0064,
300 [RFOCR] = 0x0068,
301 [FCFTR] = 0x0070,
302 [RPADIR] = 0x0078,
303 [TRIMD] = 0x007c,
304 [RBWAR] = 0x00c8,
305 [RDFAR] = 0x00cc,
306 [TBRAR] = 0x00d4,
307 [TDFAR] = 0x00d8,
308};
309
310static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
d8b0426a
SS		 311 [EDMR] = 0x0000,
312 [EDTRR] = 0x0004,
313 [EDRRR] = 0x0008,
314 [TDLAR] = 0x000c,
315 [RDLAR] = 0x0010,
316 [EESR] = 0x0014,
317 [EESIPR] = 0x0018,
318 [TRSCER] = 0x001c,
319 [RMFCR] = 0x0020,
320 [TFTR] = 0x0024,
321 [FDR] = 0x0028,
322 [RMCR] = 0x002c,
323 [EDOCR] = 0x0030,
324 [FCFTR] = 0x0034,
325 [RPADIR] = 0x0038,
326 [TRIMD] = 0x003c,
327 [RBWAR] = 0x0040,
328 [RDFAR] = 0x0044,
329 [TBRAR] = 0x004c,
330 [TDFAR] = 0x0050,
331
c0013f6f
SS		 332 [ECMR] = 0x0160,
333 [ECSR] = 0x0164,
334 [ECSIPR] = 0x0168,
335 [PIR] = 0x016c,
336 [MAHR] = 0x0170,
337 [MALR] = 0x0174,
338 [RFLR] = 0x0178,
339 [PSR] = 0x017c,
340 [TROCR] = 0x0180,
341 [CDCR] = 0x0184,
342 [LCCR] = 0x0188,
343 [CNDCR] = 0x018c,
344 [CEFCR] = 0x0194,
345 [FRECR] = 0x0198,
346 [TSFRCR] = 0x019c,
347 [TLFRCR] = 0x01a0,
348 [RFCR] = 0x01a4,
349 [MAFCR] = 0x01a8,
350 [IPGR] = 0x01b4,
351 [APR] = 0x01b8,
352 [MPR] = 0x01bc,
353 [TPAUSER] = 0x01c4,
354 [BCFR] = 0x01cc,
355
356 [ARSTR] = 0x0000,
357 [TSU_CTRST] = 0x0004,
358 [TSU_FWEN0] = 0x0010,
359 [TSU_FWEN1] = 0x0014,
360 [TSU_FCM] = 0x0018,
361 [TSU_BSYSL0] = 0x0020,
362 [TSU_BSYSL1] = 0x0024,
363 [TSU_PRISL0] = 0x0028,
364 [TSU_PRISL1] = 0x002c,
365 [TSU_FWSL0] = 0x0030,
366 [TSU_FWSL1] = 0x0034,
367 [TSU_FWSLC] = 0x0038,
368 [TSU_QTAGM0] = 0x0040,
369 [TSU_QTAGM1] = 0x0044,
370 [TSU_ADQT0] = 0x0048,
371 [TSU_ADQT1] = 0x004c,
372 [TSU_FWSR] = 0x0050,
373 [TSU_FWINMK] = 0x0054,
374 [TSU_ADSBSY] = 0x0060,
375 [TSU_TEN] = 0x0064,
376 [TSU_POST1] = 0x0070,
377 [TSU_POST2] = 0x0074,
378 [TSU_POST3] = 0x0078,
379 [TSU_POST4] = 0x007c,
380
381 [TXNLCR0] = 0x0080,
382 [TXALCR0] = 0x0084,
383 [RXNLCR0] = 0x0088,
384 [RXALCR0] = 0x008c,
385 [FWNLCR0] = 0x0090,
386 [FWALCR0] = 0x0094,
387 [TXNLCR1] = 0x00a0,
388 [TXALCR1] = 0x00a0,
389 [RXNLCR1] = 0x00a8,
390 [RXALCR1] = 0x00ac,
391 [FWNLCR1] = 0x00b0,
392 [FWALCR1] = 0x00b4,
393
394 [TSU_ADRH0] = 0x0100,
395 [TSU_ADRL0] = 0x0104,
396 [TSU_ADRL31] = 0x01fc,
397};
398
740c7f31
BH		 399static void sh_eth_rcv_snd_disable(struct net_device *ndev);
400static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
401
504c8ca5 402static bool sh_eth_is_gether(struct sh_eth_private *mdp)
dabdde9e 403{
504c8ca5 404 return mdp->reg_offset == sh_eth_offset_gigabit;
dabdde9e
NI		 405}
406
db893473
SH		 407static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
408{
409 return mdp->reg_offset == sh_eth_offset_fast_rz;
410}
411
8e994402 412static void sh_eth_select_mii(struct net_device *ndev)
5e7a76be
NI		 413{
414 u32 value = 0x0;
415 struct sh_eth_private *mdp = netdev_priv(ndev);
416
417 switch (mdp->phy_interface) {
418 case PHY_INTERFACE_MODE_GMII:
419 value = 0x2;
420 break;
421 case PHY_INTERFACE_MODE_MII:
422 value = 0x1;
423 break;
424 case PHY_INTERFACE_MODE_RMII:
425 value = 0x0;
426 break;
427 default:
f75f14ec
SS		 428 netdev_warn(ndev,
429 "PHY interface mode was not setup. Set to MII.\n");
5e7a76be
NI		 430 value = 0x1;
431 break;
432 }
433
434 sh_eth_write(ndev, value, RMII_MII);
435}
5e7a76be 436
8e994402 437static void sh_eth_set_duplex(struct net_device *ndev)
65ac8851
YS		 438{
439 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 440
441 if (mdp->duplex) /* Full */
4a55530f 442 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
65ac8851 443 else /* Half */
4a55530f 444 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
65ac8851
YS		 445}
446
04b0ed2a 447/* There is CPU dependent code */
589ebdef 448static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
65ac8851
YS		 449{
450 struct sh_eth_private *mdp = netdev_priv(ndev);
d0418bb7 451
a3f109bd
SS		 452 switch (mdp->speed) {
453 case 10: /* 10BASE */
454 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
455 break;
456 case 100:/* 100BASE */
457 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
458 break;
459 default:
460 break;
461 }
462}
463
674853b2 464/* R8A7778/9 */
589ebdef 465static struct sh_eth_cpu_data r8a777x_data = {
a3f109bd 466 .set_duplex = sh_eth_set_duplex,
589ebdef 467 .set_rate = sh_eth_set_rate_r8a777x,
a3f109bd 468
a3153d8c
SS		 469 .register_type = SH_ETH_REG_FAST_RCAR,
470
a3f109bd
SS		 471 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
472 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
473 .eesipr_value = 0x01ff009f,
474
475 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 476 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
477 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
478 EESR_ECI,
d407bc02 479 .fdr_value = 0x00000f0f,
a3f109bd
SS		 480
481 .apr = 1,
482 .mpr = 1,
483 .tpauser = 1,
484 .hw_swap = 1,
485};
a3f109bd 486
94a12b15
SS		 487/* R8A7790/1 */
488static struct sh_eth_cpu_data r8a779x_data = {
e18dbf7e
SH		 489 .set_duplex = sh_eth_set_duplex,
490 .set_rate = sh_eth_set_rate_r8a777x,
491
a3153d8c
SS		 492 .register_type = SH_ETH_REG_FAST_RCAR,
493
e18dbf7e
SH		 494 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
495 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
496 .eesipr_value = 0x01ff009f,
497
498 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ba361cb3
LP		 499 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
500 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
501 EESR_ECI,
d407bc02 502 .fdr_value = 0x00000f0f,
e18dbf7e 503
01fbd3f5
GU		 504 .trscer_err_mask = DESC_I_RINT8,
505
e18dbf7e
SH		 506 .apr = 1,
507 .mpr = 1,
508 .tpauser = 1,
509 .hw_swap = 1,
510 .rmiimode = 1,
511};
512
9c3beaab 513static void sh_eth_set_rate_sh7724(struct net_device *ndev)
a3f109bd
SS		 514{
515 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 516
517 switch (mdp->speed) {
518 case 10: /* 10BASE */
a3f109bd 519 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
65ac8851
YS		 520 break;
521 case 100:/* 100BASE */
a3f109bd 522 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
65ac8851
YS		 523 break;
524 default:
525 break;
526 }
527}
528
529/* SH7724 */
9c3beaab 530static struct sh_eth_cpu_data sh7724_data = {
65ac8851 531 .set_duplex = sh_eth_set_duplex,
9c3beaab 532 .set_rate = sh_eth_set_rate_sh7724,
65ac8851 533
a3153d8c
SS		 534 .register_type = SH_ETH_REG_FAST_SH4,
535
65ac8851
YS		 536 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
537 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
a80c3de7 538 .eesipr_value = 0x01ff009f,
65ac8851
YS		 539
540 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 541 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
542 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
543 EESR_ECI,
65ac8851
YS		 544
545 .apr = 1,
546 .mpr = 1,
547 .tpauser = 1,
548 .hw_swap = 1,
503914cf
MD		 549 .rpadir = 1,
550 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 551};
5cee1d37 552
24549e2a 553static void sh_eth_set_rate_sh7757(struct net_device *ndev)
f29a3d04
YS		 554{
555 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 556
557 switch (mdp->speed) {
558 case 10: /* 10BASE */
4a55530f 559 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 560 break;
561 case 100:/* 100BASE */
4a55530f 562 sh_eth_write(ndev, 1, RTRATE);
f29a3d04
YS		 563 break;
564 default:
565 break;
566 }
567}
568
569/* SH7757 */
24549e2a
SS		 570static struct sh_eth_cpu_data sh7757_data = {
571 .set_duplex = sh_eth_set_duplex,
572 .set_rate = sh_eth_set_rate_sh7757,
f29a3d04 573
a3153d8c
SS		 574 .register_type = SH_ETH_REG_FAST_SH4,
575
f29a3d04 576 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
f29a3d04
YS		 577
578 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 579 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
580 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
581 EESR_ECI,
f29a3d04 582
5b3dfd13 583 .irq_flags = IRQF_SHARED,
f29a3d04
YS		 584 .apr = 1,
585 .mpr = 1,
586 .tpauser = 1,
587 .hw_swap = 1,
588 .no_ade = 1,
2e98e797
YS		 589 .rpadir = 1,
590 .rpadir_value = 2 << 16,
f29a3d04 591};
65ac8851 592
e403d295 593#define SH_GIGA_ETH_BASE 0xfee00000UL
8fcd4961
YS		 594#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
595#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
596static void sh_eth_chip_reset_giga(struct net_device *ndev)
597{
598 int i;
0799c2d6 599 u32 mahr[2], malr[2];
8fcd4961
YS		 600
601 /* save MAHR and MALR */
602 for (i = 0; i < 2; i++) {
ae70644d
YS		 603 malr[i] = ioread32((void *)GIGA_MALR(i));
604 mahr[i] = ioread32((void *)GIGA_MAHR(i));
8fcd4961
YS		 605 }
606
607 /* reset device */
ae70644d 608 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
8fcd4961
YS		 609 mdelay(1);
610
611 /* restore MAHR and MALR */
612 for (i = 0; i < 2; i++) {
ae70644d
YS		 613 iowrite32(malr[i], (void *)GIGA_MALR(i));
614 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
8fcd4961
YS		 615 }
616}
617
8fcd4961
YS		 618static void sh_eth_set_rate_giga(struct net_device *ndev)
619{
620 struct sh_eth_private *mdp = netdev_priv(ndev);
621
622 switch (mdp->speed) {
623 case 10: /* 10BASE */
624 sh_eth_write(ndev, 0x00000000, GECMR);
625 break;
626 case 100:/* 100BASE */
627 sh_eth_write(ndev, 0x00000010, GECMR);
628 break;
629 case 1000: /* 1000BASE */
630 sh_eth_write(ndev, 0x00000020, GECMR);
631 break;
632 default:
633 break;
634 }
635}
636
637/* SH7757(GETHERC) */
24549e2a 638static struct sh_eth_cpu_data sh7757_data_giga = {
8fcd4961 639 .chip_reset = sh_eth_chip_reset_giga,
04b0ed2a 640 .set_duplex = sh_eth_set_duplex,
8fcd4961
YS		 641 .set_rate = sh_eth_set_rate_giga,
642
a3153d8c
SS		 643 .register_type = SH_ETH_REG_GIGABIT,
644
8fcd4961
YS		 645 .ecsr_value = ECSR_ICD | ECSR_MPD,
646 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
647 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
648
649 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 650 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
651 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
652 EESR_TDE | EESR_ECI,
8fcd4961 653 .fdr_value = 0x0000072f,
8fcd4961 654
5b3dfd13 655 .irq_flags = IRQF_SHARED,
8fcd4961
YS		 656 .apr = 1,
657 .mpr = 1,
658 .tpauser = 1,
659 .bculr = 1,
660 .hw_swap = 1,
661 .rpadir = 1,
662 .rpadir_value = 2 << 16,
663 .no_trimd = 1,
664 .no_ade = 1,
3acbc971 665 .tsu = 1,
8fcd4961
YS		 666};
667
380af9e3
YS		 668static void sh_eth_chip_reset(struct net_device *ndev)
669{
4986b996
YS		 670 struct sh_eth_private *mdp = netdev_priv(ndev);
671
380af9e3 672 /* reset device */
4986b996 673 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
380af9e3
YS		 674 mdelay(1);
675}
676
f5d12767 677static void sh_eth_set_rate_gether(struct net_device *ndev)
380af9e3
YS		 678{
679 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3
YS		 680
681 switch (mdp->speed) {
682 case 10: /* 10BASE */
4a55530f 683 sh_eth_write(ndev, GECMR_10, GECMR);
380af9e3
YS		 684 break;
685 case 100:/* 100BASE */
4a55530f 686 sh_eth_write(ndev, GECMR_100, GECMR);
380af9e3
YS		 687 break;
688 case 1000: /* 1000BASE */
4a55530f 689 sh_eth_write(ndev, GECMR_1000, GECMR);
380af9e3
YS		 690 break;
691 default:
692 break;
693 }
694}
695
f5d12767
SS		 696/* SH7734 */
697static struct sh_eth_cpu_data sh7734_data = {
380af9e3
YS		 698 .chip_reset = sh_eth_chip_reset,
699 .set_duplex = sh_eth_set_duplex,
f5d12767
SS		 700 .set_rate = sh_eth_set_rate_gether,
701
a3153d8c
SS		 702 .register_type = SH_ETH_REG_GIGABIT,
703
f5d12767
SS		 704 .ecsr_value = ECSR_ICD | ECSR_MPD,
705 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
706 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
707
708 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 709 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
710 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
711 EESR_TDE | EESR_ECI,
f5d12767
SS		 712
713 .apr = 1,
714 .mpr = 1,
715 .tpauser = 1,
716 .bculr = 1,
717 .hw_swap = 1,
718 .no_trimd = 1,
719 .no_ade = 1,
720 .tsu = 1,
721 .hw_crc = 1,
722 .select_mii = 1,
723};
724
725/* SH7763 */
726static struct sh_eth_cpu_data sh7763_data = {
727 .chip_reset = sh_eth_chip_reset,
728 .set_duplex = sh_eth_set_duplex,
729 .set_rate = sh_eth_set_rate_gether,
380af9e3 730
a3153d8c
SS		 731 .register_type = SH_ETH_REG_GIGABIT,
732
380af9e3
YS		 733 .ecsr_value = ECSR_ICD | ECSR_MPD,
734 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
735 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
736
737 .tx_check = EESR_TC1 | EESR_FTC,
128296fc
SS		 738 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
739 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
380af9e3 740 EESR_ECI,
380af9e3
YS		 741
742 .apr = 1,
743 .mpr = 1,
744 .tpauser = 1,
745 .bculr = 1,
746 .hw_swap = 1,
380af9e3
YS		 747 .no_trimd = 1,
748 .no_ade = 1,
4986b996 749 .tsu = 1,
5b3dfd13 750 .irq_flags = IRQF_SHARED,
380af9e3
YS		 751};
752
e5c9b4cd 753static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
73a0d907
YS		 754{
755 struct sh_eth_private *mdp = netdev_priv(ndev);
73a0d907
YS		 756
757 /* reset device */
758 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
759 mdelay(1);
760
5e7a76be 761 sh_eth_select_mii(ndev);
73a0d907
YS		 762}
763
73a0d907 764/* R8A7740 */
e5c9b4cd
SS		 765static struct sh_eth_cpu_data r8a7740_data = {
766 .chip_reset = sh_eth_chip_reset_r8a7740,
73a0d907 767 .set_duplex = sh_eth_set_duplex,
e5c9b4cd 768 .set_rate = sh_eth_set_rate_gether,
73a0d907 769
a3153d8c
SS		 770 .register_type = SH_ETH_REG_GIGABIT,
771
73a0d907
YS		 772 .ecsr_value = ECSR_ICD | ECSR_MPD,
773 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
774 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
775
776 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 777 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
778 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
779 EESR_TDE | EESR_ECI,
cc23528d 780 .fdr_value = 0x0000070f,
73a0d907
YS		 781
782 .apr = 1,
783 .mpr = 1,
784 .tpauser = 1,
785 .bculr = 1,
786 .hw_swap = 1,
cc23528d
SH		 787 .rpadir = 1,
788 .rpadir_value = 2 << 16,
73a0d907
YS		 789 .no_trimd = 1,
790 .no_ade = 1,
791 .tsu = 1,
5e7a76be 792 .select_mii = 1,
ac8025a6 793 .shift_rd0 = 1,
73a0d907
YS		 794};
795
db893473
SH		 796/* R7S72100 */
797static struct sh_eth_cpu_data r7s72100_data = {
798 .chip_reset = sh_eth_chip_reset,
799 .set_duplex = sh_eth_set_duplex,
800
801 .register_type = SH_ETH_REG_FAST_RZ,
802
803 .ecsr_value = ECSR_ICD,
804 .ecsipr_value = ECSIPR_ICDIP,
805 .eesipr_value = 0xff7f009f,
806
807 .tx_check = EESR_TC1 | EESR_FTC,
808 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
809 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
810 EESR_TDE | EESR_ECI,
811 .fdr_value = 0x0000070f,
db893473
SH		 812
813 .no_psr = 1,
814 .apr = 1,
815 .mpr = 1,
816 .tpauser = 1,
817 .hw_swap = 1,
818 .rpadir = 1,
819 .rpadir_value = 2 << 16,
820 .no_trimd = 1,
821 .no_ade = 1,
822 .hw_crc = 1,
823 .tsu = 1,
824 .shift_rd0 = 1,
825};
826
c18a79ab 827static struct sh_eth_cpu_data sh7619_data = {
a3153d8c
SS		 828 .register_type = SH_ETH_REG_FAST_SH3_SH2,
829
380af9e3
YS		 830 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
831
832 .apr = 1,
833 .mpr = 1,
834 .tpauser = 1,
835 .hw_swap = 1,
836};
7bbe150d
SS		 837
838static struct sh_eth_cpu_data sh771x_data = {
a3153d8c
SS		 839 .register_type = SH_ETH_REG_FAST_SH3_SH2,
840
380af9e3 841 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
4986b996 842 .tsu = 1,
380af9e3 843};
380af9e3
YS		 844
845static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
846{
847 if (!cd->ecsr_value)
848 cd->ecsr_value = DEFAULT_ECSR_INIT;
849
850 if (!cd->ecsipr_value)
851 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
852
853 if (!cd->fcftr_value)
128296fc 854 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
380af9e3
YS		 855 DEFAULT_FIFO_F_D_RFD;
856
857 if (!cd->fdr_value)
858 cd->fdr_value = DEFAULT_FDR_INIT;
859
380af9e3
YS		 860 if (!cd->tx_check)
861 cd->tx_check = DEFAULT_TX_CHECK;
862
863 if (!cd->eesr_err_check)
864 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
b284fbe3
NI		 865
866 if (!cd->trscer_err_mask)
867 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
380af9e3
YS		 868}
869
5cee1d37
NI		 870static int sh_eth_check_reset(struct net_device *ndev)
871{
872 int ret = 0;
873 int cnt = 100;
874
875 while (cnt > 0) {
876 if (!(sh_eth_read(ndev, EDMR) & 0x3))
877 break;
878 mdelay(1);
879 cnt--;
880 }
9f8c4265 881 if (cnt <= 0) {
f75f14ec 882 netdev_err(ndev, "Device reset failed\n");
5cee1d37
NI		 883 ret = -ETIMEDOUT;
884 }
885 return ret;
380af9e3 886}
dabdde9e
NI		 887
888static int sh_eth_reset(struct net_device *ndev)
889{
890 struct sh_eth_private *mdp = netdev_priv(ndev);
891 int ret = 0;
892
db893473 893 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
dabdde9e
NI		 894 sh_eth_write(ndev, EDSR_ENALL, EDSR);
895 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
896 EDMR);
897
898 ret = sh_eth_check_reset(ndev);
899 if (ret)
f738a13d 900 return ret;
dabdde9e
NI		 901
902 /* Table Init */
903 sh_eth_write(ndev, 0x0, TDLAR);
904 sh_eth_write(ndev, 0x0, TDFAR);
905 sh_eth_write(ndev, 0x0, TDFXR);
906 sh_eth_write(ndev, 0x0, TDFFR);
907 sh_eth_write(ndev, 0x0, RDLAR);
908 sh_eth_write(ndev, 0x0, RDFAR);
909 sh_eth_write(ndev, 0x0, RDFXR);
910 sh_eth_write(ndev, 0x0, RDFFR);
911
912 /* Reset HW CRC register */
913 if (mdp->cd->hw_crc)
914 sh_eth_write(ndev, 0x0, CSMR);
915
916 /* Select MII mode */
917 if (mdp->cd->select_mii)
918 sh_eth_select_mii(ndev);
919 } else {
920 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
921 EDMR);
922 mdelay(3);
923 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
924 EDMR);
925 }
926
dabdde9e
NI		 927 return ret;
928}
380af9e3 929
380af9e3
YS		 930static void sh_eth_set_receive_align(struct sk_buff *skb)
931{
4d6a949c 932 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
380af9e3 933
380af9e3 934 if (reserve)
4d6a949c 935 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
380af9e3 936}
380af9e3
YS		 937
938
71557a37
YS		 939/* CPU <-> EDMAC endian convert */
940static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
941{
942 switch (mdp->edmac_endian) {
943 case EDMAC_LITTLE_ENDIAN:
944 return cpu_to_le32(x);
945 case EDMAC_BIG_ENDIAN:
946 return cpu_to_be32(x);
947 }
948 return x;
949}
950
951static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
952{
953 switch (mdp->edmac_endian) {
954 case EDMAC_LITTLE_ENDIAN:
955 return le32_to_cpu(x);
956 case EDMAC_BIG_ENDIAN:
957 return be32_to_cpu(x);
958 }
959 return x;
960}
961
128296fc 962/* Program the hardware MAC address from dev->dev_addr. */
86a74ff2
NI		 963static void update_mac_address(struct net_device *ndev)
964{
4a55530f 965 sh_eth_write(ndev,
128296fc
SS		 966 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
967 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
4a55530f 968 sh_eth_write(ndev,
128296fc 969 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 970}
971
128296fc 972/* Get MAC address from SuperH MAC address register
86a74ff2
NI		 973 *
974 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
975 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
976 * When you want use this device, you must set MAC address in bootloader.
977 *
978 */
748031f9 979static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 980{
748031f9 981 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
d458cdf7 982 memcpy(ndev->dev_addr, mac, ETH_ALEN);
748031f9 983 } else {
4a55530f
YS		 984 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
985 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
986 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
987 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
988 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
989 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
748031f9 990 }
86a74ff2
NI		 991}
992
0799c2d6 993static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
c5ed5368 994{
db893473 995 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
c5ed5368
YS		 996 return EDTRR_TRNS_GETHER;
997 else
998 return EDTRR_TRNS_ETHER;
999}
1000
86a74ff2 1001struct bb_info {
ae70644d 1002 void (*set_gate)(void *addr);
86a74ff2 1003 struct mdiobb_ctrl ctrl;
ae70644d 1004 void *addr;
86a74ff2
NI		 1005 u32 mmd_msk;/* MMD */
1006 u32 mdo_msk;
1007 u32 mdi_msk;
1008 u32 mdc_msk;
1009};
1010
1011/* PHY bit set */
ae70644d 1012static void bb_set(void *addr, u32 msk)
86a74ff2 1013{
ae70644d 1014 iowrite32(ioread32(addr) | msk, addr);
86a74ff2
NI		 1015}
1016
1017/* PHY bit clear */
ae70644d 1018static void bb_clr(void *addr, u32 msk)
86a74ff2 1019{
ae70644d 1020 iowrite32((ioread32(addr) & ~msk), addr);
86a74ff2
NI		 1021}
1022
1023/* PHY bit read */
ae70644d 1024static int bb_read(void *addr, u32 msk)
86a74ff2 1025{
ae70644d 1026 return (ioread32(addr) & msk) != 0;
86a74ff2
NI		 1027}
1028
1029/* Data I/O pin control */
1030static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1031{
1032 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1033
1034 if (bitbang->set_gate)
1035 bitbang->set_gate(bitbang->addr);
1036
86a74ff2
NI		 1037 if (bit)
1038 bb_set(bitbang->addr, bitbang->mmd_msk);
1039 else
1040 bb_clr(bitbang->addr, bitbang->mmd_msk);
1041}
1042
1043/* Set bit data*/
1044static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1045{
1046 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1047
b3017e6a
YS		 1048 if (bitbang->set_gate)
1049 bitbang->set_gate(bitbang->addr);
1050
86a74ff2
NI		 1051 if (bit)
1052 bb_set(bitbang->addr, bitbang->mdo_msk);
1053 else
1054 bb_clr(bitbang->addr, bitbang->mdo_msk);
1055}
1056
1057/* Get bit data*/
1058static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1059{
1060 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1061
1062 if (bitbang->set_gate)
1063 bitbang->set_gate(bitbang->addr);
1064
86a74ff2
NI		 1065 return bb_read(bitbang->addr, bitbang->mdi_msk);
1066}
1067
1068/* MDC pin control */
1069static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1070{
1071 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1072
b3017e6a
YS		 1073 if (bitbang->set_gate)
1074 bitbang->set_gate(bitbang->addr);
1075
86a74ff2
NI		 1076 if (bit)
1077 bb_set(bitbang->addr, bitbang->mdc_msk);
1078 else
1079 bb_clr(bitbang->addr, bitbang->mdc_msk);
1080}
1081
1082/* mdio bus control struct */
1083static struct mdiobb_ops bb_ops = {
1084 .owner = THIS_MODULE,
1085 .set_mdc = sh_mdc_ctrl,
1086 .set_mdio_dir = sh_mmd_ctrl,
1087 .set_mdio_data = sh_set_mdio,
1088 .get_mdio_data = sh_get_mdio,
1089};
1090
86a74ff2
NI		 1091/* free skb and descriptor buffer */
1092static void sh_eth_ring_free(struct net_device *ndev)
1093{
1094 struct sh_eth_private *mdp = netdev_priv(ndev);
1095 int i;
1096
1097 /* Free Rx skb ringbuffer */
1098 if (mdp->rx_skbuff) {
179d80af
SS		 1099 for (i = 0; i < mdp->num_rx_ring; i++)
1100 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 1101 }
1102 kfree(mdp->rx_skbuff);
91c77550 1103 mdp->rx_skbuff = NULL;
86a74ff2
NI		 1104
1105 /* Free Tx skb ringbuffer */
1106 if (mdp->tx_skbuff) {
179d80af
SS		 1107 for (i = 0; i < mdp->num_tx_ring; i++)
1108 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 1109 }
1110 kfree(mdp->tx_skbuff);
91c77550 1111 mdp->tx_skbuff = NULL;
86a74ff2
NI		 1112}
1113
1114/* format skb and descriptor buffer */
1115static void sh_eth_ring_format(struct net_device *ndev)
1116{
1117 struct sh_eth_private *mdp = netdev_priv(ndev);
1118 int i;
1119 struct sk_buff *skb;
1120 struct sh_eth_rxdesc *rxdesc = NULL;
1121 struct sh_eth_txdesc *txdesc = NULL;
525b8075
YS		 1122 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1123 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
4d6a949c 1124 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN - 1;
52b9fa36 1125 dma_addr_t dma_addr;
86a74ff2 1126
128296fc
SS		 1127 mdp->cur_rx = 0;
1128 mdp->cur_tx = 0;
1129 mdp->dirty_rx = 0;
1130 mdp->dirty_tx = 0;
86a74ff2
NI		 1131
1132 memset(mdp->rx_ring, 0, rx_ringsize);
1133
1134 /* build Rx ring buffer */
525b8075 1135 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1136 /* skb */
1137 mdp->rx_skbuff[i] = NULL;
4d6a949c 1138 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1139 if (skb == NULL)
1140 break;
380af9e3
YS		 1141 sh_eth_set_receive_align(skb);
1142
86a74ff2
NI		 1143 /* RX descriptor */
1144 rxdesc = &mdp->rx_ring[i];
4d6a949c
MK		 1145 /* The size of the buffer is a multiple of 16 bytes. */
1146 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
52b9fa36
BH		 1147 dma_addr = dma_map_single(&ndev->dev, skb->data,
1148 rxdesc->buffer_length,
1149 DMA_FROM_DEVICE);
1150 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1151 kfree_skb(skb);
1152 break;
1153 }
1154 mdp->rx_skbuff[i] = skb;
1155 rxdesc->addr = dma_addr;
71557a37 1156 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2 1157
b0ca2a21
NI		 1158 /* Rx descriptor address set */
1159 if (i == 0) {
4a55530f 1160 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
db893473
SH		 1161 if (sh_eth_is_gether(mdp) ||
1162 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1163 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 1164 }
86a74ff2
NI		 1165 }
1166
525b8075 1167 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
86a74ff2
NI		 1168
1169 /* Mark the last entry as wrapping the ring. */
71557a37 1170 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
86a74ff2
NI		 1171
1172 memset(mdp->tx_ring, 0, tx_ringsize);
1173
1174 /* build Tx ring buffer */
525b8075 1175 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1176 mdp->tx_skbuff[i] = NULL;
1177 txdesc = &mdp->tx_ring[i];
71557a37 1178 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 1179 txdesc->buffer_length = 0;
b0ca2a21 1180 if (i == 0) {
71557a37 1181 /* Tx descriptor address set */
4a55530f 1182 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
db893473
SH		 1183 if (sh_eth_is_gether(mdp) ||
1184 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1185 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 1186 }
86a74ff2
NI		 1187 }
1188
71557a37 1189 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2
NI		 1190}
1191
1192/* Get skb and descriptor buffer */
1193static int sh_eth_ring_init(struct net_device *ndev)
1194{
1195 struct sh_eth_private *mdp = netdev_priv(ndev);
1196 int rx_ringsize, tx_ringsize, ret = 0;
1197
128296fc 1198 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
86a74ff2
NI		 1199 * card needs room to do 8 byte alignment, +2 so we can reserve
1200 * the first 2 bytes, and +16 gets room for the status word from the
1201 * card.
1202 */
1203 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1204 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 1205 if (mdp->cd->rpadir)
1206 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 1207
1208 /* Allocate RX and TX skb rings */
b2adaca9
JP		 1209 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1210 sizeof(*mdp->rx_skbuff), GFP_KERNEL);
86a74ff2 1211 if (!mdp->rx_skbuff) {
86a74ff2
NI		 1212 ret = -ENOMEM;
1213 return ret;
1214 }
1215
b2adaca9
JP		 1216 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1217 sizeof(*mdp->tx_skbuff), GFP_KERNEL);
86a74ff2 1218 if (!mdp->tx_skbuff) {
86a74ff2
NI		 1219 ret = -ENOMEM;
1220 goto skb_ring_free;
1221 }
1222
1223 /* Allocate all Rx descriptors. */
525b8075 1224 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
86a74ff2 1225 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
d0320f75 1226 GFP_KERNEL);
86a74ff2 1227 if (!mdp->rx_ring) {
86a74ff2
NI		 1228 ret = -ENOMEM;
1229 goto desc_ring_free;
1230 }
1231
1232 mdp->dirty_rx = 0;
1233
1234 /* Allocate all Tx descriptors. */
525b8075 1235 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
86a74ff2 1236 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
d0320f75 1237 GFP_KERNEL);
86a74ff2 1238 if (!mdp->tx_ring) {
86a74ff2
NI		 1239 ret = -ENOMEM;
1240 goto desc_ring_free;
1241 }
1242 return ret;
1243
1244desc_ring_free:
1245 /* free DMA buffer */
1246 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1247
1248skb_ring_free:
1249 /* Free Rx and Tx skb ring buffer */
1250 sh_eth_ring_free(ndev);
91c77550
YS		 1251 mdp->tx_ring = NULL;
1252 mdp->rx_ring = NULL;
86a74ff2
NI		 1253
1254 return ret;
1255}
1256
91c77550
YS		 1257static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1258{
1259 int ringsize;
1260
1261 if (mdp->rx_ring) {
525b8075 1262 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
91c77550
YS		 1263 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1264 mdp->rx_desc_dma);
1265 mdp->rx_ring = NULL;
1266 }
1267
1268 if (mdp->tx_ring) {
525b8075 1269 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
91c77550
YS		 1270 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1271 mdp->tx_desc_dma);
1272 mdp->tx_ring = NULL;
1273 }
1274}
1275
525b8075 1276static int sh_eth_dev_init(struct net_device *ndev, bool start)
86a74ff2
NI		 1277{
1278 int ret = 0;
1279 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1280 u32 val;
1281
1282 /* Soft Reset */
5cee1d37
NI		 1283 ret = sh_eth_reset(ndev);
1284 if (ret)
f738a13d 1285 return ret;
86a74ff2 1286
55754f19
SH		 1287 if (mdp->cd->rmiimode)
1288 sh_eth_write(ndev, 0x1, RMIIMODE);
1289
b0ca2a21
NI		 1290 /* Descriptor format */
1291 sh_eth_ring_format(ndev);
380af9e3 1292 if (mdp->cd->rpadir)
4a55530f 1293 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 1294
1295 /* all sh_eth int mask */
4a55530f 1296 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 1297
10b9194f 1298#if defined(__LITTLE_ENDIAN)
380af9e3 1299 if (mdp->cd->hw_swap)
4a55530f 1300 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 1301 else
b0ca2a21 1302#endif
4a55530f 1303 sh_eth_write(ndev, 0, EDMR);
86a74ff2 1304
b0ca2a21 1305 /* FIFO size set */
4a55530f
YS		 1306 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1307 sh_eth_write(ndev, 0, TFTR);
86a74ff2 1308
530aa2d0
BD		 1309 /* Frame recv control (enable multiple-packets per rx irq) */
1310 sh_eth_write(ndev, RMCR_RNC, RMCR);
86a74ff2 1311
b284fbe3 1312 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
86a74ff2 1313
380af9e3 1314 if (mdp->cd->bculr)
4a55530f 1315 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 1316
4a55530f 1317 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 1318
380af9e3 1319 if (!mdp->cd->no_trimd)
4a55530f 1320 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 1321
b0ca2a21 1322 /* Recv frame limit set register */
fdb37a7f
YS		 1323 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1324 RFLR);
86a74ff2 1325
4a55530f 1326 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
283e38db
BH		 1327 if (start) {
1328 mdp->irq_enabled = true;
525b8075 1329 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
283e38db 1330 }
86a74ff2
NI		 1331
1332 /* PAUSE Prohibition */
4a55530f 1333 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
86a74ff2
NI		 1334 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1335
4a55530f 1336 sh_eth_write(ndev, val, ECMR);
b0ca2a21 1337
380af9e3
YS		 1338 if (mdp->cd->set_rate)
1339 mdp->cd->set_rate(ndev);
1340
b0ca2a21 1341 /* E-MAC Status Register clear */
4a55530f 1342 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 1343
1344 /* E-MAC Interrupt Enable register */
525b8075
YS		 1345 if (start)
1346 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 1347
1348 /* Set MAC address */
1349 update_mac_address(ndev);
1350
1351 /* mask reset */
380af9e3 1352 if (mdp->cd->apr)
4a55530f 1353 sh_eth_write(ndev, APR_AP, APR);
380af9e3 1354 if (mdp->cd->mpr)
4a55530f 1355 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 1356 if (mdp->cd->tpauser)
4a55530f 1357 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 1358
525b8075
YS		 1359 if (start) {
1360 /* Setting the Rx mode will start the Rx process. */
1361 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2 1362
525b8075
YS		 1363 netif_start_queue(ndev);
1364 }
86a74ff2
NI		 1365
1366 return ret;
1367}
1368
740c7f31
BH		 1369static void sh_eth_dev_exit(struct net_device *ndev)
1370{
1371 struct sh_eth_private *mdp = netdev_priv(ndev);
1372 int i;
1373
1374 /* Deactivate all TX descriptors, so DMA should stop at next
1375 * packet boundary if it's currently running
1376 */
1377 for (i = 0; i < mdp->num_tx_ring; i++)
1378 mdp->tx_ring[i].status &= ~cpu_to_edmac(mdp, TD_TACT);
1379
1380 /* Disable TX FIFO egress to MAC */
1381 sh_eth_rcv_snd_disable(ndev);
1382
1383 /* Stop RX DMA at next packet boundary */
1384 sh_eth_write(ndev, 0, EDRRR);
1385
1386 /* Aside from TX DMA, we can't tell when the hardware is
1387 * really stopped, so we need to reset to make sure.
1388 * Before doing that, wait for long enough to *probably*
1389 * finish transmitting the last packet and poll stats.
1390 */
1391 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1392 sh_eth_get_stats(ndev);
1393 sh_eth_reset(ndev);
a14c7d15
GU		 1394
1395 /* Set MAC address again */
1396 update_mac_address(ndev);
740c7f31
BH		 1397}
1398
86a74ff2
NI		 1399/* free Tx skb function */
1400static int sh_eth_txfree(struct net_device *ndev)
1401{
1402 struct sh_eth_private *mdp = netdev_priv(ndev);
1403 struct sh_eth_txdesc *txdesc;
128296fc 1404 int free_num = 0;
86a74ff2
NI		 1405 int entry = 0;
1406
1407 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
525b8075 1408 entry = mdp->dirty_tx % mdp->num_tx_ring;
86a74ff2 1409 txdesc = &mdp->tx_ring[entry];
71557a37 1410 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
86a74ff2 1411 break;
7d7355f5
BH		 1412 /* TACT bit must be checked before all the following reads */
1413 rmb();
86a74ff2
NI		 1414 /* Free the original skb. */
1415 if (mdp->tx_skbuff[entry]) {
31fcb99d
YS		 1416 dma_unmap_single(&ndev->dev, txdesc->addr,
1417 txdesc->buffer_length, DMA_TO_DEVICE);
86a74ff2
NI		 1418 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1419 mdp->tx_skbuff[entry] = NULL;
128296fc 1420 free_num++;
86a74ff2 1421 }
71557a37 1422 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
525b8075 1423 if (entry >= mdp->num_tx_ring - 1)
71557a37 1424 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2 1425
bb7d92e3
ED		 1426 ndev->stats.tx_packets++;
1427 ndev->stats.tx_bytes += txdesc->buffer_length;
86a74ff2 1428 }
128296fc 1429 return free_num;
86a74ff2
NI		 1430}
1431
1432/* Packet receive function */
3719109d 1433static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
86a74ff2
NI		 1434{
1435 struct sh_eth_private *mdp = netdev_priv(ndev);
1436 struct sh_eth_rxdesc *rxdesc;
1437
525b8075
YS		 1438 int entry = mdp->cur_rx % mdp->num_rx_ring;
1439 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
319cd520 1440 int limit;
86a74ff2
NI		 1441 struct sk_buff *skb;
1442 u16 pkt_len = 0;
380af9e3 1443 u32 desc_status;
4d6a949c 1444 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN - 1;
52b9fa36 1445 dma_addr_t dma_addr;
86a74ff2 1446
319cd520
MK		 1447 boguscnt = min(boguscnt, *quota);
1448 limit = boguscnt;
86a74ff2 1449 rxdesc = &mdp->rx_ring[entry];
71557a37 1450 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
7d7355f5
BH		 1451 /* RACT bit must be checked before all the following reads */
1452 rmb();
71557a37 1453 desc_status = edmac_to_cpu(mdp, rxdesc->status);
86a74ff2
NI		 1454 pkt_len = rxdesc->frame_length;
1455
1456 if (--boguscnt < 0)
1457 break;
1458
1459 if (!(desc_status & RDFEND))
bb7d92e3 1460 ndev->stats.rx_length_errors++;
86a74ff2 1461
128296fc 1462 /* In case of almost all GETHER/ETHERs, the Receive Frame State
dd019897 1463 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
9b4a6364
BH		 1464 * bit 0. However, in case of the R8A7740 and R7S72100
1465 * the RFS bits are from bit 25 to bit 16. So, the
db893473 1466 * driver needs right shifting by 16.
dd019897 1467 */
ac8025a6
SS		 1468 if (mdp->cd->shift_rd0)
1469 desc_status >>= 16;
dd019897 1470
86a74ff2
NI		 1471 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1472 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
bb7d92e3 1473 ndev->stats.rx_errors++;
86a74ff2 1474 if (desc_status & RD_RFS1)
bb7d92e3 1475 ndev->stats.rx_crc_errors++;
86a74ff2 1476 if (desc_status & RD_RFS2)
bb7d92e3 1477 ndev->stats.rx_frame_errors++;
86a74ff2 1478 if (desc_status & RD_RFS3)
bb7d92e3 1479 ndev->stats.rx_length_errors++;
86a74ff2 1480 if (desc_status & RD_RFS4)
bb7d92e3 1481 ndev->stats.rx_length_errors++;
86a74ff2 1482 if (desc_status & RD_RFS6)
bb7d92e3 1483 ndev->stats.rx_missed_errors++;
86a74ff2 1484 if (desc_status & RD_RFS10)
bb7d92e3 1485 ndev->stats.rx_over_errors++;
86a74ff2 1486 } else {
380af9e3
YS		 1487 if (!mdp->cd->hw_swap)
1488 sh_eth_soft_swap(
1489 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1490 pkt_len + 2);
86a74ff2
NI		 1491 skb = mdp->rx_skbuff[entry];
1492 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 1493 if (mdp->cd->rpadir)
1494 skb_reserve(skb, NET_IP_ALIGN);
52b9fa36
BH		 1495 dma_unmap_single(&ndev->dev, rxdesc->addr,
1496 ALIGN(mdp->rx_buf_sz, 16),
1497 DMA_FROM_DEVICE);
86a74ff2
NI		 1498 skb_put(skb, pkt_len);
1499 skb->protocol = eth_type_trans(skb, ndev);
a8e9fd0f 1500 netif_receive_skb(skb);
bb7d92e3
ED		 1501 ndev->stats.rx_packets++;
1502 ndev->stats.rx_bytes += pkt_len;
86a74ff2 1503 }
525b8075 1504 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
862df497 1505 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 1506 }
1507
1508 /* Refill the Rx ring buffers. */
1509 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
525b8075 1510 entry = mdp->dirty_rx % mdp->num_rx_ring;
86a74ff2 1511 rxdesc = &mdp->rx_ring[entry];
b0ca2a21 1512 /* The size of the buffer is 16 byte boundary. */
0029d64a 1513 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21 1514
86a74ff2 1515 if (mdp->rx_skbuff[entry] == NULL) {
4d6a949c 1516 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1517 if (skb == NULL)
1518 break; /* Better luck next round. */
380af9e3 1519 sh_eth_set_receive_align(skb);
52b9fa36
BH		 1520 dma_addr = dma_map_single(&ndev->dev, skb->data,
1521 rxdesc->buffer_length,
1522 DMA_FROM_DEVICE);
1523 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1524 kfree_skb(skb);
1525 break;
1526 }
1527 mdp->rx_skbuff[entry] = skb;
380af9e3 1528
bc8acf2c 1529 skb_checksum_none_assert(skb);
52b9fa36 1530 rxdesc->addr = dma_addr;
86a74ff2 1531 }
7d7355f5 1532 wmb(); /* RACT bit must be set after all the above writes */
525b8075 1533 if (entry >= mdp->num_rx_ring - 1)
86a74ff2 1534 rxdesc->status |=
71557a37 1535 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
86a74ff2
NI		 1536 else
1537 rxdesc->status |=
71557a37 1538 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 1539 }
1540
1541 /* Restart Rx engine if stopped. */
1542 /* If we don't need to check status, don't. -KDU */
79fba9f5 1543 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
a18e08bd 1544 /* fix the values for the next receiving if RDE is set */
6ded2865 1545 if (intr_status & EESR_RDE && mdp->reg_offset[RDFAR] != 0) {
128296fc
SS		 1546 u32 count = (sh_eth_read(ndev, RDFAR) -
1547 sh_eth_read(ndev, RDLAR)) >> 4;
1548
1549 mdp->cur_rx = count;
1550 mdp->dirty_rx = count;
1551 }
4a55530f 1552 sh_eth_write(ndev, EDRRR_R, EDRRR);
79fba9f5 1553 }
86a74ff2 1554
319cd520
MK		 1555 *quota -= limit - boguscnt - 1;
1556
4f809cea 1557 return *quota <= 0;
86a74ff2
NI		 1558}
1559
4a55530f 1560static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 1561{
1562 /* disable tx and rx */
4a55530f
YS		 1563 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1564 ~(ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1565}
1566
4a55530f 1567static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 1568{
1569 /* enable tx and rx */
4a55530f
YS		 1570 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1571 (ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1572}
1573
86a74ff2 1574/* error control function */
0799c2d6 1575static void sh_eth_error(struct net_device *ndev, u32 intr_status)
86a74ff2
NI		 1576{
1577 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1578 u32 felic_stat;
380af9e3
YS		 1579 u32 link_stat;
1580 u32 mask;
86a74ff2
NI		 1581
1582 if (intr_status & EESR_ECI) {
4a55530f
YS		 1583 felic_stat = sh_eth_read(ndev, ECSR);
1584 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
86a74ff2 1585 if (felic_stat & ECSR_ICD)
bb7d92e3 1586 ndev->stats.tx_carrier_errors++;
86a74ff2
NI		 1587 if (felic_stat & ECSR_LCHNG) {
1588 /* Link Changed */
4923576b 1589 if (mdp->cd->no_psr || mdp->no_ether_link) {
1e1b812b 1590 goto ignore_link;
380af9e3 1591 } else {
4a55530f 1592 link_stat = (sh_eth_read(ndev, PSR));
4923576b
YS		 1593 if (mdp->ether_link_active_low)
1594 link_stat = ~link_stat;
380af9e3 1595 }
128296fc 1596 if (!(link_stat & PHY_ST_LINK)) {
4a55530f 1597 sh_eth_rcv_snd_disable(ndev);
128296fc 1598 } else {
86a74ff2 1599 /* Link Up */
4a55530f 1600 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
128296fc
SS		 1601 ~DMAC_M_ECI, EESIPR);
1602 /* clear int */
4a55530f 1603 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
128296fc 1604 ECSR);
4a55530f 1605 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
128296fc 1606 DMAC_M_ECI, EESIPR);
86a74ff2 1607 /* enable tx and rx */
4a55530f 1608 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1609 }
1610 }
1611 }
1612
1e1b812b 1613ignore_link:
86a74ff2 1614 if (intr_status & EESR_TWB) {
4eb313a7
SS		 1615 /* Unused write back interrupt */
1616 if (intr_status & EESR_TABT) { /* Transmit Abort int */
bb7d92e3 1617 ndev->stats.tx_aborted_errors++;
8d5009f6 1618 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
4eb313a7 1619 }
86a74ff2
NI		 1620 }
1621
1622 if (intr_status & EESR_RABT) {
1623 /* Receive Abort int */
1624 if (intr_status & EESR_RFRMER) {
1625 /* Receive Frame Overflow int */
bb7d92e3 1626 ndev->stats.rx_frame_errors++;
86a74ff2
NI		 1627 }
1628 }
380af9e3 1629
dc19e4e5
NI		 1630 if (intr_status & EESR_TDE) {
1631 /* Transmit Descriptor Empty int */
bb7d92e3 1632 ndev->stats.tx_fifo_errors++;
8d5009f6 1633 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
dc19e4e5
NI		 1634 }
1635
1636 if (intr_status & EESR_TFE) {
1637 /* FIFO under flow */
bb7d92e3 1638 ndev->stats.tx_fifo_errors++;
8d5009f6 1639 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1640 }
1641
1642 if (intr_status & EESR_RDE) {
1643 /* Receive Descriptor Empty int */
bb7d92e3 1644 ndev->stats.rx_over_errors++;
86a74ff2 1645 }
dc19e4e5 1646
86a74ff2
NI		 1647 if (intr_status & EESR_RFE) {
1648 /* Receive FIFO Overflow int */
bb7d92e3 1649 ndev->stats.rx_fifo_errors++;
dc19e4e5
NI		 1650 }
1651
1652 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1653 /* Address Error */
bb7d92e3 1654 ndev->stats.tx_fifo_errors++;
8d5009f6 1655 netif_err(mdp, tx_err, ndev, "Address Error\n");
86a74ff2 1656 }
380af9e3
YS		 1657
1658 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1659 if (mdp->cd->no_ade)
1660 mask &= ~EESR_ADE;
1661 if (intr_status & mask) {
86a74ff2 1662 /* Tx error */
4a55530f 1663 u32 edtrr = sh_eth_read(ndev, EDTRR);
090d560f 1664
86a74ff2 1665 /* dmesg */
da246855
SS		 1666 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1667 intr_status, mdp->cur_tx, mdp->dirty_tx,
1668 (u32)ndev->state, edtrr);
86a74ff2
NI		 1669 /* dirty buffer free */
1670 sh_eth_txfree(ndev);
1671
1672 /* SH7712 BUG */
c5ed5368 1673 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
86a74ff2 1674 /* tx dma start */
c5ed5368 1675 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
86a74ff2
NI		 1676 }
1677 /* wakeup */
1678 netif_wake_queue(ndev);
1679 }
1680}
1681
1682static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1683{
1684 struct net_device *ndev = netdev;
1685 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1686 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1687 irqreturn_t ret = IRQ_NONE;
0799c2d6 1688 u32 intr_status, intr_enable;
86a74ff2 1689
86a74ff2
NI		 1690 spin_lock(&mdp->lock);
1691
3893b273 1692 /* Get interrupt status */
4a55530f 1693 intr_status = sh_eth_read(ndev, EESR);
3893b273
SS		 1694 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1695 * enabled since it's the one that comes thru regardless of the mask,
1696 * and we need to fully handle it in sh_eth_error() in order to quench
1697 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1698 */
3719109d
SS		 1699 intr_enable = sh_eth_read(ndev, EESIPR);
1700 intr_status &= intr_enable | DMAC_M_ECI;
1701 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
0e0fde3c 1702 ret = IRQ_HANDLED;
3719109d 1703 else
283e38db
BH		 1704 goto out;
1705
1706 if (!likely(mdp->irq_enabled)) {
1707 sh_eth_write(ndev, 0, EESIPR);
1708 goto out;
1709 }
86a74ff2 1710
3719109d
SS		 1711 if (intr_status & EESR_RX_CHECK) {
1712 if (napi_schedule_prep(&mdp->napi)) {
1713 /* Mask Rx interrupts */
1714 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1715 EESIPR);
1716 __napi_schedule(&mdp->napi);
1717 } else {
da246855 1718 netdev_warn(ndev,
0799c2d6 1719 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
da246855 1720 intr_status, intr_enable);
3719109d
SS		 1721 }
1722 }
86a74ff2 1723
b0ca2a21 1724 /* Tx Check */
380af9e3 1725 if (intr_status & cd->tx_check) {
3719109d
SS		 1726 /* Clear Tx interrupts */
1727 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1728
86a74ff2
NI		 1729 sh_eth_txfree(ndev);
1730 netif_wake_queue(ndev);
1731 }
1732
3719109d
SS		 1733 if (intr_status & cd->eesr_err_check) {
1734 /* Clear error interrupts */
1735 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1736
86a74ff2 1737 sh_eth_error(ndev, intr_status);
3719109d 1738 }
86a74ff2 1739
283e38db 1740out:
86a74ff2
NI		 1741 spin_unlock(&mdp->lock);
1742
0e0fde3c 1743 return ret;
86a74ff2
NI		 1744}
1745
3719109d
SS		 1746static int sh_eth_poll(struct napi_struct *napi, int budget)
1747{
1748 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1749 napi);
1750 struct net_device *ndev = napi->dev;
1751 int quota = budget;
0799c2d6 1752 u32 intr_status;
3719109d
SS		 1753
1754 for (;;) {
1755 intr_status = sh_eth_read(ndev, EESR);
1756 if (!(intr_status & EESR_RX_CHECK))
1757 break;
1758 /* Clear Rx interrupts */
1759 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1760
1761 if (sh_eth_rx(ndev, intr_status, &quota))
1762 goto out;
1763 }
1764
1765 napi_complete(napi);
1766
1767 /* Reenable Rx interrupts */
283e38db
BH		 1768 if (mdp->irq_enabled)
1769 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
3719109d
SS		 1770out:
1771 return budget - quota;
1772}
1773
86a74ff2
NI		 1774/* PHY state control function */
1775static void sh_eth_adjust_link(struct net_device *ndev)
1776{
1777 struct sh_eth_private *mdp = netdev_priv(ndev);
1778 struct phy_device *phydev = mdp->phydev;
86a74ff2
NI		 1779 int new_state = 0;
1780
3340d2aa 1781 if (phydev->link) {
86a74ff2
NI		 1782 if (phydev->duplex != mdp->duplex) {
1783 new_state = 1;
1784 mdp->duplex = phydev->duplex;
380af9e3
YS		 1785 if (mdp->cd->set_duplex)
1786 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1787 }
1788
1789 if (phydev->speed != mdp->speed) {
1790 new_state = 1;
1791 mdp->speed = phydev->speed;
380af9e3
YS		 1792 if (mdp->cd->set_rate)
1793 mdp->cd->set_rate(ndev);
86a74ff2 1794 }
3340d2aa 1795 if (!mdp->link) {
91a56152 1796 sh_eth_write(ndev,
128296fc
SS		 1797 sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1798 ECMR);
86a74ff2
NI		 1799 new_state = 1;
1800 mdp->link = phydev->link;
1e1b812b
SS		 1801 if (mdp->cd->no_psr || mdp->no_ether_link)
1802 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1803 }
1804 } else if (mdp->link) {
1805 new_state = 1;
3340d2aa 1806 mdp->link = 0;
86a74ff2
NI		 1807 mdp->speed = 0;
1808 mdp->duplex = -1;
1e1b812b
SS		 1809 if (mdp->cd->no_psr || mdp->no_ether_link)
1810 sh_eth_rcv_snd_disable(ndev);
86a74ff2
NI		 1811 }
1812
dc19e4e5 1813 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1814 phy_print_status(phydev);
1815}
1816
1817/* PHY init function */
1818static int sh_eth_phy_init(struct net_device *ndev)
1819{
702eca02 1820 struct device_node *np = ndev->dev.parent->of_node;
86a74ff2 1821 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1822 struct phy_device *phydev = NULL;
1823
3340d2aa 1824 mdp->link = 0;
86a74ff2
NI		 1825 mdp->speed = 0;
1826 mdp->duplex = -1;
1827
1828 /* Try connect to PHY */
702eca02
BD		 1829 if (np) {
1830 struct device_node *pn;
1831
1832 pn = of_parse_phandle(np, "phy-handle", 0);
1833 phydev = of_phy_connect(ndev, pn,
1834 sh_eth_adjust_link, 0,
1835 mdp->phy_interface);
1836
1837 if (!phydev)
1838 phydev = ERR_PTR(-ENOENT);
1839 } else {
1840 char phy_id[MII_BUS_ID_SIZE + 3];
1841
1842 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1843 mdp->mii_bus->id, mdp->phy_id);
1844
1845 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1846 mdp->phy_interface);
1847 }
1848
86a74ff2 1849 if (IS_ERR(phydev)) {
da246855 1850 netdev_err(ndev, "failed to connect PHY\n");
86a74ff2
NI		 1851 return PTR_ERR(phydev);
1852 }
380af9e3 1853
da246855
SS		 1854 netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
1855 phydev->addr, phydev->irq, phydev->drv->name);
86a74ff2
NI		 1856
1857 mdp->phydev = phydev;
1858
1859 return 0;
1860}
1861
1862/* PHY control start function */
1863static int sh_eth_phy_start(struct net_device *ndev)
1864{
1865 struct sh_eth_private *mdp = netdev_priv(ndev);
1866 int ret;
1867
1868 ret = sh_eth_phy_init(ndev);
1869 if (ret)
1870 return ret;
1871
86a74ff2
NI		 1872 phy_start(mdp->phydev);
1873
1874 return 0;
1875}
1876
dc19e4e5 1877static int sh_eth_get_settings(struct net_device *ndev,
128296fc 1878 struct ethtool_cmd *ecmd)
dc19e4e5
NI		 1879{
1880 struct sh_eth_private *mdp = netdev_priv(ndev);
1881 unsigned long flags;
1882 int ret;
1883
4f9dce23
BH		 1884 if (!mdp->phydev)
1885 return -ENODEV;
1886
dc19e4e5
NI		 1887 spin_lock_irqsave(&mdp->lock, flags);
1888 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1889 spin_unlock_irqrestore(&mdp->lock, flags);
1890
1891 return ret;
1892}
1893
1894static int sh_eth_set_settings(struct net_device *ndev,
128296fc 1895 struct ethtool_cmd *ecmd)
dc19e4e5
NI		 1896{
1897 struct sh_eth_private *mdp = netdev_priv(ndev);
1898 unsigned long flags;
1899 int ret;
dc19e4e5 1900
4f9dce23
BH		 1901 if (!mdp->phydev)
1902 return -ENODEV;
1903
dc19e4e5
NI		 1904 spin_lock_irqsave(&mdp->lock, flags);
1905
1906 /* disable tx and rx */
4a55530f 1907 sh_eth_rcv_snd_disable(ndev);
dc19e4e5
NI		 1908
1909 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1910 if (ret)
1911 goto error_exit;
1912
1913 if (ecmd->duplex == DUPLEX_FULL)
1914 mdp->duplex = 1;
1915 else
1916 mdp->duplex = 0;
1917
1918 if (mdp->cd->set_duplex)
1919 mdp->cd->set_duplex(ndev);
1920
1921error_exit:
1922 mdelay(1);
1923
1924 /* enable tx and rx */
4a55530f 1925 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 1926
1927 spin_unlock_irqrestore(&mdp->lock, flags);
1928
1929 return ret;
1930}
1931
1932static int sh_eth_nway_reset(struct net_device *ndev)
1933{
1934 struct sh_eth_private *mdp = netdev_priv(ndev);
1935 unsigned long flags;
1936 int ret;
1937
4f9dce23
BH		 1938 if (!mdp->phydev)
1939 return -ENODEV;
1940
dc19e4e5
NI		 1941 spin_lock_irqsave(&mdp->lock, flags);
1942 ret = phy_start_aneg(mdp->phydev);
1943 spin_unlock_irqrestore(&mdp->lock, flags);
1944
1945 return ret;
1946}
1947
1948static u32 sh_eth_get_msglevel(struct net_device *ndev)
1949{
1950 struct sh_eth_private *mdp = netdev_priv(ndev);
1951 return mdp->msg_enable;
1952}
1953
1954static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1955{
1956 struct sh_eth_private *mdp = netdev_priv(ndev);
1957 mdp->msg_enable = value;
1958}
1959
1960static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1961 "rx_current", "tx_current",
1962 "rx_dirty", "tx_dirty",
1963};
1964#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1965
1966static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1967{
1968 switch (sset) {
1969 case ETH_SS_STATS:
1970 return SH_ETH_STATS_LEN;
1971 default:
1972 return -EOPNOTSUPP;
1973 }
1974}
1975
1976static void sh_eth_get_ethtool_stats(struct net_device *ndev,
128296fc 1977 struct ethtool_stats *stats, u64 *data)
dc19e4e5
NI		 1978{
1979 struct sh_eth_private *mdp = netdev_priv(ndev);
1980 int i = 0;
1981
1982 /* device-specific stats */
1983 data[i++] = mdp->cur_rx;
1984 data[i++] = mdp->cur_tx;
1985 data[i++] = mdp->dirty_rx;
1986 data[i++] = mdp->dirty_tx;
1987}
1988
1989static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1990{
1991 switch (stringset) {
1992 case ETH_SS_STATS:
1993 memcpy(data, *sh_eth_gstrings_stats,
128296fc 1994 sizeof(sh_eth_gstrings_stats));
dc19e4e5
NI		 1995 break;
1996 }
1997}
1998
525b8075
YS		 1999static void sh_eth_get_ringparam(struct net_device *ndev,
2000 struct ethtool_ringparam *ring)
2001{
2002 struct sh_eth_private *mdp = netdev_priv(ndev);
2003
2004 ring->rx_max_pending = RX_RING_MAX;
2005 ring->tx_max_pending = TX_RING_MAX;
2006 ring->rx_pending = mdp->num_rx_ring;
2007 ring->tx_pending = mdp->num_tx_ring;
2008}
2009
2010static int sh_eth_set_ringparam(struct net_device *ndev,
2011 struct ethtool_ringparam *ring)
2012{
2013 struct sh_eth_private *mdp = netdev_priv(ndev);
2014 int ret;
2015
2016 if (ring->tx_pending > TX_RING_MAX ||
2017 ring->rx_pending > RX_RING_MAX ||
2018 ring->tx_pending < TX_RING_MIN ||
2019 ring->rx_pending < RX_RING_MIN)
2020 return -EINVAL;
2021 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2022 return -EINVAL;
2023
2024 if (netif_running(ndev)) {
bd888916 2025 netif_device_detach(ndev);
525b8075 2026 netif_tx_disable(ndev);
283e38db
BH		 2027
2028 /* Serialise with the interrupt handler and NAPI, then
2029 * disable interrupts. We have to clear the
2030 * irq_enabled flag first to ensure that interrupts
2031 * won't be re-enabled.
2032 */
2033 mdp->irq_enabled = false;
525b8075 2034 synchronize_irq(ndev->irq);
283e38db 2035 napi_synchronize(&mdp->napi);
525b8075 2036 sh_eth_write(ndev, 0x0000, EESIPR);
525b8075 2037
740c7f31 2038 sh_eth_dev_exit(ndev);
525b8075 2039
084236d8
BH		 2040 /* Free all the skbuffs in the Rx queue. */
2041 sh_eth_ring_free(ndev);
2042 /* Free DMA buffer */
2043 sh_eth_free_dma_buffer(mdp);
2044 }
525b8075
YS		 2045
2046 /* Set new parameters */
2047 mdp->num_rx_ring = ring->rx_pending;
2048 mdp->num_tx_ring = ring->tx_pending;
2049
525b8075 2050 if (netif_running(ndev)) {
084236d8
BH		 2051 ret = sh_eth_ring_init(ndev);
2052 if (ret < 0) {
2053 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2054 __func__);
2055 return ret;
2056 }
2057 ret = sh_eth_dev_init(ndev, false);
2058 if (ret < 0) {
2059 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2060 __func__);
2061 return ret;
2062 }
2063
283e38db 2064 mdp->irq_enabled = true;
525b8075
YS		 2065 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2066 /* Setting the Rx mode will start the Rx process. */
2067 sh_eth_write(ndev, EDRRR_R, EDRRR);
bd888916 2068 netif_device_attach(ndev);
525b8075
YS		 2069 }
2070
2071 return 0;
2072}
2073
9b07be4b 2074static const struct ethtool_ops sh_eth_ethtool_ops = {
dc19e4e5
NI		 2075 .get_settings = sh_eth_get_settings,
2076 .set_settings = sh_eth_set_settings,
9b07be4b 2077 .nway_reset = sh_eth_nway_reset,
dc19e4e5
NI		 2078 .get_msglevel = sh_eth_get_msglevel,
2079 .set_msglevel = sh_eth_set_msglevel,
9b07be4b 2080 .get_link = ethtool_op_get_link,
dc19e4e5
NI		 2081 .get_strings = sh_eth_get_strings,
2082 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2083 .get_sset_count = sh_eth_get_sset_count,
525b8075
YS		 2084 .get_ringparam = sh_eth_get_ringparam,
2085 .set_ringparam = sh_eth_set_ringparam,
dc19e4e5
NI		 2086};
2087
86a74ff2
NI		 2088/* network device open function */
2089static int sh_eth_open(struct net_device *ndev)
2090{
2091 int ret = 0;
2092 struct sh_eth_private *mdp = netdev_priv(ndev);
2093
bcd5149d
MD		 2094 pm_runtime_get_sync(&mdp->pdev->dev);
2095
d2779e99
SS		 2096 napi_enable(&mdp->napi);
2097
a0607fd3 2098 ret = request_irq(ndev->irq, sh_eth_interrupt,
5b3dfd13 2099 mdp->cd->irq_flags, ndev->name, ndev);
86a74ff2 2100 if (ret) {
da246855 2101 netdev_err(ndev, "Can not assign IRQ number\n");
d2779e99 2102 goto out_napi_off;
86a74ff2
NI		 2103 }
2104
2105 /* Descriptor set */
2106 ret = sh_eth_ring_init(ndev);
2107 if (ret)
2108 goto out_free_irq;
2109
2110 /* device init */
525b8075 2111 ret = sh_eth_dev_init(ndev, true);
86a74ff2
NI		 2112 if (ret)
2113 goto out_free_irq;
2114
2115 /* PHY control start*/
2116 ret = sh_eth_phy_start(ndev);
2117 if (ret)
2118 goto out_free_irq;
2119
7fa2955f
MK		 2120 mdp->is_opened = 1;
2121
86a74ff2
NI		 2122 return ret;
2123
2124out_free_irq:
2125 free_irq(ndev->irq, ndev);
d2779e99
SS		 2126out_napi_off:
2127 napi_disable(&mdp->napi);
bcd5149d 2128 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 2129 return ret;
2130}
2131
2132/* Timeout function */
2133static void sh_eth_tx_timeout(struct net_device *ndev)
2134{
2135 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2136 struct sh_eth_rxdesc *rxdesc;
2137 int i;
2138
2139 netif_stop_queue(ndev);
2140
8d5009f6
SS		 2141 netif_err(mdp, timer, ndev,
2142 "transmit timed out, status %8.8x, resetting...\n",
0799c2d6 2143 sh_eth_read(ndev, EESR));
86a74ff2
NI		 2144
2145 /* tx_errors count up */
bb7d92e3 2146 ndev->stats.tx_errors++;
86a74ff2 2147
86a74ff2 2148 /* Free all the skbuffs in the Rx queue. */
525b8075 2149 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 2150 rxdesc = &mdp->rx_ring[i];
2151 rxdesc->status = 0;
2152 rxdesc->addr = 0xBADF00D0;
179d80af 2153 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 2154 mdp->rx_skbuff[i] = NULL;
2155 }
525b8075 2156 for (i = 0; i < mdp->num_tx_ring; i++) {
179d80af 2157 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 2158 mdp->tx_skbuff[i] = NULL;
2159 }
2160
2161 /* device init */
525b8075 2162 sh_eth_dev_init(ndev, true);
86a74ff2
NI		 2163}
2164
2165/* Packet transmit function */
2166static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2167{
2168 struct sh_eth_private *mdp = netdev_priv(ndev);
2169 struct sh_eth_txdesc *txdesc;
2170 u32 entry;
fb5e2f9b 2171 unsigned long flags;
86a74ff2
NI		 2172
2173 spin_lock_irqsave(&mdp->lock, flags);
525b8075 2174 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
86a74ff2 2175 if (!sh_eth_txfree(ndev)) {
8d5009f6 2176 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
86a74ff2
NI		 2177 netif_stop_queue(ndev);
2178 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 2179 return NETDEV_TX_BUSY;
86a74ff2
NI		 2180 }
2181 }
2182 spin_unlock_irqrestore(&mdp->lock, flags);
2183
eebfb643
BH		 2184 if (skb_padto(skb, ETH_ZLEN))
2185 return NETDEV_TX_OK;
2186
525b8075 2187 entry = mdp->cur_tx % mdp->num_tx_ring;
86a74ff2
NI		 2188 mdp->tx_skbuff[entry] = skb;
2189 txdesc = &mdp->tx_ring[entry];
86a74ff2 2190 /* soft swap. */
380af9e3
YS		 2191 if (!mdp->cd->hw_swap)
2192 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2193 skb->len + 2);
31fcb99d
YS		 2194 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2195 DMA_TO_DEVICE);
aa3933b8
BH		 2196 if (dma_mapping_error(&ndev->dev, txdesc->addr)) {
2197 kfree_skb(skb);
2198 return NETDEV_TX_OK;
2199 }
eebfb643 2200 txdesc->buffer_length = skb->len;
86a74ff2 2201
7d7355f5 2202 wmb(); /* TACT bit must be set after all the above writes */
525b8075 2203 if (entry >= mdp->num_tx_ring - 1)
71557a37 2204 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
86a74ff2 2205 else
71557a37 2206 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
86a74ff2
NI		 2207
2208 mdp->cur_tx++;
2209
c5ed5368
YS		 2210 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2211 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
b0ca2a21 2212
6ed10654 2213 return NETDEV_TX_OK;
86a74ff2
NI		 2214}
2215
7fa2955f
MK		 2216static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2217{
2218 struct sh_eth_private *mdp = netdev_priv(ndev);
2219
2220 if (sh_eth_is_rz_fast_ether(mdp))
2221 return &ndev->stats;
2222
2223 if (!mdp->is_opened)
2224 return &ndev->stats;
2225
2226 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
2227 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
2228 ndev->stats.collisions += sh_eth_read(ndev, CDCR);
2229 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
2230 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
2231 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
2232
2233 if (sh_eth_is_gether(mdp)) {
2234 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
2235 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
2236 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
2237 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
2238 } else {
2239 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
2240 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
2241 }
2242
2243 return &ndev->stats;
2244}
2245
86a74ff2
NI		 2246/* device close function */
2247static int sh_eth_close(struct net_device *ndev)
2248{
2249 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2250
2251 netif_stop_queue(ndev);
2252
283e38db
BH		 2253 /* Serialise with the interrupt handler and NAPI, then disable
2254 * interrupts. We have to clear the irq_enabled flag first to
2255 * ensure that interrupts won't be re-enabled.
2256 */
2257 mdp->irq_enabled = false;
2258 synchronize_irq(ndev->irq);
2259 napi_disable(&mdp->napi);
4a55530f 2260 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2 2261
740c7f31 2262 sh_eth_dev_exit(ndev);
86a74ff2
NI		 2263
2264 /* PHY Disconnect */
2265 if (mdp->phydev) {
2266 phy_stop(mdp->phydev);
2267 phy_disconnect(mdp->phydev);
4f9dce23 2268 mdp->phydev = NULL;
86a74ff2
NI		 2269 }
2270
2271 free_irq(ndev->irq, ndev);
2272
86a74ff2
NI		 2273 /* Free all the skbuffs in the Rx queue. */
2274 sh_eth_ring_free(ndev);
2275
2276 /* free DMA buffer */
91c77550 2277 sh_eth_free_dma_buffer(mdp);
86a74ff2 2278
bcd5149d
MD		 2279 pm_runtime_put_sync(&mdp->pdev->dev);
2280
7fa2955f 2281 mdp->is_opened = 0;
bcd5149d 2282
7fa2955f 2283 return 0;
86a74ff2
NI		 2284}
2285
bb7d92e3 2286/* ioctl to device function */
128296fc 2287static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
86a74ff2
NI		 2288{
2289 struct sh_eth_private *mdp = netdev_priv(ndev);
2290 struct phy_device *phydev = mdp->phydev;
2291
2292 if (!netif_running(ndev))
2293 return -EINVAL;
2294
2295 if (!phydev)
2296 return -ENODEV;
2297
28b04113 2298 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 2299}
2300
6743fe6d
YS		 2301/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2302static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2303 int entry)
2304{
2305 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2306}
2307
2308static u32 sh_eth_tsu_get_post_mask(int entry)
2309{
2310 return 0x0f << (28 - ((entry % 8) * 4));
2311}
2312
2313static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2314{
2315 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2316}
2317
2318static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2319 int entry)
2320{
2321 struct sh_eth_private *mdp = netdev_priv(ndev);
2322 u32 tmp;
2323 void *reg_offset;
2324
2325 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2326 tmp = ioread32(reg_offset);
2327 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2328}
2329
2330static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2331 int entry)
2332{
2333 struct sh_eth_private *mdp = netdev_priv(ndev);
2334 u32 post_mask, ref_mask, tmp;
2335 void *reg_offset;
2336
2337 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2338 post_mask = sh_eth_tsu_get_post_mask(entry);
2339 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2340
2341 tmp = ioread32(reg_offset);
2342 iowrite32(tmp & ~post_mask, reg_offset);
2343
2344 /* If other port enables, the function returns "true" */
2345 return tmp & ref_mask;
2346}
2347
2348static int sh_eth_tsu_busy(struct net_device *ndev)
2349{
2350 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2351 struct sh_eth_private *mdp = netdev_priv(ndev);
2352
2353 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2354 udelay(10);
2355 timeout--;
2356 if (timeout <= 0) {
da246855 2357 netdev_err(ndev, "%s: timeout\n", __func__);
6743fe6d
YS		 2358 return -ETIMEDOUT;
2359 }
2360 }
2361
2362 return 0;
2363}
2364
2365static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2366 const u8 *addr)
2367{
2368 u32 val;
2369
2370 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2371 iowrite32(val, reg);
2372 if (sh_eth_tsu_busy(ndev) < 0)
2373 return -EBUSY;
2374
2375 val = addr[4] << 8 | addr[5];
2376 iowrite32(val, reg + 4);
2377 if (sh_eth_tsu_busy(ndev) < 0)
2378 return -EBUSY;
2379
2380 return 0;
2381}
2382
2383static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2384{
2385 u32 val;
2386
2387 val = ioread32(reg);
2388 addr[0] = (val >> 24) & 0xff;
2389 addr[1] = (val >> 16) & 0xff;
2390 addr[2] = (val >> 8) & 0xff;
2391 addr[3] = val & 0xff;
2392 val = ioread32(reg + 4);
2393 addr[4] = (val >> 8) & 0xff;
2394 addr[5] = val & 0xff;
2395}
2396
2397
2398static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2399{
2400 struct sh_eth_private *mdp = netdev_priv(ndev);
2401 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2402 int i;
2403 u8 c_addr[ETH_ALEN];
2404
2405 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2406 sh_eth_tsu_read_entry(reg_offset, c_addr);
c4bde29c 2407 if (ether_addr_equal(addr, c_addr))
6743fe6d
YS		 2408 return i;
2409 }
2410
2411 return -ENOENT;
2412}
2413
2414static int sh_eth_tsu_find_empty(struct net_device *ndev)
2415{
2416 u8 blank[ETH_ALEN];
2417 int entry;
2418
2419 memset(blank, 0, sizeof(blank));
2420 entry = sh_eth_tsu_find_entry(ndev, blank);
2421 return (entry < 0) ? -ENOMEM : entry;
2422}
2423
2424static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2425 int entry)
2426{
2427 struct sh_eth_private *mdp = netdev_priv(ndev);
2428 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2429 int ret;
2430 u8 blank[ETH_ALEN];
2431
2432 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2433 ~(1 << (31 - entry)), TSU_TEN);
2434
2435 memset(blank, 0, sizeof(blank));
2436 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2437 if (ret < 0)
2438 return ret;
2439 return 0;
2440}
2441
2442static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2443{
2444 struct sh_eth_private *mdp = netdev_priv(ndev);
2445 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2446 int i, ret;
2447
2448 if (!mdp->cd->tsu)
2449 return 0;
2450
2451 i = sh_eth_tsu_find_entry(ndev, addr);
2452 if (i < 0) {
2453 /* No entry found, create one */
2454 i = sh_eth_tsu_find_empty(ndev);
2455 if (i < 0)
2456 return -ENOMEM;
2457 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2458 if (ret < 0)
2459 return ret;
2460
2461 /* Enable the entry */
2462 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2463 (1 << (31 - i)), TSU_TEN);
2464 }
2465
2466 /* Entry found or created, enable POST */
2467 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2468
2469 return 0;
2470}
2471
2472static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2473{
2474 struct sh_eth_private *mdp = netdev_priv(ndev);
2475 int i, ret;
2476
2477 if (!mdp->cd->tsu)
2478 return 0;
2479
2480 i = sh_eth_tsu_find_entry(ndev, addr);
2481 if (i) {
2482 /* Entry found */
2483 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2484 goto done;
2485
2486 /* Disable the entry if both ports was disabled */
2487 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2488 if (ret < 0)
2489 return ret;
2490 }
2491done:
2492 return 0;
2493}
2494
2495static int sh_eth_tsu_purge_all(struct net_device *ndev)
2496{
2497 struct sh_eth_private *mdp = netdev_priv(ndev);
2498 int i, ret;
2499
b37feed7 2500 if (!mdp->cd->tsu)
6743fe6d
YS		 2501 return 0;
2502
2503 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2504 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2505 continue;
2506
2507 /* Disable the entry if both ports was disabled */
2508 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2509 if (ret < 0)
2510 return ret;
2511 }
2512
2513 return 0;
2514}
2515
2516static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2517{
2518 struct sh_eth_private *mdp = netdev_priv(ndev);
2519 u8 addr[ETH_ALEN];
2520 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2521 int i;
2522
b37feed7 2523 if (!mdp->cd->tsu)
6743fe6d
YS		 2524 return;
2525
2526 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2527 sh_eth_tsu_read_entry(reg_offset, addr);
2528 if (is_multicast_ether_addr(addr))
2529 sh_eth_tsu_del_entry(ndev, addr);
2530 }
2531}
2532
b37feed7
BH		 2533/* Update promiscuous flag and multicast filter */
2534static void sh_eth_set_rx_mode(struct net_device *ndev)
86a74ff2 2535{
6743fe6d
YS		 2536 struct sh_eth_private *mdp = netdev_priv(ndev);
2537 u32 ecmr_bits;
2538 int mcast_all = 0;
2539 unsigned long flags;
2540
2541 spin_lock_irqsave(&mdp->lock, flags);
128296fc 2542 /* Initial condition is MCT = 1, PRM = 0.
6743fe6d
YS		 2543 * Depending on ndev->flags, set PRM or clear MCT
2544 */
b37feed7
BH		 2545 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2546 if (mdp->cd->tsu)
2547 ecmr_bits |= ECMR_MCT;
6743fe6d
YS		 2548
2549 if (!(ndev->flags & IFF_MULTICAST)) {
2550 sh_eth_tsu_purge_mcast(ndev);
2551 mcast_all = 1;
2552 }
2553 if (ndev->flags & IFF_ALLMULTI) {
2554 sh_eth_tsu_purge_mcast(ndev);
2555 ecmr_bits &= ~ECMR_MCT;
2556 mcast_all = 1;
2557 }
2558
86a74ff2 2559 if (ndev->flags & IFF_PROMISC) {
6743fe6d
YS		 2560 sh_eth_tsu_purge_all(ndev);
2561 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2562 } else if (mdp->cd->tsu) {
2563 struct netdev_hw_addr *ha;
2564 netdev_for_each_mc_addr(ha, ndev) {
2565 if (mcast_all && is_multicast_ether_addr(ha->addr))
2566 continue;
2567
2568 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2569 if (!mcast_all) {
2570 sh_eth_tsu_purge_mcast(ndev);
2571 ecmr_bits &= ~ECMR_MCT;
2572 mcast_all = 1;
2573 }
2574 }
2575 }
86a74ff2 2576 }
6743fe6d
YS		 2577
2578 /* update the ethernet mode */
2579 sh_eth_write(ndev, ecmr_bits, ECMR);
2580
2581 spin_unlock_irqrestore(&mdp->lock, flags);
86a74ff2 2582}
71cc7c37
YS		 2583
2584static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2585{
2586 if (!mdp->port)
2587 return TSU_VTAG0;
2588 else
2589 return TSU_VTAG1;
2590}
2591
80d5c368
PM		 2592static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2593 __be16 proto, u16 vid)
71cc7c37
YS		 2594{
2595 struct sh_eth_private *mdp = netdev_priv(ndev);
2596 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2597
2598 if (unlikely(!mdp->cd->tsu))
2599 return -EPERM;
2600
2601 /* No filtering if vid = 0 */
2602 if (!vid)
2603 return 0;
2604
2605 mdp->vlan_num_ids++;
2606
128296fc 2607 /* The controller has one VLAN tag HW filter. So, if the filter is
71cc7c37
YS		 2608 * already enabled, the driver disables it and the filte
2609 */
2610 if (mdp->vlan_num_ids > 1) {
2611 /* disable VLAN filter */
2612 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2613 return 0;
2614 }
2615
2616 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2617 vtag_reg_index);
2618
2619 return 0;
2620}
2621
80d5c368
PM		 2622static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2623 __be16 proto, u16 vid)
71cc7c37
YS		 2624{
2625 struct sh_eth_private *mdp = netdev_priv(ndev);
2626 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2627
2628 if (unlikely(!mdp->cd->tsu))
2629 return -EPERM;
2630
2631 /* No filtering if vid = 0 */
2632 if (!vid)
2633 return 0;
2634
2635 mdp->vlan_num_ids--;
2636 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2637
2638 return 0;
2639}
86a74ff2
NI		 2640
2641/* SuperH's TSU register init function */
4a55530f 2642static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 2643{
db893473
SH		 2644 if (sh_eth_is_rz_fast_ether(mdp)) {
2645 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2646 return;
2647 }
2648
4a55530f
YS		 2649 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2650 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2651 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2652 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2653 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2654 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2655 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2656 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2657 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2658 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
c5ed5368
YS		 2659 if (sh_eth_is_gether(mdp)) {
2660 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2661 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2662 } else {
2663 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2664 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2665 }
4a55530f
YS		 2666 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2667 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2668 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2669 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2670 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2671 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2672 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 2673}
2674
2675/* MDIO bus release function */
bd920ff5 2676static int sh_mdio_release(struct sh_eth_private *mdp)
86a74ff2 2677{
86a74ff2 2678 /* unregister mdio bus */
bd920ff5 2679 mdiobus_unregister(mdp->mii_bus);
86a74ff2
NI		 2680
2681 /* free bitbang info */
bd920ff5 2682 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2683
2684 return 0;
2685}
2686
2687/* MDIO bus init function */
bd920ff5 2688static int sh_mdio_init(struct sh_eth_private *mdp,
b3017e6a 2689 struct sh_eth_plat_data *pd)
86a74ff2
NI		 2690{
2691 int ret, i;
2692 struct bb_info *bitbang;
bd920ff5 2693 struct platform_device *pdev = mdp->pdev;
aa8d4225 2694 struct device *dev = &mdp->pdev->dev;
86a74ff2
NI		 2695
2696 /* create bit control struct for PHY */
aa8d4225 2697 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
f738a13d
LP		 2698 if (!bitbang)
2699 return -ENOMEM;
86a74ff2
NI		 2700
2701 /* bitbang init */
ae70644d 2702 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
b3017e6a 2703 bitbang->set_gate = pd->set_mdio_gate;
dfed5e7f
SS		 2704 bitbang->mdi_msk = PIR_MDI;
2705 bitbang->mdo_msk = PIR_MDO;
2706 bitbang->mmd_msk = PIR_MMD;
2707 bitbang->mdc_msk = PIR_MDC;
86a74ff2
NI		 2708 bitbang->ctrl.ops = &bb_ops;
2709
c2e07b3a 2710 /* MII controller setting */
86a74ff2 2711 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
f738a13d
LP		 2712 if (!mdp->mii_bus)
2713 return -ENOMEM;
86a74ff2
NI		 2714
2715 /* Hook up MII support for ethtool */
2716 mdp->mii_bus->name = "sh_mii";
a5bd6060 2717 mdp->mii_bus->parent = dev;
5278fb54 2718 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
bd920ff5 2719 pdev->name, pdev->id);
86a74ff2
NI		 2720
2721 /* PHY IRQ */
86b5d251
SS		 2722 mdp->mii_bus->irq = devm_kmalloc_array(dev, PHY_MAX_ADDR, sizeof(int),
2723 GFP_KERNEL);
86a74ff2
NI		 2724 if (!mdp->mii_bus->irq) {
2725 ret = -ENOMEM;
2726 goto out_free_bus;
2727 }
2728
bd920ff5
LP		 2729 /* register MDIO bus */
2730 if (dev->of_node) {
2731 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
702eca02
BD		 2732 } else {
2733 for (i = 0; i < PHY_MAX_ADDR; i++)
2734 mdp->mii_bus->irq[i] = PHY_POLL;
2735 if (pd->phy_irq > 0)
2736 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2737
2738 ret = mdiobus_register(mdp->mii_bus);
2739 }
2740
86a74ff2 2741 if (ret)
d5e07e69 2742 goto out_free_bus;
86a74ff2 2743
86a74ff2
NI		 2744 return 0;
2745
86a74ff2 2746out_free_bus:
298cf9be 2747 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2748 return ret;
2749}
2750
4a55530f
YS		 2751static const u16 *sh_eth_get_register_offset(int register_type)
2752{
2753 const u16 *reg_offset = NULL;
2754
2755 switch (register_type) {
2756 case SH_ETH_REG_GIGABIT:
2757 reg_offset = sh_eth_offset_gigabit;
2758 break;
db893473
SH		 2759 case SH_ETH_REG_FAST_RZ:
2760 reg_offset = sh_eth_offset_fast_rz;
2761 break;
a3f109bd
SS		 2762 case SH_ETH_REG_FAST_RCAR:
2763 reg_offset = sh_eth_offset_fast_rcar;
2764 break;
4a55530f
YS		 2765 case SH_ETH_REG_FAST_SH4:
2766 reg_offset = sh_eth_offset_fast_sh4;
2767 break;
2768 case SH_ETH_REG_FAST_SH3_SH2:
2769 reg_offset = sh_eth_offset_fast_sh3_sh2;
2770 break;
2771 default:
4a55530f
YS		 2772 break;
2773 }
2774
2775 return reg_offset;
2776}
2777
8f728d79 2778static const struct net_device_ops sh_eth_netdev_ops = {
ebf84eaa
AB		 2779 .ndo_open = sh_eth_open,
2780 .ndo_stop = sh_eth_close,
2781 .ndo_start_xmit = sh_eth_start_xmit,
2782 .ndo_get_stats = sh_eth_get_stats,
b37feed7 2783 .ndo_set_rx_mode = sh_eth_set_rx_mode,
ebf84eaa
AB		 2784 .ndo_tx_timeout = sh_eth_tx_timeout,
2785 .ndo_do_ioctl = sh_eth_do_ioctl,
2786 .ndo_validate_addr = eth_validate_addr,
2787 .ndo_set_mac_address = eth_mac_addr,
2788 .ndo_change_mtu = eth_change_mtu,
2789};
2790
8f728d79
SS		 2791static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2792 .ndo_open = sh_eth_open,
2793 .ndo_stop = sh_eth_close,
2794 .ndo_start_xmit = sh_eth_start_xmit,
2795 .ndo_get_stats = sh_eth_get_stats,
b37feed7 2796 .ndo_set_rx_mode = sh_eth_set_rx_mode,
8f728d79
SS		 2797 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2798 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2799 .ndo_tx_timeout = sh_eth_tx_timeout,
2800 .ndo_do_ioctl = sh_eth_do_ioctl,
2801 .ndo_validate_addr = eth_validate_addr,
2802 .ndo_set_mac_address = eth_mac_addr,
2803 .ndo_change_mtu = eth_change_mtu,
2804};
2805
b356e978
SS		 2806#ifdef CONFIG_OF
2807static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2808{
2809 struct device_node *np = dev->of_node;
2810 struct sh_eth_plat_data *pdata;
b356e978
SS		 2811 const char *mac_addr;
2812
2813 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2814 if (!pdata)
2815 return NULL;
2816
2817 pdata->phy_interface = of_get_phy_mode(np);
2818
b356e978
SS		 2819 mac_addr = of_get_mac_address(np);
2820 if (mac_addr)
2821 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2822
2823 pdata->no_ether_link =
2824 of_property_read_bool(np, "renesas,no-ether-link");
2825 pdata->ether_link_active_low =
2826 of_property_read_bool(np, "renesas,ether-link-active-low");
2827
2828 return pdata;
2829}
2830
2831static const struct of_device_id sh_eth_match_table[] = {
2832 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2833 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2834 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2835 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2836 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
9488e1e5 2837 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
0f76b9d8 2838 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
b356e978
SS		 2839 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2840 { }
2841};
2842MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2843#else
2844static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2845{
2846 return NULL;
2847}
2848#endif
2849
86a74ff2
NI		 2850static int sh_eth_drv_probe(struct platform_device *pdev)
2851{
9c38657c 2852 int ret, devno = 0;
86a74ff2
NI		 2853 struct resource *res;
2854 struct net_device *ndev = NULL;
ec0d7551 2855 struct sh_eth_private *mdp = NULL;
0b76b862 2856 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
afe391ad 2857 const struct platform_device_id *id = platform_get_device_id(pdev);
86a74ff2
NI		 2858
2859 /* get base addr */
2860 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
86a74ff2
NI		 2861
2862 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
f738a13d
LP		 2863 if (!ndev)
2864 return -ENOMEM;
86a74ff2 2865
b5893a08
BD		 2866 pm_runtime_enable(&pdev->dev);
2867 pm_runtime_get_sync(&pdev->dev);
2868
86a74ff2
NI		 2869 devno = pdev->id;
2870 if (devno < 0)
2871 devno = 0;
2872
2873 ndev->dma = -1;
cc3c080d 2874 ret = platform_get_irq(pdev, 0);
2875 if (ret < 0) {
86a74ff2
NI		 2876 ret = -ENODEV;
2877 goto out_release;
2878 }
cc3c080d 2879 ndev->irq = ret;
86a74ff2
NI		 2880
2881 SET_NETDEV_DEV(ndev, &pdev->dev);
2882
86a74ff2 2883 mdp = netdev_priv(ndev);
525b8075
YS		 2884 mdp->num_tx_ring = TX_RING_SIZE;
2885 mdp->num_rx_ring = RX_RING_SIZE;
d5e07e69
SS		 2886 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2887 if (IS_ERR(mdp->addr)) {
2888 ret = PTR_ERR(mdp->addr);
ae70644d
YS		 2889 goto out_release;
2890 }
2891
c960804f
VB		 2892 ndev->base_addr = res->start;
2893
86a74ff2 2894 spin_lock_init(&mdp->lock);
bcd5149d 2895 mdp->pdev = pdev;
86a74ff2 2896
b356e978
SS		 2897 if (pdev->dev.of_node)
2898 pd = sh_eth_parse_dt(&pdev->dev);
3b4c5cbf
SS		 2899 if (!pd) {
2900 dev_err(&pdev->dev, "no platform data\n");
2901 ret = -EINVAL;
2902 goto out_release;
2903 }
2904
86a74ff2 2905 /* get PHY ID */
71557a37 2906 mdp->phy_id = pd->phy;
e47c9052 2907 mdp->phy_interface = pd->phy_interface;
71557a37
YS		 2908 /* EDMAC endian */
2909 mdp->edmac_endian = pd->edmac_endian;
4923576b
YS		 2910 mdp->no_ether_link = pd->no_ether_link;
2911 mdp->ether_link_active_low = pd->ether_link_active_low;
86a74ff2 2912
380af9e3 2913 /* set cpu data */
b356e978
SS		 2914 if (id) {
2915 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
2916 } else {
2917 const struct of_device_id *match;
2918
2919 match = of_match_device(of_match_ptr(sh_eth_match_table),
2920 &pdev->dev);
2921 mdp->cd = (struct sh_eth_cpu_data *)match->data;
2922 }
a3153d8c 2923 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
264be2f5
SS		 2924 if (!mdp->reg_offset) {
2925 dev_err(&pdev->dev, "Unknown register type (%d)\n",
2926 mdp->cd->register_type);
2927 ret = -EINVAL;
2928 goto out_release;
2929 }
380af9e3
YS		 2930 sh_eth_set_default_cpu_data(mdp->cd);
2931
86a74ff2 2932 /* set function */
8f728d79
SS		 2933 if (mdp->cd->tsu)
2934 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2935 else
2936 ndev->netdev_ops = &sh_eth_netdev_ops;
7ad24ea4 2937 ndev->ethtool_ops = &sh_eth_ethtool_ops;
86a74ff2
NI		 2938 ndev->watchdog_timeo = TX_TIMEOUT;
2939
dc19e4e5
NI		 2940 /* debug message level */
2941 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 2942
2943 /* read and set MAC address */
748031f9 2944 read_mac_address(ndev, pd->mac_addr);
ff6e7228
SS		 2945 if (!is_valid_ether_addr(ndev->dev_addr)) {
2946 dev_warn(&pdev->dev,
2947 "no valid MAC address supplied, using a random one.\n");
2948 eth_hw_addr_random(ndev);
2949 }
86a74ff2 2950
6ba88021
YS		 2951 /* ioremap the TSU registers */
2952 if (mdp->cd->tsu) {
2953 struct resource *rtsu;
2954 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
d5e07e69
SS		 2955 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2956 if (IS_ERR(mdp->tsu_addr)) {
2957 ret = PTR_ERR(mdp->tsu_addr);
fc0c0900
SS		 2958 goto out_release;
2959 }
6743fe6d 2960 mdp->port = devno % 2;
f646968f 2961 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
6ba88021
YS		 2962 }
2963
150647fb
YS		 2964 /* initialize first or needed device */
2965 if (!devno || pd->needs_init) {
380af9e3
YS		 2966 if (mdp->cd->chip_reset)
2967 mdp->cd->chip_reset(ndev);
86a74ff2 2968
4986b996
YS		 2969 if (mdp->cd->tsu) {
2970 /* TSU init (Init only)*/
2971 sh_eth_tsu_init(mdp);
2972 }
86a74ff2
NI		 2973 }
2974
966d6dbb
HN		 2975 if (mdp->cd->rmiimode)
2976 sh_eth_write(ndev, 0x1, RMIIMODE);
2977
daacf03f
LP		 2978 /* MDIO bus init */
2979 ret = sh_mdio_init(mdp, pd);
2980 if (ret) {
2981 dev_err(&ndev->dev, "failed to initialise MDIO\n");
2982 goto out_release;
2983 }
2984
3719109d
SS		 2985 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
2986
86a74ff2
NI		 2987 /* network device register */
2988 ret = register_netdev(ndev);
2989 if (ret)
3719109d 2990 goto out_napi_del;
86a74ff2 2991
25985edc 2992 /* print device information */
f75f14ec
SS		 2993 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
2994 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2 2995
b5893a08 2996 pm_runtime_put(&pdev->dev);
86a74ff2
NI		 2997 platform_set_drvdata(pdev, ndev);
2998
2999 return ret;
3000
3719109d
SS		 3001out_napi_del:
3002 netif_napi_del(&mdp->napi);
daacf03f 3003 sh_mdio_release(mdp);
3719109d 3004
86a74ff2
NI		 3005out_release:
3006 /* net_dev free */
3007 if (ndev)
3008 free_netdev(ndev);
3009
b5893a08
BD		 3010 pm_runtime_put(&pdev->dev);
3011 pm_runtime_disable(&pdev->dev);
86a74ff2
NI		 3012 return ret;
3013}
3014
3015static int sh_eth_drv_remove(struct platform_device *pdev)
3016{
3017 struct net_device *ndev = platform_get_drvdata(pdev);
3719109d 3018 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 3019
86a74ff2 3020 unregister_netdev(ndev);
3719109d 3021 netif_napi_del(&mdp->napi);
daacf03f 3022 sh_mdio_release(mdp);
bcd5149d 3023 pm_runtime_disable(&pdev->dev);
86a74ff2 3024 free_netdev(ndev);
86a74ff2
NI		 3025
3026 return 0;
3027}
3028
540ad1b8 3029#ifdef CONFIG_PM
b71af046
MU		 3030#ifdef CONFIG_PM_SLEEP
3031static int sh_eth_suspend(struct device *dev)
3032{
3033 struct net_device *ndev = dev_get_drvdata(dev);
3034 int ret = 0;
3035
3036 if (netif_running(ndev)) {
3037 netif_device_detach(ndev);
3038 ret = sh_eth_close(ndev);
3039 }
3040
3041 return ret;
3042}
3043
3044static int sh_eth_resume(struct device *dev)
3045{
3046 struct net_device *ndev = dev_get_drvdata(dev);
3047 int ret = 0;
3048
3049 if (netif_running(ndev)) {
3050 ret = sh_eth_open(ndev);
3051 if (ret < 0)
3052 return ret;
3053 netif_device_attach(ndev);
3054 }
3055
3056 return ret;
3057}
3058#endif
3059
bcd5149d
MD		 3060static int sh_eth_runtime_nop(struct device *dev)
3061{
128296fc 3062 /* Runtime PM callback shared between ->runtime_suspend()
bcd5149d
MD		 3063 * and ->runtime_resume(). Simply returns success.
3064 *
3065 * This driver re-initializes all registers after
3066 * pm_runtime_get_sync() anyway so there is no need
3067 * to save and restore registers here.
3068 */
3069 return 0;
3070}
3071
540ad1b8 3072static const struct dev_pm_ops sh_eth_dev_pm_ops = {
b71af046 3073 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
e7d7e898 3074 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
bcd5149d 3075};
540ad1b8
NI		 3076#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3077#else
3078#define SH_ETH_PM_OPS NULL
3079#endif
bcd5149d 3080
afe391ad 3081static struct platform_device_id sh_eth_id_table[] = {
c18a79ab 3082 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
7bbe150d 3083 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
9c3beaab 3084 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
f5d12767 3085 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
24549e2a
SS		 3086 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3087 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
f5d12767 3088 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
db893473 3089 { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
e5c9b4cd 3090 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
589ebdef 3091 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
94a12b15
SS		 3092 { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
3093 { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
9488e1e5 3094 { "r8a7793-ether", (kernel_ulong_t)&r8a779x_data },
0f76b9d8 3095 { "r8a7794-ether", (kernel_ulong_t)&r8a779x_data },
afe391ad
SS		 3096 { }
3097};
3098MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3099
86a74ff2
NI		 3100static struct platform_driver sh_eth_driver = {
3101 .probe = sh_eth_drv_probe,
3102 .remove = sh_eth_drv_remove,
afe391ad 3103 .id_table = sh_eth_id_table,
86a74ff2
NI		 3104 .driver = {
3105 .name = CARDNAME,
540ad1b8 3106 .pm = SH_ETH_PM_OPS,
b356e978 3107 .of_match_table = of_match_ptr(sh_eth_match_table),
86a74ff2
NI		 3108 },
3109};
3110
db62f684 3111module_platform_driver(sh_eth_driver);
86a74ff2
NI		 3112
3113MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3114MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3115MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)