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net: sh_eth: change the condition of initialization
[linux-2.6-block.git] / drivers / net / ethernet / renesas / sh_eth.c
CommitLineData
86a74ff2
NI		 1/*
2 * SuperH Ethernet device driver
3 *
b0ca2a21 4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
380af9e3 5 * Copyright (C) 2008-2009 Renesas Solutions Corp.
86a74ff2
NI		 6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 */
22
86a74ff2 23#include <linux/init.h>
0654011d
YS		 24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/spinlock.h>
6a27cded 27#include <linux/interrupt.h>
86a74ff2
NI		 28#include <linux/dma-mapping.h>
29#include <linux/etherdevice.h>
30#include <linux/delay.h>
31#include <linux/platform_device.h>
32#include <linux/mdio-bitbang.h>
33#include <linux/netdevice.h>
34#include <linux/phy.h>
35#include <linux/cache.h>
36#include <linux/io.h>
bcd5149d 37#include <linux/pm_runtime.h>
5a0e3ad6 38#include <linux/slab.h>
dc19e4e5 39#include <linux/ethtool.h>
fdb37a7f 40#include <linux/if_vlan.h>
d4fa0e35 41#include <linux/sh_eth.h>
86a74ff2
NI		 42
43#include "sh_eth.h"
44
dc19e4e5
NI		 45#define SH_ETH_DEF_MSG_ENABLE \
46 (NETIF_MSG_LINK | \
47 NETIF_MSG_TIMER | \
48 NETIF_MSG_RX_ERR| \
49 NETIF_MSG_TX_ERR)
50
380af9e3 51/* There is CPU dependent code */
65ac8851
YS		 52#if defined(CONFIG_CPU_SUBTYPE_SH7724)
53#define SH_ETH_RESET_DEFAULT 1
54static void sh_eth_set_duplex(struct net_device *ndev)
55{
56 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 57
58 if (mdp->duplex) /* Full */
4a55530f 59 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
65ac8851 60 else /* Half */
4a55530f 61 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
65ac8851
YS		 62}
63
64static void sh_eth_set_rate(struct net_device *ndev)
65{
66 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 67
68 switch (mdp->speed) {
69 case 10: /* 10BASE */
4a55530f 70 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
65ac8851
YS		 71 break;
72 case 100:/* 100BASE */
4a55530f 73 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
65ac8851
YS		 74 break;
75 default:
76 break;
77 }
78}
79
80/* SH7724 */
81static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
82 .set_duplex = sh_eth_set_duplex,
83 .set_rate = sh_eth_set_rate,
84
85 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
86 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
87 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
88
89 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
90 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
91 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
92 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
93
94 .apr = 1,
95 .mpr = 1,
96 .tpauser = 1,
97 .hw_swap = 1,
503914cf
MD		 98 .rpadir = 1,
99 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 100};
f29a3d04 101#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
8fcd4961
YS		 102#define SH_ETH_HAS_BOTH_MODULES 1
103#define SH_ETH_HAS_TSU 1
f29a3d04
YS		 104static void sh_eth_set_duplex(struct net_device *ndev)
105{
106 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 107
108 if (mdp->duplex) /* Full */
4a55530f 109 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
f29a3d04 110 else /* Half */
4a55530f 111 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
f29a3d04
YS		 112}
113
114static void sh_eth_set_rate(struct net_device *ndev)
115{
116 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 117
118 switch (mdp->speed) {
119 case 10: /* 10BASE */
4a55530f 120 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 121 break;
122 case 100:/* 100BASE */
4a55530f 123 sh_eth_write(ndev, 1, RTRATE);
f29a3d04
YS		 124 break;
125 default:
126 break;
127 }
128}
129
130/* SH7757 */
131static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
132 .set_duplex = sh_eth_set_duplex,
133 .set_rate = sh_eth_set_rate,
134
135 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
136 .rmcr_value = 0x00000001,
137
138 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
139 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
140 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
141 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
142
143 .apr = 1,
144 .mpr = 1,
145 .tpauser = 1,
146 .hw_swap = 1,
147 .no_ade = 1,
2e98e797
YS		 148 .rpadir = 1,
149 .rpadir_value = 2 << 16,
f29a3d04 150};
65ac8851 151
8fcd4961
YS		 152#define SH_GIGA_ETH_BASE 0xfee00000
153#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
154#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
155static void sh_eth_chip_reset_giga(struct net_device *ndev)
156{
157 int i;
158 unsigned long mahr[2], malr[2];
159
160 /* save MAHR and MALR */
161 for (i = 0; i < 2; i++) {
ae70644d
YS		 162 malr[i] = ioread32((void *)GIGA_MALR(i));
163 mahr[i] = ioread32((void *)GIGA_MAHR(i));
8fcd4961
YS		 164 }
165
166 /* reset device */
ae70644d 167 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
8fcd4961
YS		 168 mdelay(1);
169
170 /* restore MAHR and MALR */
171 for (i = 0; i < 2; i++) {
ae70644d
YS		 172 iowrite32(malr[i], (void *)GIGA_MALR(i));
173 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
8fcd4961
YS		 174 }
175}
176
177static int sh_eth_is_gether(struct sh_eth_private *mdp);
178static void sh_eth_reset(struct net_device *ndev)
179{
180 struct sh_eth_private *mdp = netdev_priv(ndev);
181 int cnt = 100;
182
183 if (sh_eth_is_gether(mdp)) {
184 sh_eth_write(ndev, 0x03, EDSR);
185 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
186 EDMR);
187 while (cnt > 0) {
188 if (!(sh_eth_read(ndev, EDMR) & 0x3))
189 break;
190 mdelay(1);
191 cnt--;
192 }
193 if (cnt < 0)
194 printk(KERN_ERR "Device reset fail\n");
195
196 /* Table Init */
197 sh_eth_write(ndev, 0x0, TDLAR);
198 sh_eth_write(ndev, 0x0, TDFAR);
199 sh_eth_write(ndev, 0x0, TDFXR);
200 sh_eth_write(ndev, 0x0, TDFFR);
201 sh_eth_write(ndev, 0x0, RDLAR);
202 sh_eth_write(ndev, 0x0, RDFAR);
203 sh_eth_write(ndev, 0x0, RDFXR);
204 sh_eth_write(ndev, 0x0, RDFFR);
205 } else {
206 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
207 EDMR);
208 mdelay(3);
209 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
210 EDMR);
211 }
212}
213
214static void sh_eth_set_duplex_giga(struct net_device *ndev)
215{
216 struct sh_eth_private *mdp = netdev_priv(ndev);
217
218 if (mdp->duplex) /* Full */
219 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
220 else /* Half */
221 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
222}
223
224static void sh_eth_set_rate_giga(struct net_device *ndev)
225{
226 struct sh_eth_private *mdp = netdev_priv(ndev);
227
228 switch (mdp->speed) {
229 case 10: /* 10BASE */
230 sh_eth_write(ndev, 0x00000000, GECMR);
231 break;
232 case 100:/* 100BASE */
233 sh_eth_write(ndev, 0x00000010, GECMR);
234 break;
235 case 1000: /* 1000BASE */
236 sh_eth_write(ndev, 0x00000020, GECMR);
237 break;
238 default:
239 break;
240 }
241}
242
243/* SH7757(GETHERC) */
244static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga = {
245 .chip_reset = sh_eth_chip_reset_giga,
246 .set_duplex = sh_eth_set_duplex_giga,
247 .set_rate = sh_eth_set_rate_giga,
248
249 .ecsr_value = ECSR_ICD | ECSR_MPD,
250 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
251 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
252
253 .tx_check = EESR_TC1 | EESR_FTC,
254 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
255 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
256 EESR_ECI,
257 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
258 EESR_TFE,
259 .fdr_value = 0x0000072f,
260 .rmcr_value = 0x00000001,
261
262 .apr = 1,
263 .mpr = 1,
264 .tpauser = 1,
265 .bculr = 1,
266 .hw_swap = 1,
267 .rpadir = 1,
268 .rpadir_value = 2 << 16,
269 .no_trimd = 1,
270 .no_ade = 1,
3acbc971 271 .tsu = 1,
8fcd4961
YS		 272};
273
274static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp)
275{
276 if (sh_eth_is_gether(mdp))
277 return &sh_eth_my_cpu_data_giga;
278 else
279 return &sh_eth_my_cpu_data;
280}
281
65ac8851 282#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
380af9e3
YS		 283#define SH_ETH_HAS_TSU 1
284static void sh_eth_chip_reset(struct net_device *ndev)
285{
4986b996
YS		 286 struct sh_eth_private *mdp = netdev_priv(ndev);
287
380af9e3 288 /* reset device */
4986b996 289 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
380af9e3
YS		 290 mdelay(1);
291}
292
293static void sh_eth_reset(struct net_device *ndev)
294{
380af9e3
YS		 295 int cnt = 100;
296
4a55530f 297 sh_eth_write(ndev, EDSR_ENALL, EDSR);
c5ed5368 298 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
380af9e3 299 while (cnt > 0) {
4a55530f 300 if (!(sh_eth_read(ndev, EDMR) & 0x3))
380af9e3
YS		 301 break;
302 mdelay(1);
303 cnt--;
304 }
890c8c18 305 if (cnt == 0)
380af9e3
YS		 306 printk(KERN_ERR "Device reset fail\n");
307
308 /* Table Init */
4a55530f
YS		 309 sh_eth_write(ndev, 0x0, TDLAR);
310 sh_eth_write(ndev, 0x0, TDFAR);
311 sh_eth_write(ndev, 0x0, TDFXR);
312 sh_eth_write(ndev, 0x0, TDFFR);
313 sh_eth_write(ndev, 0x0, RDLAR);
314 sh_eth_write(ndev, 0x0, RDFAR);
315 sh_eth_write(ndev, 0x0, RDFXR);
316 sh_eth_write(ndev, 0x0, RDFFR);
380af9e3
YS		 317}
318
319static void sh_eth_set_duplex(struct net_device *ndev)
320{
321 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3
YS		 322
323 if (mdp->duplex) /* Full */
4a55530f 324 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
380af9e3 325 else /* Half */
4a55530f 326 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
380af9e3
YS		 327}
328
329static void sh_eth_set_rate(struct net_device *ndev)
330{
331 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3
YS		 332
333 switch (mdp->speed) {
334 case 10: /* 10BASE */
4a55530f 335 sh_eth_write(ndev, GECMR_10, GECMR);
380af9e3
YS		 336 break;
337 case 100:/* 100BASE */
4a55530f 338 sh_eth_write(ndev, GECMR_100, GECMR);
380af9e3
YS		 339 break;
340 case 1000: /* 1000BASE */
4a55530f 341 sh_eth_write(ndev, GECMR_1000, GECMR);
380af9e3
YS		 342 break;
343 default:
344 break;
345 }
346}
347
348/* sh7763 */
349static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
350 .chip_reset = sh_eth_chip_reset,
351 .set_duplex = sh_eth_set_duplex,
352 .set_rate = sh_eth_set_rate,
353
354 .ecsr_value = ECSR_ICD | ECSR_MPD,
355 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
356 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
357
358 .tx_check = EESR_TC1 | EESR_FTC,
359 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
360 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
361 EESR_ECI,
362 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
363 EESR_TFE,
364
365 .apr = 1,
366 .mpr = 1,
367 .tpauser = 1,
368 .bculr = 1,
369 .hw_swap = 1,
380af9e3
YS		 370 .no_trimd = 1,
371 .no_ade = 1,
4986b996 372 .tsu = 1,
380af9e3
YS		 373};
374
375#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
376#define SH_ETH_RESET_DEFAULT 1
377static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
378 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
379
380 .apr = 1,
381 .mpr = 1,
382 .tpauser = 1,
383 .hw_swap = 1,
384};
385#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
386#define SH_ETH_RESET_DEFAULT 1
387#define SH_ETH_HAS_TSU 1
388static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
389 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
4986b996 390 .tsu = 1,
380af9e3
YS		 391};
392#endif
393
394static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
395{
396 if (!cd->ecsr_value)
397 cd->ecsr_value = DEFAULT_ECSR_INIT;
398
399 if (!cd->ecsipr_value)
400 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
401
402 if (!cd->fcftr_value)
403 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
404 DEFAULT_FIFO_F_D_RFD;
405
406 if (!cd->fdr_value)
407 cd->fdr_value = DEFAULT_FDR_INIT;
408
409 if (!cd->rmcr_value)
410 cd->rmcr_value = DEFAULT_RMCR_VALUE;
411
412 if (!cd->tx_check)
413 cd->tx_check = DEFAULT_TX_CHECK;
414
415 if (!cd->eesr_err_check)
416 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
417
418 if (!cd->tx_error_check)
419 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
420}
421
422#if defined(SH_ETH_RESET_DEFAULT)
423/* Chip Reset */
424static void sh_eth_reset(struct net_device *ndev)
425{
c5ed5368 426 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, EDMR);
380af9e3 427 mdelay(3);
c5ed5368 428 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, EDMR);
380af9e3
YS		 429}
430#endif
431
432#if defined(CONFIG_CPU_SH4)
433static void sh_eth_set_receive_align(struct sk_buff *skb)
434{
435 int reserve;
436
437 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
438 if (reserve)
439 skb_reserve(skb, reserve);
440}
441#else
442static void sh_eth_set_receive_align(struct sk_buff *skb)
443{
444 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
445}
446#endif
447
448
71557a37
YS		 449/* CPU <-> EDMAC endian convert */
450static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
451{
452 switch (mdp->edmac_endian) {
453 case EDMAC_LITTLE_ENDIAN:
454 return cpu_to_le32(x);
455 case EDMAC_BIG_ENDIAN:
456 return cpu_to_be32(x);
457 }
458 return x;
459}
460
461static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
462{
463 switch (mdp->edmac_endian) {
464 case EDMAC_LITTLE_ENDIAN:
465 return le32_to_cpu(x);
466 case EDMAC_BIG_ENDIAN:
467 return be32_to_cpu(x);
468 }
469 return x;
470}
471
86a74ff2
NI		 472/*
473 * Program the hardware MAC address from dev->dev_addr.
474 */
475static void update_mac_address(struct net_device *ndev)
476{
4a55530f
YS		 477 sh_eth_write(ndev,
478 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
479 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
480 sh_eth_write(ndev,
481 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 482}
483
484/*
485 * Get MAC address from SuperH MAC address register
486 *
487 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
488 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
489 * When you want use this device, you must set MAC address in bootloader.
490 *
491 */
748031f9 492static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 493{
748031f9
MD		 494 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
495 memcpy(ndev->dev_addr, mac, 6);
496 } else {
4a55530f
YS		 497 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
498 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
499 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
500 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
501 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
502 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
748031f9 503 }
86a74ff2
NI		 504}
505
c5ed5368
YS		 506static int sh_eth_is_gether(struct sh_eth_private *mdp)
507{
508 if (mdp->reg_offset == sh_eth_offset_gigabit)
509 return 1;
510 else
511 return 0;
512}
513
514static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
515{
516 if (sh_eth_is_gether(mdp))
517 return EDTRR_TRNS_GETHER;
518 else
519 return EDTRR_TRNS_ETHER;
520}
521
86a74ff2 522struct bb_info {
ae70644d 523 void (*set_gate)(void *addr);
86a74ff2 524 struct mdiobb_ctrl ctrl;
ae70644d 525 void *addr;
86a74ff2
NI		 526 u32 mmd_msk;/* MMD */
527 u32 mdo_msk;
528 u32 mdi_msk;
529 u32 mdc_msk;
530};
531
532/* PHY bit set */
ae70644d 533static void bb_set(void *addr, u32 msk)
86a74ff2 534{
ae70644d 535 iowrite32(ioread32(addr) | msk, addr);
86a74ff2
NI		 536}
537
538/* PHY bit clear */
ae70644d 539static void bb_clr(void *addr, u32 msk)
86a74ff2 540{
ae70644d 541 iowrite32((ioread32(addr) & ~msk), addr);
86a74ff2
NI		 542}
543
544/* PHY bit read */
ae70644d 545static int bb_read(void *addr, u32 msk)
86a74ff2 546{
ae70644d 547 return (ioread32(addr) & msk) != 0;
86a74ff2
NI		 548}
549
550/* Data I/O pin control */
551static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
552{
553 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 554
555 if (bitbang->set_gate)
556 bitbang->set_gate(bitbang->addr);
557
86a74ff2
NI		 558 if (bit)
559 bb_set(bitbang->addr, bitbang->mmd_msk);
560 else
561 bb_clr(bitbang->addr, bitbang->mmd_msk);
562}
563
564/* Set bit data*/
565static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
566{
567 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
568
b3017e6a
YS		 569 if (bitbang->set_gate)
570 bitbang->set_gate(bitbang->addr);
571
86a74ff2
NI		 572 if (bit)
573 bb_set(bitbang->addr, bitbang->mdo_msk);
574 else
575 bb_clr(bitbang->addr, bitbang->mdo_msk);
576}
577
578/* Get bit data*/
579static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
580{
581 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 582
583 if (bitbang->set_gate)
584 bitbang->set_gate(bitbang->addr);
585
86a74ff2
NI		 586 return bb_read(bitbang->addr, bitbang->mdi_msk);
587}
588
589/* MDC pin control */
590static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
591{
592 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
593
b3017e6a
YS		 594 if (bitbang->set_gate)
595 bitbang->set_gate(bitbang->addr);
596
86a74ff2
NI		 597 if (bit)
598 bb_set(bitbang->addr, bitbang->mdc_msk);
599 else
600 bb_clr(bitbang->addr, bitbang->mdc_msk);
601}
602
603/* mdio bus control struct */
604static struct mdiobb_ops bb_ops = {
605 .owner = THIS_MODULE,
606 .set_mdc = sh_mdc_ctrl,
607 .set_mdio_dir = sh_mmd_ctrl,
608 .set_mdio_data = sh_set_mdio,
609 .get_mdio_data = sh_get_mdio,
610};
611
86a74ff2
NI		 612/* free skb and descriptor buffer */
613static void sh_eth_ring_free(struct net_device *ndev)
614{
615 struct sh_eth_private *mdp = netdev_priv(ndev);
616 int i;
617
618 /* Free Rx skb ringbuffer */
619 if (mdp->rx_skbuff) {
620 for (i = 0; i < RX_RING_SIZE; i++) {
621 if (mdp->rx_skbuff[i])
622 dev_kfree_skb(mdp->rx_skbuff[i]);
623 }
624 }
625 kfree(mdp->rx_skbuff);
626
627 /* Free Tx skb ringbuffer */
628 if (mdp->tx_skbuff) {
629 for (i = 0; i < TX_RING_SIZE; i++) {
630 if (mdp->tx_skbuff[i])
631 dev_kfree_skb(mdp->tx_skbuff[i]);
632 }
633 }
634 kfree(mdp->tx_skbuff);
635}
636
637/* format skb and descriptor buffer */
638static void sh_eth_ring_format(struct net_device *ndev)
639{
640 struct sh_eth_private *mdp = netdev_priv(ndev);
641 int i;
642 struct sk_buff *skb;
643 struct sh_eth_rxdesc *rxdesc = NULL;
644 struct sh_eth_txdesc *txdesc = NULL;
645 int rx_ringsize = sizeof(*rxdesc) * RX_RING_SIZE;
646 int tx_ringsize = sizeof(*txdesc) * TX_RING_SIZE;
647
648 mdp->cur_rx = mdp->cur_tx = 0;
649 mdp->dirty_rx = mdp->dirty_tx = 0;
650
651 memset(mdp->rx_ring, 0, rx_ringsize);
652
653 /* build Rx ring buffer */
654 for (i = 0; i < RX_RING_SIZE; i++) {
655 /* skb */
656 mdp->rx_skbuff[i] = NULL;
dae2e9f4 657 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
86a74ff2
NI		 658 mdp->rx_skbuff[i] = skb;
659 if (skb == NULL)
660 break;
bb7d92e3 661 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
e88aae7b 662 DMA_FROM_DEVICE);
380af9e3
YS		 663 sh_eth_set_receive_align(skb);
664
86a74ff2
NI		 665 /* RX descriptor */
666 rxdesc = &mdp->rx_ring[i];
0029d64a 667 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
71557a37 668 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 669
670 /* The size of the buffer is 16 byte boundary. */
0029d64a 671 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21
NI		 672 /* Rx descriptor address set */
673 if (i == 0) {
4a55530f 674 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
c5ed5368
YS		 675 if (sh_eth_is_gether(mdp))
676 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 677 }
86a74ff2
NI		 678 }
679
680 mdp->dirty_rx = (u32) (i - RX_RING_SIZE);
681
682 /* Mark the last entry as wrapping the ring. */
71557a37 683 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
86a74ff2
NI		 684
685 memset(mdp->tx_ring, 0, tx_ringsize);
686
687 /* build Tx ring buffer */
688 for (i = 0; i < TX_RING_SIZE; i++) {
689 mdp->tx_skbuff[i] = NULL;
690 txdesc = &mdp->tx_ring[i];
71557a37 691 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 692 txdesc->buffer_length = 0;
b0ca2a21 693 if (i == 0) {
71557a37 694 /* Tx descriptor address set */
4a55530f 695 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
c5ed5368
YS		 696 if (sh_eth_is_gether(mdp))
697 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 698 }
86a74ff2
NI		 699 }
700
71557a37 701 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2
NI		 702}
703
704/* Get skb and descriptor buffer */
705static int sh_eth_ring_init(struct net_device *ndev)
706{
707 struct sh_eth_private *mdp = netdev_priv(ndev);
708 int rx_ringsize, tx_ringsize, ret = 0;
709
710 /*
711 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
712 * card needs room to do 8 byte alignment, +2 so we can reserve
713 * the first 2 bytes, and +16 gets room for the status word from the
714 * card.
715 */
716 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
717 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 718 if (mdp->cd->rpadir)
719 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 720
721 /* Allocate RX and TX skb rings */
722 mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE,
723 GFP_KERNEL);
724 if (!mdp->rx_skbuff) {
380af9e3 725 dev_err(&ndev->dev, "Cannot allocate Rx skb\n");
86a74ff2
NI		 726 ret = -ENOMEM;
727 return ret;
728 }
729
730 mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE,
731 GFP_KERNEL);
732 if (!mdp->tx_skbuff) {
380af9e3 733 dev_err(&ndev->dev, "Cannot allocate Tx skb\n");
86a74ff2
NI		 734 ret = -ENOMEM;
735 goto skb_ring_free;
736 }
737
738 /* Allocate all Rx descriptors. */
739 rx_ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
740 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
741 GFP_KERNEL);
742
743 if (!mdp->rx_ring) {
380af9e3
YS		 744 dev_err(&ndev->dev, "Cannot allocate Rx Ring (size %d bytes)\n",
745 rx_ringsize);
86a74ff2
NI		 746 ret = -ENOMEM;
747 goto desc_ring_free;
748 }
749
750 mdp->dirty_rx = 0;
751
752 /* Allocate all Tx descriptors. */
753 tx_ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
754 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
755 GFP_KERNEL);
756 if (!mdp->tx_ring) {
380af9e3
YS		 757 dev_err(&ndev->dev, "Cannot allocate Tx Ring (size %d bytes)\n",
758 tx_ringsize);
86a74ff2
NI		 759 ret = -ENOMEM;
760 goto desc_ring_free;
761 }
762 return ret;
763
764desc_ring_free:
765 /* free DMA buffer */
766 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
767
768skb_ring_free:
769 /* Free Rx and Tx skb ring buffer */
770 sh_eth_ring_free(ndev);
771
772 return ret;
773}
774
775static int sh_eth_dev_init(struct net_device *ndev)
776{
777 int ret = 0;
778 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 779 u_int32_t rx_int_var, tx_int_var;
780 u32 val;
781
782 /* Soft Reset */
783 sh_eth_reset(ndev);
784
b0ca2a21
NI		 785 /* Descriptor format */
786 sh_eth_ring_format(ndev);
380af9e3 787 if (mdp->cd->rpadir)
4a55530f 788 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 789
790 /* all sh_eth int mask */
4a55530f 791 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 792
380af9e3
YS		 793#if defined(__LITTLE_ENDIAN__)
794 if (mdp->cd->hw_swap)
4a55530f 795 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 796 else
b0ca2a21 797#endif
4a55530f 798 sh_eth_write(ndev, 0, EDMR);
86a74ff2 799
b0ca2a21 800 /* FIFO size set */
4a55530f
YS		 801 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
802 sh_eth_write(ndev, 0, TFTR);
86a74ff2 803
b0ca2a21 804 /* Frame recv control */
4a55530f 805 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
86a74ff2
NI		 806
807 rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5;
808 tx_int_var = mdp->tx_int_var = DESC_I_TINT2;
4a55530f 809 sh_eth_write(ndev, rx_int_var | tx_int_var, TRSCER);
86a74ff2 810
380af9e3 811 if (mdp->cd->bculr)
4a55530f 812 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 813
4a55530f 814 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 815
380af9e3 816 if (!mdp->cd->no_trimd)
4a55530f 817 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 818
b0ca2a21 819 /* Recv frame limit set register */
fdb37a7f
YS		 820 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
821 RFLR);
86a74ff2 822
4a55530f
YS		 823 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
824 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
86a74ff2
NI		 825
826 /* PAUSE Prohibition */
4a55530f 827 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
86a74ff2
NI		 828 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
829
4a55530f 830 sh_eth_write(ndev, val, ECMR);
b0ca2a21 831
380af9e3
YS		 832 if (mdp->cd->set_rate)
833 mdp->cd->set_rate(ndev);
834
b0ca2a21 835 /* E-MAC Status Register clear */
4a55530f 836 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 837
838 /* E-MAC Interrupt Enable register */
4a55530f 839 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 840
841 /* Set MAC address */
842 update_mac_address(ndev);
843
844 /* mask reset */
380af9e3 845 if (mdp->cd->apr)
4a55530f 846 sh_eth_write(ndev, APR_AP, APR);
380af9e3 847 if (mdp->cd->mpr)
4a55530f 848 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 849 if (mdp->cd->tpauser)
4a55530f 850 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 851
86a74ff2 852 /* Setting the Rx mode will start the Rx process. */
4a55530f 853 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2
NI		 854
855 netif_start_queue(ndev);
856
857 return ret;
858}
859
860/* free Tx skb function */
861static int sh_eth_txfree(struct net_device *ndev)
862{
863 struct sh_eth_private *mdp = netdev_priv(ndev);
864 struct sh_eth_txdesc *txdesc;
865 int freeNum = 0;
866 int entry = 0;
867
868 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
869 entry = mdp->dirty_tx % TX_RING_SIZE;
870 txdesc = &mdp->tx_ring[entry];
71557a37 871 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
86a74ff2
NI		 872 break;
873 /* Free the original skb. */
874 if (mdp->tx_skbuff[entry]) {
31fcb99d
YS		 875 dma_unmap_single(&ndev->dev, txdesc->addr,
876 txdesc->buffer_length, DMA_TO_DEVICE);
86a74ff2
NI		 877 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
878 mdp->tx_skbuff[entry] = NULL;
879 freeNum++;
880 }
71557a37 881 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 882 if (entry >= TX_RING_SIZE - 1)
71557a37 883 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2 884
bb7d92e3
ED		 885 ndev->stats.tx_packets++;
886 ndev->stats.tx_bytes += txdesc->buffer_length;
86a74ff2
NI		 887 }
888 return freeNum;
889}
890
891/* Packet receive function */
892static int sh_eth_rx(struct net_device *ndev)
893{
894 struct sh_eth_private *mdp = netdev_priv(ndev);
895 struct sh_eth_rxdesc *rxdesc;
896
897 int entry = mdp->cur_rx % RX_RING_SIZE;
898 int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx;
899 struct sk_buff *skb;
900 u16 pkt_len = 0;
380af9e3 901 u32 desc_status;
86a74ff2
NI		 902
903 rxdesc = &mdp->rx_ring[entry];
71557a37
YS		 904 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
905 desc_status = edmac_to_cpu(mdp, rxdesc->status);
86a74ff2
NI		 906 pkt_len = rxdesc->frame_length;
907
908 if (--boguscnt < 0)
909 break;
910
911 if (!(desc_status & RDFEND))
bb7d92e3 912 ndev->stats.rx_length_errors++;
86a74ff2
NI		 913
914 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
915 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
bb7d92e3 916 ndev->stats.rx_errors++;
86a74ff2 917 if (desc_status & RD_RFS1)
bb7d92e3 918 ndev->stats.rx_crc_errors++;
86a74ff2 919 if (desc_status & RD_RFS2)
bb7d92e3 920 ndev->stats.rx_frame_errors++;
86a74ff2 921 if (desc_status & RD_RFS3)
bb7d92e3 922 ndev->stats.rx_length_errors++;
86a74ff2 923 if (desc_status & RD_RFS4)
bb7d92e3 924 ndev->stats.rx_length_errors++;
86a74ff2 925 if (desc_status & RD_RFS6)
bb7d92e3 926 ndev->stats.rx_missed_errors++;
86a74ff2 927 if (desc_status & RD_RFS10)
bb7d92e3 928 ndev->stats.rx_over_errors++;
86a74ff2 929 } else {
380af9e3
YS		 930 if (!mdp->cd->hw_swap)
931 sh_eth_soft_swap(
932 phys_to_virt(ALIGN(rxdesc->addr, 4)),
933 pkt_len + 2);
86a74ff2
NI		 934 skb = mdp->rx_skbuff[entry];
935 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 936 if (mdp->cd->rpadir)
937 skb_reserve(skb, NET_IP_ALIGN);
86a74ff2
NI		 938 skb_put(skb, pkt_len);
939 skb->protocol = eth_type_trans(skb, ndev);
940 netif_rx(skb);
bb7d92e3
ED		 941 ndev->stats.rx_packets++;
942 ndev->stats.rx_bytes += pkt_len;
86a74ff2 943 }
71557a37 944 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
86a74ff2 945 entry = (++mdp->cur_rx) % RX_RING_SIZE;
862df497 946 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 947 }
948
949 /* Refill the Rx ring buffers. */
950 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
951 entry = mdp->dirty_rx % RX_RING_SIZE;
952 rxdesc = &mdp->rx_ring[entry];
b0ca2a21 953 /* The size of the buffer is 16 byte boundary. */
0029d64a 954 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21 955
86a74ff2 956 if (mdp->rx_skbuff[entry] == NULL) {
dae2e9f4 957 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
86a74ff2
NI		 958 mdp->rx_skbuff[entry] = skb;
959 if (skb == NULL)
960 break; /* Better luck next round. */
bb7d92e3 961 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
e88aae7b 962 DMA_FROM_DEVICE);
380af9e3
YS		 963 sh_eth_set_receive_align(skb);
964
bc8acf2c 965 skb_checksum_none_assert(skb);
0029d64a 966 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
86a74ff2 967 }
86a74ff2
NI		 968 if (entry >= RX_RING_SIZE - 1)
969 rxdesc->status |=
71557a37 970 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
86a74ff2
NI		 971 else
972 rxdesc->status |=
71557a37 973 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 974 }
975
976 /* Restart Rx engine if stopped. */
977 /* If we don't need to check status, don't. -KDU */
4a55530f
YS		 978 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R))
979 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2
NI		 980
981 return 0;
982}
983
4a55530f 984static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 985{
986 /* disable tx and rx */
4a55530f
YS		 987 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
988 ~(ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 989}
990
4a55530f 991static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 992{
993 /* enable tx and rx */
4a55530f
YS		 994 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
995 (ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 996}
997
86a74ff2
NI		 998/* error control function */
999static void sh_eth_error(struct net_device *ndev, int intr_status)
1000{
1001 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1002 u32 felic_stat;
380af9e3
YS		 1003 u32 link_stat;
1004 u32 mask;
86a74ff2
NI		 1005
1006 if (intr_status & EESR_ECI) {
4a55530f
YS		 1007 felic_stat = sh_eth_read(ndev, ECSR);
1008 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
86a74ff2 1009 if (felic_stat & ECSR_ICD)
bb7d92e3 1010 ndev->stats.tx_carrier_errors++;
86a74ff2
NI		 1011 if (felic_stat & ECSR_LCHNG) {
1012 /* Link Changed */
4923576b 1013 if (mdp->cd->no_psr || mdp->no_ether_link) {
380af9e3
YS		 1014 if (mdp->link == PHY_DOWN)
1015 link_stat = 0;
1016 else
1017 link_stat = PHY_ST_LINK;
1018 } else {
4a55530f 1019 link_stat = (sh_eth_read(ndev, PSR));
4923576b
YS		 1020 if (mdp->ether_link_active_low)
1021 link_stat = ~link_stat;
380af9e3 1022 }
dc19e4e5 1023 if (!(link_stat & PHY_ST_LINK))
4a55530f 1024 sh_eth_rcv_snd_disable(ndev);
dc19e4e5 1025 else {
86a74ff2 1026 /* Link Up */
4a55530f
YS		 1027 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1028 ~DMAC_M_ECI, EESIPR);
86a74ff2 1029 /*clear int */
4a55530f
YS		 1030 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1031 ECSR);
1032 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1033 DMAC_M_ECI, EESIPR);
86a74ff2 1034 /* enable tx and rx */
4a55530f 1035 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1036 }
1037 }
1038 }
1039
1040 if (intr_status & EESR_TWB) {
1041 /* Write buck end. unused write back interrupt */
1042 if (intr_status & EESR_TABT) /* Transmit Abort int */
bb7d92e3 1043 ndev->stats.tx_aborted_errors++;
dc19e4e5
NI		 1044 if (netif_msg_tx_err(mdp))
1045 dev_err(&ndev->dev, "Transmit Abort\n");
86a74ff2
NI		 1046 }
1047
1048 if (intr_status & EESR_RABT) {
1049 /* Receive Abort int */
1050 if (intr_status & EESR_RFRMER) {
1051 /* Receive Frame Overflow int */
bb7d92e3 1052 ndev->stats.rx_frame_errors++;
dc19e4e5
NI		 1053 if (netif_msg_rx_err(mdp))
1054 dev_err(&ndev->dev, "Receive Abort\n");
86a74ff2
NI		 1055 }
1056 }
380af9e3 1057
dc19e4e5
NI		 1058 if (intr_status & EESR_TDE) {
1059 /* Transmit Descriptor Empty int */
bb7d92e3 1060 ndev->stats.tx_fifo_errors++;
dc19e4e5
NI		 1061 if (netif_msg_tx_err(mdp))
1062 dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1063 }
1064
1065 if (intr_status & EESR_TFE) {
1066 /* FIFO under flow */
bb7d92e3 1067 ndev->stats.tx_fifo_errors++;
dc19e4e5
NI		 1068 if (netif_msg_tx_err(mdp))
1069 dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1070 }
1071
1072 if (intr_status & EESR_RDE) {
1073 /* Receive Descriptor Empty int */
bb7d92e3 1074 ndev->stats.rx_over_errors++;
86a74ff2 1075
4a55530f
YS		 1076 if (sh_eth_read(ndev, EDRRR) ^ EDRRR_R)
1077 sh_eth_write(ndev, EDRRR_R, EDRRR);
dc19e4e5
NI		 1078 if (netif_msg_rx_err(mdp))
1079 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
86a74ff2 1080 }
dc19e4e5 1081
86a74ff2
NI		 1082 if (intr_status & EESR_RFE) {
1083 /* Receive FIFO Overflow int */
bb7d92e3 1084 ndev->stats.rx_fifo_errors++;
dc19e4e5
NI		 1085 if (netif_msg_rx_err(mdp))
1086 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1087 }
1088
1089 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1090 /* Address Error */
bb7d92e3 1091 ndev->stats.tx_fifo_errors++;
dc19e4e5
NI		 1092 if (netif_msg_tx_err(mdp))
1093 dev_err(&ndev->dev, "Address Error\n");
86a74ff2 1094 }
380af9e3
YS		 1095
1096 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1097 if (mdp->cd->no_ade)
1098 mask &= ~EESR_ADE;
1099 if (intr_status & mask) {
86a74ff2 1100 /* Tx error */
4a55530f 1101 u32 edtrr = sh_eth_read(ndev, EDTRR);
86a74ff2 1102 /* dmesg */
380af9e3
YS		 1103 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
1104 intr_status, mdp->cur_tx);
1105 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
86a74ff2
NI		 1106 mdp->dirty_tx, (u32) ndev->state, edtrr);
1107 /* dirty buffer free */
1108 sh_eth_txfree(ndev);
1109
1110 /* SH7712 BUG */
c5ed5368 1111 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
86a74ff2 1112 /* tx dma start */
c5ed5368 1113 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
86a74ff2
NI		 1114 }
1115 /* wakeup */
1116 netif_wake_queue(ndev);
1117 }
1118}
1119
1120static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1121{
1122 struct net_device *ndev = netdev;
1123 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1124 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1125 irqreturn_t ret = IRQ_NONE;
4a55530f 1126 u32 intr_status = 0;
86a74ff2 1127
86a74ff2
NI		 1128 spin_lock(&mdp->lock);
1129
b0ca2a21 1130 /* Get interrpt stat */
4a55530f 1131 intr_status = sh_eth_read(ndev, EESR);
86a74ff2 1132 /* Clear interrupt */
0e0fde3c
NI		 1133 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
1134 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
380af9e3 1135 cd->tx_check | cd->eesr_err_check)) {
4a55530f 1136 sh_eth_write(ndev, intr_status, EESR);
0e0fde3c
NI		 1137 ret = IRQ_HANDLED;
1138 } else
1139 goto other_irq;
86a74ff2 1140
b0ca2a21
NI		 1141 if (intr_status & (EESR_FRC | /* Frame recv*/
1142 EESR_RMAF | /* Multi cast address recv*/
1143 EESR_RRF | /* Bit frame recv */
1144 EESR_RTLF | /* Long frame recv*/
1145 EESR_RTSF | /* short frame recv */
1146 EESR_PRE | /* PHY-LSI recv error */
1147 EESR_CERF)){ /* recv frame CRC error */
86a74ff2 1148 sh_eth_rx(ndev);
b0ca2a21 1149 }
86a74ff2 1150
b0ca2a21 1151 /* Tx Check */
380af9e3 1152 if (intr_status & cd->tx_check) {
86a74ff2
NI		 1153 sh_eth_txfree(ndev);
1154 netif_wake_queue(ndev);
1155 }
1156
380af9e3 1157 if (intr_status & cd->eesr_err_check)
86a74ff2
NI		 1158 sh_eth_error(ndev, intr_status);
1159
0e0fde3c 1160other_irq:
86a74ff2
NI		 1161 spin_unlock(&mdp->lock);
1162
0e0fde3c 1163 return ret;
86a74ff2
NI		 1164}
1165
1166static void sh_eth_timer(unsigned long data)
1167{
1168 struct net_device *ndev = (struct net_device *)data;
1169 struct sh_eth_private *mdp = netdev_priv(ndev);
1170
1171 mod_timer(&mdp->timer, jiffies + (10 * HZ));
1172}
1173
1174/* PHY state control function */
1175static void sh_eth_adjust_link(struct net_device *ndev)
1176{
1177 struct sh_eth_private *mdp = netdev_priv(ndev);
1178 struct phy_device *phydev = mdp->phydev;
86a74ff2
NI		 1179 int new_state = 0;
1180
1181 if (phydev->link != PHY_DOWN) {
1182 if (phydev->duplex != mdp->duplex) {
1183 new_state = 1;
1184 mdp->duplex = phydev->duplex;
380af9e3
YS		 1185 if (mdp->cd->set_duplex)
1186 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1187 }
1188
1189 if (phydev->speed != mdp->speed) {
1190 new_state = 1;
1191 mdp->speed = phydev->speed;
380af9e3
YS		 1192 if (mdp->cd->set_rate)
1193 mdp->cd->set_rate(ndev);
86a74ff2
NI		 1194 }
1195 if (mdp->link == PHY_DOWN) {
91a56152
YS		 1196 sh_eth_write(ndev,
1197 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
86a74ff2
NI		 1198 new_state = 1;
1199 mdp->link = phydev->link;
86a74ff2
NI		 1200 }
1201 } else if (mdp->link) {
1202 new_state = 1;
1203 mdp->link = PHY_DOWN;
1204 mdp->speed = 0;
1205 mdp->duplex = -1;
86a74ff2
NI		 1206 }
1207
dc19e4e5 1208 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1209 phy_print_status(phydev);
1210}
1211
1212/* PHY init function */
1213static int sh_eth_phy_init(struct net_device *ndev)
1214{
1215 struct sh_eth_private *mdp = netdev_priv(ndev);
0a372eb9 1216 char phy_id[MII_BUS_ID_SIZE + 3];
86a74ff2
NI		 1217 struct phy_device *phydev = NULL;
1218
fb28ad35 1219 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
86a74ff2
NI		 1220 mdp->mii_bus->id , mdp->phy_id);
1221
1222 mdp->link = PHY_DOWN;
1223 mdp->speed = 0;
1224 mdp->duplex = -1;
1225
1226 /* Try connect to PHY */
c061b18d 1227 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
e47c9052 1228 0, mdp->phy_interface);
86a74ff2
NI		 1229 if (IS_ERR(phydev)) {
1230 dev_err(&ndev->dev, "phy_connect failed\n");
1231 return PTR_ERR(phydev);
1232 }
380af9e3 1233
86a74ff2 1234 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
380af9e3 1235 phydev->addr, phydev->drv->name);
86a74ff2
NI		 1236
1237 mdp->phydev = phydev;
1238
1239 return 0;
1240}
1241
1242/* PHY control start function */
1243static int sh_eth_phy_start(struct net_device *ndev)
1244{
1245 struct sh_eth_private *mdp = netdev_priv(ndev);
1246 int ret;
1247
1248 ret = sh_eth_phy_init(ndev);
1249 if (ret)
1250 return ret;
1251
1252 /* reset phy - this also wakes it from PDOWN */
1253 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1254 phy_start(mdp->phydev);
1255
1256 return 0;
1257}
1258
dc19e4e5
NI		 1259static int sh_eth_get_settings(struct net_device *ndev,
1260 struct ethtool_cmd *ecmd)
1261{
1262 struct sh_eth_private *mdp = netdev_priv(ndev);
1263 unsigned long flags;
1264 int ret;
1265
1266 spin_lock_irqsave(&mdp->lock, flags);
1267 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1268 spin_unlock_irqrestore(&mdp->lock, flags);
1269
1270 return ret;
1271}
1272
1273static int sh_eth_set_settings(struct net_device *ndev,
1274 struct ethtool_cmd *ecmd)
1275{
1276 struct sh_eth_private *mdp = netdev_priv(ndev);
1277 unsigned long flags;
1278 int ret;
dc19e4e5
NI		 1279
1280 spin_lock_irqsave(&mdp->lock, flags);
1281
1282 /* disable tx and rx */
4a55530f 1283 sh_eth_rcv_snd_disable(ndev);
dc19e4e5
NI		 1284
1285 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1286 if (ret)
1287 goto error_exit;
1288
1289 if (ecmd->duplex == DUPLEX_FULL)
1290 mdp->duplex = 1;
1291 else
1292 mdp->duplex = 0;
1293
1294 if (mdp->cd->set_duplex)
1295 mdp->cd->set_duplex(ndev);
1296
1297error_exit:
1298 mdelay(1);
1299
1300 /* enable tx and rx */
4a55530f 1301 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 1302
1303 spin_unlock_irqrestore(&mdp->lock, flags);
1304
1305 return ret;
1306}
1307
1308static int sh_eth_nway_reset(struct net_device *ndev)
1309{
1310 struct sh_eth_private *mdp = netdev_priv(ndev);
1311 unsigned long flags;
1312 int ret;
1313
1314 spin_lock_irqsave(&mdp->lock, flags);
1315 ret = phy_start_aneg(mdp->phydev);
1316 spin_unlock_irqrestore(&mdp->lock, flags);
1317
1318 return ret;
1319}
1320
1321static u32 sh_eth_get_msglevel(struct net_device *ndev)
1322{
1323 struct sh_eth_private *mdp = netdev_priv(ndev);
1324 return mdp->msg_enable;
1325}
1326
1327static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1328{
1329 struct sh_eth_private *mdp = netdev_priv(ndev);
1330 mdp->msg_enable = value;
1331}
1332
1333static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1334 "rx_current", "tx_current",
1335 "rx_dirty", "tx_dirty",
1336};
1337#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1338
1339static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1340{
1341 switch (sset) {
1342 case ETH_SS_STATS:
1343 return SH_ETH_STATS_LEN;
1344 default:
1345 return -EOPNOTSUPP;
1346 }
1347}
1348
1349static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1350 struct ethtool_stats *stats, u64 *data)
1351{
1352 struct sh_eth_private *mdp = netdev_priv(ndev);
1353 int i = 0;
1354
1355 /* device-specific stats */
1356 data[i++] = mdp->cur_rx;
1357 data[i++] = mdp->cur_tx;
1358 data[i++] = mdp->dirty_rx;
1359 data[i++] = mdp->dirty_tx;
1360}
1361
1362static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1363{
1364 switch (stringset) {
1365 case ETH_SS_STATS:
1366 memcpy(data, *sh_eth_gstrings_stats,
1367 sizeof(sh_eth_gstrings_stats));
1368 break;
1369 }
1370}
1371
9b07be4b 1372static const struct ethtool_ops sh_eth_ethtool_ops = {
dc19e4e5
NI		 1373 .get_settings = sh_eth_get_settings,
1374 .set_settings = sh_eth_set_settings,
9b07be4b 1375 .nway_reset = sh_eth_nway_reset,
dc19e4e5
NI		 1376 .get_msglevel = sh_eth_get_msglevel,
1377 .set_msglevel = sh_eth_set_msglevel,
9b07be4b 1378 .get_link = ethtool_op_get_link,
dc19e4e5
NI		 1379 .get_strings = sh_eth_get_strings,
1380 .get_ethtool_stats = sh_eth_get_ethtool_stats,
1381 .get_sset_count = sh_eth_get_sset_count,
1382};
1383
86a74ff2
NI		 1384/* network device open function */
1385static int sh_eth_open(struct net_device *ndev)
1386{
1387 int ret = 0;
1388 struct sh_eth_private *mdp = netdev_priv(ndev);
1389
bcd5149d
MD		 1390 pm_runtime_get_sync(&mdp->pdev->dev);
1391
a0607fd3 1392 ret = request_irq(ndev->irq, sh_eth_interrupt,
f29a3d04 1393#if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
dc19e4e5
NI		 1394 defined(CONFIG_CPU_SUBTYPE_SH7764) || \
1395 defined(CONFIG_CPU_SUBTYPE_SH7757)
0e0fde3c
NI		 1396 IRQF_SHARED,
1397#else
1398 0,
1399#endif
1400 ndev->name, ndev);
86a74ff2 1401 if (ret) {
380af9e3 1402 dev_err(&ndev->dev, "Can not assign IRQ number\n");
86a74ff2
NI		 1403 return ret;
1404 }
1405
1406 /* Descriptor set */
1407 ret = sh_eth_ring_init(ndev);
1408 if (ret)
1409 goto out_free_irq;
1410
1411 /* device init */
1412 ret = sh_eth_dev_init(ndev);
1413 if (ret)
1414 goto out_free_irq;
1415
1416 /* PHY control start*/
1417 ret = sh_eth_phy_start(ndev);
1418 if (ret)
1419 goto out_free_irq;
1420
1421 /* Set the timer to check for link beat. */
1422 init_timer(&mdp->timer);
1423 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
b0ca2a21 1424 setup_timer(&mdp->timer, sh_eth_timer, (unsigned long)ndev);
86a74ff2
NI		 1425
1426 return ret;
1427
1428out_free_irq:
1429 free_irq(ndev->irq, ndev);
bcd5149d 1430 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 1431 return ret;
1432}
1433
1434/* Timeout function */
1435static void sh_eth_tx_timeout(struct net_device *ndev)
1436{
1437 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1438 struct sh_eth_rxdesc *rxdesc;
1439 int i;
1440
1441 netif_stop_queue(ndev);
1442
dc19e4e5
NI		 1443 if (netif_msg_timer(mdp))
1444 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
4a55530f 1445 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
86a74ff2
NI		 1446
1447 /* tx_errors count up */
bb7d92e3 1448 ndev->stats.tx_errors++;
86a74ff2
NI		 1449
1450 /* timer off */
1451 del_timer_sync(&mdp->timer);
1452
1453 /* Free all the skbuffs in the Rx queue. */
1454 for (i = 0; i < RX_RING_SIZE; i++) {
1455 rxdesc = &mdp->rx_ring[i];
1456 rxdesc->status = 0;
1457 rxdesc->addr = 0xBADF00D0;
1458 if (mdp->rx_skbuff[i])
1459 dev_kfree_skb(mdp->rx_skbuff[i]);
1460 mdp->rx_skbuff[i] = NULL;
1461 }
1462 for (i = 0; i < TX_RING_SIZE; i++) {
1463 if (mdp->tx_skbuff[i])
1464 dev_kfree_skb(mdp->tx_skbuff[i]);
1465 mdp->tx_skbuff[i] = NULL;
1466 }
1467
1468 /* device init */
1469 sh_eth_dev_init(ndev);
1470
1471 /* timer on */
1472 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1473 add_timer(&mdp->timer);
1474}
1475
1476/* Packet transmit function */
1477static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1478{
1479 struct sh_eth_private *mdp = netdev_priv(ndev);
1480 struct sh_eth_txdesc *txdesc;
1481 u32 entry;
fb5e2f9b 1482 unsigned long flags;
86a74ff2
NI		 1483
1484 spin_lock_irqsave(&mdp->lock, flags);
1485 if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) {
1486 if (!sh_eth_txfree(ndev)) {
dc19e4e5
NI		 1487 if (netif_msg_tx_queued(mdp))
1488 dev_warn(&ndev->dev, "TxFD exhausted.\n");
86a74ff2
NI		 1489 netif_stop_queue(ndev);
1490 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 1491 return NETDEV_TX_BUSY;
86a74ff2
NI		 1492 }
1493 }
1494 spin_unlock_irqrestore(&mdp->lock, flags);
1495
1496 entry = mdp->cur_tx % TX_RING_SIZE;
1497 mdp->tx_skbuff[entry] = skb;
1498 txdesc = &mdp->tx_ring[entry];
86a74ff2 1499 /* soft swap. */
380af9e3
YS		 1500 if (!mdp->cd->hw_swap)
1501 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1502 skb->len + 2);
31fcb99d
YS		 1503 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
1504 DMA_TO_DEVICE);
86a74ff2
NI		 1505 if (skb->len < ETHERSMALL)
1506 txdesc->buffer_length = ETHERSMALL;
1507 else
1508 txdesc->buffer_length = skb->len;
1509
1510 if (entry >= TX_RING_SIZE - 1)
71557a37 1511 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
86a74ff2 1512 else
71557a37 1513 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
86a74ff2
NI		 1514
1515 mdp->cur_tx++;
1516
c5ed5368
YS		 1517 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
1518 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
b0ca2a21 1519
6ed10654 1520 return NETDEV_TX_OK;
86a74ff2
NI		 1521}
1522
1523/* device close function */
1524static int sh_eth_close(struct net_device *ndev)
1525{
1526 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1527 int ringsize;
1528
1529 netif_stop_queue(ndev);
1530
1531 /* Disable interrupts by clearing the interrupt mask. */
4a55530f 1532 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2
NI		 1533
1534 /* Stop the chip's Tx and Rx processes. */
4a55530f
YS		 1535 sh_eth_write(ndev, 0, EDTRR);
1536 sh_eth_write(ndev, 0, EDRRR);
86a74ff2
NI		 1537
1538 /* PHY Disconnect */
1539 if (mdp->phydev) {
1540 phy_stop(mdp->phydev);
1541 phy_disconnect(mdp->phydev);
1542 }
1543
1544 free_irq(ndev->irq, ndev);
1545
1546 del_timer_sync(&mdp->timer);
1547
1548 /* Free all the skbuffs in the Rx queue. */
1549 sh_eth_ring_free(ndev);
1550
1551 /* free DMA buffer */
1552 ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
1553 dma_free_coherent(NULL, ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1554
1555 /* free DMA buffer */
1556 ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
1557 dma_free_coherent(NULL, ringsize, mdp->tx_ring, mdp->tx_desc_dma);
1558
bcd5149d
MD		 1559 pm_runtime_put_sync(&mdp->pdev->dev);
1560
86a74ff2
NI		 1561 return 0;
1562}
1563
1564static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
1565{
1566 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1567
bcd5149d
MD		 1568 pm_runtime_get_sync(&mdp->pdev->dev);
1569
bb7d92e3 1570 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
4a55530f 1571 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
bb7d92e3 1572 ndev->stats.collisions += sh_eth_read(ndev, CDCR);
4a55530f 1573 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
bb7d92e3 1574 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
4a55530f 1575 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
c5ed5368 1576 if (sh_eth_is_gether(mdp)) {
bb7d92e3 1577 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
c5ed5368 1578 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
bb7d92e3 1579 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
c5ed5368
YS		 1580 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
1581 } else {
bb7d92e3 1582 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
c5ed5368
YS		 1583 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
1584 }
bcd5149d
MD		 1585 pm_runtime_put_sync(&mdp->pdev->dev);
1586
bb7d92e3 1587 return &ndev->stats;
86a74ff2
NI		 1588}
1589
bb7d92e3 1590/* ioctl to device function */
86a74ff2
NI		 1591static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
1592 int cmd)
1593{
1594 struct sh_eth_private *mdp = netdev_priv(ndev);
1595 struct phy_device *phydev = mdp->phydev;
1596
1597 if (!netif_running(ndev))
1598 return -EINVAL;
1599
1600 if (!phydev)
1601 return -ENODEV;
1602
28b04113 1603 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 1604}
1605
380af9e3 1606#if defined(SH_ETH_HAS_TSU)
86a74ff2
NI		 1607/* Multicast reception directions set */
1608static void sh_eth_set_multicast_list(struct net_device *ndev)
1609{
86a74ff2
NI		 1610 if (ndev->flags & IFF_PROMISC) {
1611 /* Set promiscuous. */
4a55530f
YS		 1612 sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_MCT) |
1613 ECMR_PRM, ECMR);
86a74ff2
NI		 1614 } else {
1615 /* Normal, unicast/broadcast-only mode. */
4a55530f
YS		 1616 sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) |
1617 ECMR_MCT, ECMR);
86a74ff2
NI		 1618 }
1619}
4986b996 1620#endif /* SH_ETH_HAS_TSU */
86a74ff2
NI		 1621
1622/* SuperH's TSU register init function */
4a55530f 1623static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 1624{
4a55530f
YS		 1625 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
1626 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
1627 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
1628 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
1629 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
1630 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
1631 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
1632 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
1633 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
1634 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
c5ed5368
YS		 1635 if (sh_eth_is_gether(mdp)) {
1636 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
1637 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
1638 } else {
1639 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
1640 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
1641 }
4a55530f
YS		 1642 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
1643 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
1644 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
1645 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
1646 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
1647 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
1648 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 1649}
1650
1651/* MDIO bus release function */
1652static int sh_mdio_release(struct net_device *ndev)
1653{
1654 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
1655
1656 /* unregister mdio bus */
1657 mdiobus_unregister(bus);
1658
1659 /* remove mdio bus info from net_device */
1660 dev_set_drvdata(&ndev->dev, NULL);
1661
0f0b405c
DK		 1662 /* free interrupts memory */
1663 kfree(bus->irq);
1664
86a74ff2
NI		 1665 /* free bitbang info */
1666 free_mdio_bitbang(bus);
1667
1668 return 0;
1669}
1670
1671/* MDIO bus init function */
b3017e6a
YS		 1672static int sh_mdio_init(struct net_device *ndev, int id,
1673 struct sh_eth_plat_data *pd)
86a74ff2
NI		 1674{
1675 int ret, i;
1676 struct bb_info *bitbang;
1677 struct sh_eth_private *mdp = netdev_priv(ndev);
1678
1679 /* create bit control struct for PHY */
1680 bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
1681 if (!bitbang) {
1682 ret = -ENOMEM;
1683 goto out;
1684 }
1685
1686 /* bitbang init */
ae70644d 1687 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
b3017e6a 1688 bitbang->set_gate = pd->set_mdio_gate;
86a74ff2
NI		 1689 bitbang->mdi_msk = 0x08;
1690 bitbang->mdo_msk = 0x04;
1691 bitbang->mmd_msk = 0x02;/* MMD */
1692 bitbang->mdc_msk = 0x01;
1693 bitbang->ctrl.ops = &bb_ops;
1694
c2e07b3a 1695 /* MII controller setting */
86a74ff2
NI		 1696 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
1697 if (!mdp->mii_bus) {
1698 ret = -ENOMEM;
1699 goto out_free_bitbang;
1700 }
1701
1702 /* Hook up MII support for ethtool */
1703 mdp->mii_bus->name = "sh_mii";
18ee49dd 1704 mdp->mii_bus->parent = &ndev->dev;
5278fb54 1705 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
34aa6f14 1706 mdp->pdev->name, id);
86a74ff2
NI		 1707
1708 /* PHY IRQ */
1709 mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1710 if (!mdp->mii_bus->irq) {
1711 ret = -ENOMEM;
1712 goto out_free_bus;
1713 }
1714
1715 for (i = 0; i < PHY_MAX_ADDR; i++)
1716 mdp->mii_bus->irq[i] = PHY_POLL;
1717
1718 /* regist mdio bus */
1719 ret = mdiobus_register(mdp->mii_bus);
1720 if (ret)
1721 goto out_free_irq;
1722
1723 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
1724
1725 return 0;
1726
1727out_free_irq:
1728 kfree(mdp->mii_bus->irq);
1729
1730out_free_bus:
298cf9be 1731 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 1732
1733out_free_bitbang:
1734 kfree(bitbang);
1735
1736out:
1737 return ret;
1738}
1739
4a55530f
YS		 1740static const u16 *sh_eth_get_register_offset(int register_type)
1741{
1742 const u16 *reg_offset = NULL;
1743
1744 switch (register_type) {
1745 case SH_ETH_REG_GIGABIT:
1746 reg_offset = sh_eth_offset_gigabit;
1747 break;
1748 case SH_ETH_REG_FAST_SH4:
1749 reg_offset = sh_eth_offset_fast_sh4;
1750 break;
1751 case SH_ETH_REG_FAST_SH3_SH2:
1752 reg_offset = sh_eth_offset_fast_sh3_sh2;
1753 break;
1754 default:
1755 printk(KERN_ERR "Unknown register type (%d)\n", register_type);
1756 break;
1757 }
1758
1759 return reg_offset;
1760}
1761
ebf84eaa
AB		 1762static const struct net_device_ops sh_eth_netdev_ops = {
1763 .ndo_open = sh_eth_open,
1764 .ndo_stop = sh_eth_close,
1765 .ndo_start_xmit = sh_eth_start_xmit,
1766 .ndo_get_stats = sh_eth_get_stats,
380af9e3 1767#if defined(SH_ETH_HAS_TSU)
afc4b13d 1768 .ndo_set_rx_mode = sh_eth_set_multicast_list,
380af9e3 1769#endif
ebf84eaa
AB		 1770 .ndo_tx_timeout = sh_eth_tx_timeout,
1771 .ndo_do_ioctl = sh_eth_do_ioctl,
1772 .ndo_validate_addr = eth_validate_addr,
1773 .ndo_set_mac_address = eth_mac_addr,
1774 .ndo_change_mtu = eth_change_mtu,
1775};
1776
86a74ff2
NI		 1777static int sh_eth_drv_probe(struct platform_device *pdev)
1778{
9c38657c 1779 int ret, devno = 0;
86a74ff2
NI		 1780 struct resource *res;
1781 struct net_device *ndev = NULL;
ec0d7551 1782 struct sh_eth_private *mdp = NULL;
71557a37 1783 struct sh_eth_plat_data *pd;
86a74ff2
NI		 1784
1785 /* get base addr */
1786 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1787 if (unlikely(res == NULL)) {
1788 dev_err(&pdev->dev, "invalid resource\n");
1789 ret = -EINVAL;
1790 goto out;
1791 }
1792
1793 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
1794 if (!ndev) {
86a74ff2
NI		 1795 ret = -ENOMEM;
1796 goto out;
1797 }
1798
1799 /* The sh Ether-specific entries in the device structure. */
1800 ndev->base_addr = res->start;
1801 devno = pdev->id;
1802 if (devno < 0)
1803 devno = 0;
1804
1805 ndev->dma = -1;
cc3c080d 1806 ret = platform_get_irq(pdev, 0);
1807 if (ret < 0) {
86a74ff2
NI		 1808 ret = -ENODEV;
1809 goto out_release;
1810 }
cc3c080d 1811 ndev->irq = ret;
86a74ff2
NI		 1812
1813 SET_NETDEV_DEV(ndev, &pdev->dev);
1814
1815 /* Fill in the fields of the device structure with ethernet values. */
1816 ether_setup(ndev);
1817
1818 mdp = netdev_priv(ndev);
ae70644d
YS		 1819 mdp->addr = ioremap(res->start, resource_size(res));
1820 if (mdp->addr == NULL) {
1821 ret = -ENOMEM;
1822 dev_err(&pdev->dev, "ioremap failed.\n");
1823 goto out_release;
1824 }
1825
86a74ff2 1826 spin_lock_init(&mdp->lock);
bcd5149d
MD		 1827 mdp->pdev = pdev;
1828 pm_runtime_enable(&pdev->dev);
1829 pm_runtime_resume(&pdev->dev);
86a74ff2 1830
71557a37 1831 pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data);
86a74ff2 1832 /* get PHY ID */
71557a37 1833 mdp->phy_id = pd->phy;
e47c9052 1834 mdp->phy_interface = pd->phy_interface;
71557a37
YS		 1835 /* EDMAC endian */
1836 mdp->edmac_endian = pd->edmac_endian;
4923576b
YS		 1837 mdp->no_ether_link = pd->no_ether_link;
1838 mdp->ether_link_active_low = pd->ether_link_active_low;
4a55530f 1839 mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
86a74ff2 1840
380af9e3 1841 /* set cpu data */
8fcd4961
YS		 1842#if defined(SH_ETH_HAS_BOTH_MODULES)
1843 mdp->cd = sh_eth_get_cpu_data(mdp);
1844#else
380af9e3 1845 mdp->cd = &sh_eth_my_cpu_data;
8fcd4961 1846#endif
380af9e3
YS		 1847 sh_eth_set_default_cpu_data(mdp->cd);
1848
86a74ff2 1849 /* set function */
ebf84eaa 1850 ndev->netdev_ops = &sh_eth_netdev_ops;
dc19e4e5 1851 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
86a74ff2
NI		 1852 ndev->watchdog_timeo = TX_TIMEOUT;
1853
dc19e4e5
NI		 1854 /* debug message level */
1855 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 1856 mdp->post_rx = POST_RX >> (devno << 1);
1857 mdp->post_fw = POST_FW >> (devno << 1);
1858
1859 /* read and set MAC address */
748031f9 1860 read_mac_address(ndev, pd->mac_addr);
86a74ff2 1861
150647fb
YS		 1862 /* initialize first or needed device */
1863 if (!devno || pd->needs_init) {
4986b996
YS		 1864 if (mdp->cd->tsu) {
1865 struct resource *rtsu;
1866 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1867 if (!rtsu) {
1868 dev_err(&pdev->dev, "Not found TSU resource\n");
1869 goto out_release;
1870 }
1871 mdp->tsu_addr = ioremap(rtsu->start,
1872 resource_size(rtsu));
1873 }
380af9e3
YS		 1874 if (mdp->cd->chip_reset)
1875 mdp->cd->chip_reset(ndev);
86a74ff2 1876
4986b996
YS		 1877 if (mdp->cd->tsu) {
1878 /* TSU init (Init only)*/
1879 sh_eth_tsu_init(mdp);
1880 }
86a74ff2
NI		 1881 }
1882
1883 /* network device register */
1884 ret = register_netdev(ndev);
1885 if (ret)
1886 goto out_release;
1887
1888 /* mdio bus init */
b3017e6a 1889 ret = sh_mdio_init(ndev, pdev->id, pd);
86a74ff2
NI		 1890 if (ret)
1891 goto out_unregister;
1892
25985edc 1893 /* print device information */
6cd9b49d
HS		 1894 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
1895 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2
NI		 1896
1897 platform_set_drvdata(pdev, ndev);
1898
1899 return ret;
1900
1901out_unregister:
1902 unregister_netdev(ndev);
1903
1904out_release:
1905 /* net_dev free */
ae70644d
YS		 1906 if (mdp && mdp->addr)
1907 iounmap(mdp->addr);
ec0d7551 1908 if (mdp && mdp->tsu_addr)
4986b996 1909 iounmap(mdp->tsu_addr);
86a74ff2
NI		 1910 if (ndev)
1911 free_netdev(ndev);
1912
1913out:
1914 return ret;
1915}
1916
1917static int sh_eth_drv_remove(struct platform_device *pdev)
1918{
1919 struct net_device *ndev = platform_get_drvdata(pdev);
4986b996 1920 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1921
4986b996 1922 iounmap(mdp->tsu_addr);
86a74ff2
NI		 1923 sh_mdio_release(ndev);
1924 unregister_netdev(ndev);
bcd5149d 1925 pm_runtime_disable(&pdev->dev);
ae70644d 1926 iounmap(mdp->addr);
86a74ff2
NI		 1927 free_netdev(ndev);
1928 platform_set_drvdata(pdev, NULL);
1929
1930 return 0;
1931}
1932
bcd5149d
MD		 1933static int sh_eth_runtime_nop(struct device *dev)
1934{
1935 /*
1936 * Runtime PM callback shared between ->runtime_suspend()
1937 * and ->runtime_resume(). Simply returns success.
1938 *
1939 * This driver re-initializes all registers after
1940 * pm_runtime_get_sync() anyway so there is no need
1941 * to save and restore registers here.
1942 */
1943 return 0;
1944}
1945
1946static struct dev_pm_ops sh_eth_dev_pm_ops = {
1947 .runtime_suspend = sh_eth_runtime_nop,
1948 .runtime_resume = sh_eth_runtime_nop,
1949};
1950
86a74ff2
NI		 1951static struct platform_driver sh_eth_driver = {
1952 .probe = sh_eth_drv_probe,
1953 .remove = sh_eth_drv_remove,
1954 .driver = {
1955 .name = CARDNAME,
bcd5149d 1956 .pm = &sh_eth_dev_pm_ops,
86a74ff2
NI		 1957 },
1958};
1959
db62f684 1960module_platform_driver(sh_eth_driver);
86a74ff2
NI		 1961
1962MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
1963MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
1964MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)