Commit | Line | Data |
---|---|---|
3590918b YS |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* Renesas Ethernet Switch device driver | |
3 | * | |
4 | * Copyright (C) 2022 Renesas Electronics Corporation | |
5 | */ | |
6 | ||
a0c55bba | 7 | #include <linux/clk.h> |
3590918b YS |
8 | #include <linux/dma-mapping.h> |
9 | #include <linux/err.h> | |
10 | #include <linux/etherdevice.h> | |
11 | #include <linux/iopoll.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/module.h> | |
6c6fa1a0 | 14 | #include <linux/net_tstamp.h> |
3590918b | 15 | #include <linux/of.h> |
3590918b YS |
16 | #include <linux/of_mdio.h> |
17 | #include <linux/of_net.h> | |
3590918b | 18 | #include <linux/phy/phy.h> |
3d40aed8 | 19 | #include <linux/platform_device.h> |
3590918b YS |
20 | #include <linux/pm_runtime.h> |
21 | #include <linux/rtnetlink.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/spinlock.h> | |
c009b903 | 24 | #include <linux/sys_soc.h> |
3590918b YS |
25 | |
26 | #include "rswitch.h" | |
27 | ||
28 | static int rswitch_reg_wait(void __iomem *addr, u32 offs, u32 mask, u32 expected) | |
29 | { | |
30 | u32 val; | |
31 | ||
32 | return readl_poll_timeout_atomic(addr + offs, val, (val & mask) == expected, | |
33 | 1, RSWITCH_TIMEOUT_US); | |
34 | } | |
35 | ||
36 | static void rswitch_modify(void __iomem *addr, enum rswitch_reg reg, u32 clear, u32 set) | |
37 | { | |
38 | iowrite32((ioread32(addr + reg) & ~clear) | set, addr + reg); | |
39 | } | |
40 | ||
41 | /* Common Agent block (COMA) */ | |
42 | static void rswitch_reset(struct rswitch_private *priv) | |
43 | { | |
44 | iowrite32(RRC_RR, priv->addr + RRC); | |
45 | iowrite32(RRC_RR_CLR, priv->addr + RRC); | |
46 | } | |
47 | ||
48 | static void rswitch_clock_enable(struct rswitch_private *priv) | |
49 | { | |
50 | iowrite32(RCEC_ACE_DEFAULT | RCEC_RCE, priv->addr + RCEC); | |
51 | } | |
52 | ||
53 | static void rswitch_clock_disable(struct rswitch_private *priv) | |
54 | { | |
55 | iowrite32(RCDC_RCD, priv->addr + RCDC); | |
56 | } | |
57 | ||
58 | static bool rswitch_agent_clock_is_enabled(void __iomem *coma_addr, int port) | |
59 | { | |
60 | u32 val = ioread32(coma_addr + RCEC); | |
61 | ||
62 | if (val & RCEC_RCE) | |
63 | return (val & BIT(port)) ? true : false; | |
64 | else | |
65 | return false; | |
66 | } | |
67 | ||
68 | static void rswitch_agent_clock_ctrl(void __iomem *coma_addr, int port, int enable) | |
69 | { | |
70 | u32 val; | |
71 | ||
72 | if (enable) { | |
73 | val = ioread32(coma_addr + RCEC); | |
74 | iowrite32(val | RCEC_RCE | BIT(port), coma_addr + RCEC); | |
75 | } else { | |
76 | val = ioread32(coma_addr + RCDC); | |
77 | iowrite32(val | BIT(port), coma_addr + RCDC); | |
78 | } | |
79 | } | |
80 | ||
81 | static int rswitch_bpool_config(struct rswitch_private *priv) | |
82 | { | |
83 | u32 val; | |
84 | ||
85 | val = ioread32(priv->addr + CABPIRM); | |
86 | if (val & CABPIRM_BPR) | |
87 | return 0; | |
88 | ||
89 | iowrite32(CABPIRM_BPIOG, priv->addr + CABPIRM); | |
90 | ||
91 | return rswitch_reg_wait(priv->addr, CABPIRM, CABPIRM_BPR, CABPIRM_BPR); | |
92 | } | |
93 | ||
c87bd91e YS |
94 | static void rswitch_coma_init(struct rswitch_private *priv) |
95 | { | |
96 | iowrite32(CABPPFLC_INIT_VALUE, priv->addr + CABPPFLC0); | |
97 | } | |
98 | ||
3590918b YS |
99 | /* R-Switch-2 block (TOP) */ |
100 | static void rswitch_top_init(struct rswitch_private *priv) | |
101 | { | |
102 | int i; | |
103 | ||
104 | for (i = 0; i < RSWITCH_MAX_NUM_QUEUES; i++) | |
105 | iowrite32((i / 16) << (GWCA_INDEX * 8), priv->addr + TPEMIMC7(i)); | |
106 | } | |
107 | ||
108 | /* Forwarding engine block (MFWD) */ | |
109 | static void rswitch_fwd_init(struct rswitch_private *priv) | |
110 | { | |
111 | int i; | |
112 | ||
113 | /* For ETHA */ | |
114 | for (i = 0; i < RSWITCH_NUM_PORTS; i++) { | |
115 | iowrite32(FWPC0_DEFAULT, priv->addr + FWPC0(i)); | |
116 | iowrite32(0, priv->addr + FWPBFC(i)); | |
117 | } | |
118 | ||
119 | for (i = 0; i < RSWITCH_NUM_PORTS; i++) { | |
120 | iowrite32(priv->rdev[i]->rx_queue->index, | |
121 | priv->addr + FWPBFCSDC(GWCA_INDEX, i)); | |
122 | iowrite32(BIT(priv->gwca.index), priv->addr + FWPBFC(i)); | |
123 | } | |
124 | ||
125 | /* For GWCA */ | |
126 | iowrite32(FWPC0_DEFAULT, priv->addr + FWPC0(priv->gwca.index)); | |
127 | iowrite32(FWPC1_DDE, priv->addr + FWPC1(priv->gwca.index)); | |
128 | iowrite32(0, priv->addr + FWPBFC(priv->gwca.index)); | |
129 | iowrite32(GENMASK(RSWITCH_NUM_PORTS - 1, 0), priv->addr + FWPBFC(priv->gwca.index)); | |
130 | } | |
131 | ||
132 | /* Gateway CPU agent block (GWCA) */ | |
133 | static int rswitch_gwca_change_mode(struct rswitch_private *priv, | |
134 | enum rswitch_gwca_mode mode) | |
135 | { | |
136 | int ret; | |
137 | ||
138 | if (!rswitch_agent_clock_is_enabled(priv->addr, priv->gwca.index)) | |
139 | rswitch_agent_clock_ctrl(priv->addr, priv->gwca.index, 1); | |
140 | ||
141 | iowrite32(mode, priv->addr + GWMC); | |
142 | ||
143 | ret = rswitch_reg_wait(priv->addr, GWMS, GWMS_OPS_MASK, mode); | |
144 | ||
145 | if (mode == GWMC_OPC_DISABLE) | |
146 | rswitch_agent_clock_ctrl(priv->addr, priv->gwca.index, 0); | |
147 | ||
148 | return ret; | |
149 | } | |
150 | ||
151 | static int rswitch_gwca_mcast_table_reset(struct rswitch_private *priv) | |
152 | { | |
153 | iowrite32(GWMTIRM_MTIOG, priv->addr + GWMTIRM); | |
154 | ||
155 | return rswitch_reg_wait(priv->addr, GWMTIRM, GWMTIRM_MTR, GWMTIRM_MTR); | |
156 | } | |
157 | ||
158 | static int rswitch_gwca_axi_ram_reset(struct rswitch_private *priv) | |
159 | { | |
160 | iowrite32(GWARIRM_ARIOG, priv->addr + GWARIRM); | |
161 | ||
162 | return rswitch_reg_wait(priv->addr, GWARIRM, GWARIRM_ARR, GWARIRM_ARR); | |
163 | } | |
164 | ||
3590918b YS |
165 | static bool rswitch_is_any_data_irq(struct rswitch_private *priv, u32 *dis, bool tx) |
166 | { | |
167 | u32 *mask = tx ? priv->gwca.tx_irq_bits : priv->gwca.rx_irq_bits; | |
168 | int i; | |
169 | ||
170 | for (i = 0; i < RSWITCH_NUM_IRQ_REGS; i++) { | |
171 | if (dis[i] & mask[i]) | |
172 | return true; | |
173 | } | |
174 | ||
175 | return false; | |
176 | } | |
177 | ||
178 | static void rswitch_get_data_irq_status(struct rswitch_private *priv, u32 *dis) | |
179 | { | |
180 | int i; | |
181 | ||
182 | for (i = 0; i < RSWITCH_NUM_IRQ_REGS; i++) { | |
183 | dis[i] = ioread32(priv->addr + GWDIS(i)); | |
184 | dis[i] &= ioread32(priv->addr + GWDIE(i)); | |
185 | } | |
186 | } | |
187 | ||
188 | static void rswitch_enadis_data_irq(struct rswitch_private *priv, int index, bool enable) | |
189 | { | |
190 | u32 offs = enable ? GWDIE(index / 32) : GWDID(index / 32); | |
191 | ||
192 | iowrite32(BIT(index % 32), priv->addr + offs); | |
193 | } | |
194 | ||
195 | static void rswitch_ack_data_irq(struct rswitch_private *priv, int index) | |
196 | { | |
197 | u32 offs = GWDIS(index / 32); | |
198 | ||
199 | iowrite32(BIT(index % 32), priv->addr + offs); | |
200 | } | |
201 | ||
380f9acd | 202 | static int rswitch_next_queue_index(struct rswitch_gwca_queue *gq, bool cur, int num) |
3590918b | 203 | { |
380f9acd | 204 | int index = cur ? gq->cur : gq->dirty; |
3590918b YS |
205 | |
206 | if (index + num >= gq->ring_size) | |
207 | index = (index + num) % gq->ring_size; | |
208 | else | |
209 | index += num; | |
210 | ||
211 | return index; | |
212 | } | |
213 | ||
380f9acd | 214 | static int rswitch_get_num_cur_queues(struct rswitch_gwca_queue *gq) |
3590918b YS |
215 | { |
216 | if (gq->cur >= gq->dirty) | |
217 | return gq->cur - gq->dirty; | |
218 | else | |
219 | return gq->ring_size - gq->dirty + gq->cur; | |
220 | } | |
221 | ||
222 | static bool rswitch_is_queue_rxed(struct rswitch_gwca_queue *gq) | |
223 | { | |
251eadcc | 224 | struct rswitch_ext_ts_desc *desc = &gq->rx_ring[gq->dirty]; |
3590918b YS |
225 | |
226 | if ((desc->desc.die_dt & DT_MASK) != DT_FEMPTY) | |
227 | return true; | |
228 | ||
229 | return false; | |
230 | } | |
231 | ||
232 | static int rswitch_gwca_queue_alloc_skb(struct rswitch_gwca_queue *gq, | |
380f9acd | 233 | int start_index, int num) |
3590918b | 234 | { |
380f9acd | 235 | int i, index; |
3590918b YS |
236 | |
237 | for (i = 0; i < num; i++) { | |
238 | index = (i + start_index) % gq->ring_size; | |
239 | if (gq->skbs[index]) | |
240 | continue; | |
241 | gq->skbs[index] = netdev_alloc_skb_ip_align(gq->ndev, | |
242 | PKT_BUF_SZ + RSWITCH_ALIGN - 1); | |
243 | if (!gq->skbs[index]) | |
244 | goto err; | |
245 | } | |
246 | ||
247 | return 0; | |
248 | ||
249 | err: | |
250 | for (i--; i >= 0; i--) { | |
251 | index = (i + start_index) % gq->ring_size; | |
252 | dev_kfree_skb(gq->skbs[index]); | |
253 | gq->skbs[index] = NULL; | |
254 | } | |
255 | ||
256 | return -ENOMEM; | |
257 | } | |
258 | ||
259 | static void rswitch_gwca_queue_free(struct net_device *ndev, | |
260 | struct rswitch_gwca_queue *gq) | |
261 | { | |
262 | int i; | |
263 | ||
48cf0a25 | 264 | if (!gq->dir_tx) { |
3590918b YS |
265 | dma_free_coherent(ndev->dev.parent, |
266 | sizeof(struct rswitch_ext_ts_desc) * | |
251eadcc YS |
267 | (gq->ring_size + 1), gq->rx_ring, gq->ring_dma); |
268 | gq->rx_ring = NULL; | |
48cf0a25 YS |
269 | |
270 | for (i = 0; i < gq->ring_size; i++) | |
271 | dev_kfree_skb(gq->skbs[i]); | |
3590918b YS |
272 | } else { |
273 | dma_free_coherent(ndev->dev.parent, | |
274 | sizeof(struct rswitch_ext_desc) * | |
251eadcc YS |
275 | (gq->ring_size + 1), gq->tx_ring, gq->ring_dma); |
276 | gq->tx_ring = NULL; | |
3590918b YS |
277 | } |
278 | ||
3590918b YS |
279 | kfree(gq->skbs); |
280 | gq->skbs = NULL; | |
281 | } | |
282 | ||
33f5d733 YS |
283 | static void rswitch_gwca_ts_queue_free(struct rswitch_private *priv) |
284 | { | |
285 | struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue; | |
286 | ||
287 | dma_free_coherent(&priv->pdev->dev, | |
288 | sizeof(struct rswitch_ts_desc) * (gq->ring_size + 1), | |
289 | gq->ts_ring, gq->ring_dma); | |
290 | gq->ts_ring = NULL; | |
291 | } | |
292 | ||
3590918b YS |
293 | static int rswitch_gwca_queue_alloc(struct net_device *ndev, |
294 | struct rswitch_private *priv, | |
295 | struct rswitch_gwca_queue *gq, | |
48cf0a25 | 296 | bool dir_tx, int ring_size) |
3590918b YS |
297 | { |
298 | int i, bit; | |
299 | ||
300 | gq->dir_tx = dir_tx; | |
3590918b YS |
301 | gq->ring_size = ring_size; |
302 | gq->ndev = ndev; | |
303 | ||
304 | gq->skbs = kcalloc(gq->ring_size, sizeof(*gq->skbs), GFP_KERNEL); | |
305 | if (!gq->skbs) | |
306 | return -ENOMEM; | |
307 | ||
48cf0a25 | 308 | if (!dir_tx) { |
3590918b YS |
309 | rswitch_gwca_queue_alloc_skb(gq, 0, gq->ring_size); |
310 | ||
251eadcc | 311 | gq->rx_ring = dma_alloc_coherent(ndev->dev.parent, |
3590918b YS |
312 | sizeof(struct rswitch_ext_ts_desc) * |
313 | (gq->ring_size + 1), &gq->ring_dma, GFP_KERNEL); | |
48cf0a25 | 314 | } else { |
251eadcc YS |
315 | gq->tx_ring = dma_alloc_coherent(ndev->dev.parent, |
316 | sizeof(struct rswitch_ext_desc) * | |
317 | (gq->ring_size + 1), &gq->ring_dma, GFP_KERNEL); | |
48cf0a25 YS |
318 | } |
319 | ||
251eadcc | 320 | if (!gq->rx_ring && !gq->tx_ring) |
3590918b YS |
321 | goto out; |
322 | ||
323 | i = gq->index / 32; | |
324 | bit = BIT(gq->index % 32); | |
325 | if (dir_tx) | |
326 | priv->gwca.tx_irq_bits[i] |= bit; | |
327 | else | |
328 | priv->gwca.rx_irq_bits[i] |= bit; | |
329 | ||
330 | return 0; | |
331 | ||
332 | out: | |
333 | rswitch_gwca_queue_free(ndev, gq); | |
334 | ||
335 | return -ENOMEM; | |
336 | } | |
337 | ||
338 | static void rswitch_desc_set_dptr(struct rswitch_desc *desc, dma_addr_t addr) | |
339 | { | |
340 | desc->dptrl = cpu_to_le32(lower_32_bits(addr)); | |
341 | desc->dptrh = upper_32_bits(addr) & 0xff; | |
342 | } | |
343 | ||
344 | static dma_addr_t rswitch_desc_get_dptr(const struct rswitch_desc *desc) | |
345 | { | |
346 | return __le32_to_cpu(desc->dptrl) | (u64)(desc->dptrh) << 32; | |
347 | } | |
348 | ||
349 | static int rswitch_gwca_queue_format(struct net_device *ndev, | |
350 | struct rswitch_private *priv, | |
351 | struct rswitch_gwca_queue *gq) | |
352 | { | |
251eadcc | 353 | int ring_size = sizeof(struct rswitch_ext_desc) * gq->ring_size; |
3590918b YS |
354 | struct rswitch_ext_desc *desc; |
355 | struct rswitch_desc *linkfix; | |
356 | dma_addr_t dma_addr; | |
357 | int i; | |
358 | ||
251eadcc YS |
359 | memset(gq->tx_ring, 0, ring_size); |
360 | for (i = 0, desc = gq->tx_ring; i < gq->ring_size; i++, desc++) { | |
3590918b YS |
361 | if (!gq->dir_tx) { |
362 | dma_addr = dma_map_single(ndev->dev.parent, | |
363 | gq->skbs[i]->data, PKT_BUF_SZ, | |
364 | DMA_FROM_DEVICE); | |
365 | if (dma_mapping_error(ndev->dev.parent, dma_addr)) | |
366 | goto err; | |
367 | ||
368 | desc->desc.info_ds = cpu_to_le16(PKT_BUF_SZ); | |
369 | rswitch_desc_set_dptr(&desc->desc, dma_addr); | |
370 | desc->desc.die_dt = DT_FEMPTY | DIE; | |
371 | } else { | |
372 | desc->desc.die_dt = DT_EEMPTY | DIE; | |
373 | } | |
374 | } | |
375 | rswitch_desc_set_dptr(&desc->desc, gq->ring_dma); | |
376 | desc->desc.die_dt = DT_LINKFIX; | |
377 | ||
e3f38039 | 378 | linkfix = &priv->gwca.linkfix_table[gq->index]; |
3590918b YS |
379 | linkfix->die_dt = DT_LINKFIX; |
380 | rswitch_desc_set_dptr(linkfix, gq->ring_dma); | |
381 | ||
c87bd91e | 382 | iowrite32(GWDCC_BALR | (gq->dir_tx ? GWDCC_DCP(GWCA_IPV_NUM) | GWDCC_DQT : 0) | GWDCC_EDE, |
3590918b YS |
383 | priv->addr + GWDCC_OFFS(gq->index)); |
384 | ||
385 | return 0; | |
386 | ||
387 | err: | |
388 | if (!gq->dir_tx) { | |
251eadcc | 389 | for (i--, desc = gq->tx_ring; i >= 0; i--, desc++) { |
3590918b YS |
390 | dma_addr = rswitch_desc_get_dptr(&desc->desc); |
391 | dma_unmap_single(ndev->dev.parent, dma_addr, PKT_BUF_SZ, | |
392 | DMA_FROM_DEVICE); | |
393 | } | |
394 | } | |
395 | ||
396 | return -ENOMEM; | |
397 | } | |
398 | ||
33f5d733 YS |
399 | static void rswitch_gwca_ts_queue_fill(struct rswitch_private *priv, |
400 | int start_index, int num) | |
401 | { | |
402 | struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue; | |
403 | struct rswitch_ts_desc *desc; | |
404 | int i, index; | |
405 | ||
406 | for (i = 0; i < num; i++) { | |
407 | index = (i + start_index) % gq->ring_size; | |
408 | desc = &gq->ts_ring[index]; | |
409 | desc->desc.die_dt = DT_FEMPTY_ND | DIE; | |
410 | } | |
411 | } | |
412 | ||
251eadcc YS |
413 | static int rswitch_gwca_queue_ext_ts_fill(struct net_device *ndev, |
414 | struct rswitch_gwca_queue *gq, | |
415 | int start_index, int num) | |
3590918b YS |
416 | { |
417 | struct rswitch_device *rdev = netdev_priv(ndev); | |
418 | struct rswitch_ext_ts_desc *desc; | |
419 | dma_addr_t dma_addr; | |
380f9acd | 420 | int i, index; |
3590918b YS |
421 | |
422 | for (i = 0; i < num; i++) { | |
423 | index = (i + start_index) % gq->ring_size; | |
251eadcc | 424 | desc = &gq->rx_ring[index]; |
3590918b YS |
425 | if (!gq->dir_tx) { |
426 | dma_addr = dma_map_single(ndev->dev.parent, | |
427 | gq->skbs[index]->data, PKT_BUF_SZ, | |
428 | DMA_FROM_DEVICE); | |
429 | if (dma_mapping_error(ndev->dev.parent, dma_addr)) | |
430 | goto err; | |
431 | ||
432 | desc->desc.info_ds = cpu_to_le16(PKT_BUF_SZ); | |
433 | rswitch_desc_set_dptr(&desc->desc, dma_addr); | |
434 | dma_wmb(); | |
435 | desc->desc.die_dt = DT_FEMPTY | DIE; | |
436 | desc->info1 = cpu_to_le64(INFO1_SPN(rdev->etha->index)); | |
437 | } else { | |
438 | desc->desc.die_dt = DT_EEMPTY | DIE; | |
439 | } | |
440 | } | |
441 | ||
442 | return 0; | |
443 | ||
444 | err: | |
445 | if (!gq->dir_tx) { | |
446 | for (i--; i >= 0; i--) { | |
447 | index = (i + start_index) % gq->ring_size; | |
251eadcc | 448 | desc = &gq->rx_ring[index]; |
3590918b YS |
449 | dma_addr = rswitch_desc_get_dptr(&desc->desc); |
450 | dma_unmap_single(ndev->dev.parent, dma_addr, PKT_BUF_SZ, | |
451 | DMA_FROM_DEVICE); | |
452 | } | |
453 | } | |
454 | ||
455 | return -ENOMEM; | |
456 | } | |
457 | ||
251eadcc YS |
458 | static int rswitch_gwca_queue_ext_ts_format(struct net_device *ndev, |
459 | struct rswitch_private *priv, | |
460 | struct rswitch_gwca_queue *gq) | |
3590918b | 461 | { |
251eadcc | 462 | int ring_size = sizeof(struct rswitch_ext_ts_desc) * gq->ring_size; |
3590918b YS |
463 | struct rswitch_ext_ts_desc *desc; |
464 | struct rswitch_desc *linkfix; | |
465 | int err; | |
466 | ||
251eadcc YS |
467 | memset(gq->rx_ring, 0, ring_size); |
468 | err = rswitch_gwca_queue_ext_ts_fill(ndev, gq, 0, gq->ring_size); | |
3590918b YS |
469 | if (err < 0) |
470 | return err; | |
471 | ||
251eadcc | 472 | desc = &gq->rx_ring[gq->ring_size]; /* Last */ |
3590918b YS |
473 | rswitch_desc_set_dptr(&desc->desc, gq->ring_dma); |
474 | desc->desc.die_dt = DT_LINKFIX; | |
475 | ||
e3f38039 | 476 | linkfix = &priv->gwca.linkfix_table[gq->index]; |
3590918b YS |
477 | linkfix->die_dt = DT_LINKFIX; |
478 | rswitch_desc_set_dptr(linkfix, gq->ring_dma); | |
479 | ||
c87bd91e YS |
480 | iowrite32(GWDCC_BALR | (gq->dir_tx ? GWDCC_DCP(GWCA_IPV_NUM) | GWDCC_DQT : 0) | |
481 | GWDCC_ETS | GWDCC_EDE, | |
3590918b YS |
482 | priv->addr + GWDCC_OFFS(gq->index)); |
483 | ||
484 | return 0; | |
485 | } | |
486 | ||
e3f38039 | 487 | static int rswitch_gwca_linkfix_alloc(struct rswitch_private *priv) |
3590918b YS |
488 | { |
489 | int i, num_queues = priv->gwca.num_queues; | |
e3f38039 | 490 | struct rswitch_gwca *gwca = &priv->gwca; |
3590918b YS |
491 | struct device *dev = &priv->pdev->dev; |
492 | ||
e3f38039 YS |
493 | gwca->linkfix_table_size = sizeof(struct rswitch_desc) * num_queues; |
494 | gwca->linkfix_table = dma_alloc_coherent(dev, gwca->linkfix_table_size, | |
495 | &gwca->linkfix_table_dma, GFP_KERNEL); | |
496 | if (!gwca->linkfix_table) | |
3590918b YS |
497 | return -ENOMEM; |
498 | for (i = 0; i < num_queues; i++) | |
e3f38039 | 499 | gwca->linkfix_table[i].die_dt = DT_EOS; |
3590918b YS |
500 | |
501 | return 0; | |
502 | } | |
503 | ||
e3f38039 | 504 | static void rswitch_gwca_linkfix_free(struct rswitch_private *priv) |
3590918b | 505 | { |
e3f38039 YS |
506 | struct rswitch_gwca *gwca = &priv->gwca; |
507 | ||
508 | if (gwca->linkfix_table) | |
509 | dma_free_coherent(&priv->pdev->dev, gwca->linkfix_table_size, | |
510 | gwca->linkfix_table, gwca->linkfix_table_dma); | |
511 | gwca->linkfix_table = NULL; | |
3590918b YS |
512 | } |
513 | ||
0ad4982c YS |
514 | static int rswitch_gwca_ts_queue_alloc(struct rswitch_private *priv) |
515 | { | |
516 | struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue; | |
517 | struct rswitch_ts_desc *desc; | |
518 | ||
519 | gq->ring_size = TS_RING_SIZE; | |
520 | gq->ts_ring = dma_alloc_coherent(&priv->pdev->dev, | |
521 | sizeof(struct rswitch_ts_desc) * | |
522 | (gq->ring_size + 1), &gq->ring_dma, GFP_KERNEL); | |
523 | ||
524 | if (!gq->ts_ring) | |
525 | return -ENOMEM; | |
526 | ||
527 | rswitch_gwca_ts_queue_fill(priv, 0, TS_RING_SIZE); | |
528 | desc = &gq->ts_ring[gq->ring_size]; | |
529 | desc->desc.die_dt = DT_LINKFIX; | |
530 | rswitch_desc_set_dptr(&desc->desc, gq->ring_dma); | |
531 | INIT_LIST_HEAD(&priv->gwca.ts_info_list); | |
532 | ||
533 | return 0; | |
534 | } | |
535 | ||
3590918b YS |
536 | static struct rswitch_gwca_queue *rswitch_gwca_get(struct rswitch_private *priv) |
537 | { | |
538 | struct rswitch_gwca_queue *gq; | |
539 | int index; | |
540 | ||
541 | index = find_first_zero_bit(priv->gwca.used, priv->gwca.num_queues); | |
542 | if (index >= priv->gwca.num_queues) | |
543 | return NULL; | |
544 | set_bit(index, priv->gwca.used); | |
545 | gq = &priv->gwca.queues[index]; | |
546 | memset(gq, 0, sizeof(*gq)); | |
547 | gq->index = index; | |
548 | ||
549 | return gq; | |
550 | } | |
551 | ||
552 | static void rswitch_gwca_put(struct rswitch_private *priv, | |
553 | struct rswitch_gwca_queue *gq) | |
554 | { | |
555 | clear_bit(gq->index, priv->gwca.used); | |
556 | } | |
557 | ||
558 | static int rswitch_txdmac_alloc(struct net_device *ndev) | |
559 | { | |
560 | struct rswitch_device *rdev = netdev_priv(ndev); | |
561 | struct rswitch_private *priv = rdev->priv; | |
562 | int err; | |
563 | ||
564 | rdev->tx_queue = rswitch_gwca_get(priv); | |
565 | if (!rdev->tx_queue) | |
566 | return -EBUSY; | |
567 | ||
48cf0a25 | 568 | err = rswitch_gwca_queue_alloc(ndev, priv, rdev->tx_queue, true, TX_RING_SIZE); |
3590918b YS |
569 | if (err < 0) { |
570 | rswitch_gwca_put(priv, rdev->tx_queue); | |
571 | return err; | |
572 | } | |
573 | ||
574 | return 0; | |
575 | } | |
576 | ||
577 | static void rswitch_txdmac_free(struct net_device *ndev) | |
578 | { | |
579 | struct rswitch_device *rdev = netdev_priv(ndev); | |
580 | ||
581 | rswitch_gwca_queue_free(ndev, rdev->tx_queue); | |
582 | rswitch_gwca_put(rdev->priv, rdev->tx_queue); | |
583 | } | |
584 | ||
585 | static int rswitch_txdmac_init(struct rswitch_private *priv, int index) | |
586 | { | |
587 | struct rswitch_device *rdev = priv->rdev[index]; | |
588 | ||
589 | return rswitch_gwca_queue_format(rdev->ndev, priv, rdev->tx_queue); | |
590 | } | |
591 | ||
592 | static int rswitch_rxdmac_alloc(struct net_device *ndev) | |
593 | { | |
594 | struct rswitch_device *rdev = netdev_priv(ndev); | |
595 | struct rswitch_private *priv = rdev->priv; | |
596 | int err; | |
597 | ||
598 | rdev->rx_queue = rswitch_gwca_get(priv); | |
599 | if (!rdev->rx_queue) | |
600 | return -EBUSY; | |
601 | ||
48cf0a25 | 602 | err = rswitch_gwca_queue_alloc(ndev, priv, rdev->rx_queue, false, RX_RING_SIZE); |
3590918b YS |
603 | if (err < 0) { |
604 | rswitch_gwca_put(priv, rdev->rx_queue); | |
605 | return err; | |
606 | } | |
607 | ||
608 | return 0; | |
609 | } | |
610 | ||
611 | static void rswitch_rxdmac_free(struct net_device *ndev) | |
612 | { | |
613 | struct rswitch_device *rdev = netdev_priv(ndev); | |
614 | ||
615 | rswitch_gwca_queue_free(ndev, rdev->rx_queue); | |
616 | rswitch_gwca_put(rdev->priv, rdev->rx_queue); | |
617 | } | |
618 | ||
619 | static int rswitch_rxdmac_init(struct rswitch_private *priv, int index) | |
620 | { | |
621 | struct rswitch_device *rdev = priv->rdev[index]; | |
622 | struct net_device *ndev = rdev->ndev; | |
623 | ||
251eadcc | 624 | return rswitch_gwca_queue_ext_ts_format(ndev, priv, rdev->rx_queue); |
3590918b YS |
625 | } |
626 | ||
627 | static int rswitch_gwca_hw_init(struct rswitch_private *priv) | |
628 | { | |
629 | int i, err; | |
630 | ||
631 | err = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); | |
632 | if (err < 0) | |
633 | return err; | |
634 | err = rswitch_gwca_change_mode(priv, GWMC_OPC_CONFIG); | |
635 | if (err < 0) | |
636 | return err; | |
637 | ||
638 | err = rswitch_gwca_mcast_table_reset(priv); | |
639 | if (err < 0) | |
640 | return err; | |
641 | err = rswitch_gwca_axi_ram_reset(priv); | |
642 | if (err < 0) | |
643 | return err; | |
644 | ||
645 | iowrite32(GWVCC_VEM_SC_TAG, priv->addr + GWVCC); | |
646 | iowrite32(0, priv->addr + GWTTFC); | |
e3f38039 YS |
647 | iowrite32(lower_32_bits(priv->gwca.linkfix_table_dma), priv->addr + GWDCBAC1); |
648 | iowrite32(upper_32_bits(priv->gwca.linkfix_table_dma), priv->addr + GWDCBAC0); | |
33f5d733 YS |
649 | iowrite32(lower_32_bits(priv->gwca.ts_queue.ring_dma), priv->addr + GWTDCAC10); |
650 | iowrite32(upper_32_bits(priv->gwca.ts_queue.ring_dma), priv->addr + GWTDCAC00); | |
651 | iowrite32(GWCA_TS_IRQ_BIT, priv->addr + GWTSDCC0); | |
c87bd91e YS |
652 | |
653 | iowrite32(GWTPC_PPPL(GWCA_IPV_NUM), priv->addr + GWTPC0); | |
3590918b YS |
654 | |
655 | for (i = 0; i < RSWITCH_NUM_PORTS; i++) { | |
656 | err = rswitch_rxdmac_init(priv, i); | |
657 | if (err < 0) | |
658 | return err; | |
659 | err = rswitch_txdmac_init(priv, i); | |
660 | if (err < 0) | |
661 | return err; | |
662 | } | |
663 | ||
664 | err = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); | |
665 | if (err < 0) | |
666 | return err; | |
667 | return rswitch_gwca_change_mode(priv, GWMC_OPC_OPERATION); | |
668 | } | |
669 | ||
670 | static int rswitch_gwca_hw_deinit(struct rswitch_private *priv) | |
671 | { | |
672 | int err; | |
673 | ||
674 | err = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); | |
675 | if (err < 0) | |
676 | return err; | |
677 | err = rswitch_gwca_change_mode(priv, GWMC_OPC_RESET); | |
678 | if (err < 0) | |
679 | return err; | |
680 | ||
681 | return rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); | |
682 | } | |
683 | ||
684 | static int rswitch_gwca_halt(struct rswitch_private *priv) | |
685 | { | |
686 | int err; | |
687 | ||
688 | priv->gwca_halt = true; | |
689 | err = rswitch_gwca_hw_deinit(priv); | |
690 | dev_err(&priv->pdev->dev, "halted (%d)\n", err); | |
691 | ||
692 | return err; | |
693 | } | |
694 | ||
695 | static bool rswitch_rx(struct net_device *ndev, int *quota) | |
696 | { | |
697 | struct rswitch_device *rdev = netdev_priv(ndev); | |
698 | struct rswitch_gwca_queue *gq = rdev->rx_queue; | |
699 | struct rswitch_ext_ts_desc *desc; | |
700 | int limit, boguscnt, num, ret; | |
701 | struct sk_buff *skb; | |
702 | dma_addr_t dma_addr; | |
703 | u16 pkt_len; | |
6c6fa1a0 | 704 | u32 get_ts; |
3590918b | 705 | |
e05bb97d YS |
706 | if (*quota <= 0) |
707 | return true; | |
708 | ||
3590918b YS |
709 | boguscnt = min_t(int, gq->ring_size, *quota); |
710 | limit = boguscnt; | |
711 | ||
251eadcc | 712 | desc = &gq->rx_ring[gq->cur]; |
3590918b | 713 | while ((desc->desc.die_dt & DT_MASK) != DT_FEMPTY) { |
3590918b YS |
714 | dma_rmb(); |
715 | pkt_len = le16_to_cpu(desc->desc.info_ds) & RX_DS; | |
716 | skb = gq->skbs[gq->cur]; | |
717 | gq->skbs[gq->cur] = NULL; | |
718 | dma_addr = rswitch_desc_get_dptr(&desc->desc); | |
719 | dma_unmap_single(ndev->dev.parent, dma_addr, PKT_BUF_SZ, DMA_FROM_DEVICE); | |
6c6fa1a0 YS |
720 | get_ts = rdev->priv->ptp_priv->tstamp_rx_ctrl & RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT; |
721 | if (get_ts) { | |
722 | struct skb_shared_hwtstamps *shhwtstamps; | |
723 | struct timespec64 ts; | |
724 | ||
725 | shhwtstamps = skb_hwtstamps(skb); | |
726 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); | |
727 | ts.tv_sec = __le32_to_cpu(desc->ts_sec); | |
728 | ts.tv_nsec = __le32_to_cpu(desc->ts_nsec & cpu_to_le32(0x3fffffff)); | |
729 | shhwtstamps->hwtstamp = timespec64_to_ktime(ts); | |
730 | } | |
3590918b YS |
731 | skb_put(skb, pkt_len); |
732 | skb->protocol = eth_type_trans(skb, ndev); | |
dc510c6d | 733 | napi_gro_receive(&rdev->napi, skb); |
3590918b YS |
734 | rdev->ndev->stats.rx_packets++; |
735 | rdev->ndev->stats.rx_bytes += pkt_len; | |
736 | ||
737 | gq->cur = rswitch_next_queue_index(gq, true, 1); | |
251eadcc | 738 | desc = &gq->rx_ring[gq->cur]; |
e05bb97d YS |
739 | |
740 | if (--boguscnt <= 0) | |
741 | break; | |
3590918b YS |
742 | } |
743 | ||
744 | num = rswitch_get_num_cur_queues(gq); | |
745 | ret = rswitch_gwca_queue_alloc_skb(gq, gq->dirty, num); | |
746 | if (ret < 0) | |
747 | goto err; | |
251eadcc | 748 | ret = rswitch_gwca_queue_ext_ts_fill(ndev, gq, gq->dirty, num); |
3590918b YS |
749 | if (ret < 0) |
750 | goto err; | |
751 | gq->dirty = rswitch_next_queue_index(gq, false, num); | |
752 | ||
e05bb97d | 753 | *quota -= limit - boguscnt; |
3590918b YS |
754 | |
755 | return boguscnt <= 0; | |
756 | ||
757 | err: | |
758 | rswitch_gwca_halt(rdev->priv); | |
759 | ||
760 | return 0; | |
761 | } | |
762 | ||
763 | static int rswitch_tx_free(struct net_device *ndev, bool free_txed_only) | |
764 | { | |
765 | struct rswitch_device *rdev = netdev_priv(ndev); | |
766 | struct rswitch_gwca_queue *gq = rdev->tx_queue; | |
767 | struct rswitch_ext_desc *desc; | |
768 | dma_addr_t dma_addr; | |
769 | struct sk_buff *skb; | |
770 | int free_num = 0; | |
771 | int size; | |
772 | ||
380f9acd YS |
773 | for (; rswitch_get_num_cur_queues(gq) > 0; |
774 | gq->dirty = rswitch_next_queue_index(gq, false, 1)) { | |
251eadcc | 775 | desc = &gq->tx_ring[gq->dirty]; |
3590918b YS |
776 | if (free_txed_only && (desc->desc.die_dt & DT_MASK) != DT_FEMPTY) |
777 | break; | |
778 | ||
779 | dma_rmb(); | |
780 | size = le16_to_cpu(desc->desc.info_ds) & TX_DS; | |
781 | skb = gq->skbs[gq->dirty]; | |
782 | if (skb) { | |
783 | dma_addr = rswitch_desc_get_dptr(&desc->desc); | |
784 | dma_unmap_single(ndev->dev.parent, dma_addr, | |
785 | size, DMA_TO_DEVICE); | |
786 | dev_kfree_skb_any(gq->skbs[gq->dirty]); | |
787 | gq->skbs[gq->dirty] = NULL; | |
788 | free_num++; | |
789 | } | |
790 | desc->desc.die_dt = DT_EEMPTY; | |
791 | rdev->ndev->stats.tx_packets++; | |
792 | rdev->ndev->stats.tx_bytes += size; | |
793 | } | |
794 | ||
795 | return free_num; | |
796 | } | |
797 | ||
798 | static int rswitch_poll(struct napi_struct *napi, int budget) | |
799 | { | |
800 | struct net_device *ndev = napi->dev; | |
801 | struct rswitch_private *priv; | |
802 | struct rswitch_device *rdev; | |
c4f922e8 | 803 | unsigned long flags; |
3590918b YS |
804 | int quota = budget; |
805 | ||
806 | rdev = netdev_priv(ndev); | |
807 | priv = rdev->priv; | |
808 | ||
809 | retry: | |
810 | rswitch_tx_free(ndev, true); | |
811 | ||
812 | if (rswitch_rx(ndev, "a)) | |
813 | goto out; | |
814 | else if (rdev->priv->gwca_halt) | |
815 | goto err; | |
816 | else if (rswitch_is_queue_rxed(rdev->rx_queue)) | |
817 | goto retry; | |
818 | ||
819 | netif_wake_subqueue(ndev, 0); | |
820 | ||
e7b1ef29 | 821 | if (napi_complete_done(napi, budget - quota)) { |
c4f922e8 | 822 | spin_lock_irqsave(&priv->lock, flags); |
e7b1ef29 YS |
823 | rswitch_enadis_data_irq(priv, rdev->tx_queue->index, true); |
824 | rswitch_enadis_data_irq(priv, rdev->rx_queue->index, true); | |
c4f922e8 | 825 | spin_unlock_irqrestore(&priv->lock, flags); |
e7b1ef29 | 826 | } |
3590918b YS |
827 | |
828 | out: | |
829 | return budget - quota; | |
830 | ||
831 | err: | |
832 | napi_complete(napi); | |
833 | ||
834 | return 0; | |
835 | } | |
836 | ||
837 | static void rswitch_queue_interrupt(struct net_device *ndev) | |
838 | { | |
839 | struct rswitch_device *rdev = netdev_priv(ndev); | |
840 | ||
841 | if (napi_schedule_prep(&rdev->napi)) { | |
c4f922e8 | 842 | spin_lock(&rdev->priv->lock); |
3590918b YS |
843 | rswitch_enadis_data_irq(rdev->priv, rdev->tx_queue->index, false); |
844 | rswitch_enadis_data_irq(rdev->priv, rdev->rx_queue->index, false); | |
c4f922e8 | 845 | spin_unlock(&rdev->priv->lock); |
3590918b YS |
846 | __napi_schedule(&rdev->napi); |
847 | } | |
848 | } | |
849 | ||
850 | static irqreturn_t rswitch_data_irq(struct rswitch_private *priv, u32 *dis) | |
851 | { | |
852 | struct rswitch_gwca_queue *gq; | |
853 | int i, index, bit; | |
854 | ||
855 | for (i = 0; i < priv->gwca.num_queues; i++) { | |
856 | gq = &priv->gwca.queues[i]; | |
857 | index = gq->index / 32; | |
858 | bit = BIT(gq->index % 32); | |
859 | if (!(dis[index] & bit)) | |
860 | continue; | |
861 | ||
862 | rswitch_ack_data_irq(priv, gq->index); | |
863 | rswitch_queue_interrupt(gq->ndev); | |
864 | } | |
865 | ||
866 | return IRQ_HANDLED; | |
867 | } | |
868 | ||
869 | static irqreturn_t rswitch_gwca_irq(int irq, void *dev_id) | |
870 | { | |
871 | struct rswitch_private *priv = dev_id; | |
872 | u32 dis[RSWITCH_NUM_IRQ_REGS]; | |
873 | irqreturn_t ret = IRQ_NONE; | |
874 | ||
875 | rswitch_get_data_irq_status(priv, dis); | |
876 | ||
877 | if (rswitch_is_any_data_irq(priv, dis, true) || | |
878 | rswitch_is_any_data_irq(priv, dis, false)) | |
879 | ret = rswitch_data_irq(priv, dis); | |
880 | ||
881 | return ret; | |
882 | } | |
883 | ||
884 | static int rswitch_gwca_request_irqs(struct rswitch_private *priv) | |
885 | { | |
886 | char *resource_name, *irq_name; | |
887 | int i, ret, irq; | |
888 | ||
889 | for (i = 0; i < GWCA_NUM_IRQS; i++) { | |
890 | resource_name = kasprintf(GFP_KERNEL, GWCA_IRQ_RESOURCE_NAME, i); | |
891 | if (!resource_name) | |
892 | return -ENOMEM; | |
893 | ||
894 | irq = platform_get_irq_byname(priv->pdev, resource_name); | |
895 | kfree(resource_name); | |
896 | if (irq < 0) | |
897 | return irq; | |
898 | ||
899 | irq_name = devm_kasprintf(&priv->pdev->dev, GFP_KERNEL, | |
900 | GWCA_IRQ_NAME, i); | |
901 | if (!irq_name) | |
902 | return -ENOMEM; | |
903 | ||
904 | ret = devm_request_irq(&priv->pdev->dev, irq, rswitch_gwca_irq, | |
905 | 0, irq_name, priv); | |
906 | if (ret < 0) | |
907 | return ret; | |
908 | } | |
909 | ||
910 | return 0; | |
911 | } | |
912 | ||
33f5d733 YS |
913 | static void rswitch_ts(struct rswitch_private *priv) |
914 | { | |
915 | struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue; | |
916 | struct rswitch_gwca_ts_info *ts_info, *ts_info2; | |
917 | struct skb_shared_hwtstamps shhwtstamps; | |
918 | struct rswitch_ts_desc *desc; | |
919 | struct timespec64 ts; | |
920 | u32 tag, port; | |
921 | int num; | |
922 | ||
923 | desc = &gq->ts_ring[gq->cur]; | |
924 | while ((desc->desc.die_dt & DT_MASK) != DT_FEMPTY_ND) { | |
925 | dma_rmb(); | |
926 | ||
927 | port = TS_DESC_DPN(__le32_to_cpu(desc->desc.dptrl)); | |
928 | tag = TS_DESC_TSUN(__le32_to_cpu(desc->desc.dptrl)); | |
929 | ||
930 | list_for_each_entry_safe(ts_info, ts_info2, &priv->gwca.ts_info_list, list) { | |
931 | if (!(ts_info->port == port && ts_info->tag == tag)) | |
932 | continue; | |
933 | ||
934 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
935 | ts.tv_sec = __le32_to_cpu(desc->ts_sec); | |
936 | ts.tv_nsec = __le32_to_cpu(desc->ts_nsec & cpu_to_le32(0x3fffffff)); | |
937 | shhwtstamps.hwtstamp = timespec64_to_ktime(ts); | |
938 | skb_tstamp_tx(ts_info->skb, &shhwtstamps); | |
939 | dev_consume_skb_irq(ts_info->skb); | |
940 | list_del(&ts_info->list); | |
941 | kfree(ts_info); | |
942 | break; | |
943 | } | |
944 | ||
945 | gq->cur = rswitch_next_queue_index(gq, true, 1); | |
946 | desc = &gq->ts_ring[gq->cur]; | |
947 | } | |
948 | ||
949 | num = rswitch_get_num_cur_queues(gq); | |
950 | rswitch_gwca_ts_queue_fill(priv, gq->dirty, num); | |
951 | gq->dirty = rswitch_next_queue_index(gq, false, num); | |
952 | } | |
953 | ||
954 | static irqreturn_t rswitch_gwca_ts_irq(int irq, void *dev_id) | |
955 | { | |
956 | struct rswitch_private *priv = dev_id; | |
957 | ||
958 | if (ioread32(priv->addr + GWTSDIS) & GWCA_TS_IRQ_BIT) { | |
959 | iowrite32(GWCA_TS_IRQ_BIT, priv->addr + GWTSDIS); | |
960 | rswitch_ts(priv); | |
961 | ||
962 | return IRQ_HANDLED; | |
963 | } | |
964 | ||
965 | return IRQ_NONE; | |
966 | } | |
967 | ||
968 | static int rswitch_gwca_ts_request_irqs(struct rswitch_private *priv) | |
969 | { | |
970 | int irq; | |
971 | ||
972 | irq = platform_get_irq_byname(priv->pdev, GWCA_TS_IRQ_RESOURCE_NAME); | |
973 | if (irq < 0) | |
974 | return irq; | |
975 | ||
976 | return devm_request_irq(&priv->pdev->dev, irq, rswitch_gwca_ts_irq, | |
977 | 0, GWCA_TS_IRQ_NAME, priv); | |
978 | } | |
979 | ||
3590918b YS |
980 | /* Ethernet TSN Agent block (ETHA) and Ethernet MAC IP block (RMAC) */ |
981 | static int rswitch_etha_change_mode(struct rswitch_etha *etha, | |
982 | enum rswitch_etha_mode mode) | |
983 | { | |
984 | int ret; | |
985 | ||
986 | if (!rswitch_agent_clock_is_enabled(etha->coma_addr, etha->index)) | |
987 | rswitch_agent_clock_ctrl(etha->coma_addr, etha->index, 1); | |
988 | ||
989 | iowrite32(mode, etha->addr + EAMC); | |
990 | ||
991 | ret = rswitch_reg_wait(etha->addr, EAMS, EAMS_OPS_MASK, mode); | |
992 | ||
993 | if (mode == EAMC_OPC_DISABLE) | |
994 | rswitch_agent_clock_ctrl(etha->coma_addr, etha->index, 0); | |
995 | ||
996 | return ret; | |
997 | } | |
998 | ||
999 | static void rswitch_etha_read_mac_address(struct rswitch_etha *etha) | |
1000 | { | |
1001 | u32 mrmac0 = ioread32(etha->addr + MRMAC0); | |
1002 | u32 mrmac1 = ioread32(etha->addr + MRMAC1); | |
1003 | u8 *mac = ða->mac_addr[0]; | |
1004 | ||
1005 | mac[0] = (mrmac0 >> 8) & 0xFF; | |
1006 | mac[1] = (mrmac0 >> 0) & 0xFF; | |
1007 | mac[2] = (mrmac1 >> 24) & 0xFF; | |
1008 | mac[3] = (mrmac1 >> 16) & 0xFF; | |
1009 | mac[4] = (mrmac1 >> 8) & 0xFF; | |
1010 | mac[5] = (mrmac1 >> 0) & 0xFF; | |
1011 | } | |
1012 | ||
1013 | static void rswitch_etha_write_mac_address(struct rswitch_etha *etha, const u8 *mac) | |
1014 | { | |
1015 | iowrite32((mac[0] << 8) | mac[1], etha->addr + MRMAC0); | |
1016 | iowrite32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], | |
1017 | etha->addr + MRMAC1); | |
1018 | } | |
1019 | ||
b4b221bd | 1020 | static int rswitch_etha_wait_link_verification(struct rswitch_etha *etha) |
3590918b YS |
1021 | { |
1022 | iowrite32(MLVC_PLV, etha->addr + MLVC); | |
1023 | ||
1024 | return rswitch_reg_wait(etha->addr, MLVC, MLVC_PLV, 0); | |
1025 | } | |
1026 | ||
1027 | static void rswitch_rmac_setting(struct rswitch_etha *etha, const u8 *mac) | |
1028 | { | |
1029 | u32 val; | |
1030 | ||
1031 | rswitch_etha_write_mac_address(etha, mac); | |
1032 | ||
1033 | switch (etha->speed) { | |
1034 | case 100: | |
1035 | val = MPIC_LSC_100M; | |
1036 | break; | |
1037 | case 1000: | |
1038 | val = MPIC_LSC_1G; | |
1039 | break; | |
1040 | case 2500: | |
1041 | val = MPIC_LSC_2_5G; | |
1042 | break; | |
1043 | default: | |
1044 | return; | |
1045 | } | |
1046 | ||
1047 | iowrite32(MPIC_PIS_GMII | val, etha->addr + MPIC); | |
1048 | } | |
1049 | ||
1050 | static void rswitch_etha_enable_mii(struct rswitch_etha *etha) | |
1051 | { | |
1052 | rswitch_modify(etha->addr, MPIC, MPIC_PSMCS_MASK | MPIC_PSMHT_MASK, | |
a0c55bba | 1053 | MPIC_PSMCS(etha->psmcs) | MPIC_PSMHT(0x06)); |
3590918b YS |
1054 | rswitch_modify(etha->addr, MPSM, 0, MPSM_MFF_C45); |
1055 | } | |
1056 | ||
1057 | static int rswitch_etha_hw_init(struct rswitch_etha *etha, const u8 *mac) | |
1058 | { | |
1059 | int err; | |
1060 | ||
1061 | err = rswitch_etha_change_mode(etha, EAMC_OPC_DISABLE); | |
1062 | if (err < 0) | |
1063 | return err; | |
1064 | err = rswitch_etha_change_mode(etha, EAMC_OPC_CONFIG); | |
1065 | if (err < 0) | |
1066 | return err; | |
1067 | ||
1068 | iowrite32(EAVCC_VEM_SC_TAG, etha->addr + EAVCC); | |
1069 | rswitch_rmac_setting(etha, mac); | |
1070 | rswitch_etha_enable_mii(etha); | |
1071 | ||
1072 | err = rswitch_etha_wait_link_verification(etha); | |
1073 | if (err < 0) | |
1074 | return err; | |
1075 | ||
1076 | err = rswitch_etha_change_mode(etha, EAMC_OPC_DISABLE); | |
1077 | if (err < 0) | |
1078 | return err; | |
1079 | ||
1080 | return rswitch_etha_change_mode(etha, EAMC_OPC_OPERATION); | |
1081 | } | |
1082 | ||
1083 | static int rswitch_etha_set_access(struct rswitch_etha *etha, bool read, | |
1084 | int phyad, int devad, int regad, int data) | |
1085 | { | |
1086 | int pop = read ? MDIO_READ_C45 : MDIO_WRITE_C45; | |
1087 | u32 val; | |
1088 | int ret; | |
1089 | ||
1090 | if (devad == 0xffffffff) | |
1091 | return -ENODEV; | |
1092 | ||
1093 | writel(MMIS1_CLEAR_FLAGS, etha->addr + MMIS1); | |
1094 | ||
1095 | val = MPSM_PSME | MPSM_MFF_C45; | |
1096 | iowrite32((regad << 16) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM); | |
1097 | ||
1098 | ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PAACS, MMIS1_PAACS); | |
1099 | if (ret) | |
1100 | return ret; | |
1101 | ||
1102 | rswitch_modify(etha->addr, MMIS1, MMIS1_PAACS, MMIS1_PAACS); | |
1103 | ||
1104 | if (read) { | |
1105 | writel((pop << 13) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM); | |
1106 | ||
1107 | ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PRACS, MMIS1_PRACS); | |
1108 | if (ret) | |
1109 | return ret; | |
1110 | ||
1111 | ret = (ioread32(etha->addr + MPSM) & MPSM_PRD_MASK) >> 16; | |
1112 | ||
1113 | rswitch_modify(etha->addr, MMIS1, MMIS1_PRACS, MMIS1_PRACS); | |
1114 | } else { | |
1115 | iowrite32((data << 16) | (pop << 13) | (devad << 8) | (phyad << 3) | val, | |
1116 | etha->addr + MPSM); | |
1117 | ||
1118 | ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PWACS, MMIS1_PWACS); | |
1119 | } | |
1120 | ||
1121 | return ret; | |
1122 | } | |
1123 | ||
95331514 MW |
1124 | static int rswitch_etha_mii_read_c45(struct mii_bus *bus, int addr, int devad, |
1125 | int regad) | |
3590918b YS |
1126 | { |
1127 | struct rswitch_etha *etha = bus->priv; | |
3590918b YS |
1128 | |
1129 | return rswitch_etha_set_access(etha, true, addr, devad, regad, 0); | |
1130 | } | |
1131 | ||
95331514 MW |
1132 | static int rswitch_etha_mii_write_c45(struct mii_bus *bus, int addr, int devad, |
1133 | int regad, u16 val) | |
3590918b YS |
1134 | { |
1135 | struct rswitch_etha *etha = bus->priv; | |
3590918b YS |
1136 | |
1137 | return rswitch_etha_set_access(etha, false, addr, devad, regad, val); | |
1138 | } | |
1139 | ||
1140 | /* Call of_node_put(port) after done */ | |
1141 | static struct device_node *rswitch_get_port_node(struct rswitch_device *rdev) | |
1142 | { | |
1143 | struct device_node *ports, *port; | |
1144 | int err = 0; | |
1145 | u32 index; | |
1146 | ||
1147 | ports = of_get_child_by_name(rdev->ndev->dev.parent->of_node, | |
1148 | "ethernet-ports"); | |
1149 | if (!ports) | |
1150 | return NULL; | |
1151 | ||
1152 | for_each_child_of_node(ports, port) { | |
1153 | err = of_property_read_u32(port, "reg", &index); | |
1154 | if (err < 0) { | |
1155 | port = NULL; | |
1156 | goto out; | |
1157 | } | |
fd941bd6 YS |
1158 | if (index == rdev->etha->index) { |
1159 | if (!of_device_is_available(port)) | |
1160 | port = NULL; | |
3590918b | 1161 | break; |
fd941bd6 | 1162 | } |
3590918b YS |
1163 | } |
1164 | ||
1165 | out: | |
1166 | of_node_put(ports); | |
1167 | ||
1168 | return port; | |
1169 | } | |
1170 | ||
3590918b YS |
1171 | static int rswitch_etha_get_params(struct rswitch_device *rdev) |
1172 | { | |
04c77d91 | 1173 | u32 max_speed; |
3590918b YS |
1174 | int err; |
1175 | ||
b46f1e57 | 1176 | if (!rdev->np_port) |
fd941bd6 | 1177 | return 0; /* ignored */ |
3590918b | 1178 | |
b46f1e57 | 1179 | err = of_get_phy_mode(rdev->np_port, &rdev->etha->phy_interface); |
04c77d91 YS |
1180 | if (err) |
1181 | return err; | |
1182 | ||
1183 | err = of_property_read_u32(rdev->np_port, "max-speed", &max_speed); | |
1184 | if (!err) { | |
1185 | rdev->etha->speed = max_speed; | |
1186 | return 0; | |
1187 | } | |
3590918b | 1188 | |
04c77d91 | 1189 | /* if no "max-speed" property, let's use default speed */ |
3590918b YS |
1190 | switch (rdev->etha->phy_interface) { |
1191 | case PHY_INTERFACE_MODE_MII: | |
1192 | rdev->etha->speed = SPEED_100; | |
1193 | break; | |
1194 | case PHY_INTERFACE_MODE_SGMII: | |
1195 | rdev->etha->speed = SPEED_1000; | |
1196 | break; | |
1197 | case PHY_INTERFACE_MODE_USXGMII: | |
1198 | rdev->etha->speed = SPEED_2500; | |
1199 | break; | |
1200 | default: | |
04c77d91 | 1201 | return -EINVAL; |
3590918b YS |
1202 | } |
1203 | ||
04c77d91 | 1204 | return 0; |
3590918b YS |
1205 | } |
1206 | ||
1207 | static int rswitch_mii_register(struct rswitch_device *rdev) | |
1208 | { | |
1209 | struct device_node *mdio_np; | |
1210 | struct mii_bus *mii_bus; | |
1211 | int err; | |
1212 | ||
1213 | mii_bus = mdiobus_alloc(); | |
1214 | if (!mii_bus) | |
1215 | return -ENOMEM; | |
1216 | ||
1217 | mii_bus->name = "rswitch_mii"; | |
1218 | sprintf(mii_bus->id, "etha%d", rdev->etha->index); | |
1219 | mii_bus->priv = rdev->etha; | |
95331514 MW |
1220 | mii_bus->read_c45 = rswitch_etha_mii_read_c45; |
1221 | mii_bus->write_c45 = rswitch_etha_mii_write_c45; | |
3590918b YS |
1222 | mii_bus->parent = &rdev->priv->pdev->dev; |
1223 | ||
b46f1e57 | 1224 | mdio_np = of_get_child_by_name(rdev->np_port, "mdio"); |
3590918b YS |
1225 | err = of_mdiobus_register(mii_bus, mdio_np); |
1226 | if (err < 0) { | |
1227 | mdiobus_free(mii_bus); | |
1228 | goto out; | |
1229 | } | |
1230 | ||
1231 | rdev->etha->mii = mii_bus; | |
1232 | ||
1233 | out: | |
1234 | of_node_put(mdio_np); | |
1235 | ||
1236 | return err; | |
1237 | } | |
1238 | ||
1239 | static void rswitch_mii_unregister(struct rswitch_device *rdev) | |
1240 | { | |
1241 | if (rdev->etha->mii) { | |
1242 | mdiobus_unregister(rdev->etha->mii); | |
1243 | mdiobus_free(rdev->etha->mii); | |
1244 | rdev->etha->mii = NULL; | |
1245 | } | |
1246 | } | |
1247 | ||
c16a5033 | 1248 | static void rswitch_adjust_link(struct net_device *ndev) |
3590918b | 1249 | { |
c16a5033 YS |
1250 | struct rswitch_device *rdev = netdev_priv(ndev); |
1251 | struct phy_device *phydev = ndev->phydev; | |
3590918b | 1252 | |
c16a5033 YS |
1253 | if (phydev->link != rdev->etha->link) { |
1254 | phy_print_status(phydev); | |
5cb63092 YS |
1255 | if (phydev->link) |
1256 | phy_power_on(rdev->serdes); | |
1257 | else | |
1258 | phy_power_off(rdev->serdes); | |
1259 | ||
c16a5033 | 1260 | rdev->etha->link = phydev->link; |
c009b903 YS |
1261 | |
1262 | if (!rdev->priv->etha_no_runtime_change && | |
1263 | phydev->speed != rdev->etha->speed) { | |
1264 | rdev->etha->speed = phydev->speed; | |
1265 | ||
1266 | rswitch_etha_hw_init(rdev->etha, rdev->ndev->dev_addr); | |
1267 | phy_set_speed(rdev->serdes, rdev->etha->speed); | |
1268 | } | |
c16a5033 | 1269 | } |
3590918b YS |
1270 | } |
1271 | ||
c16a5033 YS |
1272 | static void rswitch_phy_remove_link_mode(struct rswitch_device *rdev, |
1273 | struct phy_device *phydev) | |
3590918b | 1274 | { |
c009b903 YS |
1275 | if (!rdev->priv->etha_no_runtime_change) |
1276 | return; | |
1277 | ||
c16a5033 YS |
1278 | switch (rdev->etha->speed) { |
1279 | case SPEED_2500: | |
1280 | phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Full_BIT); | |
1281 | phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Full_BIT); | |
1282 | break; | |
1283 | case SPEED_1000: | |
1284 | phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_2500baseX_Full_BIT); | |
1285 | phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Full_BIT); | |
1286 | break; | |
1287 | case SPEED_100: | |
1288 | phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_2500baseX_Full_BIT); | |
1289 | phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Full_BIT); | |
1290 | break; | |
1291 | default: | |
1292 | break; | |
1293 | } | |
3590918b | 1294 | |
c16a5033 YS |
1295 | phy_set_max_speed(phydev, rdev->etha->speed); |
1296 | } | |
3590918b | 1297 | |
c16a5033 | 1298 | static int rswitch_phy_device_init(struct rswitch_device *rdev) |
3590918b | 1299 | { |
c16a5033 YS |
1300 | struct phy_device *phydev; |
1301 | struct device_node *phy; | |
0df024d0 | 1302 | int err = -ENOENT; |
3590918b | 1303 | |
b46f1e57 | 1304 | if (!rdev->np_port) |
3590918b YS |
1305 | return -ENODEV; |
1306 | ||
c16a5033 YS |
1307 | phy = of_parse_phandle(rdev->np_port, "phy-handle", 0); |
1308 | if (!phy) | |
1309 | return -ENODEV; | |
1310 | ||
0df024d0 YS |
1311 | /* Set phydev->host_interfaces before calling of_phy_connect() to |
1312 | * configure the PHY with the information of host_interfaces. | |
1313 | */ | |
1314 | phydev = of_phy_find_device(phy); | |
1315 | if (!phydev) | |
1316 | goto out; | |
1317 | __set_bit(rdev->etha->phy_interface, phydev->host_interfaces); | |
1318 | ||
c16a5033 YS |
1319 | phydev = of_phy_connect(rdev->ndev, phy, rswitch_adjust_link, 0, |
1320 | rdev->etha->phy_interface); | |
c16a5033 | 1321 | if (!phydev) |
0df024d0 | 1322 | goto out; |
3590918b | 1323 | |
c16a5033 YS |
1324 | phy_set_max_speed(phydev, SPEED_2500); |
1325 | phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); | |
1326 | phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); | |
1327 | phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); | |
1328 | phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); | |
1329 | rswitch_phy_remove_link_mode(rdev, phydev); | |
3590918b | 1330 | |
c16a5033 | 1331 | phy_attached_info(phydev); |
3590918b | 1332 | |
0df024d0 YS |
1333 | err = 0; |
1334 | out: | |
1335 | of_node_put(phy); | |
1336 | ||
1337 | return err; | |
3590918b YS |
1338 | } |
1339 | ||
c16a5033 | 1340 | static void rswitch_phy_device_deinit(struct rswitch_device *rdev) |
3590918b | 1341 | { |
22f5c234 | 1342 | if (rdev->ndev->phydev) |
c16a5033 | 1343 | phy_disconnect(rdev->ndev->phydev); |
3590918b YS |
1344 | } |
1345 | ||
1346 | static int rswitch_serdes_set_params(struct rswitch_device *rdev) | |
1347 | { | |
3590918b YS |
1348 | int err; |
1349 | ||
b46f1e57 | 1350 | err = phy_set_mode_ext(rdev->serdes, PHY_MODE_ETHERNET, |
3590918b YS |
1351 | rdev->etha->phy_interface); |
1352 | if (err < 0) | |
1353 | return err; | |
1354 | ||
b46f1e57 | 1355 | return phy_set_speed(rdev->serdes, rdev->etha->speed); |
3590918b YS |
1356 | } |
1357 | ||
1358 | static int rswitch_ether_port_init_one(struct rswitch_device *rdev) | |
1359 | { | |
1360 | int err; | |
1361 | ||
1362 | if (!rdev->etha->operated) { | |
1363 | err = rswitch_etha_hw_init(rdev->etha, rdev->ndev->dev_addr); | |
1364 | if (err < 0) | |
1365 | return err; | |
c009b903 YS |
1366 | if (rdev->priv->etha_no_runtime_change) |
1367 | rdev->etha->operated = true; | |
3590918b YS |
1368 | } |
1369 | ||
1370 | err = rswitch_mii_register(rdev); | |
1371 | if (err < 0) | |
1372 | return err; | |
1373 | ||
c16a5033 | 1374 | err = rswitch_phy_device_init(rdev); |
3590918b | 1375 | if (err < 0) |
c16a5033 | 1376 | goto err_phy_device_init; |
3590918b | 1377 | |
b46f1e57 YS |
1378 | rdev->serdes = devm_of_phy_get(&rdev->priv->pdev->dev, rdev->np_port, NULL); |
1379 | if (IS_ERR(rdev->serdes)) { | |
1380 | err = PTR_ERR(rdev->serdes); | |
1381 | goto err_serdes_phy_get; | |
1382 | } | |
1383 | ||
3590918b YS |
1384 | err = rswitch_serdes_set_params(rdev); |
1385 | if (err < 0) | |
1386 | goto err_serdes_set_params; | |
1387 | ||
1388 | return 0; | |
1389 | ||
1390 | err_serdes_set_params: | |
b46f1e57 | 1391 | err_serdes_phy_get: |
c16a5033 | 1392 | rswitch_phy_device_deinit(rdev); |
3590918b | 1393 | |
c16a5033 | 1394 | err_phy_device_init: |
3590918b YS |
1395 | rswitch_mii_unregister(rdev); |
1396 | ||
1397 | return err; | |
1398 | } | |
1399 | ||
1400 | static void rswitch_ether_port_deinit_one(struct rswitch_device *rdev) | |
1401 | { | |
c16a5033 | 1402 | rswitch_phy_device_deinit(rdev); |
3590918b YS |
1403 | rswitch_mii_unregister(rdev); |
1404 | } | |
1405 | ||
1406 | static int rswitch_ether_port_init_all(struct rswitch_private *priv) | |
1407 | { | |
1408 | int i, err; | |
1409 | ||
fd941bd6 | 1410 | rswitch_for_each_enabled_port(priv, i) { |
3590918b YS |
1411 | err = rswitch_ether_port_init_one(priv->rdev[i]); |
1412 | if (err) | |
1413 | goto err_init_one; | |
1414 | } | |
1415 | ||
fd941bd6 | 1416 | rswitch_for_each_enabled_port(priv, i) { |
b46f1e57 | 1417 | err = phy_init(priv->rdev[i]->serdes); |
3590918b YS |
1418 | if (err) |
1419 | goto err_serdes; | |
1420 | } | |
1421 | ||
1422 | return 0; | |
1423 | ||
1424 | err_serdes: | |
fd941bd6 | 1425 | rswitch_for_each_enabled_port_continue_reverse(priv, i) |
b46f1e57 | 1426 | phy_exit(priv->rdev[i]->serdes); |
3590918b YS |
1427 | i = RSWITCH_NUM_PORTS; |
1428 | ||
1429 | err_init_one: | |
fd941bd6 | 1430 | rswitch_for_each_enabled_port_continue_reverse(priv, i) |
3590918b YS |
1431 | rswitch_ether_port_deinit_one(priv->rdev[i]); |
1432 | ||
1433 | return err; | |
1434 | } | |
1435 | ||
1436 | static void rswitch_ether_port_deinit_all(struct rswitch_private *priv) | |
1437 | { | |
1438 | int i; | |
1439 | ||
1440 | for (i = 0; i < RSWITCH_NUM_PORTS; i++) { | |
b46f1e57 | 1441 | phy_exit(priv->rdev[i]->serdes); |
3590918b YS |
1442 | rswitch_ether_port_deinit_one(priv->rdev[i]); |
1443 | } | |
1444 | } | |
1445 | ||
1446 | static int rswitch_open(struct net_device *ndev) | |
1447 | { | |
1448 | struct rswitch_device *rdev = netdev_priv(ndev); | |
c4f922e8 | 1449 | unsigned long flags; |
3590918b | 1450 | |
c16a5033 | 1451 | phy_start(ndev->phydev); |
3590918b YS |
1452 | |
1453 | napi_enable(&rdev->napi); | |
1454 | netif_start_queue(ndev); | |
1455 | ||
c4f922e8 | 1456 | spin_lock_irqsave(&rdev->priv->lock, flags); |
3590918b YS |
1457 | rswitch_enadis_data_irq(rdev->priv, rdev->tx_queue->index, true); |
1458 | rswitch_enadis_data_irq(rdev->priv, rdev->rx_queue->index, true); | |
c4f922e8 | 1459 | spin_unlock_irqrestore(&rdev->priv->lock, flags); |
3590918b | 1460 | |
2c59e993 YS |
1461 | if (bitmap_empty(rdev->priv->opened_ports, RSWITCH_NUM_PORTS)) |
1462 | iowrite32(GWCA_TS_IRQ_BIT, rdev->priv->addr + GWTSDIE); | |
1463 | ||
1464 | bitmap_set(rdev->priv->opened_ports, rdev->port, 1); | |
33f5d733 | 1465 | |
3590918b YS |
1466 | return 0; |
1467 | }; | |
1468 | ||
1469 | static int rswitch_stop(struct net_device *ndev) | |
1470 | { | |
1471 | struct rswitch_device *rdev = netdev_priv(ndev); | |
33f5d733 | 1472 | struct rswitch_gwca_ts_info *ts_info, *ts_info2; |
c4f922e8 | 1473 | unsigned long flags; |
3590918b YS |
1474 | |
1475 | netif_tx_stop_all_queues(ndev); | |
2c59e993 | 1476 | bitmap_clear(rdev->priv->opened_ports, rdev->port, 1); |
3590918b | 1477 | |
2c59e993 YS |
1478 | if (bitmap_empty(rdev->priv->opened_ports, RSWITCH_NUM_PORTS)) |
1479 | iowrite32(GWCA_TS_IRQ_BIT, rdev->priv->addr + GWTSDID); | |
33f5d733 YS |
1480 | |
1481 | list_for_each_entry_safe(ts_info, ts_info2, &rdev->priv->gwca.ts_info_list, list) { | |
1482 | if (ts_info->port != rdev->port) | |
1483 | continue; | |
1484 | dev_kfree_skb_irq(ts_info->skb); | |
1485 | list_del(&ts_info->list); | |
1486 | kfree(ts_info); | |
1487 | } | |
1488 | ||
c4f922e8 | 1489 | spin_lock_irqsave(&rdev->priv->lock, flags); |
3590918b YS |
1490 | rswitch_enadis_data_irq(rdev->priv, rdev->tx_queue->index, false); |
1491 | rswitch_enadis_data_irq(rdev->priv, rdev->rx_queue->index, false); | |
c4f922e8 | 1492 | spin_unlock_irqrestore(&rdev->priv->lock, flags); |
3590918b | 1493 | |
c16a5033 | 1494 | phy_stop(ndev->phydev); |
3590918b YS |
1495 | napi_disable(&rdev->napi); |
1496 | ||
1497 | return 0; | |
1498 | }; | |
1499 | ||
8e0aa1ff | 1500 | static netdev_tx_t rswitch_start_xmit(struct sk_buff *skb, struct net_device *ndev) |
3590918b YS |
1501 | { |
1502 | struct rswitch_device *rdev = netdev_priv(ndev); | |
1503 | struct rswitch_gwca_queue *gq = rdev->tx_queue; | |
1504 | struct rswitch_ext_desc *desc; | |
1505 | int ret = NETDEV_TX_OK; | |
1506 | dma_addr_t dma_addr; | |
1507 | ||
1508 | if (rswitch_get_num_cur_queues(gq) >= gq->ring_size - 1) { | |
1509 | netif_stop_subqueue(ndev, 0); | |
a60caf03 | 1510 | return NETDEV_TX_BUSY; |
3590918b YS |
1511 | } |
1512 | ||
1513 | if (skb_put_padto(skb, ETH_ZLEN)) | |
1514 | return ret; | |
1515 | ||
1516 | dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, DMA_TO_DEVICE); | |
1517 | if (dma_mapping_error(ndev->dev.parent, dma_addr)) { | |
1518 | dev_kfree_skb_any(skb); | |
1519 | return ret; | |
1520 | } | |
1521 | ||
1522 | gq->skbs[gq->cur] = skb; | |
251eadcc | 1523 | desc = &gq->tx_ring[gq->cur]; |
3590918b YS |
1524 | rswitch_desc_set_dptr(&desc->desc, dma_addr); |
1525 | desc->desc.info_ds = cpu_to_le16(skb->len); | |
1526 | ||
c87bd91e YS |
1527 | desc->info1 = cpu_to_le64(INFO1_DV(BIT(rdev->etha->index)) | |
1528 | INFO1_IPV(GWCA_IPV_NUM) | INFO1_FMT); | |
3590918b | 1529 | if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { |
33f5d733 YS |
1530 | struct rswitch_gwca_ts_info *ts_info; |
1531 | ||
1532 | ts_info = kzalloc(sizeof(*ts_info), GFP_ATOMIC); | |
1533 | if (!ts_info) { | |
1534 | dma_unmap_single(ndev->dev.parent, dma_addr, skb->len, DMA_TO_DEVICE); | |
1535 | return -ENOMEM; | |
1536 | } | |
1537 | ||
3590918b YS |
1538 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
1539 | rdev->ts_tag++; | |
1540 | desc->info1 |= cpu_to_le64(INFO1_TSUN(rdev->ts_tag) | INFO1_TXC); | |
33f5d733 YS |
1541 | |
1542 | ts_info->skb = skb_get(skb); | |
1543 | ts_info->port = rdev->port; | |
1544 | ts_info->tag = rdev->ts_tag; | |
1545 | list_add_tail(&ts_info->list, &rdev->priv->gwca.ts_info_list); | |
1546 | ||
1547 | skb_tx_timestamp(skb); | |
3590918b | 1548 | } |
3590918b YS |
1549 | |
1550 | dma_wmb(); | |
1551 | ||
1552 | desc->desc.die_dt = DT_FSINGLE | DIE; | |
1553 | wmb(); /* gq->cur must be incremented after die_dt was set */ | |
1554 | ||
1555 | gq->cur = rswitch_next_queue_index(gq, true, 1); | |
1556 | rswitch_modify(rdev->addr, GWTRC(gq->index), 0, BIT(gq->index % 32)); | |
1557 | ||
1558 | return ret; | |
1559 | } | |
1560 | ||
1561 | static struct net_device_stats *rswitch_get_stats(struct net_device *ndev) | |
1562 | { | |
1563 | return &ndev->stats; | |
1564 | } | |
1565 | ||
6c6fa1a0 YS |
1566 | static int rswitch_hwstamp_get(struct net_device *ndev, struct ifreq *req) |
1567 | { | |
1568 | struct rswitch_device *rdev = netdev_priv(ndev); | |
1569 | struct rcar_gen4_ptp_private *ptp_priv; | |
1570 | struct hwtstamp_config config; | |
1571 | ||
1572 | ptp_priv = rdev->priv->ptp_priv; | |
1573 | ||
1574 | config.flags = 0; | |
1575 | config.tx_type = ptp_priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : | |
1576 | HWTSTAMP_TX_OFF; | |
1577 | switch (ptp_priv->tstamp_rx_ctrl & RCAR_GEN4_RXTSTAMP_TYPE) { | |
1578 | case RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT: | |
1579 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; | |
1580 | break; | |
1581 | case RCAR_GEN4_RXTSTAMP_TYPE_ALL: | |
1582 | config.rx_filter = HWTSTAMP_FILTER_ALL; | |
1583 | break; | |
1584 | default: | |
1585 | config.rx_filter = HWTSTAMP_FILTER_NONE; | |
1586 | break; | |
1587 | } | |
1588 | ||
1589 | return copy_to_user(req->ifr_data, &config, sizeof(config)) ? -EFAULT : 0; | |
1590 | } | |
1591 | ||
1592 | static int rswitch_hwstamp_set(struct net_device *ndev, struct ifreq *req) | |
1593 | { | |
1594 | struct rswitch_device *rdev = netdev_priv(ndev); | |
1595 | u32 tstamp_rx_ctrl = RCAR_GEN4_RXTSTAMP_ENABLED; | |
1596 | struct hwtstamp_config config; | |
1597 | u32 tstamp_tx_ctrl; | |
1598 | ||
1599 | if (copy_from_user(&config, req->ifr_data, sizeof(config))) | |
1600 | return -EFAULT; | |
1601 | ||
1602 | if (config.flags) | |
1603 | return -EINVAL; | |
1604 | ||
1605 | switch (config.tx_type) { | |
1606 | case HWTSTAMP_TX_OFF: | |
1607 | tstamp_tx_ctrl = 0; | |
1608 | break; | |
1609 | case HWTSTAMP_TX_ON: | |
1610 | tstamp_tx_ctrl = RCAR_GEN4_TXTSTAMP_ENABLED; | |
1611 | break; | |
1612 | default: | |
1613 | return -ERANGE; | |
1614 | } | |
1615 | ||
1616 | switch (config.rx_filter) { | |
1617 | case HWTSTAMP_FILTER_NONE: | |
1618 | tstamp_rx_ctrl = 0; | |
1619 | break; | |
1620 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
1621 | tstamp_rx_ctrl |= RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT; | |
1622 | break; | |
1623 | default: | |
1624 | config.rx_filter = HWTSTAMP_FILTER_ALL; | |
1625 | tstamp_rx_ctrl |= RCAR_GEN4_RXTSTAMP_TYPE_ALL; | |
1626 | break; | |
1627 | } | |
1628 | ||
1629 | rdev->priv->ptp_priv->tstamp_tx_ctrl = tstamp_tx_ctrl; | |
1630 | rdev->priv->ptp_priv->tstamp_rx_ctrl = tstamp_rx_ctrl; | |
1631 | ||
1632 | return copy_to_user(req->ifr_data, &config, sizeof(config)) ? -EFAULT : 0; | |
1633 | } | |
1634 | ||
3590918b YS |
1635 | static int rswitch_eth_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) |
1636 | { | |
3590918b YS |
1637 | if (!netif_running(ndev)) |
1638 | return -EINVAL; | |
1639 | ||
6c6fa1a0 YS |
1640 | switch (cmd) { |
1641 | case SIOCGHWTSTAMP: | |
1642 | return rswitch_hwstamp_get(ndev, req); | |
1643 | case SIOCSHWTSTAMP: | |
1644 | return rswitch_hwstamp_set(ndev, req); | |
1645 | default: | |
c16a5033 | 1646 | return phy_mii_ioctl(ndev->phydev, req, cmd); |
6c6fa1a0 | 1647 | } |
3590918b YS |
1648 | } |
1649 | ||
1650 | static const struct net_device_ops rswitch_netdev_ops = { | |
1651 | .ndo_open = rswitch_open, | |
1652 | .ndo_stop = rswitch_stop, | |
1653 | .ndo_start_xmit = rswitch_start_xmit, | |
1654 | .ndo_get_stats = rswitch_get_stats, | |
1655 | .ndo_eth_ioctl = rswitch_eth_ioctl, | |
1656 | .ndo_validate_addr = eth_validate_addr, | |
1657 | .ndo_set_mac_address = eth_mac_addr, | |
1658 | }; | |
1659 | ||
6c6fa1a0 YS |
1660 | static int rswitch_get_ts_info(struct net_device *ndev, struct ethtool_ts_info *info) |
1661 | { | |
1662 | struct rswitch_device *rdev = netdev_priv(ndev); | |
1663 | ||
1664 | info->phc_index = ptp_clock_index(rdev->priv->ptp_priv->clock); | |
1665 | info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | | |
1666 | SOF_TIMESTAMPING_RX_SOFTWARE | | |
1667 | SOF_TIMESTAMPING_SOFTWARE | | |
1668 | SOF_TIMESTAMPING_TX_HARDWARE | | |
1669 | SOF_TIMESTAMPING_RX_HARDWARE | | |
1670 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
1671 | info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON); | |
1672 | info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); | |
1673 | ||
1674 | return 0; | |
1675 | } | |
1676 | ||
1677 | static const struct ethtool_ops rswitch_ethtool_ops = { | |
1678 | .get_ts_info = rswitch_get_ts_info, | |
20f8be6b YS |
1679 | .get_link_ksettings = phy_ethtool_get_link_ksettings, |
1680 | .set_link_ksettings = phy_ethtool_set_link_ksettings, | |
6c6fa1a0 YS |
1681 | }; |
1682 | ||
3590918b YS |
1683 | static const struct of_device_id renesas_eth_sw_of_table[] = { |
1684 | { .compatible = "renesas,r8a779f0-ether-switch", }, | |
1685 | { } | |
1686 | }; | |
1687 | MODULE_DEVICE_TABLE(of, renesas_eth_sw_of_table); | |
1688 | ||
1689 | static void rswitch_etha_init(struct rswitch_private *priv, int index) | |
1690 | { | |
1691 | struct rswitch_etha *etha = &priv->etha[index]; | |
1692 | ||
1693 | memset(etha, 0, sizeof(*etha)); | |
1694 | etha->index = index; | |
1695 | etha->addr = priv->addr + RSWITCH_ETHA_OFFSET + index * RSWITCH_ETHA_SIZE; | |
1696 | etha->coma_addr = priv->addr; | |
a0c55bba YS |
1697 | |
1698 | /* MPIC.PSMCS = (clk [MHz] / (MDC frequency [MHz] * 2) - 1. | |
1699 | * Calculating PSMCS value as MDC frequency = 2.5MHz. So, multiply | |
1700 | * both the numerator and the denominator by 10. | |
1701 | */ | |
1702 | etha->psmcs = clk_get_rate(priv->clk) / 100000 / (25 * 2) - 1; | |
3590918b YS |
1703 | } |
1704 | ||
1705 | static int rswitch_device_alloc(struct rswitch_private *priv, int index) | |
1706 | { | |
1707 | struct platform_device *pdev = priv->pdev; | |
1708 | struct rswitch_device *rdev; | |
1709 | struct net_device *ndev; | |
1710 | int err; | |
1711 | ||
1712 | if (index >= RSWITCH_NUM_PORTS) | |
1713 | return -EINVAL; | |
1714 | ||
1715 | ndev = alloc_etherdev_mqs(sizeof(struct rswitch_device), 1, 1); | |
1716 | if (!ndev) | |
1717 | return -ENOMEM; | |
1718 | ||
1719 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1720 | ether_setup(ndev); | |
1721 | ||
1722 | rdev = netdev_priv(ndev); | |
1723 | rdev->ndev = ndev; | |
1724 | rdev->priv = priv; | |
1725 | priv->rdev[index] = rdev; | |
1726 | rdev->port = index; | |
1727 | rdev->etha = &priv->etha[index]; | |
1728 | rdev->addr = priv->addr; | |
1729 | ||
1730 | ndev->base_addr = (unsigned long)rdev->addr; | |
1731 | snprintf(ndev->name, IFNAMSIZ, "tsn%d", index); | |
1732 | ndev->netdev_ops = &rswitch_netdev_ops; | |
6c6fa1a0 | 1733 | ndev->ethtool_ops = &rswitch_ethtool_ops; |
3590918b YS |
1734 | |
1735 | netif_napi_add(ndev, &rdev->napi, rswitch_poll); | |
1736 | ||
b46f1e57 YS |
1737 | rdev->np_port = rswitch_get_port_node(rdev); |
1738 | rdev->disabled = !rdev->np_port; | |
1739 | err = of_get_ethdev_address(rdev->np_port, ndev); | |
1740 | of_node_put(rdev->np_port); | |
3590918b YS |
1741 | if (err) { |
1742 | if (is_valid_ether_addr(rdev->etha->mac_addr)) | |
1743 | eth_hw_addr_set(ndev, rdev->etha->mac_addr); | |
1744 | else | |
1745 | eth_hw_addr_random(ndev); | |
1746 | } | |
1747 | ||
1748 | err = rswitch_etha_get_params(rdev); | |
1749 | if (err < 0) | |
1750 | goto out_get_params; | |
1751 | ||
1752 | if (rdev->priv->gwca.speed < rdev->etha->speed) | |
1753 | rdev->priv->gwca.speed = rdev->etha->speed; | |
1754 | ||
1755 | err = rswitch_rxdmac_alloc(ndev); | |
1756 | if (err < 0) | |
1757 | goto out_rxdmac; | |
1758 | ||
1759 | err = rswitch_txdmac_alloc(ndev); | |
1760 | if (err < 0) | |
1761 | goto out_txdmac; | |
1762 | ||
1763 | return 0; | |
1764 | ||
1765 | out_txdmac: | |
1766 | rswitch_rxdmac_free(ndev); | |
1767 | ||
1768 | out_rxdmac: | |
1769 | out_get_params: | |
1770 | netif_napi_del(&rdev->napi); | |
1771 | free_netdev(ndev); | |
1772 | ||
1773 | return err; | |
1774 | } | |
1775 | ||
1776 | static void rswitch_device_free(struct rswitch_private *priv, int index) | |
1777 | { | |
1778 | struct rswitch_device *rdev = priv->rdev[index]; | |
1779 | struct net_device *ndev = rdev->ndev; | |
1780 | ||
1781 | rswitch_txdmac_free(ndev); | |
1782 | rswitch_rxdmac_free(ndev); | |
1783 | netif_napi_del(&rdev->napi); | |
1784 | free_netdev(ndev); | |
1785 | } | |
1786 | ||
1787 | static int rswitch_init(struct rswitch_private *priv) | |
1788 | { | |
1789 | int i, err; | |
1790 | ||
1791 | for (i = 0; i < RSWITCH_NUM_PORTS; i++) | |
1792 | rswitch_etha_init(priv, i); | |
1793 | ||
1794 | rswitch_clock_enable(priv); | |
1795 | for (i = 0; i < RSWITCH_NUM_PORTS; i++) | |
1796 | rswitch_etha_read_mac_address(&priv->etha[i]); | |
1797 | ||
1798 | rswitch_reset(priv); | |
1799 | ||
1800 | rswitch_clock_enable(priv); | |
1801 | rswitch_top_init(priv); | |
1802 | err = rswitch_bpool_config(priv); | |
1803 | if (err < 0) | |
1804 | return err; | |
1805 | ||
c87bd91e YS |
1806 | rswitch_coma_init(priv); |
1807 | ||
e3f38039 | 1808 | err = rswitch_gwca_linkfix_alloc(priv); |
3590918b YS |
1809 | if (err < 0) |
1810 | return -ENOMEM; | |
1811 | ||
33f5d733 YS |
1812 | err = rswitch_gwca_ts_queue_alloc(priv); |
1813 | if (err < 0) | |
1814 | goto err_ts_queue_alloc; | |
1815 | ||
3590918b YS |
1816 | for (i = 0; i < RSWITCH_NUM_PORTS; i++) { |
1817 | err = rswitch_device_alloc(priv, i); | |
1818 | if (err < 0) { | |
1819 | for (i--; i >= 0; i--) | |
1820 | rswitch_device_free(priv, i); | |
1821 | goto err_device_alloc; | |
1822 | } | |
1823 | } | |
1824 | ||
1825 | rswitch_fwd_init(priv); | |
1826 | ||
6c6fa1a0 YS |
1827 | err = rcar_gen4_ptp_register(priv->ptp_priv, RCAR_GEN4_PTP_REG_LAYOUT_S4, |
1828 | RCAR_GEN4_PTP_CLOCK_S4); | |
1829 | if (err < 0) | |
1830 | goto err_ptp_register; | |
1831 | ||
3590918b YS |
1832 | err = rswitch_gwca_request_irqs(priv); |
1833 | if (err < 0) | |
1834 | goto err_gwca_request_irq; | |
1835 | ||
33f5d733 YS |
1836 | err = rswitch_gwca_ts_request_irqs(priv); |
1837 | if (err < 0) | |
1838 | goto err_gwca_ts_request_irq; | |
1839 | ||
3590918b YS |
1840 | err = rswitch_gwca_hw_init(priv); |
1841 | if (err < 0) | |
1842 | goto err_gwca_hw_init; | |
1843 | ||
1844 | err = rswitch_ether_port_init_all(priv); | |
1845 | if (err) | |
1846 | goto err_ether_port_init_all; | |
1847 | ||
fd941bd6 | 1848 | rswitch_for_each_enabled_port(priv, i) { |
3590918b YS |
1849 | err = register_netdev(priv->rdev[i]->ndev); |
1850 | if (err) { | |
fd941bd6 | 1851 | rswitch_for_each_enabled_port_continue_reverse(priv, i) |
3590918b YS |
1852 | unregister_netdev(priv->rdev[i]->ndev); |
1853 | goto err_register_netdev; | |
1854 | } | |
1855 | } | |
1856 | ||
fd941bd6 | 1857 | rswitch_for_each_enabled_port(priv, i) |
1cb50726 | 1858 | netdev_info(priv->rdev[i]->ndev, "MAC address %pM\n", |
3590918b YS |
1859 | priv->rdev[i]->ndev->dev_addr); |
1860 | ||
1861 | return 0; | |
1862 | ||
1863 | err_register_netdev: | |
1864 | rswitch_ether_port_deinit_all(priv); | |
1865 | ||
1866 | err_ether_port_init_all: | |
1867 | rswitch_gwca_hw_deinit(priv); | |
1868 | ||
1869 | err_gwca_hw_init: | |
33f5d733 | 1870 | err_gwca_ts_request_irq: |
3590918b | 1871 | err_gwca_request_irq: |
6c6fa1a0 YS |
1872 | rcar_gen4_ptp_unregister(priv->ptp_priv); |
1873 | ||
1874 | err_ptp_register: | |
3590918b YS |
1875 | for (i = 0; i < RSWITCH_NUM_PORTS; i++) |
1876 | rswitch_device_free(priv, i); | |
1877 | ||
1878 | err_device_alloc: | |
33f5d733 YS |
1879 | rswitch_gwca_ts_queue_free(priv); |
1880 | ||
1881 | err_ts_queue_alloc: | |
e3f38039 | 1882 | rswitch_gwca_linkfix_free(priv); |
3590918b YS |
1883 | |
1884 | return err; | |
1885 | } | |
1886 | ||
c009b903 YS |
1887 | static const struct soc_device_attribute rswitch_soc_no_speed_change[] = { |
1888 | { .soc_id = "r8a779f0", .revision = "ES1.0" }, | |
1889 | { /* Sentinel */ } | |
1890 | }; | |
1891 | ||
3590918b YS |
1892 | static int renesas_eth_sw_probe(struct platform_device *pdev) |
1893 | { | |
c009b903 | 1894 | const struct soc_device_attribute *attr; |
3590918b YS |
1895 | struct rswitch_private *priv; |
1896 | struct resource *res; | |
1897 | int ret; | |
1898 | ||
1899 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "secure_base"); | |
1900 | if (!res) { | |
1901 | dev_err(&pdev->dev, "invalid resource\n"); | |
1902 | return -EINVAL; | |
1903 | } | |
1904 | ||
1905 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); | |
1906 | if (!priv) | |
1907 | return -ENOMEM; | |
c4f922e8 | 1908 | spin_lock_init(&priv->lock); |
3590918b | 1909 | |
a0c55bba YS |
1910 | priv->clk = devm_clk_get(&pdev->dev, NULL); |
1911 | if (IS_ERR(priv->clk)) | |
1912 | return PTR_ERR(priv->clk); | |
1913 | ||
c009b903 YS |
1914 | attr = soc_device_match(rswitch_soc_no_speed_change); |
1915 | if (attr) | |
1916 | priv->etha_no_runtime_change = true; | |
1917 | ||
6c6fa1a0 YS |
1918 | priv->ptp_priv = rcar_gen4_ptp_alloc(pdev); |
1919 | if (!priv->ptp_priv) | |
1920 | return -ENOMEM; | |
1921 | ||
3590918b YS |
1922 | platform_set_drvdata(pdev, priv); |
1923 | priv->pdev = pdev; | |
1924 | priv->addr = devm_ioremap_resource(&pdev->dev, res); | |
1925 | if (IS_ERR(priv->addr)) | |
1926 | return PTR_ERR(priv->addr); | |
1927 | ||
6c6fa1a0 YS |
1928 | priv->ptp_priv->addr = priv->addr + RCAR_GEN4_GPTP_OFFSET_S4; |
1929 | ||
3590918b YS |
1930 | ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); |
1931 | if (ret < 0) { | |
1932 | ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); | |
1933 | if (ret < 0) | |
1934 | return ret; | |
1935 | } | |
1936 | ||
1937 | priv->gwca.index = AGENT_INDEX_GWCA; | |
1938 | priv->gwca.num_queues = min(RSWITCH_NUM_PORTS * NUM_QUEUES_PER_NDEV, | |
1939 | RSWITCH_MAX_NUM_QUEUES); | |
1940 | priv->gwca.queues = devm_kcalloc(&pdev->dev, priv->gwca.num_queues, | |
1941 | sizeof(*priv->gwca.queues), GFP_KERNEL); | |
1942 | if (!priv->gwca.queues) | |
1943 | return -ENOMEM; | |
1944 | ||
1945 | pm_runtime_enable(&pdev->dev); | |
1946 | pm_runtime_get_sync(&pdev->dev); | |
1947 | ||
1948 | ret = rswitch_init(priv); | |
8e6a8d7a YS |
1949 | if (ret < 0) { |
1950 | pm_runtime_put(&pdev->dev); | |
1951 | pm_runtime_disable(&pdev->dev); | |
1952 | return ret; | |
1953 | } | |
3590918b YS |
1954 | |
1955 | device_set_wakeup_capable(&pdev->dev, 1); | |
1956 | ||
1957 | return ret; | |
1958 | } | |
1959 | ||
1960 | static void rswitch_deinit(struct rswitch_private *priv) | |
1961 | { | |
1962 | int i; | |
1963 | ||
1964 | rswitch_gwca_hw_deinit(priv); | |
6c6fa1a0 | 1965 | rcar_gen4_ptp_unregister(priv->ptp_priv); |
3590918b YS |
1966 | |
1967 | for (i = 0; i < RSWITCH_NUM_PORTS; i++) { | |
1968 | struct rswitch_device *rdev = priv->rdev[i]; | |
1969 | ||
b46f1e57 | 1970 | phy_exit(priv->rdev[i]->serdes); |
3590918b YS |
1971 | rswitch_ether_port_deinit_one(rdev); |
1972 | unregister_netdev(rdev->ndev); | |
1973 | rswitch_device_free(priv, i); | |
1974 | } | |
1975 | ||
33f5d733 | 1976 | rswitch_gwca_ts_queue_free(priv); |
e3f38039 | 1977 | rswitch_gwca_linkfix_free(priv); |
3590918b YS |
1978 | |
1979 | rswitch_clock_disable(priv); | |
1980 | } | |
1981 | ||
1982 | static int renesas_eth_sw_remove(struct platform_device *pdev) | |
1983 | { | |
1984 | struct rswitch_private *priv = platform_get_drvdata(pdev); | |
1985 | ||
1986 | rswitch_deinit(priv); | |
1987 | ||
1988 | pm_runtime_put(&pdev->dev); | |
1989 | pm_runtime_disable(&pdev->dev); | |
1990 | ||
1991 | platform_set_drvdata(pdev, NULL); | |
1992 | ||
1993 | return 0; | |
1994 | } | |
1995 | ||
1996 | static struct platform_driver renesas_eth_sw_driver_platform = { | |
1997 | .probe = renesas_eth_sw_probe, | |
1998 | .remove = renesas_eth_sw_remove, | |
1999 | .driver = { | |
2000 | .name = "renesas_eth_sw", | |
2001 | .of_match_table = renesas_eth_sw_of_table, | |
2002 | } | |
2003 | }; | |
2004 | module_platform_driver(renesas_eth_sw_driver_platform); | |
2005 | MODULE_AUTHOR("Yoshihiro Shimoda"); | |
2006 | MODULE_DESCRIPTION("Renesas Ethernet Switch device driver"); | |
2007 | MODULE_LICENSE("GPL"); |