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Merge tag 'pci-v6.16-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
[linux-block.git] / drivers / net / ethernet / realtek / r8169_main.c
CommitLineData
09c434b8 1// SPDX-License-Identifier: GPL-2.0-only
1da177e4 2/*
07d3f51f
FR		 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 *
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
8 *
9 * See MAINTAINERS file for support contact information.
1da177e4
LT		 10 */
11
12#include <linux/module.h>
1da177e4
LT		 13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
c2f6f3ee 16#include <linux/clk.h>
1da177e4
LT		 17#include <linux/delay.h>
18#include <linux/ethtool.h>
f1e911d5 19#include <linux/phy.h>
1da177e4 20#include <linux/if_vlan.h>
1da177e4 21#include <linux/in.h>
098b01ad 22#include <linux/io.h>
1da177e4
LT		 23#include <linux/ip.h>
24#include <linux/tcp.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
6cf96dd4 28#include <linux/bitfield.h>
70c71606 29#include <linux/prefetch.h>
e974604b 30#include <linux/ipv6.h>
5f60d5f6 31#include <linux/unaligned.h>
e974604b 32#include <net/ip6_checksum.h>
8624e9bb 33#include <net/netdev_queues.h>
1da177e4 34
2992bdfa 35#include "r8169.h"
8197f9d2
HK		 36#include "r8169_firmware.h"
37
bca03d5f 38#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 40#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 42#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 43#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
44#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 45#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 46#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 47#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45dd95c4 48#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
5598bfe5 49#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
58152cd4 50#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
beb330a4 51#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
57538c4a 52#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
6e1d0b89 53#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
229c1e0d 54#define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw"
6e1d0b89 55#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
02bf642b 56#define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw"
0439297b 57#define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw"
f75d1fbe 58#define FIRMWARE_8125D_1 "rtl_nic/rtl8125d-1.fw"
b3593df2 59#define FIRMWARE_8125D_2 "rtl_nic/rtl8125d-2.fw"
b11bff90 60#define FIRMWARE_8125BP_2 "rtl_nic/rtl8125bp-2.fw"
3907f1ff 61#define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw"
69cb8998 62#define FIRMWARE_8126A_3 "rtl_nic/rtl8126a-3.fw"
f24f7b2f 63#define FIRMWARE_8127A_1 "rtl_nic/rtl8127a-1.fw"
bca03d5f 64
aee77e4a 65#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 66#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
67
68#define R8169_REGS_SIZE 256
1d0254dd 69#define R8169_RX_BUF_SIZE (SZ_16K - 1)
f06059c2 70#define NUM_TX_DESC 256 /* Number of Tx descriptor registers */
ed22a8ff 71#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
1da177e4
LT		 72#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
73#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
8624e9bb
HK		 74#define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1)
75#define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS)
1da177e4 76
0360c046
HK		 77#define OCP_STD_PHY_BASE 0xa400
78
145a40e8
HK		 79#define RTL_CFG_NO_GBIT 1
80
1da177e4 81/* write/read MMIO register */
1ef7286e
AS		 82#define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
83#define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
84#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
85#define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
86#define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
87#define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
1da177e4 88
b410439c
HK		 89#define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
90#define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
91#define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
92#define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
473367a5 93#define JUMBO_16K (SZ_16K - VLAN_ETH_HLEN - ETH_FCS_LEN)
d58d46b5 94
2b065c09
HK		 95static const struct rtl_chip_info {
96 u16 mask;
97 u16 val;
98 enum mac_version mac_version;
1da177e4 99 const char *name;
953a12cc 100 const char *fw_name;
85bffe6c 101} rtl_chip_infos[] = {
f24f7b2f
CL		 102 /* 8127A family. */
103 { 0x7cf, 0x6c9, RTL_GIGA_MAC_VER_80, "RTL8127A", FIRMWARE_8127A_1 },
104
2b065c09 105 /* 8126A family. */
4dec0702 106 { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_70, "RTL8126A", FIRMWARE_8126A_3 },
2b065c09
HK		 107 { 0x7cf, 0x649, RTL_GIGA_MAC_VER_70, "RTL8126A", FIRMWARE_8126A_2 },
108
109 /* 8125BP family. */
110 { 0x7cf, 0x681, RTL_GIGA_MAC_VER_66, "RTL8125BP", FIRMWARE_8125BP_2 },
111
112 /* 8125D family. */
f372ef6e 113 { 0x7cf, 0x689, RTL_GIGA_MAC_VER_64, "RTL8125D", FIRMWARE_8125D_2 },
2b065c09
HK		 114 { 0x7cf, 0x688, RTL_GIGA_MAC_VER_64, "RTL8125D", FIRMWARE_8125D_1 },
115
116 /* 8125B family. */
117 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63, "RTL8125B", FIRMWARE_8125B_2 },
118
119 /* 8125A family. */
120 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61, "RTL8125A", FIRMWARE_8125A_3 },
121
122 /* RTL8117 */
4f51e7d3 123 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_52, "RTL8168fp/RTL8117" },
2b065c09
HK		 124 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52, "RTL8168fp/RTL8117",
125 FIRMWARE_8168FP_3 },
126
127 /* 8168EP family. */
128 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51, "RTL8168ep/8111ep" },
129
130 /* 8168H family. */
131 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46, "RTL8168h/8111h",
132 FIRMWARE_8168H_2 },
133 /* Realtek calls it RTL8168M, but it's handled like RTL8168H */
134 { 0x7cf, 0x6c0, RTL_GIGA_MAC_VER_46, "RTL8168M", FIRMWARE_8168H_2 },
135
136 /* 8168G family. */
137 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44, "RTL8411b", FIRMWARE_8411_2 },
138 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42, "RTL8168gu/8111gu",
139 FIRMWARE_8168G_3 },
140 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40, "RTL8168g/8111g",
141 FIRMWARE_8168G_2 },
142
143 /* 8168F family. */
144 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38, "RTL8411", FIRMWARE_8411_1 },
145 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36, "RTL8168f/8111f",
146 FIRMWARE_8168F_2 },
147 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35, "RTL8168f/8111f",
148 FIRMWARE_8168F_1 },
149
150 /* 8168E family. */
151 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34, "RTL8168evl/8111evl",
152 FIRMWARE_8168E_3 },
153 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32, "RTL8168e/8111e",
154 FIRMWARE_8168E_1 },
155 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33, "RTL8168e/8111e",
156 FIRMWARE_8168E_2 },
157
158 /* 8168D family. */
159 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25, "RTL8168d/8111d",
160 FIRMWARE_8168D_1 },
161 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26, "RTL8168d/8111d",
162 FIRMWARE_8168D_2 },
163
164 /* 8168DP family. */
165 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28, "RTL8168dp/8111dp" },
166 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31, "RTL8168dp/8111dp" },
167
168 /* 8168C family. */
169 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23, "RTL8168cp/8111cp" },
170 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18, "RTL8168cp/8111cp" },
171 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24, "RTL8168cp/8111cp" },
172 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19, "RTL8168c/8111c" },
173 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20, "RTL8168c/8111c" },
174 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21, "RTL8168c/8111c" },
175 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22, "RTL8168c/8111c" },
176
177 /* 8168B family. */
178 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17, "RTL8168b/8111b" },
179 /* This one is very old and rare, support has been removed.
180 * { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11, "RTL8168b/8111b" },
181 */
182
183 /* 8101 family. */
184 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39, "RTL8106e", FIRMWARE_8106E_1 },
185 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37, "RTL8402", FIRMWARE_8402_1 },
186 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29, "RTL8105e", FIRMWARE_8105E_1 },
187 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30, "RTL8105e", FIRMWARE_8105E_1 },
188 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08, "RTL8102e" },
189 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08, "RTL8102e" },
190 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07, "RTL8102e" },
191 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07, "RTL8102e" },
192 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14, "RTL8401" },
193 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09, "RTL8102e/RTL8103e" },
194 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09, "RTL8102e/RTL8103e" },
195 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10, "RTL8101e/RTL8100e" },
196
197 /* 8110 family. */
198 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06, "RTL8169sc/8110sc" },
199 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05, "RTL8169sc/8110sc" },
200 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04, "RTL8169sb/8110sb" },
201 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03, "RTL8110s" },
202 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02, "RTL8169s" },
203
204 /* Catch-all */
205 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
953a12cc
FR		 206};
207
9baa3c34 208static const struct pci_device_id rtl8169_pci_tbl[] = {
145a40e8
HK		 209 { PCI_VDEVICE(REALTEK, 0x2502) },
210 { PCI_VDEVICE(REALTEK, 0x2600) },
211 { PCI_VDEVICE(REALTEK, 0x8129) },
212 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
213 { PCI_VDEVICE(REALTEK, 0x8161) },
72f898ca 214 { PCI_VDEVICE(REALTEK, 0x8162) },
145a40e8
HK		 215 { PCI_VDEVICE(REALTEK, 0x8167) },
216 { PCI_VDEVICE(REALTEK, 0x8168) },
217 { PCI_VDEVICE(NCUBE, 0x8168) },
218 { PCI_VDEVICE(REALTEK, 0x8169) },
6f0d3088 219 { PCI_VENDOR_ID_DLINK, 0x4300,
145a40e8 220 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
9d9f3fba
HK		 221 { PCI_VDEVICE(DLINK, 0x4300) },
222 { PCI_VDEVICE(DLINK, 0x4302) },
223 { PCI_VDEVICE(AT, 0xc107) },
224 { PCI_VDEVICE(USR, 0x0116) },
225 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
226 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
f1bce4ad 227 { PCI_VDEVICE(REALTEK, 0x8125) },
3907f1ff 228 { PCI_VDEVICE(REALTEK, 0x8126) },
f24f7b2f 229 { PCI_VDEVICE(REALTEK, 0x8127) },
f1bce4ad 230 { PCI_VDEVICE(REALTEK, 0x3000) },
d30460f4 231 { PCI_VDEVICE(REALTEK, 0x5000) },
f24f7b2f 232 { PCI_VDEVICE(REALTEK, 0x0e10) },
6f0d3088 233 {}
1da177e4
LT		 234};
235
236MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
237
07d3f51f
FR		 238enum rtl_registers {
239 MAC0 = 0, /* Ethernet hardware address. */
773d2021 240 MAC4 = 4,
07d3f51f
FR		 241 MAR0 = 8, /* Multicast filter. */
242 CounterAddrLow = 0x10,
243 CounterAddrHigh = 0x14,
244 TxDescStartAddrLow = 0x20,
245 TxDescStartAddrHigh = 0x24,
246 TxHDescStartAddrLow = 0x28,
247 TxHDescStartAddrHigh = 0x2c,
248 FLASH = 0x30,
249 ERSR = 0x36,
250 ChipCmd = 0x37,
251 TxPoll = 0x38,
252 IntrMask = 0x3c,
253 IntrStatus = 0x3e,
4f6b00e5 254
07d3f51f 255 TxConfig = 0x40,
4f6b00e5
HW		 256#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
257#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 258
4f6b00e5
HW		 259 RxConfig = 0x44,
260#define RX128_INT_EN (1 << 15) /* 8111c and later */
261#define RX_MULTI_EN (1 << 14) /* 8111c only */
262#define RXCFG_FIFO_SHIFT 13
263 /* No threshold before first PCI xfer */
264#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 265#define RX_EARLY_OFF (1 << 11)
4b0768b6 266#define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */
4f6b00e5
HW		 267#define RXCFG_DMA_SHIFT 8
268 /* Unlimited maximum PCI burst. */
269#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 270
07d3f51f
FR		 271 Cfg9346 = 0x50,
272 Config0 = 0x51,
273 Config1 = 0x52,
274 Config2 = 0x53,
d387b427
FR		 275#define PME_SIGNAL (1 << 5) /* 8168c and later */
276
07d3f51f
FR		 277 Config3 = 0x54,
278 Config4 = 0x55,
279 Config5 = 0x56,
07d3f51f 280 PHYAR = 0x60,
07d3f51f
FR		 281 PHYstatus = 0x6c,
282 RxMaxSize = 0xda,
283 CPlusCmd = 0xe0,
284 IntrMitigate = 0xe2,
50970831 285
6cf96dd4
HK		 286#define RTL_COALESCE_TX_USECS GENMASK(15, 12)
287#define RTL_COALESCE_TX_FRAMES GENMASK(11, 8)
288#define RTL_COALESCE_RX_USECS GENMASK(7, 4)
289#define RTL_COALESCE_RX_FRAMES GENMASK(3, 0)
290
2b3e48b6
HK		 291#define RTL_COALESCE_T_MAX 0x0fU
292#define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4)
50970831 293
07d3f51f
FR		 294 RxDescAddrLow = 0xe4,
295 RxDescAddrHigh = 0xe8,
f0298f81 296 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
297
298#define NoEarlyTx 0x3f /* Max value : no early transmit. */
299
300 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
301
302#define TxPacketMax (8064 >> 7)
3090bd9a 303#define EarlySize 0x27
f0298f81 304
07d3f51f
FR		 305 FuncEvent = 0xf0,
306 FuncEventMask = 0xf4,
307 FuncPresetState = 0xf8,
935e2218
CHL		 308 IBCR0 = 0xf8,
309 IBCR2 = 0xf9,
310 IBIMR0 = 0xfa,
311 IBISR0 = 0xfb,
07d3f51f 312 FuncForceEvent = 0xfc,
1da177e4
LT		 313};
314
f162a5d1
FR		 315enum rtl8168_8101_registers {
316 CSIDR = 0x64,
317 CSIAR = 0x68,
318#define CSIAR_FLAG 0x80000000
319#define CSIAR_WRITE_CMD 0x80000000
ff1d7331
HK		 320#define CSIAR_BYTE_ENABLE 0x0000f000
321#define CSIAR_ADDR_MASK 0x00000fff
065c27c1 322 PMCH = 0x6f,
128735a1
HK		 323#define D3COLD_NO_PLL_DOWN BIT(7)
324#define D3HOT_NO_PLL_DOWN BIT(6)
325#define D3_NO_PLL_DOWN (BIT(7) | BIT(6))
f162a5d1
FR		 326 EPHYAR = 0x80,
327#define EPHYAR_FLAG 0x80000000
328#define EPHYAR_WRITE_CMD 0x80000000
329#define EPHYAR_REG_MASK 0x1f
330#define EPHYAR_REG_SHIFT 16
331#define EPHYAR_DATA_MASK 0xffff
5a5e4443 332 DLLPR = 0xd0,
4f6b00e5 333#define PFM_EN (1 << 6)
6e1d0b89 334#define TX_10M_PS_EN (1 << 7)
f162a5d1
FR		 335 DBG_REG = 0xd1,
336#define FIX_NAK_1 (1 << 4)
337#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 338 TWSI = 0xd2,
339 MCU = 0xd3,
4f6b00e5 340#define NOW_IS_OOB (1 << 7)
c558386b
HW		 341#define TX_EMPTY (1 << 5)
342#define RX_EMPTY (1 << 4)
343#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 344#define EN_NDP (1 << 3)
345#define EN_OOB_RESET (1 << 2)
c558386b 346#define LINK_LIST_RDY (1 << 1)
daf9df6d 347 EFUSEAR = 0xdc,
348#define EFUSEAR_FLAG 0x80000000
349#define EFUSEAR_WRITE_CMD 0x80000000
350#define EFUSEAR_READ_CMD 0x00000000
351#define EFUSEAR_REG_MASK 0x03ff
352#define EFUSEAR_REG_SHIFT 8
353#define EFUSEAR_DATA_MASK 0xff
6e1d0b89
CHL		 354 MISC_1 = 0xf2,
355#define PFM_D3COLD_EN (1 << 6)
f162a5d1
FR		 356};
357
c0e45c1c 358enum rtl8168_registers {
18764b88 359 LED_CTRL = 0x18,
4f6b00e5
HW		 360 LED_FREQ = 0x1a,
361 EEE_LED = 0x1b,
b646d900 362 ERIDR = 0x70,
363 ERIAR = 0x74,
364#define ERIAR_FLAG 0x80000000
365#define ERIAR_WRITE_CMD 0x80000000
366#define ERIAR_READ_CMD 0x00000000
367#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 368#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 369#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
370#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
371#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
935e2218 372#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
4f6b00e5
HW		 373#define ERIAR_MASK_SHIFT 12
374#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
375#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
6e1d0b89 376#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
c558386b 377#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 378#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 379 EPHY_RXER_NUM = 0x7c,
380 OCPDR = 0xb0, /* OCP GPHY access */
381#define OCPDR_WRITE_CMD 0x80000000
382#define OCPDR_READ_CMD 0x00000000
383#define OCPDR_REG_MASK 0x7f
384#define OCPDR_GPHY_REG_SHIFT 16
385#define OCPDR_DATA_MASK 0xffff
386 OCPAR = 0xb4,
387#define OCPAR_FLAG 0x80000000
388#define OCPAR_GPHY_WRITE_CMD 0x8000f060
389#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 390 GPHY_OCP = 0xb8,
01dc7fec 391 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
392 MISC = 0xf0, /* 8168e only. */
cecb5fd7 393#define TXPLA_RST (1 << 29)
5598bfe5 394#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 395#define PWM_EN (1 << 22)
c558386b 396#define RXDV_GATED_EN (1 << 19)
5598bfe5 397#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 398};
399
f1bce4ad 400enum rtl8125_registers {
be51ed10 401 LEDSEL0 = 0x18,
3907f1ff
HK		 402 INT_CFG0_8125 = 0x34,
403#define INT_CFG0_ENABLE_8125 BIT(0)
404#define INT_CFG0_CLKREQEN BIT(3)
f1bce4ad
HK		 405 IntrMask_8125 = 0x38,
406 IntrStatus_8125 = 0x3c,
3907f1ff 407 INT_CFG1_8125 = 0x7a,
be51ed10
HK		 408 LEDSEL2 = 0x84,
409 LEDSEL1 = 0x86,
f1bce4ad 410 TxPoll_8125 = 0x90,
be51ed10 411 LEDSEL3 = 0x96,
f1bce4ad 412 MAC0_BKP = 0x19e0,
2cd02f2f
HK		 413 RSS_CTRL_8125 = 0x4500,
414 Q_NUM_CTRL_8125 = 0x4800,
0439297b 415 EEE_TXIDLE_TIMER_8125 = 0x6048,
f1bce4ad
HK		 416};
417
be51ed10
HK		 418#define LEDSEL_MASK_8125 0x23f
419
f1bce4ad
HK		 420#define RX_VLAN_INNER_8125 BIT(22)
421#define RX_VLAN_OUTER_8125 BIT(23)
422#define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
423
424#define RX_FETCH_DFLT_8125 (8 << 27)
425
07d3f51f 426enum rtl_register_content {
1da177e4 427 /* InterruptStatusBits */
07d3f51f
FR		 428 SYSErr = 0x8000,
429 PCSTimeout = 0x4000,
430 SWInt = 0x0100,
431 TxDescUnavail = 0x0080,
432 RxFIFOOver = 0x0040,
433 LinkChg = 0x0020,
434 RxOverflow = 0x0010,
435 TxErr = 0x0008,
436 TxOK = 0x0004,
437 RxErr = 0x0002,
438 RxOK = 0x0001,
1da177e4
LT		 439
440 /* RxStatusDesc */
9dccf611
FR		 441 RxRWT = (1 << 22),
442 RxRES = (1 << 21),
443 RxRUNT = (1 << 20),
444 RxCRC = (1 << 19),
1da177e4
LT		 445
446 /* ChipCmdBits */
4f6b00e5 447 StopReq = 0x80,
07d3f51f
FR		 448 CmdReset = 0x10,
449 CmdRxEnb = 0x08,
450 CmdTxEnb = 0x04,
451 RxBufEmpty = 0x01,
1da177e4 452
275391a4
FR		 453 /* TXPoll register p.5 */
454 HPQ = 0x80, /* Poll cmd on the high prio queue */
455 NPQ = 0x40, /* Poll cmd on the low prio queue */
456 FSWInt = 0x01, /* Forced software interrupt */
457
1da177e4 458 /* Cfg9346Bits */
07d3f51f
FR		 459 Cfg9346_Lock = 0x00,
460 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 461
462 /* rx_mode_bits */
07d3f51f
FR		 463 AcceptErr = 0x20,
464 AcceptRunt = 0x10,
10478283 465#define RX_CONFIG_ACCEPT_ERR_MASK 0x30
07d3f51f
FR		 466 AcceptBroadcast = 0x08,
467 AcceptMulticast = 0x04,
468 AcceptMyPhys = 0x02,
469 AcceptAllPhys = 0x01,
10478283 470#define RX_CONFIG_ACCEPT_OK_MASK 0x0f
1687b566 471#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 472
1da177e4
LT		 473 /* TxConfigBits */
474 TxInterFrameGapShift = 24,
475 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
476
5d06a99f 477 /* Config1 register p.24 */
f162a5d1
FR		 478 LEDS1 = (1 << 7),
479 LEDS0 = (1 << 6),
f162a5d1
FR		 480 Speed_down = (1 << 4),
481 MEMMAP = (1 << 3),
482 IOMAP = (1 << 2),
483 VPD = (1 << 1),
5d06a99f
FR		 484 PMEnable = (1 << 0), /* Power Management Enable */
485
6dccd16b 486 /* Config2 register p. 25 */
57538c4a 487 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 488 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 489 PCI_Clock_66MHz = 0x01,
490 PCI_Clock_33MHz = 0x00,
491
61a4dcc2
FR		 492 /* Config3 register p.25 */
493 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
494 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 495 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
b51ecea8 496 Rdy_to_L23 = (1 << 1), /* L23 Enable */
f162a5d1 497 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 498
d58d46b5
FR		 499 /* Config4 register */
500 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
501
5d06a99f 502 /* Config5 register p.27 */
61a4dcc2
FR		 503 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
504 MWF = (1 << 5), /* Accept Multicast wakeup frame */
505 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 506 Spi_en = (1 << 3),
61a4dcc2 507 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 508 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
57538c4a 509 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 510
1da177e4 511 /* CPlusCmd p.31 */
f162a5d1
FR		 512 EnableBist = (1 << 15), // 8168 8101
513 Mac_dbgo_oe = (1 << 14), // 8168 8101
09e65335 514 EnAnaPLL = (1 << 14), // 8169
f162a5d1
FR		 515 Normal_mode = (1 << 13), // unused
516 Force_half_dup = (1 << 12), // 8168 8101
517 Force_rxflow_en = (1 << 11), // 8168 8101
518 Force_txflow_en = (1 << 10), // 8168 8101
519 Cxpl_dbg_sel = (1 << 9), // 8168 8101
520 ASF = (1 << 8), // 8168 8101
521 PktCntrDisable = (1 << 7), // 8168 8101
522 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 523 RxVlan = (1 << 6),
524 RxChkSum = (1 << 5),
525 PCIDAC = (1 << 4),
526 PCIMulRW = (1 << 3),
9a3c81fa 527#define INTT_MASK GENMASK(1, 0)
bc73241e 528#define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
1da177e4
LT		 529
530 /* rtl8169_PHYstatus */
07d3f51f
FR		 531 TBI_Enable = 0x80,
532 TxFlowCtrl = 0x40,
533 RxFlowCtrl = 0x20,
534 _1000bpsF = 0x10,
535 _100bps = 0x08,
536 _10bps = 0x04,
537 LinkStatus = 0x02,
538 FullDup = 0x01,
1da177e4 539
6e85d5ad
CV		 540 /* ResetCounterCommand */
541 CounterReset = 0x1,
542
d4a3a0fc 543 /* DumpCounterCommand */
07d3f51f 544 CounterDump = 0x8,
6e1d0b89
CHL		 545
546 /* magic enable v2 */
547 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
1da177e4
LT		 548};
549
2b7b4318
FR		 550enum rtl_desc_bit {
551 /* First doubleword. */
1da177e4
LT		 552 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
553 RingEnd = (1 << 30), /* End of descriptor ring */
554 FirstFrag = (1 << 29), /* First segment of a packet */
555 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 556};
557
558/* Generic case. */
559enum rtl_tx_desc_bit {
560 /* First doubleword. */
561 TD_LSO = (1 << 27), /* Large Send Offload */
562#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 563
2b7b4318
FR		 564 /* Second doubleword. */
565 TxVlanTag = (1 << 17), /* Add VLAN tag */
566};
567
568/* 8169, 8168b and 810x except 8102e. */
569enum rtl_tx_desc_bit_0 {
570 /* First doubleword. */
571#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
572 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
573 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
574 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
575};
576
577/* 8102e, 8168c and beyond. */
578enum rtl_tx_desc_bit_1 {
bdfa4ed6 579 /* First doubleword. */
580 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
e974604b 581 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
bdfa4ed6 582#define GTTCPHO_SHIFT 18
e64e0c89 583#define GTTCPHO_MAX 0x7f
bdfa4ed6 584
2b7b4318 585 /* Second doubleword. */
e974604b 586#define TCPHO_SHIFT 18
e64e0c89 587#define TCPHO_MAX 0x3ff
2b7b4318 588#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
e974604b 589 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
590 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
2b7b4318
FR		 591 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
592 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
593};
1da177e4 594
2b7b4318 595enum rtl_rx_desc_bit {
1da177e4
LT		 596 /* Rx private */
597 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
9b60047a 598 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
1da177e4
LT		 599
600#define RxProtoUDP (PID1)
601#define RxProtoTCP (PID0)
602#define RxProtoIP (PID1 | PID0)
603#define RxProtoMask RxProtoIP
604
605 IPFail = (1 << 16), /* IP checksum failed */
606 UDPFail = (1 << 15), /* UDP/IP checksum failed */
607 TCPFail = (1 << 14), /* TCP/IP checksum failed */
206a75e0
HK		 608
609#define RxCSFailMask (IPFail | UDPFail | TCPFail)
610
1da177e4
LT		 611 RxVlanTag = (1 << 16), /* VLAN tag available */
612};
613
0170d594
HK		 614#define RTL_GSO_MAX_SIZE_V1 32000
615#define RTL_GSO_MAX_SEGS_V1 24
616#define RTL_GSO_MAX_SIZE_V2 64000
617#define RTL_GSO_MAX_SEGS_V2 64
618
1da177e4 619struct TxDesc {
6cccd6e7
REB		 620 __le32 opts1;
621 __le32 opts2;
622 __le64 addr;
1da177e4
LT		 623};
624
625struct RxDesc {
6cccd6e7
REB		 626 __le32 opts1;
627 __le32 opts2;
628 __le64 addr;
1da177e4
LT		 629};
630
631struct ring_info {
632 struct sk_buff *skb;
633 u32 len;
1da177e4
LT		 634};
635
355423d0
IV		 636struct rtl8169_counters {
637 __le64 tx_packets;
638 __le64 rx_packets;
639 __le64 tx_errors;
640 __le32 rx_errors;
641 __le16 rx_missed;
642 __le16 align_errors;
643 __le32 tx_one_collision;
644 __le32 tx_multi_collision;
645 __le64 rx_unicast;
646 __le64 rx_broadcast;
647 __le32 rx_multicast;
648 __le16 tx_aborted;
8df94393 649 __le16 tx_underrun;
ced8e8b8
HK		 650 /* new since RTL8125 */
651 __le64 tx_octets;
652 __le64 rx_octets;
653 __le64 rx_multicast64;
654 __le64 tx_unicast64;
655 __le64 tx_broadcast64;
656 __le64 tx_multicast64;
657 __le32 tx_pause_on;
658 __le32 tx_pause_off;
659 __le32 tx_pause_all;
660 __le32 tx_deferred;
661 __le32 tx_late_collision;
662 __le32 tx_all_collision;
663 __le32 tx_aborted32;
664 __le32 align_errors32;
665 __le32 rx_frame_too_long;
666 __le32 rx_runt;
667 __le32 rx_pause_on;
668 __le32 rx_pause_off;
669 __le32 rx_pause_all;
670 __le32 rx_unknown_opcode;
671 __le32 rx_mac_error;
672 __le32 tx_underrun32;
673 __le32 rx_mac_missed;
674 __le32 rx_tcam_dropped;
675 __le32 tdu;
676 __le32 rdu;
355423d0
IV		 677};
678
6e85d5ad
CV		 679struct rtl8169_tc_offsets {
680 bool inited;
681 __le64 tx_errors;
682 __le32 tx_multi_collision;
6e85d5ad 683 __le16 tx_aborted;
0da3359a 684 __le16 rx_missed;
6e85d5ad
CV		 685};
686
da78dbff 687enum rtl_flag {
da78dbff 688 RTL_FLAG_TASK_RESET_PENDING,
80c0576e 689 RTL_FLAG_TASK_TX_TIMEOUT,
da78dbff
FR		 690 RTL_FLAG_MAX
691};
692
e0d38b58
HK		 693enum rtl_dash_type {
694 RTL_DASH_NONE,
695 RTL_DASH_DP,
696 RTL_DASH_EP,
b11bff90 697 RTL_DASH_25_BP,
e0d38b58
HK		 698};
699
1da177e4
LT		 700struct rtl8169_private {
701 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 702 struct pci_dev *pci_dev;
c4028958 703 struct net_device *dev;
703732f0 704 struct phy_device *phydev;
bea3348e 705 struct napi_struct napi;
76719ee2 706 enum mac_version mac_version;
e0d38b58 707 enum rtl_dash_type dash_type;
1da177e4
LT		 708 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
709 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4
LT		 710 u32 dirty_tx;
711 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
712 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
713 dma_addr_t TxPhyAddr;
714 dma_addr_t RxPhyAddr;
32879f00 715 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 716 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4 717 u16 cp_cmd;
2ce30993 718 u16 tx_lpi_timer;
c1d532d2 719 u32 irq_mask;
1bd32771 720 int irq;
c2f6f3ee 721 struct clk *clk;
c0e45c1c 722
4422bcd4 723 struct {
da78dbff 724 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
4422bcd4
FR		 725 struct work_struct work;
726 } wk;
727
d6c36cbc 728 raw_spinlock_t mac_ocp_lock;
18764b88 729 struct mutex led_lock; /* serialize LED ctrl RMW access */
91c86435 730
f7ffa9ae 731 unsigned supports_gmii:1;
cf2ffdea 732 unsigned aspm_manageable:1;
0ab0c45d 733 unsigned dash_enabled:1;
42020320
CV		 734 dma_addr_t counters_phys_addr;
735 struct rtl8169_counters *counters;
6e85d5ad 736 struct rtl8169_tc_offsets tc_offset;
e1759441 737 u32 saved_wolopts;
f1e02ed1 738
254764e5 739 const char *fw_name;
8197f9d2 740 struct rtl_fw *rtl_fw;
c558386b 741
19fa4f2a
HK		 742 struct r8169_led_classdev *leds;
743
c558386b 744 u32 ocp_base;
1da177e4
LT		 745};
746
1fcd1658
HK		 747typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
748
979b6c13 749MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 750MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
11287b69 751MODULE_SOFTDEP("pre: realtek");
1da177e4 752MODULE_LICENSE("GPL");
bca03d5f 753MODULE_FIRMWARE(FIRMWARE_8168D_1);
754MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 755MODULE_FIRMWARE(FIRMWARE_8168E_1);
756MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 757MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 758MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 759MODULE_FIRMWARE(FIRMWARE_8168F_1);
760MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 761MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 762MODULE_FIRMWARE(FIRMWARE_8411_1);
45dd95c4 763MODULE_FIRMWARE(FIRMWARE_8411_2);
5598bfe5 764MODULE_FIRMWARE(FIRMWARE_8106E_1);
58152cd4 765MODULE_FIRMWARE(FIRMWARE_8106E_2);
beb330a4 766MODULE_FIRMWARE(FIRMWARE_8168G_2);
57538c4a 767MODULE_FIRMWARE(FIRMWARE_8168G_3);
6e1d0b89 768MODULE_FIRMWARE(FIRMWARE_8168H_2);
229c1e0d 769MODULE_FIRMWARE(FIRMWARE_8168FP_3);
a3bf5c42 770MODULE_FIRMWARE(FIRMWARE_8107E_2);
02bf642b 771MODULE_FIRMWARE(FIRMWARE_8125A_3);
0439297b 772MODULE_FIRMWARE(FIRMWARE_8125B_2);
f75d1fbe 773MODULE_FIRMWARE(FIRMWARE_8125D_1);
b3593df2 774MODULE_FIRMWARE(FIRMWARE_8125D_2);
b11bff90 775MODULE_FIRMWARE(FIRMWARE_8125BP_2);
f4d3e595 776MODULE_FIRMWARE(FIRMWARE_8126A_2);
3b067536 777MODULE_FIRMWARE(FIRMWARE_8126A_3);
f24f7b2f 778MODULE_FIRMWARE(FIRMWARE_8127A_1);
1da177e4 779
1e1205b7
HK		 780static inline struct device *tp_to_dev(struct rtl8169_private *tp)
781{
782 return &tp->pci_dev->dev;
783}
784
df320ed7
HK		 785static void rtl_lock_config_regs(struct rtl8169_private *tp)
786{
83cb4b47 787 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
df320ed7
HK		 788}
789
790static void rtl_unlock_config_regs(struct rtl8169_private *tp)
791{
83cb4b47 792 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
df320ed7
HK		 793}
794
711463f8
HK		 795static void rtl_pci_commit(struct rtl8169_private *tp)
796{
797 /* Read an arbitrary register to commit a preceding PCI write */
798 RTL_R8(tp, ChipCmd);
799}
800
6bc6c4e6
HK		 801static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set)
802{
6bc6c4e6
HK		 803 u8 val;
804
6bc6c4e6
HK		 805 val = RTL_R8(tp, Config2);
806 RTL_W8(tp, Config2, (val & ~clear) | set);
6bc6c4e6
HK		 807}
808
809static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set)
810{
6bc6c4e6
HK		 811 u8 val;
812
6bc6c4e6
HK		 813 val = RTL_R8(tp, Config5);
814 RTL_W8(tp, Config5, (val & ~clear) | set);
6bc6c4e6
HK		 815}
816
c507e96b
HK		 817static void r8169_mod_reg8_cond(struct rtl8169_private *tp, int reg,
818 u8 bits, bool cond)
819{
820 u8 val, old_val;
821
822 old_val = RTL_R8(tp, reg);
823 if (cond)
824 val = old_val | bits;
825 else
826 val = old_val & ~bits;
827 if (val != old_val)
828 RTL_W8(tp, reg, val);
829}
830
f1bce4ad
HK		 831static bool rtl_is_8125(struct rtl8169_private *tp)
832{
efc37109 833 return tp->mac_version >= RTL_GIGA_MAC_VER_61;
f1bce4ad
HK		 834}
835
9e9f33ba
HK		 836static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
837{
838 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
c623305b 839 tp->mac_version != RTL_GIGA_MAC_VER_39 &&
4f51e7d3 840 tp->mac_version <= RTL_GIGA_MAC_VER_52;
9e9f33ba
HK		 841}
842
2e779ddb
HK		 843static bool rtl_supports_eee(struct rtl8169_private *tp)
844{
845 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
846 tp->mac_version != RTL_GIGA_MAC_VER_37 &&
847 tp->mac_version != RTL_GIGA_MAC_VER_39;
848}
849
ce37115e
HK		 850static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
851{
852 int i;
853
854 for (i = 0; i < ETH_ALEN; i++)
855 mac[i] = RTL_R8(tp, reg + i);
856}
857
ffc46952
FR		 858struct rtl_cond {
859 bool (*check)(struct rtl8169_private *);
860 const char *msg;
861};
862
ffc46952 863static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
d6836ef0 864 unsigned long usecs, int n, bool high)
ffc46952
FR		 865{
866 int i;
867
868 for (i = 0; i < n; i++) {
ffc46952
FR		 869 if (c->check(tp) == high)
870 return true;
d6836ef0 871 fsleep(usecs);
ffc46952 872 }
93882c6f
HK		 873
874 if (net_ratelimit())
d6836ef0
HK		 875 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
876 c->msg, !high, n, usecs);
ffc46952
FR		 877 return false;
878}
879
d6836ef0
HK		 880static bool rtl_loop_wait_high(struct rtl8169_private *tp,
881 const struct rtl_cond *c,
882 unsigned long d, int n)
ffc46952 883{
d6836ef0 884 return rtl_loop_wait(tp, c, d, n, true);
ffc46952
FR		 885}
886
d6836ef0
HK		 887static bool rtl_loop_wait_low(struct rtl8169_private *tp,
888 const struct rtl_cond *c,
889 unsigned long d, int n)
ffc46952 890{
d6836ef0 891 return rtl_loop_wait(tp, c, d, n, false);
ffc46952
FR		 892}
893
894#define DECLARE_RTL_COND(name) \
895static bool name ## _check(struct rtl8169_private *); \
896 \
897static const struct rtl_cond name = { \
898 .check = name ## _check, \
899 .msg = #name \
900}; \
901 \
902static bool name ## _check(struct rtl8169_private *tp)
903
18764b88
HK		 904int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val)
905{
906 struct device *dev = tp_to_dev(tp);
907 int ret;
908
909 ret = pm_runtime_resume_and_get(dev);
910 if (ret < 0)
911 return ret;
912
913 mutex_lock(&tp->led_lock);
914 RTL_W16(tp, LED_CTRL, (RTL_R16(tp, LED_CTRL) & ~mask) | val);
915 mutex_unlock(&tp->led_lock);
916
917 pm_runtime_put_sync(dev);
918
919 return 0;
920}
921
922int rtl8168_get_led_mode(struct rtl8169_private *tp)
923{
924 struct device *dev = tp_to_dev(tp);
925 int ret;
926
927 ret = pm_runtime_resume_and_get(dev);
928 if (ret < 0)
929 return ret;
930
931 ret = RTL_R16(tp, LED_CTRL);
932
933 pm_runtime_put_sync(dev);
934
935 return ret;
936}
937
be51ed10
HK		 938static int rtl8125_get_led_reg(int index)
939{
940 static const int led_regs[] = { LEDSEL0, LEDSEL1, LEDSEL2, LEDSEL3 };
941
942 return led_regs[index];
943}
944
945int rtl8125_set_led_mode(struct rtl8169_private *tp, int index, u16 mode)
946{
947 int reg = rtl8125_get_led_reg(index);
948 struct device *dev = tp_to_dev(tp);
949 int ret;
950 u16 val;
951
952 ret = pm_runtime_resume_and_get(dev);
953 if (ret < 0)
954 return ret;
955
956 mutex_lock(&tp->led_lock);
957 val = RTL_R16(tp, reg) & ~LEDSEL_MASK_8125;
958 RTL_W16(tp, reg, val | mode);
959 mutex_unlock(&tp->led_lock);
960
961 pm_runtime_put_sync(dev);
962
963 return 0;
964}
965
966int rtl8125_get_led_mode(struct rtl8169_private *tp, int index)
967{
968 int reg = rtl8125_get_led_reg(index);
969 struct device *dev = tp_to_dev(tp);
970 int ret;
971
972 ret = pm_runtime_resume_and_get(dev);
973 if (ret < 0)
974 return ret;
975
976 ret = RTL_R16(tp, reg);
977
978 pm_runtime_put_sync(dev);
979
980 return ret;
981}
982
18764b88
HK		 983void r8169_get_led_name(struct rtl8169_private *tp, int idx,
984 char *buf, int buf_len)
985{
986 struct pci_dev *pdev = tp->pci_dev;
987 char pdom[8], pfun[8];
988 int domain;
989
990 domain = pci_domain_nr(pdev->bus);
991 if (domain)
992 snprintf(pdom, sizeof(pdom), "P%d", domain);
993 else
994 pdom[0] = '\0';
995
996 if (pdev->multifunction)
997 snprintf(pfun, sizeof(pfun), "f%d", PCI_FUNC(pdev->devfn));
998 else
999 pfun[0] = '\0';
1000
1001 snprintf(buf, buf_len, "en%sp%ds%d%s-%d::lan", pdom, pdev->bus->number,
1002 PCI_SLOT(pdev->devfn), pfun, idx);
1003}
1004
c6cff9df
HK		 1005static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
1006{
1007 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
4f51e7d3 1008 if (type == ERIAR_OOB && tp->mac_version == RTL_GIGA_MAC_VER_52)
abbf9a0e 1009 *cmd |= 0xf70 << 18;
c6cff9df
HK		 1010}
1011
1012DECLARE_RTL_COND(rtl_eriar_cond)
1013{
1014 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1015}
1016
1017static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1018 u32 val, int type)
1019{
1020 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
1021
5f1e1224
HK		 1022 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask))
1023 return;
1024
c6cff9df
HK		 1025 RTL_W32(tp, ERIDR, val);
1026 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
1027 RTL_W32(tp, ERIAR, cmd);
1028
1029 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1030}
1031
1032static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1033 u32 val)
1034{
1035 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1036}
1037
1038static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1039{
1040 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
1041
1042 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
1043 RTL_W32(tp, ERIAR, cmd);
1044
1045 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1046 RTL_R32(tp, ERIDR) : ~0;
1047}
1048
1049static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1050{
1051 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1052}
1053
1054static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
1055{
1056 u32 val = rtl_eri_read(tp, addr);
1057
1058 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
1059}
1060
1061static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
1062{
1063 rtl_w0w1_eri(tp, addr, p, 0);
1064}
1065
1066static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
1067{
1068 rtl_w0w1_eri(tp, addr, 0, m);
1069}
1070
a46604d7 1071static bool rtl_ocp_reg_failure(u32 reg)
c558386b 1072{
a46604d7 1073 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg);
c558386b
HW		 1074}
1075
1076DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1077{
1ef7286e 1078 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
c558386b
HW		 1079}
1080
1081static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1082{
a46604d7 1083 if (rtl_ocp_reg_failure(reg))
c558386b
HW		 1084 return;
1085
1ef7286e 1086 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
c558386b 1087
d6836ef0 1088 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
c558386b
HW		 1089}
1090
9b994b4a 1091static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
c558386b 1092{
a46604d7 1093 if (rtl_ocp_reg_failure(reg))
c558386b
HW		 1094 return 0;
1095
1ef7286e 1096 RTL_W32(tp, GPHY_OCP, reg << 15);
c558386b 1097
d6836ef0 1098 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
9b994b4a 1099 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
c558386b
HW		 1100}
1101
91c86435 1102static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
c558386b 1103{
a46604d7 1104 if (rtl_ocp_reg_failure(reg))
c558386b
HW		 1105 return;
1106
1ef7286e 1107 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 1108}
1109
91c86435
HK		 1110static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1111{
1112 unsigned long flags;
1113
d6c36cbc 1114 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
91c86435 1115 __r8168_mac_ocp_write(tp, reg, data);
d6c36cbc 1116 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
91c86435
HK		 1117}
1118
1119static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
c558386b 1120{
a46604d7 1121 if (rtl_ocp_reg_failure(reg))
c558386b
HW		 1122 return 0;
1123
1ef7286e 1124 RTL_W32(tp, OCPDR, reg << 15);
c558386b 1125
1ef7286e 1126 return RTL_R32(tp, OCPDR);
c558386b
HW		 1127}
1128
91c86435
HK		 1129static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1130{
1131 unsigned long flags;
1132 u16 val;
1133
d6c36cbc 1134 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
91c86435 1135 val = __r8168_mac_ocp_read(tp, reg);
d6c36cbc 1136 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
91c86435
HK		 1137
1138 return val;
1139}
1140
ef712ede
HK		 1141static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
1142 u16 set)
1143{
91c86435
HK		 1144 unsigned long flags;
1145 u16 data;
ef712ede 1146
d6c36cbc 1147 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
91c86435
HK		 1148 data = __r8168_mac_ocp_read(tp, reg);
1149 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
d6c36cbc 1150 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
ef712ede
HK		 1151}
1152
acb58657
HK		 1153/* Work around a hw issue with RTL8168g PHY, the quirk disables
1154 * PHY MCU interrupts before PHY power-down.
1155 */
1156static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value)
1157{
1158 switch (tp->mac_version) {
1159 case RTL_GIGA_MAC_VER_40:
acb58657
HK		 1160 if (value & BMCR_RESET || !(value & BMCR_PDOWN))
1161 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
1162 else
1163 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
1164 break;
1165 default:
1166 break;
1167 }
1168};
1169
c558386b
HW		 1170static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1171{
1172 if (reg == 0x1f) {
1173 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1174 return;
1175 }
1176
1177 if (tp->ocp_base != OCP_STD_PHY_BASE)
1178 reg -= 0x10;
1179
acb58657
HK		 1180 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR)
1181 rtl8168g_phy_suspend_quirk(tp, value);
1182
c558386b
HW		 1183 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1184}
1185
1186static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1187{
9c6850fe
HK		 1188 if (reg == 0x1f)
1189 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
1190
c558386b
HW		 1191 if (tp->ocp_base != OCP_STD_PHY_BASE)
1192 reg -= 0x10;
1193
1194 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1195}
1196
eee3786f 1197static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1198{
1199 if (reg == 0x1f) {
1200 tp->ocp_base = value << 4;
1201 return;
1202 }
1203
1204 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1205}
1206
1207static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1208{
1209 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1210}
1211
ffc46952
FR		 1212DECLARE_RTL_COND(rtl_phyar_cond)
1213{
1ef7286e 1214 return RTL_R32(tp, PHYAR) & 0x80000000;
ffc46952
FR		 1215}
1216
24192210 1217static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 1218{
1ef7286e 1219 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 1220
d6836ef0 1221 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 1222 /*
81a95f04
TT		 1223 * According to hardware specs a 20us delay is required after write
1224 * complete indication, but before sending next command.
024a07ba 1225 */
81a95f04 1226 udelay(20);
1da177e4
LT		 1227}
1228
24192210 1229static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 1230{
ffc46952 1231 int value;
1da177e4 1232
1ef7286e 1233 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1234
d6836ef0 1235 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
9b994b4a 1236 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
ffc46952 1237
81a95f04
TT		 1238 /*
1239 * According to hardware specs a 20us delay is required after read
1240 * complete indication, but before sending next command.
1241 */
1242 udelay(20);
1243
1da177e4
LT		 1244 return value;
1245}
1246
935e2218
CHL		 1247DECLARE_RTL_COND(rtl_ocpar_cond)
1248{
1ef7286e 1249 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
935e2218
CHL		 1250}
1251
e6de30d6 1252#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1253
1ef7286e 1254static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
e6de30d6 1255{
1ef7286e 1256 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 1257}
1258
1ef7286e 1259static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
e6de30d6 1260{
1ef7286e 1261 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 1262}
1263
24192210 1264static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1265{
1ef7286e 1266 r8168dp_2_mdio_start(tp);
e6de30d6 1267
24192210 1268 r8169_mdio_write(tp, reg, value);
e6de30d6 1269
1ef7286e 1270 r8168dp_2_mdio_stop(tp);
e6de30d6 1271}
1272
24192210 1273static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1274{
1275 int value;
1276
62bdc8fd
HK		 1277 /* Work around issue with chip reporting wrong PHY ID */
1278 if (reg == MII_PHYSID2)
1279 return 0xc912;
1280
1ef7286e 1281 r8168dp_2_mdio_start(tp);
e6de30d6 1282
24192210 1283 value = r8169_mdio_read(tp, reg);
e6de30d6 1284
1ef7286e 1285 r8168dp_2_mdio_stop(tp);
e6de30d6 1286
1287 return value;
1288}
1289
ce8843ab 1290static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
dacf8154 1291{
5f950523 1292 switch (tp->mac_version) {
5f950523
HK		 1293 case RTL_GIGA_MAC_VER_28:
1294 case RTL_GIGA_MAC_VER_31:
1295 r8168dp_2_mdio_write(tp, location, val);
1296 break;
fe733618 1297 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST:
5f950523
HK		 1298 r8168g_mdio_write(tp, location, val);
1299 break;
1300 default:
1301 r8169_mdio_write(tp, location, val);
1302 break;
1303 }
dacf8154
FR		 1304}
1305
4da19633 1306static int rtl_readphy(struct rtl8169_private *tp, int location)
1307{
5f950523 1308 switch (tp->mac_version) {
5f950523
HK		 1309 case RTL_GIGA_MAC_VER_28:
1310 case RTL_GIGA_MAC_VER_31:
1311 return r8168dp_2_mdio_read(tp, location);
fe733618 1312 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST:
5f950523
HK		 1313 return r8168g_mdio_read(tp, location);
1314 default:
1315 return r8169_mdio_read(tp, location);
1316 }
4da19633 1317}
1318
ffc46952
FR		 1319DECLARE_RTL_COND(rtl_ephyar_cond)
1320{
1ef7286e 1321 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
ffc46952
FR		 1322}
1323
fdf6fc06 1324static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1325{
1ef7286e 1326 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
dacf8154
FR		 1327 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1328
d6836ef0 1329 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
ffc46952
FR		 1330
1331 udelay(10);
dacf8154
FR		 1332}
1333
fdf6fc06 1334static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1335{
1ef7286e 1336 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
dacf8154 1337
d6836ef0 1338 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1ef7286e 1339 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1340}
1341
a15aaa03 1342static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
935e2218 1343{
a15aaa03 1344 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
d6836ef0 1345 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1ef7286e 1346 RTL_R32(tp, OCPDR) : ~0;
935e2218
CHL		 1347}
1348
787c0c04 1349static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
935e2218 1350{
724c6fd0 1351 return _rtl_eri_read(tp, reg, ERIAR_OOB);
935e2218
CHL		 1352}
1353
935e2218
CHL		 1354static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1355 u32 data)
1356{
1ef7286e
AS		 1357 RTL_W32(tp, OCPDR, data);
1358 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
d6836ef0 1359 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
935e2218
CHL		 1360}
1361
1362static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1363 u32 data)
1364{
724c6fd0
HK		 1365 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1366 data, ERIAR_OOB);
935e2218
CHL		 1367}
1368
3c72bf71 1369static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
2a9b4d96 1370{
724c6fd0 1371 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
2a9b4d96 1372
3c72bf71 1373 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
2a9b4d96
CHL		 1374}
1375
1376#define OOB_CMD_RESET 0x00
1377#define OOB_CMD_DRIVER_START 0x05
1378#define OOB_CMD_DRIVER_STOP 0x06
1379
1380static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1381{
1382 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1383}
1384
3c72bf71 1385DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
2a9b4d96
CHL		 1386{
1387 u16 reg;
1388
1389 reg = rtl8168_get_ocp_reg(tp);
1390
a15aaa03 1391 return r8168dp_ocp_read(tp, reg) & 0x00000800;
2a9b4d96
CHL		 1392}
1393
935e2218 1394DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
2a9b4d96 1395{
787c0c04 1396 return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
935e2218
CHL		 1397}
1398
1399DECLARE_RTL_COND(rtl_ocp_tx_cond)
1400{
1ef7286e 1401 return RTL_R8(tp, IBISR0) & 0x20;
935e2218 1402}
2a9b4d96 1403
003609da
CHL		 1404static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1405{
1ef7286e 1406 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
d6836ef0 1407 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
1ef7286e
AS		 1408 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1409 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
003609da
CHL		 1410}
1411
935e2218
CHL		 1412static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1413{
3c72bf71 1414 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
d64113c6
HK		 1415 if (tp->dash_enabled)
1416 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
2a9b4d96
CHL		 1417}
1418
935e2218 1419static void rtl8168ep_driver_start(struct rtl8169_private *tp)
2a9b4d96 1420{
3c72bf71 1421 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
787c0c04 1422 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
d64113c6
HK		 1423 if (tp->dash_enabled)
1424 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30);
935e2218
CHL		 1425}
1426
b11bff90
CL		 1427static void rtl8125bp_driver_start(struct rtl8169_private *tp)
1428{
1429 r8168ep_ocp_write(tp, 0x01, 0x14, OOB_CMD_DRIVER_START);
1430 r8168ep_ocp_write(tp, 0x01, 0x18, 0x00);
1431 r8168ep_ocp_write(tp, 0x01, 0x10, 0x01);
1432}
1433
935e2218
CHL		 1434static void rtl8168_driver_start(struct rtl8169_private *tp)
1435{
e0d38b58 1436 if (tp->dash_type == RTL_DASH_DP)
935e2218 1437 rtl8168dp_driver_start(tp);
b11bff90
CL		 1438 else if (tp->dash_type == RTL_DASH_25_BP)
1439 rtl8125bp_driver_start(tp);
e0d38b58 1440 else
935e2218 1441 rtl8168ep_driver_start(tp);
935e2218 1442}
2a9b4d96 1443
935e2218
CHL		 1444static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1445{
3c72bf71 1446 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
d64113c6
HK		 1447 if (tp->dash_enabled)
1448 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
2a9b4d96
CHL		 1449}
1450
935e2218
CHL		 1451static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1452{
003609da 1453 rtl8168ep_stop_cmac(tp);
3c72bf71 1454 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
787c0c04 1455 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
d64113c6
HK		 1456 if (tp->dash_enabled)
1457 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
935e2218
CHL		 1458}
1459
b11bff90
CL		 1460static void rtl8125bp_driver_stop(struct rtl8169_private *tp)
1461{
1462 r8168ep_ocp_write(tp, 0x01, 0x14, OOB_CMD_DRIVER_STOP);
1463 r8168ep_ocp_write(tp, 0x01, 0x18, 0x00);
1464 r8168ep_ocp_write(tp, 0x01, 0x10, 0x01);
1465}
1466
935e2218
CHL		 1467static void rtl8168_driver_stop(struct rtl8169_private *tp)
1468{
e0d38b58 1469 if (tp->dash_type == RTL_DASH_DP)
935e2218 1470 rtl8168dp_driver_stop(tp);
b11bff90
CL		 1471 else if (tp->dash_type == RTL_DASH_25_BP)
1472 rtl8125bp_driver_stop(tp);
e0d38b58 1473 else
935e2218 1474 rtl8168ep_driver_stop(tp);
935e2218
CHL		 1475}
1476
9dbe7896 1477static bool r8168dp_check_dash(struct rtl8169_private *tp)
2a9b4d96
CHL		 1478{
1479 u16 reg = rtl8168_get_ocp_reg(tp);
1480
e0d38b58 1481 return r8168dp_ocp_read(tp, reg) & BIT(15);
2a9b4d96
CHL		 1482}
1483
9dbe7896 1484static bool r8168ep_check_dash(struct rtl8169_private *tp)
935e2218 1485{
e0d38b58 1486 return r8168ep_ocp_read(tp, 0x128) & BIT(0);
935e2218
CHL		 1487}
1488
0ab0c45d
CL		 1489static bool rtl_dash_is_enabled(struct rtl8169_private *tp)
1490{
1491 switch (tp->dash_type) {
1492 case RTL_DASH_DP:
1493 return r8168dp_check_dash(tp);
1494 case RTL_DASH_EP:
b11bff90 1495 case RTL_DASH_25_BP:
0ab0c45d
CL		 1496 return r8168ep_check_dash(tp);
1497 default:
1498 return false;
1499 }
1500}
1501
1502static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp)
935e2218
CHL		 1503{
1504 switch (tp->mac_version) {
935e2218
CHL		 1505 case RTL_GIGA_MAC_VER_28:
1506 case RTL_GIGA_MAC_VER_31:
0ab0c45d 1507 return RTL_DASH_DP;
4f51e7d3 1508 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_52:
0ab0c45d 1509 return RTL_DASH_EP;
b11bff90
CL		 1510 case RTL_GIGA_MAC_VER_66:
1511 return RTL_DASH_25_BP;
935e2218 1512 default:
e0d38b58 1513 return RTL_DASH_NONE;
935e2218
CHL		 1514 }
1515}
1516
128735a1
HK		 1517static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable)
1518{
330dc229
HK		 1519 if (tp->mac_version >= RTL_GIGA_MAC_VER_25 &&
1520 tp->mac_version != RTL_GIGA_MAC_VER_28 &&
1521 tp->mac_version != RTL_GIGA_MAC_VER_31 &&
1522 tp->mac_version != RTL_GIGA_MAC_VER_38)
1523 r8169_mod_reg8_cond(tp, PMCH, D3_NO_PLL_DOWN, !enable);
128735a1
HK		 1524}
1525
4e7e4621
HK		 1526static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1527{
54113ded
HK		 1528 rtl_eri_clear_bits(tp, 0xdc, BIT(0));
1529 rtl_eri_set_bits(tp, 0xdc, BIT(0));
4e7e4621
HK		 1530}
1531
ffc46952
FR		 1532DECLARE_RTL_COND(rtl_efusear_cond)
1533{
1ef7286e 1534 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
ffc46952
FR		 1535}
1536
2992bdfa 1537u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1538{
1ef7286e 1539 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
daf9df6d 1540
d6836ef0 1541 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1ef7286e 1542 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1543}
1544
c1d532d2
HK		 1545static u32 rtl_get_events(struct rtl8169_private *tp)
1546{
f1bce4ad
HK		 1547 if (rtl_is_8125(tp))
1548 return RTL_R32(tp, IntrStatus_8125);
1549 else
1550 return RTL_R16(tp, IntrStatus);
c1d532d2
HK		 1551}
1552
1553static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
9085cdfa 1554{
f1bce4ad
HK		 1555 if (rtl_is_8125(tp))
1556 RTL_W32(tp, IntrStatus_8125, bits);
1557 else
1558 RTL_W16(tp, IntrStatus, bits);
9085cdfa
FR		 1559}
1560
1561static void rtl_irq_disable(struct rtl8169_private *tp)
1562{
f1bce4ad
HK		 1563 if (rtl_is_8125(tp))
1564 RTL_W32(tp, IntrMask_8125, 0);
1565 else
1566 RTL_W16(tp, IntrMask, 0);
3e990ff5
FR		 1567}
1568
fe716f8a 1569static void rtl_irq_enable(struct rtl8169_private *tp)
da78dbff 1570{
f1bce4ad
HK		 1571 if (rtl_is_8125(tp))
1572 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1573 else
1574 RTL_W16(tp, IntrMask, tp->irq_mask);
da78dbff
FR		 1575}
1576
811fd301 1577static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1578{
9085cdfa 1579 rtl_irq_disable(tp);
c1d532d2 1580 rtl_ack_events(tp, 0xffffffff);
711463f8 1581 rtl_pci_commit(tp);
1da177e4
LT		 1582}
1583
70090424
HW		 1584static void rtl_link_chg_patch(struct rtl8169_private *tp)
1585{
703732f0 1586 struct phy_device *phydev = tp->phydev;
70090424 1587
b3d7b2f2
HW		 1588 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1589 tp->mac_version == RTL_GIGA_MAC_VER_38) {
29a12b49 1590 if (phydev->speed == SPEED_1000) {
724c6fd0
HK		 1591 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1592 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
29a12b49 1593 } else if (phydev->speed == SPEED_100) {
724c6fd0
HK		 1594 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1595 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
70090424 1596 } else {
724c6fd0
HK		 1597 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1598 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
70090424 1599 }
4e7e4621 1600 rtl_reset_packet_filter(tp);
c2218925
HW		 1601 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1602 tp->mac_version == RTL_GIGA_MAC_VER_36) {
29a12b49 1603 if (phydev->speed == SPEED_1000) {
724c6fd0
HK		 1604 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1605 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
c2218925 1606 } else {
724c6fd0
HK		 1607 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1608 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
c2218925 1609 }
7e18dca1 1610 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
29a12b49 1611 if (phydev->speed == SPEED_10) {
724c6fd0
HK		 1612 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1613 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
7e18dca1 1614 } else {
724c6fd0 1615 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
7e18dca1 1616 }
70090424
HW		 1617 }
1618}
1619
e1759441
RW		 1620#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1621
e1759441 1622static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1623{
1624 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1625
e1759441 1626 wol->supported = WAKE_ANY;
433f9d0d 1627 wol->wolopts = tp->saved_wolopts;
e1759441
RW		 1628}
1629
1630static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1631{
df320ed7 1632 rtl_unlock_config_regs(tp);
61a4dcc2 1633
9e9f33ba 1634 if (rtl_is_8168evl_up(tp)) {
6e1d0b89 1635 if (wolopts & WAKE_MAGIC)
54113ded 1636 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
6e1d0b89 1637 else
54113ded 1638 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
f1bce4ad 1639 } else if (rtl_is_8125(tp)) {
f1bce4ad
HK		 1640 if (wolopts & WAKE_MAGIC)
1641 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1642 else
1643 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
c507e96b
HK		 1644 } else {
1645 r8169_mod_reg8_cond(tp, Config3, MagicPacket,
1646 wolopts & WAKE_MAGIC);
6e1d0b89
CHL		 1647 }
1648
c507e96b 1649 r8169_mod_reg8_cond(tp, Config3, LinkUp, wolopts & WAKE_PHY);
e3e9e903
HK		 1650 if (rtl_is_8125(tp))
1651 r8168_mac_ocp_modify(tp, 0xe0c6, 0x3f,
1652 wolopts & WAKE_PHY ? 0x13 : 0);
c507e96b
HK		 1653 r8169_mod_reg8_cond(tp, Config5, UWF, wolopts & WAKE_UCAST);
1654 r8169_mod_reg8_cond(tp, Config5, BWF, wolopts & WAKE_BCAST);
1655 r8169_mod_reg8_cond(tp, Config5, MWF, wolopts & WAKE_MCAST);
1656 r8169_mod_reg8_cond(tp, Config5, LanWake, wolopts);
61a4dcc2 1657
851e6022 1658 switch (tp->mac_version) {
edcde3ee 1659 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
c507e96b 1660 r8169_mod_reg8_cond(tp, Config1, PMEnable, wolopts);
851e6022 1661 break;
edcde3ee
HK		 1662 case RTL_GIGA_MAC_VER_34:
1663 case RTL_GIGA_MAC_VER_37:
fe733618 1664 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_LAST:
c507e96b 1665 r8169_mod_reg8_cond(tp, Config2, PME_SIGNAL, wolopts);
851e6022 1666 break;
edcde3ee
HK		 1667 default:
1668 break;
851e6022
FR		 1669 }
1670
df320ed7 1671 rtl_lock_config_regs(tp);
3bd82645
HK		 1672
1673 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
54744510 1674
0ab0c45d 1675 if (!tp->dash_enabled) {
54744510 1676 rtl_set_d3_pll_down(tp, !wolopts);
3ebbd9f6 1677 tp->dev->ethtool->wol_enabled = wolopts ? 1 : 0;
54744510 1678 }
e1759441
RW		 1679}
1680
1681static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1682{
1683 struct rtl8169_private *tp = netdev_priv(dev);
5fa80a32 1684
2f533f6b
HK		 1685 if (wol->wolopts & ~WAKE_ANY)
1686 return -EINVAL;
1687
2f533f6b 1688 tp->saved_wolopts = wol->wolopts;
ec2f204b 1689 __rtl8169_set_wol(tp, tp->saved_wolopts);
da78dbff 1690
61a4dcc2
FR		 1691 return 0;
1692}
1693
1da177e4
LT		 1694static void rtl8169_get_drvinfo(struct net_device *dev,
1695 struct ethtool_drvinfo *info)
1696{
1697 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1698 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1699
f029c781
WS		 1700 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1701 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1702 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
254764e5 1703 if (rtl_fw)
f029c781 1704 strscpy(info->fw_version, rtl_fw->version,
8ac72d16 1705 sizeof(info->fw_version));
1da177e4
LT		 1706}
1707
1708static int rtl8169_get_regs_len(struct net_device *dev)
1709{
1710 return R8169_REGS_SIZE;
1711}
1712
c8f44aff
MM		 1713static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1714 netdev_features_t features)
1da177e4 1715{
d58d46b5
FR		 1716 struct rtl8169_private *tp = netdev_priv(dev);
1717
2b7b4318 1718 if (dev->mtu > TD_MSS_MAX)
350fb32a 1719 features &= ~NETIF_F_ALL_TSO;
1da177e4 1720
a8ec173a 1721 if (dev->mtu > ETH_DATA_LEN &&
6ed0e08f 1722 tp->mac_version > RTL_GIGA_MAC_VER_06)
7cb83b21 1723 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
d58d46b5 1724
350fb32a 1725 return features;
1da177e4
LT		 1726}
1727
10478283
HK		 1728static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1729 netdev_features_t features)
1da177e4 1730{
10478283 1731 u32 rx_config = RTL_R32(tp, RxConfig);
a3984578 1732
929a031d 1733 if (features & NETIF_F_RXALL)
10478283 1734 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
929a031d 1735 else
10478283 1736 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
1da177e4 1737
f1bce4ad
HK		 1738 if (rtl_is_8125(tp)) {
1739 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1740 rx_config |= RX_VLAN_8125;
1741 else
1742 rx_config &= ~RX_VLAN_8125;
1743 }
1744
1ef7286e 1745 RTL_W32(tp, RxConfig, rx_config);
10478283
HK		 1746}
1747
1748static int rtl8169_set_features(struct net_device *dev,
1749 netdev_features_t features)
1750{
1751 struct rtl8169_private *tp = netdev_priv(dev);
1752
10478283 1753 rtl_set_rx_config_features(tp, features);
350fb32a 1754
929a031d 1755 if (features & NETIF_F_RXCSUM)
1756 tp->cp_cmd |= RxChkSum;
1757 else
1758 tp->cp_cmd &= ~RxChkSum;
6bbe021d 1759
f1bce4ad
HK		 1760 if (!rtl_is_8125(tp)) {
1761 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1762 tp->cp_cmd |= RxVlan;
1763 else
1764 tp->cp_cmd &= ~RxVlan;
1765 }
929a031d 1766
1ef7286e 1767 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
711463f8 1768 rtl_pci_commit(tp);
1da177e4 1769
1da177e4
LT		 1770 return 0;
1771}
1772
810f4893 1773static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 1774{
df8a39de 1775 return (skb_vlan_tag_present(skb)) ?
7424edbb 1776 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1da177e4
LT		 1777}
1778
7a8fc77b 1779static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1780{
1781 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1782
7a8fc77b 1783 if (opts2 & RxVlanTag)
7424edbb 1784 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1da177e4
LT		 1785}
1786
1da177e4
LT		 1787static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1788 void *p)
1789{
5b0384f4 1790 struct rtl8169_private *tp = netdev_priv(dev);
15edae91
PW		 1791 u32 __iomem *data = tp->mmio_addr;
1792 u32 *dw = p;
1793 int i;
1da177e4 1794
15edae91
PW		 1795 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1796 memcpy_fromio(dw++, data++, 4);
1da177e4
LT		 1797}
1798
d4a3a0fc
SH		 1799static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1800 "tx_packets",
1801 "rx_packets",
1802 "tx_errors",
1803 "rx_errors",
1804 "rx_missed",
1805 "align_errors",
1806 "tx_single_collisions",
1807 "tx_multi_collisions",
1808 "unicast",
1809 "broadcast",
1810 "multicast",
1811 "tx_aborted",
1812 "tx_underrun",
1813};
1814
b9f2c044 1815static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1816{
b9f2c044
JG		 1817 switch (sset) {
1818 case ETH_SS_STATS:
1819 return ARRAY_SIZE(rtl8169_gstrings);
1820 default:
1821 return -EOPNOTSUPP;
1822 }
d4a3a0fc
SH		 1823}
1824
42020320 1825DECLARE_RTL_COND(rtl_counters_cond)
6e85d5ad 1826{
1ef7286e 1827 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
6e85d5ad
CV		 1828}
1829
d56f58ce 1830static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
6e85d5ad 1831{
b498ee3f 1832 u32 cmd = lower_32_bits(tp->counters_phys_addr);
6e85d5ad 1833
b498ee3f 1834 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr));
711463f8 1835 rtl_pci_commit(tp);
1ef7286e
AS		 1836 RTL_W32(tp, CounterAddrLow, cmd);
1837 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
6e85d5ad 1838
d6836ef0 1839 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
6e85d5ad
CV		 1840}
1841
d56f58ce 1842static void rtl8169_update_counters(struct rtl8169_private *tp)
d4a3a0fc 1843{
10262b0b
HK		 1844 u8 val = RTL_R8(tp, ChipCmd);
1845
355423d0
IV		 1846 /*
1847 * Some chips are unable to dump tally counters when the receiver
10262b0b 1848 * is disabled. If 0xff chip may be in a PCI power-save state.
355423d0 1849 */
d56f58ce
HK		 1850 if (val & CmdRxEnb && val != 0xff)
1851 rtl8169_do_counters(tp, CounterDump);
6e85d5ad
CV		 1852}
1853
d56f58ce 1854static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
6e85d5ad 1855{
42020320 1856 struct rtl8169_counters *counters = tp->counters;
6e85d5ad
CV		 1857
1858 /*
1859 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1860 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1861 * reset by a power cycle, while the counter values collected by the
1862 * driver are reset at every driver unload/load cycle.
1863 *
1864 * To make sure the HW values returned by @get_stats64 match the SW
1865 * values, we collect the initial values at first open(*) and use them
1866 * as offsets to normalize the values returned by @get_stats64.
1867 *
1868 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1869 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1870 * set at open time by rtl_hw_start.
1871 */
1872
1873 if (tp->tc_offset.inited)
d56f58ce 1874 return;
6e85d5ad 1875
6b4f5031
HK		 1876 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) {
1877 rtl8169_do_counters(tp, CounterReset);
1878 } else {
1879 rtl8169_update_counters(tp);
1880 tp->tc_offset.tx_errors = counters->tx_errors;
1881 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1882 tp->tc_offset.tx_aborted = counters->tx_aborted;
1883 tp->tc_offset.rx_missed = counters->rx_missed;
1884 }
6e85d5ad 1885
6e85d5ad 1886 tp->tc_offset.inited = true;
d4a3a0fc
SH		 1887}
1888
355423d0
IV		 1889static void rtl8169_get_ethtool_stats(struct net_device *dev,
1890 struct ethtool_stats *stats, u64 *data)
1891{
1892 struct rtl8169_private *tp = netdev_priv(dev);
ec2f204b 1893 struct rtl8169_counters *counters;
e0636236 1894
ec2f204b
HK		 1895 counters = tp->counters;
1896 rtl8169_update_counters(tp);
355423d0 1897
42020320
CV		 1898 data[0] = le64_to_cpu(counters->tx_packets);
1899 data[1] = le64_to_cpu(counters->rx_packets);
1900 data[2] = le64_to_cpu(counters->tx_errors);
1901 data[3] = le32_to_cpu(counters->rx_errors);
1902 data[4] = le16_to_cpu(counters->rx_missed);
1903 data[5] = le16_to_cpu(counters->align_errors);
1904 data[6] = le32_to_cpu(counters->tx_one_collision);
1905 data[7] = le32_to_cpu(counters->tx_multi_collision);
1906 data[8] = le64_to_cpu(counters->rx_unicast);
1907 data[9] = le64_to_cpu(counters->rx_broadcast);
1908 data[10] = le32_to_cpu(counters->rx_multicast);
1909 data[11] = le16_to_cpu(counters->tx_aborted);
8df94393 1910 data[12] = le16_to_cpu(counters->tx_underrun);
355423d0
IV		 1911}
1912
d4a3a0fc
SH		 1913static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1914{
1915 switch(stringset) {
1916 case ETH_SS_STATS:
da5ac772 1917 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings));
d4a3a0fc
SH		 1918 break;
1919 }
1920}
1921
50970831
FR		 1922/*
1923 * Interrupt coalescing
1924 *
1925 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1926 * > 8169, 8168 and 810x line of chipsets
1927 *
1928 * 8169, 8168, and 8136(810x) serial chipsets support it.
1929 *
1930 * > 2 - the Tx timer unit at gigabit speed
1931 *
1932 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1933 * (0xe0) bit 1 and bit 0.
1934 *
1935 * For 8169
1936 * bit[1:0] \ speed 1000M 100M 10M
1937 * 0 0 320ns 2.56us 40.96us
1938 * 0 1 2.56us 20.48us 327.7us
1939 * 1 0 5.12us 40.96us 655.4us
1940 * 1 1 10.24us 81.92us 1.31ms
1941 *
1942 * For the other
1943 * bit[1:0] \ speed 1000M 100M 10M
1944 * 0 0 5us 2.56us 40.96us
1945 * 0 1 40us 20.48us 327.7us
1946 * 1 0 80us 40.96us 655.4us
1947 * 1 1 160us 81.92us 1.31ms
1948 */
1949
50970831
FR		 1950/* rx/tx scale factors for all CPlusCmd[0:1] cases */
1951struct rtl_coalesce_info {
1952 u32 speed;
2815b305 1953 u32 scale_nsecs[4];
50970831
FR		 1954};
1955
2815b305
HK		 1956/* produce array with base delay *1, *8, *8*2, *8*2*2 */
1957#define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1958
50970831 1959static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
2815b305 1960 { SPEED_1000, COALESCE_DELAY(320) },
51f6291b
HK		 1961 { SPEED_100, COALESCE_DELAY(2560) },
1962 { SPEED_10, COALESCE_DELAY(40960) },
50970831
FR		 1963 { 0 },
1964};
1965
1966static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
2815b305 1967 { SPEED_1000, COALESCE_DELAY(5000) },
51f6291b
HK		 1968 { SPEED_100, COALESCE_DELAY(2560) },
1969 { SPEED_10, COALESCE_DELAY(40960) },
50970831
FR		 1970 { 0 },
1971};
2815b305 1972#undef COALESCE_DELAY
50970831
FR		 1973
1974/* get rx/tx scale vector corresponding to current speed */
ef2c0a78
HK		 1975static const struct rtl_coalesce_info *
1976rtl_coalesce_info(struct rtl8169_private *tp)
50970831 1977{
50970831 1978 const struct rtl_coalesce_info *ci;
50970831 1979
20023d3e
HK		 1980 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1981 ci = rtl_coalesce_info_8169;
1982 else
1983 ci = rtl_coalesce_info_8168_8136;
50970831 1984
51f6291b
HK		 1985 /* if speed is unknown assume highest one */
1986 if (tp->phydev->speed == SPEED_UNKNOWN)
1987 return ci;
1988
20023d3e
HK		 1989 for (; ci->speed; ci++) {
1990 if (tp->phydev->speed == ci->speed)
50970831 1991 return ci;
50970831
FR		 1992 }
1993
1994 return ERR_PTR(-ELNRNG);
1995}
1996
f3ccfda1
YM		 1997static int rtl_get_coalesce(struct net_device *dev,
1998 struct ethtool_coalesce *ec,
1999 struct kernel_ethtool_coalesce *kernel_coal,
2000 struct netlink_ext_ack *extack)
50970831
FR		 2001{
2002 struct rtl8169_private *tp = netdev_priv(dev);
50970831 2003 const struct rtl_coalesce_info *ci;
6cf96dd4
HK		 2004 u32 scale, c_us, c_fr;
2005 u16 intrmit;
50970831 2006
f1bce4ad
HK		 2007 if (rtl_is_8125(tp))
2008 return -EOPNOTSUPP;
2009
50970831
FR		 2010 memset(ec, 0, sizeof(*ec));
2011
2012 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
ef2c0a78 2013 ci = rtl_coalesce_info(tp);
50970831
FR		 2014 if (IS_ERR(ci))
2015 return PTR_ERR(ci);
2016
2815b305 2017 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
50970831 2018
6cf96dd4 2019 intrmit = RTL_R16(tp, IntrMitigate);
50970831 2020
6cf96dd4
HK		 2021 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
2022 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
50970831 2023
6cf96dd4
HK		 2024 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
2025 /* ethtool_coalesce states usecs and max_frames must not both be 0 */
2026 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
2027
2028 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
2029 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
2030
2031 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
2032 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
50970831
FR		 2033
2034 return 0;
2035}
2036
cb9d97de
HK		 2037/* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
2038static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
2815b305 2039 u16 *cp01)
50970831
FR		 2040{
2041 const struct rtl_coalesce_info *ci;
2042 u16 i;
2043
ef2c0a78 2044 ci = rtl_coalesce_info(tp);
50970831 2045 if (IS_ERR(ci))
2815b305 2046 return PTR_ERR(ci);
50970831
FR		 2047
2048 for (i = 0; i < 4; i++) {
cb9d97de 2049 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
50970831 2050 *cp01 = i;
2815b305 2051 return ci->scale_nsecs[i];
50970831
FR		 2052 }
2053 }
2054
cb9d97de 2055 return -ERANGE;
50970831
FR		 2056}
2057
f3ccfda1
YM		 2058static int rtl_set_coalesce(struct net_device *dev,
2059 struct ethtool_coalesce *ec,
2060 struct kernel_ethtool_coalesce *kernel_coal,
2061 struct netlink_ext_ack *extack)
50970831
FR		 2062{
2063 struct rtl8169_private *tp = netdev_priv(dev);
2b3e48b6
HK		 2064 u32 tx_fr = ec->tx_max_coalesced_frames;
2065 u32 rx_fr = ec->rx_max_coalesced_frames;
2066 u32 coal_usec_max, units;
2815b305 2067 u16 w = 0, cp01 = 0;
2b3e48b6 2068 int scale;
50970831 2069
f1bce4ad
HK		 2070 if (rtl_is_8125(tp))
2071 return -EOPNOTSUPP;
2072
2b3e48b6
HK		 2073 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
2074 return -ERANGE;
2075
cb9d97de
HK		 2076 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
2077 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
2815b305
HK		 2078 if (scale < 0)
2079 return scale;
50970831 2080
2b3e48b6
HK		 2081 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
2082 * not only when usecs=0 because of e.g. the following scenario:
2083 *
2084 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2085 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2086 * - then user does `ethtool -C eth0 rx-usecs 100`
2087 *
2088 * Since ethtool sends to kernel whole ethtool_coalesce settings,
2089 * if we want to ignore rx_frames then it has to be set to 0.
2090 */
2091 if (rx_fr == 1)
2092 rx_fr = 0;
2093 if (tx_fr == 1)
2094 tx_fr = 0;
50970831 2095
81496b72
HK		 2096 /* HW requires time limit to be set if frame limit is set */
2097 if ((tx_fr && !ec->tx_coalesce_usecs) ||
2098 (rx_fr && !ec->rx_coalesce_usecs))
2099 return -EINVAL;
2100
2b3e48b6
HK		 2101 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
2102 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
50970831 2103
2b3e48b6
HK		 2104 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
2105 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
2106 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
2107 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
50970831 2108
2b3e48b6 2109 RTL_W16(tp, IntrMitigate, w);
50970831 2110
5cdfe830
HK		 2111 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
2112 if (rtl_is_8168evl_up(tp)) {
2113 if (!rx_fr && !tx_fr)
2114 /* disable packet counter */
2115 tp->cp_cmd |= PktCntrDisable;
2116 else
2117 tp->cp_cmd &= ~PktCntrDisable;
2118 }
2119
9a3c81fa 2120 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1ef7286e 2121 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
711463f8 2122 rtl_pci_commit(tp);
50970831 2123
50970831
FR		 2124 return 0;
2125}
2126
2ce30993
HK		 2127static void rtl_set_eee_txidle_timer(struct rtl8169_private *tp)
2128{
2129 unsigned int timer_val = READ_ONCE(tp->dev->mtu) + ETH_HLEN + 0x20;
2130
2131 switch (tp->mac_version) {
57d2d2c8
HK		 2132 case RTL_GIGA_MAC_VER_46:
2133 case RTL_GIGA_MAC_VER_48:
2134 tp->tx_lpi_timer = timer_val;
2135 r8168_mac_ocp_write(tp, 0xe048, timer_val);
2136 break;
fe733618 2137 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST:
2ce30993
HK		 2138 tp->tx_lpi_timer = timer_val;
2139 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val);
2140 break;
2141 default:
2142 break;
2143 }
2144}
2145
9c501397
HK		 2146static unsigned int r8169_get_tx_lpi_timer_us(struct rtl8169_private *tp)
2147{
2148 unsigned int speed = tp->phydev->speed;
2149 unsigned int timer = tp->tx_lpi_timer;
2150
2151 if (!timer || speed == SPEED_UNKNOWN)
2152 return 0;
2153
2154 /* tx_lpi_timer value is in bytes */
2155 return DIV_ROUND_CLOSEST(timer * BITS_PER_BYTE, speed);
2156}
2157
d80a5233 2158static int rtl8169_get_eee(struct net_device *dev, struct ethtool_keee *data)
df6f1856
HK		 2159{
2160 struct rtl8169_private *tp = netdev_priv(dev);
9c501397 2161 int ret;
df6f1856 2162
2e779ddb
HK		 2163 if (!rtl_supports_eee(tp))
2164 return -EOPNOTSUPP;
2165
9c501397
HK		 2166 ret = phy_ethtool_get_eee(tp->phydev, data);
2167 if (ret)
2168 return ret;
2169
2170 data->tx_lpi_timer = r8169_get_tx_lpi_timer_us(tp);
9c501397
HK		 2171
2172 return 0;
df6f1856
HK		 2173}
2174
d80a5233 2175static int rtl8169_set_eee(struct net_device *dev, struct ethtool_keee *data)
df6f1856
HK		 2176{
2177 struct rtl8169_private *tp = netdev_priv(dev);
2e779ddb
HK		 2178
2179 if (!rtl_supports_eee(tp))
2180 return -EOPNOTSUPP;
df6f1856 2181
f5d59230 2182 return phy_ethtool_set_eee(tp->phydev, data);
df6f1856
HK		 2183}
2184
dc4aa50b 2185static void rtl8169_get_ringparam(struct net_device *dev,
74624944
HC		 2186 struct ethtool_ringparam *data,
2187 struct kernel_ethtool_ringparam *kernel_data,
2188 struct netlink_ext_ack *extack)
dc4aa50b
HK		 2189{
2190 data->rx_max_pending = NUM_RX_DESC;
2191 data->rx_pending = NUM_RX_DESC;
2192 data->tx_max_pending = NUM_TX_DESC;
2193 data->tx_pending = NUM_TX_DESC;
2194}
2195
e3fc5139
HK		 2196static void rtl8169_get_pause_stats(struct net_device *dev,
2197 struct ethtool_pause_stats *pause_stats)
2198{
2199 struct rtl8169_private *tp = netdev_priv(dev);
2200
2201 if (!rtl_is_8125(tp))
2202 return;
2203
2204 rtl8169_update_counters(tp);
2205 pause_stats->tx_pause_frames = le32_to_cpu(tp->counters->tx_pause_on);
2206 pause_stats->rx_pause_frames = le32_to_cpu(tp->counters->rx_pause_on);
2207}
2208
216f78ea
HK		 2209static void rtl8169_get_pauseparam(struct net_device *dev,
2210 struct ethtool_pauseparam *data)
2211{
2212 struct rtl8169_private *tp = netdev_priv(dev);
2213 bool tx_pause, rx_pause;
2214
2215 phy_get_pause(tp->phydev, &tx_pause, &rx_pause);
2216
2217 data->autoneg = tp->phydev->autoneg;
2218 data->tx_pause = tx_pause ? 1 : 0;
2219 data->rx_pause = rx_pause ? 1 : 0;
2220}
2221
2222static int rtl8169_set_pauseparam(struct net_device *dev,
2223 struct ethtool_pauseparam *data)
2224{
2225 struct rtl8169_private *tp = netdev_priv(dev);
2226
2227 if (dev->mtu > ETH_DATA_LEN)
2228 return -EOPNOTSUPP;
2229
2230 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause);
2231
2232 return 0;
2233}
2234
e3fc5139
HK		 2235static void rtl8169_get_eth_mac_stats(struct net_device *dev,
2236 struct ethtool_eth_mac_stats *mac_stats)
2237{
2238 struct rtl8169_private *tp = netdev_priv(dev);
2239
2240 rtl8169_update_counters(tp);
2241
2242 mac_stats->FramesTransmittedOK =
2243 le64_to_cpu(tp->counters->tx_packets);
2244 mac_stats->SingleCollisionFrames =
2245 le32_to_cpu(tp->counters->tx_one_collision);
2246 mac_stats->MultipleCollisionFrames =
2247 le32_to_cpu(tp->counters->tx_multi_collision);
2248 mac_stats->FramesReceivedOK =
2249 le64_to_cpu(tp->counters->rx_packets);
2250 mac_stats->AlignmentErrors =
2251 le16_to_cpu(tp->counters->align_errors);
2252 mac_stats->FramesLostDueToIntMACXmitError =
2253 le64_to_cpu(tp->counters->tx_errors);
2254 mac_stats->BroadcastFramesReceivedOK =
2255 le64_to_cpu(tp->counters->rx_broadcast);
2256 mac_stats->MulticastFramesReceivedOK =
2257 le32_to_cpu(tp->counters->rx_multicast);
2258
2259 if (!rtl_is_8125(tp))
2260 return;
2261
2262 mac_stats->AlignmentErrors =
2263 le32_to_cpu(tp->counters->align_errors32);
2264 mac_stats->OctetsTransmittedOK =
2265 le64_to_cpu(tp->counters->tx_octets);
2266 mac_stats->LateCollisions =
2267 le32_to_cpu(tp->counters->tx_late_collision);
2268 mac_stats->FramesAbortedDueToXSColls =
2269 le32_to_cpu(tp->counters->tx_aborted32);
2270 mac_stats->OctetsReceivedOK =
2271 le64_to_cpu(tp->counters->rx_octets);
2272 mac_stats->FramesLostDueToIntMACRcvError =
2273 le32_to_cpu(tp->counters->rx_mac_error);
2274 mac_stats->MulticastFramesXmittedOK =
2275 le64_to_cpu(tp->counters->tx_multicast64);
2276 mac_stats->BroadcastFramesXmittedOK =
2277 le64_to_cpu(tp->counters->tx_broadcast64);
2278 mac_stats->MulticastFramesReceivedOK =
2279 le64_to_cpu(tp->counters->rx_multicast64);
b8bd8c44 2280 mac_stats->FrameTooLongErrors =
e3fc5139
HK		 2281 le32_to_cpu(tp->counters->rx_frame_too_long);
2282}
2283
2284static void rtl8169_get_eth_ctrl_stats(struct net_device *dev,
2285 struct ethtool_eth_ctrl_stats *ctrl_stats)
2286{
2287 struct rtl8169_private *tp = netdev_priv(dev);
2288
2289 if (!rtl_is_8125(tp))
2290 return;
2291
2292 rtl8169_update_counters(tp);
2293
2294 ctrl_stats->UnsupportedOpcodesReceived =
2295 le32_to_cpu(tp->counters->rx_unknown_opcode);
2296}
2297
7282d491 2298static const struct ethtool_ops rtl8169_ethtool_ops = {
b604eb31
JK		 2299 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
2300 ETHTOOL_COALESCE_MAX_FRAMES,
1da177e4
LT		 2301 .get_drvinfo = rtl8169_get_drvinfo,
2302 .get_regs_len = rtl8169_get_regs_len,
2303 .get_link = ethtool_op_get_link,
50970831
FR		 2304 .get_coalesce = rtl_get_coalesce,
2305 .set_coalesce = rtl_set_coalesce,
1da177e4 2306 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2307 .get_wol = rtl8169_get_wol,
2308 .set_wol = rtl8169_set_wol,
d4a3a0fc 2309 .get_strings = rtl8169_get_strings,
b9f2c044 2310 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2311 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2312 .get_ts_info = ethtool_op_get_ts_info,
dd84957e 2313 .nway_reset = phy_ethtool_nway_reset,
df6f1856
HK		 2314 .get_eee = rtl8169_get_eee,
2315 .set_eee = rtl8169_set_eee,
45772433
HK		 2316 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2317 .set_link_ksettings = phy_ethtool_set_link_ksettings,
dc4aa50b 2318 .get_ringparam = rtl8169_get_ringparam,
e3fc5139 2319 .get_pause_stats = rtl8169_get_pause_stats,
216f78ea
HK		 2320 .get_pauseparam = rtl8169_get_pauseparam,
2321 .set_pauseparam = rtl8169_set_pauseparam,
e3fc5139
HK		 2322 .get_eth_mac_stats = rtl8169_get_eth_mac_stats,
2323 .get_eth_ctrl_stats = rtl8169_get_eth_ctrl_stats,
1da177e4
LT		 2324};
2325
2b065c09 2326static const struct rtl_chip_info *rtl8169_get_chip_version(u16 xid, bool gmii)
1da177e4 2327{
2b065c09
HK		 2328 /* Chips combining a 1Gbps MAC with a 100Mbps PHY */
2329 static const struct rtl_chip_info rtl8106eus_info = {
2330 .mac_version = RTL_GIGA_MAC_VER_43,
2331 .name = "RTL8106eus",
2332 .fw_name = FIRMWARE_8106E_2,
2333 };
2334 static const struct rtl_chip_info rtl8107e_info = {
2335 .mac_version = RTL_GIGA_MAC_VER_48,
2336 .name = "RTL8107e",
2337 .fw_name = FIRMWARE_8107E_2,
3744100e 2338 };
2b065c09 2339 const struct rtl_chip_info *p = rtl_chip_infos;
1da177e4 2340
f1f9ca28 2341 while ((xid & p->mask) != p->val)
1da177e4 2342 p++;
f1f9ca28 2343
2b065c09
HK		 2344 if (p->mac_version == RTL_GIGA_MAC_VER_42 && !gmii)
2345 return &rtl8106eus_info;
2346 if (p->mac_version == RTL_GIGA_MAC_VER_46 && !gmii)
2347 return &rtl8107e_info;
f1f9ca28 2348
2b065c09 2349 return p;
1da177e4
LT		 2350}
2351
f1e02ed1 2352static void rtl_release_firmware(struct rtl8169_private *tp)
2353{
254764e5 2354 if (tp->rtl_fw) {
47ad5931 2355 rtl_fw_release_firmware(tp->rtl_fw);
b6ffd97f 2356 kfree(tp->rtl_fw);
254764e5 2357 tp->rtl_fw = NULL;
b6ffd97f 2358 }
f1e02ed1 2359}
2360
2992bdfa 2361void r8169_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2362{
47dda786
HK		 2363 int val;
2364
ce8843ab 2365 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
89fbd26c 2366 if (tp->rtl_fw) {
ce8843ab 2367 rtl_fw_write_firmware(tp, tp->rtl_fw);
89fbd26c
HK		 2368 /* At least one firmware doesn't reset tp->ocp_base. */
2369 tp->ocp_base = OCP_STD_PHY_BASE;
47dda786
HK		 2370
2371 /* PHY soft reset may still be in progress */
2372 phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
2373 !(val & BMCR_RESET),
2374 50000, 600000, true);
89fbd26c 2375 }
953a12cc
FR		 2376}
2377
df6f1856
HK		 2378static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2379{
f452825d
HK		 2380 /* Adjust EEE LED frequency */
2381 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2382 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2383
54113ded 2384 rtl_eri_set_bits(tp, 0x1b0, 0x0003);
df6f1856
HK		 2385}
2386
4640338c 2387static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
b3a42e3a
HK		 2388{
2389 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2390 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2391}
2392
0439297b
HK		 2393static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
2394{
0439297b
HK		 2395 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2396}
2397
ae1e82c6 2398static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr)
9ecb9aab 2399{
ae1e82c6
HK		 2400 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr));
2401 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4));
2402 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16);
2403 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2));
9ecb9aab 2404}
2405
2992bdfa 2406u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
3127f7c9
HK		 2407{
2408 u16 data1, data2, ioffset;
2409
2410 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2411 data1 = r8168_mac_ocp_read(tp, 0xdd02);
2412 data2 = r8168_mac_ocp_read(tp, 0xdd00);
2413
2414 ioffset = (data2 >> 1) & 0x7ff8;
2415 ioffset |= data2 & 0x0007;
2416 if (data1 & BIT(7))
2417 ioffset |= BIT(15);
2418
2419 return ioffset;
2420}
2421
da78dbff
FR		 2422static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2423{
3f6ca6c7 2424 set_bit(flag, tp->wk.flags);
e2015942
HK		 2425 if (!schedule_work(&tp->wk.work))
2426 clear_bit(flag, tp->wk.flags);
da78dbff
FR		 2427}
2428
b5aed0b3 2429static void rtl8169_init_phy(struct rtl8169_private *tp)
4ff96fa6 2430{
becd837e 2431 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
4ff96fa6 2432
77332894 2433 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
7a67e11d
HK		 2434 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2435 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
b5aed0b3 2436 /* set undocumented MAC Reg C+CR Offset 0x82h */
1ef7286e 2437 RTL_W8(tp, 0x82, 0x01);
77332894 2438 }
4ff96fa6 2439
fc712387
HK		 2440 if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2441 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2442 tp->pci_dev->subsystem_device == 0xe000)
2443 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2444
5b7ad4b7 2445 /* We may have called phy_speed_down before */
703732f0 2446 phy_speed_up(tp->phydev);
5b7ad4b7 2447
703732f0 2448 genphy_soft_reset(tp->phydev);
4ff96fa6
FR		 2449}
2450
ae1e82c6 2451static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr)
773d2021 2452{
df320ed7 2453 rtl_unlock_config_regs(tp);
908ba2bf 2454
ae1e82c6 2455 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4));
711463f8 2456 rtl_pci_commit(tp);
908ba2bf 2457
ae1e82c6 2458 RTL_W32(tp, MAC0, get_unaligned_le32(addr));
711463f8 2459 rtl_pci_commit(tp);
908ba2bf 2460
9ecb9aab 2461 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2462 rtl_rar_exgmac_set(tp, addr);
c28aa385 2463
df320ed7 2464 rtl_lock_config_regs(tp);
773d2021
FR		 2465}
2466
2467static int rtl_set_mac_address(struct net_device *dev, void *p)
2468{
2469 struct rtl8169_private *tp = netdev_priv(dev);
1f7aa2bc 2470 int ret;
773d2021 2471
1f7aa2bc
HK		 2472 ret = eth_mac_addr(dev, p);
2473 if (ret)
2474 return ret;
773d2021 2475
ec2f204b 2476 rtl_rar_set(tp, dev->dev_addr);
773d2021
FR		 2477
2478 return 0;
2479}
2480
e542a226
HW		 2481static void rtl_init_rxcfg(struct rtl8169_private *tp)
2482{
e542a226 2483 switch (tp->mac_version) {
e9588eb9 2484 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2a71883c 2485 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
1ef7286e 2486 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
e542a226 2487 break;
2a71883c 2488 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
511cfd58
MS		 2489 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2490 case RTL_GIGA_MAC_VER_38:
1ef7286e 2491 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
e542a226 2492 break;
4f51e7d3 2493 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
1ef7286e 2494 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
beb330a4 2495 break;
4b0768b6 2496 case RTL_GIGA_MAC_VER_61:
10478283 2497 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
f1bce4ad 2498 break;
fe733618 2499 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_LAST:
4b0768b6
CL		 2500 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST |
2501 RX_PAUSE_SLOT_ON);
2502 break;
e542a226 2503 default:
1ef7286e 2504 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
e542a226
HW		 2505 break;
2506 }
2507}
2508
92fc43b4
HW		 2509static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2510{
9fba0812 2511 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 2512}
2513
9db0ac57 2514static void rtl_jumbo_config(struct rtl8169_private *tp)
d58d46b5 2515{
9db0ac57 2516 bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
5e00e16c 2517 int readrq = 4096;
d58d46b5 2518
7a3bcd39
HK		 2519 if (jumbo && tp->mac_version >= RTL_GIGA_MAC_VER_17 &&
2520 tp->mac_version <= RTL_GIGA_MAC_VER_26)
2521 readrq = 512;
2522
485bb1b3
HK		 2523 rtl_unlock_config_regs(tp);
2524 switch (tp->mac_version) {
485bb1b3 2525 case RTL_GIGA_MAC_VER_17:
7a3bcd39 2526 r8169_mod_reg8_cond(tp, Config4, BIT(0), jumbo);
485bb1b3
HK		 2527 break;
2528 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
7a3bcd39
HK		 2529 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo);
2530 r8169_mod_reg8_cond(tp, Config4, Jumbo_En1, jumbo);
485bb1b3 2531 break;
01649011 2532 case RTL_GIGA_MAC_VER_28:
7a3bcd39 2533 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo);
485bb1b3 2534 break;
0fc75219 2535 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
7a3bcd39
HK		 2536 RTL_W8(tp, MaxTxPacketSize, jumbo ? 0x24 : 0x3f);
2537 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo);
2538 r8169_mod_reg8_cond(tp, Config4, BIT(0), jumbo);
485bb1b3 2539 break;
d58d46b5 2540 default:
d58d46b5
FR		 2541 break;
2542 }
485bb1b3 2543 rtl_lock_config_regs(tp);
21b5f672 2544
5e00e16c
HK		 2545 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2546 pcie_set_readrq(tp->pci_dev, readrq);
453a7789
HK		 2547
2548 /* Chip doesn't support pause in jumbo mode */
11ac4e66
HK		 2549 if (jumbo) {
2550 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2551 tp->phydev->advertising);
2552 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2553 tp->phydev->advertising);
2554 phy_start_aneg(tp->phydev);
2555 }
d58d46b5
FR		 2556}
2557
ffc46952
FR		 2558DECLARE_RTL_COND(rtl_chipcmd_cond)
2559{
1ef7286e 2560 return RTL_R8(tp, ChipCmd) & CmdReset;
ffc46952
FR		 2561}
2562
6f43adc8
FR		 2563static void rtl_hw_reset(struct rtl8169_private *tp)
2564{
1ef7286e 2565 RTL_W8(tp, ChipCmd, CmdReset);
6f43adc8 2566
d6836ef0 2567 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 2568}
2569
254764e5 2570static void rtl_request_firmware(struct rtl8169_private *tp)
953a12cc 2571{
b6ffd97f 2572 struct rtl_fw *rtl_fw;
953a12cc 2573
254764e5
HK		 2574 /* firmware loaded already or no firmware available */
2575 if (tp->rtl_fw || !tp->fw_name)
2576 return;
953a12cc 2577
b6ffd97f 2578 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3bf6ff3c 2579 if (!rtl_fw)
47ad5931 2580 return;
31bd204f 2581
ce8843ab
HK		 2582 rtl_fw->phy_write = rtl_writephy;
2583 rtl_fw->phy_read = rtl_readphy;
2584 rtl_fw->mac_mcu_write = mac_mcu_write;
2585 rtl_fw->mac_mcu_read = mac_mcu_read;
4edb00f3
HK		 2586 rtl_fw->fw_name = tp->fw_name;
2587 rtl_fw->dev = tp_to_dev(tp);
ce8843ab 2588
47ad5931
HK		 2589 if (rtl_fw_request_firmware(rtl_fw))
2590 kfree(rtl_fw);
2591 else
2592 tp->rtl_fw = rtl_fw;
953a12cc
FR		 2593}
2594
92fc43b4
HW		 2595static void rtl_rx_close(struct rtl8169_private *tp)
2596{
1ef7286e 2597 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 2598}
2599
ffc46952
FR		 2600DECLARE_RTL_COND(rtl_npq_cond)
2601{
1ef7286e 2602 return RTL_R8(tp, TxPoll) & NPQ;
ffc46952
FR		 2603}
2604
2605DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2606{
1ef7286e 2607 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
ffc46952
FR		 2608}
2609
6f9395c6
HK		 2610DECLARE_RTL_COND(rtl_rxtx_empty_cond)
2611{
2612 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2613}
2614
0439297b
HK		 2615DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)
2616{
2617 /* IntrMitigate has new functionality on RTL8125 */
2618 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2619}
2620
6f9395c6
HK		 2621static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2622{
2623 switch (tp->mac_version) {
4f51e7d3 2624 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
6f9395c6
HK		 2625 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
2626 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2627 break;
efc37109 2628 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61:
6f9395c6
HK		 2629 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2630 break;
fe733618 2631 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_LAST:
0439297b
HK		 2632 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2633 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2634 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
2635 break;
6f9395c6
HK		 2636 default:
2637 break;
2638 }
2639}
2640
3406079b
CL		 2641static void rtl_disable_rxdvgate(struct rtl8169_private *tp)
2642{
2643 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2644}
2645
9617886f
HK		 2646static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2647{
2648 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2649 fsleep(2000);
6f9395c6 2650 rtl_wait_txrx_fifo_empty(tp);
9617886f
HK		 2651}
2652
ad425666
CL		 2653static void rtl_wol_enable_rx(struct rtl8169_private *tp)
2654{
2655 if (tp->mac_version >= RTL_GIGA_MAC_VER_25)
2656 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2657 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
bb41c13c
CL		 2658
2659 if (tp->mac_version >= RTL_GIGA_MAC_VER_40)
2660 rtl_disable_rxdvgate(tp);
ad425666
CL		 2661}
2662
2663static void rtl_prepare_power_down(struct rtl8169_private *tp)
2664{
0ab0c45d 2665 if (tp->dash_enabled)
ad425666
CL		 2666 return;
2667
2668 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2669 tp->mac_version == RTL_GIGA_MAC_VER_33)
2670 rtl_ephy_write(tp, 0x19, 0xff64);
2671
2672 if (device_may_wakeup(tp_to_dev(tp))) {
2673 phy_speed_down(tp->phydev, false);
2674 rtl_wol_enable_rx(tp);
2675 }
2676}
2677
05212ba8 2678static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
9cb427b6 2679{
ad5f97fa
HK		 2680 u32 val = TX_DMA_BURST << TxDMAShift |
2681 InterFrameGap << TxInterFrameGapShift;
2682
9e9f33ba 2683 if (rtl_is_8168evl_up(tp))
ad5f97fa
HK		 2684 val |= TXCFG_AUTO_FIFO;
2685
2686 RTL_W32(tp, TxConfig, val);
9cb427b6
FR		 2687}
2688
4fd48c4a 2689static void rtl_set_rx_max_size(struct rtl8169_private *tp)
1da177e4 2690{
4fd48c4a
HK		 2691 /* Low hurts. Let's disable the filtering. */
2692 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
07ce4064
FR		 2693}
2694
1ef7286e 2695static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
7f796d83
FR		 2696{
2697 /*
2698 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2699 * register to be written before TxDescAddrLow to work.
2700 * Switching from MMIO to I/O access fixes the issue as well.
2701 */
1ef7286e
AS		 2702 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2703 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2704 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2705 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 2706}
2707
ef891284 2708static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
6dccd16b 2709{
34bc0095
HK		 2710 u32 val;
2711
2712 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2713 val = 0x000fff00;
2714 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2715 val = 0x00ffff00;
2716 else
2717 return;
2718
2719 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2720 val |= 0xff;
2721
2722 RTL_W32(tp, 0x7c, val);
6dccd16b
FR		 2723}
2724
e6b763ea
FR		 2725static void rtl_set_rx_mode(struct net_device *dev)
2726{
81cd17a4
HK		 2727 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2728 /* Multicast hash filter */
2729 u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
e6b763ea 2730 struct rtl8169_private *tp = netdev_priv(dev);
81cd17a4 2731 u32 tmp;
e6b763ea
FR		 2732
2733 if (dev->flags & IFF_PROMISC) {
81cd17a4 2734 rx_mode |= AcceptAllPhys;
8999ce4c
HK		 2735 } else if (!(dev->flags & IFF_MULTICAST)) {
2736 rx_mode &= ~AcceptMulticast;
cd04b44b 2737 } else if (dev->flags & IFF_ALLMULTI ||
6a263102 2738 tp->mac_version == RTL_GIGA_MAC_VER_35) {
81cd17a4
HK		 2739 /* accept all multicasts */
2740 } else if (netdev_mc_empty(dev)) {
2741 rx_mode &= ~AcceptMulticast;
e6b763ea
FR		 2742 } else {
2743 struct netdev_hw_addr *ha;
2744
e6b763ea
FR		 2745 mc_filter[1] = mc_filter[0] = 0;
2746 netdev_for_each_mc_addr(ha, dev) {
bc54ac36 2747 u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
81cd17a4
HK		 2748 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2749 }
2750
2751 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2752 tmp = mc_filter[0];
2753 mc_filter[0] = swab32(mc_filter[1]);
2754 mc_filter[1] = swab32(tmp);
e6b763ea
FR		 2755 }
2756 }
2757
1ef7286e
AS		 2758 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2759 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
e6b763ea 2760
81cd17a4 2761 tmp = RTL_R32(tp, RxConfig);
10478283 2762 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
e6b763ea
FR		 2763}
2764
ffc46952
FR		 2765DECLARE_RTL_COND(rtl_csiar_cond)
2766{
1ef7286e 2767 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
ffc46952
FR		 2768}
2769
ff1d7331 2770static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
beb1fe18 2771{
ff1d7331 2772 u32 func = PCI_FUNC(tp->pci_dev->devfn);
beb1fe18 2773
1ef7286e
AS		 2774 RTL_W32(tp, CSIDR, value);
2775 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
ff1d7331 2776 CSIAR_BYTE_ENABLE | func << 16);
7e18dca1 2777
d6836ef0 2778 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 2779}
2780
ff1d7331 2781static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 2782{
ff1d7331
HK		 2783 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2784
2785 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2786 CSIAR_BYTE_ENABLE);
7e18dca1 2787
d6836ef0 2788 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
1ef7286e 2789 RTL_R32(tp, CSIDR) : ~0;
7e18dca1
HW		 2790}
2791
8c40d99e
HK		 2792static void rtl_csi_mod(struct rtl8169_private *tp, int addr,
2793 u32 mask, u32 set)
2794{
2795 u32 val;
2796
2797 WARN(addr % 4, "Invalid CSI address %#x\n", addr);
2798
2799 netdev_notice_once(tp->dev,
2800 "No native access to PCI extended config space, falling back to CSI\n");
2801
2802 val = rtl_csi_read(tp, addr);
2803 rtl_csi_write(tp, addr, (val & ~mask) | set);
2804}
2805
b48688ea
CL		 2806static void rtl_disable_zrxdc_timeout(struct rtl8169_private *tp)
2807{
2808 struct pci_dev *pdev = tp->pci_dev;
b48688ea
CL		 2809 int rc;
2810 u8 val;
2811
2812#define RTL_GEN3_RELATED_OFF 0x0890
2813#define RTL_GEN3_ZRXDC_NONCOMPL 0x1
2814 if (pdev->cfg_size > RTL_GEN3_RELATED_OFF) {
2815 rc = pci_read_config_byte(pdev, RTL_GEN3_RELATED_OFF, &val);
2816 if (rc == PCIBIOS_SUCCESSFUL) {
2817 val &= ~RTL_GEN3_ZRXDC_NONCOMPL;
2818 rc = pci_write_config_byte(pdev, RTL_GEN3_RELATED_OFF,
2819 val);
2820 if (rc == PCIBIOS_SUCCESSFUL)
2821 return;
2822 }
2823 }
2824
8c40d99e 2825 rtl_csi_mod(tp, RTL_GEN3_RELATED_OFF, RTL_GEN3_ZRXDC_NONCOMPL, 0);
b48688ea
CL		 2826}
2827
c07c8ffc 2828static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val)
45dd95c4 2829{
ff1d7331 2830 struct pci_dev *pdev = tp->pci_dev;
45dd95c4 2831
ff1d7331
HK		 2832 /* According to Realtek the value at config space address 0x070f
2833 * controls the L0s/L1 entrance latency. We try standard ECAM access
2834 * first and if it fails fall back to CSI.
c07c8ffc
HK		 2835 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo)
2836 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us
ff1d7331
HK		 2837 */
2838 if (pdev->cfg_size > 0x070f &&
2839 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
2840 return;
2841
8c40d99e 2842 rtl_csi_mod(tp, 0x070c, 0xff000000, val << 24);
45dd95c4 2843}
2844
f37658da 2845static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
beb1fe18 2846{
c07c8ffc
HK		 2847 /* L0 7us, L1 16us */
2848 rtl_set_aspm_entry_latency(tp, 0x27);
dacf8154
FR		 2849}
2850
2851struct ephy_info {
2852 unsigned int offset;
2853 u16 mask;
2854 u16 bits;
2855};
2856
1791ad50
HK		 2857static void __rtl_ephy_init(struct rtl8169_private *tp,
2858 const struct ephy_info *e, int len)
dacf8154
FR		 2859{
2860 u16 w;
2861
2862 while (len-- > 0) {
fdf6fc06
FR		 2863 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2864 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 2865 e++;
2866 }
2867}
2868
1791ad50
HK		 2869#define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2870
73c86ee3 2871static void rtl_disable_clock_request(struct rtl8169_private *tp)
b726e493 2872{
73c86ee3 2873 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 2874 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 2875}
2876
73c86ee3 2877static void rtl_enable_clock_request(struct rtl8169_private *tp)
e6de30d6 2878{
73c86ee3 2879 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 2880 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 2881}
2882
c259b7f4 2883static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
b51ecea8 2884{
c259b7f4
HK		 2885 /* work around an issue when PCI reset occurs during L2/L3 state */
2886 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
b51ecea8 2887}
2888
4b33433e
HK		 2889static void rtl_enable_exit_l1(struct rtl8169_private *tp)
2890{
2891 /* Bits control which events trigger ASPM L1 exit:
2892 * Bit 12: rxdv
2893 * Bit 11: ltr_msg
2894 * Bit 10: txdma_poll
2895 * Bit 9: xadm
2896 * Bit 8: pktavi
2897 * Bit 7: txpla
2898 */
2899 switch (tp->mac_version) {
2900 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2901 rtl_eri_set_bits(tp, 0xd4, 0x1f00);
2902 break;
2903 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38:
2904 rtl_eri_set_bits(tp, 0xd4, 0x0c00);
2905 break;
fe733618 2906 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST:
4b33433e
HK		 2907 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80);
2908 break;
2909 default:
2910 break;
2911 }
2912}
2913
d192181c
HK		 2914static void rtl_disable_exit_l1(struct rtl8169_private *tp)
2915{
2916 switch (tp->mac_version) {
2917 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
2918 rtl_eri_clear_bits(tp, 0xd4, 0x1f00);
2919 break;
fe733618 2920 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST:
d192181c
HK		 2921 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0);
2922 break;
2923 default:
2924 break;
2925 }
2926}
2927
a99790bf
KHF		 2928static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2929{
3907f1ff
HK		 2930 u8 val8;
2931
49ef7d84
HK		 2932 if (tp->mac_version < RTL_GIGA_MAC_VER_32)
2933 return;
2934
cf2ffdea
HK		 2935 /* Don't enable ASPM in the chip if OS can't control ASPM */
2936 if (enable && tp->aspm_manageable) {
162d626f
HK		 2937 /* On these chip versions ASPM can even harm
2938 * bus communication of other PCI devices.
2939 */
2940 if (tp->mac_version == RTL_GIGA_MAC_VER_42 ||
2941 tp->mac_version == RTL_GIGA_MAC_VER_43)
2942 return;
2943
6bc6c4e6 2944 rtl_mod_config5(tp, 0, ASPM_en);
3907f1ff 2945 switch (tp->mac_version) {
b299ea00 2946 case RTL_GIGA_MAC_VER_70:
f24f7b2f 2947 case RTL_GIGA_MAC_VER_80:
3907f1ff
HK		 2948 val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN;
2949 RTL_W8(tp, INT_CFG0_8125, val8);
2950 break;
2951 default:
2952 rtl_mod_config2(tp, 0, ClkReqEn);
2953 break;
2954 }
c217ab7a
HK		 2955
2956 switch (tp->mac_version) {
ebe59898 2957 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
fe733618 2958 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST:
c217ab7a
HK		 2959 /* reset ephy tx/rx disable timer */
2960 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0);
2961 /* chip can trigger L1.2 */
2962 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2));
2963 break;
2964 default:
2965 break;
2966 }
a99790bf 2967 } else {
c217ab7a 2968 switch (tp->mac_version) {
ebe59898 2969 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
fe733618 2970 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST:
c217ab7a
HK		 2971 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0);
2972 break;
2973 default:
2974 break;
2975 }
2976
3907f1ff 2977 switch (tp->mac_version) {
b299ea00 2978 case RTL_GIGA_MAC_VER_70:
f24f7b2f 2979 case RTL_GIGA_MAC_VER_80:
3907f1ff
HK		 2980 val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN;
2981 RTL_W8(tp, INT_CFG0_8125, val8);
2982 break;
2983 default:
2984 rtl_mod_config2(tp, ClkReqEn, 0);
2985 break;
2986 }
6bc6c4e6 2987 rtl_mod_config5(tp, ASPM_en, 0);
a99790bf
KHF		 2988 }
2989}
2990
6b1bd242
HK		 2991static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2992 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
2993{
2994 /* Usage of dynamic vs. static FIFO is controlled by bit
2995 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
2996 */
2997 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
2998 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
2999}
3000
0ebacd12
HK		 3001static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
3002 u8 low, u8 high)
3003{
3004 /* FIFO thresholds for pause flow control */
3005 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
3006 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
3007}
3008
94b5ff74 3009static void rtl_hw_start_8168b(struct rtl8169_private *tp)
219a1e9d 3010{
1ef7286e 3011 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
219a1e9d
FR		 3012}
3013
beb1fe18 3014static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 3015{
1ef7286e 3016 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
b726e493 3017
1ef7286e 3018 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
b726e493 3019
73c86ee3 3020 rtl_disable_clock_request(tp);
219a1e9d
FR		 3021}
3022
beb1fe18 3023static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 3024{
350f7596 3025 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 3026 { 0x01, 0, 0x0001 },
3027 { 0x02, 0x0800, 0x1000 },
3028 { 0x03, 0, 0x0042 },
3029 { 0x06, 0x0080, 0x0000 },
3030 { 0x07, 0, 0x2000 }
3031 };
3032
f37658da 3033 rtl_set_def_aspm_entry_latency(tp);
b726e493 3034
1791ad50 3035 rtl_ephy_init(tp, e_info_8168cp);
b726e493 3036
beb1fe18 3037 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 3038}
3039
beb1fe18 3040static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 3041{
f37658da 3042 rtl_set_def_aspm_entry_latency(tp);
ef3386f0 3043
1ef7286e 3044 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
ef3386f0
FR		 3045}
3046
beb1fe18 3047static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 3048{
f37658da 3049 rtl_set_def_aspm_entry_latency(tp);
7f3e3d3a 3050
1ef7286e 3051 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
7f3e3d3a
FR		 3052
3053 /* Magic. */
1ef7286e 3054 RTL_W8(tp, DBG_REG, 0x20);
7f3e3d3a
FR		 3055}
3056
beb1fe18 3057static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 3058{
350f7596 3059 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 3060 { 0x02, 0x0800, 0x1000 },
3061 { 0x03, 0, 0x0002 },
3062 { 0x06, 0x0080, 0x0000 }
3063 };
3064
f37658da 3065 rtl_set_def_aspm_entry_latency(tp);
b726e493 3066
1ef7286e 3067 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
b726e493 3068
1791ad50 3069 rtl_ephy_init(tp, e_info_8168c_1);
b726e493 3070
beb1fe18 3071 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 3072}
3073
beb1fe18 3074static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 3075{
350f7596 3076 static const struct ephy_info e_info_8168c_2[] = {
b726e493 3077 { 0x01, 0, 0x0001 },
a7a92cf8 3078 { 0x03, 0x0400, 0x0020 }
b726e493
FR		 3079 };
3080
f37658da 3081 rtl_set_def_aspm_entry_latency(tp);
b726e493 3082
1791ad50 3083 rtl_ephy_init(tp, e_info_8168c_2);
b726e493 3084
beb1fe18 3085 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 3086}
3087
beb1fe18 3088static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 3089{
f37658da 3090 rtl_set_def_aspm_entry_latency(tp);
6fb07058 3091
beb1fe18 3092 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 3093}
3094
beb1fe18 3095static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 3096{
f37658da 3097 rtl_set_def_aspm_entry_latency(tp);
5b538df9 3098
73c86ee3 3099 rtl_disable_clock_request(tp);
5b538df9
FR		 3100}
3101
beb1fe18 3102static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 3103{
3104 static const struct ephy_info e_info_8168d_4[] = {
1016a4a1
CHL		 3105 { 0x0b, 0x0000, 0x0048 },
3106 { 0x19, 0x0020, 0x0050 },
a7a92cf8
HK		 3107 { 0x0c, 0x0100, 0x0020 },
3108 { 0x10, 0x0004, 0x0000 },
e6de30d6 3109 };
e6de30d6 3110
f37658da 3111 rtl_set_def_aspm_entry_latency(tp);
e6de30d6 3112
1791ad50 3113 rtl_ephy_init(tp, e_info_8168d_4);
e6de30d6 3114
73c86ee3 3115 rtl_enable_clock_request(tp);
e6de30d6 3116}
3117
beb1fe18 3118static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 3119{
70090424 3120 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 3121 { 0x00, 0x0200, 0x0100 },
3122 { 0x00, 0x0000, 0x0004 },
3123 { 0x06, 0x0002, 0x0001 },
3124 { 0x06, 0x0000, 0x0030 },
3125 { 0x07, 0x0000, 0x2000 },
3126 { 0x00, 0x0000, 0x0020 },
3127 { 0x03, 0x5800, 0x2000 },
3128 { 0x03, 0x0000, 0x0001 },
3129 { 0x01, 0x0800, 0x1000 },
3130 { 0x07, 0x0000, 0x4000 },
3131 { 0x1e, 0x0000, 0x2000 },
3132 { 0x19, 0xffff, 0xfe6c },
3133 { 0x0a, 0x0000, 0x0040 }
3134 };
3135
f37658da 3136 rtl_set_def_aspm_entry_latency(tp);
01dc7fec 3137
1791ad50 3138 rtl_ephy_init(tp, e_info_8168e_1);
01dc7fec 3139
73c86ee3 3140 rtl_disable_clock_request(tp);
01dc7fec 3141
3142 /* Reset tx FIFO pointer */
1ef7286e
AS		 3143 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
3144 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
01dc7fec 3145
6bc6c4e6 3146 rtl_mod_config5(tp, Spi_en, 0);
01dc7fec 3147}
3148
beb1fe18 3149static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424
HW		 3150{
3151 static const struct ephy_info e_info_8168e_2[] = {
3152 { 0x09, 0x0000, 0x0080 },
a7a92cf8
HK		 3153 { 0x19, 0x0000, 0x0224 },
3154 { 0x00, 0x0000, 0x0004 },
3155 { 0x0c, 0x3df0, 0x0200 },
70090424
HW		 3156 };
3157
f37658da 3158 rtl_set_def_aspm_entry_latency(tp);
70090424 3159
1791ad50 3160 rtl_ephy_init(tp, e_info_8168e_2);
70090424 3161
724c6fd0 3162 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
33b00ca1 3163 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
6b1bd242 3164 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
33b00ca1
HK		 3165 rtl_eri_set_bits(tp, 0x1d0, BIT(1));
3166 rtl_reset_packet_filter(tp);
3167 rtl_eri_set_bits(tp, 0x1b0, BIT(4));
724c6fd0
HK		 3168 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
3169 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
70090424 3170
73c86ee3 3171 rtl_disable_clock_request(tp);
4521e1a9 3172
1ef7286e 3173 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
70090424 3174
cc07d271
HK		 3175 rtl8168_config_eee_mac(tp);
3176
1ef7286e
AS		 3177 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3178 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
6bc6c4e6 3179 rtl_mod_config5(tp, Spi_en, 0);
70090424
HW		 3180}
3181
5f886e08 3182static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 3183{
f37658da 3184 rtl_set_def_aspm_entry_latency(tp);
c2218925 3185
724c6fd0 3186 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
d05890c5 3187 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
6b1bd242 3188 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4e7e4621 3189 rtl_reset_packet_filter(tp);
54113ded 3190 rtl_eri_set_bits(tp, 0x1b0, BIT(4));
d05890c5 3191 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
724c6fd0
HK		 3192 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
3193 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
c2218925 3194
73c86ee3 3195 rtl_disable_clock_request(tp);
4521e1a9 3196
1ef7286e
AS		 3197 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3198 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3199 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
6bc6c4e6 3200 rtl_mod_config5(tp, Spi_en, 0);
cc07d271
HK		 3201
3202 rtl8168_config_eee_mac(tp);
c2218925
HW		 3203}
3204
5f886e08
HW		 3205static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
3206{
5f886e08
HW		 3207 static const struct ephy_info e_info_8168f_1[] = {
3208 { 0x06, 0x00c0, 0x0020 },
3209 { 0x08, 0x0001, 0x0002 },
3210 { 0x09, 0x0000, 0x0080 },
a7a92cf8 3211 { 0x19, 0x0000, 0x0224 },
709a16be 3212 { 0x00, 0x0000, 0x0008 },
a7a92cf8 3213 { 0x0c, 0x3df0, 0x0200 },
5f886e08
HW		 3214 };
3215
3216 rtl_hw_start_8168f(tp);
3217
1791ad50 3218 rtl_ephy_init(tp, e_info_8168f_1);
5f886e08
HW		 3219}
3220
b3d7b2f2
HW		 3221static void rtl_hw_start_8411(struct rtl8169_private *tp)
3222{
b3d7b2f2
HW		 3223 static const struct ephy_info e_info_8168f_1[] = {
3224 { 0x06, 0x00c0, 0x0020 },
3225 { 0x0f, 0xffff, 0x5200 },
a7a92cf8 3226 { 0x19, 0x0000, 0x0224 },
709a16be 3227 { 0x00, 0x0000, 0x0008 },
a7a92cf8 3228 { 0x0c, 0x3df0, 0x0200 },
b3d7b2f2
HW		 3229 };
3230
3231 rtl_hw_start_8168f(tp);
c259b7f4 3232 rtl_pcie_state_l2l3_disable(tp);
b3d7b2f2 3233
1791ad50 3234 rtl_ephy_init(tp, e_info_8168f_1);
b3d7b2f2
HW		 3235}
3236
5fbea337 3237static void rtl_hw_start_8168g(struct rtl8169_private *tp)
c558386b 3238{
6b1bd242 3239 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
0ebacd12 3240 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
c558386b 3241
f37658da 3242 rtl_set_def_aspm_entry_latency(tp);
c558386b 3243
4e7e4621 3244 rtl_reset_packet_filter(tp);
724c6fd0 3245 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
c558386b 3246
3406079b 3247 rtl_disable_rxdvgate(tp);
c558386b 3248
724c6fd0
HK		 3249 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3250 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
c558386b 3251
df6f1856
HK		 3252 rtl8168_config_eee_mac(tp);
3253
54113ded
HK		 3254 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3255 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
b51ecea8 3256
c259b7f4 3257 rtl_pcie_state_l2l3_disable(tp);
c558386b
HW		 3258}
3259
5fbea337
CHL		 3260static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
3261{
5fbea337 3262 static const struct ephy_info e_info_8168g_1[] = {
a7a92cf8
HK		 3263 { 0x00, 0x0008, 0x0000 },
3264 { 0x0c, 0x3ff0, 0x0820 },
5fbea337
CHL		 3265 { 0x1e, 0x0000, 0x0001 },
3266 { 0x19, 0x8000, 0x0000 }
3267 };
3268
3269 rtl_hw_start_8168g(tp);
1791ad50 3270 rtl_ephy_init(tp, e_info_8168g_1);
5fbea337
CHL		 3271}
3272
57538c4a 3273static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
3274{
57538c4a 3275 static const struct ephy_info e_info_8168g_2[] = {
a7a92cf8
HK		 3276 { 0x00, 0x0008, 0x0000 },
3277 { 0x0c, 0x3ff0, 0x0820 },
3278 { 0x19, 0xffff, 0x7c00 },
3279 { 0x1e, 0xffff, 0x20eb },
3280 { 0x0d, 0xffff, 0x1666 },
3281 { 0x00, 0xffff, 0x10a3 },
3282 { 0x06, 0xffff, 0xf050 },
3283 { 0x04, 0x0000, 0x0010 },
3284 { 0x1d, 0x4000, 0x0000 },
57538c4a 3285 };
3286
5fbea337 3287 rtl_hw_start_8168g(tp);
1791ad50 3288 rtl_ephy_init(tp, e_info_8168g_2);
57538c4a 3289}
3290
055dd751
HK		 3291static void rtl8411b_fix_phy_down(struct rtl8169_private *tp)
3292{
3293 static const u16 fix_data[] = {
3294/* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065,
3295/* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00,
3296/* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009,
3297/* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006,
3298/* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2,
3299/* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400,
3300/* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519,
3301/* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4,
3302/* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508,
3303/* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434,
3304/* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007,
3305/* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00,
3306/* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1,
3307/* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132
3308 };
3309 unsigned long flags;
3310 int i;
3311
3312 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
3313 for (i = 0; i < ARRAY_SIZE(fix_data); i++)
3314 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]);
3315 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
3316}
3317
45dd95c4 3318static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
3319{
45dd95c4 3320 static const struct ephy_info e_info_8411_2[] = {
a7a92cf8
HK		 3321 { 0x00, 0x0008, 0x0000 },
3322 { 0x0c, 0x37d0, 0x0820 },
3323 { 0x1e, 0x0000, 0x0001 },
3324 { 0x19, 0x8021, 0x0000 },
3325 { 0x1e, 0x0000, 0x2000 },
3326 { 0x0d, 0x0100, 0x0200 },
3327 { 0x00, 0x0000, 0x0080 },
3328 { 0x06, 0x0000, 0x0010 },
3329 { 0x04, 0x0000, 0x0010 },
3330 { 0x1d, 0x0000, 0x4000 },
45dd95c4 3331 };
3332
5fbea337 3333 rtl_hw_start_8168g(tp);
45dd95c4 3334
1791ad50 3335 rtl_ephy_init(tp, e_info_8411_2);
fe4e8db0
HK		 3336
3337 /* The following Realtek-provided magic fixes an issue with the RX unit
3338 * getting confused after the PHY having been powered-down.
3339 */
3340 r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3341 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3342 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3343 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
3344 r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
3345 r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
3346 r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
3347 r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
3348 mdelay(3);
3349 r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
3350
055dd751 3351 rtl8411b_fix_phy_down(tp);
fe4e8db0
HK		 3352
3353 r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3354
3355 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3356 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3357 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3358 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3359 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3360 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3361 r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
45dd95c4 3362}
3363
6e1d0b89
CHL		 3364static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3365{
6e1d0b89
CHL		 3366 static const struct ephy_info e_info_8168h_1[] = {
3367 { 0x1e, 0x0800, 0x0001 },
3368 { 0x1d, 0x0000, 0x0800 },
3369 { 0x05, 0xffff, 0x2089 },
3370 { 0x06, 0xffff, 0x5881 },
a7a92cf8 3371 { 0x04, 0xffff, 0x854a },
6e1d0b89
CHL		 3372 { 0x01, 0xffff, 0x068b }
3373 };
ef712ede 3374 int rg_saw_cnt;
6e1d0b89 3375
1791ad50 3376 rtl_ephy_init(tp, e_info_8168h_1);
6e1d0b89 3377
6b1bd242 3378 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
0ebacd12 3379 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
6e1d0b89 3380
f37658da 3381 rtl_set_def_aspm_entry_latency(tp);
6e1d0b89 3382
4e7e4621 3383 rtl_reset_packet_filter(tp);
6e1d0b89 3384
ee1350f9 3385 rtl_eri_set_bits(tp, 0xdc, 0x001c);
6e1d0b89 3386
724c6fd0 3387 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
6e1d0b89 3388
3406079b 3389 rtl_disable_rxdvgate(tp);
6e1d0b89 3390
724c6fd0
HK		 3391 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3392 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
6e1d0b89 3393
df6f1856
HK		 3394 rtl8168_config_eee_mac(tp);
3395
1ef7286e
AS		 3396 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3397 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
6e1d0b89 3398
1ef7286e 3399 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
6e1d0b89 3400
54113ded 3401 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
6e1d0b89 3402
c259b7f4 3403 rtl_pcie_state_l2l3_disable(tp);
6e1d0b89 3404
3ab077d2 3405 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
6e1d0b89
CHL		 3406 if (rg_saw_cnt > 0) {
3407 u16 sw_cnt_1ms_ini;
3408
3409 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3410 sw_cnt_1ms_ini &= 0x0fff;
ef712ede 3411 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
6e1d0b89
CHL		 3412 }
3413
ef712ede
HK		 3414 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3415 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3416 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3417 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
6e1d0b89
CHL		 3418
3419 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3420 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3421 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3422 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3423}
3424
935e2218
CHL		 3425static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3426{
003609da
CHL		 3427 rtl8168ep_stop_cmac(tp);
3428
6b1bd242 3429 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
0ebacd12 3430 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
935e2218 3431
f37658da 3432 rtl_set_def_aspm_entry_latency(tp);
935e2218 3433
4e7e4621 3434 rtl_reset_packet_filter(tp);
935e2218 3435
724c6fd0 3436 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
935e2218 3437
3406079b 3438 rtl_disable_rxdvgate(tp);
935e2218 3439
724c6fd0
HK		 3440 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3441 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
935e2218 3442
df6f1856
HK		 3443 rtl8168_config_eee_mac(tp);
3444
54113ded 3445 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
935e2218 3446
1ef7286e 3447 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
935e2218 3448
c259b7f4 3449 rtl_pcie_state_l2l3_disable(tp);
935e2218
CHL		 3450}
3451
935e2218
CHL		 3452static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3453{
935e2218 3454 static const struct ephy_info e_info_8168ep_3[] = {
a7a92cf8
HK		 3455 { 0x00, 0x0000, 0x0080 },
3456 { 0x0d, 0x0100, 0x0200 },
3457 { 0x19, 0x8021, 0x0000 },
3458 { 0x1e, 0x0000, 0x2000 },
935e2218
CHL		 3459 };
3460
1791ad50 3461 rtl_ephy_init(tp, e_info_8168ep_3);
935e2218
CHL		 3462
3463 rtl_hw_start_8168ep(tp);
3464
1ef7286e
AS		 3465 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3466 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
935e2218 3467
ef712ede
HK		 3468 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3469 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3470 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
935e2218
CHL		 3471}
3472
1287723a
HK		 3473static void rtl_hw_start_8117(struct rtl8169_private *tp)
3474{
3475 static const struct ephy_info e_info_8117[] = {
3476 { 0x19, 0x0040, 0x1100 },
3477 { 0x59, 0x0040, 0x1100 },
3478 };
3479 int rg_saw_cnt;
3480
3481 rtl8168ep_stop_cmac(tp);
1287723a
HK		 3482 rtl_ephy_init(tp, e_info_8117);
3483
3484 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3485 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3486
3487 rtl_set_def_aspm_entry_latency(tp);
3488
3489 rtl_reset_packet_filter(tp);
3490
4b33433e 3491 rtl_eri_set_bits(tp, 0xd4, 0x0010);
1287723a
HK		 3492
3493 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3494
3406079b 3495 rtl_disable_rxdvgate(tp);
1287723a
HK		 3496
3497 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3498 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3499
3500 rtl8168_config_eee_mac(tp);
3501
3502 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3503 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3504
3505 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3506
54113ded 3507 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
1287723a
HK		 3508
3509 rtl_pcie_state_l2l3_disable(tp);
3510
3511 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3512 if (rg_saw_cnt > 0) {
3513 u16 sw_cnt_1ms_ini;
3514
3515 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3516 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3517 }
3518
3519 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3520 r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3521 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3522 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3523
3524 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3525 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3526 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3527 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3528
229c1e0d 3529 /* firmware is for MAC only */
1c5be5e9 3530 r8169_apply_firmware(tp);
1287723a
HK		 3531}
3532
beb1fe18 3533static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 3534{
350f7596 3535 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 3536 { 0x01, 0, 0x6e65 },
3537 { 0x02, 0, 0x091f },
3538 { 0x03, 0, 0xc2f9 },
3539 { 0x06, 0, 0xafb5 },
3540 { 0x07, 0, 0x0e00 },
3541 { 0x19, 0, 0xec80 },
3542 { 0x01, 0, 0x2e65 },
3543 { 0x01, 0, 0x6e65 }
3544 };
3545 u8 cfg1;
3546
f37658da 3547 rtl_set_def_aspm_entry_latency(tp);
2857ffb7 3548
1ef7286e 3549 RTL_W8(tp, DBG_REG, FIX_NAK_1);
2857ffb7 3550
1ef7286e 3551 RTL_W8(tp, Config1,
2857ffb7 3552 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
1ef7286e 3553 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7 3554
1ef7286e 3555 cfg1 = RTL_R8(tp, Config1);
2857ffb7 3556 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
1ef7286e 3557 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
2857ffb7 3558
1791ad50 3559 rtl_ephy_init(tp, e_info_8102e_1);
2857ffb7
FR		 3560}
3561
beb1fe18 3562static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 3563{
f37658da 3564 rtl_set_def_aspm_entry_latency(tp);
2857ffb7 3565
1ef7286e
AS		 3566 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3567 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7
FR		 3568}
3569
beb1fe18 3570static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 3571{
beb1fe18 3572 rtl_hw_start_8102e_2(tp);
2857ffb7 3573
fdf6fc06 3574 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 3575}
3576
cdafdc29
HK		 3577static void rtl_hw_start_8401(struct rtl8169_private *tp)
3578{
3579 static const struct ephy_info e_info_8401[] = {
3580 { 0x01, 0xffff, 0x6fe5 },
3581 { 0x03, 0xffff, 0x0599 },
3582 { 0x06, 0xffff, 0xaf25 },
3583 { 0x07, 0xffff, 0x8e68 },
3584 };
3585
3586 rtl_ephy_init(tp, e_info_8401);
3587 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3588}
3589
beb1fe18 3590static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443
HW		 3591{
3592 static const struct ephy_info e_info_8105e_1[] = {
3593 { 0x07, 0, 0x4000 },
3594 { 0x19, 0, 0x0200 },
3595 { 0x19, 0, 0x0020 },
3596 { 0x1e, 0, 0x2000 },
3597 { 0x03, 0, 0x0001 },
3598 { 0x19, 0, 0x0100 },
3599 { 0x19, 0, 0x0004 },
3600 { 0x0a, 0, 0x0020 }
3601 };
3602
cecb5fd7 3603 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 3604 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5a5e4443 3605
cecb5fd7 3606 /* Disable Early Tally Counter */
1ef7286e 3607 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5a5e4443 3608
1ef7286e
AS		 3609 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3610 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5a5e4443 3611
1791ad50 3612 rtl_ephy_init(tp, e_info_8105e_1);
b51ecea8 3613
c259b7f4 3614 rtl_pcie_state_l2l3_disable(tp);
5a5e4443
HW		 3615}
3616
beb1fe18 3617static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 3618{
beb1fe18 3619 rtl_hw_start_8105e_1(tp);
fdf6fc06 3620 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 3621}
3622
7e18dca1
HW		 3623static void rtl_hw_start_8402(struct rtl8169_private *tp)
3624{
7e18dca1
HW		 3625 static const struct ephy_info e_info_8402[] = {
3626 { 0x19, 0xffff, 0xff64 },
3627 { 0x1e, 0, 0x4000 }
3628 };
3629
f37658da 3630 rtl_set_def_aspm_entry_latency(tp);
7e18dca1
HW		 3631
3632 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 3633 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
7e18dca1 3634
1ef7286e 3635 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7e18dca1 3636
1791ad50 3637 rtl_ephy_init(tp, e_info_8402);
7e18dca1 3638
6b1bd242 3639 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
4e7e4621 3640 rtl_reset_packet_filter(tp);
724c6fd0
HK		 3641 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3642 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
54113ded 3643 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
b51ecea8 3644
6d7a631e
HK		 3645 /* disable EEE */
3646 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3647
c259b7f4 3648 rtl_pcie_state_l2l3_disable(tp);
7e18dca1
HW		 3649}
3650
5598bfe5
HW		 3651static void rtl_hw_start_8106(struct rtl8169_private *tp)
3652{
5598bfe5 3653 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 3654 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5598bfe5 3655
1ef7286e
AS		 3656 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3657 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3658 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
b51ecea8 3659
c07c8ffc
HK		 3660 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */
3661 rtl_set_aspm_entry_latency(tp, 0x2f);
9c401864 3662
8d46f620
HK		 3663 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3664
6d7a631e
HK		 3665 /* disable EEE */
3666 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3667
c259b7f4 3668 rtl_pcie_state_l2l3_disable(tp);
5598bfe5
HW		 3669}
3670
f1bce4ad
HK		 3671DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3672{
3673 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3674}
3675
3676static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3677{
3678 rtl_pcie_state_l2l3_disable(tp);
3679
3680 RTL_W16(tp, 0x382, 0x221b);
2cd02f2f
HK		 3681 RTL_W32(tp, RSS_CTRL_8125, 0);
3682 RTL_W16(tp, Q_NUM_CTRL_8125, 0);
f1bce4ad
HK		 3683
3684 /* disable UPS */
3685 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3686
3687 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3688
3689 r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3690 r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3691
3692 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3693 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3694 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3695
3696 /* disable new tx descriptor format */
3697 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3698
f24f7b2f
CL		 3699 if (tp->mac_version == RTL_GIGA_MAC_VER_70 ||
3700 tp->mac_version == RTL_GIGA_MAC_VER_80)
3907f1ff
HK		 3701 RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02);
3702
f24f7b2f
CL		 3703 if (tp->mac_version == RTL_GIGA_MAC_VER_80)
3704 r8168_mac_ocp_modify(tp, 0xe614, 0x0f00, 0x0f00);
3705 else if (tp->mac_version == RTL_GIGA_MAC_VER_70)
3907f1ff
HK		 3706 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3707 else if (tp->mac_version == RTL_GIGA_MAC_VER_63)
0439297b
HK		 3708 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
3709 else
3907f1ff 3710 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0300);
0439297b
HK		 3711
3712 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3713 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
3714 else
3715 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3716
f1bce4ad
HK		 3717 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3718 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3719 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3720 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3721 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
0439297b 3722 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
f24f7b2f
CL		 3723 if (tp->mac_version == RTL_GIGA_MAC_VER_70 ||
3724 tp->mac_version == RTL_GIGA_MAC_VER_80)
3907f1ff
HK		 3725 r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000);
3726 else
3727 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
f1bce4ad 3728 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
0439297b 3729 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
f1bce4ad 3730 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
0439297b 3731
f1bce4ad
HK		 3732 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3733 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3734 udelay(1);
3735 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3736 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3737
3738 r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3739
d6836ef0 3740 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
f1bce4ad 3741
3907f1ff 3742 if (tp->mac_version == RTL_GIGA_MAC_VER_61)
0439297b 3743 rtl8125a_config_eee_mac(tp);
3907f1ff
HK		 3744 else
3745 rtl8125b_config_eee_mac(tp);
b3a42e3a 3746
3406079b 3747 rtl_disable_rxdvgate(tp);
f1bce4ad
HK		 3748}
3749
4640338c 3750static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
f1bce4ad 3751{
4640338c 3752 static const struct ephy_info e_info_8125a_2[] = {
f1bce4ad
HK		 3753 { 0x04, 0xffff, 0xd000 },
3754 { 0x0a, 0xffff, 0x8653 },
3755 { 0x23, 0xffff, 0xab66 },
3756 { 0x20, 0xffff, 0x9455 },
3757 { 0x21, 0xffff, 0x99ff },
3758 { 0x29, 0xffff, 0xfe04 },
3759
3760 { 0x44, 0xffff, 0xd000 },
3761 { 0x4a, 0xffff, 0x8653 },
3762 { 0x63, 0xffff, 0xab66 },
3763 { 0x60, 0xffff, 0x9455 },
3764 { 0x61, 0xffff, 0x99ff },
3765 { 0x69, 0xffff, 0xfe04 },
3766 };
3767
3768 rtl_set_def_aspm_entry_latency(tp);
4640338c 3769 rtl_ephy_init(tp, e_info_8125a_2);
f1bce4ad
HK		 3770 rtl_hw_start_8125_common(tp);
3771}
3772
0439297b
HK		 3773static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3774{
3775 static const struct ephy_info e_info_8125b[] = {
3776 { 0x0b, 0xffff, 0xa908 },
3777 { 0x1e, 0xffff, 0x20eb },
3778 { 0x4b, 0xffff, 0xa908 },
3779 { 0x5e, 0xffff, 0x20eb },
3780 { 0x22, 0x0030, 0x0020 },
3781 { 0x62, 0x0030, 0x0020 },
3782 };
3783
3784 rtl_set_def_aspm_entry_latency(tp);
0439297b
HK		 3785 rtl_ephy_init(tp, e_info_8125b);
3786 rtl_hw_start_8125_common(tp);
0439297b
HK		 3787}
3788
f75d1fbe
HK		 3789static void rtl_hw_start_8125d(struct rtl8169_private *tp)
3790{
3791 rtl_set_def_aspm_entry_latency(tp);
3792 rtl_hw_start_8125_common(tp);
3793}
3794
3907f1ff
HK		 3795static void rtl_hw_start_8126a(struct rtl8169_private *tp)
3796{
b48688ea 3797 rtl_disable_zrxdc_timeout(tp);
3907f1ff
HK		 3798 rtl_set_def_aspm_entry_latency(tp);
3799 rtl_hw_start_8125_common(tp);
3800}
3801
f24f7b2f
CL		 3802static void rtl_hw_start_8127a(struct rtl8169_private *tp)
3803{
3804 rtl_set_def_aspm_entry_latency(tp);
3805 rtl_hw_start_8125_common(tp);
3806}
3807
8344ffff
HK		 3808static void rtl_hw_config(struct rtl8169_private *tp)
3809{
3810 static const rtl_generic_fct hw_configs[] = {
3811 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3812 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3813 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3814 [RTL_GIGA_MAC_VER_10] = NULL,
cdafdc29 3815 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401,
94b5ff74 3816 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
8344ffff
HK		 3817 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3818 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3819 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
96ef6928 3820 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2,
8344ffff
HK		 3821 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3822 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3823 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3824 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3825 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
8344ffff
HK		 3826 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3827 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3828 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
0a413e6b 3829 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
8344ffff
HK		 3830 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3831 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3832 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3833 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3834 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3835 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3836 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3837 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3838 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
8344ffff
HK		 3839 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3840 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3841 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
8344ffff 3842 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
8344ffff 3843 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
8344ffff 3844 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
1287723a 3845 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
4640338c 3846 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
0439297b 3847 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
f75d1fbe 3848 [RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d,
b11bff90 3849 [RTL_GIGA_MAC_VER_66] = rtl_hw_start_8125d,
b299ea00 3850 [RTL_GIGA_MAC_VER_70] = rtl_hw_start_8126a,
f24f7b2f 3851 [RTL_GIGA_MAC_VER_80] = rtl_hw_start_8127a,
8344ffff
HK		 3852 };
3853
3854 if (hw_configs[tp->mac_version])
3855 hw_configs[tp->mac_version](tp);
3856}
3857
f1bce4ad
HK		 3858static void rtl_hw_start_8125(struct rtl8169_private *tp)
3859{
3860 int i;
3861
3907f1ff
HK		 3862 RTL_W8(tp, INT_CFG0_8125, 0x00);
3863
f1bce4ad 3864 /* disable interrupt coalescing */
3907f1ff
HK		 3865 switch (tp->mac_version) {
3866 case RTL_GIGA_MAC_VER_61:
f75d1fbe 3867 case RTL_GIGA_MAC_VER_64:
b11bff90 3868 case RTL_GIGA_MAC_VER_66:
f24f7b2f 3869 case RTL_GIGA_MAC_VER_80:
3907f1ff
HK		 3870 for (i = 0xa00; i < 0xb00; i += 4)
3871 RTL_W32(tp, i, 0);
f24f7b2f
CL		 3872 if (tp->mac_version == RTL_GIGA_MAC_VER_80)
3873 RTL_W16(tp, INT_CFG1_8125, 0x0000);
3907f1ff
HK		 3874 break;
3875 case RTL_GIGA_MAC_VER_63:
b299ea00 3876 case RTL_GIGA_MAC_VER_70:
3907f1ff
HK		 3877 for (i = 0xa00; i < 0xa80; i += 4)
3878 RTL_W32(tp, i, 0);
3879 RTL_W16(tp, INT_CFG1_8125, 0x0000);
3880 break;
3881 default:
3882 break;
3883 }
f1bce4ad 3884
e3fc5139
HK		 3885 /* enable extended tally counter */
3886 r8168_mac_ocp_modify(tp, 0xea84, 0, BIT(1) | BIT(0));
3887
f1bce4ad
HK		 3888 rtl_hw_config(tp);
3889}
3890
8344ffff 3891static void rtl_hw_start_8168(struct rtl8169_private *tp)
07ce4064 3892{
272b2265
HK		 3893 if (rtl_is_8168evl_up(tp))
3894 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3895 else
3896 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
1a964649 3897
8344ffff 3898 rtl_hw_config(tp);
bcf2b868
HK		 3899
3900 /* disable interrupt coalescing */
3901 RTL_W16(tp, IntrMitigate, 0x0000);
1da177e4
LT		 3902}
3903
6c19156e
HK		 3904static void rtl_hw_start_8169(struct rtl8169_private *tp)
3905{
6c19156e
HK		 3906 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3907
3908 tp->cp_cmd |= PCIMulRW;
3909
3910 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
09e65335
HK		 3911 tp->mac_version == RTL_GIGA_MAC_VER_03)
3912 tp->cp_cmd |= EnAnaPLL;
6c19156e
HK		 3913
3914 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3915
ef891284 3916 rtl8169_set_magic_reg(tp);
6c19156e 3917
bcf2b868
HK		 3918 /* disable interrupt coalescing */
3919 RTL_W16(tp, IntrMitigate, 0x0000);
6c19156e
HK		 3920}
3921
3922static void rtl_hw_start(struct rtl8169_private *tp)
3923{
3924 rtl_unlock_config_regs(tp);
5fc3f6c9
HK		 3925 /* disable aspm and clock request before ephy access */
3926 rtl_hw_aspm_clkreq_enable(tp, false);
6c19156e
HK		 3927 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3928
2ce30993
HK		 3929 rtl_set_eee_txidle_timer(tp);
3930
6c19156e
HK		 3931 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3932 rtl_hw_start_8169(tp);
f1bce4ad
HK		 3933 else if (rtl_is_8125(tp))
3934 rtl_hw_start_8125(tp);
6c19156e
HK		 3935 else
3936 rtl_hw_start_8168(tp);
3937
4b33433e 3938 rtl_enable_exit_l1(tp);
5fc3f6c9 3939 rtl_hw_aspm_clkreq_enable(tp, true);
6c19156e
HK		 3940 rtl_set_rx_max_size(tp);
3941 rtl_set_rx_tx_desc_registers(tp);
3942 rtl_lock_config_regs(tp);
3943
9db0ac57 3944 rtl_jumbo_config(tp);
4ebcb113 3945
6c19156e 3946 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
711463f8
HK		 3947 rtl_pci_commit(tp);
3948
6c19156e
HK		 3949 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3950 rtl_init_rxcfg(tp);
3951 rtl_set_tx_config_registers(tp);
10478283 3952 rtl_set_rx_config_features(tp, tp->dev->features);
6c19156e 3953 rtl_set_rx_mode(tp->dev);
6c19156e
HK		 3954 rtl_irq_enable(tp);
3955}
3956
1da177e4
LT		 3957static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3958{
d58d46b5
FR		 3959 struct rtl8169_private *tp = netdev_priv(dev);
3960
1eb2cded 3961 WRITE_ONCE(dev->mtu, new_mtu);
350fb32a 3962 netdev_update_features(dev);
9db0ac57 3963 rtl_jumbo_config(tp);
2ce30993 3964 rtl_set_eee_txidle_timer(tp);
0439297b 3965
323bb685 3966 return 0;
1da177e4
LT		 3967}
3968
e2e5fb8d 3969static void rtl8169_mark_to_asic(struct RxDesc *desc)
1da177e4
LT		 3970{
3971 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3972
047521d7 3973 desc->opts2 = 0;
a0750138
AD		 3974 /* Force memory writes to complete before releasing descriptor */
3975 dma_wmb();
e2e5fb8d 3976 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
1da177e4
LT		 3977}
3978
32879f00
HK		 3979static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3980 struct RxDesc *desc)
1da177e4 3981{
1e1205b7 3982 struct device *d = tp_to_dev(tp);
d3b404c2 3983 int node = dev_to_node(d);
32879f00
HK		 3984 dma_addr_t mapping;
3985 struct page *data;
1da177e4 3986
32879f00 3987 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
6f0333b8
ED		 3988 if (!data)
3989 return NULL;
e9f63f30 3990
32879f00 3991 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
d827d86b 3992 if (unlikely(dma_mapping_error(d, mapping))) {
93882c6f 3993 netdev_err(tp->dev, "Failed to map RX DMA!\n");
32879f00
HK		 3994 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
3995 return NULL;
d827d86b 3996 }
1da177e4 3997
d731af78
HK		 3998 desc->addr = cpu_to_le64(mapping);
3999 rtl8169_mark_to_asic(desc);
3eafe507 4000
32879f00 4001 return data;
1da177e4
LT		 4002}
4003
4004static void rtl8169_rx_clear(struct rtl8169_private *tp)
4005{
ed22a8ff 4006 int i;
1da177e4 4007
eb2e7f09
HK		 4008 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
4009 dma_unmap_page(tp_to_dev(tp),
4010 le64_to_cpu(tp->RxDescArray[i].addr),
4011 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
4012 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
4013 tp->Rx_databuff[i] = NULL;
9d3679fe
HK		 4014 tp->RxDescArray[i].addr = 0;
4015 tp->RxDescArray[i].opts1 = 0;
1da177e4
LT		 4016 }
4017}
4018
0ecbe1ca
SG		 4019static int rtl8169_rx_fill(struct rtl8169_private *tp)
4020{
ed22a8ff 4021 int i;
1da177e4 4022
0ecbe1ca 4023 for (i = 0; i < NUM_RX_DESC; i++) {
32879f00 4024 struct page *data;
4ae47c2d 4025
0ecbe1ca 4026 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8 4027 if (!data) {
e4b5c7a5
HK		 4028 rtl8169_rx_clear(tp);
4029 return -ENOMEM;
6f0333b8
ED		 4030 }
4031 tp->Rx_databuff[i] = data;
1da177e4 4032 }
1da177e4 4033
2ac1fa43
HK		 4034 /* mark as last descriptor in the ring */
4035 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
0ecbe1ca 4036
e4b5c7a5 4037 return 0;
1da177e4
LT		 4038}
4039
b1127e64 4040static int rtl8169_init_ring(struct rtl8169_private *tp)
1da177e4 4041{
1da177e4
LT		 4042 rtl8169_init_ring_indexes(tp);
4043
b1127e64
HK		 4044 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
4045 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
1da177e4 4046
0ecbe1ca 4047 return rtl8169_rx_fill(tp);
1da177e4
LT		 4048}
4049
22d352c5 4050static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
1da177e4 4051{
22d352c5
HK		 4052 struct ring_info *tx_skb = tp->tx_skb + entry;
4053 struct TxDesc *desc = tp->TxDescArray + entry;
1da177e4 4054
22d352c5
HK		 4055 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
4056 DMA_TO_DEVICE);
6a41f2b2
HK		 4057 memset(desc, 0, sizeof(*desc));
4058 memset(tx_skb, 0, sizeof(*tx_skb));
1da177e4
LT		 4059}
4060
3eafe507
SG		 4061static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4062 unsigned int n)
1da177e4
LT		 4063{
4064 unsigned int i;
4065
3eafe507
SG		 4066 for (i = 0; i < n; i++) {
4067 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 4068 struct ring_info *tx_skb = tp->tx_skb + entry;
4069 unsigned int len = tx_skb->len;
4070
4071 if (len) {
4072 struct sk_buff *skb = tx_skb->skb;
4073
22d352c5 4074 rtl8169_unmap_tx_skb(tp, entry);
6a41f2b2 4075 if (skb)
7a4b813c 4076 dev_consume_skb_any(skb);
1da177e4
LT		 4077 }
4078 }
3eafe507
SG		 4079}
4080
4081static void rtl8169_tx_clear(struct rtl8169_private *tp)
4082{
4083 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
d92060bc 4084 netdev_reset_queue(tp->dev);
1da177e4
LT		 4085}
4086
bb41c13c 4087static void rtl8169_cleanup(struct rtl8169_private *tp)
bac75d85 4088{
0c28a63a
HK		 4089 napi_disable(&tp->napi);
4090
bac75d85 4091 /* Give a racing hard_start_xmit a few cycles to complete. */
7190aeec 4092 synchronize_net();
bac75d85
HK		 4093
4094 /* Disable interrupts */
4095 rtl8169_irq_mask_and_ack(tp);
4096
4097 rtl_rx_close(tp);
4098
4099 switch (tp->mac_version) {
bac75d85
HK		 4100 case RTL_GIGA_MAC_VER_28:
4101 case RTL_GIGA_MAC_VER_31:
4102 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
4103 break;
4104 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4105 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4106 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4107 break;
fe733618 4108 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST:
bac75d85
HK		 4109 rtl_enable_rxdvgate(tp);
4110 fsleep(2000);
4111 break;
4112 default:
4113 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4114 fsleep(100);
4115 break;
4116 }
4117
4118 rtl_hw_reset(tp);
bb41c13c 4119
bac75d85
HK		 4120 rtl8169_tx_clear(tp);
4121 rtl8169_init_ring_indexes(tp);
4122}
4123
4422bcd4 4124static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 4125{
56de414c 4126 int i;
1da177e4 4127
476c4f5d 4128 netif_stop_queue(tp->dev);
1da177e4 4129
bb41c13c 4130 rtl8169_cleanup(tp);
c7c2c39b 4131
56de414c 4132 for (i = 0; i < NUM_RX_DESC; i++)
1d0254dd 4133 rtl8169_mark_to_asic(tp->RxDescArray + i);
56de414c 4134
da78dbff 4135 napi_enable(&tp->napi);
61cb532d 4136 rtl_hw_start(tp);
1da177e4
LT		 4137}
4138
0290bd29 4139static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
1da177e4 4140{
da78dbff
FR		 4141 struct rtl8169_private *tp = netdev_priv(dev);
4142
80c0576e 4143 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT);
1da177e4
LT		 4144}
4145
b8447abc
HK		 4146static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
4147 void *addr, unsigned int entry, bool desc_own)
734c1409 4148{
b8447abc
HK		 4149 struct TxDesc *txd = tp->TxDescArray + entry;
4150 struct device *d = tp_to_dev(tp);
4151 dma_addr_t mapping;
4152 u32 opts1;
4153 int ret;
4154
4155 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4156 ret = dma_mapping_error(d, mapping);
4157 if (unlikely(ret)) {
4158 if (net_ratelimit())
93882c6f 4159 netdev_err(tp->dev, "Failed to map TX data!\n");
b8447abc
HK		 4160 return ret;
4161 }
4162
4163 txd->addr = cpu_to_le64(mapping);
4164 txd->opts2 = cpu_to_le32(opts[1]);
734c1409 4165
b8447abc 4166 opts1 = opts[0] | len;
734c1409 4167 if (entry == NUM_TX_DESC - 1)
b8447abc
HK		 4168 opts1 |= RingEnd;
4169 if (desc_own)
4170 opts1 |= DescOwn;
4171 txd->opts1 = cpu_to_le32(opts1);
734c1409 4172
b8447abc
HK		 4173 tp->tx_skb[entry].len = len;
4174
4175 return 0;
734c1409
HK		 4176}
4177
1da177e4 4178static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
b8447abc 4179 const u32 *opts, unsigned int entry)
1da177e4
LT		 4180{
4181 struct skb_shared_info *info = skb_shinfo(skb);
b8447abc 4182 unsigned int cur_frag;
1da177e4 4183
1da177e4 4184 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 4185 const skb_frag_t *frag = info->frags + cur_frag;
b8447abc
HK		 4186 void *addr = skb_frag_address(frag);
4187 u32 len = skb_frag_size(frag);
1da177e4
LT		 4188
4189 entry = (entry + 1) % NUM_TX_DESC;
4190
b8447abc 4191 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
3eafe507 4192 goto err_out;
1da177e4
LT		 4193 }
4194
9020845f 4195 return 0;
3eafe507
SG		 4196
4197err_out:
4198 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4199 return -EIO;
1da177e4
LT		 4200}
4201
8d520b4d
HK		 4202static bool rtl_skb_is_udp(struct sk_buff *skb)
4203{
4204 int no = skb_network_offset(skb);
4205 struct ipv6hdr *i6h, _i6h;
4206 struct iphdr *ih, _ih;
4207
4208 switch (vlan_get_protocol(skb)) {
4209 case htons(ETH_P_IP):
4210 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih);
4211 return ih && ih->protocol == IPPROTO_UDP;
4212 case htons(ETH_P_IPV6):
4213 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h);
4214 return i6h && i6h->nexthdr == IPPROTO_UDP;
4215 default:
4216 return false;
4217 }
4218}
4219
4220#define RTL_MIN_PATCH_LEN 47
4221
4222/* see rtl8125_get_patch_pad_len() in r8125 vendor driver */
4223static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp,
4224 struct sk_buff *skb)
b423e9ae 4225{
8d520b4d
HK		 4226 unsigned int padto = 0, len = skb->len;
4227
87e26448
HK		 4228 if (len < 128 + RTL_MIN_PATCH_LEN && rtl_skb_is_udp(skb) &&
4229 skb_transport_header_was_set(skb)) {
8d520b4d
HK		 4230 unsigned int trans_data_len = skb_tail_pointer(skb) -
4231 skb_transport_header(skb);
4232
4233 if (trans_data_len >= offsetof(struct udphdr, len) &&
4234 trans_data_len < RTL_MIN_PATCH_LEN) {
4235 u16 dest = ntohs(udp_hdr(skb)->dest);
4236
4237 /* dest is a standard PTP port */
4238 if (dest == 319 || dest == 320)
4239 padto = len + RTL_MIN_PATCH_LEN - trans_data_len;
4240 }
4241
4242 if (trans_data_len < sizeof(struct udphdr))
4243 padto = max_t(unsigned int, padto,
4244 len + sizeof(struct udphdr) - trans_data_len);
4245 }
4246
4247 return padto;
4248}
4249
4250static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,
4251 struct sk_buff *skb)
4252{
87e26448 4253 unsigned int padto = 0;
8d520b4d 4254
87e26448
HK		 4255 switch (tp->mac_version) {
4256 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
4257 padto = rtl8125_quirk_udp_padto(tp, skb);
4258 break;
4259 default:
4260 break;
4261 }
8d520b4d 4262
2aaf09a0
HK		 4263 switch (tp->mac_version) {
4264 case RTL_GIGA_MAC_VER_34:
fe733618 4265 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST:
8d520b4d 4266 padto = max_t(unsigned int, padto, ETH_ZLEN);
ffb35c67 4267 break;
2aaf09a0 4268 default:
8d520b4d 4269 break;
2aaf09a0 4270 }
8d520b4d
HK		 4271
4272 return padto;
b423e9ae 4273}
4274
87945b6d 4275static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
1da177e4 4276{
350fb32a
MM		 4277 u32 mss = skb_shinfo(skb)->gso_size;
4278
2b7b4318
FR		 4279 if (mss) {
4280 opts[0] |= TD_LSO;
4abc3c04 4281 opts[0] |= mss << TD0_MSS_SHIFT;
5888d3fc 4282 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4283 const struct iphdr *ip = ip_hdr(skb);
4284
4285 if (ip->protocol == IPPROTO_TCP)
4286 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4287 else if (ip->protocol == IPPROTO_UDP)
4288 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4289 else
4290 WARN_ON_ONCE(1);
4291 }
5888d3fc 4292}
4293
4294static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4295 struct sk_buff *skb, u32 *opts)
4296{
0623b98b
HK		 4297 struct skb_shared_info *shinfo = skb_shinfo(skb);
4298 u32 mss = shinfo->gso_size;
5888d3fc 4299
4300 if (mss) {
0623b98b 4301 if (shinfo->gso_type & SKB_GSO_TCPV4) {
e974604b 4302 opts[0] |= TD1_GTSENV4;
0623b98b 4303 } else if (shinfo->gso_type & SKB_GSO_TCPV6) {
8b19c68c 4304 if (skb_cow_head(skb, 0))
e974604b 4305 return false;
4306
8b19c68c 4307 tcp_v6_gso_csum_prep(skb);
e974604b 4308 opts[0] |= TD1_GTSENV6;
0623b98b 4309 } else {
e974604b 4310 WARN_ON_ONCE(1);
e974604b 4311 }
4312
faa4e04e 4313 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT;
4abc3c04 4314 opts[1] |= mss << TD1_MSS_SHIFT;
2b7b4318 4315 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
e974604b 4316 u8 ip_protocol;
1da177e4 4317
4ff36466 4318 switch (vlan_get_protocol(skb)) {
e974604b 4319 case htons(ETH_P_IP):
4320 opts[1] |= TD1_IPv4_CS;
4321 ip_protocol = ip_hdr(skb)->protocol;
4322 break;
4323
4324 case htons(ETH_P_IPV6):
4325 opts[1] |= TD1_IPv6_CS;
4326 ip_protocol = ipv6_hdr(skb)->nexthdr;
4327 break;
4328
4329 default:
4330 ip_protocol = IPPROTO_RAW;
4331 break;
4332 }
4333
4334 if (ip_protocol == IPPROTO_TCP)
4335 opts[1] |= TD1_TCP_CS;
4336 else if (ip_protocol == IPPROTO_UDP)
4337 opts[1] |= TD1_UDP_CS;
2b7b4318
FR		 4338 else
4339 WARN_ON_ONCE(1);
e974604b 4340
faa4e04e 4341 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT;
b423e9ae 4342 } else {
8d520b4d
HK		 4343 unsigned int padto = rtl_quirk_packet_padto(tp, skb);
4344
4345 /* skb_padto would free the skb on error */
4346 return !__skb_put_padto(skb, padto, false);
1da177e4 4347 }
5888d3fc 4348
b423e9ae 4349 return true;
1da177e4
LT		 4350}
4351
8624e9bb 4352static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp)
76085c9e 4353{
8624e9bb 4354 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx);
76085c9e
HK		 4355}
4356
87945b6d
HK		 4357/* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
4358static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4359{
4360 switch (tp->mac_version) {
4361 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4362 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4363 return false;
4364 default:
4365 return true;
4366 }
4367}
4368
f1bce4ad
HK		 4369static void rtl8169_doorbell(struct rtl8169_private *tp)
4370{
4371 if (rtl_is_8125(tp))
4372 RTL_W16(tp, TxPoll_8125, BIT(0));
4373 else
4374 RTL_W8(tp, TxPoll, NPQ);
4375}
4376
61357325
SH		 4377static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4378 struct net_device *dev)
1da177e4
LT		 4379{
4380 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 4381 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
b8447abc
HK		 4382 struct TxDesc *txd_first, *txd_last;
4383 bool stop_queue, door_bell;
c71e3a5c 4384 unsigned int frags;
b8447abc
HK		 4385 u32 opts[2];
4386
83c317d7 4387 if (unlikely(!rtl_tx_slots_avail(tp))) {
93882c6f
HK		 4388 if (net_ratelimit())
4389 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
d516b187
HK		 4390 netif_stop_queue(dev);
4391 return NETDEV_TX_BUSY;
1da177e4
LT		 4392 }
4393
355f948a 4394 opts[1] = rtl8169_tx_vlan_tag(skb);
b8447abc 4395 opts[0] = 0;
b423e9ae 4396
b8447abc 4397 if (!rtl_chip_supports_csum_v2(tp))
87945b6d 4398 rtl8169_tso_csum_v1(skb, opts);
b8447abc 4399 else if (!rtl8169_tso_csum_v2(tp, skb, opts))
3eafe507
SG		 4400 goto err_dma_0;
4401
b8447abc
HK		 4402 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4403 entry, false)))
4404 goto err_dma_0;
1da177e4 4405
bd4bdeb4
HK		 4406 txd_first = tp->TxDescArray + entry;
4407
c71e3a5c 4408 frags = skb_shinfo(skb)->nr_frags;
b8447abc
HK		 4409 if (frags) {
4410 if (rtl8169_xmit_frags(tp, skb, opts, entry))
9020845f 4411 goto err_dma_1;
b8447abc 4412 entry = (entry + frags) % NUM_TX_DESC;
1da177e4
LT		 4413 }
4414
b8447abc
HK		 4415 txd_last = tp->TxDescArray + entry;
4416 txd_last->opts1 |= cpu_to_le32(LastFrag);
4417 tp->tx_skb[entry].skb = skb;
2b7b4318 4418
5047fb5d
RC		 4419 skb_tx_timestamp(skb);
4420
a0750138
AD		 4421 /* Force memory writes to complete before releasing descriptor */
4422 dma_wmb();
1da177e4 4423
ef143585
HK		 4424 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
4425
b8447abc 4426 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
1da177e4 4427
794867ee
HK		 4428 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4429 smp_wmb();
1da177e4 4430
41294e6a 4431 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1);
a0750138 4432
8624e9bb
HK		 4433 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp),
4434 R8169_TX_STOP_THRS,
4435 R8169_TX_START_THRS);
4436 if (door_bell || stop_queue)
41294e6a
HK		 4437 rtl8169_doorbell(tp);
4438
61357325 4439 return NETDEV_TX_OK;
1da177e4 4440
3eafe507 4441err_dma_1:
22d352c5 4442 rtl8169_unmap_tx_skb(tp, entry);
3eafe507 4443err_dma_0:
989c9ba1 4444 dev_kfree_skb_any(skb);
3eafe507
SG		 4445 dev->stats.tx_dropped++;
4446 return NETDEV_TX_OK;
1da177e4
LT		 4447}
4448
773235f4
HK		 4449static unsigned int rtl_last_frag_len(struct sk_buff *skb)
4450{
4451 struct skb_shared_info *info = skb_shinfo(skb);
4452 unsigned int nr_frags = info->nr_frags;
4453
4454 if (!nr_frags)
4455 return UINT_MAX;
4456
4457 return skb_frag_size(info->frags + nr_frags - 1);
4458}
4459
4460/* Workaround for hw issues with TSO on RTL8168evl */
4461static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
4462 netdev_features_t features)
4463{
4464 /* IPv4 header has options field */
4465 if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
4466 ip_hdrlen(skb) > sizeof(struct iphdr))
4467 features &= ~NETIF_F_ALL_TSO;
4468
4469 /* IPv4 TCP header has options field */
4470 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
4471 tcp_hdrlen(skb) > sizeof(struct tcphdr))
4472 features &= ~NETIF_F_ALL_TSO;
4473
4474 else if (rtl_last_frag_len(skb) <= 6)
4475 features &= ~NETIF_F_ALL_TSO;
4476
4477 return features;
4478}
4479
e64e0c89
HK		 4480static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4481 struct net_device *dev,
4482 netdev_features_t features)
4483{
e64e0c89
HK		 4484 struct rtl8169_private *tp = netdev_priv(dev);
4485
4486 if (skb_is_gso(skb)) {
773235f4
HK		 4487 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4488 features = rtl8168evl_fix_tso(skb, features);
4489
faa4e04e 4490 if (skb_transport_offset(skb) > GTTCPHO_MAX &&
e64e0c89
HK		 4491 rtl_chip_supports_csum_v2(tp))
4492 features &= ~NETIF_F_ALL_TSO;
4493 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
847f0a2b
HK		 4494 /* work around hw bug on some chip versions */
4495 if (skb->len < ETH_ZLEN)
4496 features &= ~NETIF_F_CSUM_MASK;
e64e0c89 4497
8d520b4d
HK		 4498 if (rtl_quirk_packet_padto(tp, skb))
4499 features &= ~NETIF_F_CSUM_MASK;
e64e0c89 4500
faa4e04e 4501 if (skb_transport_offset(skb) > TCPHO_MAX &&
e64e0c89
HK		 4502 rtl_chip_supports_csum_v2(tp))
4503 features &= ~NETIF_F_CSUM_MASK;
4504 }
4505
4506 return vlan_features_check(skb, features);
4507}
4508
1da177e4
LT		 4509static void rtl8169_pcierr_interrupt(struct net_device *dev)
4510{
4511 struct rtl8169_private *tp = netdev_priv(dev);
4512 struct pci_dev *pdev = tp->pci_dev;
2864a883
HK		 4513 int pci_status_errs;
4514 u16 pci_cmd;
1da177e4
LT		 4515
4516 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1da177e4 4517
2864a883
HK		 4518 pci_status_errs = pci_status_get_and_clear_errors(pdev);
4519
93882c6f
HK		 4520 if (net_ratelimit())
4521 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4522 pci_cmd, pci_status_errs);
1da177e4 4523
98ddf986 4524 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 4525}
4526
5317d5c6
HK		 4527static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4528 int budget)
1da177e4 4529{
ca1ab89c 4530 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0;
94d8a98e 4531 struct sk_buff *skb;
1da177e4 4532
1da177e4 4533 dirty_tx = tp->dirty_tx;
1da177e4 4534
ca1ab89c 4535 while (READ_ONCE(tp->cur_tx) != dirty_tx) {
1da177e4 4536 unsigned int entry = dirty_tx % NUM_TX_DESC;
1da177e4
LT		 4537 u32 status;
4538
dcf75a0f 4539 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1));
1da177e4
LT		 4540 if (status & DescOwn)
4541 break;
4542
94d8a98e 4543 skb = tp->tx_skb[entry].skb;
22d352c5
HK		 4544 rtl8169_unmap_tx_skb(tp, entry);
4545
6a41f2b2 4546 if (skb) {
d92060bc 4547 pkts_compl++;
6a41f2b2
HK		 4548 bytes_compl += skb->len;
4549 napi_consume_skb(skb, budget);
1da177e4
LT		 4550 }
4551 dirty_tx++;
1da177e4
LT		 4552 }
4553
4554 if (tp->dirty_tx != dirty_tx) {
5e4cb480 4555 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl);
1a31ae00 4556 WRITE_ONCE(tp->dirty_tx, dirty_tx);
d92060bc 4557
1a31ae00
HK		 4558 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl,
4559 rtl_tx_slots_avail(tp),
4560 R8169_TX_START_THRS);
d78ae2dc
FR		 4561 /*
4562 * 8168 hack: TxPoll requests are lost when the Tx packets are
4563 * too close. Let's kick an extra TxPoll request when a burst
4564 * of start_xmit activity is detected (if it is not detected,
4565 * it is slow enough). -- FR
94d8a98e
HK		 4566 * If skb is NULL then we come here again once a tx irq is
4567 * triggered after the last fragment is marked transmitted.
d78ae2dc 4568 */
c1c0ce31 4569 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb)
f1bce4ad 4570 rtl8169_doorbell(tp);
1da177e4
LT		 4571 }
4572}
4573
126fa4b9
FR		 4574static inline int rtl8169_fragmented_frame(u32 status)
4575{
4576 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4577}
4578
adea1ac7 4579static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 4580{
206a75e0 4581 u32 status = opts1 & (RxProtoMask | RxCSFailMask);
1da177e4 4582
206a75e0 4583 if (status == RxProtoTCP || status == RxProtoUDP)
1da177e4
LT		 4584 skb->ip_summed = CHECKSUM_UNNECESSARY;
4585 else
bc8acf2c 4586 skb_checksum_none_assert(skb);
1da177e4
LT		 4587}
4588
2f53e9d7 4589static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget)
1da177e4 4590{
588c7e5c 4591 struct device *d = tp_to_dev(tp);
2f53e9d7 4592 int count;
1da177e4 4593
2f53e9d7
HK		 4594 for (count = 0; count < budget; count++, tp->cur_rx++) {
4595 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC;
126fa4b9 4596 struct RxDesc *desc = tp->RxDescArray + entry;
588c7e5c
HK		 4597 struct sk_buff *skb;
4598 const void *rx_buf;
4599 dma_addr_t addr;
1da177e4
LT		 4600 u32 status;
4601
f97eee48 4602 status = le32_to_cpu(READ_ONCE(desc->opts1));
1da177e4
LT		 4603 if (status & DescOwn)
4604 break;
a0750138
AD		 4605
4606 /* This barrier is needed to keep us from reading
4607 * any other fields out of the Rx descriptor until
4608 * we know the status of DescOwn
4609 */
4610 dma_rmb();
4611
4dcb7d33 4612 if (unlikely(status & RxRES)) {
93882c6f
HK		 4613 if (net_ratelimit())
4614 netdev_warn(dev, "Rx ERROR. status = %08x\n",
4615 status);
cebf8cc7 4616 dev->stats.rx_errors++;
1da177e4 4617 if (status & (RxRWT | RxRUNT))
cebf8cc7 4618 dev->stats.rx_length_errors++;
1da177e4 4619 if (status & RxCRC)
cebf8cc7 4620 dev->stats.rx_crc_errors++;
126fa4b9 4621
588c7e5c 4622 if (!(dev->features & NETIF_F_RXALL))
ce11ff5e 4623 goto release_descriptor;
588c7e5c
HK		 4624 else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
4625 goto release_descriptor;
4626 }
1da177e4 4627
588c7e5c
HK		 4628 pkt_size = status & GENMASK(13, 0);
4629 if (likely(!(dev->features & NETIF_F_RXFCS)))
4630 pkt_size -= ETH_FCS_LEN;
fcd4e608 4631
588c7e5c
HK		 4632 /* The driver does not support incoming fragmented frames.
4633 * They are seen as a symptom of over-mtu sized frames.
4634 */
4635 if (unlikely(rtl8169_fragmented_frame(status))) {
4636 dev->stats.rx_dropped++;
4637 dev->stats.rx_length_errors++;
4638 goto release_descriptor;
4639 }
d4ed7463 4640
588c7e5c
HK		 4641 skb = napi_alloc_skb(&tp->napi, pkt_size);
4642 if (unlikely(!skb)) {
4643 dev->stats.rx_dropped++;
4644 goto release_descriptor;
4645 }
1da177e4 4646
588c7e5c
HK		 4647 addr = le64_to_cpu(desc->addr);
4648 rx_buf = page_address(tp->Rx_databuff[entry]);
7a8fc77b 4649
588c7e5c
HK		 4650 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4651 prefetch(rx_buf);
4652 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
4653 skb->tail += pkt_size;
4654 skb->len = pkt_size;
4655 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
39174291 4656
588c7e5c
HK		 4657 rtl8169_rx_csum(skb, status);
4658 skb->protocol = eth_type_trans(skb, dev);
4659
4660 rtl8169_rx_vlan_tag(desc, skb);
4661
4662 if (skb->pkt_type == PACKET_MULTICAST)
4663 dev->stats.multicast++;
4664
4665 napi_gro_receive(&tp->napi, skb);
4666
5e4cb480 4667 dev_sw_netstats_rx_add(dev, pkt_size);
ce11ff5e 4668release_descriptor:
1d0254dd 4669 rtl8169_mark_to_asic(desc);
1da177e4
LT		 4670 }
4671
1da177e4
LT		 4672 return count;
4673}
4674
07d3f51f 4675static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 4676{
ebcd5daa 4677 struct rtl8169_private *tp = dev_instance;
c1d532d2 4678 u32 status = rtl_get_events(tp);
1da177e4 4679
9e89d719 4680 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
05bbe558 4681 return IRQ_NONE;
1da177e4 4682
10ce0db7
HK		 4683 /* At least RTL8168fp may unexpectedly set the SYSErr bit */
4684 if (unlikely(status & SYSErr &&
4685 tp->mac_version <= RTL_GIGA_MAC_VER_06)) {
38caff5a
HK		 4686 rtl8169_pcierr_interrupt(tp->dev);
4687 goto out;
4688 }
da78dbff 4689
703732f0
HK		 4690 if (status & LinkChg)
4691 phy_mac_interrupt(tp->phydev);
1da177e4 4692
eabb8a9b
HK		 4693 rtl_irq_disable(tp);
4694 napi_schedule(&tp->napi);
38caff5a
HK		 4695out:
4696 rtl_ack_events(tp, status);
1da177e4 4697
38caff5a 4698 return IRQ_HANDLED;
1da177e4
LT		 4699}
4700
4422bcd4
FR		 4701static void rtl_task(struct work_struct *work)
4702{
4703 struct rtl8169_private *tp =
4704 container_of(work, struct rtl8169_private, wk.work);
80c0576e 4705 int ret;
da78dbff 4706
80c0576e 4707 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) {
ce870af3
HK		 4708 /* if chip isn't accessible, reset bus to revive it */
4709 if (RTL_R32(tp, TxConfig) == ~0) {
4710 ret = pci_reset_bus(tp->pci_dev);
4711 if (ret < 0) {
4712 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n");
4713 netif_device_detach(tp->dev);
ac484303 4714 return;
ce870af3
HK		 4715 }
4716 }
4717
80c0576e
HK		 4718 /* ASPM compatibility issues are a typical reason for tx timeouts */
4719 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 |
4720 PCIE_LINK_STATE_L0S);
4721 if (!ret)
4722 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n");
4723 goto reset;
4724 }
4725
476c4f5d 4726 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
80c0576e 4727reset:
e18958c6 4728 rtl_reset_work(tp);
476c4f5d
HK		 4729 netif_wake_queue(tp->dev);
4730 }
4422bcd4
FR		 4731}
4732
bea3348e 4733static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 4734{
bea3348e
SH		 4735 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4736 struct net_device *dev = tp->dev;
6b839b6c 4737 int work_done;
da78dbff 4738
5317d5c6 4739 rtl_tx(dev, tp, budget);
1da177e4 4740
9fbb4a7a
HK		 4741 work_done = rtl_rx(dev, tp, budget);
4742
e31a9fed 4743 if (work_done < budget && napi_complete_done(napi, work_done))
fe716f8a 4744 rtl_irq_enable(tp);
1da177e4 4745
bea3348e 4746 return work_done;
1da177e4 4747}
1da177e4 4748
f1e911d5
HK		 4749static void r8169_phylink_handler(struct net_device *ndev)
4750{
4751 struct rtl8169_private *tp = netdev_priv(ndev);
4b6c6065 4752 struct device *d = tp_to_dev(tp);
f1e911d5
HK		 4753
4754 if (netif_carrier_ok(ndev)) {
4755 rtl_link_chg_patch(tp);
4b6c6065 4756 pm_request_resume(d);
f1e911d5 4757 } else {
4b6c6065 4758 pm_runtime_idle(d);
f1e911d5
HK		 4759 }
4760
96efd6d0 4761 phy_print_status(tp->phydev);
f1e911d5
HK		 4762}
4763
4764static int r8169_phy_connect(struct rtl8169_private *tp)
4765{
703732f0 4766 struct phy_device *phydev = tp->phydev;
f1e911d5
HK		 4767 phy_interface_t phy_mode;
4768 int ret;
4769
f7ffa9ae 4770 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
f1e911d5
HK		 4771 PHY_INTERFACE_MODE_MII;
4772
4773 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4774 phy_mode);
4775 if (ret)
4776 return ret;
4777
66058b1c 4778 if (!tp->supports_gmii)
f1e911d5
HK		 4779 phy_set_max_speed(phydev, SPEED_100);
4780
f1e911d5
HK		 4781 phy_attached_info(phydev);
4782
4783 return 0;
4784}
4785
8ac8e8c6 4786static void rtl8169_down(struct rtl8169_private *tp)
1da177e4 4787{
e2015942 4788 disable_work_sync(&tp->wk.work);
8ac8e8c6
HK		 4789 /* Clear all task flags */
4790 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
f1e911d5 4791
8ac8e8c6 4792 phy_stop(tp->phydev);
1da177e4 4793
a2ee8472
HK		 4794 rtl8169_update_counters(tp);
4795
f658b909
HK		 4796 pci_clear_master(tp->pci_dev);
4797 rtl_pci_commit(tp);
4798
bb41c13c 4799 rtl8169_cleanup(tp);
d192181c 4800 rtl_disable_exit_l1(tp);
7257c977 4801 rtl_prepare_power_down(tp);
868c3b95
CL		 4802
4803 if (tp->dash_type != RTL_DASH_NONE)
4804 rtl8168_driver_stop(tp);
1da177e4
LT		 4805}
4806
567ca57f
HK		 4807static void rtl8169_up(struct rtl8169_private *tp)
4808{
868c3b95
CL		 4809 if (tp->dash_type != RTL_DASH_NONE)
4810 rtl8168_driver_start(tp);
4811
f658b909 4812 pci_set_master(tp->pci_dev);
5c2280fc 4813 phy_init_hw(tp->phydev);
7257c977 4814 phy_resume(tp->phydev);
567ca57f
HK		 4815 rtl8169_init_phy(tp);
4816 napi_enable(&tp->napi);
e2015942 4817 enable_work(&tp->wk.work);
567ca57f
HK		 4818 rtl_reset_work(tp);
4819
4820 phy_start(tp->phydev);
567ca57f
HK		 4821}
4822
1da177e4
LT		 4823static int rtl8169_close(struct net_device *dev)
4824{
4825 struct rtl8169_private *tp = netdev_priv(dev);
4826 struct pci_dev *pdev = tp->pci_dev;
4827
e1759441
RW		 4828 pm_runtime_get_sync(&pdev->dev);
4829
8ac8e8c6
HK		 4830 netif_stop_queue(dev);
4831 rtl8169_down(tp);
4832 rtl8169_rx_clear(tp);
1da177e4 4833
1bd32771 4834 free_irq(tp->irq, tp);
1da177e4 4835
cc9f07a8
HK		 4836 phy_disconnect(tp->phydev);
4837
82553bb6
SG		 4838 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4839 tp->RxPhyAddr);
4840 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4841 tp->TxPhyAddr);
1da177e4
LT		 4842 tp->TxDescArray = NULL;
4843 tp->RxDescArray = NULL;
4844
e1759441
RW		 4845 pm_runtime_put_sync(&pdev->dev);
4846
1da177e4
LT		 4847 return 0;
4848}
4849
dc1c00ce
FR		 4850#ifdef CONFIG_NET_POLL_CONTROLLER
4851static void rtl8169_netpoll(struct net_device *dev)
4852{
4853 struct rtl8169_private *tp = netdev_priv(dev);
4854
1bd32771 4855 rtl8169_interrupt(tp->irq, tp);
dc1c00ce
FR		 4856}
4857#endif
4858
df43ac78
FR		 4859static int rtl_open(struct net_device *dev)
4860{
4861 struct rtl8169_private *tp = netdev_priv(dev);
df43ac78 4862 struct pci_dev *pdev = tp->pci_dev;
870f531e 4863 unsigned long irqflags;
df43ac78
FR		 4864 int retval = -ENOMEM;
4865
4866 pm_runtime_get_sync(&pdev->dev);
4867
4868 /*
e75d6606 4869 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 4870 * dma_alloc_coherent provides more.
4871 */
4872 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4873 &tp->TxPhyAddr, GFP_KERNEL);
4874 if (!tp->TxDescArray)
1c470b53 4875 goto out;
df43ac78
FR		 4876
4877 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4878 &tp->RxPhyAddr, GFP_KERNEL);
4879 if (!tp->RxDescArray)
4880 goto err_free_tx_0;
4881
b1127e64 4882 retval = rtl8169_init_ring(tp);
df43ac78
FR		 4883 if (retval < 0)
4884 goto err_free_rx_1;
4885
df43ac78
FR		 4886 rtl_request_firmware(tp);
4887
870f531e 4888 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED;
1bd32771 4889 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp);
df43ac78
FR		 4890 if (retval < 0)
4891 goto err_release_fw_2;
4892
f1e911d5
HK		 4893 retval = r8169_phy_connect(tp);
4894 if (retval)
4895 goto err_free_irq;
4896
567ca57f 4897 rtl8169_up(tp);
d56f58ce 4898 rtl8169_init_counter_offsets(tp);
df43ac78 4899 netif_start_queue(dev);
df43ac78 4900out:
1c470b53
HK		 4901 pm_runtime_put_sync(&pdev->dev);
4902
df43ac78
FR		 4903 return retval;
4904
f1e911d5 4905err_free_irq:
1bd32771 4906 free_irq(tp->irq, tp);
df43ac78
FR		 4907err_release_fw_2:
4908 rtl_release_firmware(tp);
4909 rtl8169_rx_clear(tp);
4910err_free_rx_1:
4911 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4912 tp->RxPhyAddr);
4913 tp->RxDescArray = NULL;
4914err_free_tx_0:
4915 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4916 tp->TxPhyAddr);
4917 tp->TxDescArray = NULL;
df43ac78
FR		 4918 goto out;
4919}
4920
bc1f4470 4921static void
8027aa24 4922rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 4923{
4924 struct rtl8169_private *tp = netdev_priv(dev);
f09cf4b7 4925 struct pci_dev *pdev = tp->pci_dev;
42020320 4926 struct rtl8169_counters *counters = tp->counters;
1da177e4 4927
f09cf4b7
CHL		 4928 pm_runtime_get_noresume(&pdev->dev);
4929
314a9cbb 4930 netdev_stats_to_stats64(stats, &dev->stats);
5e4cb480 4931 dev_fetch_sw_netstats(stats, dev->tstats);
8027aa24 4932
6e85d5ad 4933 /*
ed72a9bb 4934 * Fetch additional counter values missing in stats collected by driver
6e85d5ad
CV		 4935 * from tally counters.
4936 */
f09cf4b7 4937 if (pm_runtime_active(&pdev->dev))
e71c9ce2 4938 rtl8169_update_counters(tp);
6e85d5ad
CV		 4939
4940 /*
4941 * Subtract values fetched during initalization.
4942 * See rtl8169_init_counter_offsets for a description why we do that.
4943 */
42020320 4944 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6e85d5ad 4945 le64_to_cpu(tp->tc_offset.tx_errors);
42020320 4946 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6e85d5ad 4947 le32_to_cpu(tp->tc_offset.tx_multi_collision);
42020320 4948 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6e85d5ad 4949 le16_to_cpu(tp->tc_offset.tx_aborted);
0da3359a
HK		 4950 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
4951 le16_to_cpu(tp->tc_offset.rx_missed);
6e85d5ad 4952
f09cf4b7 4953 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 4954}
4955
27dc36ae 4956static void rtl8169_net_suspend(struct rtl8169_private *tp)
5d06a99f 4957{
27dc36ae 4958 netif_device_detach(tp->dev);
476c4f5d
HK		 4959
4960 if (netif_running(tp->dev))
4961 rtl8169_down(tp);
861ab440
RW		 4962}
4963
06e56697 4964static int rtl8169_runtime_resume(struct device *dev)
bb13a800 4965{
06e56697
HK		 4966 struct rtl8169_private *tp = dev_get_drvdata(dev);
4967
bb13a800 4968 rtl_rar_set(tp, tp->dev->dev_addr);
06e56697 4969 __rtl8169_set_wol(tp, tp->saved_wolopts);
bb13a800
HK		 4970
4971 if (tp->TxDescArray)
4972 rtl8169_up(tp);
4973
4974 netif_device_attach(tp->dev);
4975
4976 return 0;
4977}
4978
8fe6e670 4979static int rtl8169_suspend(struct device *device)
861ab440 4980{
27dc36ae 4981 struct rtl8169_private *tp = dev_get_drvdata(device);
5d06a99f 4982
abe5fc42 4983 rtnl_lock();
27dc36ae 4984 rtl8169_net_suspend(tp);
bb13a800
HK		 4985 if (!device_may_wakeup(tp_to_dev(tp)))
4986 clk_disable_unprepare(tp->clk);
abe5fc42 4987 rtnl_unlock();
1371fa6d 4988
5d06a99f
FR		 4989 return 0;
4990}
4991
8fe6e670 4992static int rtl8169_resume(struct device *device)
5d06a99f 4993{
27dc36ae 4994 struct rtl8169_private *tp = dev_get_drvdata(device);
ac8bd9e1 4995
bb13a800
HK		 4996 if (!device_may_wakeup(tp_to_dev(tp)))
4997 clk_prepare_enable(tp->clk);
5d06a99f 4998
ef9da46d
HK		 4999 /* Reportedly at least Asus X453MA truncates packets otherwise */
5000 if (tp->mac_version == RTL_GIGA_MAC_VER_37)
5001 rtl_init_rxcfg(tp);
476c4f5d 5002
06e56697 5003 return rtl8169_runtime_resume(device);
e1759441
RW		 5004}
5005
5006static int rtl8169_runtime_suspend(struct device *device)
5007{
27dc36ae 5008 struct rtl8169_private *tp = dev_get_drvdata(device);
e1759441 5009
476c4f5d
HK		 5010 if (!tp->TxDescArray) {
5011 netif_device_detach(tp->dev);
e1759441 5012 return 0;
476c4f5d 5013 }
e1759441 5014
abe5fc42 5015 rtnl_lock();
01bd753d 5016 __rtl8169_set_wol(tp, WAKE_PHY);
27dc36ae 5017 rtl8169_net_suspend(tp);
abe5fc42 5018 rtnl_unlock();
e1759441
RW		 5019
5020 return 0;
5021}
5022
e1759441
RW		 5023static int rtl8169_runtime_idle(struct device *device)
5024{
27dc36ae 5025 struct rtl8169_private *tp = dev_get_drvdata(device);
e1759441 5026
0ab0c45d 5027 if (tp->dash_enabled)
54744510
HK		 5028 return -EBUSY;
5029
27dc36ae 5030 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
a92a0849
HK		 5031 pm_schedule_suspend(device, 10000);
5032
5033 return -EBUSY;
e1759441
RW		 5034}
5035
47145210 5036static const struct dev_pm_ops rtl8169_pm_ops = {
8fe6e670
HK		 5037 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
5038 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
5039 rtl8169_runtime_idle)
861ab440
RW		 5040};
5041
1765f95d
FR		 5042static void rtl_shutdown(struct pci_dev *pdev)
5043{
27dc36ae 5044 struct rtl8169_private *tp = pci_get_drvdata(pdev);
861ab440 5045
abe5fc42 5046 rtnl_lock();
27dc36ae 5047 rtl8169_net_suspend(tp);
abe5fc42 5048 rtnl_unlock();
1765f95d 5049
cecb5fd7 5050 /* Restore original MAC address */
27dc36ae 5051 rtl_rar_set(tp, tp->dev->perm_addr);
cc098dc7 5052
b7ed5d5a
HK		 5053 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled)
5054 pci_prepare_to_sleep(pdev);
861ab440 5055}
5d06a99f 5056
baf63293 5057static void rtl_remove_one(struct pci_dev *pdev)
e27566ed 5058{
27dc36ae 5059 struct rtl8169_private *tp = pci_get_drvdata(pdev);
e27566ed 5060
12b1bc75
HK		 5061 if (pci_dev_run_wake(pdev))
5062 pm_runtime_get_noresume(&pdev->dev);
ad1be8d3 5063
e2015942 5064 disable_work_sync(&tp->wk.work);
91d3d149 5065
97e176fc
HK		 5066 if (IS_ENABLED(CONFIG_R8169_LEDS))
5067 r8169_remove_leds(tp->leds);
19fa4f2a 5068
27dc36ae 5069 unregister_netdev(tp->dev);
e27566ed 5070
e0d38b58 5071 if (tp->dash_type != RTL_DASH_NONE)
12b1bc75 5072 rtl8168_driver_stop(tp);
e27566ed 5073
12b1bc75 5074 rtl_release_firmware(tp);
e27566ed
FR		 5075
5076 /* restore original MAC address */
27dc36ae 5077 rtl_rar_set(tp, tp->dev->perm_addr);
e27566ed
FR		 5078}
5079
fa9c385e 5080static const struct net_device_ops rtl_netdev_ops = {
df43ac78 5081 .ndo_open = rtl_open,
fa9c385e
FR		 5082 .ndo_stop = rtl8169_close,
5083 .ndo_get_stats64 = rtl8169_get_stats64,
5084 .ndo_start_xmit = rtl8169_start_xmit,
e64e0c89 5085 .ndo_features_check = rtl8169_features_check,
fa9c385e
FR		 5086 .ndo_tx_timeout = rtl8169_tx_timeout,
5087 .ndo_validate_addr = eth_validate_addr,
5088 .ndo_change_mtu = rtl8169_change_mtu,
5089 .ndo_fix_features = rtl8169_fix_features,
5090 .ndo_set_features = rtl8169_set_features,
5091 .ndo_set_mac_address = rtl_set_mac_address,
a7605370 5092 .ndo_eth_ioctl = phy_do_ioctl_running,
fa9c385e
FR		 5093 .ndo_set_rx_mode = rtl_set_rx_mode,
5094#ifdef CONFIG_NET_POLL_CONTROLLER
5095 .ndo_poll_controller = rtl8169_netpoll,
5096#endif
5097
5098};
5099
ec9a4088
HK		 5100static void rtl_set_irq_mask(struct rtl8169_private *tp)
5101{
2045e158 5102 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
ec9a4088
HK		 5103
5104 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6994520a 5105 tp->irq_mask |= SYSErr | RxFIFOOver;
ec9a4088
HK		 5106}
5107
6c6aa15f 5108static int rtl_alloc_irq(struct rtl8169_private *tp)
31fa8b18 5109{
6c6aa15f 5110 unsigned int flags;
31fa8b18 5111
003bd5b4
HK		 5112 switch (tp->mac_version) {
5113 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
df320ed7 5114 rtl_unlock_config_regs(tp);
1ef7286e 5115 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
df320ed7 5116 rtl_lock_config_regs(tp);
df561f66 5117 fallthrough;
f13bc681 5118 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
b14ed986 5119 flags = PCI_IRQ_INTX;
003bd5b4
HK		 5120 break;
5121 default:
6c6aa15f 5122 flags = PCI_IRQ_ALL_TYPES;
003bd5b4 5123 break;
31fa8b18 5124 }
6c6aa15f
HK		 5125
5126 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
31fa8b18
FR		 5127}
5128
04c7788c
TR		 5129static void rtl_read_mac_address(struct rtl8169_private *tp,
5130 u8 mac_addr[ETH_ALEN])
5131{
5132 /* Get MAC address */
9e9f33ba 5133 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
ae1e82c6 5134 u32 value;
deedf1fe 5135
ae1e82c6
HK		 5136 value = rtl_eri_read(tp, 0xe0);
5137 put_unaligned_le32(value, mac_addr);
724c6fd0 5138 value = rtl_eri_read(tp, 0xe4);
ae1e82c6 5139 put_unaligned_le16(value, mac_addr + 4);
f1bce4ad
HK		 5140 } else if (rtl_is_8125(tp)) {
5141 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
04c7788c
TR		 5142 }
5143}
5144
c558386b
HW		 5145DECLARE_RTL_COND(rtl_link_list_ready_cond)
5146{
1ef7286e 5147 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
c558386b
HW		 5148}
5149
e031ce80
HK		 5150static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
5151{
5152 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
5153}
5154
f1e911d5
HK		 5155static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
5156{
5157 struct rtl8169_private *tp = mii_bus->priv;
5158
5159 if (phyaddr > 0)
5160 return -ENODEV;
5161
5162 return rtl_readphy(tp, phyreg);
5163}
5164
5165static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
5166 int phyreg, u16 val)
5167{
5168 struct rtl8169_private *tp = mii_bus->priv;
5169
5170 if (phyaddr > 0)
5171 return -ENODEV;
5172
5173 rtl_writephy(tp, phyreg, val);
5174
5175 return 0;
5176}
5177
853e8036
HK		 5178static int r8169_mdio_read_reg_c45(struct mii_bus *mii_bus, int addr,
5179 int devnum, int regnum)
5180{
5181 struct rtl8169_private *tp = mii_bus->priv;
5182
5183 if (addr > 0)
5184 return -ENODEV;
5185
5186 if (devnum == MDIO_MMD_VEND2 && regnum > MDIO_STAT2)
5187 return r8168_phy_ocp_read(tp, regnum);
5188
5189 return 0;
5190}
5191
5192static int r8169_mdio_write_reg_c45(struct mii_bus *mii_bus, int addr,
5193 int devnum, int regnum, u16 val)
5194{
5195 struct rtl8169_private *tp = mii_bus->priv;
5196
5197 if (addr > 0 || devnum != MDIO_MMD_VEND2 || regnum <= MDIO_STAT2)
5198 return -ENODEV;
5199
5200 r8168_phy_ocp_write(tp, regnum, val);
5201
5202 return 0;
5203}
5204
f1e911d5
HK		 5205static int r8169_mdio_register(struct rtl8169_private *tp)
5206{
5207 struct pci_dev *pdev = tp->pci_dev;
f1e911d5
HK		 5208 struct mii_bus *new_bus;
5209 int ret;
5210
5d872c9f
HK		 5211 /* On some boards with this chip version the BIOS is buggy and misses
5212 * to reset the PHY page selector. This results in the PHY ID read
5213 * accessing registers on a different page, returning a more or
5214 * less random value. Fix this by resetting the page selector first.
5215 */
5216 if (tp->mac_version == RTL_GIGA_MAC_VER_25 ||
5217 tp->mac_version == RTL_GIGA_MAC_VER_26)
5218 r8169_mdio_write(tp, 0x1f, 0);
5219
f1e911d5
HK		 5220 new_bus = devm_mdiobus_alloc(&pdev->dev);
5221 if (!new_bus)
5222 return -ENOMEM;
5223
5224 new_bus->name = "r8169";
5225 new_bus->priv = tp;
5226 new_bus->parent = &pdev->dev;
93e8990c 5227 new_bus->irq[0] = PHY_MAC_INTERRUPT;
faac69a4 5228 new_bus->phy_mask = GENMASK(31, 1);
e9a72f87
SP		 5229 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x",
5230 pci_domain_nr(pdev->bus), pci_dev_id(pdev));
f1e911d5
HK		 5231
5232 new_bus->read = r8169_mdio_read_reg;
5233 new_bus->write = r8169_mdio_write_reg;
5234
853e8036
HK		 5235 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) {
5236 new_bus->read_c45 = r8169_mdio_read_reg_c45;
5237 new_bus->write_c45 = r8169_mdio_write_reg_c45;
5238 }
5239
ac3a68d5 5240 ret = devm_mdiobus_register(&pdev->dev, new_bus);
f1e911d5
HK		 5241 if (ret)
5242 return ret;
5243
703732f0
HK		 5244 tp->phydev = mdiobus_get_phy(new_bus, 0);
5245 if (!tp->phydev) {
f1e911d5 5246 return -ENODEV;
2e8c339b
HK		 5247 } else if (!tp->phydev->drv) {
5248 /* Most chip versions fail with the genphy driver.
5249 * Therefore ensure that the dedicated PHY driver is loaded.
5250 */
0c2006b2
HK		 5251 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5252 tp->phydev->phy_id);
2e8c339b 5253 return -EUNATCH;
f1e911d5
HK		 5254 }
5255
eca485d2 5256 tp->phydev->mac_managed_pm = true;
f5d59230 5257 if (rtl_supports_eee(tp))
031a239c 5258 phy_support_eee(tp->phydev);
11ac4e66
HK		 5259 phy_support_asym_pause(tp->phydev);
5260
e340bff2
HK		 5261 /* mimic behavior of r8125/r8126 vendor drivers */
5262 if (tp->mac_version == RTL_GIGA_MAC_VER_61)
5e7a74b6
HK		 5263 phy_disable_eee_mode(tp->phydev,
5264 ETHTOOL_LINK_MODE_2500baseT_Full_BIT);
5265 phy_disable_eee_mode(tp->phydev, ETHTOOL_LINK_MODE_5000baseT_Full_BIT);
e340bff2 5266
242cd9b5 5267 /* PHY will be woken up in rtl_open() */
703732f0 5268 phy_suspend(tp->phydev);
f1e911d5
HK		 5269
5270 return 0;
5271}
5272
baf63293 5273static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b 5274{
9617886f 5275 rtl_enable_rxdvgate(tp);
c558386b 5276
1ef7286e 5277 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
c558386b 5278 msleep(1);
1ef7286e 5279 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
c558386b 5280
ef712ede 5281 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
e031ce80 5282 r8168g_wait_ll_share_fifo_ready(tp);
c558386b 5283
ef712ede 5284 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
e031ce80 5285 r8168g_wait_ll_share_fifo_ready(tp);
c558386b
HW		 5286}
5287
f1bce4ad
HK		 5288static void rtl_hw_init_8125(struct rtl8169_private *tp)
5289{
9617886f 5290 rtl_enable_rxdvgate(tp);
f1bce4ad 5291
f1bce4ad
HK		 5292 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5293 msleep(1);
5294 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5295
5296 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
e031ce80 5297 r8168g_wait_ll_share_fifo_ready(tp);
f1bce4ad
HK		 5298
5299 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5300 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5301 r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
e031ce80 5302 r8168g_wait_ll_share_fifo_ready(tp);
f1bce4ad
HK		 5303}
5304
baf63293 5305static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 5306{
5307 switch (tp->mac_version) {
4f51e7d3 5308 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_52:
29ec0482 5309 rtl8168ep_stop_cmac(tp);
df561f66 5310 fallthrough;
2a71883c 5311 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
003609da
CHL		 5312 rtl_hw_init_8168g(tp);
5313 break;
fe733618 5314 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST:
f1bce4ad
HK		 5315 rtl_hw_init_8125(tp);
5316 break;
c558386b
HW		 5317 default:
5318 break;
5319 }
5320}
5321
abe8b2f7
HK		 5322static int rtl_jumbo_max(struct rtl8169_private *tp)
5323{
5324 /* Non-GBit versions don't support jumbo frames */
5325 if (!tp->supports_gmii)
a8ec173a 5326 return 0;
abe8b2f7
HK		 5327
5328 switch (tp->mac_version) {
5329 /* RTL8169 */
e9588eb9 5330 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
abe8b2f7
HK		 5331 return JUMBO_7K;
5332 /* RTL8168b */
abe8b2f7
HK		 5333 case RTL_GIGA_MAC_VER_17:
5334 return JUMBO_4K;
5335 /* RTL8168c */
5336 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5337 return JUMBO_6K;
473367a5 5338 /* RTL8125/8126 */
fe733618 5339 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST:
473367a5 5340 return JUMBO_16K;
abe8b2f7
HK		 5341 default:
5342 return JUMBO_9K;
5343 }
5344}
5345
c782e204
HK		 5346static void rtl_init_mac_address(struct rtl8169_private *tp)
5347{
c75a9ad4 5348 u8 mac_addr[ETH_ALEN] __aligned(2) = {};
c782e204 5349 struct net_device *dev = tp->dev;
ce37115e 5350 int rc;
c782e204
HK		 5351
5352 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5353 if (!rc)
5354 goto done;
5355
5356 rtl_read_mac_address(tp, mac_addr);
5357 if (is_valid_ether_addr(mac_addr))
5358 goto done;
5359
ce37115e 5360 rtl_read_mac_from_reg(tp, mac_addr, MAC0);
c782e204
HK		 5361 if (is_valid_ether_addr(mac_addr))
5362 goto done;
5363
c75a9ad4
HK		 5364 eth_random_addr(mac_addr);
5365 dev->addr_assign_type = NET_ADDR_RANDOM;
c782e204
HK		 5366 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5367done:
1c5d09d5 5368 eth_hw_addr_set(dev, mac_addr);
c782e204
HK		 5369 rtl_rar_set(tp, mac_addr);
5370}
5371
cf2ffdea
HK		 5372/* register is set if system vendor successfully tested ASPM 1.2 */
5373static bool rtl_aspm_is_safe(struct rtl8169_private *tp)
5374{
3d9b8ac5 5375 if (tp->mac_version >= RTL_GIGA_MAC_VER_46 &&
cf2ffdea
HK		 5376 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf)
5377 return true;
5378
5379 return false;
5380}
5381
929a031d 5382static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3b6cf25d 5383{
2b065c09 5384 const struct rtl_chip_info *chip;
3b6cf25d 5385 struct rtl8169_private *tp;
f1f9ca28 5386 int jumbo_max, region, rc;
3b6cf25d 5387 struct net_device *dev;
bc590b47 5388 u32 txconfig;
f1f9ca28 5389 u16 xid;
3b6cf25d 5390
4c45d24a
HK		 5391 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5392 if (!dev)
5393 return -ENOMEM;
3b6cf25d
FR		 5394
5395 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 5396 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 5397 tp = netdev_priv(dev);
5398 tp->dev = dev;
5399 tp->pci_dev = pdev;
145a40e8 5400 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
0360c046 5401 tp->ocp_base = OCP_STD_PHY_BASE;
3b6cf25d 5402
d6c36cbc 5403 raw_spin_lock_init(&tp->mac_ocp_lock);
18764b88 5404 mutex_init(&tp->led_lock);
91c86435 5405
c2f6f3ee 5406 /* Get the *optional* external "ether_clk" used on some boards */
599566c1
HK		 5407 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk");
5408 if (IS_ERR(tp->clk))
5409 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n");
c2f6f3ee 5410
3b6cf25d 5411 /* enable device (incl. PCI PM wakeup and hotplug setup) */
4c45d24a 5412 rc = pcim_enable_device(pdev);
733b3e27
HK		 5413 if (rc < 0)
5414 return dev_err_probe(&pdev->dev, rc, "enable failure\n");
3b6cf25d 5415
4c45d24a 5416 if (pcim_set_mwi(pdev) < 0)
22148df0 5417 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
3b6cf25d 5418
c8d48d9c
HK		 5419 /* use first MMIO region */
5420 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
733b3e27
HK		 5421 if (region < 0)
5422 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n");
3b6cf25d 5423
34e5eded
HK		 5424 tp->mmio_addr = pcim_iomap_region(pdev, region, KBUILD_MODNAME);
5425 if (IS_ERR(tp->mmio_addr))
5426 return dev_err_probe(&pdev->dev, PTR_ERR(tp->mmio_addr),
5427 "cannot remap MMIO, aborting\n");
3b6cf25d 5428
bc590b47 5429 txconfig = RTL_R32(tp, TxConfig);
733b3e27
HK		 5430 if (txconfig == ~0U)
5431 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n");
bc590b47
HK		 5432
5433 xid = (txconfig >> 20) & 0xfcf;
f1f9ca28 5434
3b6cf25d 5435 /* Identify chip attached to board */
2b065c09
HK		 5436 chip = rtl8169_get_chip_version(xid, tp->supports_gmii);
5437 if (chip->mac_version == RTL_GIGA_MAC_NONE)
733b3e27
HK		 5438 return dev_err_probe(&pdev->dev, -ENODEV,
5439 "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n",
5440 xid);
2b065c09
HK		 5441 tp->mac_version = chip->mac_version;
5442 tp->fw_name = chip->fw_name;
3b6cf25d 5443
cf2ffdea
HK		 5444 /* Disable ASPM L1 as that cause random device stop working
5445 * problems as well as full system hangs for some PCIe devices users.
cf2ffdea
HK		 5446 */
5447 if (rtl_aspm_is_safe(tp))
5448 rc = 0;
cf2ffdea
HK		 5449 else
5450 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1);
5451 tp->aspm_manageable = !rc;
5452
0ab0c45d
CL		 5453 tp->dash_type = rtl_get_dash_type(tp);
5454 tp->dash_enabled = rtl_dash_is_enabled(tp);
e0d38b58 5455
975e8505 5456 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
27896c83 5457
10b63e85 5458 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
3c18cbe3 5459 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
27896c83 5460 dev->features |= NETIF_F_HIGHDMA;
27896c83 5461
3b6cf25d
FR		 5462 rtl_init_rxcfg(tp);
5463
de20e12f 5464 rtl8169_irq_mask_and_ack(tp);
3b6cf25d 5465
c558386b
HW		 5466 rtl_hw_initialize(tp);
5467
3b6cf25d
FR		 5468 rtl_hw_reset(tp);
5469
6c6aa15f 5470 rc = rtl_alloc_irq(tp);
733b3e27
HK		 5471 if (rc < 0)
5472 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n");
5473
1bd32771 5474 tp->irq = pci_irq_vector(pdev, 0);
3b6cf25d 5475
5c41e78f 5476 INIT_WORK(&tp->wk.work, rtl_task);
e2015942 5477 disable_work(&tp->wk.work);
3b6cf25d 5478
c782e204 5479 rtl_init_mac_address(tp);
3b6cf25d 5480
7ad24ea4 5481 dev->ethtool_ops = &rtl8169_ethtool_ops;
3b6cf25d 5482
b48b89f9 5483 netif_napi_add(dev, &tp->napi, rtl8169_poll);
3b6cf25d 5484
95099c56
HK		 5485 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5486 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
a9b3d568 5487 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
2d0ec544 5488 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
3b6cf25d 5489
929a031d 5490 /*
5491 * Pretend we are using VLANs; This bypasses a nasty bug where
5492 * Interrupts stop flowing on high load on 8110SCd controllers.
5493 */
3b6cf25d 5494 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
929a031d 5495 /* Disallow toggling */
f646968f 5496 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d 5497
95099c56
HK		 5498 if (rtl_chip_supports_csum_v2(tp))
5499 dev->hw_features |= NETIF_F_IPV6_CSUM;
5500
5501 dev->features |= dev->hw_features;
5502
0170d594 5503 if (rtl_chip_supports_csum_v2(tp)) {
95099c56 5504 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
ee8b7a11
JK		 5505 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2);
5506 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2);
0170d594 5507 } else {
95099c56 5508 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
ee8b7a11
JK		 5509 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1);
5510 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1);
0170d594 5511 }
5888d3fc 5512
b8bf3844
HK		 5513 /* There has been a number of reports that using SG/TSO results in
5514 * tx timeouts. However for a lot of people SG/TSO works fine.
5515 * It's not fully clear which chip versions are affected. Vendor
5516 * drivers enable SG/TSO for certain chip versions per default,
5517 * let's mimic this here. On other chip versions users can
5518 * use ethtool to enable SG/TSO, use at own risk!
5519 */
5520 if (tp->mac_version >= RTL_GIGA_MAC_VER_46 &&
5521 tp->mac_version != RTL_GIGA_MAC_VER_61)
5522 dev->features |= dev->hw_features;
5523
3b6cf25d
FR		 5524 dev->hw_features |= NETIF_F_RXALL;
5525 dev->hw_features |= NETIF_F_RXFCS;
5526
400909df
HK		 5527 dev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS;
5528
42f66a44
HK		 5529 netdev_sw_irq_coalesce_default_on(dev);
5530
145192f8
HK		 5531 /* configure chip for default features */
5532 rtl8169_set_features(dev, dev->features);
5533
0ab0c45d 5534 if (!tp->dash_enabled) {
54744510
HK		 5535 rtl_set_d3_pll_down(tp, true);
5536 } else {
5537 rtl_set_d3_pll_down(tp, false);
3ebbd9f6 5538 dev->ethtool->wol_enabled = 1;
54744510 5539 }
128735a1 5540
abe8b2f7 5541 jumbo_max = rtl_jumbo_max(tp);
a8ec173a
HK		 5542 if (jumbo_max)
5543 dev->max_mtu = jumbo_max;
c7315a95 5544
ec9a4088 5545 rtl_set_irq_mask(tp);
9fa0a8e1 5546
4c45d24a
HK		 5547 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5548 &tp->counters_phys_addr,
5549 GFP_KERNEL);
4cf964af
HK		 5550 if (!tp->counters)
5551 return -ENOMEM;
42020320 5552
27dc36ae 5553 pci_set_drvdata(pdev, tp);
19c9ea36 5554
f1e911d5
HK		 5555 rc = r8169_mdio_register(tp);
5556 if (rc)
4cf964af 5557 return rc;
3b6cf25d 5558
f1e911d5
HK		 5559 rc = register_netdev(dev);
5560 if (rc)
0785dad4 5561 return rc;
f1e911d5 5562
be51ed10
HK		 5563 if (IS_ENABLED(CONFIG_R8169_LEDS)) {
5564 if (rtl_is_8125(tp))
19fa4f2a 5565 tp->leds = rtl8125_init_leds(dev);
be51ed10 5566 else if (tp->mac_version > RTL_GIGA_MAC_VER_06)
19fa4f2a 5567 tp->leds = rtl8168_init_leds(dev);
be51ed10 5568 }
18764b88 5569
93882c6f 5570 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n",
2b065c09 5571 chip->name, dev->dev_addr, xid, tp->irq);
abe8b2f7 5572
a8ec173a 5573 if (jumbo_max)
93882c6f
HK		 5574 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5575 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5576 "ok" : "ko");
3b6cf25d 5577
e0d38b58 5578 if (tp->dash_type != RTL_DASH_NONE) {
0ab0c45d
CL		 5579 netdev_info(dev, "DASH %s\n",
5580 tp->dash_enabled ? "enabled" : "disabled");
3b6cf25d 5581 rtl8168_driver_start(tp);
a38b7fbf 5582 }
3b6cf25d 5583
a92a0849
HK		 5584 if (pci_dev_run_wake(pdev))
5585 pm_runtime_put_sync(&pdev->dev);
5586
4c45d24a 5587 return 0;
3b6cf25d
FR		 5588}
5589
1da177e4 5590static struct pci_driver rtl8169_pci_driver = {
7cb7541a 5591 .name = KBUILD_MODNAME,
1da177e4 5592 .id_table = rtl8169_pci_tbl,
3b6cf25d 5593 .probe = rtl_init_one,
baf63293 5594 .remove = rtl_remove_one,
1765f95d 5595 .shutdown = rtl_shutdown,
8fe6e670 5596 .driver.pm = pm_ptr(&rtl8169_pm_ops),
1da177e4
LT		 5597};
5598
3eeb7da9 5599module_pci_driver(rtl8169_pci_driver);
Linux 6.x block layer and io_uring tree(s)