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Merge tag 'perf-urgent-2023-11-26' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-block.git] / drivers / net / ethernet / realtek / r8169_main.c
CommitLineData
09c434b8 1// SPDX-License-Identifier: GPL-2.0-only
1da177e4 2/*
07d3f51f
FR		 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 *
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
8 *
9 * See MAINTAINERS file for support contact information.
1da177e4
LT		 10 */
11
12#include <linux/module.h>
1da177e4
LT		 13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
c2f6f3ee 16#include <linux/clk.h>
1da177e4
LT		 17#include <linux/delay.h>
18#include <linux/ethtool.h>
f1e911d5 19#include <linux/phy.h>
1da177e4 20#include <linux/if_vlan.h>
1da177e4 21#include <linux/in.h>
098b01ad 22#include <linux/io.h>
1da177e4
LT		 23#include <linux/ip.h>
24#include <linux/tcp.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
6cf96dd4 28#include <linux/bitfield.h>
70c71606 29#include <linux/prefetch.h>
e974604b 30#include <linux/ipv6.h>
ae1e82c6 31#include <asm/unaligned.h>
e974604b 32#include <net/ip6_checksum.h>
8624e9bb 33#include <net/netdev_queues.h>
1da177e4 34
2992bdfa 35#include "r8169.h"
8197f9d2
HK		 36#include "r8169_firmware.h"
37
bca03d5f 38#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 40#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 42#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 43#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
44#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 45#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 46#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 47#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45dd95c4 48#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
5598bfe5 49#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
58152cd4 50#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
beb330a4 51#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
57538c4a 52#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
6e1d0b89 53#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
229c1e0d 54#define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw"
6e1d0b89 55#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
02bf642b 56#define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw"
0439297b 57#define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw"
bca03d5f 58
1da177e4
LT		 59/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
60 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
81cd17a4 61#define MC_FILTER_LIMIT 32
1da177e4 62
aee77e4a 63#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 64#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
65
66#define R8169_REGS_SIZE 256
1d0254dd 67#define R8169_RX_BUF_SIZE (SZ_16K - 1)
f06059c2 68#define NUM_TX_DESC 256 /* Number of Tx descriptor registers */
ed22a8ff 69#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
1da177e4
LT		 70#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
71#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
8624e9bb
HK		 72#define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1)
73#define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS)
1da177e4 74
0360c046
HK		 75#define OCP_STD_PHY_BASE 0xa400
76
145a40e8
HK		 77#define RTL_CFG_NO_GBIT 1
78
1da177e4 79/* write/read MMIO register */
1ef7286e
AS		 80#define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
81#define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
82#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
83#define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
84#define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
85#define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
1da177e4 86
b410439c
HK		 87#define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
88#define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
89#define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
90#define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
d58d46b5 91
3c6bee1d 92static const struct {
1da177e4 93 const char *name;
953a12cc 94 const char *fw_name;
85bffe6c
FR		 95} rtl_chip_infos[] = {
96 /* PCI devices. */
abe8b2f7
HK		 97 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
98 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
99 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
100 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
101 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
85bffe6c 102 /* PCI-E devices. */
abe8b2f7
HK		 103 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
104 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
9e0773c3 105 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" },
e66d6586 106 [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" },
abe8b2f7 107 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
cdafdc29 108 [RTL_GIGA_MAC_VER_14] = {"RTL8401" },
abe8b2f7
HK		 109 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
110 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
111 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
112 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
113 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
114 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
115 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
116 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
117 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
118 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
abe8b2f7
HK		 119 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
120 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
121 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
122 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
123 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
124 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
125 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
126 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
127 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
128 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
129 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
130 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
131 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
9e0773c3
HK		 132 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3},
133 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2},
134 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 },
abe8b2f7 135 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
abe8b2f7 136 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
abe8b2f7 137 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
229c1e0d 138 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3},
e6d6ca6e 139 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", },
4640338c 140 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3},
0439297b
HK		 141 /* reserve 62 for CFG_METHOD_4 in the vendor driver */
142 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2},
953a12cc
FR		 143};
144
9baa3c34 145static const struct pci_device_id rtl8169_pci_tbl[] = {
145a40e8
HK		 146 { PCI_VDEVICE(REALTEK, 0x2502) },
147 { PCI_VDEVICE(REALTEK, 0x2600) },
148 { PCI_VDEVICE(REALTEK, 0x8129) },
149 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
150 { PCI_VDEVICE(REALTEK, 0x8161) },
72f898ca 151 { PCI_VDEVICE(REALTEK, 0x8162) },
145a40e8
HK		 152 { PCI_VDEVICE(REALTEK, 0x8167) },
153 { PCI_VDEVICE(REALTEK, 0x8168) },
154 { PCI_VDEVICE(NCUBE, 0x8168) },
155 { PCI_VDEVICE(REALTEK, 0x8169) },
6f0d3088 156 { PCI_VENDOR_ID_DLINK, 0x4300,
145a40e8 157 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
9d9f3fba
HK		 158 { PCI_VDEVICE(DLINK, 0x4300) },
159 { PCI_VDEVICE(DLINK, 0x4302) },
160 { PCI_VDEVICE(AT, 0xc107) },
161 { PCI_VDEVICE(USR, 0x0116) },
162 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
163 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
f1bce4ad
HK		 164 { PCI_VDEVICE(REALTEK, 0x8125) },
165 { PCI_VDEVICE(REALTEK, 0x3000) },
6f0d3088 166 {}
1da177e4
LT		 167};
168
169MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
170
07d3f51f
FR		 171enum rtl_registers {
172 MAC0 = 0, /* Ethernet hardware address. */
773d2021 173 MAC4 = 4,
07d3f51f
FR		 174 MAR0 = 8, /* Multicast filter. */
175 CounterAddrLow = 0x10,
176 CounterAddrHigh = 0x14,
177 TxDescStartAddrLow = 0x20,
178 TxDescStartAddrHigh = 0x24,
179 TxHDescStartAddrLow = 0x28,
180 TxHDescStartAddrHigh = 0x2c,
181 FLASH = 0x30,
182 ERSR = 0x36,
183 ChipCmd = 0x37,
184 TxPoll = 0x38,
185 IntrMask = 0x3c,
186 IntrStatus = 0x3e,
4f6b00e5 187
07d3f51f 188 TxConfig = 0x40,
4f6b00e5
HW		 189#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
190#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 191
4f6b00e5
HW		 192 RxConfig = 0x44,
193#define RX128_INT_EN (1 << 15) /* 8111c and later */
194#define RX_MULTI_EN (1 << 14) /* 8111c only */
195#define RXCFG_FIFO_SHIFT 13
196 /* No threshold before first PCI xfer */
197#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 198#define RX_EARLY_OFF (1 << 11)
4f6b00e5
HW		 199#define RXCFG_DMA_SHIFT 8
200 /* Unlimited maximum PCI burst. */
201#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 202
07d3f51f
FR		 203 Cfg9346 = 0x50,
204 Config0 = 0x51,
205 Config1 = 0x52,
206 Config2 = 0x53,
d387b427
FR		 207#define PME_SIGNAL (1 << 5) /* 8168c and later */
208
07d3f51f
FR		 209 Config3 = 0x54,
210 Config4 = 0x55,
211 Config5 = 0x56,
07d3f51f 212 PHYAR = 0x60,
07d3f51f
FR		 213 PHYstatus = 0x6c,
214 RxMaxSize = 0xda,
215 CPlusCmd = 0xe0,
216 IntrMitigate = 0xe2,
50970831 217
6cf96dd4
HK		 218#define RTL_COALESCE_TX_USECS GENMASK(15, 12)
219#define RTL_COALESCE_TX_FRAMES GENMASK(11, 8)
220#define RTL_COALESCE_RX_USECS GENMASK(7, 4)
221#define RTL_COALESCE_RX_FRAMES GENMASK(3, 0)
222
2b3e48b6
HK		 223#define RTL_COALESCE_T_MAX 0x0fU
224#define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4)
50970831 225
07d3f51f
FR		 226 RxDescAddrLow = 0xe4,
227 RxDescAddrHigh = 0xe8,
f0298f81 228 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
229
230#define NoEarlyTx 0x3f /* Max value : no early transmit. */
231
232 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
233
234#define TxPacketMax (8064 >> 7)
3090bd9a 235#define EarlySize 0x27
f0298f81 236
07d3f51f
FR		 237 FuncEvent = 0xf0,
238 FuncEventMask = 0xf4,
239 FuncPresetState = 0xf8,
935e2218
CHL		 240 IBCR0 = 0xf8,
241 IBCR2 = 0xf9,
242 IBIMR0 = 0xfa,
243 IBISR0 = 0xfb,
07d3f51f 244 FuncForceEvent = 0xfc,
1da177e4
LT		 245};
246
f162a5d1
FR		 247enum rtl8168_8101_registers {
248 CSIDR = 0x64,
249 CSIAR = 0x68,
250#define CSIAR_FLAG 0x80000000
251#define CSIAR_WRITE_CMD 0x80000000
ff1d7331
HK		 252#define CSIAR_BYTE_ENABLE 0x0000f000
253#define CSIAR_ADDR_MASK 0x00000fff
065c27c1 254 PMCH = 0x6f,
128735a1
HK		 255#define D3COLD_NO_PLL_DOWN BIT(7)
256#define D3HOT_NO_PLL_DOWN BIT(6)
257#define D3_NO_PLL_DOWN (BIT(7) | BIT(6))
f162a5d1
FR		 258 EPHYAR = 0x80,
259#define EPHYAR_FLAG 0x80000000
260#define EPHYAR_WRITE_CMD 0x80000000
261#define EPHYAR_REG_MASK 0x1f
262#define EPHYAR_REG_SHIFT 16
263#define EPHYAR_DATA_MASK 0xffff
5a5e4443 264 DLLPR = 0xd0,
4f6b00e5 265#define PFM_EN (1 << 6)
6e1d0b89 266#define TX_10M_PS_EN (1 << 7)
f162a5d1
FR		 267 DBG_REG = 0xd1,
268#define FIX_NAK_1 (1 << 4)
269#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 270 TWSI = 0xd2,
271 MCU = 0xd3,
4f6b00e5 272#define NOW_IS_OOB (1 << 7)
c558386b
HW		 273#define TX_EMPTY (1 << 5)
274#define RX_EMPTY (1 << 4)
275#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 276#define EN_NDP (1 << 3)
277#define EN_OOB_RESET (1 << 2)
c558386b 278#define LINK_LIST_RDY (1 << 1)
daf9df6d 279 EFUSEAR = 0xdc,
280#define EFUSEAR_FLAG 0x80000000
281#define EFUSEAR_WRITE_CMD 0x80000000
282#define EFUSEAR_READ_CMD 0x00000000
283#define EFUSEAR_REG_MASK 0x03ff
284#define EFUSEAR_REG_SHIFT 8
285#define EFUSEAR_DATA_MASK 0xff
6e1d0b89
CHL		 286 MISC_1 = 0xf2,
287#define PFM_D3COLD_EN (1 << 6)
f162a5d1
FR		 288};
289
c0e45c1c 290enum rtl8168_registers {
4f6b00e5
HW		 291 LED_FREQ = 0x1a,
292 EEE_LED = 0x1b,
b646d900 293 ERIDR = 0x70,
294 ERIAR = 0x74,
295#define ERIAR_FLAG 0x80000000
296#define ERIAR_WRITE_CMD 0x80000000
297#define ERIAR_READ_CMD 0x00000000
298#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 299#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 300#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
301#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
302#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
935e2218 303#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
4f6b00e5
HW		 304#define ERIAR_MASK_SHIFT 12
305#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
306#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
6e1d0b89 307#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
c558386b 308#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 309#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 310 EPHY_RXER_NUM = 0x7c,
311 OCPDR = 0xb0, /* OCP GPHY access */
312#define OCPDR_WRITE_CMD 0x80000000
313#define OCPDR_READ_CMD 0x00000000
314#define OCPDR_REG_MASK 0x7f
315#define OCPDR_GPHY_REG_SHIFT 16
316#define OCPDR_DATA_MASK 0xffff
317 OCPAR = 0xb4,
318#define OCPAR_FLAG 0x80000000
319#define OCPAR_GPHY_WRITE_CMD 0x8000f060
320#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 321 GPHY_OCP = 0xb8,
01dc7fec 322 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
323 MISC = 0xf0, /* 8168e only. */
cecb5fd7 324#define TXPLA_RST (1 << 29)
5598bfe5 325#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 326#define PWM_EN (1 << 22)
c558386b 327#define RXDV_GATED_EN (1 << 19)
5598bfe5 328#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 329};
330
f1bce4ad
HK		 331enum rtl8125_registers {
332 IntrMask_8125 = 0x38,
333 IntrStatus_8125 = 0x3c,
334 TxPoll_8125 = 0x90,
335 MAC0_BKP = 0x19e0,
0439297b 336 EEE_TXIDLE_TIMER_8125 = 0x6048,
f1bce4ad
HK		 337};
338
339#define RX_VLAN_INNER_8125 BIT(22)
340#define RX_VLAN_OUTER_8125 BIT(23)
341#define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
342
343#define RX_FETCH_DFLT_8125 (8 << 27)
344
07d3f51f 345enum rtl_register_content {
1da177e4 346 /* InterruptStatusBits */
07d3f51f
FR		 347 SYSErr = 0x8000,
348 PCSTimeout = 0x4000,
349 SWInt = 0x0100,
350 TxDescUnavail = 0x0080,
351 RxFIFOOver = 0x0040,
352 LinkChg = 0x0020,
353 RxOverflow = 0x0010,
354 TxErr = 0x0008,
355 TxOK = 0x0004,
356 RxErr = 0x0002,
357 RxOK = 0x0001,
1da177e4
LT		 358
359 /* RxStatusDesc */
9dccf611
FR		 360 RxRWT = (1 << 22),
361 RxRES = (1 << 21),
362 RxRUNT = (1 << 20),
363 RxCRC = (1 << 19),
1da177e4
LT		 364
365 /* ChipCmdBits */
4f6b00e5 366 StopReq = 0x80,
07d3f51f
FR		 367 CmdReset = 0x10,
368 CmdRxEnb = 0x08,
369 CmdTxEnb = 0x04,
370 RxBufEmpty = 0x01,
1da177e4 371
275391a4
FR		 372 /* TXPoll register p.5 */
373 HPQ = 0x80, /* Poll cmd on the high prio queue */
374 NPQ = 0x40, /* Poll cmd on the low prio queue */
375 FSWInt = 0x01, /* Forced software interrupt */
376
1da177e4 377 /* Cfg9346Bits */
07d3f51f
FR		 378 Cfg9346_Lock = 0x00,
379 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 380
381 /* rx_mode_bits */
07d3f51f
FR		 382 AcceptErr = 0x20,
383 AcceptRunt = 0x10,
10478283 384#define RX_CONFIG_ACCEPT_ERR_MASK 0x30
07d3f51f
FR		 385 AcceptBroadcast = 0x08,
386 AcceptMulticast = 0x04,
387 AcceptMyPhys = 0x02,
388 AcceptAllPhys = 0x01,
10478283 389#define RX_CONFIG_ACCEPT_OK_MASK 0x0f
1687b566 390#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 391
1da177e4
LT		 392 /* TxConfigBits */
393 TxInterFrameGapShift = 24,
394 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
395
5d06a99f 396 /* Config1 register p.24 */
f162a5d1
FR		 397 LEDS1 = (1 << 7),
398 LEDS0 = (1 << 6),
f162a5d1
FR		 399 Speed_down = (1 << 4),
400 MEMMAP = (1 << 3),
401 IOMAP = (1 << 2),
402 VPD = (1 << 1),
5d06a99f
FR		 403 PMEnable = (1 << 0), /* Power Management Enable */
404
6dccd16b 405 /* Config2 register p. 25 */
57538c4a 406 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 407 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 408 PCI_Clock_66MHz = 0x01,
409 PCI_Clock_33MHz = 0x00,
410
61a4dcc2
FR		 411 /* Config3 register p.25 */
412 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
413 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 414 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
b51ecea8 415 Rdy_to_L23 = (1 << 1), /* L23 Enable */
f162a5d1 416 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 417
d58d46b5
FR		 418 /* Config4 register */
419 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
420
5d06a99f 421 /* Config5 register p.27 */
61a4dcc2
FR		 422 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
423 MWF = (1 << 5), /* Accept Multicast wakeup frame */
424 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 425 Spi_en = (1 << 3),
61a4dcc2 426 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 427 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
57538c4a 428 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 429
1da177e4 430 /* CPlusCmd p.31 */
f162a5d1
FR		 431 EnableBist = (1 << 15), // 8168 8101
432 Mac_dbgo_oe = (1 << 14), // 8168 8101
09e65335 433 EnAnaPLL = (1 << 14), // 8169
f162a5d1
FR		 434 Normal_mode = (1 << 13), // unused
435 Force_half_dup = (1 << 12), // 8168 8101
436 Force_rxflow_en = (1 << 11), // 8168 8101
437 Force_txflow_en = (1 << 10), // 8168 8101
438 Cxpl_dbg_sel = (1 << 9), // 8168 8101
439 ASF = (1 << 8), // 8168 8101
440 PktCntrDisable = (1 << 7), // 8168 8101
441 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 442 RxVlan = (1 << 6),
443 RxChkSum = (1 << 5),
444 PCIDAC = (1 << 4),
445 PCIMulRW = (1 << 3),
9a3c81fa 446#define INTT_MASK GENMASK(1, 0)
bc73241e 447#define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
1da177e4
LT		 448
449 /* rtl8169_PHYstatus */
07d3f51f
FR		 450 TBI_Enable = 0x80,
451 TxFlowCtrl = 0x40,
452 RxFlowCtrl = 0x20,
453 _1000bpsF = 0x10,
454 _100bps = 0x08,
455 _10bps = 0x04,
456 LinkStatus = 0x02,
457 FullDup = 0x01,
1da177e4 458
6e85d5ad
CV		 459 /* ResetCounterCommand */
460 CounterReset = 0x1,
461
d4a3a0fc 462 /* DumpCounterCommand */
07d3f51f 463 CounterDump = 0x8,
6e1d0b89
CHL		 464
465 /* magic enable v2 */
466 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
1da177e4
LT		 467};
468
2b7b4318
FR		 469enum rtl_desc_bit {
470 /* First doubleword. */
1da177e4
LT		 471 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
472 RingEnd = (1 << 30), /* End of descriptor ring */
473 FirstFrag = (1 << 29), /* First segment of a packet */
474 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 475};
476
477/* Generic case. */
478enum rtl_tx_desc_bit {
479 /* First doubleword. */
480 TD_LSO = (1 << 27), /* Large Send Offload */
481#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 482
2b7b4318
FR		 483 /* Second doubleword. */
484 TxVlanTag = (1 << 17), /* Add VLAN tag */
485};
486
487/* 8169, 8168b and 810x except 8102e. */
488enum rtl_tx_desc_bit_0 {
489 /* First doubleword. */
490#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
491 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
492 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
493 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
494};
495
496/* 8102e, 8168c and beyond. */
497enum rtl_tx_desc_bit_1 {
bdfa4ed6 498 /* First doubleword. */
499 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
e974604b 500 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
bdfa4ed6 501#define GTTCPHO_SHIFT 18
e64e0c89 502#define GTTCPHO_MAX 0x7f
bdfa4ed6 503
2b7b4318 504 /* Second doubleword. */
e974604b 505#define TCPHO_SHIFT 18
e64e0c89 506#define TCPHO_MAX 0x3ff
2b7b4318 507#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
e974604b 508 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
509 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
2b7b4318
FR		 510 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
511 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
512};
1da177e4 513
2b7b4318 514enum rtl_rx_desc_bit {
1da177e4
LT		 515 /* Rx private */
516 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
9b60047a 517 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
1da177e4
LT		 518
519#define RxProtoUDP (PID1)
520#define RxProtoTCP (PID0)
521#define RxProtoIP (PID1 | PID0)
522#define RxProtoMask RxProtoIP
523
524 IPFail = (1 << 16), /* IP checksum failed */
525 UDPFail = (1 << 15), /* UDP/IP checksum failed */
526 TCPFail = (1 << 14), /* TCP/IP checksum failed */
206a75e0
HK		 527
528#define RxCSFailMask (IPFail | UDPFail | TCPFail)
529
1da177e4
LT		 530 RxVlanTag = (1 << 16), /* VLAN tag available */
531};
532
0170d594
HK		 533#define RTL_GSO_MAX_SIZE_V1 32000
534#define RTL_GSO_MAX_SEGS_V1 24
535#define RTL_GSO_MAX_SIZE_V2 64000
536#define RTL_GSO_MAX_SEGS_V2 64
537
1da177e4 538struct TxDesc {
6cccd6e7
REB		 539 __le32 opts1;
540 __le32 opts2;
541 __le64 addr;
1da177e4
LT		 542};
543
544struct RxDesc {
6cccd6e7
REB		 545 __le32 opts1;
546 __le32 opts2;
547 __le64 addr;
1da177e4
LT		 548};
549
550struct ring_info {
551 struct sk_buff *skb;
552 u32 len;
1da177e4
LT		 553};
554
355423d0
IV		 555struct rtl8169_counters {
556 __le64 tx_packets;
557 __le64 rx_packets;
558 __le64 tx_errors;
559 __le32 rx_errors;
560 __le16 rx_missed;
561 __le16 align_errors;
562 __le32 tx_one_collision;
563 __le32 tx_multi_collision;
564 __le64 rx_unicast;
565 __le64 rx_broadcast;
566 __le32 rx_multicast;
567 __le16 tx_aborted;
568 __le16 tx_underun;
569};
570
6e85d5ad
CV		 571struct rtl8169_tc_offsets {
572 bool inited;
573 __le64 tx_errors;
574 __le32 tx_multi_collision;
6e85d5ad 575 __le16 tx_aborted;
0da3359a 576 __le16 rx_missed;
6e85d5ad
CV		 577};
578
da78dbff 579enum rtl_flag {
6ad56901 580 RTL_FLAG_TASK_ENABLED = 0,
da78dbff 581 RTL_FLAG_TASK_RESET_PENDING,
80c0576e 582 RTL_FLAG_TASK_TX_TIMEOUT,
da78dbff
FR		 583 RTL_FLAG_MAX
584};
585
e0d38b58
HK		 586enum rtl_dash_type {
587 RTL_DASH_NONE,
588 RTL_DASH_DP,
589 RTL_DASH_EP,
590};
591
1da177e4
LT		 592struct rtl8169_private {
593 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 594 struct pci_dev *pci_dev;
c4028958 595 struct net_device *dev;
703732f0 596 struct phy_device *phydev;
bea3348e 597 struct napi_struct napi;
76719ee2 598 enum mac_version mac_version;
e0d38b58 599 enum rtl_dash_type dash_type;
1da177e4
LT		 600 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
601 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4
LT		 602 u32 dirty_tx;
603 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
604 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
605 dma_addr_t TxPhyAddr;
606 dma_addr_t RxPhyAddr;
32879f00 607 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 608 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4 609 u16 cp_cmd;
c1d532d2 610 u32 irq_mask;
1bd32771 611 int irq;
c2f6f3ee 612 struct clk *clk;
c0e45c1c 613
4422bcd4 614 struct {
da78dbff 615 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
4422bcd4
FR		 616 struct work_struct work;
617 } wk;
618
d6c36cbc
SAS		 619 raw_spinlock_t config25_lock;
620 raw_spinlock_t mac_ocp_lock;
91c86435 621
d6c36cbc 622 raw_spinlock_t cfg9346_usage_lock;
59ee97c0
HK		 623 int cfg9346_usage_count;
624
f7ffa9ae 625 unsigned supports_gmii:1;
cf2ffdea 626 unsigned aspm_manageable:1;
0ab0c45d 627 unsigned dash_enabled:1;
42020320
CV		 628 dma_addr_t counters_phys_addr;
629 struct rtl8169_counters *counters;
6e85d5ad 630 struct rtl8169_tc_offsets tc_offset;
e1759441 631 u32 saved_wolopts;
7ec3f872 632 int eee_adv;
f1e02ed1 633
254764e5 634 const char *fw_name;
8197f9d2 635 struct rtl_fw *rtl_fw;
c558386b
HW		 636
637 u32 ocp_base;
1da177e4
LT		 638};
639
1fcd1658
HK		 640typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
641
979b6c13 642MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 643MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
11287b69 644MODULE_SOFTDEP("pre: realtek");
1da177e4 645MODULE_LICENSE("GPL");
bca03d5f 646MODULE_FIRMWARE(FIRMWARE_8168D_1);
647MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 648MODULE_FIRMWARE(FIRMWARE_8168E_1);
649MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 650MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 651MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 652MODULE_FIRMWARE(FIRMWARE_8168F_1);
653MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 654MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 655MODULE_FIRMWARE(FIRMWARE_8411_1);
45dd95c4 656MODULE_FIRMWARE(FIRMWARE_8411_2);
5598bfe5 657MODULE_FIRMWARE(FIRMWARE_8106E_1);
58152cd4 658MODULE_FIRMWARE(FIRMWARE_8106E_2);
beb330a4 659MODULE_FIRMWARE(FIRMWARE_8168G_2);
57538c4a 660MODULE_FIRMWARE(FIRMWARE_8168G_3);
6e1d0b89 661MODULE_FIRMWARE(FIRMWARE_8168H_2);
229c1e0d 662MODULE_FIRMWARE(FIRMWARE_8168FP_3);
a3bf5c42 663MODULE_FIRMWARE(FIRMWARE_8107E_2);
02bf642b 664MODULE_FIRMWARE(FIRMWARE_8125A_3);
0439297b 665MODULE_FIRMWARE(FIRMWARE_8125B_2);
1da177e4 666
1e1205b7
HK		 667static inline struct device *tp_to_dev(struct rtl8169_private *tp)
668{
669 return &tp->pci_dev->dev;
670}
671
df320ed7
HK		 672static void rtl_lock_config_regs(struct rtl8169_private *tp)
673{
59ee97c0
HK		 674 unsigned long flags;
675
d6c36cbc 676 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags);
59ee97c0
HK		 677 if (!--tp->cfg9346_usage_count)
678 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
d6c36cbc 679 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags);
df320ed7
HK		 680}
681
682static void rtl_unlock_config_regs(struct rtl8169_private *tp)
683{
59ee97c0
HK		 684 unsigned long flags;
685
d6c36cbc 686 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags);
59ee97c0
HK		 687 if (!tp->cfg9346_usage_count++)
688 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
d6c36cbc 689 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags);
df320ed7
HK		 690}
691
711463f8
HK		 692static void rtl_pci_commit(struct rtl8169_private *tp)
693{
694 /* Read an arbitrary register to commit a preceding PCI write */
695 RTL_R8(tp, ChipCmd);
696}
697
6bc6c4e6
HK		 698static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set)
699{
700 unsigned long flags;
701 u8 val;
702
d6c36cbc 703 raw_spin_lock_irqsave(&tp->config25_lock, flags);
6bc6c4e6
HK		 704 val = RTL_R8(tp, Config2);
705 RTL_W8(tp, Config2, (val & ~clear) | set);
d6c36cbc 706 raw_spin_unlock_irqrestore(&tp->config25_lock, flags);
6bc6c4e6
HK		 707}
708
709static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set)
710{
711 unsigned long flags;
712 u8 val;
713
d6c36cbc 714 raw_spin_lock_irqsave(&tp->config25_lock, flags);
6bc6c4e6
HK		 715 val = RTL_R8(tp, Config5);
716 RTL_W8(tp, Config5, (val & ~clear) | set);
d6c36cbc 717 raw_spin_unlock_irqrestore(&tp->config25_lock, flags);
6bc6c4e6
HK		 718}
719
f1bce4ad
HK		 720static bool rtl_is_8125(struct rtl8169_private *tp)
721{
efc37109 722 return tp->mac_version >= RTL_GIGA_MAC_VER_61;
f1bce4ad
HK		 723}
724
9e9f33ba
HK		 725static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
726{
727 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
c623305b 728 tp->mac_version != RTL_GIGA_MAC_VER_39 &&
e6d6ca6e 729 tp->mac_version <= RTL_GIGA_MAC_VER_53;
9e9f33ba
HK		 730}
731
2e779ddb
HK		 732static bool rtl_supports_eee(struct rtl8169_private *tp)
733{
734 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
735 tp->mac_version != RTL_GIGA_MAC_VER_37 &&
736 tp->mac_version != RTL_GIGA_MAC_VER_39;
737}
738
ce37115e
HK		 739static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
740{
741 int i;
742
743 for (i = 0; i < ETH_ALEN; i++)
744 mac[i] = RTL_R8(tp, reg + i);
745}
746
ffc46952
FR		 747struct rtl_cond {
748 bool (*check)(struct rtl8169_private *);
749 const char *msg;
750};
751
ffc46952 752static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
d6836ef0 753 unsigned long usecs, int n, bool high)
ffc46952
FR		 754{
755 int i;
756
757 for (i = 0; i < n; i++) {
ffc46952
FR		 758 if (c->check(tp) == high)
759 return true;
d6836ef0 760 fsleep(usecs);
ffc46952 761 }
93882c6f
HK		 762
763 if (net_ratelimit())
d6836ef0
HK		 764 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
765 c->msg, !high, n, usecs);
ffc46952
FR		 766 return false;
767}
768
d6836ef0
HK		 769static bool rtl_loop_wait_high(struct rtl8169_private *tp,
770 const struct rtl_cond *c,
771 unsigned long d, int n)
ffc46952 772{
d6836ef0 773 return rtl_loop_wait(tp, c, d, n, true);
ffc46952
FR		 774}
775
d6836ef0
HK		 776static bool rtl_loop_wait_low(struct rtl8169_private *tp,
777 const struct rtl_cond *c,
778 unsigned long d, int n)
ffc46952 779{
d6836ef0 780 return rtl_loop_wait(tp, c, d, n, false);
ffc46952
FR		 781}
782
783#define DECLARE_RTL_COND(name) \
784static bool name ## _check(struct rtl8169_private *); \
785 \
786static const struct rtl_cond name = { \
787 .check = name ## _check, \
788 .msg = #name \
789}; \
790 \
791static bool name ## _check(struct rtl8169_private *tp)
792
c6cff9df
HK		 793static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
794{
795 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
e6d6ca6e
KHF		 796 if (type == ERIAR_OOB &&
797 (tp->mac_version == RTL_GIGA_MAC_VER_52 ||
798 tp->mac_version == RTL_GIGA_MAC_VER_53))
abbf9a0e 799 *cmd |= 0xf70 << 18;
c6cff9df
HK		 800}
801
802DECLARE_RTL_COND(rtl_eriar_cond)
803{
804 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
805}
806
807static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
808 u32 val, int type)
809{
810 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
811
5f1e1224
HK		 812 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask))
813 return;
814
c6cff9df
HK		 815 RTL_W32(tp, ERIDR, val);
816 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
817 RTL_W32(tp, ERIAR, cmd);
818
819 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
820}
821
822static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
823 u32 val)
824{
825 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
826}
827
828static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
829{
830 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
831
832 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
833 RTL_W32(tp, ERIAR, cmd);
834
835 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
836 RTL_R32(tp, ERIDR) : ~0;
837}
838
839static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
840{
841 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
842}
843
844static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
845{
846 u32 val = rtl_eri_read(tp, addr);
847
848 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
849}
850
851static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
852{
853 rtl_w0w1_eri(tp, addr, p, 0);
854}
855
856static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
857{
858 rtl_w0w1_eri(tp, addr, 0, m);
859}
860
a46604d7 861static bool rtl_ocp_reg_failure(u32 reg)
c558386b 862{
a46604d7 863 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg);
c558386b
HW		 864}
865
866DECLARE_RTL_COND(rtl_ocp_gphy_cond)
867{
1ef7286e 868 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
c558386b
HW		 869}
870
871static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
872{
a46604d7 873 if (rtl_ocp_reg_failure(reg))
c558386b
HW		 874 return;
875
1ef7286e 876 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
c558386b 877
d6836ef0 878 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
c558386b
HW		 879}
880
9b994b4a 881static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
c558386b 882{
a46604d7 883 if (rtl_ocp_reg_failure(reg))
c558386b
HW		 884 return 0;
885
1ef7286e 886 RTL_W32(tp, GPHY_OCP, reg << 15);
c558386b 887
d6836ef0 888 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
9b994b4a 889 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
c558386b
HW		 890}
891
91c86435 892static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
c558386b 893{
a46604d7 894 if (rtl_ocp_reg_failure(reg))
c558386b
HW		 895 return;
896
1ef7286e 897 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 898}
899
91c86435
HK		 900static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
901{
902 unsigned long flags;
903
d6c36cbc 904 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
91c86435 905 __r8168_mac_ocp_write(tp, reg, data);
d6c36cbc 906 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
91c86435
HK		 907}
908
909static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
c558386b 910{
a46604d7 911 if (rtl_ocp_reg_failure(reg))
c558386b
HW		 912 return 0;
913
1ef7286e 914 RTL_W32(tp, OCPDR, reg << 15);
c558386b 915
1ef7286e 916 return RTL_R32(tp, OCPDR);
c558386b
HW		 917}
918
91c86435
HK		 919static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
920{
921 unsigned long flags;
922 u16 val;
923
d6c36cbc 924 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
91c86435 925 val = __r8168_mac_ocp_read(tp, reg);
d6c36cbc 926 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
91c86435
HK		 927
928 return val;
929}
930
ef712ede
HK		 931static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
932 u16 set)
933{
91c86435
HK		 934 unsigned long flags;
935 u16 data;
ef712ede 936
d6c36cbc 937 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
91c86435
HK		 938 data = __r8168_mac_ocp_read(tp, reg);
939 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
d6c36cbc 940 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
ef712ede
HK		 941}
942
acb58657
HK		 943/* Work around a hw issue with RTL8168g PHY, the quirk disables
944 * PHY MCU interrupts before PHY power-down.
945 */
946static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value)
947{
948 switch (tp->mac_version) {
949 case RTL_GIGA_MAC_VER_40:
acb58657
HK		 950 if (value & BMCR_RESET || !(value & BMCR_PDOWN))
951 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
952 else
953 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
954 break;
955 default:
956 break;
957 }
958};
959
c558386b
HW		 960static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
961{
962 if (reg == 0x1f) {
963 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
964 return;
965 }
966
967 if (tp->ocp_base != OCP_STD_PHY_BASE)
968 reg -= 0x10;
969
acb58657
HK		 970 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR)
971 rtl8168g_phy_suspend_quirk(tp, value);
972
c558386b
HW		 973 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
974}
975
976static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
977{
9c6850fe
HK		 978 if (reg == 0x1f)
979 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
980
c558386b
HW		 981 if (tp->ocp_base != OCP_STD_PHY_BASE)
982 reg -= 0x10;
983
984 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
985}
986
eee3786f 987static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
988{
989 if (reg == 0x1f) {
990 tp->ocp_base = value << 4;
991 return;
992 }
993
994 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
995}
996
997static int mac_mcu_read(struct rtl8169_private *tp, int reg)
998{
999 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1000}
1001
ffc46952
FR		 1002DECLARE_RTL_COND(rtl_phyar_cond)
1003{
1ef7286e 1004 return RTL_R32(tp, PHYAR) & 0x80000000;
ffc46952
FR		 1005}
1006
24192210 1007static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 1008{
1ef7286e 1009 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 1010
d6836ef0 1011 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 1012 /*
81a95f04
TT		 1013 * According to hardware specs a 20us delay is required after write
1014 * complete indication, but before sending next command.
024a07ba 1015 */
81a95f04 1016 udelay(20);
1da177e4
LT		 1017}
1018
24192210 1019static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 1020{
ffc46952 1021 int value;
1da177e4 1022
1ef7286e 1023 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1024
d6836ef0 1025 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
9b994b4a 1026 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
ffc46952 1027
81a95f04
TT		 1028 /*
1029 * According to hardware specs a 20us delay is required after read
1030 * complete indication, but before sending next command.
1031 */
1032 udelay(20);
1033
1da177e4
LT		 1034 return value;
1035}
1036
935e2218
CHL		 1037DECLARE_RTL_COND(rtl_ocpar_cond)
1038{
1ef7286e 1039 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
935e2218
CHL		 1040}
1041
e6de30d6 1042#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1043
1ef7286e 1044static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
e6de30d6 1045{
1ef7286e 1046 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 1047}
1048
1ef7286e 1049static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
e6de30d6 1050{
1ef7286e 1051 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 1052}
1053
24192210 1054static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1055{
1ef7286e 1056 r8168dp_2_mdio_start(tp);
e6de30d6 1057
24192210 1058 r8169_mdio_write(tp, reg, value);
e6de30d6 1059
1ef7286e 1060 r8168dp_2_mdio_stop(tp);
e6de30d6 1061}
1062
24192210 1063static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1064{
1065 int value;
1066
62bdc8fd
HK		 1067 /* Work around issue with chip reporting wrong PHY ID */
1068 if (reg == MII_PHYSID2)
1069 return 0xc912;
1070
1ef7286e 1071 r8168dp_2_mdio_start(tp);
e6de30d6 1072
24192210 1073 value = r8169_mdio_read(tp, reg);
e6de30d6 1074
1ef7286e 1075 r8168dp_2_mdio_stop(tp);
e6de30d6 1076
1077 return value;
1078}
1079
ce8843ab 1080static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
dacf8154 1081{
5f950523 1082 switch (tp->mac_version) {
5f950523
HK		 1083 case RTL_GIGA_MAC_VER_28:
1084 case RTL_GIGA_MAC_VER_31:
1085 r8168dp_2_mdio_write(tp, location, val);
1086 break;
0439297b 1087 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
5f950523
HK		 1088 r8168g_mdio_write(tp, location, val);
1089 break;
1090 default:
1091 r8169_mdio_write(tp, location, val);
1092 break;
1093 }
dacf8154
FR		 1094}
1095
4da19633 1096static int rtl_readphy(struct rtl8169_private *tp, int location)
1097{
5f950523 1098 switch (tp->mac_version) {
5f950523
HK		 1099 case RTL_GIGA_MAC_VER_28:
1100 case RTL_GIGA_MAC_VER_31:
1101 return r8168dp_2_mdio_read(tp, location);
0439297b 1102 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
5f950523
HK		 1103 return r8168g_mdio_read(tp, location);
1104 default:
1105 return r8169_mdio_read(tp, location);
1106 }
4da19633 1107}
1108
ffc46952
FR		 1109DECLARE_RTL_COND(rtl_ephyar_cond)
1110{
1ef7286e 1111 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
ffc46952
FR		 1112}
1113
fdf6fc06 1114static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1115{
1ef7286e 1116 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
dacf8154
FR		 1117 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1118
d6836ef0 1119 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
ffc46952
FR		 1120
1121 udelay(10);
dacf8154
FR		 1122}
1123
fdf6fc06 1124static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1125{
1ef7286e 1126 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
dacf8154 1127
d6836ef0 1128 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1ef7286e 1129 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1130}
1131
a15aaa03 1132static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
935e2218 1133{
a15aaa03 1134 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
d6836ef0 1135 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1ef7286e 1136 RTL_R32(tp, OCPDR) : ~0;
935e2218
CHL		 1137}
1138
787c0c04 1139static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
935e2218 1140{
724c6fd0 1141 return _rtl_eri_read(tp, reg, ERIAR_OOB);
935e2218
CHL		 1142}
1143
935e2218
CHL		 1144static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1145 u32 data)
1146{
1ef7286e
AS		 1147 RTL_W32(tp, OCPDR, data);
1148 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
d6836ef0 1149 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
935e2218
CHL		 1150}
1151
1152static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1153 u32 data)
1154{
724c6fd0
HK		 1155 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1156 data, ERIAR_OOB);
935e2218
CHL		 1157}
1158
3c72bf71 1159static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
2a9b4d96 1160{
724c6fd0 1161 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
2a9b4d96 1162
3c72bf71 1163 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
2a9b4d96
CHL		 1164}
1165
1166#define OOB_CMD_RESET 0x00
1167#define OOB_CMD_DRIVER_START 0x05
1168#define OOB_CMD_DRIVER_STOP 0x06
1169
1170static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1171{
1172 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1173}
1174
3c72bf71 1175DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
2a9b4d96
CHL		 1176{
1177 u16 reg;
1178
1179 reg = rtl8168_get_ocp_reg(tp);
1180
a15aaa03 1181 return r8168dp_ocp_read(tp, reg) & 0x00000800;
2a9b4d96
CHL		 1182}
1183
935e2218 1184DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
2a9b4d96 1185{
787c0c04 1186 return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
935e2218
CHL		 1187}
1188
1189DECLARE_RTL_COND(rtl_ocp_tx_cond)
1190{
1ef7286e 1191 return RTL_R8(tp, IBISR0) & 0x20;
935e2218 1192}
2a9b4d96 1193
003609da
CHL		 1194static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1195{
1ef7286e 1196 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
d6836ef0 1197 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
1ef7286e
AS		 1198 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1199 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
003609da
CHL		 1200}
1201
935e2218
CHL		 1202static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1203{
3c72bf71 1204 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
d6836ef0 1205 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
2a9b4d96
CHL		 1206}
1207
935e2218 1208static void rtl8168ep_driver_start(struct rtl8169_private *tp)
2a9b4d96 1209{
3c72bf71 1210 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
787c0c04 1211 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
d6836ef0 1212 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10);
935e2218
CHL		 1213}
1214
1215static void rtl8168_driver_start(struct rtl8169_private *tp)
1216{
e0d38b58 1217 if (tp->dash_type == RTL_DASH_DP)
935e2218 1218 rtl8168dp_driver_start(tp);
e0d38b58 1219 else
935e2218 1220 rtl8168ep_driver_start(tp);
935e2218 1221}
2a9b4d96 1222
935e2218
CHL		 1223static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1224{
3c72bf71 1225 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
d6836ef0 1226 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
2a9b4d96
CHL		 1227}
1228
935e2218
CHL		 1229static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1230{
003609da 1231 rtl8168ep_stop_cmac(tp);
3c72bf71 1232 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
787c0c04 1233 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
d6836ef0 1234 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
935e2218
CHL		 1235}
1236
1237static void rtl8168_driver_stop(struct rtl8169_private *tp)
1238{
e0d38b58 1239 if (tp->dash_type == RTL_DASH_DP)
935e2218 1240 rtl8168dp_driver_stop(tp);
e0d38b58 1241 else
935e2218 1242 rtl8168ep_driver_stop(tp);
935e2218
CHL		 1243}
1244
9dbe7896 1245static bool r8168dp_check_dash(struct rtl8169_private *tp)
2a9b4d96
CHL		 1246{
1247 u16 reg = rtl8168_get_ocp_reg(tp);
1248
e0d38b58 1249 return r8168dp_ocp_read(tp, reg) & BIT(15);
2a9b4d96
CHL		 1250}
1251
9dbe7896 1252static bool r8168ep_check_dash(struct rtl8169_private *tp)
935e2218 1253{
e0d38b58 1254 return r8168ep_ocp_read(tp, 0x128) & BIT(0);
935e2218
CHL		 1255}
1256
0ab0c45d
CL		 1257static bool rtl_dash_is_enabled(struct rtl8169_private *tp)
1258{
1259 switch (tp->dash_type) {
1260 case RTL_DASH_DP:
1261 return r8168dp_check_dash(tp);
1262 case RTL_DASH_EP:
1263 return r8168ep_check_dash(tp);
1264 default:
1265 return false;
1266 }
1267}
1268
1269static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp)
935e2218
CHL		 1270{
1271 switch (tp->mac_version) {
935e2218
CHL		 1272 case RTL_GIGA_MAC_VER_28:
1273 case RTL_GIGA_MAC_VER_31:
0ab0c45d 1274 return RTL_DASH_DP;
133706a9 1275 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53:
0ab0c45d 1276 return RTL_DASH_EP;
935e2218 1277 default:
e0d38b58 1278 return RTL_DASH_NONE;
935e2218
CHL		 1279 }
1280}
1281
128735a1
HK		 1282static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable)
1283{
1284 switch (tp->mac_version) {
1285 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
d2a04370 1286 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:
128735a1
HK		 1287 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37:
1288 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1289 if (enable)
1290 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN);
1291 else
1292 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN);
1293 break;
1294 default:
1295 break;
1296 }
1297}
1298
4e7e4621
HK		 1299static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1300{
54113ded
HK		 1301 rtl_eri_clear_bits(tp, 0xdc, BIT(0));
1302 rtl_eri_set_bits(tp, 0xdc, BIT(0));
4e7e4621
HK		 1303}
1304
ffc46952
FR		 1305DECLARE_RTL_COND(rtl_efusear_cond)
1306{
1ef7286e 1307 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
ffc46952
FR		 1308}
1309
2992bdfa 1310u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1311{
1ef7286e 1312 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
daf9df6d 1313
d6836ef0 1314 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1ef7286e 1315 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1316}
1317
c1d532d2
HK		 1318static u32 rtl_get_events(struct rtl8169_private *tp)
1319{
f1bce4ad
HK		 1320 if (rtl_is_8125(tp))
1321 return RTL_R32(tp, IntrStatus_8125);
1322 else
1323 return RTL_R16(tp, IntrStatus);
c1d532d2
HK		 1324}
1325
1326static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
9085cdfa 1327{
f1bce4ad
HK		 1328 if (rtl_is_8125(tp))
1329 RTL_W32(tp, IntrStatus_8125, bits);
1330 else
1331 RTL_W16(tp, IntrStatus, bits);
9085cdfa
FR		 1332}
1333
1334static void rtl_irq_disable(struct rtl8169_private *tp)
1335{
f1bce4ad
HK		 1336 if (rtl_is_8125(tp))
1337 RTL_W32(tp, IntrMask_8125, 0);
1338 else
1339 RTL_W16(tp, IntrMask, 0);
3e990ff5
FR		 1340}
1341
fe716f8a 1342static void rtl_irq_enable(struct rtl8169_private *tp)
da78dbff 1343{
f1bce4ad
HK		 1344 if (rtl_is_8125(tp))
1345 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1346 else
1347 RTL_W16(tp, IntrMask, tp->irq_mask);
da78dbff
FR		 1348}
1349
811fd301 1350static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1351{
9085cdfa 1352 rtl_irq_disable(tp);
c1d532d2 1353 rtl_ack_events(tp, 0xffffffff);
711463f8 1354 rtl_pci_commit(tp);
1da177e4
LT		 1355}
1356
70090424
HW		 1357static void rtl_link_chg_patch(struct rtl8169_private *tp)
1358{
703732f0 1359 struct phy_device *phydev = tp->phydev;
70090424 1360
b3d7b2f2
HW		 1361 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1362 tp->mac_version == RTL_GIGA_MAC_VER_38) {
29a12b49 1363 if (phydev->speed == SPEED_1000) {
724c6fd0
HK		 1364 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1365 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
29a12b49 1366 } else if (phydev->speed == SPEED_100) {
724c6fd0
HK		 1367 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1368 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
70090424 1369 } else {
724c6fd0
HK		 1370 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1371 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
70090424 1372 }
4e7e4621 1373 rtl_reset_packet_filter(tp);
c2218925
HW		 1374 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1375 tp->mac_version == RTL_GIGA_MAC_VER_36) {
29a12b49 1376 if (phydev->speed == SPEED_1000) {
724c6fd0
HK		 1377 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1378 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
c2218925 1379 } else {
724c6fd0
HK		 1380 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1381 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
c2218925 1382 }
7e18dca1 1383 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
29a12b49 1384 if (phydev->speed == SPEED_10) {
724c6fd0
HK		 1385 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1386 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
7e18dca1 1387 } else {
724c6fd0 1388 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
7e18dca1 1389 }
70090424
HW		 1390 }
1391}
1392
e1759441
RW		 1393#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1394
e1759441 1395static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1396{
1397 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1398
e1759441 1399 wol->supported = WAKE_ANY;
433f9d0d 1400 wol->wolopts = tp->saved_wolopts;
e1759441
RW		 1401}
1402
1403static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1404{
350f7596 1405 static const struct {
61a4dcc2
FR		 1406 u32 opt;
1407 u16 reg;
1408 u8 mask;
1409 } cfg[] = {
61a4dcc2 1410 { WAKE_PHY, Config3, LinkUp },
61a4dcc2
FR		 1411 { WAKE_UCAST, Config5, UWF },
1412 { WAKE_BCAST, Config5, BWF },
1413 { WAKE_MCAST, Config5, MWF },
6e1d0b89
CHL		 1414 { WAKE_ANY, Config5, LanWake },
1415 { WAKE_MAGIC, Config3, MagicPacket }
61a4dcc2 1416 };
f1bce4ad 1417 unsigned int i, tmp = ARRAY_SIZE(cfg);
6bc6c4e6 1418 unsigned long flags;
851e6022 1419 u8 options;
61a4dcc2 1420
df320ed7 1421 rtl_unlock_config_regs(tp);
61a4dcc2 1422
9e9f33ba 1423 if (rtl_is_8168evl_up(tp)) {
f1bce4ad 1424 tmp--;
6e1d0b89 1425 if (wolopts & WAKE_MAGIC)
54113ded 1426 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
6e1d0b89 1427 else
54113ded 1428 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
f1bce4ad
HK		 1429 } else if (rtl_is_8125(tp)) {
1430 tmp--;
1431 if (wolopts & WAKE_MAGIC)
1432 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1433 else
1434 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
6e1d0b89
CHL		 1435 }
1436
d6c36cbc 1437 raw_spin_lock_irqsave(&tp->config25_lock, flags);
6e1d0b89 1438 for (i = 0; i < tmp; i++) {
1ef7286e 1439 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
e1759441 1440 if (wolopts & cfg[i].opt)
61a4dcc2 1441 options |= cfg[i].mask;
1ef7286e 1442 RTL_W8(tp, cfg[i].reg, options);
61a4dcc2 1443 }
d6c36cbc 1444 raw_spin_unlock_irqrestore(&tp->config25_lock, flags);
61a4dcc2 1445
851e6022 1446 switch (tp->mac_version) {
edcde3ee 1447 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1ef7286e 1448 options = RTL_R8(tp, Config1) & ~PMEnable;
851e6022
FR		 1449 if (wolopts)
1450 options |= PMEnable;
1ef7286e 1451 RTL_W8(tp, Config1, options);
851e6022 1452 break;
edcde3ee
HK		 1453 case RTL_GIGA_MAC_VER_34:
1454 case RTL_GIGA_MAC_VER_37:
0439297b 1455 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
d387b427 1456 if (wolopts)
6bc6c4e6
HK		 1457 rtl_mod_config2(tp, 0, PME_SIGNAL);
1458 else
1459 rtl_mod_config2(tp, PME_SIGNAL, 0);
851e6022 1460 break;
edcde3ee
HK		 1461 default:
1462 break;
851e6022
FR		 1463 }
1464
df320ed7 1465 rtl_lock_config_regs(tp);
3bd82645
HK		 1466
1467 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
54744510 1468
0ab0c45d 1469 if (!tp->dash_enabled) {
54744510
HK		 1470 rtl_set_d3_pll_down(tp, !wolopts);
1471 tp->dev->wol_enabled = wolopts ? 1 : 0;
1472 }
e1759441
RW		 1473}
1474
1475static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1476{
1477 struct rtl8169_private *tp = netdev_priv(dev);
5fa80a32 1478
2f533f6b
HK		 1479 if (wol->wolopts & ~WAKE_ANY)
1480 return -EINVAL;
1481
2f533f6b 1482 tp->saved_wolopts = wol->wolopts;
ec2f204b 1483 __rtl8169_set_wol(tp, tp->saved_wolopts);
da78dbff 1484
61a4dcc2
FR		 1485 return 0;
1486}
1487
1da177e4
LT		 1488static void rtl8169_get_drvinfo(struct net_device *dev,
1489 struct ethtool_drvinfo *info)
1490{
1491 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1492 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1493
f029c781
WS		 1494 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1495 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1496 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
254764e5 1497 if (rtl_fw)
f029c781 1498 strscpy(info->fw_version, rtl_fw->version,
8ac72d16 1499 sizeof(info->fw_version));
1da177e4
LT		 1500}
1501
1502static int rtl8169_get_regs_len(struct net_device *dev)
1503{
1504 return R8169_REGS_SIZE;
1505}
1506
c8f44aff
MM		 1507static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1508 netdev_features_t features)
1da177e4 1509{
d58d46b5
FR		 1510 struct rtl8169_private *tp = netdev_priv(dev);
1511
2b7b4318 1512 if (dev->mtu > TD_MSS_MAX)
350fb32a 1513 features &= ~NETIF_F_ALL_TSO;
1da177e4 1514
a8ec173a 1515 if (dev->mtu > ETH_DATA_LEN &&
6ed0e08f 1516 tp->mac_version > RTL_GIGA_MAC_VER_06)
7cb83b21 1517 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
d58d46b5 1518
350fb32a 1519 return features;
1da177e4
LT		 1520}
1521
10478283
HK		 1522static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1523 netdev_features_t features)
1da177e4 1524{
10478283 1525 u32 rx_config = RTL_R32(tp, RxConfig);
a3984578 1526
929a031d 1527 if (features & NETIF_F_RXALL)
10478283 1528 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
929a031d 1529 else
10478283 1530 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
1da177e4 1531
f1bce4ad
HK		 1532 if (rtl_is_8125(tp)) {
1533 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1534 rx_config |= RX_VLAN_8125;
1535 else
1536 rx_config &= ~RX_VLAN_8125;
1537 }
1538
1ef7286e 1539 RTL_W32(tp, RxConfig, rx_config);
10478283
HK		 1540}
1541
1542static int rtl8169_set_features(struct net_device *dev,
1543 netdev_features_t features)
1544{
1545 struct rtl8169_private *tp = netdev_priv(dev);
1546
10478283 1547 rtl_set_rx_config_features(tp, features);
350fb32a 1548
929a031d 1549 if (features & NETIF_F_RXCSUM)
1550 tp->cp_cmd |= RxChkSum;
1551 else
1552 tp->cp_cmd &= ~RxChkSum;
6bbe021d 1553
f1bce4ad
HK		 1554 if (!rtl_is_8125(tp)) {
1555 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1556 tp->cp_cmd |= RxVlan;
1557 else
1558 tp->cp_cmd &= ~RxVlan;
1559 }
929a031d 1560
1ef7286e 1561 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
711463f8 1562 rtl_pci_commit(tp);
1da177e4 1563
1da177e4
LT		 1564 return 0;
1565}
1566
810f4893 1567static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 1568{
df8a39de 1569 return (skb_vlan_tag_present(skb)) ?
7424edbb 1570 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1da177e4
LT		 1571}
1572
7a8fc77b 1573static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1574{
1575 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1576
7a8fc77b 1577 if (opts2 & RxVlanTag)
7424edbb 1578 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1da177e4
LT		 1579}
1580
1da177e4
LT		 1581static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1582 void *p)
1583{
5b0384f4 1584 struct rtl8169_private *tp = netdev_priv(dev);
15edae91
PW		 1585 u32 __iomem *data = tp->mmio_addr;
1586 u32 *dw = p;
1587 int i;
1da177e4 1588
15edae91
PW		 1589 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1590 memcpy_fromio(dw++, data++, 4);
1da177e4
LT		 1591}
1592
d4a3a0fc
SH		 1593static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1594 "tx_packets",
1595 "rx_packets",
1596 "tx_errors",
1597 "rx_errors",
1598 "rx_missed",
1599 "align_errors",
1600 "tx_single_collisions",
1601 "tx_multi_collisions",
1602 "unicast",
1603 "broadcast",
1604 "multicast",
1605 "tx_aborted",
1606 "tx_underrun",
1607};
1608
b9f2c044 1609static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1610{
b9f2c044
JG		 1611 switch (sset) {
1612 case ETH_SS_STATS:
1613 return ARRAY_SIZE(rtl8169_gstrings);
1614 default:
1615 return -EOPNOTSUPP;
1616 }
d4a3a0fc
SH		 1617}
1618
42020320 1619DECLARE_RTL_COND(rtl_counters_cond)
6e85d5ad 1620{
1ef7286e 1621 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
6e85d5ad
CV		 1622}
1623
d56f58ce 1624static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
6e85d5ad 1625{
b498ee3f 1626 u32 cmd = lower_32_bits(tp->counters_phys_addr);
6e85d5ad 1627
b498ee3f 1628 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr));
711463f8 1629 rtl_pci_commit(tp);
1ef7286e
AS		 1630 RTL_W32(tp, CounterAddrLow, cmd);
1631 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
6e85d5ad 1632
d6836ef0 1633 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
6e85d5ad
CV		 1634}
1635
d56f58ce 1636static void rtl8169_update_counters(struct rtl8169_private *tp)
d4a3a0fc 1637{
10262b0b
HK		 1638 u8 val = RTL_R8(tp, ChipCmd);
1639
355423d0
IV		 1640 /*
1641 * Some chips are unable to dump tally counters when the receiver
10262b0b 1642 * is disabled. If 0xff chip may be in a PCI power-save state.
355423d0 1643 */
d56f58ce
HK		 1644 if (val & CmdRxEnb && val != 0xff)
1645 rtl8169_do_counters(tp, CounterDump);
6e85d5ad
CV		 1646}
1647
d56f58ce 1648static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
6e85d5ad 1649{
42020320 1650 struct rtl8169_counters *counters = tp->counters;
6e85d5ad
CV		 1651
1652 /*
1653 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1654 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1655 * reset by a power cycle, while the counter values collected by the
1656 * driver are reset at every driver unload/load cycle.
1657 *
1658 * To make sure the HW values returned by @get_stats64 match the SW
1659 * values, we collect the initial values at first open(*) and use them
1660 * as offsets to normalize the values returned by @get_stats64.
1661 *
1662 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1663 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1664 * set at open time by rtl_hw_start.
1665 */
1666
1667 if (tp->tc_offset.inited)
d56f58ce 1668 return;
6e85d5ad 1669
6b4f5031
HK		 1670 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) {
1671 rtl8169_do_counters(tp, CounterReset);
1672 } else {
1673 rtl8169_update_counters(tp);
1674 tp->tc_offset.tx_errors = counters->tx_errors;
1675 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1676 tp->tc_offset.tx_aborted = counters->tx_aborted;
1677 tp->tc_offset.rx_missed = counters->rx_missed;
1678 }
6e85d5ad 1679
6e85d5ad 1680 tp->tc_offset.inited = true;
d4a3a0fc
SH		 1681}
1682
355423d0
IV		 1683static void rtl8169_get_ethtool_stats(struct net_device *dev,
1684 struct ethtool_stats *stats, u64 *data)
1685{
1686 struct rtl8169_private *tp = netdev_priv(dev);
ec2f204b 1687 struct rtl8169_counters *counters;
e0636236 1688
ec2f204b
HK		 1689 counters = tp->counters;
1690 rtl8169_update_counters(tp);
355423d0 1691
42020320
CV		 1692 data[0] = le64_to_cpu(counters->tx_packets);
1693 data[1] = le64_to_cpu(counters->rx_packets);
1694 data[2] = le64_to_cpu(counters->tx_errors);
1695 data[3] = le32_to_cpu(counters->rx_errors);
1696 data[4] = le16_to_cpu(counters->rx_missed);
1697 data[5] = le16_to_cpu(counters->align_errors);
1698 data[6] = le32_to_cpu(counters->tx_one_collision);
1699 data[7] = le32_to_cpu(counters->tx_multi_collision);
1700 data[8] = le64_to_cpu(counters->rx_unicast);
1701 data[9] = le64_to_cpu(counters->rx_broadcast);
1702 data[10] = le32_to_cpu(counters->rx_multicast);
1703 data[11] = le16_to_cpu(counters->tx_aborted);
1704 data[12] = le16_to_cpu(counters->tx_underun);
355423d0
IV		 1705}
1706
d4a3a0fc
SH		 1707static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1708{
1709 switch(stringset) {
1710 case ETH_SS_STATS:
da5ac772 1711 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings));
d4a3a0fc
SH		 1712 break;
1713 }
1714}
1715
50970831
FR		 1716/*
1717 * Interrupt coalescing
1718 *
1719 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1720 * > 8169, 8168 and 810x line of chipsets
1721 *
1722 * 8169, 8168, and 8136(810x) serial chipsets support it.
1723 *
1724 * > 2 - the Tx timer unit at gigabit speed
1725 *
1726 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1727 * (0xe0) bit 1 and bit 0.
1728 *
1729 * For 8169
1730 * bit[1:0] \ speed 1000M 100M 10M
1731 * 0 0 320ns 2.56us 40.96us
1732 * 0 1 2.56us 20.48us 327.7us
1733 * 1 0 5.12us 40.96us 655.4us
1734 * 1 1 10.24us 81.92us 1.31ms
1735 *
1736 * For the other
1737 * bit[1:0] \ speed 1000M 100M 10M
1738 * 0 0 5us 2.56us 40.96us
1739 * 0 1 40us 20.48us 327.7us
1740 * 1 0 80us 40.96us 655.4us
1741 * 1 1 160us 81.92us 1.31ms
1742 */
1743
50970831
FR		 1744/* rx/tx scale factors for all CPlusCmd[0:1] cases */
1745struct rtl_coalesce_info {
1746 u32 speed;
2815b305 1747 u32 scale_nsecs[4];
50970831
FR		 1748};
1749
2815b305
HK		 1750/* produce array with base delay *1, *8, *8*2, *8*2*2 */
1751#define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1752
50970831 1753static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
2815b305 1754 { SPEED_1000, COALESCE_DELAY(320) },
51f6291b
HK		 1755 { SPEED_100, COALESCE_DELAY(2560) },
1756 { SPEED_10, COALESCE_DELAY(40960) },
50970831
FR		 1757 { 0 },
1758};
1759
1760static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
2815b305 1761 { SPEED_1000, COALESCE_DELAY(5000) },
51f6291b
HK		 1762 { SPEED_100, COALESCE_DELAY(2560) },
1763 { SPEED_10, COALESCE_DELAY(40960) },
50970831
FR		 1764 { 0 },
1765};
2815b305 1766#undef COALESCE_DELAY
50970831
FR		 1767
1768/* get rx/tx scale vector corresponding to current speed */
ef2c0a78
HK		 1769static const struct rtl_coalesce_info *
1770rtl_coalesce_info(struct rtl8169_private *tp)
50970831 1771{
50970831 1772 const struct rtl_coalesce_info *ci;
50970831 1773
20023d3e
HK		 1774 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1775 ci = rtl_coalesce_info_8169;
1776 else
1777 ci = rtl_coalesce_info_8168_8136;
50970831 1778
51f6291b
HK		 1779 /* if speed is unknown assume highest one */
1780 if (tp->phydev->speed == SPEED_UNKNOWN)
1781 return ci;
1782
20023d3e
HK		 1783 for (; ci->speed; ci++) {
1784 if (tp->phydev->speed == ci->speed)
50970831 1785 return ci;
50970831
FR		 1786 }
1787
1788 return ERR_PTR(-ELNRNG);
1789}
1790
f3ccfda1
YM		 1791static int rtl_get_coalesce(struct net_device *dev,
1792 struct ethtool_coalesce *ec,
1793 struct kernel_ethtool_coalesce *kernel_coal,
1794 struct netlink_ext_ack *extack)
50970831
FR		 1795{
1796 struct rtl8169_private *tp = netdev_priv(dev);
50970831 1797 const struct rtl_coalesce_info *ci;
6cf96dd4
HK		 1798 u32 scale, c_us, c_fr;
1799 u16 intrmit;
50970831 1800
f1bce4ad
HK		 1801 if (rtl_is_8125(tp))
1802 return -EOPNOTSUPP;
1803
50970831
FR		 1804 memset(ec, 0, sizeof(*ec));
1805
1806 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
ef2c0a78 1807 ci = rtl_coalesce_info(tp);
50970831
FR		 1808 if (IS_ERR(ci))
1809 return PTR_ERR(ci);
1810
2815b305 1811 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
50970831 1812
6cf96dd4 1813 intrmit = RTL_R16(tp, IntrMitigate);
50970831 1814
6cf96dd4
HK		 1815 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
1816 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
50970831 1817
6cf96dd4
HK		 1818 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
1819 /* ethtool_coalesce states usecs and max_frames must not both be 0 */
1820 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1821
1822 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
1823 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1824
1825 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
1826 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
50970831
FR		 1827
1828 return 0;
1829}
1830
cb9d97de
HK		 1831/* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
1832static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
2815b305 1833 u16 *cp01)
50970831
FR		 1834{
1835 const struct rtl_coalesce_info *ci;
1836 u16 i;
1837
ef2c0a78 1838 ci = rtl_coalesce_info(tp);
50970831 1839 if (IS_ERR(ci))
2815b305 1840 return PTR_ERR(ci);
50970831
FR		 1841
1842 for (i = 0; i < 4; i++) {
cb9d97de 1843 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
50970831 1844 *cp01 = i;
2815b305 1845 return ci->scale_nsecs[i];
50970831
FR		 1846 }
1847 }
1848
cb9d97de 1849 return -ERANGE;
50970831
FR		 1850}
1851
f3ccfda1
YM		 1852static int rtl_set_coalesce(struct net_device *dev,
1853 struct ethtool_coalesce *ec,
1854 struct kernel_ethtool_coalesce *kernel_coal,
1855 struct netlink_ext_ack *extack)
50970831
FR		 1856{
1857 struct rtl8169_private *tp = netdev_priv(dev);
2b3e48b6
HK		 1858 u32 tx_fr = ec->tx_max_coalesced_frames;
1859 u32 rx_fr = ec->rx_max_coalesced_frames;
1860 u32 coal_usec_max, units;
2815b305 1861 u16 w = 0, cp01 = 0;
2b3e48b6 1862 int scale;
50970831 1863
f1bce4ad
HK		 1864 if (rtl_is_8125(tp))
1865 return -EOPNOTSUPP;
1866
2b3e48b6
HK		 1867 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
1868 return -ERANGE;
1869
cb9d97de
HK		 1870 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
1871 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
2815b305
HK		 1872 if (scale < 0)
1873 return scale;
50970831 1874
2b3e48b6
HK		 1875 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
1876 * not only when usecs=0 because of e.g. the following scenario:
1877 *
1878 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1879 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1880 * - then user does `ethtool -C eth0 rx-usecs 100`
1881 *
1882 * Since ethtool sends to kernel whole ethtool_coalesce settings,
1883 * if we want to ignore rx_frames then it has to be set to 0.
1884 */
1885 if (rx_fr == 1)
1886 rx_fr = 0;
1887 if (tx_fr == 1)
1888 tx_fr = 0;
50970831 1889
81496b72
HK		 1890 /* HW requires time limit to be set if frame limit is set */
1891 if ((tx_fr && !ec->tx_coalesce_usecs) ||
1892 (rx_fr && !ec->rx_coalesce_usecs))
1893 return -EINVAL;
1894
2b3e48b6
HK		 1895 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
1896 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
50970831 1897
2b3e48b6
HK		 1898 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
1899 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
1900 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
1901 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
50970831 1902
2b3e48b6 1903 RTL_W16(tp, IntrMitigate, w);
50970831 1904
5cdfe830
HK		 1905 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
1906 if (rtl_is_8168evl_up(tp)) {
1907 if (!rx_fr && !tx_fr)
1908 /* disable packet counter */
1909 tp->cp_cmd |= PktCntrDisable;
1910 else
1911 tp->cp_cmd &= ~PktCntrDisable;
1912 }
1913
9a3c81fa 1914 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1ef7286e 1915 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
711463f8 1916 rtl_pci_commit(tp);
50970831 1917
50970831
FR		 1918 return 0;
1919}
1920
df6f1856
HK		 1921static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
1922{
1923 struct rtl8169_private *tp = netdev_priv(dev);
df6f1856 1924
2e779ddb
HK		 1925 if (!rtl_supports_eee(tp))
1926 return -EOPNOTSUPP;
1927
ec2f204b 1928 return phy_ethtool_get_eee(tp->phydev, data);
df6f1856
HK		 1929}
1930
1931static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
1932{
1933 struct rtl8169_private *tp = netdev_priv(dev);
2e779ddb
HK		 1934 int ret;
1935
1936 if (!rtl_supports_eee(tp))
1937 return -EOPNOTSUPP;
df6f1856 1938
2e779ddb 1939 ret = phy_ethtool_set_eee(tp->phydev, data);
7ec3f872
HK		 1940
1941 if (!ret)
1942 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
1943 MDIO_AN_EEE_ADV);
2e779ddb 1944 return ret;
df6f1856
HK		 1945}
1946
dc4aa50b 1947static void rtl8169_get_ringparam(struct net_device *dev,
74624944
HC		 1948 struct ethtool_ringparam *data,
1949 struct kernel_ethtool_ringparam *kernel_data,
1950 struct netlink_ext_ack *extack)
dc4aa50b
HK		 1951{
1952 data->rx_max_pending = NUM_RX_DESC;
1953 data->rx_pending = NUM_RX_DESC;
1954 data->tx_max_pending = NUM_TX_DESC;
1955 data->tx_pending = NUM_TX_DESC;
1956}
1957
216f78ea
HK		 1958static void rtl8169_get_pauseparam(struct net_device *dev,
1959 struct ethtool_pauseparam *data)
1960{
1961 struct rtl8169_private *tp = netdev_priv(dev);
1962 bool tx_pause, rx_pause;
1963
1964 phy_get_pause(tp->phydev, &tx_pause, &rx_pause);
1965
1966 data->autoneg = tp->phydev->autoneg;
1967 data->tx_pause = tx_pause ? 1 : 0;
1968 data->rx_pause = rx_pause ? 1 : 0;
1969}
1970
1971static int rtl8169_set_pauseparam(struct net_device *dev,
1972 struct ethtool_pauseparam *data)
1973{
1974 struct rtl8169_private *tp = netdev_priv(dev);
1975
1976 if (dev->mtu > ETH_DATA_LEN)
1977 return -EOPNOTSUPP;
1978
1979 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause);
1980
1981 return 0;
1982}
1983
7282d491 1984static const struct ethtool_ops rtl8169_ethtool_ops = {
b604eb31
JK		 1985 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1986 ETHTOOL_COALESCE_MAX_FRAMES,
1da177e4
LT		 1987 .get_drvinfo = rtl8169_get_drvinfo,
1988 .get_regs_len = rtl8169_get_regs_len,
1989 .get_link = ethtool_op_get_link,
50970831
FR		 1990 .get_coalesce = rtl_get_coalesce,
1991 .set_coalesce = rtl_set_coalesce,
1da177e4 1992 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1993 .get_wol = rtl8169_get_wol,
1994 .set_wol = rtl8169_set_wol,
d4a3a0fc 1995 .get_strings = rtl8169_get_strings,
b9f2c044 1996 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1997 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 1998 .get_ts_info = ethtool_op_get_ts_info,
dd84957e 1999 .nway_reset = phy_ethtool_nway_reset,
df6f1856
HK		 2000 .get_eee = rtl8169_get_eee,
2001 .set_eee = rtl8169_set_eee,
45772433
HK		 2002 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2003 .set_link_ksettings = phy_ethtool_set_link_ksettings,
dc4aa50b 2004 .get_ringparam = rtl8169_get_ringparam,
216f78ea
HK		 2005 .get_pauseparam = rtl8169_get_pauseparam,
2006 .set_pauseparam = rtl8169_set_pauseparam,
1da177e4
LT		 2007};
2008
b6c7fa40
HK		 2009static void rtl_enable_eee(struct rtl8169_private *tp)
2010{
2e779ddb 2011 struct phy_device *phydev = tp->phydev;
7ec3f872
HK		 2012 int adv;
2013
2014 /* respect EEE advertisement the user may have set */
2015 if (tp->eee_adv >= 0)
2016 adv = tp->eee_adv;
2017 else
2018 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
b6c7fa40 2019
7ec3f872
HK		 2020 if (adv >= 0)
2021 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
b6c7fa40
HK		 2022}
2023
f1f9ca28 2024static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
1da177e4 2025{
0e485150
FR		 2026 /*
2027 * The driver currently handles the 8168Bf and the 8168Be identically
2028 * but they can be identified more specifically through the test below
2029 * if needed:
2030 *
1ef7286e 2031 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2032 *
2033 * Same thing for the 8101Eb and the 8101Ec:
2034 *
1ef7286e 2035 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2036 */
3744100e 2037 static const struct rtl_mac_info {
55d2ad7b
HK		 2038 u16 mask;
2039 u16 val;
f1f9ca28 2040 enum mac_version ver;
1da177e4 2041 } mac_info[] = {
0439297b
HK		 2042 /* 8125B family. */
2043 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 },
2044
2045 /* 8125A family. */
4e9c91cf
HK		 2046 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 },
2047 /* It seems only XID 609 made it to the mass market.
2048 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
2049 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
2050 */
f1bce4ad 2051
1287723a 2052 /* RTL8117 */
e6d6ca6e 2053 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 },
1287723a
HK		 2054 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
2055
935e2218 2056 /* 8168EP family. */
55d2ad7b 2057 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2d6600c7
HK		 2058 /* It seems this chip version never made it to
2059 * the wild. Let's disable detection.
2060 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2061 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2062 */
935e2218 2063
6e1d0b89 2064 /* 8168H family. */
55d2ad7b 2065 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
6c8a5cf9
HK		 2066 /* It seems this chip version never made it to
2067 * the wild. Let's disable detection.
2068 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2069 */
6e1d0b89 2070
c558386b 2071 /* 8168G family. */
55d2ad7b
HK		 2072 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2073 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
364ef1f3
HK		 2074 /* It seems this chip version never made it to
2075 * the wild. Let's disable detection.
2076 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2077 */
55d2ad7b 2078 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
c558386b 2079
c2218925 2080 /* 8168F family. */
55d2ad7b 2081 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2ea26b4d 2082 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
55d2ad7b 2083 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
c2218925 2084
01dc7fec 2085 /* 8168E family. */
55d2ad7b
HK		 2086 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2087 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2088 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
01dc7fec 2089
5b538df9 2090 /* 8168D family. */
55d2ad7b
HK		 2091 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2092 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
5b538df9 2093
e6de30d6 2094 /* 8168DP family. */
beb401ec 2095 /* It seems this early RTL8168dp version never made it to
01649011 2096 * the wild. Support has been removed.
beb401ec
HK		 2097 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2098 */
55d2ad7b
HK		 2099 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2100 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
e6de30d6 2101
ef808d50 2102 /* 8168C family. */
55d2ad7b
HK		 2103 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2104 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2105 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2106 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2107 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2108 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2109 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2110
2111 /* 8168B family. */
55d2ad7b
HK		 2112 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2113 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
e3cf0cc0
FR		 2114
2115 /* 8101 family. */
55d2ad7b
HK		 2116 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2117 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2118 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2119 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2120 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2121 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2122 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2123 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
cdafdc29 2124 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 },
55d2ad7b
HK		 2125 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2126 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
e66d6586 2127 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 },
e3cf0cc0
FR		 2128
2129 /* 8110 family. */
55d2ad7b
HK		 2130 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2131 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2132 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2133 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2134 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
e3cf0cc0 2135
f21b75e9 2136 /* Catch-all */
55d2ad7b 2137 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2138 };
2139 const struct rtl_mac_info *p = mac_info;
f1f9ca28 2140 enum mac_version ver;
1da177e4 2141
f1f9ca28 2142 while ((xid & p->mask) != p->val)
1da177e4 2143 p++;
f1f9ca28
HK		 2144 ver = p->ver;
2145
2146 if (ver != RTL_GIGA_MAC_NONE && !gmii) {
2147 if (ver == RTL_GIGA_MAC_VER_42)
2148 ver = RTL_GIGA_MAC_VER_43;
f1f9ca28
HK		 2149 else if (ver == RTL_GIGA_MAC_VER_46)
2150 ver = RTL_GIGA_MAC_VER_48;
5d320a20 2151 }
f1f9ca28
HK		 2152
2153 return ver;
1da177e4
LT		 2154}
2155
f1e02ed1 2156static void rtl_release_firmware(struct rtl8169_private *tp)
2157{
254764e5 2158 if (tp->rtl_fw) {
47ad5931 2159 rtl_fw_release_firmware(tp->rtl_fw);
b6ffd97f 2160 kfree(tp->rtl_fw);
254764e5 2161 tp->rtl_fw = NULL;
b6ffd97f 2162 }
f1e02ed1 2163}
2164
2992bdfa 2165void r8169_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2166{
47dda786
HK		 2167 int val;
2168
ce8843ab 2169 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
89fbd26c 2170 if (tp->rtl_fw) {
ce8843ab 2171 rtl_fw_write_firmware(tp, tp->rtl_fw);
89fbd26c
HK		 2172 /* At least one firmware doesn't reset tp->ocp_base. */
2173 tp->ocp_base = OCP_STD_PHY_BASE;
47dda786
HK		 2174
2175 /* PHY soft reset may still be in progress */
2176 phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
2177 !(val & BMCR_RESET),
2178 50000, 600000, true);
89fbd26c 2179 }
953a12cc
FR		 2180}
2181
df6f1856
HK		 2182static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2183{
f452825d
HK		 2184 /* Adjust EEE LED frequency */
2185 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2186 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2187
54113ded 2188 rtl_eri_set_bits(tp, 0x1b0, 0x0003);
df6f1856
HK		 2189}
2190
4640338c 2191static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
b3a42e3a
HK		 2192{
2193 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2194 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2195}
2196
0439297b
HK		 2197static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp)
2198{
2199 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20);
2200}
2201
2202static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
2203{
2204 rtl8125_set_eee_txidle_timer(tp);
2205 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2206}
2207
ae1e82c6 2208static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr)
9ecb9aab 2209{
ae1e82c6
HK		 2210 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr));
2211 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4));
2212 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16);
2213 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2));
9ecb9aab 2214}
2215
2992bdfa 2216u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
3127f7c9
HK		 2217{
2218 u16 data1, data2, ioffset;
2219
2220 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2221 data1 = r8168_mac_ocp_read(tp, 0xdd02);
2222 data2 = r8168_mac_ocp_read(tp, 0xdd00);
2223
2224 ioffset = (data2 >> 1) & 0x7ff8;
2225 ioffset |= data2 & 0x0007;
2226 if (data1 & BIT(7))
2227 ioffset |= BIT(15);
2228
2229 return ioffset;
2230}
2231
da78dbff
FR		 2232static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2233{
3f6ca6c7
HK		 2234 set_bit(flag, tp->wk.flags);
2235 schedule_work(&tp->wk.work);
da78dbff
FR		 2236}
2237
b5aed0b3 2238static void rtl8169_init_phy(struct rtl8169_private *tp)
4ff96fa6 2239{
becd837e 2240 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
4ff96fa6 2241
77332894 2242 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
7a67e11d
HK		 2243 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2244 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
b5aed0b3 2245 /* set undocumented MAC Reg C+CR Offset 0x82h */
1ef7286e 2246 RTL_W8(tp, 0x82, 0x01);
77332894 2247 }
4ff96fa6 2248
fc712387
HK		 2249 if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2250 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2251 tp->pci_dev->subsystem_device == 0xe000)
2252 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2253
5b7ad4b7 2254 /* We may have called phy_speed_down before */
703732f0 2255 phy_speed_up(tp->phydev);
5b7ad4b7 2256
af779778
HK		 2257 if (rtl_supports_eee(tp))
2258 rtl_enable_eee(tp);
2259
703732f0 2260 genphy_soft_reset(tp->phydev);
4ff96fa6
FR		 2261}
2262
ae1e82c6 2263static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr)
773d2021 2264{
df320ed7 2265 rtl_unlock_config_regs(tp);
908ba2bf 2266
ae1e82c6 2267 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4));
711463f8 2268 rtl_pci_commit(tp);
908ba2bf 2269
ae1e82c6 2270 RTL_W32(tp, MAC0, get_unaligned_le32(addr));
711463f8 2271 rtl_pci_commit(tp);
908ba2bf 2272
9ecb9aab 2273 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2274 rtl_rar_exgmac_set(tp, addr);
c28aa385 2275
df320ed7 2276 rtl_lock_config_regs(tp);
773d2021
FR		 2277}
2278
2279static int rtl_set_mac_address(struct net_device *dev, void *p)
2280{
2281 struct rtl8169_private *tp = netdev_priv(dev);
1f7aa2bc 2282 int ret;
773d2021 2283
1f7aa2bc
HK		 2284 ret = eth_mac_addr(dev, p);
2285 if (ret)
2286 return ret;
773d2021 2287
ec2f204b 2288 rtl_rar_set(tp, dev->dev_addr);
773d2021
FR		 2289
2290 return 0;
2291}
2292
e542a226
HW		 2293static void rtl_init_rxcfg(struct rtl8169_private *tp)
2294{
e542a226 2295 switch (tp->mac_version) {
e9588eb9 2296 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2a71883c 2297 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
1ef7286e 2298 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
e542a226 2299 break;
2a71883c 2300 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
511cfd58
MS		 2301 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2302 case RTL_GIGA_MAC_VER_38:
1ef7286e 2303 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
e542a226 2304 break;
e6d6ca6e 2305 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
1ef7286e 2306 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
beb330a4 2307 break;
efc37109 2308 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
10478283 2309 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
f1bce4ad 2310 break;
e542a226 2311 default:
1ef7286e 2312 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
e542a226
HW		 2313 break;
2314 }
2315}
2316
92fc43b4
HW		 2317static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2318{
9fba0812 2319 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 2320}
2321
d58d46b5
FR		 2322static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
2323{
1ef7286e
AS		 2324 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2325 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
d58d46b5
FR		 2326}
2327
2328static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
2329{
1ef7286e
AS		 2330 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2331 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
d58d46b5
FR		 2332}
2333
2334static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
2335{
1ef7286e 2336 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
d58d46b5
FR		 2337}
2338
2339static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
2340{
1ef7286e 2341 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
d58d46b5
FR		 2342}
2343
2344static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
2345{
6cf73913 2346 RTL_W8(tp, MaxTxPacketSize, 0x24);
1ef7286e
AS		 2347 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2348 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
d58d46b5
FR		 2349}
2350
2351static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
2352{
6cf73913 2353 RTL_W8(tp, MaxTxPacketSize, 0x3f);
1ef7286e
AS		 2354 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2355 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
d58d46b5
FR		 2356}
2357
d58d46b5
FR		 2358static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
2359{
1ef7286e 2360 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
d58d46b5
FR		 2361}
2362
2363static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
2364{
1ef7286e 2365 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
d58d46b5
FR		 2366}
2367
9db0ac57 2368static void rtl_jumbo_config(struct rtl8169_private *tp)
d58d46b5 2369{
9db0ac57 2370 bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
5e00e16c 2371 int readrq = 4096;
d58d46b5 2372
485bb1b3
HK		 2373 rtl_unlock_config_regs(tp);
2374 switch (tp->mac_version) {
485bb1b3 2375 case RTL_GIGA_MAC_VER_17:
9db0ac57 2376 if (jumbo) {
5e00e16c 2377 readrq = 512;
9db0ac57
HK		 2378 r8168b_1_hw_jumbo_enable(tp);
2379 } else {
2380 r8168b_1_hw_jumbo_disable(tp);
2381 }
485bb1b3
HK		 2382 break;
2383 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
9db0ac57 2384 if (jumbo) {
5e00e16c 2385 readrq = 512;
9db0ac57
HK		 2386 r8168c_hw_jumbo_enable(tp);
2387 } else {
2388 r8168c_hw_jumbo_disable(tp);
2389 }
485bb1b3 2390 break;
01649011 2391 case RTL_GIGA_MAC_VER_28:
9db0ac57
HK		 2392 if (jumbo)
2393 r8168dp_hw_jumbo_enable(tp);
2394 else
2395 r8168dp_hw_jumbo_disable(tp);
485bb1b3 2396 break;
0fc75219 2397 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2007317e 2398 if (jumbo)
9db0ac57 2399 r8168e_hw_jumbo_enable(tp);
2007317e 2400 else
9db0ac57 2401 r8168e_hw_jumbo_disable(tp);
485bb1b3 2402 break;
d58d46b5 2403 default:
d58d46b5
FR		 2404 break;
2405 }
485bb1b3 2406 rtl_lock_config_regs(tp);
21b5f672 2407
5e00e16c
HK		 2408 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2409 pcie_set_readrq(tp->pci_dev, readrq);
453a7789
HK		 2410
2411 /* Chip doesn't support pause in jumbo mode */
11ac4e66
HK		 2412 if (jumbo) {
2413 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2414 tp->phydev->advertising);
2415 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2416 tp->phydev->advertising);
2417 phy_start_aneg(tp->phydev);
2418 }
d58d46b5
FR		 2419}
2420
ffc46952
FR		 2421DECLARE_RTL_COND(rtl_chipcmd_cond)
2422{
1ef7286e 2423 return RTL_R8(tp, ChipCmd) & CmdReset;
ffc46952
FR		 2424}
2425
6f43adc8
FR		 2426static void rtl_hw_reset(struct rtl8169_private *tp)
2427{
1ef7286e 2428 RTL_W8(tp, ChipCmd, CmdReset);
6f43adc8 2429
d6836ef0 2430 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 2431}
2432
254764e5 2433static void rtl_request_firmware(struct rtl8169_private *tp)
953a12cc 2434{
b6ffd97f 2435 struct rtl_fw *rtl_fw;
953a12cc 2436
254764e5
HK		 2437 /* firmware loaded already or no firmware available */
2438 if (tp->rtl_fw || !tp->fw_name)
2439 return;
953a12cc 2440
b6ffd97f 2441 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3bf6ff3c 2442 if (!rtl_fw)
47ad5931 2443 return;
31bd204f 2444
ce8843ab
HK		 2445 rtl_fw->phy_write = rtl_writephy;
2446 rtl_fw->phy_read = rtl_readphy;
2447 rtl_fw->mac_mcu_write = mac_mcu_write;
2448 rtl_fw->mac_mcu_read = mac_mcu_read;
4edb00f3
HK		 2449 rtl_fw->fw_name = tp->fw_name;
2450 rtl_fw->dev = tp_to_dev(tp);
ce8843ab 2451
47ad5931
HK		 2452 if (rtl_fw_request_firmware(rtl_fw))
2453 kfree(rtl_fw);
2454 else
2455 tp->rtl_fw = rtl_fw;
953a12cc
FR		 2456}
2457
92fc43b4
HW		 2458static void rtl_rx_close(struct rtl8169_private *tp)
2459{
1ef7286e 2460 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 2461}
2462
ffc46952
FR		 2463DECLARE_RTL_COND(rtl_npq_cond)
2464{
1ef7286e 2465 return RTL_R8(tp, TxPoll) & NPQ;
ffc46952
FR		 2466}
2467
2468DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2469{
1ef7286e 2470 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
ffc46952
FR		 2471}
2472
6f9395c6
HK		 2473DECLARE_RTL_COND(rtl_rxtx_empty_cond)
2474{
2475 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2476}
2477
0439297b
HK		 2478DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)
2479{
2480 /* IntrMitigate has new functionality on RTL8125 */
2481 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2482}
2483
6f9395c6
HK		 2484static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2485{
2486 switch (tp->mac_version) {
e6d6ca6e 2487 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
6f9395c6
HK		 2488 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
2489 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2490 break;
efc37109 2491 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61:
6f9395c6
HK		 2492 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2493 break;
0439297b
HK		 2494 case RTL_GIGA_MAC_VER_63:
2495 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2496 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2497 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
2498 break;
6f9395c6
HK		 2499 default:
2500 break;
2501 }
2502}
2503
3406079b
CL		 2504static void rtl_disable_rxdvgate(struct rtl8169_private *tp)
2505{
2506 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2507}
2508
9617886f
HK		 2509static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2510{
2511 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2512 fsleep(2000);
6f9395c6 2513 rtl_wait_txrx_fifo_empty(tp);
9617886f
HK		 2514}
2515
ad425666
CL		 2516static void rtl_wol_enable_rx(struct rtl8169_private *tp)
2517{
2518 if (tp->mac_version >= RTL_GIGA_MAC_VER_25)
2519 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2520 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
bb41c13c
CL		 2521
2522 if (tp->mac_version >= RTL_GIGA_MAC_VER_40)
2523 rtl_disable_rxdvgate(tp);
ad425666
CL		 2524}
2525
2526static void rtl_prepare_power_down(struct rtl8169_private *tp)
2527{
0ab0c45d 2528 if (tp->dash_enabled)
ad425666
CL		 2529 return;
2530
2531 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2532 tp->mac_version == RTL_GIGA_MAC_VER_33)
2533 rtl_ephy_write(tp, 0x19, 0xff64);
2534
2535 if (device_may_wakeup(tp_to_dev(tp))) {
2536 phy_speed_down(tp->phydev, false);
2537 rtl_wol_enable_rx(tp);
2538 }
2539}
2540
05212ba8 2541static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
9cb427b6 2542{
ad5f97fa
HK		 2543 u32 val = TX_DMA_BURST << TxDMAShift |
2544 InterFrameGap << TxInterFrameGapShift;
2545
9e9f33ba 2546 if (rtl_is_8168evl_up(tp))
ad5f97fa
HK		 2547 val |= TXCFG_AUTO_FIFO;
2548
2549 RTL_W32(tp, TxConfig, val);
9cb427b6
FR		 2550}
2551
4fd48c4a 2552static void rtl_set_rx_max_size(struct rtl8169_private *tp)
1da177e4 2553{
4fd48c4a
HK		 2554 /* Low hurts. Let's disable the filtering. */
2555 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
07ce4064
FR		 2556}
2557
1ef7286e 2558static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
7f796d83
FR		 2559{
2560 /*
2561 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2562 * register to be written before TxDescAddrLow to work.
2563 * Switching from MMIO to I/O access fixes the issue as well.
2564 */
1ef7286e
AS		 2565 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2566 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2567 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2568 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 2569}
2570
ef891284 2571static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
6dccd16b 2572{
34bc0095
HK		 2573 u32 val;
2574
2575 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2576 val = 0x000fff00;
2577 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2578 val = 0x00ffff00;
2579 else
2580 return;
2581
2582 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2583 val |= 0xff;
2584
2585 RTL_W32(tp, 0x7c, val);
6dccd16b
FR		 2586}
2587
e6b763ea
FR		 2588static void rtl_set_rx_mode(struct net_device *dev)
2589{
81cd17a4
HK		 2590 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2591 /* Multicast hash filter */
2592 u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
e6b763ea 2593 struct rtl8169_private *tp = netdev_priv(dev);
81cd17a4 2594 u32 tmp;
e6b763ea
FR		 2595
2596 if (dev->flags & IFF_PROMISC) {
81cd17a4 2597 rx_mode |= AcceptAllPhys;
8999ce4c
HK		 2598 } else if (!(dev->flags & IFF_MULTICAST)) {
2599 rx_mode &= ~AcceptMulticast;
81cd17a4
HK		 2600 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
2601 dev->flags & IFF_ALLMULTI ||
6a263102 2602 tp->mac_version == RTL_GIGA_MAC_VER_35) {
81cd17a4
HK		 2603 /* accept all multicasts */
2604 } else if (netdev_mc_empty(dev)) {
2605 rx_mode &= ~AcceptMulticast;
e6b763ea
FR		 2606 } else {
2607 struct netdev_hw_addr *ha;
2608
e6b763ea
FR		 2609 mc_filter[1] = mc_filter[0] = 0;
2610 netdev_for_each_mc_addr(ha, dev) {
bc54ac36 2611 u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
81cd17a4
HK		 2612 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2613 }
2614
2615 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2616 tmp = mc_filter[0];
2617 mc_filter[0] = swab32(mc_filter[1]);
2618 mc_filter[1] = swab32(tmp);
e6b763ea
FR		 2619 }
2620 }
2621
1ef7286e
AS		 2622 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2623 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
e6b763ea 2624
81cd17a4 2625 tmp = RTL_R32(tp, RxConfig);
10478283 2626 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
e6b763ea
FR		 2627}
2628
ffc46952
FR		 2629DECLARE_RTL_COND(rtl_csiar_cond)
2630{
1ef7286e 2631 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
ffc46952
FR		 2632}
2633
ff1d7331 2634static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
beb1fe18 2635{
ff1d7331 2636 u32 func = PCI_FUNC(tp->pci_dev->devfn);
beb1fe18 2637
1ef7286e
AS		 2638 RTL_W32(tp, CSIDR, value);
2639 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
ff1d7331 2640 CSIAR_BYTE_ENABLE | func << 16);
7e18dca1 2641
d6836ef0 2642 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 2643}
2644
ff1d7331 2645static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 2646{
ff1d7331
HK		 2647 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2648
2649 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2650 CSIAR_BYTE_ENABLE);
7e18dca1 2651
d6836ef0 2652 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
1ef7286e 2653 RTL_R32(tp, CSIDR) : ~0;
7e18dca1
HW		 2654}
2655
c07c8ffc 2656static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val)
45dd95c4 2657{
ff1d7331
HK		 2658 struct pci_dev *pdev = tp->pci_dev;
2659 u32 csi;
45dd95c4 2660
ff1d7331
HK		 2661 /* According to Realtek the value at config space address 0x070f
2662 * controls the L0s/L1 entrance latency. We try standard ECAM access
2663 * first and if it fails fall back to CSI.
c07c8ffc
HK		 2664 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo)
2665 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us
ff1d7331
HK		 2666 */
2667 if (pdev->cfg_size > 0x070f &&
2668 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
2669 return;
2670
2671 netdev_notice_once(tp->dev,
2672 "No native access to PCI extended config space, falling back to CSI\n");
2673 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2674 rtl_csi_write(tp, 0x070c, csi | val << 24);
45dd95c4 2675}
2676
f37658da 2677static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
beb1fe18 2678{
c07c8ffc
HK		 2679 /* L0 7us, L1 16us */
2680 rtl_set_aspm_entry_latency(tp, 0x27);
dacf8154
FR		 2681}
2682
2683struct ephy_info {
2684 unsigned int offset;
2685 u16 mask;
2686 u16 bits;
2687};
2688
1791ad50
HK		 2689static void __rtl_ephy_init(struct rtl8169_private *tp,
2690 const struct ephy_info *e, int len)
dacf8154
FR		 2691{
2692 u16 w;
2693
2694 while (len-- > 0) {
fdf6fc06
FR		 2695 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2696 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 2697 e++;
2698 }
2699}
2700
1791ad50
HK		 2701#define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2702
73c86ee3 2703static void rtl_disable_clock_request(struct rtl8169_private *tp)
b726e493 2704{
73c86ee3 2705 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 2706 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 2707}
2708
73c86ee3 2709static void rtl_enable_clock_request(struct rtl8169_private *tp)
e6de30d6 2710{
73c86ee3 2711 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 2712 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 2713}
2714
c259b7f4 2715static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
b51ecea8 2716{
c259b7f4
HK		 2717 /* work around an issue when PCI reset occurs during L2/L3 state */
2718 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
b51ecea8 2719}
2720
4b33433e
HK		 2721static void rtl_enable_exit_l1(struct rtl8169_private *tp)
2722{
2723 /* Bits control which events trigger ASPM L1 exit:
2724 * Bit 12: rxdv
2725 * Bit 11: ltr_msg
2726 * Bit 10: txdma_poll
2727 * Bit 9: xadm
2728 * Bit 8: pktavi
2729 * Bit 7: txpla
2730 */
2731 switch (tp->mac_version) {
2732 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2733 rtl_eri_set_bits(tp, 0xd4, 0x1f00);
2734 break;
2735 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38:
2736 rtl_eri_set_bits(tp, 0xd4, 0x0c00);
2737 break;
d192181c 2738 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
4b33433e
HK		 2739 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80);
2740 break;
2741 default:
2742 break;
2743 }
2744}
2745
d192181c
HK		 2746static void rtl_disable_exit_l1(struct rtl8169_private *tp)
2747{
2748 switch (tp->mac_version) {
2749 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
2750 rtl_eri_clear_bits(tp, 0xd4, 0x1f00);
2751 break;
2752 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
2753 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0);
2754 break;
2755 default:
2756 break;
2757 }
2758}
2759
a99790bf
KHF		 2760static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2761{
49ef7d84
HK		 2762 if (tp->mac_version < RTL_GIGA_MAC_VER_32)
2763 return;
2764
cf2ffdea
HK		 2765 /* Don't enable ASPM in the chip if OS can't control ASPM */
2766 if (enable && tp->aspm_manageable) {
162d626f
HK		 2767 /* On these chip versions ASPM can even harm
2768 * bus communication of other PCI devices.
2769 */
2770 if (tp->mac_version == RTL_GIGA_MAC_VER_42 ||
2771 tp->mac_version == RTL_GIGA_MAC_VER_43)
2772 return;
2773
6bc6c4e6
HK		 2774 rtl_mod_config5(tp, 0, ASPM_en);
2775 rtl_mod_config2(tp, 0, ClkReqEn);
c217ab7a
HK		 2776
2777 switch (tp->mac_version) {
ebe59898 2778 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
efc37109 2779 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
c217ab7a
HK		 2780 /* reset ephy tx/rx disable timer */
2781 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0);
2782 /* chip can trigger L1.2 */
2783 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2));
2784 break;
2785 default:
2786 break;
2787 }
a99790bf 2788 } else {
c217ab7a 2789 switch (tp->mac_version) {
ebe59898 2790 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
efc37109 2791 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
c217ab7a
HK		 2792 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0);
2793 break;
2794 default:
2795 break;
2796 }
2797
6bc6c4e6
HK		 2798 rtl_mod_config2(tp, ClkReqEn, 0);
2799 rtl_mod_config5(tp, ASPM_en, 0);
a99790bf
KHF		 2800 }
2801}
2802
6b1bd242
HK		 2803static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2804 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
2805{
2806 /* Usage of dynamic vs. static FIFO is controlled by bit
2807 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
2808 */
2809 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
2810 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
2811}
2812
0ebacd12
HK		 2813static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
2814 u8 low, u8 high)
2815{
2816 /* FIFO thresholds for pause flow control */
2817 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
2818 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
2819}
2820
94b5ff74 2821static void rtl_hw_start_8168b(struct rtl8169_private *tp)
219a1e9d 2822{
1ef7286e 2823 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
219a1e9d
FR		 2824}
2825
beb1fe18 2826static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 2827{
1ef7286e 2828 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
b726e493 2829
1ef7286e 2830 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
b726e493 2831
73c86ee3 2832 rtl_disable_clock_request(tp);
219a1e9d
FR		 2833}
2834
beb1fe18 2835static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 2836{
350f7596 2837 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 2838 { 0x01, 0, 0x0001 },
2839 { 0x02, 0x0800, 0x1000 },
2840 { 0x03, 0, 0x0042 },
2841 { 0x06, 0x0080, 0x0000 },
2842 { 0x07, 0, 0x2000 }
2843 };
2844
f37658da 2845 rtl_set_def_aspm_entry_latency(tp);
b726e493 2846
1791ad50 2847 rtl_ephy_init(tp, e_info_8168cp);
b726e493 2848
beb1fe18 2849 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 2850}
2851
beb1fe18 2852static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 2853{
f37658da 2854 rtl_set_def_aspm_entry_latency(tp);
ef3386f0 2855
1ef7286e 2856 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
ef3386f0
FR		 2857}
2858
beb1fe18 2859static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 2860{
f37658da 2861 rtl_set_def_aspm_entry_latency(tp);
7f3e3d3a 2862
1ef7286e 2863 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
7f3e3d3a
FR		 2864
2865 /* Magic. */
1ef7286e 2866 RTL_W8(tp, DBG_REG, 0x20);
7f3e3d3a
FR		 2867}
2868
beb1fe18 2869static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 2870{
350f7596 2871 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 2872 { 0x02, 0x0800, 0x1000 },
2873 { 0x03, 0, 0x0002 },
2874 { 0x06, 0x0080, 0x0000 }
2875 };
2876
f37658da 2877 rtl_set_def_aspm_entry_latency(tp);
b726e493 2878
1ef7286e 2879 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
b726e493 2880
1791ad50 2881 rtl_ephy_init(tp, e_info_8168c_1);
b726e493 2882
beb1fe18 2883 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 2884}
2885
beb1fe18 2886static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 2887{
350f7596 2888 static const struct ephy_info e_info_8168c_2[] = {
b726e493 2889 { 0x01, 0, 0x0001 },
a7a92cf8 2890 { 0x03, 0x0400, 0x0020 }
b726e493
FR		 2891 };
2892
f37658da 2893 rtl_set_def_aspm_entry_latency(tp);
b726e493 2894
1791ad50 2895 rtl_ephy_init(tp, e_info_8168c_2);
b726e493 2896
beb1fe18 2897 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 2898}
2899
beb1fe18 2900static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 2901{
f37658da 2902 rtl_set_def_aspm_entry_latency(tp);
6fb07058 2903
beb1fe18 2904 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 2905}
2906
beb1fe18 2907static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 2908{
f37658da 2909 rtl_set_def_aspm_entry_latency(tp);
5b538df9 2910
73c86ee3 2911 rtl_disable_clock_request(tp);
5b538df9
FR		 2912}
2913
beb1fe18 2914static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 2915{
2916 static const struct ephy_info e_info_8168d_4[] = {
1016a4a1
CHL		 2917 { 0x0b, 0x0000, 0x0048 },
2918 { 0x19, 0x0020, 0x0050 },
a7a92cf8
HK		 2919 { 0x0c, 0x0100, 0x0020 },
2920 { 0x10, 0x0004, 0x0000 },
e6de30d6 2921 };
e6de30d6 2922
f37658da 2923 rtl_set_def_aspm_entry_latency(tp);
e6de30d6 2924
1791ad50 2925 rtl_ephy_init(tp, e_info_8168d_4);
e6de30d6 2926
73c86ee3 2927 rtl_enable_clock_request(tp);
e6de30d6 2928}
2929
beb1fe18 2930static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 2931{
70090424 2932 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 2933 { 0x00, 0x0200, 0x0100 },
2934 { 0x00, 0x0000, 0x0004 },
2935 { 0x06, 0x0002, 0x0001 },
2936 { 0x06, 0x0000, 0x0030 },
2937 { 0x07, 0x0000, 0x2000 },
2938 { 0x00, 0x0000, 0x0020 },
2939 { 0x03, 0x5800, 0x2000 },
2940 { 0x03, 0x0000, 0x0001 },
2941 { 0x01, 0x0800, 0x1000 },
2942 { 0x07, 0x0000, 0x4000 },
2943 { 0x1e, 0x0000, 0x2000 },
2944 { 0x19, 0xffff, 0xfe6c },
2945 { 0x0a, 0x0000, 0x0040 }
2946 };
2947
f37658da 2948 rtl_set_def_aspm_entry_latency(tp);
01dc7fec 2949
1791ad50 2950 rtl_ephy_init(tp, e_info_8168e_1);
01dc7fec 2951
73c86ee3 2952 rtl_disable_clock_request(tp);
01dc7fec 2953
2954 /* Reset tx FIFO pointer */
1ef7286e
AS		 2955 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
2956 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
01dc7fec 2957
6bc6c4e6 2958 rtl_mod_config5(tp, Spi_en, 0);
01dc7fec 2959}
2960
beb1fe18 2961static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424
HW		 2962{
2963 static const struct ephy_info e_info_8168e_2[] = {
2964 { 0x09, 0x0000, 0x0080 },
a7a92cf8
HK		 2965 { 0x19, 0x0000, 0x0224 },
2966 { 0x00, 0x0000, 0x0004 },
2967 { 0x0c, 0x3df0, 0x0200 },
70090424
HW		 2968 };
2969
f37658da 2970 rtl_set_def_aspm_entry_latency(tp);
70090424 2971
1791ad50 2972 rtl_ephy_init(tp, e_info_8168e_2);
70090424 2973
724c6fd0 2974 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
33b00ca1 2975 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
6b1bd242 2976 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
33b00ca1
HK		 2977 rtl_eri_set_bits(tp, 0x1d0, BIT(1));
2978 rtl_reset_packet_filter(tp);
2979 rtl_eri_set_bits(tp, 0x1b0, BIT(4));
724c6fd0
HK		 2980 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2981 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
70090424 2982
73c86ee3 2983 rtl_disable_clock_request(tp);
4521e1a9 2984
1ef7286e 2985 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
70090424 2986
cc07d271
HK		 2987 rtl8168_config_eee_mac(tp);
2988
1ef7286e
AS		 2989 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2990 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
6bc6c4e6 2991 rtl_mod_config5(tp, Spi_en, 0);
70090424
HW		 2992}
2993
5f886e08 2994static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 2995{
f37658da 2996 rtl_set_def_aspm_entry_latency(tp);
c2218925 2997
724c6fd0 2998 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
d05890c5 2999 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
6b1bd242 3000 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4e7e4621 3001 rtl_reset_packet_filter(tp);
54113ded 3002 rtl_eri_set_bits(tp, 0x1b0, BIT(4));
d05890c5 3003 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
724c6fd0
HK		 3004 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
3005 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
c2218925 3006
73c86ee3 3007 rtl_disable_clock_request(tp);
4521e1a9 3008
1ef7286e
AS		 3009 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3010 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3011 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
6bc6c4e6 3012 rtl_mod_config5(tp, Spi_en, 0);
cc07d271
HK		 3013
3014 rtl8168_config_eee_mac(tp);
c2218925
HW		 3015}
3016
5f886e08
HW		 3017static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
3018{
5f886e08
HW		 3019 static const struct ephy_info e_info_8168f_1[] = {
3020 { 0x06, 0x00c0, 0x0020 },
3021 { 0x08, 0x0001, 0x0002 },
3022 { 0x09, 0x0000, 0x0080 },
a7a92cf8 3023 { 0x19, 0x0000, 0x0224 },
709a16be 3024 { 0x00, 0x0000, 0x0008 },
a7a92cf8 3025 { 0x0c, 0x3df0, 0x0200 },
5f886e08
HW		 3026 };
3027
3028 rtl_hw_start_8168f(tp);
3029
1791ad50 3030 rtl_ephy_init(tp, e_info_8168f_1);
5f886e08
HW		 3031}
3032
b3d7b2f2
HW		 3033static void rtl_hw_start_8411(struct rtl8169_private *tp)
3034{
b3d7b2f2
HW		 3035 static const struct ephy_info e_info_8168f_1[] = {
3036 { 0x06, 0x00c0, 0x0020 },
3037 { 0x0f, 0xffff, 0x5200 },
a7a92cf8 3038 { 0x19, 0x0000, 0x0224 },
709a16be 3039 { 0x00, 0x0000, 0x0008 },
a7a92cf8 3040 { 0x0c, 0x3df0, 0x0200 },
b3d7b2f2
HW		 3041 };
3042
3043 rtl_hw_start_8168f(tp);
c259b7f4 3044 rtl_pcie_state_l2l3_disable(tp);
b3d7b2f2 3045
1791ad50 3046 rtl_ephy_init(tp, e_info_8168f_1);
b3d7b2f2
HW		 3047}
3048
5fbea337 3049static void rtl_hw_start_8168g(struct rtl8169_private *tp)
c558386b 3050{
6b1bd242 3051 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
0ebacd12 3052 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
c558386b 3053
f37658da 3054 rtl_set_def_aspm_entry_latency(tp);
c558386b 3055
4e7e4621 3056 rtl_reset_packet_filter(tp);
724c6fd0 3057 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
c558386b 3058
3406079b 3059 rtl_disable_rxdvgate(tp);
c558386b 3060
724c6fd0
HK		 3061 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3062 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
c558386b 3063
df6f1856
HK		 3064 rtl8168_config_eee_mac(tp);
3065
54113ded
HK		 3066 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3067 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
b51ecea8 3068
c259b7f4 3069 rtl_pcie_state_l2l3_disable(tp);
c558386b
HW		 3070}
3071
5fbea337
CHL		 3072static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
3073{
5fbea337 3074 static const struct ephy_info e_info_8168g_1[] = {
a7a92cf8
HK		 3075 { 0x00, 0x0008, 0x0000 },
3076 { 0x0c, 0x3ff0, 0x0820 },
5fbea337
CHL		 3077 { 0x1e, 0x0000, 0x0001 },
3078 { 0x19, 0x8000, 0x0000 }
3079 };
3080
3081 rtl_hw_start_8168g(tp);
1791ad50 3082 rtl_ephy_init(tp, e_info_8168g_1);
5fbea337
CHL		 3083}
3084
57538c4a 3085static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
3086{
57538c4a 3087 static const struct ephy_info e_info_8168g_2[] = {
a7a92cf8
HK		 3088 { 0x00, 0x0008, 0x0000 },
3089 { 0x0c, 0x3ff0, 0x0820 },
3090 { 0x19, 0xffff, 0x7c00 },
3091 { 0x1e, 0xffff, 0x20eb },
3092 { 0x0d, 0xffff, 0x1666 },
3093 { 0x00, 0xffff, 0x10a3 },
3094 { 0x06, 0xffff, 0xf050 },
3095 { 0x04, 0x0000, 0x0010 },
3096 { 0x1d, 0x4000, 0x0000 },
57538c4a 3097 };
3098
5fbea337 3099 rtl_hw_start_8168g(tp);
1791ad50 3100 rtl_ephy_init(tp, e_info_8168g_2);
57538c4a 3101}
3102
45dd95c4 3103static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
3104{
45dd95c4 3105 static const struct ephy_info e_info_8411_2[] = {
a7a92cf8
HK		 3106 { 0x00, 0x0008, 0x0000 },
3107 { 0x0c, 0x37d0, 0x0820 },
3108 { 0x1e, 0x0000, 0x0001 },
3109 { 0x19, 0x8021, 0x0000 },
3110 { 0x1e, 0x0000, 0x2000 },
3111 { 0x0d, 0x0100, 0x0200 },
3112 { 0x00, 0x0000, 0x0080 },
3113 { 0x06, 0x0000, 0x0010 },
3114 { 0x04, 0x0000, 0x0010 },
3115 { 0x1d, 0x0000, 0x4000 },
45dd95c4 3116 };
3117
5fbea337 3118 rtl_hw_start_8168g(tp);
45dd95c4 3119
1791ad50 3120 rtl_ephy_init(tp, e_info_8411_2);
fe4e8db0
HK		 3121
3122 /* The following Realtek-provided magic fixes an issue with the RX unit
3123 * getting confused after the PHY having been powered-down.
3124 */
3125 r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3126 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3127 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3128 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
3129 r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
3130 r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
3131 r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
3132 r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
3133 mdelay(3);
3134 r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
3135
3136 r8168_mac_ocp_write(tp, 0xF800, 0xE008);
3137 r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
3138 r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
3139 r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
3140 r8168_mac_ocp_write(tp, 0xF808, 0xE027);
3141 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
3142 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
3143 r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
3144 r8168_mac_ocp_write(tp, 0xF810, 0xC602);
3145 r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
3146 r8168_mac_ocp_write(tp, 0xF814, 0x0000);
3147 r8168_mac_ocp_write(tp, 0xF816, 0xC502);
3148 r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
3149 r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
3150 r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
3151 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
3152 r8168_mac_ocp_write(tp, 0xF820, 0x080A);
3153 r8168_mac_ocp_write(tp, 0xF822, 0x6420);
3154 r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
3155 r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
3156 r8168_mac_ocp_write(tp, 0xF828, 0xC516);
3157 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
3158 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
3159 r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
3160 r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
3161 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
3162 r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
3163 r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
3164 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
3165 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
3166 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
3167 r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
3168 r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
3169 r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
3170 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
3171 r8168_mac_ocp_write(tp, 0xF846, 0xC404);
3172 r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
3173 r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
3174 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
3175 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
3176 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
3177 r8168_mac_ocp_write(tp, 0xF852, 0xE434);
3178 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
3179 r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
3180 r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
3181 r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
3182 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
3183 r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
3184 r8168_mac_ocp_write(tp, 0xF860, 0xF007);
3185 r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
3186 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
3187 r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
3188 r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
3189 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
3190 r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
3191 r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
3192 r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
3193 r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
3194 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
3195 r8168_mac_ocp_write(tp, 0xF876, 0xC516);
3196 r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
3197 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
3198 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
3199 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
3200 r8168_mac_ocp_write(tp, 0xF880, 0xC512);
3201 r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
3202 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
3203 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
3204 r8168_mac_ocp_write(tp, 0xF888, 0x483F);
3205 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
3206 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
3207 r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
3208 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
3209 r8168_mac_ocp_write(tp, 0xF892, 0xC505);
3210 r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
3211 r8168_mac_ocp_write(tp, 0xF896, 0xC502);
3212 r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
3213 r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
3214 r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
3215 r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
3216 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
3217 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
3218 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
3219 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
3220 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
3221 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
3222 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
3223 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
3224 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
3225 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
3226 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
3227 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
3228 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
3229 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
3230 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
3231 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
3232 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
3233 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
3234 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
3235 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
3236 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
3237 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
3238 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
3239 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
3240 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
3241 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
3242 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
3243 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
3244 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
3245 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
3246 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
3247
3248 r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3249
3250 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3251 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3252 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3253 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3254 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3255 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3256 r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
45dd95c4 3257}
3258
6e1d0b89
CHL		 3259static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3260{
6e1d0b89
CHL		 3261 static const struct ephy_info e_info_8168h_1[] = {
3262 { 0x1e, 0x0800, 0x0001 },
3263 { 0x1d, 0x0000, 0x0800 },
3264 { 0x05, 0xffff, 0x2089 },
3265 { 0x06, 0xffff, 0x5881 },
a7a92cf8 3266 { 0x04, 0xffff, 0x854a },
6e1d0b89
CHL		 3267 { 0x01, 0xffff, 0x068b }
3268 };
ef712ede 3269 int rg_saw_cnt;
6e1d0b89 3270
1791ad50 3271 rtl_ephy_init(tp, e_info_8168h_1);
6e1d0b89 3272
6b1bd242 3273 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
0ebacd12 3274 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
6e1d0b89 3275
f37658da 3276 rtl_set_def_aspm_entry_latency(tp);
6e1d0b89 3277
4e7e4621 3278 rtl_reset_packet_filter(tp);
6e1d0b89 3279
ee1350f9 3280 rtl_eri_set_bits(tp, 0xdc, 0x001c);
6e1d0b89 3281
724c6fd0 3282 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
6e1d0b89 3283
3406079b 3284 rtl_disable_rxdvgate(tp);
6e1d0b89 3285
724c6fd0
HK		 3286 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3287 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
6e1d0b89 3288
df6f1856
HK		 3289 rtl8168_config_eee_mac(tp);
3290
1ef7286e
AS		 3291 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3292 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
6e1d0b89 3293
1ef7286e 3294 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
6e1d0b89 3295
54113ded 3296 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
6e1d0b89 3297
c259b7f4 3298 rtl_pcie_state_l2l3_disable(tp);
6e1d0b89 3299
3ab077d2 3300 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
6e1d0b89
CHL		 3301 if (rg_saw_cnt > 0) {
3302 u16 sw_cnt_1ms_ini;
3303
3304 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3305 sw_cnt_1ms_ini &= 0x0fff;
ef712ede 3306 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
6e1d0b89
CHL		 3307 }
3308
ef712ede
HK		 3309 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3310 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3311 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3312 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
6e1d0b89
CHL		 3313
3314 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3315 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3316 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3317 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3318}
3319
935e2218
CHL		 3320static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3321{
003609da
CHL		 3322 rtl8168ep_stop_cmac(tp);
3323
6b1bd242 3324 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
0ebacd12 3325 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
935e2218 3326
f37658da 3327 rtl_set_def_aspm_entry_latency(tp);
935e2218 3328
4e7e4621 3329 rtl_reset_packet_filter(tp);
935e2218 3330
724c6fd0 3331 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
935e2218 3332
3406079b 3333 rtl_disable_rxdvgate(tp);
935e2218 3334
724c6fd0
HK		 3335 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3336 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
935e2218 3337
df6f1856
HK		 3338 rtl8168_config_eee_mac(tp);
3339
54113ded 3340 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
935e2218 3341
1ef7286e 3342 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
935e2218 3343
c259b7f4 3344 rtl_pcie_state_l2l3_disable(tp);
935e2218
CHL		 3345}
3346
935e2218
CHL		 3347static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3348{
935e2218 3349 static const struct ephy_info e_info_8168ep_3[] = {
a7a92cf8
HK		 3350 { 0x00, 0x0000, 0x0080 },
3351 { 0x0d, 0x0100, 0x0200 },
3352 { 0x19, 0x8021, 0x0000 },
3353 { 0x1e, 0x0000, 0x2000 },
935e2218
CHL		 3354 };
3355
1791ad50 3356 rtl_ephy_init(tp, e_info_8168ep_3);
935e2218
CHL		 3357
3358 rtl_hw_start_8168ep(tp);
3359
1ef7286e
AS		 3360 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3361 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
935e2218 3362
ef712ede
HK		 3363 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3364 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3365 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
935e2218
CHL		 3366}
3367
1287723a
HK		 3368static void rtl_hw_start_8117(struct rtl8169_private *tp)
3369{
3370 static const struct ephy_info e_info_8117[] = {
3371 { 0x19, 0x0040, 0x1100 },
3372 { 0x59, 0x0040, 0x1100 },
3373 };
3374 int rg_saw_cnt;
3375
3376 rtl8168ep_stop_cmac(tp);
1287723a
HK		 3377 rtl_ephy_init(tp, e_info_8117);
3378
3379 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3380 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3381
3382 rtl_set_def_aspm_entry_latency(tp);
3383
3384 rtl_reset_packet_filter(tp);
3385
4b33433e 3386 rtl_eri_set_bits(tp, 0xd4, 0x0010);
1287723a
HK		 3387
3388 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3389
3406079b 3390 rtl_disable_rxdvgate(tp);
1287723a
HK		 3391
3392 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3393 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3394
3395 rtl8168_config_eee_mac(tp);
3396
3397 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3398 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3399
3400 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3401
54113ded 3402 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
1287723a
HK		 3403
3404 rtl_pcie_state_l2l3_disable(tp);
3405
3406 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3407 if (rg_saw_cnt > 0) {
3408 u16 sw_cnt_1ms_ini;
3409
3410 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3411 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3412 }
3413
3414 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3415 r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3416 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3417 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3418
3419 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3420 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3421 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3422 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3423
229c1e0d 3424 /* firmware is for MAC only */
1c5be5e9 3425 r8169_apply_firmware(tp);
1287723a
HK		 3426}
3427
beb1fe18 3428static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 3429{
350f7596 3430 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 3431 { 0x01, 0, 0x6e65 },
3432 { 0x02, 0, 0x091f },
3433 { 0x03, 0, 0xc2f9 },
3434 { 0x06, 0, 0xafb5 },
3435 { 0x07, 0, 0x0e00 },
3436 { 0x19, 0, 0xec80 },
3437 { 0x01, 0, 0x2e65 },
3438 { 0x01, 0, 0x6e65 }
3439 };
3440 u8 cfg1;
3441
f37658da 3442 rtl_set_def_aspm_entry_latency(tp);
2857ffb7 3443
1ef7286e 3444 RTL_W8(tp, DBG_REG, FIX_NAK_1);
2857ffb7 3445
1ef7286e 3446 RTL_W8(tp, Config1,
2857ffb7 3447 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
1ef7286e 3448 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7 3449
1ef7286e 3450 cfg1 = RTL_R8(tp, Config1);
2857ffb7 3451 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
1ef7286e 3452 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
2857ffb7 3453
1791ad50 3454 rtl_ephy_init(tp, e_info_8102e_1);
2857ffb7
FR		 3455}
3456
beb1fe18 3457static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 3458{
f37658da 3459 rtl_set_def_aspm_entry_latency(tp);
2857ffb7 3460
1ef7286e
AS		 3461 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3462 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7
FR		 3463}
3464
beb1fe18 3465static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 3466{
beb1fe18 3467 rtl_hw_start_8102e_2(tp);
2857ffb7 3468
fdf6fc06 3469 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 3470}
3471
cdafdc29
HK		 3472static void rtl_hw_start_8401(struct rtl8169_private *tp)
3473{
3474 static const struct ephy_info e_info_8401[] = {
3475 { 0x01, 0xffff, 0x6fe5 },
3476 { 0x03, 0xffff, 0x0599 },
3477 { 0x06, 0xffff, 0xaf25 },
3478 { 0x07, 0xffff, 0x8e68 },
3479 };
3480
3481 rtl_ephy_init(tp, e_info_8401);
3482 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3483}
3484
beb1fe18 3485static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443
HW		 3486{
3487 static const struct ephy_info e_info_8105e_1[] = {
3488 { 0x07, 0, 0x4000 },
3489 { 0x19, 0, 0x0200 },
3490 { 0x19, 0, 0x0020 },
3491 { 0x1e, 0, 0x2000 },
3492 { 0x03, 0, 0x0001 },
3493 { 0x19, 0, 0x0100 },
3494 { 0x19, 0, 0x0004 },
3495 { 0x0a, 0, 0x0020 }
3496 };
3497
cecb5fd7 3498 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 3499 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5a5e4443 3500
cecb5fd7 3501 /* Disable Early Tally Counter */
1ef7286e 3502 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5a5e4443 3503
1ef7286e
AS		 3504 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3505 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5a5e4443 3506
1791ad50 3507 rtl_ephy_init(tp, e_info_8105e_1);
b51ecea8 3508
c259b7f4 3509 rtl_pcie_state_l2l3_disable(tp);
5a5e4443
HW		 3510}
3511
beb1fe18 3512static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 3513{
beb1fe18 3514 rtl_hw_start_8105e_1(tp);
fdf6fc06 3515 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 3516}
3517
7e18dca1
HW		 3518static void rtl_hw_start_8402(struct rtl8169_private *tp)
3519{
7e18dca1
HW		 3520 static const struct ephy_info e_info_8402[] = {
3521 { 0x19, 0xffff, 0xff64 },
3522 { 0x1e, 0, 0x4000 }
3523 };
3524
f37658da 3525 rtl_set_def_aspm_entry_latency(tp);
7e18dca1
HW		 3526
3527 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 3528 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
7e18dca1 3529
1ef7286e 3530 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7e18dca1 3531
1791ad50 3532 rtl_ephy_init(tp, e_info_8402);
7e18dca1 3533
6b1bd242 3534 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
4e7e4621 3535 rtl_reset_packet_filter(tp);
724c6fd0
HK		 3536 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3537 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
54113ded 3538 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
b51ecea8 3539
6d7a631e
HK		 3540 /* disable EEE */
3541 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3542
c259b7f4 3543 rtl_pcie_state_l2l3_disable(tp);
7e18dca1
HW		 3544}
3545
5598bfe5
HW		 3546static void rtl_hw_start_8106(struct rtl8169_private *tp)
3547{
5598bfe5 3548 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 3549 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5598bfe5 3550
1ef7286e
AS		 3551 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3552 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3553 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
b51ecea8 3554
c07c8ffc
HK		 3555 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */
3556 rtl_set_aspm_entry_latency(tp, 0x2f);
9c401864 3557
8d46f620
HK		 3558 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3559
6d7a631e
HK		 3560 /* disable EEE */
3561 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3562
c259b7f4 3563 rtl_pcie_state_l2l3_disable(tp);
5598bfe5
HW		 3564}
3565
f1bce4ad
HK		 3566DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3567{
3568 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3569}
3570
3571static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3572{
3573 rtl_pcie_state_l2l3_disable(tp);
3574
3575 RTL_W16(tp, 0x382, 0x221b);
3576 RTL_W8(tp, 0x4500, 0);
3577 RTL_W16(tp, 0x4800, 0);
3578
3579 /* disable UPS */
3580 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3581
3582 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3583
3584 r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3585 r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3586
3587 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3588 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3589 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3590
3591 /* disable new tx descriptor format */
3592 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3593
0439297b
HK		 3594 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3595 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
3596 else
3597 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3598
3599 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3600 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
3601 else
3602 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3603
f1bce4ad
HK		 3604 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3605 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3606 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3607 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3608 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
0439297b 3609 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
f1bce4ad 3610 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
0439297b 3611 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
f1bce4ad 3612 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
0439297b 3613
f1bce4ad
HK		 3614 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3615 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3616 udelay(1);
3617 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3618 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3619
3620 r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3621
d6836ef0 3622 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
f1bce4ad 3623
0439297b
HK		 3624 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3625 rtl8125b_config_eee_mac(tp);
3626 else
3627 rtl8125a_config_eee_mac(tp);
b3a42e3a 3628
3406079b 3629 rtl_disable_rxdvgate(tp);
f1bce4ad
HK		 3630}
3631
4640338c 3632static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
f1bce4ad 3633{
4640338c 3634 static const struct ephy_info e_info_8125a_2[] = {
f1bce4ad
HK		 3635 { 0x04, 0xffff, 0xd000 },
3636 { 0x0a, 0xffff, 0x8653 },
3637 { 0x23, 0xffff, 0xab66 },
3638 { 0x20, 0xffff, 0x9455 },
3639 { 0x21, 0xffff, 0x99ff },
3640 { 0x29, 0xffff, 0xfe04 },
3641
3642 { 0x44, 0xffff, 0xd000 },
3643 { 0x4a, 0xffff, 0x8653 },
3644 { 0x63, 0xffff, 0xab66 },
3645 { 0x60, 0xffff, 0x9455 },
3646 { 0x61, 0xffff, 0x99ff },
3647 { 0x69, 0xffff, 0xfe04 },
3648 };
3649
3650 rtl_set_def_aspm_entry_latency(tp);
4640338c 3651 rtl_ephy_init(tp, e_info_8125a_2);
f1bce4ad
HK		 3652 rtl_hw_start_8125_common(tp);
3653}
3654
0439297b
HK		 3655static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3656{
3657 static const struct ephy_info e_info_8125b[] = {
3658 { 0x0b, 0xffff, 0xa908 },
3659 { 0x1e, 0xffff, 0x20eb },
3660 { 0x4b, 0xffff, 0xa908 },
3661 { 0x5e, 0xffff, 0x20eb },
3662 { 0x22, 0x0030, 0x0020 },
3663 { 0x62, 0x0030, 0x0020 },
3664 };
3665
3666 rtl_set_def_aspm_entry_latency(tp);
0439297b
HK		 3667 rtl_ephy_init(tp, e_info_8125b);
3668 rtl_hw_start_8125_common(tp);
0439297b
HK		 3669}
3670
8344ffff
HK		 3671static void rtl_hw_config(struct rtl8169_private *tp)
3672{
3673 static const rtl_generic_fct hw_configs[] = {
3674 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3675 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3676 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3677 [RTL_GIGA_MAC_VER_10] = NULL,
94b5ff74 3678 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
cdafdc29 3679 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401,
94b5ff74 3680 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
8344ffff
HK		 3681 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3682 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3683 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
96ef6928 3684 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2,
8344ffff
HK		 3685 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3686 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3687 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3688 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3689 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
8344ffff
HK		 3690 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3691 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3692 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
0a413e6b 3693 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
8344ffff
HK		 3694 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3695 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3696 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3697 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3698 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3699 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3700 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3701 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3702 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
8344ffff
HK		 3703 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3704 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3705 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
8344ffff 3706 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
8344ffff 3707 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
8344ffff 3708 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
1287723a 3709 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
e6d6ca6e 3710 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117,
4640338c 3711 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
0439297b 3712 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
8344ffff
HK		 3713 };
3714
3715 if (hw_configs[tp->mac_version])
3716 hw_configs[tp->mac_version](tp);
3717}
3718
f1bce4ad
HK		 3719static void rtl_hw_start_8125(struct rtl8169_private *tp)
3720{
3721 int i;
3722
3723 /* disable interrupt coalescing */
3724 for (i = 0xa00; i < 0xb00; i += 4)
3725 RTL_W32(tp, i, 0);
3726
3727 rtl_hw_config(tp);
3728}
3729
8344ffff 3730static void rtl_hw_start_8168(struct rtl8169_private *tp)
07ce4064 3731{
272b2265
HK		 3732 if (rtl_is_8168evl_up(tp))
3733 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3734 else
3735 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
1a964649 3736
8344ffff 3737 rtl_hw_config(tp);
bcf2b868
HK		 3738
3739 /* disable interrupt coalescing */
3740 RTL_W16(tp, IntrMitigate, 0x0000);
1da177e4
LT		 3741}
3742
6c19156e
HK		 3743static void rtl_hw_start_8169(struct rtl8169_private *tp)
3744{
6c19156e
HK		 3745 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3746
3747 tp->cp_cmd |= PCIMulRW;
3748
3749 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
09e65335
HK		 3750 tp->mac_version == RTL_GIGA_MAC_VER_03)
3751 tp->cp_cmd |= EnAnaPLL;
6c19156e
HK		 3752
3753 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3754
ef891284 3755 rtl8169_set_magic_reg(tp);
6c19156e 3756
bcf2b868
HK		 3757 /* disable interrupt coalescing */
3758 RTL_W16(tp, IntrMitigate, 0x0000);
6c19156e
HK		 3759}
3760
3761static void rtl_hw_start(struct rtl8169_private *tp)
3762{
3763 rtl_unlock_config_regs(tp);
5fc3f6c9
HK		 3764 /* disable aspm and clock request before ephy access */
3765 rtl_hw_aspm_clkreq_enable(tp, false);
6c19156e
HK		 3766 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3767
3768 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3769 rtl_hw_start_8169(tp);
f1bce4ad
HK		 3770 else if (rtl_is_8125(tp))
3771 rtl_hw_start_8125(tp);
6c19156e
HK		 3772 else
3773 rtl_hw_start_8168(tp);
3774
4b33433e 3775 rtl_enable_exit_l1(tp);
5fc3f6c9 3776 rtl_hw_aspm_clkreq_enable(tp, true);
6c19156e
HK		 3777 rtl_set_rx_max_size(tp);
3778 rtl_set_rx_tx_desc_registers(tp);
3779 rtl_lock_config_regs(tp);
3780
9db0ac57 3781 rtl_jumbo_config(tp);
4ebcb113 3782
6c19156e 3783 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
711463f8
HK		 3784 rtl_pci_commit(tp);
3785
6c19156e
HK		 3786 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3787 rtl_init_rxcfg(tp);
3788 rtl_set_tx_config_registers(tp);
10478283 3789 rtl_set_rx_config_features(tp, tp->dev->features);
6c19156e 3790 rtl_set_rx_mode(tp->dev);
6c19156e
HK		 3791 rtl_irq_enable(tp);
3792}
3793
1da177e4
LT		 3794static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3795{
d58d46b5
FR		 3796 struct rtl8169_private *tp = netdev_priv(dev);
3797
1da177e4 3798 dev->mtu = new_mtu;
350fb32a 3799 netdev_update_features(dev);
9db0ac57 3800 rtl_jumbo_config(tp);
350fb32a 3801
0439297b
HK		 3802 switch (tp->mac_version) {
3803 case RTL_GIGA_MAC_VER_61:
3804 case RTL_GIGA_MAC_VER_63:
3805 rtl8125_set_eee_txidle_timer(tp);
3806 break;
3807 default:
3808 break;
3809 }
3810
323bb685 3811 return 0;
1da177e4
LT		 3812}
3813
e2e5fb8d 3814static void rtl8169_mark_to_asic(struct RxDesc *desc)
1da177e4
LT		 3815{
3816 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3817
047521d7 3818 desc->opts2 = 0;
a0750138
AD		 3819 /* Force memory writes to complete before releasing descriptor */
3820 dma_wmb();
e2e5fb8d 3821 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
1da177e4
LT		 3822}
3823
32879f00
HK		 3824static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3825 struct RxDesc *desc)
1da177e4 3826{
1e1205b7 3827 struct device *d = tp_to_dev(tp);
d3b404c2 3828 int node = dev_to_node(d);
32879f00
HK		 3829 dma_addr_t mapping;
3830 struct page *data;
1da177e4 3831
32879f00 3832 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
6f0333b8
ED		 3833 if (!data)
3834 return NULL;
e9f63f30 3835
32879f00 3836 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
d827d86b 3837 if (unlikely(dma_mapping_error(d, mapping))) {
93882c6f 3838 netdev_err(tp->dev, "Failed to map RX DMA!\n");
32879f00
HK		 3839 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
3840 return NULL;
d827d86b 3841 }
1da177e4 3842
d731af78
HK		 3843 desc->addr = cpu_to_le64(mapping);
3844 rtl8169_mark_to_asic(desc);
3eafe507 3845
32879f00 3846 return data;
1da177e4
LT		 3847}
3848
3849static void rtl8169_rx_clear(struct rtl8169_private *tp)
3850{
ed22a8ff 3851 int i;
1da177e4 3852
eb2e7f09
HK		 3853 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
3854 dma_unmap_page(tp_to_dev(tp),
3855 le64_to_cpu(tp->RxDescArray[i].addr),
3856 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3857 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
3858 tp->Rx_databuff[i] = NULL;
9d3679fe
HK		 3859 tp->RxDescArray[i].addr = 0;
3860 tp->RxDescArray[i].opts1 = 0;
1da177e4
LT		 3861 }
3862}
3863
0ecbe1ca
SG		 3864static int rtl8169_rx_fill(struct rtl8169_private *tp)
3865{
ed22a8ff 3866 int i;
1da177e4 3867
0ecbe1ca 3868 for (i = 0; i < NUM_RX_DESC; i++) {
32879f00 3869 struct page *data;
4ae47c2d 3870
0ecbe1ca 3871 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8 3872 if (!data) {
e4b5c7a5
HK		 3873 rtl8169_rx_clear(tp);
3874 return -ENOMEM;
6f0333b8
ED		 3875 }
3876 tp->Rx_databuff[i] = data;
1da177e4 3877 }
1da177e4 3878
2ac1fa43
HK		 3879 /* mark as last descriptor in the ring */
3880 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
0ecbe1ca 3881
e4b5c7a5 3882 return 0;
1da177e4
LT		 3883}
3884
b1127e64 3885static int rtl8169_init_ring(struct rtl8169_private *tp)
1da177e4 3886{
1da177e4
LT		 3887 rtl8169_init_ring_indexes(tp);
3888
b1127e64
HK		 3889 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
3890 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
1da177e4 3891
0ecbe1ca 3892 return rtl8169_rx_fill(tp);
1da177e4
LT		 3893}
3894
22d352c5 3895static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
1da177e4 3896{
22d352c5
HK		 3897 struct ring_info *tx_skb = tp->tx_skb + entry;
3898 struct TxDesc *desc = tp->TxDescArray + entry;
1da177e4 3899
22d352c5
HK		 3900 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
3901 DMA_TO_DEVICE);
6a41f2b2
HK		 3902 memset(desc, 0, sizeof(*desc));
3903 memset(tx_skb, 0, sizeof(*tx_skb));
1da177e4
LT		 3904}
3905
3eafe507
SG		 3906static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3907 unsigned int n)
1da177e4
LT		 3908{
3909 unsigned int i;
3910
3eafe507
SG		 3911 for (i = 0; i < n; i++) {
3912 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 3913 struct ring_info *tx_skb = tp->tx_skb + entry;
3914 unsigned int len = tx_skb->len;
3915
3916 if (len) {
3917 struct sk_buff *skb = tx_skb->skb;
3918
22d352c5 3919 rtl8169_unmap_tx_skb(tp, entry);
6a41f2b2 3920 if (skb)
7a4b813c 3921 dev_consume_skb_any(skb);
1da177e4
LT		 3922 }
3923 }
3eafe507
SG		 3924}
3925
3926static void rtl8169_tx_clear(struct rtl8169_private *tp)
3927{
3928 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
d92060bc 3929 netdev_reset_queue(tp->dev);
1da177e4
LT		 3930}
3931
bb41c13c 3932static void rtl8169_cleanup(struct rtl8169_private *tp)
bac75d85 3933{
0c28a63a
HK		 3934 napi_disable(&tp->napi);
3935
bac75d85 3936 /* Give a racing hard_start_xmit a few cycles to complete. */
7190aeec 3937 synchronize_net();
bac75d85
HK		 3938
3939 /* Disable interrupts */
3940 rtl8169_irq_mask_and_ack(tp);
3941
3942 rtl_rx_close(tp);
3943
3944 switch (tp->mac_version) {
bac75d85
HK		 3945 case RTL_GIGA_MAC_VER_28:
3946 case RTL_GIGA_MAC_VER_31:
3947 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
3948 break;
3949 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
3950 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3951 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
3952 break;
0439297b 3953 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
bac75d85
HK		 3954 rtl_enable_rxdvgate(tp);
3955 fsleep(2000);
3956 break;
3957 default:
3958 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3959 fsleep(100);
3960 break;
3961 }
3962
3963 rtl_hw_reset(tp);
bb41c13c 3964
bac75d85
HK		 3965 rtl8169_tx_clear(tp);
3966 rtl8169_init_ring_indexes(tp);
3967}
3968
4422bcd4 3969static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 3970{
56de414c 3971 int i;
1da177e4 3972
476c4f5d 3973 netif_stop_queue(tp->dev);
1da177e4 3974
bb41c13c 3975 rtl8169_cleanup(tp);
c7c2c39b 3976
56de414c 3977 for (i = 0; i < NUM_RX_DESC; i++)
1d0254dd 3978 rtl8169_mark_to_asic(tp->RxDescArray + i);
56de414c 3979
da78dbff 3980 napi_enable(&tp->napi);
61cb532d 3981 rtl_hw_start(tp);
1da177e4
LT		 3982}
3983
0290bd29 3984static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
1da177e4 3985{
da78dbff
FR		 3986 struct rtl8169_private *tp = netdev_priv(dev);
3987
80c0576e 3988 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT);
1da177e4
LT		 3989}
3990
b8447abc
HK		 3991static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
3992 void *addr, unsigned int entry, bool desc_own)
734c1409 3993{
b8447abc
HK		 3994 struct TxDesc *txd = tp->TxDescArray + entry;
3995 struct device *d = tp_to_dev(tp);
3996 dma_addr_t mapping;
3997 u32 opts1;
3998 int ret;
3999
4000 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4001 ret = dma_mapping_error(d, mapping);
4002 if (unlikely(ret)) {
4003 if (net_ratelimit())
93882c6f 4004 netdev_err(tp->dev, "Failed to map TX data!\n");
b8447abc
HK		 4005 return ret;
4006 }
4007
4008 txd->addr = cpu_to_le64(mapping);
4009 txd->opts2 = cpu_to_le32(opts[1]);
734c1409 4010
b8447abc 4011 opts1 = opts[0] | len;
734c1409 4012 if (entry == NUM_TX_DESC - 1)
b8447abc
HK		 4013 opts1 |= RingEnd;
4014 if (desc_own)
4015 opts1 |= DescOwn;
4016 txd->opts1 = cpu_to_le32(opts1);
734c1409 4017
b8447abc
HK		 4018 tp->tx_skb[entry].len = len;
4019
4020 return 0;
734c1409
HK		 4021}
4022
1da177e4 4023static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
b8447abc 4024 const u32 *opts, unsigned int entry)
1da177e4
LT		 4025{
4026 struct skb_shared_info *info = skb_shinfo(skb);
b8447abc 4027 unsigned int cur_frag;
1da177e4 4028
1da177e4 4029 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 4030 const skb_frag_t *frag = info->frags + cur_frag;
b8447abc
HK		 4031 void *addr = skb_frag_address(frag);
4032 u32 len = skb_frag_size(frag);
1da177e4
LT		 4033
4034 entry = (entry + 1) % NUM_TX_DESC;
4035
b8447abc 4036 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
3eafe507 4037 goto err_out;
1da177e4
LT		 4038 }
4039
9020845f 4040 return 0;
3eafe507
SG		 4041
4042err_out:
4043 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4044 return -EIO;
1da177e4
LT		 4045}
4046
8d520b4d
HK		 4047static bool rtl_skb_is_udp(struct sk_buff *skb)
4048{
4049 int no = skb_network_offset(skb);
4050 struct ipv6hdr *i6h, _i6h;
4051 struct iphdr *ih, _ih;
4052
4053 switch (vlan_get_protocol(skb)) {
4054 case htons(ETH_P_IP):
4055 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih);
4056 return ih && ih->protocol == IPPROTO_UDP;
4057 case htons(ETH_P_IPV6):
4058 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h);
4059 return i6h && i6h->nexthdr == IPPROTO_UDP;
4060 default:
4061 return false;
4062 }
4063}
4064
4065#define RTL_MIN_PATCH_LEN 47
4066
4067/* see rtl8125_get_patch_pad_len() in r8125 vendor driver */
4068static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp,
4069 struct sk_buff *skb)
b423e9ae 4070{
8d520b4d
HK		 4071 unsigned int padto = 0, len = skb->len;
4072
4073 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN &&
4074 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) {
4075 unsigned int trans_data_len = skb_tail_pointer(skb) -
4076 skb_transport_header(skb);
4077
4078 if (trans_data_len >= offsetof(struct udphdr, len) &&
4079 trans_data_len < RTL_MIN_PATCH_LEN) {
4080 u16 dest = ntohs(udp_hdr(skb)->dest);
4081
4082 /* dest is a standard PTP port */
4083 if (dest == 319 || dest == 320)
4084 padto = len + RTL_MIN_PATCH_LEN - trans_data_len;
4085 }
4086
4087 if (trans_data_len < sizeof(struct udphdr))
4088 padto = max_t(unsigned int, padto,
4089 len + sizeof(struct udphdr) - trans_data_len);
4090 }
4091
4092 return padto;
4093}
4094
4095static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,
4096 struct sk_buff *skb)
4097{
4098 unsigned int padto;
4099
4100 padto = rtl8125_quirk_udp_padto(tp, skb);
4101
2aaf09a0
HK		 4102 switch (tp->mac_version) {
4103 case RTL_GIGA_MAC_VER_34:
2aaf09a0
HK		 4104 case RTL_GIGA_MAC_VER_61:
4105 case RTL_GIGA_MAC_VER_63:
8d520b4d 4106 padto = max_t(unsigned int, padto, ETH_ZLEN);
ffb35c67 4107 break;
2aaf09a0 4108 default:
8d520b4d 4109 break;
2aaf09a0 4110 }
8d520b4d
HK		 4111
4112 return padto;
b423e9ae 4113}
4114
87945b6d 4115static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
1da177e4 4116{
350fb32a
MM		 4117 u32 mss = skb_shinfo(skb)->gso_size;
4118
2b7b4318
FR		 4119 if (mss) {
4120 opts[0] |= TD_LSO;
4abc3c04 4121 opts[0] |= mss << TD0_MSS_SHIFT;
5888d3fc 4122 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4123 const struct iphdr *ip = ip_hdr(skb);
4124
4125 if (ip->protocol == IPPROTO_TCP)
4126 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4127 else if (ip->protocol == IPPROTO_UDP)
4128 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4129 else
4130 WARN_ON_ONCE(1);
4131 }
5888d3fc 4132}
4133
4134static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4135 struct sk_buff *skb, u32 *opts)
4136{
0623b98b
HK		 4137 struct skb_shared_info *shinfo = skb_shinfo(skb);
4138 u32 mss = shinfo->gso_size;
5888d3fc 4139
4140 if (mss) {
0623b98b 4141 if (shinfo->gso_type & SKB_GSO_TCPV4) {
e974604b 4142 opts[0] |= TD1_GTSENV4;
0623b98b 4143 } else if (shinfo->gso_type & SKB_GSO_TCPV6) {
8b19c68c 4144 if (skb_cow_head(skb, 0))
e974604b 4145 return false;
4146
8b19c68c 4147 tcp_v6_gso_csum_prep(skb);
e974604b 4148 opts[0] |= TD1_GTSENV6;
0623b98b 4149 } else {
e974604b 4150 WARN_ON_ONCE(1);
e974604b 4151 }
4152
faa4e04e 4153 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT;
4abc3c04 4154 opts[1] |= mss << TD1_MSS_SHIFT;
2b7b4318 4155 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
e974604b 4156 u8 ip_protocol;
1da177e4 4157
4ff36466 4158 switch (vlan_get_protocol(skb)) {
e974604b 4159 case htons(ETH_P_IP):
4160 opts[1] |= TD1_IPv4_CS;
4161 ip_protocol = ip_hdr(skb)->protocol;
4162 break;
4163
4164 case htons(ETH_P_IPV6):
4165 opts[1] |= TD1_IPv6_CS;
4166 ip_protocol = ipv6_hdr(skb)->nexthdr;
4167 break;
4168
4169 default:
4170 ip_protocol = IPPROTO_RAW;
4171 break;
4172 }
4173
4174 if (ip_protocol == IPPROTO_TCP)
4175 opts[1] |= TD1_TCP_CS;
4176 else if (ip_protocol == IPPROTO_UDP)
4177 opts[1] |= TD1_UDP_CS;
2b7b4318
FR		 4178 else
4179 WARN_ON_ONCE(1);
e974604b 4180
faa4e04e 4181 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT;
b423e9ae 4182 } else {
8d520b4d
HK		 4183 unsigned int padto = rtl_quirk_packet_padto(tp, skb);
4184
4185 /* skb_padto would free the skb on error */
4186 return !__skb_put_padto(skb, padto, false);
1da177e4 4187 }
5888d3fc 4188
b423e9ae 4189 return true;
1da177e4
LT		 4190}
4191
8624e9bb 4192static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp)
76085c9e 4193{
8624e9bb 4194 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx);
76085c9e
HK		 4195}
4196
87945b6d
HK		 4197/* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
4198static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4199{
4200 switch (tp->mac_version) {
4201 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4202 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4203 return false;
4204 default:
4205 return true;
4206 }
4207}
4208
f1bce4ad
HK		 4209static void rtl8169_doorbell(struct rtl8169_private *tp)
4210{
4211 if (rtl_is_8125(tp))
4212 RTL_W16(tp, TxPoll_8125, BIT(0));
4213 else
4214 RTL_W8(tp, TxPoll, NPQ);
4215}
4216
61357325
SH		 4217static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4218 struct net_device *dev)
1da177e4 4219{
9020845f 4220 unsigned int frags = skb_shinfo(skb)->nr_frags;
1da177e4 4221 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 4222 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
b8447abc
HK		 4223 struct TxDesc *txd_first, *txd_last;
4224 bool stop_queue, door_bell;
4225 u32 opts[2];
4226
83c317d7 4227 if (unlikely(!rtl_tx_slots_avail(tp))) {
93882c6f
HK		 4228 if (net_ratelimit())
4229 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 4230 goto err_stop_0;
1da177e4
LT		 4231 }
4232
355f948a 4233 opts[1] = rtl8169_tx_vlan_tag(skb);
b8447abc 4234 opts[0] = 0;
b423e9ae 4235
b8447abc 4236 if (!rtl_chip_supports_csum_v2(tp))
87945b6d 4237 rtl8169_tso_csum_v1(skb, opts);
b8447abc 4238 else if (!rtl8169_tso_csum_v2(tp, skb, opts))
3eafe507
SG		 4239 goto err_dma_0;
4240
b8447abc
HK		 4241 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4242 entry, false)))
4243 goto err_dma_0;
1da177e4 4244
bd4bdeb4
HK		 4245 txd_first = tp->TxDescArray + entry;
4246
b8447abc
HK		 4247 if (frags) {
4248 if (rtl8169_xmit_frags(tp, skb, opts, entry))
9020845f 4249 goto err_dma_1;
b8447abc 4250 entry = (entry + frags) % NUM_TX_DESC;
1da177e4
LT		 4251 }
4252
b8447abc
HK		 4253 txd_last = tp->TxDescArray + entry;
4254 txd_last->opts1 |= cpu_to_le32(LastFrag);
4255 tp->tx_skb[entry].skb = skb;
2b7b4318 4256
5047fb5d
RC		 4257 skb_tx_timestamp(skb);
4258
a0750138
AD		 4259 /* Force memory writes to complete before releasing descriptor */
4260 dma_wmb();
1da177e4 4261
ef143585
HK		 4262 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
4263
b8447abc 4264 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
1da177e4 4265
794867ee
HK		 4266 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4267 smp_wmb();
1da177e4 4268
41294e6a 4269 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1);
a0750138 4270
8624e9bb
HK		 4271 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp),
4272 R8169_TX_STOP_THRS,
4273 R8169_TX_START_THRS);
4274 if (door_bell || stop_queue)
41294e6a
HK		 4275 rtl8169_doorbell(tp);
4276
61357325 4277 return NETDEV_TX_OK;
1da177e4 4278
3eafe507 4279err_dma_1:
22d352c5 4280 rtl8169_unmap_tx_skb(tp, entry);
3eafe507 4281err_dma_0:
989c9ba1 4282 dev_kfree_skb_any(skb);
3eafe507
SG		 4283 dev->stats.tx_dropped++;
4284 return NETDEV_TX_OK;
4285
4286err_stop_0:
1da177e4 4287 netif_stop_queue(dev);
cebf8cc7 4288 dev->stats.tx_dropped++;
61357325 4289 return NETDEV_TX_BUSY;
1da177e4
LT		 4290}
4291
773235f4
HK		 4292static unsigned int rtl_last_frag_len(struct sk_buff *skb)
4293{
4294 struct skb_shared_info *info = skb_shinfo(skb);
4295 unsigned int nr_frags = info->nr_frags;
4296
4297 if (!nr_frags)
4298 return UINT_MAX;
4299
4300 return skb_frag_size(info->frags + nr_frags - 1);
4301}
4302
4303/* Workaround for hw issues with TSO on RTL8168evl */
4304static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
4305 netdev_features_t features)
4306{
4307 /* IPv4 header has options field */
4308 if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
4309 ip_hdrlen(skb) > sizeof(struct iphdr))
4310 features &= ~NETIF_F_ALL_TSO;
4311
4312 /* IPv4 TCP header has options field */
4313 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
4314 tcp_hdrlen(skb) > sizeof(struct tcphdr))
4315 features &= ~NETIF_F_ALL_TSO;
4316
4317 else if (rtl_last_frag_len(skb) <= 6)
4318 features &= ~NETIF_F_ALL_TSO;
4319
4320 return features;
4321}
4322
e64e0c89
HK		 4323static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4324 struct net_device *dev,
4325 netdev_features_t features)
4326{
e64e0c89
HK		 4327 struct rtl8169_private *tp = netdev_priv(dev);
4328
4329 if (skb_is_gso(skb)) {
773235f4
HK		 4330 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4331 features = rtl8168evl_fix_tso(skb, features);
4332
faa4e04e 4333 if (skb_transport_offset(skb) > GTTCPHO_MAX &&
e64e0c89
HK		 4334 rtl_chip_supports_csum_v2(tp))
4335 features &= ~NETIF_F_ALL_TSO;
4336 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
847f0a2b
HK		 4337 /* work around hw bug on some chip versions */
4338 if (skb->len < ETH_ZLEN)
4339 features &= ~NETIF_F_CSUM_MASK;
e64e0c89 4340
8d520b4d
HK		 4341 if (rtl_quirk_packet_padto(tp, skb))
4342 features &= ~NETIF_F_CSUM_MASK;
e64e0c89 4343
faa4e04e 4344 if (skb_transport_offset(skb) > TCPHO_MAX &&
e64e0c89
HK		 4345 rtl_chip_supports_csum_v2(tp))
4346 features &= ~NETIF_F_CSUM_MASK;
4347 }
4348
4349 return vlan_features_check(skb, features);
4350}
4351
1da177e4
LT		 4352static void rtl8169_pcierr_interrupt(struct net_device *dev)
4353{
4354 struct rtl8169_private *tp = netdev_priv(dev);
4355 struct pci_dev *pdev = tp->pci_dev;
2864a883
HK		 4356 int pci_status_errs;
4357 u16 pci_cmd;
1da177e4
LT		 4358
4359 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1da177e4 4360
2864a883
HK		 4361 pci_status_errs = pci_status_get_and_clear_errors(pdev);
4362
93882c6f
HK		 4363 if (net_ratelimit())
4364 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4365 pci_cmd, pci_status_errs);
1da177e4 4366
98ddf986 4367 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 4368}
4369
5317d5c6
HK		 4370static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4371 int budget)
1da177e4 4372{
ca1ab89c 4373 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0;
94d8a98e 4374 struct sk_buff *skb;
1da177e4 4375
1da177e4 4376 dirty_tx = tp->dirty_tx;
1da177e4 4377
ca1ab89c 4378 while (READ_ONCE(tp->cur_tx) != dirty_tx) {
1da177e4 4379 unsigned int entry = dirty_tx % NUM_TX_DESC;
1da177e4
LT		 4380 u32 status;
4381
dcf75a0f 4382 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1));
1da177e4
LT		 4383 if (status & DescOwn)
4384 break;
4385
94d8a98e 4386 skb = tp->tx_skb[entry].skb;
22d352c5
HK		 4387 rtl8169_unmap_tx_skb(tp, entry);
4388
6a41f2b2 4389 if (skb) {
d92060bc 4390 pkts_compl++;
6a41f2b2
HK		 4391 bytes_compl += skb->len;
4392 napi_consume_skb(skb, budget);
1da177e4
LT		 4393 }
4394 dirty_tx++;
1da177e4
LT		 4395 }
4396
4397 if (tp->dirty_tx != dirty_tx) {
5e4cb480 4398 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl);
1a31ae00 4399 WRITE_ONCE(tp->dirty_tx, dirty_tx);
d92060bc 4400
1a31ae00
HK		 4401 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl,
4402 rtl_tx_slots_avail(tp),
4403 R8169_TX_START_THRS);
d78ae2dc
FR		 4404 /*
4405 * 8168 hack: TxPoll requests are lost when the Tx packets are
4406 * too close. Let's kick an extra TxPoll request when a burst
4407 * of start_xmit activity is detected (if it is not detected,
4408 * it is slow enough). -- FR
94d8a98e
HK		 4409 * If skb is NULL then we come here again once a tx irq is
4410 * triggered after the last fragment is marked transmitted.
d78ae2dc 4411 */
c1c0ce31 4412 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb)
f1bce4ad 4413 rtl8169_doorbell(tp);
1da177e4
LT		 4414 }
4415}
4416
126fa4b9
FR		 4417static inline int rtl8169_fragmented_frame(u32 status)
4418{
4419 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4420}
4421
adea1ac7 4422static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 4423{
206a75e0 4424 u32 status = opts1 & (RxProtoMask | RxCSFailMask);
1da177e4 4425
206a75e0 4426 if (status == RxProtoTCP || status == RxProtoUDP)
1da177e4
LT		 4427 skb->ip_summed = CHECKSUM_UNNECESSARY;
4428 else
bc8acf2c 4429 skb_checksum_none_assert(skb);
1da177e4
LT		 4430}
4431
2f53e9d7 4432static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget)
1da177e4 4433{
588c7e5c 4434 struct device *d = tp_to_dev(tp);
2f53e9d7 4435 int count;
1da177e4 4436
2f53e9d7
HK		 4437 for (count = 0; count < budget; count++, tp->cur_rx++) {
4438 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC;
126fa4b9 4439 struct RxDesc *desc = tp->RxDescArray + entry;
588c7e5c
HK		 4440 struct sk_buff *skb;
4441 const void *rx_buf;
4442 dma_addr_t addr;
1da177e4
LT		 4443 u32 status;
4444
f97eee48 4445 status = le32_to_cpu(READ_ONCE(desc->opts1));
1da177e4
LT		 4446 if (status & DescOwn)
4447 break;
a0750138
AD		 4448
4449 /* This barrier is needed to keep us from reading
4450 * any other fields out of the Rx descriptor until
4451 * we know the status of DescOwn
4452 */
4453 dma_rmb();
4454
4dcb7d33 4455 if (unlikely(status & RxRES)) {
93882c6f
HK		 4456 if (net_ratelimit())
4457 netdev_warn(dev, "Rx ERROR. status = %08x\n",
4458 status);
cebf8cc7 4459 dev->stats.rx_errors++;
1da177e4 4460 if (status & (RxRWT | RxRUNT))
cebf8cc7 4461 dev->stats.rx_length_errors++;
1da177e4 4462 if (status & RxCRC)
cebf8cc7 4463 dev->stats.rx_crc_errors++;
126fa4b9 4464
588c7e5c 4465 if (!(dev->features & NETIF_F_RXALL))
ce11ff5e 4466 goto release_descriptor;
588c7e5c
HK		 4467 else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
4468 goto release_descriptor;
4469 }
1da177e4 4470
588c7e5c
HK		 4471 pkt_size = status & GENMASK(13, 0);
4472 if (likely(!(dev->features & NETIF_F_RXFCS)))
4473 pkt_size -= ETH_FCS_LEN;
fcd4e608 4474
588c7e5c
HK		 4475 /* The driver does not support incoming fragmented frames.
4476 * They are seen as a symptom of over-mtu sized frames.
4477 */
4478 if (unlikely(rtl8169_fragmented_frame(status))) {
4479 dev->stats.rx_dropped++;
4480 dev->stats.rx_length_errors++;
4481 goto release_descriptor;
4482 }
d4ed7463 4483
588c7e5c
HK		 4484 skb = napi_alloc_skb(&tp->napi, pkt_size);
4485 if (unlikely(!skb)) {
4486 dev->stats.rx_dropped++;
4487 goto release_descriptor;
4488 }
1da177e4 4489
588c7e5c
HK		 4490 addr = le64_to_cpu(desc->addr);
4491 rx_buf = page_address(tp->Rx_databuff[entry]);
7a8fc77b 4492
588c7e5c
HK		 4493 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4494 prefetch(rx_buf);
4495 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
4496 skb->tail += pkt_size;
4497 skb->len = pkt_size;
4498 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
39174291 4499
588c7e5c
HK		 4500 rtl8169_rx_csum(skb, status);
4501 skb->protocol = eth_type_trans(skb, dev);
4502
4503 rtl8169_rx_vlan_tag(desc, skb);
4504
4505 if (skb->pkt_type == PACKET_MULTICAST)
4506 dev->stats.multicast++;
4507
4508 napi_gro_receive(&tp->napi, skb);
4509
5e4cb480 4510 dev_sw_netstats_rx_add(dev, pkt_size);
ce11ff5e 4511release_descriptor:
1d0254dd 4512 rtl8169_mark_to_asic(desc);
1da177e4
LT		 4513 }
4514
1da177e4
LT		 4515 return count;
4516}
4517
07d3f51f 4518static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 4519{
ebcd5daa 4520 struct rtl8169_private *tp = dev_instance;
c1d532d2 4521 u32 status = rtl_get_events(tp);
1da177e4 4522
9e89d719 4523 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
05bbe558 4524 return IRQ_NONE;
1da177e4 4525
38caff5a
HK		 4526 if (unlikely(status & SYSErr)) {
4527 rtl8169_pcierr_interrupt(tp->dev);
4528 goto out;
4529 }
da78dbff 4530
703732f0
HK		 4531 if (status & LinkChg)
4532 phy_mac_interrupt(tp->phydev);
1da177e4 4533
38caff5a
HK		 4534 if (unlikely(status & RxFIFOOver &&
4535 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4536 netif_stop_queue(tp->dev);
6b02e407 4537 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
da78dbff 4538 }
1da177e4 4539
7274c414
HK		 4540 if (napi_schedule_prep(&tp->napi)) {
4541 rtl_irq_disable(tp);
4542 __napi_schedule(&tp->napi);
4543 }
38caff5a
HK		 4544out:
4545 rtl_ack_events(tp, status);
1da177e4 4546
38caff5a 4547 return IRQ_HANDLED;
1da177e4
LT		 4548}
4549
4422bcd4
FR		 4550static void rtl_task(struct work_struct *work)
4551{
4552 struct rtl8169_private *tp =
4553 container_of(work, struct rtl8169_private, wk.work);
80c0576e 4554 int ret;
da78dbff 4555
abe5fc42 4556 rtnl_lock();
da78dbff 4557
e18958c6 4558 if (!netif_running(tp->dev) ||
6c4a70c5 4559 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 4560 goto out_unlock;
4561
80c0576e 4562 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) {
ce870af3
HK		 4563 /* if chip isn't accessible, reset bus to revive it */
4564 if (RTL_R32(tp, TxConfig) == ~0) {
4565 ret = pci_reset_bus(tp->pci_dev);
4566 if (ret < 0) {
4567 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n");
4568 netif_device_detach(tp->dev);
4569 goto out_unlock;
4570 }
4571 }
4572
80c0576e
HK		 4573 /* ASPM compatibility issues are a typical reason for tx timeouts */
4574 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 |
4575 PCIE_LINK_STATE_L0S);
4576 if (!ret)
4577 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n");
4578 goto reset;
4579 }
4580
476c4f5d 4581 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
80c0576e 4582reset:
e18958c6 4583 rtl_reset_work(tp);
476c4f5d
HK		 4584 netif_wake_queue(tp->dev);
4585 }
da78dbff 4586out_unlock:
abe5fc42 4587 rtnl_unlock();
4422bcd4
FR		 4588}
4589
bea3348e 4590static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 4591{
bea3348e
SH		 4592 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4593 struct net_device *dev = tp->dev;
6b839b6c 4594 int work_done;
da78dbff 4595
5317d5c6 4596 rtl_tx(dev, tp, budget);
1da177e4 4597
9fbb4a7a
HK		 4598 work_done = rtl_rx(dev, tp, budget);
4599
e31a9fed 4600 if (work_done < budget && napi_complete_done(napi, work_done))
fe716f8a 4601 rtl_irq_enable(tp);
1da177e4 4602
bea3348e 4603 return work_done;
1da177e4 4604}
1da177e4 4605
f1e911d5
HK		 4606static void r8169_phylink_handler(struct net_device *ndev)
4607{
4608 struct rtl8169_private *tp = netdev_priv(ndev);
4b6c6065 4609 struct device *d = tp_to_dev(tp);
f1e911d5
HK		 4610
4611 if (netif_carrier_ok(ndev)) {
4612 rtl_link_chg_patch(tp);
4b6c6065 4613 pm_request_resume(d);
621735f5 4614 netif_wake_queue(tp->dev);
f1e911d5 4615 } else {
621735f5
HK		 4616 /* In few cases rx is broken after link-down otherwise */
4617 if (rtl_is_8125(tp))
4618 rtl_reset_work(tp);
4b6c6065 4619 pm_runtime_idle(d);
f1e911d5
HK		 4620 }
4621
96efd6d0 4622 phy_print_status(tp->phydev);
f1e911d5
HK		 4623}
4624
4625static int r8169_phy_connect(struct rtl8169_private *tp)
4626{
703732f0 4627 struct phy_device *phydev = tp->phydev;
f1e911d5
HK		 4628 phy_interface_t phy_mode;
4629 int ret;
4630
f7ffa9ae 4631 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
f1e911d5
HK		 4632 PHY_INTERFACE_MODE_MII;
4633
4634 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4635 phy_mode);
4636 if (ret)
4637 return ret;
4638
66058b1c 4639 if (!tp->supports_gmii)
f1e911d5
HK		 4640 phy_set_max_speed(phydev, SPEED_100);
4641
f1e911d5
HK		 4642 phy_attached_info(phydev);
4643
4644 return 0;
4645}
4646
8ac8e8c6 4647static void rtl8169_down(struct rtl8169_private *tp)
1da177e4 4648{
8ac8e8c6
HK		 4649 /* Clear all task flags */
4650 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
f1e911d5 4651
8ac8e8c6 4652 phy_stop(tp->phydev);
1da177e4 4653
a2ee8472
HK		 4654 rtl8169_update_counters(tp);
4655
f658b909
HK		 4656 pci_clear_master(tp->pci_dev);
4657 rtl_pci_commit(tp);
4658
bb41c13c 4659 rtl8169_cleanup(tp);
d192181c 4660 rtl_disable_exit_l1(tp);
7257c977 4661 rtl_prepare_power_down(tp);
868c3b95
CL		 4662
4663 if (tp->dash_type != RTL_DASH_NONE)
4664 rtl8168_driver_stop(tp);
1da177e4
LT		 4665}
4666
567ca57f
HK		 4667static void rtl8169_up(struct rtl8169_private *tp)
4668{
868c3b95
CL		 4669 if (tp->dash_type != RTL_DASH_NONE)
4670 rtl8168_driver_start(tp);
4671
f658b909 4672 pci_set_master(tp->pci_dev);
5c2280fc 4673 phy_init_hw(tp->phydev);
7257c977 4674 phy_resume(tp->phydev);
567ca57f
HK		 4675 rtl8169_init_phy(tp);
4676 napi_enable(&tp->napi);
4677 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4678 rtl_reset_work(tp);
4679
4680 phy_start(tp->phydev);
567ca57f
HK		 4681}
4682
1da177e4
LT		 4683static int rtl8169_close(struct net_device *dev)
4684{
4685 struct rtl8169_private *tp = netdev_priv(dev);
4686 struct pci_dev *pdev = tp->pci_dev;
4687
e1759441
RW		 4688 pm_runtime_get_sync(&pdev->dev);
4689
8ac8e8c6
HK		 4690 netif_stop_queue(dev);
4691 rtl8169_down(tp);
4692 rtl8169_rx_clear(tp);
1da177e4 4693
4ea72445
L		 4694 cancel_work_sync(&tp->wk.work);
4695
1bd32771 4696 free_irq(tp->irq, tp);
1da177e4 4697
cc9f07a8
HK		 4698 phy_disconnect(tp->phydev);
4699
82553bb6
SG		 4700 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4701 tp->RxPhyAddr);
4702 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4703 tp->TxPhyAddr);
1da177e4
LT		 4704 tp->TxDescArray = NULL;
4705 tp->RxDescArray = NULL;
4706
e1759441
RW		 4707 pm_runtime_put_sync(&pdev->dev);
4708
1da177e4
LT		 4709 return 0;
4710}
4711
dc1c00ce
FR		 4712#ifdef CONFIG_NET_POLL_CONTROLLER
4713static void rtl8169_netpoll(struct net_device *dev)
4714{
4715 struct rtl8169_private *tp = netdev_priv(dev);
4716
1bd32771 4717 rtl8169_interrupt(tp->irq, tp);
dc1c00ce
FR		 4718}
4719#endif
4720
df43ac78
FR		 4721static int rtl_open(struct net_device *dev)
4722{
4723 struct rtl8169_private *tp = netdev_priv(dev);
df43ac78 4724 struct pci_dev *pdev = tp->pci_dev;
870f531e 4725 unsigned long irqflags;
df43ac78
FR		 4726 int retval = -ENOMEM;
4727
4728 pm_runtime_get_sync(&pdev->dev);
4729
4730 /*
e75d6606 4731 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 4732 * dma_alloc_coherent provides more.
4733 */
4734 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4735 &tp->TxPhyAddr, GFP_KERNEL);
4736 if (!tp->TxDescArray)
1c470b53 4737 goto out;
df43ac78
FR		 4738
4739 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4740 &tp->RxPhyAddr, GFP_KERNEL);
4741 if (!tp->RxDescArray)
4742 goto err_free_tx_0;
4743
b1127e64 4744 retval = rtl8169_init_ring(tp);
df43ac78
FR		 4745 if (retval < 0)
4746 goto err_free_rx_1;
4747
df43ac78
FR		 4748 rtl_request_firmware(tp);
4749
870f531e 4750 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED;
1bd32771 4751 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp);
df43ac78
FR		 4752 if (retval < 0)
4753 goto err_release_fw_2;
4754
f1e911d5
HK		 4755 retval = r8169_phy_connect(tp);
4756 if (retval)
4757 goto err_free_irq;
4758
567ca57f 4759 rtl8169_up(tp);
d56f58ce 4760 rtl8169_init_counter_offsets(tp);
df43ac78 4761 netif_start_queue(dev);
df43ac78 4762out:
1c470b53
HK		 4763 pm_runtime_put_sync(&pdev->dev);
4764
df43ac78
FR		 4765 return retval;
4766
f1e911d5 4767err_free_irq:
1bd32771 4768 free_irq(tp->irq, tp);
df43ac78
FR		 4769err_release_fw_2:
4770 rtl_release_firmware(tp);
4771 rtl8169_rx_clear(tp);
4772err_free_rx_1:
4773 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4774 tp->RxPhyAddr);
4775 tp->RxDescArray = NULL;
4776err_free_tx_0:
4777 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4778 tp->TxPhyAddr);
4779 tp->TxDescArray = NULL;
df43ac78
FR		 4780 goto out;
4781}
4782
bc1f4470 4783static void
8027aa24 4784rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 4785{
4786 struct rtl8169_private *tp = netdev_priv(dev);
f09cf4b7 4787 struct pci_dev *pdev = tp->pci_dev;
42020320 4788 struct rtl8169_counters *counters = tp->counters;
1da177e4 4789
f09cf4b7
CHL		 4790 pm_runtime_get_noresume(&pdev->dev);
4791
314a9cbb 4792 netdev_stats_to_stats64(stats, &dev->stats);
5e4cb480 4793 dev_fetch_sw_netstats(stats, dev->tstats);
8027aa24 4794
6e85d5ad 4795 /*
ed72a9bb 4796 * Fetch additional counter values missing in stats collected by driver
6e85d5ad
CV		 4797 * from tally counters.
4798 */
f09cf4b7 4799 if (pm_runtime_active(&pdev->dev))
e71c9ce2 4800 rtl8169_update_counters(tp);
6e85d5ad
CV		 4801
4802 /*
4803 * Subtract values fetched during initalization.
4804 * See rtl8169_init_counter_offsets for a description why we do that.
4805 */
42020320 4806 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6e85d5ad 4807 le64_to_cpu(tp->tc_offset.tx_errors);
42020320 4808 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6e85d5ad 4809 le32_to_cpu(tp->tc_offset.tx_multi_collision);
42020320 4810 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6e85d5ad 4811 le16_to_cpu(tp->tc_offset.tx_aborted);
0da3359a
HK		 4812 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
4813 le16_to_cpu(tp->tc_offset.rx_missed);
6e85d5ad 4814
f09cf4b7 4815 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 4816}
4817
27dc36ae 4818static void rtl8169_net_suspend(struct rtl8169_private *tp)
5d06a99f 4819{
27dc36ae 4820 netif_device_detach(tp->dev);
476c4f5d
HK		 4821
4822 if (netif_running(tp->dev))
4823 rtl8169_down(tp);
861ab440
RW		 4824}
4825
06e56697 4826static int rtl8169_runtime_resume(struct device *dev)
bb13a800 4827{
06e56697
HK		 4828 struct rtl8169_private *tp = dev_get_drvdata(dev);
4829
bb13a800 4830 rtl_rar_set(tp, tp->dev->dev_addr);
06e56697 4831 __rtl8169_set_wol(tp, tp->saved_wolopts);
bb13a800
HK		 4832
4833 if (tp->TxDescArray)
4834 rtl8169_up(tp);
4835
4836 netif_device_attach(tp->dev);
4837
4838 return 0;
4839}
4840
8fe6e670 4841static int rtl8169_suspend(struct device *device)
861ab440 4842{
27dc36ae 4843 struct rtl8169_private *tp = dev_get_drvdata(device);
5d06a99f 4844
abe5fc42 4845 rtnl_lock();
27dc36ae 4846 rtl8169_net_suspend(tp);
bb13a800
HK		 4847 if (!device_may_wakeup(tp_to_dev(tp)))
4848 clk_disable_unprepare(tp->clk);
abe5fc42 4849 rtnl_unlock();
1371fa6d 4850
5d06a99f
FR		 4851 return 0;
4852}
4853
8fe6e670 4854static int rtl8169_resume(struct device *device)
5d06a99f 4855{
27dc36ae 4856 struct rtl8169_private *tp = dev_get_drvdata(device);
ac8bd9e1 4857
bb13a800
HK		 4858 if (!device_may_wakeup(tp_to_dev(tp)))
4859 clk_prepare_enable(tp->clk);
5d06a99f 4860
ef9da46d
HK		 4861 /* Reportedly at least Asus X453MA truncates packets otherwise */
4862 if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4863 rtl_init_rxcfg(tp);
476c4f5d 4864
06e56697 4865 return rtl8169_runtime_resume(device);
e1759441
RW		 4866}
4867
4868static int rtl8169_runtime_suspend(struct device *device)
4869{
27dc36ae 4870 struct rtl8169_private *tp = dev_get_drvdata(device);
e1759441 4871
476c4f5d
HK		 4872 if (!tp->TxDescArray) {
4873 netif_device_detach(tp->dev);
e1759441 4874 return 0;
476c4f5d 4875 }
e1759441 4876
abe5fc42 4877 rtnl_lock();
01bd753d 4878 __rtl8169_set_wol(tp, WAKE_PHY);
27dc36ae 4879 rtl8169_net_suspend(tp);
abe5fc42 4880 rtnl_unlock();
e1759441
RW		 4881
4882 return 0;
4883}
4884
e1759441
RW		 4885static int rtl8169_runtime_idle(struct device *device)
4886{
27dc36ae 4887 struct rtl8169_private *tp = dev_get_drvdata(device);
e1759441 4888
0ab0c45d 4889 if (tp->dash_enabled)
54744510
HK		 4890 return -EBUSY;
4891
27dc36ae 4892 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
a92a0849
HK		 4893 pm_schedule_suspend(device, 10000);
4894
4895 return -EBUSY;
e1759441
RW		 4896}
4897
47145210 4898static const struct dev_pm_ops rtl8169_pm_ops = {
8fe6e670
HK		 4899 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
4900 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
4901 rtl8169_runtime_idle)
861ab440
RW		 4902};
4903
1765f95d
FR		 4904static void rtl_shutdown(struct pci_dev *pdev)
4905{
27dc36ae 4906 struct rtl8169_private *tp = pci_get_drvdata(pdev);
861ab440 4907
abe5fc42 4908 rtnl_lock();
27dc36ae 4909 rtl8169_net_suspend(tp);
abe5fc42 4910 rtnl_unlock();
1765f95d 4911
cecb5fd7 4912 /* Restore original MAC address */
27dc36ae 4913 rtl_rar_set(tp, tp->dev->perm_addr);
cc098dc7 4914
0ab0c45d 4915 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) {
bb703e57 4916 pci_wake_from_d3(pdev, tp->saved_wolopts);
861ab440
RW		 4917 pci_set_power_state(pdev, PCI_D3hot);
4918 }
4919}
5d06a99f 4920
baf63293 4921static void rtl_remove_one(struct pci_dev *pdev)
e27566ed 4922{
27dc36ae 4923 struct rtl8169_private *tp = pci_get_drvdata(pdev);
e27566ed 4924
12b1bc75
HK		 4925 if (pci_dev_run_wake(pdev))
4926 pm_runtime_get_noresume(&pdev->dev);
ad1be8d3 4927
27dc36ae 4928 unregister_netdev(tp->dev);
e27566ed 4929
e0d38b58 4930 if (tp->dash_type != RTL_DASH_NONE)
12b1bc75 4931 rtl8168_driver_stop(tp);
e27566ed 4932
12b1bc75 4933 rtl_release_firmware(tp);
e27566ed
FR		 4934
4935 /* restore original MAC address */
27dc36ae 4936 rtl_rar_set(tp, tp->dev->perm_addr);
e27566ed
FR		 4937}
4938
fa9c385e 4939static const struct net_device_ops rtl_netdev_ops = {
df43ac78 4940 .ndo_open = rtl_open,
fa9c385e
FR		 4941 .ndo_stop = rtl8169_close,
4942 .ndo_get_stats64 = rtl8169_get_stats64,
4943 .ndo_start_xmit = rtl8169_start_xmit,
e64e0c89 4944 .ndo_features_check = rtl8169_features_check,
fa9c385e
FR		 4945 .ndo_tx_timeout = rtl8169_tx_timeout,
4946 .ndo_validate_addr = eth_validate_addr,
4947 .ndo_change_mtu = rtl8169_change_mtu,
4948 .ndo_fix_features = rtl8169_fix_features,
4949 .ndo_set_features = rtl8169_set_features,
4950 .ndo_set_mac_address = rtl_set_mac_address,
a7605370 4951 .ndo_eth_ioctl = phy_do_ioctl_running,
fa9c385e
FR		 4952 .ndo_set_rx_mode = rtl_set_rx_mode,
4953#ifdef CONFIG_NET_POLL_CONTROLLER
4954 .ndo_poll_controller = rtl8169_netpoll,
4955#endif
4956
4957};
4958
ec9a4088
HK		 4959static void rtl_set_irq_mask(struct rtl8169_private *tp)
4960{
2045e158 4961 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
ec9a4088
HK		 4962
4963 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4964 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
4965 else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
4966 /* special workaround needed */
4967 tp->irq_mask |= RxFIFOOver;
4968 else
4969 tp->irq_mask |= RxOverflow;
4970}
4971
6c6aa15f 4972static int rtl_alloc_irq(struct rtl8169_private *tp)
31fa8b18 4973{
6c6aa15f 4974 unsigned int flags;
31fa8b18 4975
003bd5b4
HK		 4976 switch (tp->mac_version) {
4977 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
df320ed7 4978 rtl_unlock_config_regs(tp);
1ef7286e 4979 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
df320ed7 4980 rtl_lock_config_regs(tp);
df561f66 4981 fallthrough;
f13bc681 4982 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
6c6aa15f 4983 flags = PCI_IRQ_LEGACY;
003bd5b4
HK		 4984 break;
4985 default:
6c6aa15f 4986 flags = PCI_IRQ_ALL_TYPES;
003bd5b4 4987 break;
31fa8b18 4988 }
6c6aa15f
HK		 4989
4990 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
31fa8b18
FR		 4991}
4992
04c7788c
TR		 4993static void rtl_read_mac_address(struct rtl8169_private *tp,
4994 u8 mac_addr[ETH_ALEN])
4995{
4996 /* Get MAC address */
9e9f33ba 4997 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
ae1e82c6 4998 u32 value;
deedf1fe 4999
ae1e82c6
HK		 5000 value = rtl_eri_read(tp, 0xe0);
5001 put_unaligned_le32(value, mac_addr);
724c6fd0 5002 value = rtl_eri_read(tp, 0xe4);
ae1e82c6 5003 put_unaligned_le16(value, mac_addr + 4);
f1bce4ad
HK		 5004 } else if (rtl_is_8125(tp)) {
5005 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
04c7788c
TR		 5006 }
5007}
5008
c558386b
HW		 5009DECLARE_RTL_COND(rtl_link_list_ready_cond)
5010{
1ef7286e 5011 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
c558386b
HW		 5012}
5013
e031ce80
HK		 5014static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
5015{
5016 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
5017}
5018
f1e911d5
HK		 5019static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
5020{
5021 struct rtl8169_private *tp = mii_bus->priv;
5022
5023 if (phyaddr > 0)
5024 return -ENODEV;
5025
5026 return rtl_readphy(tp, phyreg);
5027}
5028
5029static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
5030 int phyreg, u16 val)
5031{
5032 struct rtl8169_private *tp = mii_bus->priv;
5033
5034 if (phyaddr > 0)
5035 return -ENODEV;
5036
5037 rtl_writephy(tp, phyreg, val);
5038
5039 return 0;
5040}
5041
5042static int r8169_mdio_register(struct rtl8169_private *tp)
5043{
5044 struct pci_dev *pdev = tp->pci_dev;
f1e911d5
HK		 5045 struct mii_bus *new_bus;
5046 int ret;
5047
5048 new_bus = devm_mdiobus_alloc(&pdev->dev);
5049 if (!new_bus)
5050 return -ENOMEM;
5051
5052 new_bus->name = "r8169";
5053 new_bus->priv = tp;
5054 new_bus->parent = &pdev->dev;
93e8990c 5055 new_bus->irq[0] = PHY_MAC_INTERRUPT;
e9a72f87
SP		 5056 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x",
5057 pci_domain_nr(pdev->bus), pci_dev_id(pdev));
f1e911d5
HK		 5058
5059 new_bus->read = r8169_mdio_read_reg;
5060 new_bus->write = r8169_mdio_write_reg;
5061
ac3a68d5 5062 ret = devm_mdiobus_register(&pdev->dev, new_bus);
f1e911d5
HK		 5063 if (ret)
5064 return ret;
5065
703732f0
HK		 5066 tp->phydev = mdiobus_get_phy(new_bus, 0);
5067 if (!tp->phydev) {
f1e911d5 5068 return -ENODEV;
2e8c339b
HK		 5069 } else if (!tp->phydev->drv) {
5070 /* Most chip versions fail with the genphy driver.
5071 * Therefore ensure that the dedicated PHY driver is loaded.
5072 */
0c2006b2
HK		 5073 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5074 tp->phydev->phy_id);
2e8c339b 5075 return -EUNATCH;
f1e911d5
HK		 5076 }
5077
eca485d2 5078 tp->phydev->mac_managed_pm = true;
5c2280fc 5079
11ac4e66
HK		 5080 phy_support_asym_pause(tp->phydev);
5081
242cd9b5 5082 /* PHY will be woken up in rtl_open() */
703732f0 5083 phy_suspend(tp->phydev);
f1e911d5
HK		 5084
5085 return 0;
5086}
5087
baf63293 5088static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b 5089{
9617886f 5090 rtl_enable_rxdvgate(tp);
c558386b 5091
1ef7286e 5092 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
c558386b 5093 msleep(1);
1ef7286e 5094 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
c558386b 5095
ef712ede 5096 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
e031ce80 5097 r8168g_wait_ll_share_fifo_ready(tp);
c558386b 5098
ef712ede 5099 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
e031ce80 5100 r8168g_wait_ll_share_fifo_ready(tp);
c558386b
HW		 5101}
5102
f1bce4ad
HK		 5103static void rtl_hw_init_8125(struct rtl8169_private *tp)
5104{
9617886f 5105 rtl_enable_rxdvgate(tp);
f1bce4ad 5106
f1bce4ad
HK		 5107 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5108 msleep(1);
5109 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5110
5111 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
e031ce80 5112 r8168g_wait_ll_share_fifo_ready(tp);
f1bce4ad
HK		 5113
5114 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5115 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5116 r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
e031ce80 5117 r8168g_wait_ll_share_fifo_ready(tp);
f1bce4ad
HK		 5118}
5119
baf63293 5120static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 5121{
5122 switch (tp->mac_version) {
133706a9 5123 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53:
29ec0482 5124 rtl8168ep_stop_cmac(tp);
df561f66 5125 fallthrough;
2a71883c 5126 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
003609da
CHL		 5127 rtl_hw_init_8168g(tp);
5128 break;
efc37109 5129 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
f1bce4ad
HK		 5130 rtl_hw_init_8125(tp);
5131 break;
c558386b
HW		 5132 default:
5133 break;
5134 }
5135}
5136
abe8b2f7
HK		 5137static int rtl_jumbo_max(struct rtl8169_private *tp)
5138{
5139 /* Non-GBit versions don't support jumbo frames */
5140 if (!tp->supports_gmii)
a8ec173a 5141 return 0;
abe8b2f7
HK		 5142
5143 switch (tp->mac_version) {
5144 /* RTL8169 */
e9588eb9 5145 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
abe8b2f7
HK		 5146 return JUMBO_7K;
5147 /* RTL8168b */
5148 case RTL_GIGA_MAC_VER_11:
abe8b2f7
HK		 5149 case RTL_GIGA_MAC_VER_17:
5150 return JUMBO_4K;
5151 /* RTL8168c */
5152 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5153 return JUMBO_6K;
5154 default:
5155 return JUMBO_9K;
5156 }
5157}
5158
c782e204
HK		 5159static void rtl_init_mac_address(struct rtl8169_private *tp)
5160{
c75a9ad4 5161 u8 mac_addr[ETH_ALEN] __aligned(2) = {};
c782e204 5162 struct net_device *dev = tp->dev;
ce37115e 5163 int rc;
c782e204
HK		 5164
5165 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5166 if (!rc)
5167 goto done;
5168
5169 rtl_read_mac_address(tp, mac_addr);
5170 if (is_valid_ether_addr(mac_addr))
5171 goto done;
5172
ce37115e 5173 rtl_read_mac_from_reg(tp, mac_addr, MAC0);
c782e204
HK		 5174 if (is_valid_ether_addr(mac_addr))
5175 goto done;
5176
c75a9ad4
HK		 5177 eth_random_addr(mac_addr);
5178 dev->addr_assign_type = NET_ADDR_RANDOM;
c782e204
HK		 5179 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5180done:
1c5d09d5 5181 eth_hw_addr_set(dev, mac_addr);
c782e204
HK		 5182 rtl_rar_set(tp, mac_addr);
5183}
5184
cf2ffdea
HK		 5185/* register is set if system vendor successfully tested ASPM 1.2 */
5186static bool rtl_aspm_is_safe(struct rtl8169_private *tp)
5187{
5188 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 &&
5189 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf)
5190 return true;
5191
5192 return false;
5193}
5194
929a031d 5195static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3b6cf25d 5196{
3b6cf25d 5197 struct rtl8169_private *tp;
f1f9ca28
HK		 5198 int jumbo_max, region, rc;
5199 enum mac_version chipset;
3b6cf25d 5200 struct net_device *dev;
bc590b47 5201 u32 txconfig;
f1f9ca28 5202 u16 xid;
3b6cf25d 5203
4c45d24a
HK		 5204 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5205 if (!dev)
5206 return -ENOMEM;
3b6cf25d
FR		 5207
5208 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 5209 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 5210 tp = netdev_priv(dev);
5211 tp->dev = dev;
5212 tp->pci_dev = pdev;
145a40e8 5213 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
7ec3f872 5214 tp->eee_adv = -1;
0360c046 5215 tp->ocp_base = OCP_STD_PHY_BASE;
3b6cf25d 5216
d6c36cbc
SAS		 5217 raw_spin_lock_init(&tp->cfg9346_usage_lock);
5218 raw_spin_lock_init(&tp->config25_lock);
5219 raw_spin_lock_init(&tp->mac_ocp_lock);
91c86435 5220
5e4cb480
HK		 5221 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev,
5222 struct pcpu_sw_netstats);
5223 if (!dev->tstats)
5224 return -ENOMEM;
5225
c2f6f3ee 5226 /* Get the *optional* external "ether_clk" used on some boards */
599566c1
HK		 5227 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk");
5228 if (IS_ERR(tp->clk))
5229 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n");
c2f6f3ee 5230
3b6cf25d 5231 /* enable device (incl. PCI PM wakeup and hotplug setup) */
4c45d24a 5232 rc = pcim_enable_device(pdev);
733b3e27
HK		 5233 if (rc < 0)
5234 return dev_err_probe(&pdev->dev, rc, "enable failure\n");
3b6cf25d 5235
4c45d24a 5236 if (pcim_set_mwi(pdev) < 0)
22148df0 5237 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
3b6cf25d 5238
c8d48d9c
HK		 5239 /* use first MMIO region */
5240 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
733b3e27
HK		 5241 if (region < 0)
5242 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n");
3b6cf25d 5243
7cb7541a 5244 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME);
733b3e27
HK		 5245 if (rc < 0)
5246 return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n");
3b6cf25d 5247
93a00d4d 5248 tp->mmio_addr = pcim_iomap_table(pdev)[region];
3b6cf25d 5249
bc590b47 5250 txconfig = RTL_R32(tp, TxConfig);
733b3e27
HK		 5251 if (txconfig == ~0U)
5252 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n");
bc590b47
HK		 5253
5254 xid = (txconfig >> 20) & 0xfcf;
f1f9ca28 5255
3b6cf25d 5256 /* Identify chip attached to board */
f1f9ca28 5257 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
733b3e27
HK		 5258 if (chipset == RTL_GIGA_MAC_NONE)
5259 return dev_err_probe(&pdev->dev, -ENODEV,
5260 "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n",
5261 xid);
f1f9ca28 5262 tp->mac_version = chipset;
3b6cf25d 5263
cf2ffdea
HK		 5264 /* Disable ASPM L1 as that cause random device stop working
5265 * problems as well as full system hangs for some PCIe devices users.
cf2ffdea
HK		 5266 */
5267 if (rtl_aspm_is_safe(tp))
5268 rc = 0;
cf2ffdea
HK		 5269 else
5270 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1);
5271 tp->aspm_manageable = !rc;
5272
0ab0c45d
CL		 5273 tp->dash_type = rtl_get_dash_type(tp);
5274 tp->dash_enabled = rtl_dash_is_enabled(tp);
e0d38b58 5275
975e8505 5276 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
27896c83 5277
10b63e85 5278 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
3c18cbe3 5279 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
27896c83 5280 dev->features |= NETIF_F_HIGHDMA;
27896c83 5281
3b6cf25d
FR		 5282 rtl_init_rxcfg(tp);
5283
de20e12f 5284 rtl8169_irq_mask_and_ack(tp);
3b6cf25d 5285
c558386b
HW		 5286 rtl_hw_initialize(tp);
5287
3b6cf25d
FR		 5288 rtl_hw_reset(tp);
5289
6c6aa15f 5290 rc = rtl_alloc_irq(tp);
733b3e27
HK		 5291 if (rc < 0)
5292 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n");
5293
1bd32771 5294 tp->irq = pci_irq_vector(pdev, 0);
3b6cf25d 5295
5c41e78f 5296 INIT_WORK(&tp->wk.work, rtl_task);
3b6cf25d 5297
c782e204 5298 rtl_init_mac_address(tp);
3b6cf25d 5299
7ad24ea4 5300 dev->ethtool_ops = &rtl8169_ethtool_ops;
3b6cf25d 5301
b48b89f9 5302 netif_napi_add(dev, &tp->napi, rtl8169_poll);
3b6cf25d 5303
95099c56
HK		 5304 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5305 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
a9b3d568 5306 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
2d0ec544 5307 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
3b6cf25d 5308
929a031d 5309 /*
5310 * Pretend we are using VLANs; This bypasses a nasty bug where
5311 * Interrupts stop flowing on high load on 8110SCd controllers.
5312 */
3b6cf25d 5313 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
929a031d 5314 /* Disallow toggling */
f646968f 5315 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d 5316
95099c56
HK		 5317 if (rtl_chip_supports_csum_v2(tp))
5318 dev->hw_features |= NETIF_F_IPV6_CSUM;
5319
5320 dev->features |= dev->hw_features;
5321
5322 /* There has been a number of reports that using SG/TSO results in
5323 * tx timeouts. However for a lot of people SG/TSO works fine.
5324 * Therefore disable both features by default, but allow users to
5325 * enable them. Use at own risk!
5326 */
0170d594 5327 if (rtl_chip_supports_csum_v2(tp)) {
95099c56 5328 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
ee8b7a11
JK		 5329 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2);
5330 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2);
0170d594 5331 } else {
95099c56 5332 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
ee8b7a11
JK		 5333 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1);
5334 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1);
0170d594 5335 }
5888d3fc 5336
3b6cf25d
FR		 5337 dev->hw_features |= NETIF_F_RXALL;
5338 dev->hw_features |= NETIF_F_RXFCS;
5339
42f66a44
HK		 5340 netdev_sw_irq_coalesce_default_on(dev);
5341
145192f8
HK		 5342 /* configure chip for default features */
5343 rtl8169_set_features(dev, dev->features);
5344
0ab0c45d 5345 if (!tp->dash_enabled) {
54744510
HK		 5346 rtl_set_d3_pll_down(tp, true);
5347 } else {
5348 rtl_set_d3_pll_down(tp, false);
5349 dev->wol_enabled = 1;
5350 }
128735a1 5351
abe8b2f7 5352 jumbo_max = rtl_jumbo_max(tp);
a8ec173a
HK		 5353 if (jumbo_max)
5354 dev->max_mtu = jumbo_max;
c7315a95 5355
ec9a4088 5356 rtl_set_irq_mask(tp);
9fa0a8e1 5357
254764e5 5358 tp->fw_name = rtl_chip_infos[chipset].fw_name;
3b6cf25d 5359
4c45d24a
HK		 5360 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5361 &tp->counters_phys_addr,
5362 GFP_KERNEL);
4cf964af
HK		 5363 if (!tp->counters)
5364 return -ENOMEM;
42020320 5365
27dc36ae 5366 pci_set_drvdata(pdev, tp);
19c9ea36 5367
f1e911d5
HK		 5368 rc = r8169_mdio_register(tp);
5369 if (rc)
4cf964af 5370 return rc;
3b6cf25d 5371
f1e911d5
HK		 5372 rc = register_netdev(dev);
5373 if (rc)
0785dad4 5374 return rc;
f1e911d5 5375
93882c6f 5376 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n",
1bd32771 5377 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq);
abe8b2f7 5378
a8ec173a 5379 if (jumbo_max)
93882c6f
HK		 5380 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5381 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5382 "ok" : "ko");
3b6cf25d 5383
e0d38b58 5384 if (tp->dash_type != RTL_DASH_NONE) {
0ab0c45d
CL		 5385 netdev_info(dev, "DASH %s\n",
5386 tp->dash_enabled ? "enabled" : "disabled");
3b6cf25d 5387 rtl8168_driver_start(tp);
a38b7fbf 5388 }
3b6cf25d 5389
a92a0849
HK		 5390 if (pci_dev_run_wake(pdev))
5391 pm_runtime_put_sync(&pdev->dev);
5392
4c45d24a 5393 return 0;
3b6cf25d
FR		 5394}
5395
1da177e4 5396static struct pci_driver rtl8169_pci_driver = {
7cb7541a 5397 .name = KBUILD_MODNAME,
1da177e4 5398 .id_table = rtl8169_pci_tbl,
3b6cf25d 5399 .probe = rtl_init_one,
baf63293 5400 .remove = rtl_remove_one,
1765f95d 5401 .shutdown = rtl_shutdown,
8fe6e670 5402 .driver.pm = pm_ptr(&rtl8169_pm_ops),
1da177e4
LT		 5403};
5404
3eeb7da9 5405module_pci_driver(rtl8169_pci_driver);
Linux 6.x block layer and io_uring tree(s)