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netdev: pass the stuck queue to the timeout handler
[linux-block.git] / drivers / net / ethernet / realtek / r8169_main.c
CommitLineData
09c434b8 1// SPDX-License-Identifier: GPL-2.0-only
1da177e4 2/*
07d3f51f
FR		 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 *
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
8 *
9 * See MAINTAINERS file for support contact information.
1da177e4
LT		 10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/pci.h>
15#include <linux/netdevice.h>
16#include <linux/etherdevice.h>
c2f6f3ee 17#include <linux/clk.h>
1da177e4
LT		 18#include <linux/delay.h>
19#include <linux/ethtool.h>
f1e911d5 20#include <linux/phy.h>
1da177e4
LT		 21#include <linux/if_vlan.h>
22#include <linux/crc32.h>
23#include <linux/in.h>
098b01ad 24#include <linux/io.h>
1da177e4
LT		 25#include <linux/ip.h>
26#include <linux/tcp.h>
a6b7a407 27#include <linux/interrupt.h>
1da177e4 28#include <linux/dma-mapping.h>
e1759441 29#include <linux/pm_runtime.h>
70c71606 30#include <linux/prefetch.h>
e974604b 31#include <linux/ipv6.h>
32#include <net/ip6_checksum.h>
1da177e4 33
8197f9d2
HK		 34#include "r8169_firmware.h"
35
1da177e4 36#define MODULENAME "r8169"
1da177e4 37
bca03d5f 38#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 40#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 42#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 43#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
44#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 45#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 46#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 47#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45dd95c4 48#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
5598bfe5 49#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
58152cd4 50#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
beb330a4 51#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
57538c4a 52#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
6e1d0b89
CHL		 53#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
54#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
229c1e0d 55#define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw"
6e1d0b89
CHL		 56#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
57#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
02bf642b 58#define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw"
bca03d5f 59
b57b7e5a 60#define R8169_MSG_DEFAULT \
f0e837d9 61 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 62
1da177e4
LT		 63/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
64 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
81cd17a4 65#define MC_FILTER_LIMIT 32
1da177e4 66
aee77e4a 67#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 68#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
69
70#define R8169_REGS_SIZE 256
1d0254dd 71#define R8169_RX_BUF_SIZE (SZ_16K - 1)
1da177e4 72#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 73#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 74#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
75#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
76
145a40e8
HK		 77#define RTL_CFG_NO_GBIT 1
78
1da177e4 79/* write/read MMIO register */
1ef7286e
AS		 80#define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
81#define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
82#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
83#define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
84#define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
85#define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
1da177e4
LT		 86
87enum mac_version {
e9588eb9 88 /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */
85bffe6c
FR		 89 RTL_GIGA_MAC_VER_02,
90 RTL_GIGA_MAC_VER_03,
91 RTL_GIGA_MAC_VER_04,
92 RTL_GIGA_MAC_VER_05,
93 RTL_GIGA_MAC_VER_06,
94 RTL_GIGA_MAC_VER_07,
95 RTL_GIGA_MAC_VER_08,
96 RTL_GIGA_MAC_VER_09,
97 RTL_GIGA_MAC_VER_10,
98 RTL_GIGA_MAC_VER_11,
99 RTL_GIGA_MAC_VER_12,
100 RTL_GIGA_MAC_VER_13,
101 RTL_GIGA_MAC_VER_14,
102 RTL_GIGA_MAC_VER_15,
103 RTL_GIGA_MAC_VER_16,
104 RTL_GIGA_MAC_VER_17,
105 RTL_GIGA_MAC_VER_18,
106 RTL_GIGA_MAC_VER_19,
107 RTL_GIGA_MAC_VER_20,
108 RTL_GIGA_MAC_VER_21,
109 RTL_GIGA_MAC_VER_22,
110 RTL_GIGA_MAC_VER_23,
111 RTL_GIGA_MAC_VER_24,
112 RTL_GIGA_MAC_VER_25,
113 RTL_GIGA_MAC_VER_26,
114 RTL_GIGA_MAC_VER_27,
115 RTL_GIGA_MAC_VER_28,
116 RTL_GIGA_MAC_VER_29,
117 RTL_GIGA_MAC_VER_30,
118 RTL_GIGA_MAC_VER_31,
119 RTL_GIGA_MAC_VER_32,
120 RTL_GIGA_MAC_VER_33,
70090424 121 RTL_GIGA_MAC_VER_34,
c2218925
HW		 122 RTL_GIGA_MAC_VER_35,
123 RTL_GIGA_MAC_VER_36,
7e18dca1 124 RTL_GIGA_MAC_VER_37,
b3d7b2f2 125 RTL_GIGA_MAC_VER_38,
5598bfe5 126 RTL_GIGA_MAC_VER_39,
c558386b
HW		 127 RTL_GIGA_MAC_VER_40,
128 RTL_GIGA_MAC_VER_41,
57538c4a 129 RTL_GIGA_MAC_VER_42,
58152cd4 130 RTL_GIGA_MAC_VER_43,
45dd95c4 131 RTL_GIGA_MAC_VER_44,
6e1d0b89
CHL		 132 RTL_GIGA_MAC_VER_45,
133 RTL_GIGA_MAC_VER_46,
134 RTL_GIGA_MAC_VER_47,
135 RTL_GIGA_MAC_VER_48,
935e2218
CHL		 136 RTL_GIGA_MAC_VER_49,
137 RTL_GIGA_MAC_VER_50,
138 RTL_GIGA_MAC_VER_51,
1287723a 139 RTL_GIGA_MAC_VER_52,
f1bce4ad
HK		 140 RTL_GIGA_MAC_VER_60,
141 RTL_GIGA_MAC_VER_61,
76719ee2 142 RTL_GIGA_MAC_NONE
1da177e4
LT		 143};
144
d58d46b5
FR		 145#define JUMBO_1K ETH_DATA_LEN
146#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
147#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
148#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
149#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
150
3c6bee1d 151static const struct {
1da177e4 152 const char *name;
953a12cc 153 const char *fw_name;
85bffe6c
FR		 154} rtl_chip_infos[] = {
155 /* PCI devices. */
abe8b2f7
HK		 156 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
157 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
158 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
159 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
160 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
85bffe6c 161 /* PCI-E devices. */
abe8b2f7
HK		 162 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
163 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
9e0773c3 164 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" },
abe8b2f7
HK		 165 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
166 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
167 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
168 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
169 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
170 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
171 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
172 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
173 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
174 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
175 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
176 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
177 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
178 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
179 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
180 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
181 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
182 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
183 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
184 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
185 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
186 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
187 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
188 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
189 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
190 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
191 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
192 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
193 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
194 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
195 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
196 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
9e0773c3
HK		 197 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3},
198 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2},
199 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 },
abe8b2f7
HK		 200 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
201 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
202 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
203 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
204 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
205 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
206 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
229c1e0d 207 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3},
f1bce4ad 208 [RTL_GIGA_MAC_VER_60] = {"RTL8125" },
02bf642b 209 [RTL_GIGA_MAC_VER_61] = {"RTL8125", FIRMWARE_8125A_3},
953a12cc
FR		 210};
211
9baa3c34 212static const struct pci_device_id rtl8169_pci_tbl[] = {
145a40e8
HK		 213 { PCI_VDEVICE(REALTEK, 0x2502) },
214 { PCI_VDEVICE(REALTEK, 0x2600) },
215 { PCI_VDEVICE(REALTEK, 0x8129) },
216 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
217 { PCI_VDEVICE(REALTEK, 0x8161) },
218 { PCI_VDEVICE(REALTEK, 0x8167) },
219 { PCI_VDEVICE(REALTEK, 0x8168) },
220 { PCI_VDEVICE(NCUBE, 0x8168) },
221 { PCI_VDEVICE(REALTEK, 0x8169) },
6f0d3088 222 { PCI_VENDOR_ID_DLINK, 0x4300,
145a40e8 223 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
9d9f3fba
HK		 224 { PCI_VDEVICE(DLINK, 0x4300) },
225 { PCI_VDEVICE(DLINK, 0x4302) },
226 { PCI_VDEVICE(AT, 0xc107) },
227 { PCI_VDEVICE(USR, 0x0116) },
228 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
229 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
f1bce4ad
HK		 230 { PCI_VDEVICE(REALTEK, 0x8125) },
231 { PCI_VDEVICE(REALTEK, 0x3000) },
6f0d3088 232 {}
1da177e4
LT		 233};
234
235MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
236
b57b7e5a
SH		 237static struct {
238 u32 msg_enable;
239} debug = { -1 };
1da177e4 240
07d3f51f
FR		 241enum rtl_registers {
242 MAC0 = 0, /* Ethernet hardware address. */
773d2021 243 MAC4 = 4,
07d3f51f
FR		 244 MAR0 = 8, /* Multicast filter. */
245 CounterAddrLow = 0x10,
246 CounterAddrHigh = 0x14,
247 TxDescStartAddrLow = 0x20,
248 TxDescStartAddrHigh = 0x24,
249 TxHDescStartAddrLow = 0x28,
250 TxHDescStartAddrHigh = 0x2c,
251 FLASH = 0x30,
252 ERSR = 0x36,
253 ChipCmd = 0x37,
254 TxPoll = 0x38,
255 IntrMask = 0x3c,
256 IntrStatus = 0x3e,
4f6b00e5 257
07d3f51f 258 TxConfig = 0x40,
4f6b00e5
HW		 259#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
260#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 261
4f6b00e5
HW		 262 RxConfig = 0x44,
263#define RX128_INT_EN (1 << 15) /* 8111c and later */
264#define RX_MULTI_EN (1 << 14) /* 8111c only */
265#define RXCFG_FIFO_SHIFT 13
266 /* No threshold before first PCI xfer */
267#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 268#define RX_EARLY_OFF (1 << 11)
4f6b00e5
HW		 269#define RXCFG_DMA_SHIFT 8
270 /* Unlimited maximum PCI burst. */
271#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 272
07d3f51f
FR		 273 RxMissed = 0x4c,
274 Cfg9346 = 0x50,
275 Config0 = 0x51,
276 Config1 = 0x52,
277 Config2 = 0x53,
d387b427
FR		 278#define PME_SIGNAL (1 << 5) /* 8168c and later */
279
07d3f51f
FR		 280 Config3 = 0x54,
281 Config4 = 0x55,
282 Config5 = 0x56,
07d3f51f 283 PHYAR = 0x60,
07d3f51f
FR		 284 PHYstatus = 0x6c,
285 RxMaxSize = 0xda,
286 CPlusCmd = 0xe0,
287 IntrMitigate = 0xe2,
50970831
FR		 288
289#define RTL_COALESCE_MASK 0x0f
290#define RTL_COALESCE_SHIFT 4
291#define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
292#define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
293
07d3f51f
FR		 294 RxDescAddrLow = 0xe4,
295 RxDescAddrHigh = 0xe8,
f0298f81 296 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
297
298#define NoEarlyTx 0x3f /* Max value : no early transmit. */
299
300 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
301
302#define TxPacketMax (8064 >> 7)
3090bd9a 303#define EarlySize 0x27
f0298f81 304
07d3f51f
FR		 305 FuncEvent = 0xf0,
306 FuncEventMask = 0xf4,
307 FuncPresetState = 0xf8,
935e2218
CHL		 308 IBCR0 = 0xf8,
309 IBCR2 = 0xf9,
310 IBIMR0 = 0xfa,
311 IBISR0 = 0xfb,
07d3f51f 312 FuncForceEvent = 0xfc,
1da177e4
LT		 313};
314
f162a5d1
FR		 315enum rtl8168_8101_registers {
316 CSIDR = 0x64,
317 CSIAR = 0x68,
318#define CSIAR_FLAG 0x80000000
319#define CSIAR_WRITE_CMD 0x80000000
ff1d7331
HK		 320#define CSIAR_BYTE_ENABLE 0x0000f000
321#define CSIAR_ADDR_MASK 0x00000fff
065c27c1 322 PMCH = 0x6f,
f162a5d1
FR		 323 EPHYAR = 0x80,
324#define EPHYAR_FLAG 0x80000000
325#define EPHYAR_WRITE_CMD 0x80000000
326#define EPHYAR_REG_MASK 0x1f
327#define EPHYAR_REG_SHIFT 16
328#define EPHYAR_DATA_MASK 0xffff
5a5e4443 329 DLLPR = 0xd0,
4f6b00e5 330#define PFM_EN (1 << 6)
6e1d0b89 331#define TX_10M_PS_EN (1 << 7)
f162a5d1
FR		 332 DBG_REG = 0xd1,
333#define FIX_NAK_1 (1 << 4)
334#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 335 TWSI = 0xd2,
336 MCU = 0xd3,
4f6b00e5 337#define NOW_IS_OOB (1 << 7)
c558386b
HW		 338#define TX_EMPTY (1 << 5)
339#define RX_EMPTY (1 << 4)
340#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 341#define EN_NDP (1 << 3)
342#define EN_OOB_RESET (1 << 2)
c558386b 343#define LINK_LIST_RDY (1 << 1)
daf9df6d 344 EFUSEAR = 0xdc,
345#define EFUSEAR_FLAG 0x80000000
346#define EFUSEAR_WRITE_CMD 0x80000000
347#define EFUSEAR_READ_CMD 0x00000000
348#define EFUSEAR_REG_MASK 0x03ff
349#define EFUSEAR_REG_SHIFT 8
350#define EFUSEAR_DATA_MASK 0xff
6e1d0b89
CHL		 351 MISC_1 = 0xf2,
352#define PFM_D3COLD_EN (1 << 6)
f162a5d1
FR		 353};
354
c0e45c1c 355enum rtl8168_registers {
4f6b00e5
HW		 356 LED_FREQ = 0x1a,
357 EEE_LED = 0x1b,
b646d900 358 ERIDR = 0x70,
359 ERIAR = 0x74,
360#define ERIAR_FLAG 0x80000000
361#define ERIAR_WRITE_CMD 0x80000000
362#define ERIAR_READ_CMD 0x00000000
363#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 364#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 365#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
366#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
367#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
935e2218 368#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
4f6b00e5
HW		 369#define ERIAR_MASK_SHIFT 12
370#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
371#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
6e1d0b89 372#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
c558386b 373#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 374#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 375 EPHY_RXER_NUM = 0x7c,
376 OCPDR = 0xb0, /* OCP GPHY access */
377#define OCPDR_WRITE_CMD 0x80000000
378#define OCPDR_READ_CMD 0x00000000
379#define OCPDR_REG_MASK 0x7f
380#define OCPDR_GPHY_REG_SHIFT 16
381#define OCPDR_DATA_MASK 0xffff
382 OCPAR = 0xb4,
383#define OCPAR_FLAG 0x80000000
384#define OCPAR_GPHY_WRITE_CMD 0x8000f060
385#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 386 GPHY_OCP = 0xb8,
01dc7fec 387 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
388 MISC = 0xf0, /* 8168e only. */
cecb5fd7 389#define TXPLA_RST (1 << 29)
5598bfe5 390#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 391#define PWM_EN (1 << 22)
c558386b 392#define RXDV_GATED_EN (1 << 19)
5598bfe5 393#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 394};
395
f1bce4ad
HK		 396enum rtl8125_registers {
397 IntrMask_8125 = 0x38,
398 IntrStatus_8125 = 0x3c,
399 TxPoll_8125 = 0x90,
400 MAC0_BKP = 0x19e0,
401};
402
403#define RX_VLAN_INNER_8125 BIT(22)
404#define RX_VLAN_OUTER_8125 BIT(23)
405#define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
406
407#define RX_FETCH_DFLT_8125 (8 << 27)
408
07d3f51f 409enum rtl_register_content {
1da177e4 410 /* InterruptStatusBits */
07d3f51f
FR		 411 SYSErr = 0x8000,
412 PCSTimeout = 0x4000,
413 SWInt = 0x0100,
414 TxDescUnavail = 0x0080,
415 RxFIFOOver = 0x0040,
416 LinkChg = 0x0020,
417 RxOverflow = 0x0010,
418 TxErr = 0x0008,
419 TxOK = 0x0004,
420 RxErr = 0x0002,
421 RxOK = 0x0001,
1da177e4
LT		 422
423 /* RxStatusDesc */
9dccf611
FR		 424 RxRWT = (1 << 22),
425 RxRES = (1 << 21),
426 RxRUNT = (1 << 20),
427 RxCRC = (1 << 19),
1da177e4
LT		 428
429 /* ChipCmdBits */
4f6b00e5 430 StopReq = 0x80,
07d3f51f
FR		 431 CmdReset = 0x10,
432 CmdRxEnb = 0x08,
433 CmdTxEnb = 0x04,
434 RxBufEmpty = 0x01,
1da177e4 435
275391a4
FR		 436 /* TXPoll register p.5 */
437 HPQ = 0x80, /* Poll cmd on the high prio queue */
438 NPQ = 0x40, /* Poll cmd on the low prio queue */
439 FSWInt = 0x01, /* Forced software interrupt */
440
1da177e4 441 /* Cfg9346Bits */
07d3f51f
FR		 442 Cfg9346_Lock = 0x00,
443 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 444
445 /* rx_mode_bits */
07d3f51f
FR		 446 AcceptErr = 0x20,
447 AcceptRunt = 0x10,
448 AcceptBroadcast = 0x08,
449 AcceptMulticast = 0x04,
450 AcceptMyPhys = 0x02,
451 AcceptAllPhys = 0x01,
1687b566 452#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 453
1da177e4
LT		 454 /* TxConfigBits */
455 TxInterFrameGapShift = 24,
456 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
457
5d06a99f 458 /* Config1 register p.24 */
f162a5d1
FR		 459 LEDS1 = (1 << 7),
460 LEDS0 = (1 << 6),
f162a5d1
FR		 461 Speed_down = (1 << 4),
462 MEMMAP = (1 << 3),
463 IOMAP = (1 << 2),
464 VPD = (1 << 1),
5d06a99f
FR		 465 PMEnable = (1 << 0), /* Power Management Enable */
466
6dccd16b 467 /* Config2 register p. 25 */
57538c4a 468 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 469 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 470 PCI_Clock_66MHz = 0x01,
471 PCI_Clock_33MHz = 0x00,
472
61a4dcc2
FR		 473 /* Config3 register p.25 */
474 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
475 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 476 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
b51ecea8 477 Rdy_to_L23 = (1 << 1), /* L23 Enable */
f162a5d1 478 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 479
d58d46b5
FR		 480 /* Config4 register */
481 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
482
5d06a99f 483 /* Config5 register p.27 */
61a4dcc2
FR		 484 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
485 MWF = (1 << 5), /* Accept Multicast wakeup frame */
486 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 487 Spi_en = (1 << 3),
61a4dcc2 488 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 489 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
57538c4a 490 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 491
1da177e4 492 /* CPlusCmd p.31 */
f162a5d1
FR		 493 EnableBist = (1 << 15), // 8168 8101
494 Mac_dbgo_oe = (1 << 14), // 8168 8101
495 Normal_mode = (1 << 13), // unused
496 Force_half_dup = (1 << 12), // 8168 8101
497 Force_rxflow_en = (1 << 11), // 8168 8101
498 Force_txflow_en = (1 << 10), // 8168 8101
499 Cxpl_dbg_sel = (1 << 9), // 8168 8101
500 ASF = (1 << 8), // 8168 8101
501 PktCntrDisable = (1 << 7), // 8168 8101
502 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 503 RxVlan = (1 << 6),
504 RxChkSum = (1 << 5),
505 PCIDAC = (1 << 4),
506 PCIMulRW = (1 << 3),
9a3c81fa 507#define INTT_MASK GENMASK(1, 0)
bc73241e 508#define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
1da177e4
LT		 509
510 /* rtl8169_PHYstatus */
07d3f51f
FR		 511 TBI_Enable = 0x80,
512 TxFlowCtrl = 0x40,
513 RxFlowCtrl = 0x20,
514 _1000bpsF = 0x10,
515 _100bps = 0x08,
516 _10bps = 0x04,
517 LinkStatus = 0x02,
518 FullDup = 0x01,
1da177e4 519
6e85d5ad
CV		 520 /* ResetCounterCommand */
521 CounterReset = 0x1,
522
d4a3a0fc 523 /* DumpCounterCommand */
07d3f51f 524 CounterDump = 0x8,
6e1d0b89
CHL		 525
526 /* magic enable v2 */
527 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
1da177e4
LT		 528};
529
2b7b4318
FR		 530enum rtl_desc_bit {
531 /* First doubleword. */
1da177e4
LT		 532 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
533 RingEnd = (1 << 30), /* End of descriptor ring */
534 FirstFrag = (1 << 29), /* First segment of a packet */
535 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 536};
537
538/* Generic case. */
539enum rtl_tx_desc_bit {
540 /* First doubleword. */
541 TD_LSO = (1 << 27), /* Large Send Offload */
542#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 543
2b7b4318
FR		 544 /* Second doubleword. */
545 TxVlanTag = (1 << 17), /* Add VLAN tag */
546};
547
548/* 8169, 8168b and 810x except 8102e. */
549enum rtl_tx_desc_bit_0 {
550 /* First doubleword. */
551#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
552 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
553 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
554 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
555};
556
557/* 8102e, 8168c and beyond. */
558enum rtl_tx_desc_bit_1 {
bdfa4ed6 559 /* First doubleword. */
560 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
e974604b 561 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
bdfa4ed6 562#define GTTCPHO_SHIFT 18
e64e0c89 563#define GTTCPHO_MAX 0x7f
bdfa4ed6 564
2b7b4318 565 /* Second doubleword. */
e974604b 566#define TCPHO_SHIFT 18
e64e0c89 567#define TCPHO_MAX 0x3ff
2b7b4318 568#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
e974604b 569 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
570 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
2b7b4318
FR		 571 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
572 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
573};
1da177e4 574
2b7b4318 575enum rtl_rx_desc_bit {
1da177e4
LT		 576 /* Rx private */
577 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
9b60047a 578 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
1da177e4
LT		 579
580#define RxProtoUDP (PID1)
581#define RxProtoTCP (PID0)
582#define RxProtoIP (PID1 | PID0)
583#define RxProtoMask RxProtoIP
584
585 IPFail = (1 << 16), /* IP checksum failed */
586 UDPFail = (1 << 15), /* UDP/IP checksum failed */
587 TCPFail = (1 << 14), /* TCP/IP checksum failed */
588 RxVlanTag = (1 << 16), /* VLAN tag available */
589};
590
591#define RsvdMask 0x3fffc000
592
0170d594
HK		 593#define RTL_GSO_MAX_SIZE_V1 32000
594#define RTL_GSO_MAX_SEGS_V1 24
595#define RTL_GSO_MAX_SIZE_V2 64000
596#define RTL_GSO_MAX_SEGS_V2 64
597
1da177e4 598struct TxDesc {
6cccd6e7
REB		 599 __le32 opts1;
600 __le32 opts2;
601 __le64 addr;
1da177e4
LT		 602};
603
604struct RxDesc {
6cccd6e7
REB		 605 __le32 opts1;
606 __le32 opts2;
607 __le64 addr;
1da177e4
LT		 608};
609
610struct ring_info {
611 struct sk_buff *skb;
612 u32 len;
1da177e4
LT		 613};
614
355423d0
IV		 615struct rtl8169_counters {
616 __le64 tx_packets;
617 __le64 rx_packets;
618 __le64 tx_errors;
619 __le32 rx_errors;
620 __le16 rx_missed;
621 __le16 align_errors;
622 __le32 tx_one_collision;
623 __le32 tx_multi_collision;
624 __le64 rx_unicast;
625 __le64 rx_broadcast;
626 __le32 rx_multicast;
627 __le16 tx_aborted;
628 __le16 tx_underun;
629};
630
6e85d5ad
CV		 631struct rtl8169_tc_offsets {
632 bool inited;
633 __le64 tx_errors;
634 __le32 tx_multi_collision;
6e85d5ad
CV		 635 __le16 tx_aborted;
636};
637
da78dbff 638enum rtl_flag {
6ad56901 639 RTL_FLAG_TASK_ENABLED = 0,
da78dbff 640 RTL_FLAG_TASK_RESET_PENDING,
da78dbff
FR		 641 RTL_FLAG_MAX
642};
643
8027aa24
JW		 644struct rtl8169_stats {
645 u64 packets;
646 u64 bytes;
647 struct u64_stats_sync syncp;
648};
649
1da177e4
LT		 650struct rtl8169_private {
651 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 652 struct pci_dev *pci_dev;
c4028958 653 struct net_device *dev;
703732f0 654 struct phy_device *phydev;
bea3348e 655 struct napi_struct napi;
b57b7e5a 656 u32 msg_enable;
76719ee2 657 enum mac_version mac_version;
1da177e4
LT		 658 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
659 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 660 u32 dirty_tx;
8027aa24
JW		 661 struct rtl8169_stats rx_stats;
662 struct rtl8169_stats tx_stats;
1da177e4
LT		 663 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
664 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
665 dma_addr_t TxPhyAddr;
666 dma_addr_t RxPhyAddr;
32879f00 667 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 668 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4 669 u16 cp_cmd;
c1d532d2 670 u32 irq_mask;
c2f6f3ee 671 struct clk *clk;
c0e45c1c 672
4422bcd4 673 struct {
da78dbff
FR		 674 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
675 struct mutex mutex;
4422bcd4
FR		 676 struct work_struct work;
677 } wk;
678
c8248c6c 679 unsigned irq_enabled:1;
f7ffa9ae 680 unsigned supports_gmii:1;
62b1b3b3 681 unsigned aspm_manageable:1;
42020320
CV		 682 dma_addr_t counters_phys_addr;
683 struct rtl8169_counters *counters;
6e85d5ad 684 struct rtl8169_tc_offsets tc_offset;
e1759441 685 u32 saved_wolopts;
7ec3f872 686 int eee_adv;
f1e02ed1 687
254764e5 688 const char *fw_name;
8197f9d2 689 struct rtl_fw *rtl_fw;
c558386b
HW		 690
691 u32 ocp_base;
1da177e4
LT		 692};
693
1fcd1658
HK		 694typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
695
979b6c13 696MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 697MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
b57b7e5a
SH		 698module_param_named(debug, debug.msg_enable, int, 0);
699MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
11287b69 700MODULE_SOFTDEP("pre: realtek");
1da177e4 701MODULE_LICENSE("GPL");
bca03d5f 702MODULE_FIRMWARE(FIRMWARE_8168D_1);
703MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 704MODULE_FIRMWARE(FIRMWARE_8168E_1);
705MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 706MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 707MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 708MODULE_FIRMWARE(FIRMWARE_8168F_1);
709MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 710MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 711MODULE_FIRMWARE(FIRMWARE_8411_1);
45dd95c4 712MODULE_FIRMWARE(FIRMWARE_8411_2);
5598bfe5 713MODULE_FIRMWARE(FIRMWARE_8106E_1);
58152cd4 714MODULE_FIRMWARE(FIRMWARE_8106E_2);
beb330a4 715MODULE_FIRMWARE(FIRMWARE_8168G_2);
57538c4a 716MODULE_FIRMWARE(FIRMWARE_8168G_3);
6e1d0b89
CHL		 717MODULE_FIRMWARE(FIRMWARE_8168H_1);
718MODULE_FIRMWARE(FIRMWARE_8168H_2);
229c1e0d 719MODULE_FIRMWARE(FIRMWARE_8168FP_3);
a3bf5c42
FR		 720MODULE_FIRMWARE(FIRMWARE_8107E_1);
721MODULE_FIRMWARE(FIRMWARE_8107E_2);
02bf642b 722MODULE_FIRMWARE(FIRMWARE_8125A_3);
1da177e4 723
1e1205b7
HK		 724static inline struct device *tp_to_dev(struct rtl8169_private *tp)
725{
726 return &tp->pci_dev->dev;
727}
728
da78dbff
FR		 729static void rtl_lock_work(struct rtl8169_private *tp)
730{
731 mutex_lock(&tp->wk.mutex);
732}
733
734static void rtl_unlock_work(struct rtl8169_private *tp)
735{
736 mutex_unlock(&tp->wk.mutex);
737}
738
df320ed7
HK		 739static void rtl_lock_config_regs(struct rtl8169_private *tp)
740{
741 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
742}
743
744static void rtl_unlock_config_regs(struct rtl8169_private *tp)
745{
746 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
747}
748
f1bce4ad
HK		 749static bool rtl_is_8125(struct rtl8169_private *tp)
750{
751 return tp->mac_version >= RTL_GIGA_MAC_VER_60;
752}
753
9e9f33ba
HK		 754static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
755{
756 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
c623305b 757 tp->mac_version != RTL_GIGA_MAC_VER_39 &&
1287723a 758 tp->mac_version <= RTL_GIGA_MAC_VER_52;
9e9f33ba
HK		 759}
760
2e779ddb
HK		 761static bool rtl_supports_eee(struct rtl8169_private *tp)
762{
763 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
764 tp->mac_version != RTL_GIGA_MAC_VER_37 &&
765 tp->mac_version != RTL_GIGA_MAC_VER_39;
766}
767
ce37115e
HK		 768static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
769{
770 int i;
771
772 for (i = 0; i < ETH_ALEN; i++)
773 mac[i] = RTL_R8(tp, reg + i);
774}
775
ffc46952
FR		 776struct rtl_cond {
777 bool (*check)(struct rtl8169_private *);
778 const char *msg;
779};
780
781static void rtl_udelay(unsigned int d)
782{
783 udelay(d);
784}
785
786static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
787 void (*delay)(unsigned int), unsigned int d, int n,
788 bool high)
789{
790 int i;
791
792 for (i = 0; i < n; i++) {
ffc46952
FR		 793 if (c->check(tp) == high)
794 return true;
d1f5050b 795 delay(d);
ffc46952 796 }
82e316ef
FR		 797 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
798 c->msg, !high, n, d);
ffc46952
FR		 799 return false;
800}
801
802static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
803 const struct rtl_cond *c,
804 unsigned int d, int n)
805{
806 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
807}
808
809static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
810 const struct rtl_cond *c,
811 unsigned int d, int n)
812{
813 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
814}
815
816static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
817 const struct rtl_cond *c,
818 unsigned int d, int n)
819{
820 return rtl_loop_wait(tp, c, msleep, d, n, true);
821}
822
823static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
824 const struct rtl_cond *c,
825 unsigned int d, int n)
826{
827 return rtl_loop_wait(tp, c, msleep, d, n, false);
828}
829
830#define DECLARE_RTL_COND(name) \
831static bool name ## _check(struct rtl8169_private *); \
832 \
833static const struct rtl_cond name = { \
834 .check = name ## _check, \
835 .msg = #name \
836}; \
837 \
838static bool name ## _check(struct rtl8169_private *tp)
839
c558386b
HW		 840static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
841{
842 if (reg & 0xffff0001) {
843 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
844 return true;
845 }
846 return false;
847}
848
849DECLARE_RTL_COND(rtl_ocp_gphy_cond)
850{
1ef7286e 851 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
c558386b
HW		 852}
853
854static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
855{
c558386b
HW		 856 if (rtl_ocp_reg_failure(tp, reg))
857 return;
858
1ef7286e 859 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 860
861 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
862}
863
9b994b4a 864static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
c558386b 865{
c558386b
HW		 866 if (rtl_ocp_reg_failure(tp, reg))
867 return 0;
868
1ef7286e 869 RTL_W32(tp, GPHY_OCP, reg << 15);
c558386b
HW		 870
871 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
9b994b4a 872 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
c558386b
HW		 873}
874
c558386b
HW		 875static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
876{
c558386b
HW		 877 if (rtl_ocp_reg_failure(tp, reg))
878 return;
879
1ef7286e 880 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 881}
882
883static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
884{
c558386b
HW		 885 if (rtl_ocp_reg_failure(tp, reg))
886 return 0;
887
1ef7286e 888 RTL_W32(tp, OCPDR, reg << 15);
c558386b 889
1ef7286e 890 return RTL_R32(tp, OCPDR);
c558386b
HW		 891}
892
ef712ede
HK		 893static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
894 u16 set)
895{
896 u16 data = r8168_mac_ocp_read(tp, reg);
897
898 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
899}
900
c558386b
HW		 901#define OCP_STD_PHY_BASE 0xa400
902
903static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
904{
905 if (reg == 0x1f) {
906 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
907 return;
908 }
909
910 if (tp->ocp_base != OCP_STD_PHY_BASE)
911 reg -= 0x10;
912
913 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
914}
915
916static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
917{
9c6850fe
HK		 918 if (reg == 0x1f)
919 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
920
c558386b
HW		 921 if (tp->ocp_base != OCP_STD_PHY_BASE)
922 reg -= 0x10;
923
924 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
925}
926
eee3786f 927static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
928{
929 if (reg == 0x1f) {
930 tp->ocp_base = value << 4;
931 return;
932 }
933
934 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
935}
936
937static int mac_mcu_read(struct rtl8169_private *tp, int reg)
938{
939 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
940}
941
ffc46952
FR		 942DECLARE_RTL_COND(rtl_phyar_cond)
943{
1ef7286e 944 return RTL_R32(tp, PHYAR) & 0x80000000;
ffc46952
FR		 945}
946
24192210 947static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 948{
1ef7286e 949 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 950
ffc46952 951 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 952 /*
81a95f04
TT		 953 * According to hardware specs a 20us delay is required after write
954 * complete indication, but before sending next command.
024a07ba 955 */
81a95f04 956 udelay(20);
1da177e4
LT		 957}
958
24192210 959static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 960{
ffc46952 961 int value;
1da177e4 962
1ef7286e 963 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 964
ffc46952 965 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
9b994b4a 966 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
ffc46952 967
81a95f04
TT		 968 /*
969 * According to hardware specs a 20us delay is required after read
970 * complete indication, but before sending next command.
971 */
972 udelay(20);
973
1da177e4
LT		 974 return value;
975}
976
935e2218
CHL		 977DECLARE_RTL_COND(rtl_ocpar_cond)
978{
1ef7286e 979 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
935e2218
CHL		 980}
981
24192210 982static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 983{
1ef7286e
AS		 984 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
985 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
986 RTL_W32(tp, EPHY_RXER_NUM, 0);
c0e45c1c 987
ffc46952 988 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 989}
990
24192210 991static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 992{
24192210
FR		 993 r8168dp_1_mdio_access(tp, reg,
994 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 995}
996
24192210 997static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 998{
24192210 999 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1000
1001 mdelay(1);
1ef7286e
AS		 1002 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1003 RTL_W32(tp, EPHY_RXER_NUM, 0);
c0e45c1c 1004
ffc46952 1005 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
9b994b4a 1006 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
c0e45c1c 1007}
1008
e6de30d6 1009#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1010
1ef7286e 1011static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
e6de30d6 1012{
1ef7286e 1013 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 1014}
1015
1ef7286e 1016static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
e6de30d6 1017{
1ef7286e 1018 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 1019}
1020
24192210 1021static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1022{
1ef7286e 1023 r8168dp_2_mdio_start(tp);
e6de30d6 1024
24192210 1025 r8169_mdio_write(tp, reg, value);
e6de30d6 1026
1ef7286e 1027 r8168dp_2_mdio_stop(tp);
e6de30d6 1028}
1029
24192210 1030static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1031{
1032 int value;
1033
62bdc8fd
HK		 1034 /* Work around issue with chip reporting wrong PHY ID */
1035 if (reg == MII_PHYSID2)
1036 return 0xc912;
1037
1ef7286e 1038 r8168dp_2_mdio_start(tp);
e6de30d6 1039
24192210 1040 value = r8169_mdio_read(tp, reg);
e6de30d6 1041
1ef7286e 1042 r8168dp_2_mdio_stop(tp);
e6de30d6 1043
1044 return value;
1045}
1046
ce8843ab 1047static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
dacf8154 1048{
5f950523
HK		 1049 switch (tp->mac_version) {
1050 case RTL_GIGA_MAC_VER_27:
1051 r8168dp_1_mdio_write(tp, location, val);
1052 break;
1053 case RTL_GIGA_MAC_VER_28:
1054 case RTL_GIGA_MAC_VER_31:
1055 r8168dp_2_mdio_write(tp, location, val);
1056 break;
f1bce4ad 1057 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61:
5f950523
HK		 1058 r8168g_mdio_write(tp, location, val);
1059 break;
1060 default:
1061 r8169_mdio_write(tp, location, val);
1062 break;
1063 }
dacf8154
FR		 1064}
1065
4da19633 1066static int rtl_readphy(struct rtl8169_private *tp, int location)
1067{
5f950523
HK		 1068 switch (tp->mac_version) {
1069 case RTL_GIGA_MAC_VER_27:
1070 return r8168dp_1_mdio_read(tp, location);
1071 case RTL_GIGA_MAC_VER_28:
1072 case RTL_GIGA_MAC_VER_31:
1073 return r8168dp_2_mdio_read(tp, location);
f1bce4ad 1074 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61:
5f950523
HK		 1075 return r8168g_mdio_read(tp, location);
1076 default:
1077 return r8169_mdio_read(tp, location);
1078 }
4da19633 1079}
1080
1081static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1082{
1083 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1084}
1085
76564428 1086static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1087{
1088 int val;
1089
4da19633 1090 val = rtl_readphy(tp, reg_addr);
76564428 1091 rtl_writephy(tp, reg_addr, (val & ~m) | p);
daf9df6d 1092}
1093
0721914a
HK		 1094static void r8168d_modify_extpage(struct phy_device *phydev, int extpage,
1095 int reg, u16 mask, u16 val)
1096{
1097 int oldpage = phy_select_page(phydev, 0x0007);
1098
1099 __phy_write(phydev, 0x1e, extpage);
1100 __phy_modify(phydev, reg, mask, val);
1101
1102 phy_restore_page(phydev, oldpage, 0);
1103}
1104
b5e189b4
HK		 1105static void r8168d_phy_param(struct phy_device *phydev, u16 parm,
1106 u16 mask, u16 val)
1107{
1108 int oldpage = phy_select_page(phydev, 0x0005);
1109
1110 __phy_write(phydev, 0x05, parm);
1111 __phy_modify(phydev, 0x06, mask, val);
1112
1113 phy_restore_page(phydev, oldpage, 0);
1114}
1115
8bfdce1d
HK		 1116static void r8168g_phy_param(struct phy_device *phydev, u16 parm,
1117 u16 mask, u16 val)
1118{
1119 int oldpage = phy_select_page(phydev, 0x0a43);
1120
1121 __phy_write(phydev, 0x13, parm);
1122 __phy_modify(phydev, 0x14, mask, val);
1123
1124 phy_restore_page(phydev, oldpage, 0);
1125}
1126
ffc46952
FR		 1127DECLARE_RTL_COND(rtl_ephyar_cond)
1128{
1ef7286e 1129 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
ffc46952
FR		 1130}
1131
fdf6fc06 1132static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1133{
1ef7286e 1134 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
dacf8154
FR		 1135 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1136
ffc46952
FR		 1137 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1138
1139 udelay(10);
dacf8154
FR		 1140}
1141
fdf6fc06 1142static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1143{
1ef7286e 1144 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
dacf8154 1145
ffc46952 1146 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1ef7286e 1147 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1148}
1149
935e2218
CHL		 1150DECLARE_RTL_COND(rtl_eriar_cond)
1151{
1ef7286e 1152 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
935e2218
CHL		 1153}
1154
724c6fd0
HK		 1155static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1156 u32 val, int type)
133ac40a 1157{
133ac40a 1158 BUG_ON((addr & 3) || (mask == 0));
1ef7286e
AS		 1159 RTL_W32(tp, ERIDR, val);
1160 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
133ac40a 1161
ffc46952 1162 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1163}
1164
724c6fd0
HK		 1165static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1166 u32 val)
1167{
1168 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1169}
1170
1171static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1172{
1ef7286e 1173 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
133ac40a 1174
ffc46952 1175 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1ef7286e 1176 RTL_R32(tp, ERIDR) : ~0;
133ac40a
HW		 1177}
1178
724c6fd0
HK		 1179static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1180{
1181 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1182}
1183
706123d0 1184static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
724c6fd0 1185 u32 m)
133ac40a
HW		 1186{
1187 u32 val;
1188
724c6fd0
HK		 1189 val = rtl_eri_read(tp, addr);
1190 rtl_eri_write(tp, addr, mask, (val & ~m) | p);
133ac40a
HW		 1191}
1192
e719b3ea
HK		 1193static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1194 u32 p)
1195{
1196 rtl_w0w1_eri(tp, addr, mask, p, 0);
1197}
1198
1199static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1200 u32 m)
1201{
1202 rtl_w0w1_eri(tp, addr, mask, 0, m);
1203}
1204
935e2218
CHL		 1205static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1206{
1ef7286e 1207 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
935e2218 1208 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1ef7286e 1209 RTL_R32(tp, OCPDR) : ~0;
935e2218
CHL		 1210}
1211
1212static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1213{
724c6fd0 1214 return _rtl_eri_read(tp, reg, ERIAR_OOB);
935e2218
CHL		 1215}
1216
935e2218
CHL		 1217static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1218 u32 data)
1219{
1ef7286e
AS		 1220 RTL_W32(tp, OCPDR, data);
1221 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
935e2218
CHL		 1222 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1223}
1224
1225static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1226 u32 data)
1227{
724c6fd0
HK		 1228 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1229 data, ERIAR_OOB);
935e2218
CHL		 1230}
1231
3c72bf71 1232static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
2a9b4d96 1233{
724c6fd0 1234 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
2a9b4d96 1235
3c72bf71 1236 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
2a9b4d96
CHL		 1237}
1238
1239#define OOB_CMD_RESET 0x00
1240#define OOB_CMD_DRIVER_START 0x05
1241#define OOB_CMD_DRIVER_STOP 0x06
1242
1243static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1244{
1245 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1246}
1247
3c72bf71 1248DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
2a9b4d96
CHL		 1249{
1250 u16 reg;
1251
1252 reg = rtl8168_get_ocp_reg(tp);
1253
3c72bf71 1254 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
2a9b4d96
CHL		 1255}
1256
935e2218 1257DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
2a9b4d96 1258{
3c72bf71 1259 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
935e2218
CHL		 1260}
1261
1262DECLARE_RTL_COND(rtl_ocp_tx_cond)
1263{
1ef7286e 1264 return RTL_R8(tp, IBISR0) & 0x20;
935e2218 1265}
2a9b4d96 1266
003609da
CHL		 1267static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1268{
1ef7286e 1269 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
086ca23d 1270 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1ef7286e
AS		 1271 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1272 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
003609da
CHL		 1273}
1274
935e2218
CHL		 1275static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1276{
3c72bf71
HK		 1277 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1278 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
2a9b4d96
CHL		 1279}
1280
935e2218 1281static void rtl8168ep_driver_start(struct rtl8169_private *tp)
2a9b4d96 1282{
3c72bf71
HK		 1283 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1284 r8168ep_ocp_write(tp, 0x01, 0x30,
1285 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
935e2218
CHL		 1286 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1287}
1288
1289static void rtl8168_driver_start(struct rtl8169_private *tp)
1290{
1291 switch (tp->mac_version) {
1292 case RTL_GIGA_MAC_VER_27:
1293 case RTL_GIGA_MAC_VER_28:
1294 case RTL_GIGA_MAC_VER_31:
1295 rtl8168dp_driver_start(tp);
1296 break;
1287723a 1297 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
935e2218
CHL		 1298 rtl8168ep_driver_start(tp);
1299 break;
1300 default:
1301 BUG();
1302 break;
1303 }
1304}
2a9b4d96 1305
935e2218
CHL		 1306static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1307{
3c72bf71
HK		 1308 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1309 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
2a9b4d96
CHL		 1310}
1311
935e2218
CHL		 1312static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1313{
003609da 1314 rtl8168ep_stop_cmac(tp);
3c72bf71
HK		 1315 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1316 r8168ep_ocp_write(tp, 0x01, 0x30,
1317 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
935e2218
CHL		 1318 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1319}
1320
1321static void rtl8168_driver_stop(struct rtl8169_private *tp)
1322{
1323 switch (tp->mac_version) {
1324 case RTL_GIGA_MAC_VER_27:
1325 case RTL_GIGA_MAC_VER_28:
1326 case RTL_GIGA_MAC_VER_31:
1327 rtl8168dp_driver_stop(tp);
1328 break;
1287723a 1329 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
935e2218
CHL		 1330 rtl8168ep_driver_stop(tp);
1331 break;
1332 default:
1333 BUG();
1334 break;
1335 }
1336}
1337
9dbe7896 1338static bool r8168dp_check_dash(struct rtl8169_private *tp)
2a9b4d96
CHL		 1339{
1340 u16 reg = rtl8168_get_ocp_reg(tp);
1341
3c72bf71 1342 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
2a9b4d96
CHL		 1343}
1344
9dbe7896 1345static bool r8168ep_check_dash(struct rtl8169_private *tp)
935e2218 1346{
3c72bf71 1347 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
935e2218
CHL		 1348}
1349
9dbe7896 1350static bool r8168_check_dash(struct rtl8169_private *tp)
935e2218
CHL		 1351{
1352 switch (tp->mac_version) {
1353 case RTL_GIGA_MAC_VER_27:
1354 case RTL_GIGA_MAC_VER_28:
1355 case RTL_GIGA_MAC_VER_31:
1356 return r8168dp_check_dash(tp);
1287723a 1357 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
935e2218
CHL		 1358 return r8168ep_check_dash(tp);
1359 default:
9dbe7896 1360 return false;
935e2218
CHL		 1361 }
1362}
1363
4e7e4621
HK		 1364static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1365{
1366 rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1367 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1368}
1369
ffc46952
FR		 1370DECLARE_RTL_COND(rtl_efusear_cond)
1371{
1ef7286e 1372 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
ffc46952
FR		 1373}
1374
fdf6fc06 1375static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1376{
1ef7286e 1377 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
daf9df6d 1378
ffc46952 1379 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1ef7286e 1380 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1381}
1382
c1d532d2
HK		 1383static u32 rtl_get_events(struct rtl8169_private *tp)
1384{
f1bce4ad
HK		 1385 if (rtl_is_8125(tp))
1386 return RTL_R32(tp, IntrStatus_8125);
1387 else
1388 return RTL_R16(tp, IntrStatus);
c1d532d2
HK		 1389}
1390
1391static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
9085cdfa 1392{
f1bce4ad
HK		 1393 if (rtl_is_8125(tp))
1394 RTL_W32(tp, IntrStatus_8125, bits);
1395 else
1396 RTL_W16(tp, IntrStatus, bits);
9085cdfa
FR		 1397}
1398
1399static void rtl_irq_disable(struct rtl8169_private *tp)
1400{
f1bce4ad
HK		 1401 if (rtl_is_8125(tp))
1402 RTL_W32(tp, IntrMask_8125, 0);
1403 else
1404 RTL_W16(tp, IntrMask, 0);
c8248c6c 1405 tp->irq_enabled = 0;
3e990ff5
FR		 1406}
1407
da78dbff
FR		 1408#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1409#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1410#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1411
fe716f8a 1412static void rtl_irq_enable(struct rtl8169_private *tp)
da78dbff 1413{
c8248c6c 1414 tp->irq_enabled = 1;
f1bce4ad
HK		 1415 if (rtl_is_8125(tp))
1416 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1417 else
1418 RTL_W16(tp, IntrMask, tp->irq_mask);
da78dbff
FR		 1419}
1420
811fd301 1421static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1422{
9085cdfa 1423 rtl_irq_disable(tp);
c1d532d2 1424 rtl_ack_events(tp, 0xffffffff);
de20e12f 1425 /* PCI commit */
1ef7286e 1426 RTL_R8(tp, ChipCmd);
1da177e4
LT		 1427}
1428
70090424
HW		 1429static void rtl_link_chg_patch(struct rtl8169_private *tp)
1430{
70090424 1431 struct net_device *dev = tp->dev;
703732f0 1432 struct phy_device *phydev = tp->phydev;
70090424
HW		 1433
1434 if (!netif_running(dev))
1435 return;
1436
b3d7b2f2
HW		 1437 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1438 tp->mac_version == RTL_GIGA_MAC_VER_38) {
29a12b49 1439 if (phydev->speed == SPEED_1000) {
724c6fd0
HK		 1440 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1441 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
29a12b49 1442 } else if (phydev->speed == SPEED_100) {
724c6fd0
HK		 1443 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1444 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
70090424 1445 } else {
724c6fd0
HK		 1446 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1447 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
70090424 1448 }
4e7e4621 1449 rtl_reset_packet_filter(tp);
c2218925
HW		 1450 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1451 tp->mac_version == RTL_GIGA_MAC_VER_36) {
29a12b49 1452 if (phydev->speed == SPEED_1000) {
724c6fd0
HK		 1453 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1454 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
c2218925 1455 } else {
724c6fd0
HK		 1456 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1457 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
c2218925 1458 }
7e18dca1 1459 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
29a12b49 1460 if (phydev->speed == SPEED_10) {
724c6fd0
HK		 1461 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1462 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
7e18dca1 1463 } else {
724c6fd0 1464 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
7e18dca1 1465 }
70090424
HW		 1466 }
1467}
1468
e1759441
RW		 1469#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1470
e1759441 1471static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1472{
1473 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1474
da78dbff 1475 rtl_lock_work(tp);
e1759441 1476 wol->supported = WAKE_ANY;
433f9d0d 1477 wol->wolopts = tp->saved_wolopts;
da78dbff 1478 rtl_unlock_work(tp);
e1759441
RW		 1479}
1480
1481static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1482{
350f7596 1483 static const struct {
61a4dcc2
FR		 1484 u32 opt;
1485 u16 reg;
1486 u8 mask;
1487 } cfg[] = {
61a4dcc2 1488 { WAKE_PHY, Config3, LinkUp },
61a4dcc2
FR		 1489 { WAKE_UCAST, Config5, UWF },
1490 { WAKE_BCAST, Config5, BWF },
1491 { WAKE_MCAST, Config5, MWF },
6e1d0b89
CHL		 1492 { WAKE_ANY, Config5, LanWake },
1493 { WAKE_MAGIC, Config3, MagicPacket }
61a4dcc2 1494 };
f1bce4ad 1495 unsigned int i, tmp = ARRAY_SIZE(cfg);
851e6022 1496 u8 options;
61a4dcc2 1497
df320ed7 1498 rtl_unlock_config_regs(tp);
61a4dcc2 1499
9e9f33ba 1500 if (rtl_is_8168evl_up(tp)) {
f1bce4ad 1501 tmp--;
6e1d0b89 1502 if (wolopts & WAKE_MAGIC)
e719b3ea
HK		 1503 rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1504 MagicPacket_v2);
6e1d0b89 1505 else
e719b3ea
HK		 1506 rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1507 MagicPacket_v2);
f1bce4ad
HK		 1508 } else if (rtl_is_8125(tp)) {
1509 tmp--;
1510 if (wolopts & WAKE_MAGIC)
1511 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1512 else
1513 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
6e1d0b89
CHL		 1514 }
1515
1516 for (i = 0; i < tmp; i++) {
1ef7286e 1517 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
e1759441 1518 if (wolopts & cfg[i].opt)
61a4dcc2 1519 options |= cfg[i].mask;
1ef7286e 1520 RTL_W8(tp, cfg[i].reg, options);
61a4dcc2
FR		 1521 }
1522
851e6022 1523 switch (tp->mac_version) {
edcde3ee 1524 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1ef7286e 1525 options = RTL_R8(tp, Config1) & ~PMEnable;
851e6022
FR		 1526 if (wolopts)
1527 options |= PMEnable;
1ef7286e 1528 RTL_W8(tp, Config1, options);
851e6022 1529 break;
edcde3ee
HK		 1530 case RTL_GIGA_MAC_VER_34:
1531 case RTL_GIGA_MAC_VER_37:
1287723a 1532 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_52:
1ef7286e 1533 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
d387b427
FR		 1534 if (wolopts)
1535 options |= PME_SIGNAL;
1ef7286e 1536 RTL_W8(tp, Config2, options);
851e6022 1537 break;
edcde3ee
HK		 1538 default:
1539 break;
851e6022
FR		 1540 }
1541
df320ed7 1542 rtl_lock_config_regs(tp);
3bd82645
HK		 1543
1544 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
398fd408 1545 tp->dev->wol_enabled = wolopts ? 1 : 0;
e1759441
RW		 1546}
1547
1548static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1549{
1550 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 1551 struct device *d = tp_to_dev(tp);
5fa80a32 1552
2f533f6b
HK		 1553 if (wol->wolopts & ~WAKE_ANY)
1554 return -EINVAL;
1555
5fa80a32 1556 pm_runtime_get_noresume(d);
e1759441 1557
da78dbff 1558 rtl_lock_work(tp);
61a4dcc2 1559
2f533f6b 1560 tp->saved_wolopts = wol->wolopts;
433f9d0d 1561
5fa80a32 1562 if (pm_runtime_active(d))
433f9d0d 1563 __rtl8169_set_wol(tp, tp->saved_wolopts);
da78dbff
FR		 1564
1565 rtl_unlock_work(tp);
61a4dcc2 1566
5fa80a32
CHL		 1567 pm_runtime_put_noidle(d);
1568
61a4dcc2
FR		 1569 return 0;
1570}
1571
1da177e4
LT		 1572static void rtl8169_get_drvinfo(struct net_device *dev,
1573 struct ethtool_drvinfo *info)
1574{
1575 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1576 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1577
68aad78c 1578 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
68aad78c 1579 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1580 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
254764e5 1581 if (rtl_fw)
8ac72d16
RJ		 1582 strlcpy(info->fw_version, rtl_fw->version,
1583 sizeof(info->fw_version));
1da177e4
LT		 1584}
1585
1586static int rtl8169_get_regs_len(struct net_device *dev)
1587{
1588 return R8169_REGS_SIZE;
1589}
1590
c8f44aff
MM		 1591static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1592 netdev_features_t features)
1da177e4 1593{
d58d46b5
FR		 1594 struct rtl8169_private *tp = netdev_priv(dev);
1595
2b7b4318 1596 if (dev->mtu > TD_MSS_MAX)
350fb32a 1597 features &= ~NETIF_F_ALL_TSO;
1da177e4 1598
d58d46b5 1599 if (dev->mtu > JUMBO_1K &&
6ed0e08f 1600 tp->mac_version > RTL_GIGA_MAC_VER_06)
7cb83b21 1601 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
d58d46b5 1602
350fb32a 1603 return features;
1da177e4
LT		 1604}
1605
a3984578
HK		 1606static int rtl8169_set_features(struct net_device *dev,
1607 netdev_features_t features)
1da177e4
LT		 1608{
1609 struct rtl8169_private *tp = netdev_priv(dev);
929a031d 1610 u32 rx_config;
1da177e4 1611
a3984578
HK		 1612 rtl_lock_work(tp);
1613
1ef7286e 1614 rx_config = RTL_R32(tp, RxConfig);
929a031d 1615 if (features & NETIF_F_RXALL)
1616 rx_config |= (AcceptErr | AcceptRunt);
1617 else
1618 rx_config &= ~(AcceptErr | AcceptRunt);
1da177e4 1619
f1bce4ad
HK		 1620 if (rtl_is_8125(tp)) {
1621 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1622 rx_config |= RX_VLAN_8125;
1623 else
1624 rx_config &= ~RX_VLAN_8125;
1625 }
1626
1ef7286e 1627 RTL_W32(tp, RxConfig, rx_config);
350fb32a 1628
929a031d 1629 if (features & NETIF_F_RXCSUM)
1630 tp->cp_cmd |= RxChkSum;
1631 else
1632 tp->cp_cmd &= ~RxChkSum;
6bbe021d 1633
f1bce4ad
HK		 1634 if (!rtl_is_8125(tp)) {
1635 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1636 tp->cp_cmd |= RxVlan;
1637 else
1638 tp->cp_cmd &= ~RxVlan;
1639 }
929a031d 1640
1ef7286e
AS		 1641 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1642 RTL_R16(tp, CPlusCmd);
1da177e4 1643
da78dbff 1644 rtl_unlock_work(tp);
1da177e4
LT		 1645
1646 return 0;
1647}
1648
810f4893 1649static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 1650{
df8a39de 1651 return (skb_vlan_tag_present(skb)) ?
7424edbb 1652 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1da177e4
LT		 1653}
1654
7a8fc77b 1655static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1656{
1657 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1658
7a8fc77b 1659 if (opts2 & RxVlanTag)
7424edbb 1660 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1da177e4
LT		 1661}
1662
1da177e4
LT		 1663static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1664 void *p)
1665{
5b0384f4 1666 struct rtl8169_private *tp = netdev_priv(dev);
15edae91
PW		 1667 u32 __iomem *data = tp->mmio_addr;
1668 u32 *dw = p;
1669 int i;
1da177e4 1670
da78dbff 1671 rtl_lock_work(tp);
15edae91
PW		 1672 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1673 memcpy_fromio(dw++, data++, 4);
da78dbff 1674 rtl_unlock_work(tp);
1da177e4
LT		 1675}
1676
b57b7e5a
SH		 1677static u32 rtl8169_get_msglevel(struct net_device *dev)
1678{
1679 struct rtl8169_private *tp = netdev_priv(dev);
1680
1681 return tp->msg_enable;
1682}
1683
1684static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1685{
1686 struct rtl8169_private *tp = netdev_priv(dev);
1687
1688 tp->msg_enable = value;
1689}
1690
d4a3a0fc
SH		 1691static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1692 "tx_packets",
1693 "rx_packets",
1694 "tx_errors",
1695 "rx_errors",
1696 "rx_missed",
1697 "align_errors",
1698 "tx_single_collisions",
1699 "tx_multi_collisions",
1700 "unicast",
1701 "broadcast",
1702 "multicast",
1703 "tx_aborted",
1704 "tx_underrun",
1705};
1706
b9f2c044 1707static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1708{
b9f2c044
JG		 1709 switch (sset) {
1710 case ETH_SS_STATS:
1711 return ARRAY_SIZE(rtl8169_gstrings);
1712 default:
1713 return -EOPNOTSUPP;
1714 }
d4a3a0fc
SH		 1715}
1716
42020320 1717DECLARE_RTL_COND(rtl_counters_cond)
6e85d5ad 1718{
1ef7286e 1719 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
6e85d5ad
CV		 1720}
1721
e71c9ce2 1722static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
6e85d5ad 1723{
42020320
CV		 1724 dma_addr_t paddr = tp->counters_phys_addr;
1725 u32 cmd;
6e85d5ad 1726
1ef7286e
AS		 1727 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1728 RTL_R32(tp, CounterAddrHigh);
42020320 1729 cmd = (u64)paddr & DMA_BIT_MASK(32);
1ef7286e
AS		 1730 RTL_W32(tp, CounterAddrLow, cmd);
1731 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
6e85d5ad 1732
a78e9366 1733 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
6e85d5ad
CV		 1734}
1735
e71c9ce2 1736static bool rtl8169_reset_counters(struct rtl8169_private *tp)
6e85d5ad 1737{
6e85d5ad
CV		 1738 /*
1739 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1740 * tally counters.
1741 */
1742 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1743 return true;
1744
e71c9ce2 1745 return rtl8169_do_counters(tp, CounterReset);
ffc46952
FR		 1746}
1747
e71c9ce2 1748static bool rtl8169_update_counters(struct rtl8169_private *tp)
d4a3a0fc 1749{
10262b0b
HK		 1750 u8 val = RTL_R8(tp, ChipCmd);
1751
355423d0
IV		 1752 /*
1753 * Some chips are unable to dump tally counters when the receiver
10262b0b 1754 * is disabled. If 0xff chip may be in a PCI power-save state.
355423d0 1755 */
10262b0b 1756 if (!(val & CmdRxEnb) || val == 0xff)
6e85d5ad 1757 return true;
d4a3a0fc 1758
e71c9ce2 1759 return rtl8169_do_counters(tp, CounterDump);
6e85d5ad
CV		 1760}
1761
e71c9ce2 1762static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
6e85d5ad 1763{
42020320 1764 struct rtl8169_counters *counters = tp->counters;
6e85d5ad
CV		 1765 bool ret = false;
1766
1767 /*
1768 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1769 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1770 * reset by a power cycle, while the counter values collected by the
1771 * driver are reset at every driver unload/load cycle.
1772 *
1773 * To make sure the HW values returned by @get_stats64 match the SW
1774 * values, we collect the initial values at first open(*) and use them
1775 * as offsets to normalize the values returned by @get_stats64.
1776 *
1777 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1778 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1779 * set at open time by rtl_hw_start.
1780 */
1781
1782 if (tp->tc_offset.inited)
1783 return true;
1784
1785 /* If both, reset and update fail, propagate to caller. */
e71c9ce2 1786 if (rtl8169_reset_counters(tp))
6e85d5ad
CV		 1787 ret = true;
1788
e71c9ce2 1789 if (rtl8169_update_counters(tp))
6e85d5ad
CV		 1790 ret = true;
1791
42020320
CV		 1792 tp->tc_offset.tx_errors = counters->tx_errors;
1793 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1794 tp->tc_offset.tx_aborted = counters->tx_aborted;
6e85d5ad
CV		 1795 tp->tc_offset.inited = true;
1796
1797 return ret;
d4a3a0fc
SH		 1798}
1799
355423d0
IV		 1800static void rtl8169_get_ethtool_stats(struct net_device *dev,
1801 struct ethtool_stats *stats, u64 *data)
1802{
1803 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 1804 struct device *d = tp_to_dev(tp);
42020320 1805 struct rtl8169_counters *counters = tp->counters;
355423d0
IV		 1806
1807 ASSERT_RTNL();
1808
e0636236
CHL		 1809 pm_runtime_get_noresume(d);
1810
1811 if (pm_runtime_active(d))
e71c9ce2 1812 rtl8169_update_counters(tp);
e0636236
CHL		 1813
1814 pm_runtime_put_noidle(d);
355423d0 1815
42020320
CV		 1816 data[0] = le64_to_cpu(counters->tx_packets);
1817 data[1] = le64_to_cpu(counters->rx_packets);
1818 data[2] = le64_to_cpu(counters->tx_errors);
1819 data[3] = le32_to_cpu(counters->rx_errors);
1820 data[4] = le16_to_cpu(counters->rx_missed);
1821 data[5] = le16_to_cpu(counters->align_errors);
1822 data[6] = le32_to_cpu(counters->tx_one_collision);
1823 data[7] = le32_to_cpu(counters->tx_multi_collision);
1824 data[8] = le64_to_cpu(counters->rx_unicast);
1825 data[9] = le64_to_cpu(counters->rx_broadcast);
1826 data[10] = le32_to_cpu(counters->rx_multicast);
1827 data[11] = le16_to_cpu(counters->tx_aborted);
1828 data[12] = le16_to_cpu(counters->tx_underun);
355423d0
IV		 1829}
1830
d4a3a0fc
SH		 1831static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1832{
1833 switch(stringset) {
1834 case ETH_SS_STATS:
1835 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1836 break;
1837 }
1838}
1839
50970831
FR		 1840/*
1841 * Interrupt coalescing
1842 *
1843 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1844 * > 8169, 8168 and 810x line of chipsets
1845 *
1846 * 8169, 8168, and 8136(810x) serial chipsets support it.
1847 *
1848 * > 2 - the Tx timer unit at gigabit speed
1849 *
1850 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1851 * (0xe0) bit 1 and bit 0.
1852 *
1853 * For 8169
1854 * bit[1:0] \ speed 1000M 100M 10M
1855 * 0 0 320ns 2.56us 40.96us
1856 * 0 1 2.56us 20.48us 327.7us
1857 * 1 0 5.12us 40.96us 655.4us
1858 * 1 1 10.24us 81.92us 1.31ms
1859 *
1860 * For the other
1861 * bit[1:0] \ speed 1000M 100M 10M
1862 * 0 0 5us 2.56us 40.96us
1863 * 0 1 40us 20.48us 327.7us
1864 * 1 0 80us 40.96us 655.4us
1865 * 1 1 160us 81.92us 1.31ms
1866 */
1867
1868/* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1869struct rtl_coalesce_scale {
1870 /* Rx / Tx */
1871 u32 nsecs[2];
1872};
1873
1874/* rx/tx scale factors for all CPlusCmd[0:1] cases */
1875struct rtl_coalesce_info {
1876 u32 speed;
1877 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1878};
1879
1880/* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1881#define rxtx_x1822(r, t) { \
1882 {{(r), (t)}}, \
1883 {{(r)*8, (t)*8}}, \
1884 {{(r)*8*2, (t)*8*2}}, \
1885 {{(r)*8*2*2, (t)*8*2*2}}, \
1886}
1887static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1888 /* speed delays: rx00 tx00 */
1889 { SPEED_10, rxtx_x1822(40960, 40960) },
1890 { SPEED_100, rxtx_x1822( 2560, 2560) },
1891 { SPEED_1000, rxtx_x1822( 320, 320) },
1892 { 0 },
1893};
1894
1895static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1896 /* speed delays: rx00 tx00 */
1897 { SPEED_10, rxtx_x1822(40960, 40960) },
1898 { SPEED_100, rxtx_x1822( 2560, 2560) },
1899 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1900 { 0 },
1901};
1902#undef rxtx_x1822
1903
1904/* get rx/tx scale vector corresponding to current speed */
1905static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1906{
1907 struct rtl8169_private *tp = netdev_priv(dev);
50970831 1908 const struct rtl_coalesce_info *ci;
50970831 1909
20023d3e
HK		 1910 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1911 ci = rtl_coalesce_info_8169;
1912 else
1913 ci = rtl_coalesce_info_8168_8136;
50970831 1914
20023d3e
HK		 1915 for (; ci->speed; ci++) {
1916 if (tp->phydev->speed == ci->speed)
50970831 1917 return ci;
50970831
FR		 1918 }
1919
1920 return ERR_PTR(-ELNRNG);
1921}
1922
1923static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1924{
1925 struct rtl8169_private *tp = netdev_priv(dev);
50970831
FR		 1926 const struct rtl_coalesce_info *ci;
1927 const struct rtl_coalesce_scale *scale;
1928 struct {
1929 u32 *max_frames;
1930 u32 *usecs;
1931 } coal_settings [] = {
1932 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1933 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1934 }, *p = coal_settings;
1935 int i;
1936 u16 w;
1937
f1bce4ad
HK		 1938 if (rtl_is_8125(tp))
1939 return -EOPNOTSUPP;
1940
50970831
FR		 1941 memset(ec, 0, sizeof(*ec));
1942
1943 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1944 ci = rtl_coalesce_info(dev);
1945 if (IS_ERR(ci))
1946 return PTR_ERR(ci);
1947
0ae0974e 1948 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
50970831
FR		 1949
1950 /* read IntrMitigate and adjust according to scale */
1ef7286e 1951 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
50970831
FR		 1952 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1953 w >>= RTL_COALESCE_SHIFT;
1954 *p->usecs = w & RTL_COALESCE_MASK;
1955 }
1956
1957 for (i = 0; i < 2; i++) {
1958 p = coal_settings + i;
1959 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1960
1961 /*
1962 * ethtool_coalesce says it is illegal to set both usecs and
1963 * max_frames to 0.
1964 */
1965 if (!*p->usecs && !*p->max_frames)
1966 *p->max_frames = 1;
1967 }
1968
1969 return 0;
1970}
1971
1972/* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1973static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1974 struct net_device *dev, u32 nsec, u16 *cp01)
1975{
1976 const struct rtl_coalesce_info *ci;
1977 u16 i;
1978
1979 ci = rtl_coalesce_info(dev);
1980 if (IS_ERR(ci))
1981 return ERR_CAST(ci);
1982
1983 for (i = 0; i < 4; i++) {
1984 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1985 ci->scalev[i].nsecs[1]);
1986 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1987 *cp01 = i;
1988 return &ci->scalev[i];
1989 }
1990 }
1991
1992 return ERR_PTR(-EINVAL);
1993}
1994
1995static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1996{
1997 struct rtl8169_private *tp = netdev_priv(dev);
50970831
FR		 1998 const struct rtl_coalesce_scale *scale;
1999 struct {
2000 u32 frames;
2001 u32 usecs;
2002 } coal_settings [] = {
2003 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
2004 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
2005 }, *p = coal_settings;
2006 u16 w = 0, cp01;
2007 int i;
2008
f1bce4ad
HK		 2009 if (rtl_is_8125(tp))
2010 return -EOPNOTSUPP;
2011
50970831
FR		 2012 scale = rtl_coalesce_choose_scale(dev,
2013 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
2014 if (IS_ERR(scale))
2015 return PTR_ERR(scale);
2016
2017 for (i = 0; i < 2; i++, p++) {
2018 u32 units;
2019
2020 /*
2021 * accept max_frames=1 we returned in rtl_get_coalesce.
2022 * accept it not only when usecs=0 because of e.g. the following scenario:
2023 *
2024 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2025 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2026 * - then user does `ethtool -C eth0 rx-usecs 100`
2027 *
2028 * since ethtool sends to kernel whole ethtool_coalesce
2029 * settings, if we do not handle rx_usecs=!0, rx_frames=1
2030 * we'll reject it below in `frames % 4 != 0`.
2031 */
2032 if (p->frames == 1) {
2033 p->frames = 0;
2034 }
2035
2036 units = p->usecs * 1000 / scale->nsecs[i];
2037 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2038 return -EINVAL;
2039
2040 w <<= RTL_COALESCE_SHIFT;
2041 w |= units;
2042 w <<= RTL_COALESCE_SHIFT;
2043 w |= p->frames >> 2;
2044 }
2045
2046 rtl_lock_work(tp);
2047
1ef7286e 2048 RTL_W16(tp, IntrMitigate, swab16(w));
50970831 2049
9a3c81fa 2050 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1ef7286e
AS		 2051 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2052 RTL_R16(tp, CPlusCmd);
50970831
FR		 2053
2054 rtl_unlock_work(tp);
2055
2056 return 0;
2057}
2058
df6f1856
HK		 2059static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2060{
2061 struct rtl8169_private *tp = netdev_priv(dev);
2062 struct device *d = tp_to_dev(tp);
2063 int ret;
2064
2e779ddb
HK		 2065 if (!rtl_supports_eee(tp))
2066 return -EOPNOTSUPP;
2067
df6f1856
HK		 2068 pm_runtime_get_noresume(d);
2069
2070 if (!pm_runtime_active(d)) {
2071 ret = -EOPNOTSUPP;
2e779ddb
HK		 2072 } else {
2073 ret = phy_ethtool_get_eee(tp->phydev, data);
df6f1856
HK		 2074 }
2075
df6f1856 2076 pm_runtime_put_noidle(d);
2e779ddb
HK		 2077
2078 return ret;
df6f1856
HK		 2079}
2080
2081static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2082{
2083 struct rtl8169_private *tp = netdev_priv(dev);
2084 struct device *d = tp_to_dev(tp);
2e779ddb
HK		 2085 int ret;
2086
2087 if (!rtl_supports_eee(tp))
2088 return -EOPNOTSUPP;
df6f1856
HK		 2089
2090 pm_runtime_get_noresume(d);
2091
2e779ddb 2092 if (!pm_runtime_active(d)) {
df6f1856
HK		 2093 ret = -EOPNOTSUPP;
2094 goto out;
2095 }
2096
2097 if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2098 dev->phydev->duplex != DUPLEX_FULL) {
2099 ret = -EPROTONOSUPPORT;
2100 goto out;
2101 }
2102
2e779ddb 2103 ret = phy_ethtool_set_eee(tp->phydev, data);
7ec3f872
HK		 2104
2105 if (!ret)
2106 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
2107 MDIO_AN_EEE_ADV);
df6f1856
HK		 2108out:
2109 pm_runtime_put_noidle(d);
2e779ddb 2110 return ret;
df6f1856
HK		 2111}
2112
7282d491 2113static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2114 .get_drvinfo = rtl8169_get_drvinfo,
2115 .get_regs_len = rtl8169_get_regs_len,
2116 .get_link = ethtool_op_get_link,
50970831
FR		 2117 .get_coalesce = rtl_get_coalesce,
2118 .set_coalesce = rtl_set_coalesce,
b57b7e5a
SH		 2119 .get_msglevel = rtl8169_get_msglevel,
2120 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2121 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2122 .get_wol = rtl8169_get_wol,
2123 .set_wol = rtl8169_set_wol,
d4a3a0fc 2124 .get_strings = rtl8169_get_strings,
b9f2c044 2125 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2126 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2127 .get_ts_info = ethtool_op_get_ts_info,
dd84957e 2128 .nway_reset = phy_ethtool_nway_reset,
df6f1856
HK		 2129 .get_eee = rtl8169_get_eee,
2130 .set_eee = rtl8169_set_eee,
45772433
HK		 2131 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2132 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1da177e4
LT		 2133};
2134
b6c7fa40
HK		 2135static void rtl_enable_eee(struct rtl8169_private *tp)
2136{
2e779ddb 2137 struct phy_device *phydev = tp->phydev;
7ec3f872
HK		 2138 int adv;
2139
2140 /* respect EEE advertisement the user may have set */
2141 if (tp->eee_adv >= 0)
2142 adv = tp->eee_adv;
2143 else
2144 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
b6c7fa40 2145
7ec3f872
HK		 2146 if (adv >= 0)
2147 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
b6c7fa40
HK		 2148}
2149
b4cc2dcc 2150static void rtl8169_get_mac_version(struct rtl8169_private *tp)
1da177e4 2151{
0e485150
FR		 2152 /*
2153 * The driver currently handles the 8168Bf and the 8168Be identically
2154 * but they can be identified more specifically through the test below
2155 * if needed:
2156 *
1ef7286e 2157 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2158 *
2159 * Same thing for the 8101Eb and the 8101Ec:
2160 *
1ef7286e 2161 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2162 */
3744100e 2163 static const struct rtl_mac_info {
55d2ad7b
HK		 2164 u16 mask;
2165 u16 val;
2166 u16 mac_version;
1da177e4 2167 } mac_info[] = {
f1bce4ad
HK		 2168 /* 8125 family. */
2169 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
2170 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
2171
1287723a
HK		 2172 /* RTL8117 */
2173 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
2174
935e2218 2175 /* 8168EP family. */
55d2ad7b
HK		 2176 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2177 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2178 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
935e2218 2179
6e1d0b89 2180 /* 8168H family. */
55d2ad7b
HK		 2181 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2182 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
6e1d0b89 2183
c558386b 2184 /* 8168G family. */
55d2ad7b
HK		 2185 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2186 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2187 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2188 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
c558386b 2189
c2218925 2190 /* 8168F family. */
55d2ad7b
HK		 2191 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2192 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2193 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
c2218925 2194
01dc7fec 2195 /* 8168E family. */
55d2ad7b
HK		 2196 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2197 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2198 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
01dc7fec 2199
5b538df9 2200 /* 8168D family. */
55d2ad7b
HK		 2201 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2202 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
5b538df9 2203
e6de30d6 2204 /* 8168DP family. */
55d2ad7b
HK		 2205 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2206 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2207 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
e6de30d6 2208
ef808d50 2209 /* 8168C family. */
55d2ad7b
HK		 2210 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2211 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2212 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2213 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2214 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2215 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2216 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2217
2218 /* 8168B family. */
55d2ad7b
HK		 2219 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2220 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2221 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
e3cf0cc0
FR		 2222
2223 /* 8101 family. */
55d2ad7b
HK		 2224 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2225 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2226 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2227 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2228 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2229 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2230 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2231 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2232 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2233 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2234 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2235 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2236 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2237 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
e3cf0cc0 2238 /* FIXME: where did these entries come from ? -- FR */
55d2ad7b
HK		 2239 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2240 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
e3cf0cc0
FR		 2241
2242 /* 8110 family. */
55d2ad7b
HK		 2243 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2244 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2245 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2246 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2247 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
e3cf0cc0 2248
f21b75e9 2249 /* Catch-all */
55d2ad7b 2250 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2251 };
2252 const struct rtl_mac_info *p = mac_info;
55d2ad7b 2253 u16 reg = RTL_R32(tp, TxConfig) >> 20;
1da177e4 2254
e3cf0cc0 2255 while ((reg & p->mask) != p->val)
1da177e4
LT		 2256 p++;
2257 tp->mac_version = p->mac_version;
5d320a20
FR		 2258
2259 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
b4cc2dcc 2260 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
45f1996f
HK		 2261 } else if (!tp->supports_gmii) {
2262 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2263 tp->mac_version = RTL_GIGA_MAC_VER_43;
2264 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2265 tp->mac_version = RTL_GIGA_MAC_VER_47;
2266 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2267 tp->mac_version = RTL_GIGA_MAC_VER_48;
5d320a20 2268 }
1da177e4
LT		 2269}
2270
867763c1
FR		 2271struct phy_reg {
2272 u16 reg;
2273 u16 val;
2274};
2275
1791ad50
HK		 2276static void __rtl_writephy_batch(struct rtl8169_private *tp,
2277 const struct phy_reg *regs, int len)
867763c1
FR		 2278{
2279 while (len-- > 0) {
4da19633 2280 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2281 regs++;
2282 }
2283}
2284
1791ad50
HK		 2285#define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2286
f1e02ed1 2287static void rtl_release_firmware(struct rtl8169_private *tp)
2288{
254764e5 2289 if (tp->rtl_fw) {
47ad5931 2290 rtl_fw_release_firmware(tp->rtl_fw);
b6ffd97f 2291 kfree(tp->rtl_fw);
254764e5 2292 tp->rtl_fw = NULL;
b6ffd97f 2293 }
f1e02ed1 2294}
2295
953a12cc 2296static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2297{
ce8843ab 2298 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
254764e5 2299 if (tp->rtl_fw)
ce8843ab 2300 rtl_fw_write_firmware(tp, tp->rtl_fw);
953a12cc
FR		 2301}
2302
df6f1856
HK		 2303static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2304{
f452825d
HK		 2305 /* Adjust EEE LED frequency */
2306 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2307 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2308
e719b3ea 2309 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
df6f1856
HK		 2310}
2311
b3a42e3a
HK		 2312static void rtl8125_config_eee_mac(struct rtl8169_private *tp)
2313{
2314 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2315 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2316}
2317
cc07d271
HK		 2318static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2319{
2320 struct phy_device *phydev = tp->phydev;
2321
d0db136f 2322 r8168d_modify_extpage(phydev, 0x0020, 0x15, 0, BIT(8));
b5e189b4 2323 r8168d_phy_param(phydev, 0x8b85, 0, BIT(13));
cc07d271
HK		 2324}
2325
df6f1856
HK		 2326static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2327{
a2928d28 2328 phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4));
df6f1856
HK		 2329}
2330
b6cef26f
HK		 2331static void rtl8168h_config_eee_phy(struct rtl8169_private *tp)
2332{
2333 struct phy_device *phydev = tp->phydev;
2334
2335 rtl8168g_config_eee_phy(tp);
2336
2337 phy_modify_paged(phydev, 0xa4a, 0x11, 0x0000, 0x0200);
2338 phy_modify_paged(phydev, 0xa42, 0x14, 0x0000, 0x0080);
2339}
2340
b3a42e3a
HK		 2341static void rtl8125_config_eee_phy(struct rtl8169_private *tp)
2342{
2343 struct phy_device *phydev = tp->phydev;
2344
2345 rtl8168h_config_eee_phy(tp);
2346
2347 phy_modify_paged(phydev, 0xa6d, 0x12, 0x0001, 0x0000);
2348 phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000);
2349}
2350
4da19633 2351static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2352{
350f7596 2353 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2354 { 0x1f, 0x0001 },
2355 { 0x06, 0x006e },
2356 { 0x08, 0x0708 },
2357 { 0x15, 0x4000 },
2358 { 0x18, 0x65c7 },
1da177e4 2359
0b9b571d 2360 { 0x1f, 0x0001 },
2361 { 0x03, 0x00a1 },
2362 { 0x02, 0x0008 },
2363 { 0x01, 0x0120 },
2364 { 0x00, 0x1000 },
2365 { 0x04, 0x0800 },
2366 { 0x04, 0x0000 },
1da177e4 2367
0b9b571d 2368 { 0x03, 0xff41 },
2369 { 0x02, 0xdf60 },
2370 { 0x01, 0x0140 },
2371 { 0x00, 0x0077 },
2372 { 0x04, 0x7800 },
2373 { 0x04, 0x7000 },
2374
2375 { 0x03, 0x802f },
2376 { 0x02, 0x4f02 },
2377 { 0x01, 0x0409 },
2378 { 0x00, 0xf0f9 },
2379 { 0x04, 0x9800 },
2380 { 0x04, 0x9000 },
2381
2382 { 0x03, 0xdf01 },
2383 { 0x02, 0xdf20 },
2384 { 0x01, 0xff95 },
2385 { 0x00, 0xba00 },
2386 { 0x04, 0xa800 },
2387 { 0x04, 0xa000 },
2388
2389 { 0x03, 0xff41 },
2390 { 0x02, 0xdf20 },
2391 { 0x01, 0x0140 },
2392 { 0x00, 0x00bb },
2393 { 0x04, 0xb800 },
2394 { 0x04, 0xb000 },
2395
2396 { 0x03, 0xdf41 },
2397 { 0x02, 0xdc60 },
2398 { 0x01, 0x6340 },
2399 { 0x00, 0x007d },
2400 { 0x04, 0xd800 },
2401 { 0x04, 0xd000 },
2402
2403 { 0x03, 0xdf01 },
2404 { 0x02, 0xdf20 },
2405 { 0x01, 0x100a },
2406 { 0x00, 0xa0ff },
2407 { 0x04, 0xf800 },
2408 { 0x04, 0xf000 },
2409
2410 { 0x1f, 0x0000 },
2411 { 0x0b, 0x0000 },
2412 { 0x00, 0x9200 }
2413 };
1da177e4 2414
1791ad50 2415 rtl_writephy_batch(tp, phy_reg_init);
1da177e4
LT		 2416}
2417
4da19633 2418static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2419{
3a129e3f 2420 phy_write_paged(tp->phydev, 0x0002, 0x01, 0x90d0);
5615d9f1
FR		 2421}
2422
4da19633 2423static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2424{
2425 struct pci_dev *pdev = tp->pci_dev;
2e955856 2426
ccbae55e
SS		 2427 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2428 (pdev->subsystem_device != 0xe000))
2e955856 2429 return;
2430
3a129e3f 2431 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2e955856 2432}
2433
4da19633 2434static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2435{
350f7596 2436 static const struct phy_reg phy_reg_init[] = {
2e955856 2437 { 0x1f, 0x0001 },
2438 { 0x04, 0x0000 },
2439 { 0x03, 0x00a1 },
2440 { 0x02, 0x0008 },
2441 { 0x01, 0x0120 },
2442 { 0x00, 0x1000 },
2443 { 0x04, 0x0800 },
2444 { 0x04, 0x9000 },
2445 { 0x03, 0x802f },
2446 { 0x02, 0x4f02 },
2447 { 0x01, 0x0409 },
2448 { 0x00, 0xf099 },
2449 { 0x04, 0x9800 },
2450 { 0x04, 0xa000 },
2451 { 0x03, 0xdf01 },
2452 { 0x02, 0xdf20 },
2453 { 0x01, 0xff95 },
2454 { 0x00, 0xba00 },
2455 { 0x04, 0xa800 },
2456 { 0x04, 0xf000 },
2457 { 0x03, 0xdf01 },
2458 { 0x02, 0xdf20 },
2459 { 0x01, 0x101a },
2460 { 0x00, 0xa0ff },
2461 { 0x04, 0xf800 },
2462 { 0x04, 0x0000 },
2463 { 0x1f, 0x0000 },
2464
2465 { 0x1f, 0x0001 },
2466 { 0x10, 0xf41b },
2467 { 0x14, 0xfb54 },
2468 { 0x18, 0xf5c7 },
2469 { 0x1f, 0x0000 },
2470
2471 { 0x1f, 0x0001 },
2472 { 0x17, 0x0cc0 },
2473 { 0x1f, 0x0000 }
2474 };
2475
1791ad50 2476 rtl_writephy_batch(tp, phy_reg_init);
2e955856 2477
4da19633 2478 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2479}
2480
4da19633 2481static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2482{
350f7596 2483 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2484 { 0x1f, 0x0001 },
2485 { 0x04, 0x0000 },
2486 { 0x03, 0x00a1 },
2487 { 0x02, 0x0008 },
2488 { 0x01, 0x0120 },
2489 { 0x00, 0x1000 },
2490 { 0x04, 0x0800 },
2491 { 0x04, 0x9000 },
2492 { 0x03, 0x802f },
2493 { 0x02, 0x4f02 },
2494 { 0x01, 0x0409 },
2495 { 0x00, 0xf099 },
2496 { 0x04, 0x9800 },
2497 { 0x04, 0xa000 },
2498 { 0x03, 0xdf01 },
2499 { 0x02, 0xdf20 },
2500 { 0x01, 0xff95 },
2501 { 0x00, 0xba00 },
2502 { 0x04, 0xa800 },
2503 { 0x04, 0xf000 },
2504 { 0x03, 0xdf01 },
2505 { 0x02, 0xdf20 },
2506 { 0x01, 0x101a },
2507 { 0x00, 0xa0ff },
2508 { 0x04, 0xf800 },
2509 { 0x04, 0x0000 },
2510 { 0x1f, 0x0000 },
2511
2512 { 0x1f, 0x0001 },
2513 { 0x0b, 0x8480 },
2514 { 0x1f, 0x0000 },
2515
2516 { 0x1f, 0x0001 },
2517 { 0x18, 0x67c7 },
2518 { 0x04, 0x2000 },
2519 { 0x03, 0x002f },
2520 { 0x02, 0x4360 },
2521 { 0x01, 0x0109 },
2522 { 0x00, 0x3022 },
2523 { 0x04, 0x2800 },
2524 { 0x1f, 0x0000 },
2525
2526 { 0x1f, 0x0001 },
2527 { 0x17, 0x0cc0 },
2528 { 0x1f, 0x0000 }
2529 };
2530
1791ad50 2531 rtl_writephy_batch(tp, phy_reg_init);
8c7006aa 2532}
2533
4da19633 2534static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2535{
4da19633 2536 rtl_writephy(tp, 0x1f, 0x0001);
2537 rtl_patchphy(tp, 0x16, 1 << 0);
3a129e3f
HK		 2538 rtl_writephy(tp, 0x10, 0xf41b);
2539 rtl_writephy(tp, 0x1f, 0x0000);
236b8082
FR		 2540}
2541
4da19633 2542static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2543{
3a129e3f 2544 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf41b);
236b8082
FR		 2545}
2546
4da19633 2547static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2548{
3a129e3f
HK		 2549 phy_write(tp->phydev, 0x1d, 0x0f00);
2550 phy_write_paged(tp->phydev, 0x0002, 0x0c, 0x1ec8);
867763c1
FR		 2551}
2552
4da19633 2553static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2554{
3a129e3f
HK		 2555 phy_set_bits(tp->phydev, 0x14, BIT(5));
2556 phy_set_bits(tp->phydev, 0x0d, BIT(5));
2557 phy_write_paged(tp->phydev, 0x0001, 0x1d, 0x3d98);
ef3386f0
FR		 2558}
2559
4da19633 2560static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2561{
350f7596 2562 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2563 { 0x1f, 0x0001 },
2564 { 0x12, 0x2300 },
867763c1
FR		 2565 { 0x1f, 0x0002 },
2566 { 0x00, 0x88d4 },
2567 { 0x01, 0x82b1 },
2568 { 0x03, 0x7002 },
2569 { 0x08, 0x9e30 },
2570 { 0x09, 0x01f0 },
2571 { 0x0a, 0x5500 },
2572 { 0x0c, 0x00c8 },
2573 { 0x1f, 0x0003 },
2574 { 0x12, 0xc096 },
2575 { 0x16, 0x000a },
f50d4275
FR		 2576 { 0x1f, 0x0000 },
2577 { 0x1f, 0x0000 },
2578 { 0x09, 0x2000 },
2579 { 0x09, 0x0000 }
867763c1
FR		 2580 };
2581
1791ad50 2582 rtl_writephy_batch(tp, phy_reg_init);
f50d4275 2583
4da19633 2584 rtl_patchphy(tp, 0x14, 1 << 5);
2585 rtl_patchphy(tp, 0x0d, 1 << 5);
2586 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2587}
2588
4da19633 2589static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2590{
350f7596 2591 static const struct phy_reg phy_reg_init[] = {
f50d4275 2592 { 0x1f, 0x0001 },
7da97ec9 2593 { 0x12, 0x2300 },
f50d4275
FR		 2594 { 0x03, 0x802f },
2595 { 0x02, 0x4f02 },
2596 { 0x01, 0x0409 },
2597 { 0x00, 0xf099 },
2598 { 0x04, 0x9800 },
2599 { 0x04, 0x9000 },
2600 { 0x1d, 0x3d98 },
7da97ec9
FR		 2601 { 0x1f, 0x0002 },
2602 { 0x0c, 0x7eb8 },
f50d4275
FR		 2603 { 0x06, 0x0761 },
2604 { 0x1f, 0x0003 },
2605 { 0x16, 0x0f0a },
7da97ec9
FR		 2606 { 0x1f, 0x0000 }
2607 };
2608
1791ad50 2609 rtl_writephy_batch(tp, phy_reg_init);
f50d4275 2610
4da19633 2611 rtl_patchphy(tp, 0x16, 1 << 0);
2612 rtl_patchphy(tp, 0x14, 1 << 5);
2613 rtl_patchphy(tp, 0x0d, 1 << 5);
2614 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2615}
2616
4da19633 2617static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2618{
350f7596 2619 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2620 { 0x1f, 0x0001 },
2621 { 0x12, 0x2300 },
2622 { 0x1d, 0x3d98 },
2623 { 0x1f, 0x0002 },
2624 { 0x0c, 0x7eb8 },
2625 { 0x06, 0x5461 },
2626 { 0x1f, 0x0003 },
2627 { 0x16, 0x0f0a },
2628 { 0x1f, 0x0000 }
2629 };
2630
1791ad50 2631 rtl_writephy_batch(tp, phy_reg_init);
197ff761 2632
4da19633 2633 rtl_patchphy(tp, 0x16, 1 << 0);
2634 rtl_patchphy(tp, 0x14, 1 << 5);
2635 rtl_patchphy(tp, 0x0d, 1 << 5);
2636 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2637}
2638
fcb40e16
HK		 2639static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
2640 /* Channel Estimation */
2641 { 0x1f, 0x0001 },
2642 { 0x06, 0x4064 },
2643 { 0x07, 0x2863 },
2644 { 0x08, 0x059c },
2645 { 0x09, 0x26b4 },
2646 { 0x0a, 0x6a19 },
2647 { 0x0b, 0xdcc8 },
2648 { 0x10, 0xf06d },
2649 { 0x14, 0x7f68 },
2650 { 0x18, 0x7fd9 },
2651 { 0x1c, 0xf0ff },
2652 { 0x1d, 0x3d9c },
2653 { 0x1f, 0x0003 },
2654 { 0x12, 0xf49f },
2655 { 0x13, 0x070b },
2656 { 0x1a, 0x05ad },
2657 { 0x14, 0x94c0 },
bca03d5f 2658
fcb40e16
HK		 2659 /*
2660 * Tx Error Issue
2661 * Enhance line driver power
2662 */
2663 { 0x1f, 0x0002 },
2664 { 0x06, 0x5561 },
2665 { 0x1f, 0x0005 },
2666 { 0x05, 0x8332 },
2667 { 0x06, 0x5561 },
bca03d5f 2668
fcb40e16
HK		 2669 /*
2670 * Can not link to 1Gbps with bad cable
2671 * Decrease SNR threshold form 21.07dB to 19.04dB
2672 */
2673 { 0x1f, 0x0001 },
2674 { 0x17, 0x0cc0 },
daf9df6d 2675
fcb40e16
HK		 2676 { 0x1f, 0x0000 },
2677 { 0x0d, 0xf880 }
2678};
2679
2680static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
2681 { 0x1f, 0x0002 },
2682 { 0x05, 0x669a },
2683 { 0x1f, 0x0005 },
2684 { 0x05, 0x8330 },
2685 { 0x06, 0x669a },
2686 { 0x1f, 0x0002 }
2687};
daf9df6d 2688
718af5bc
HK		 2689static void rtl8168d_apply_firmware_cond(struct rtl8169_private *tp, u16 val)
2690{
2691 u16 reg_val;
2692
2693 rtl_writephy(tp, 0x1f, 0x0005);
2694 rtl_writephy(tp, 0x05, 0x001b);
2695 reg_val = rtl_readphy(tp, 0x06);
2696 rtl_writephy(tp, 0x1f, 0x0000);
2697
2698 if (reg_val != val)
2699 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2700 else
2701 rtl_apply_firmware(tp);
2702}
2703
fcb40e16
HK		 2704static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2705{
2706 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
daf9df6d 2707
bca03d5f 2708 /*
2709 * Rx Error Issue
2710 * Fine Tune Switching regulator parameter
2711 */
4da19633 2712 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 2713 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2714 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2715
fdf6fc06 2716 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
daf9df6d 2717 int val;
2718
fcb40e16 2719 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
daf9df6d 2720
4da19633 2721 val = rtl_readphy(tp, 0x0d);
daf9df6d 2722
2723 if ((val & 0x00ff) != 0x006c) {
350f7596 2724 static const u32 set[] = {
daf9df6d 2725 0x0065, 0x0066, 0x0067, 0x0068,
2726 0x0069, 0x006a, 0x006b, 0x006c
2727 };
2728 int i;
2729
4da19633 2730 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2731
2732 val &= 0xff00;
2733 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2734 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2735 }
2736 } else {
b5e189b4
HK		 2737 phy_write_paged(tp->phydev, 0x0002, 0x05, 0x6662);
2738 r8168d_phy_param(tp->phydev, 0x8330, 0xffff, 0x6662);
daf9df6d 2739 }
2740
bca03d5f 2741 /* RSET couple improve */
4da19633 2742 rtl_writephy(tp, 0x1f, 0x0002);
2743 rtl_patchphy(tp, 0x0d, 0x0300);
2744 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2745
bca03d5f 2746 /* Fine tune PLL performance */
4da19633 2747 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 2748 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2749 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
4da19633 2750 rtl_writephy(tp, 0x1f, 0x0000);
718af5bc
HK		 2751
2752 rtl8168d_apply_firmware_cond(tp, 0xbf00);
daf9df6d 2753}
2754
bca03d5f 2755static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2756{
fcb40e16 2757 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
5b538df9 2758
fdf6fc06 2759 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
daf9df6d 2760 int val;
2761
fcb40e16 2762 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
daf9df6d 2763
4da19633 2764 val = rtl_readphy(tp, 0x0d);
daf9df6d 2765 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2766 static const u32 set[] = {
daf9df6d 2767 0x0065, 0x0066, 0x0067, 0x0068,
2768 0x0069, 0x006a, 0x006b, 0x006c
2769 };
2770 int i;
2771
4da19633 2772 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2773
2774 val &= 0xff00;
2775 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2776 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2777 }
2778 } else {
b5e189b4
HK		 2779 phy_write_paged(tp->phydev, 0x0002, 0x05, 0x2642);
2780 r8168d_phy_param(tp->phydev, 0x8330, 0xffff, 0x2642);
5b538df9
FR		 2781 }
2782
bca03d5f 2783 /* Fine tune PLL performance */
4da19633 2784 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 2785 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2786 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2787
bca03d5f 2788 /* Switching regulator Slew rate */
4da19633 2789 rtl_writephy(tp, 0x1f, 0x0002);
2790 rtl_patchphy(tp, 0x0f, 0x0017);
4da19633 2791 rtl_writephy(tp, 0x1f, 0x0000);
718af5bc
HK		 2792
2793 rtl8168d_apply_firmware_cond(tp, 0xb300);
daf9df6d 2794}
2795
4da19633 2796static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2797{
350f7596 2798 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2799 { 0x1f, 0x0002 },
2800 { 0x10, 0x0008 },
2801 { 0x0d, 0x006c },
2802
2803 { 0x1f, 0x0000 },
2804 { 0x0d, 0xf880 },
2805
2806 { 0x1f, 0x0001 },
2807 { 0x17, 0x0cc0 },
2808
2809 { 0x1f, 0x0001 },
2810 { 0x0b, 0xa4d8 },
2811 { 0x09, 0x281c },
2812 { 0x07, 0x2883 },
2813 { 0x0a, 0x6b35 },
2814 { 0x1d, 0x3da4 },
2815 { 0x1c, 0xeffd },
2816 { 0x14, 0x7f52 },
2817 { 0x18, 0x7fc6 },
2818 { 0x08, 0x0601 },
2819 { 0x06, 0x4063 },
2820 { 0x10, 0xf074 },
2821 { 0x1f, 0x0003 },
2822 { 0x13, 0x0789 },
2823 { 0x12, 0xf4bd },
2824 { 0x1a, 0x04fd },
2825 { 0x14, 0x84b0 },
2826 { 0x1f, 0x0000 },
2827 { 0x00, 0x9200 },
2828
2829 { 0x1f, 0x0005 },
2830 { 0x01, 0x0340 },
2831 { 0x1f, 0x0001 },
2832 { 0x04, 0x4000 },
2833 { 0x03, 0x1d21 },
2834 { 0x02, 0x0c32 },
2835 { 0x01, 0x0200 },
2836 { 0x00, 0x5554 },
2837 { 0x04, 0x4800 },
2838 { 0x04, 0x4000 },
2839 { 0x04, 0xf000 },
2840 { 0x03, 0xdf01 },
2841 { 0x02, 0xdf20 },
2842 { 0x01, 0x101a },
2843 { 0x00, 0xa0ff },
2844 { 0x04, 0xf800 },
2845 { 0x04, 0xf000 },
2846 { 0x1f, 0x0000 },
daf9df6d 2847 };
2848
1791ad50 2849 rtl_writephy_batch(tp, phy_reg_init);
0721914a
HK		 2850
2851 r8168d_modify_extpage(tp->phydev, 0x0023, 0x16, 0xffff, 0x0000);
5b538df9
FR		 2852}
2853
e6de30d6 2854static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2855{
0721914a
HK		 2856 phy_write_paged(tp->phydev, 0x0001, 0x17, 0x0cc0);
2857 r8168d_modify_extpage(tp->phydev, 0x002d, 0x18, 0xffff, 0x0040);
2858 phy_set_bits(tp->phydev, 0x0d, BIT(5));
e6de30d6 2859}
2860
70090424 2861static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 2862{
2863 static const struct phy_reg phy_reg_init[] = {
01dc7fec 2864 /* Channel estimation fine tune */
2865 { 0x1f, 0x0001 },
2866 { 0x0b, 0x6c20 },
2867 { 0x07, 0x2872 },
2868 { 0x1c, 0xefff },
2869 { 0x1f, 0x0003 },
2870 { 0x14, 0x6420 },
2871 { 0x1f, 0x0000 },
01dc7fec 2872 };
b5e189b4 2873 struct phy_device *phydev = tp->phydev;
01dc7fec 2874
15ecd039
FR		 2875 rtl_apply_firmware(tp);
2876
b5e189b4
HK		 2877 /* Enable Delay cap */
2878 r8168d_phy_param(phydev, 0x8b80, 0xffff, 0xc896);
2879
1791ad50 2880 rtl_writephy_batch(tp, phy_reg_init);
01dc7fec 2881
0721914a
HK		 2882 /* Update PFM & 10M TX idle timer */
2883 r8168d_modify_extpage(phydev, 0x002f, 0x15, 0xffff, 0x1919);
2884
2885 r8168d_modify_extpage(phydev, 0x00ac, 0x18, 0xffff, 0x0006);
2886
01dc7fec 2887 /* DCO enable for 10M IDLE Power */
0721914a 2888 r8168d_modify_extpage(phydev, 0x0023, 0x17, 0x0000, 0x0006);
01dc7fec 2889
2890 /* For impedance matching */
3a129e3f 2891 phy_modify_paged(phydev, 0x0002, 0x08, 0x7f00, 0x8000);
01dc7fec 2892
2893 /* PHY auto speed down */
0721914a
HK		 2894 r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0050);
2895 phy_set_bits(phydev, 0x14, BIT(15));
01dc7fec 2896
b5e189b4
HK		 2897 r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001);
2898 r8168d_phy_param(phydev, 0x8b85, 0x2000, 0x0000);
01dc7fec 2899
0721914a
HK		 2900 r8168d_modify_extpage(phydev, 0x0020, 0x15, 0x1100, 0x0000);
2901 phy_write_paged(phydev, 0x0006, 0x00, 0x5a00);
b5e189b4
HK		 2902
2903 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0000);
01dc7fec 2904}
2905
9ecb9aab 2906static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
2907{
2908 const u16 w[] = {
2909 addr[0] | (addr[1] << 8),
2910 addr[2] | (addr[3] << 8),
2911 addr[4] | (addr[5] << 8)
2912 };
9ecb9aab 2913
3aa4c491
HK		 2914 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
2915 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
2916 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
2917 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
9ecb9aab 2918}
2919
70090424
HW		 2920static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2921{
b5e189b4 2922 struct phy_device *phydev = tp->phydev;
70090424
HW		 2923
2924 rtl_apply_firmware(tp);
2925
0721914a
HK		 2926 /* Enable Delay cap */
2927 r8168d_modify_extpage(phydev, 0x00ac, 0x18, 0xffff, 0x0006);
2928
2929 /* Channel estimation fine tune */
2930 phy_write_paged(phydev, 0x0003, 0x09, 0xa20f);
70090424 2931
b5e189b4
HK		 2932 /* Green Setting */
2933 r8168d_phy_param(phydev, 0x8b5b, 0xffff, 0x9222);
2934 r8168d_phy_param(phydev, 0x8b6d, 0xffff, 0x8000);
2935 r8168d_phy_param(phydev, 0x8b76, 0xffff, 0x8000);
2936
70090424
HW		 2937 /* For 4-corner performance improve */
2938 rtl_writephy(tp, 0x1f, 0x0005);
2939 rtl_writephy(tp, 0x05, 0x8b80);
76564428 2940 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
70090424
HW		 2941 rtl_writephy(tp, 0x1f, 0x0000);
2942
2943 /* PHY auto speed down */
0721914a
HK		 2944 r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0010);
2945 phy_set_bits(phydev, 0x14, BIT(15));
70090424
HW		 2946
2947 /* improve 10M EEE waveform */
b5e189b4 2948 r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001);
70090424
HW		 2949
2950 /* Improve 2-pair detection performance */
b5e189b4 2951 r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000);
70090424 2952
cc07d271 2953 rtl8168f_config_eee_phy(tp);
1563daa3 2954 rtl_enable_eee(tp);
70090424
HW		 2955
2956 /* Green feature */
2957 rtl_writephy(tp, 0x1f, 0x0003);
1814d6a8
HK		 2958 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
2959 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
70090424 2960 rtl_writephy(tp, 0x1f, 0x0000);
b399a394
HK		 2961 rtl_writephy(tp, 0x1f, 0x0005);
2962 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
2963 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 2964
9ecb9aab 2965 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
2966 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 2967}
2968
5f886e08
HW		 2969static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
2970{
b5e189b4
HK		 2971 struct phy_device *phydev = tp->phydev;
2972
5f886e08 2973 /* For 4-corner performance improve */
b5e189b4 2974 r8168d_phy_param(phydev, 0x8b80, 0x0000, 0x0006);
5f886e08
HW		 2975
2976 /* PHY auto speed down */
0721914a
HK		 2977 r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0010);
2978 phy_set_bits(phydev, 0x14, BIT(15));
5f886e08
HW		 2979
2980 /* Improve 10M EEE waveform */
b5e189b4 2981 r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001);
cc07d271
HK		 2982
2983 rtl8168f_config_eee_phy(tp);
1563daa3 2984 rtl_enable_eee(tp);
5f886e08
HW		 2985}
2986
c2218925
HW		 2987static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
2988{
b5e189b4 2989 struct phy_device *phydev = tp->phydev;
c2218925 2990
b5e189b4 2991 rtl_apply_firmware(tp);
c2218925 2992
b5e189b4
HK		 2993 /* Channel estimation fine tune */
2994 phy_write_paged(phydev, 0x0003, 0x09, 0xa20f);
c2218925 2995
b5e189b4
HK		 2996 /* Modify green table for giga & fnet */
2997 r8168d_phy_param(phydev, 0x8b55, 0xffff, 0x0000);
2998 r8168d_phy_param(phydev, 0x8b5e, 0xffff, 0x0000);
2999 r8168d_phy_param(phydev, 0x8b67, 0xffff, 0x0000);
3000 r8168d_phy_param(phydev, 0x8b70, 0xffff, 0x0000);
0721914a
HK		 3001 r8168d_modify_extpage(phydev, 0x0078, 0x17, 0xffff, 0x0000);
3002 r8168d_modify_extpage(phydev, 0x0078, 0x19, 0xffff, 0x00fb);
c2218925 3003
b5e189b4
HK		 3004 /* Modify green table for 10M */
3005 r8168d_phy_param(phydev, 0x8b79, 0xffff, 0xaa00);
c2218925 3006
b5e189b4
HK		 3007 /* Disable hiimpedance detection (RTCT) */
3008 phy_write_paged(phydev, 0x0003, 0x01, 0x328a);
c2218925 3009
5f886e08 3010 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3011
3012 /* Improve 2-pair detection performance */
b5e189b4 3013 r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000);
c2218925
HW		 3014}
3015
3016static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3017{
3018 rtl_apply_firmware(tp);
3019
5f886e08 3020 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3021}
3022
b3d7b2f2
HW		 3023static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3024{
b5e189b4 3025 struct phy_device *phydev = tp->phydev;
b3d7b2f2
HW		 3026
3027 rtl_apply_firmware(tp);
3028
3029 rtl8168f_hw_phy_config(tp);
3030
3031 /* Improve 2-pair detection performance */
b5e189b4 3032 r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000);
b3d7b2f2 3033
b5e189b4
HK		 3034 /* Channel estimation fine tune */
3035 phy_write_paged(phydev, 0x0003, 0x09, 0xa20f);
3036
3037 /* Modify green table for giga & fnet */
3038 r8168d_phy_param(phydev, 0x8b55, 0xffff, 0x0000);
3039 r8168d_phy_param(phydev, 0x8b5e, 0xffff, 0x0000);
3040 r8168d_phy_param(phydev, 0x8b67, 0xffff, 0x0000);
3041 r8168d_phy_param(phydev, 0x8b70, 0xffff, 0x0000);
0721914a
HK		 3042 r8168d_modify_extpage(phydev, 0x0078, 0x17, 0xffff, 0x0000);
3043 r8168d_modify_extpage(phydev, 0x0078, 0x19, 0xffff, 0x00aa);
b5e189b4
HK		 3044
3045 /* Modify green table for 10M */
3046 r8168d_phy_param(phydev, 0x8b79, 0xffff, 0xaa00);
3047
3048 /* Disable hiimpedance detection (RTCT) */
3049 phy_write_paged(phydev, 0x0003, 0x01, 0x328a);
b3d7b2f2
HW		 3050
3051 /* Modify green table for giga */
b5e189b4
HK		 3052 r8168d_phy_param(phydev, 0x8b54, 0x0800, 0x0000);
3053 r8168d_phy_param(phydev, 0x8b5d, 0x0800, 0x0000);
3054 r8168d_phy_param(phydev, 0x8a7c, 0x0100, 0x0000);
3055 r8168d_phy_param(phydev, 0x8a7f, 0x0000, 0x0100);
3056 r8168d_phy_param(phydev, 0x8a82, 0x0100, 0x0000);
3057 r8168d_phy_param(phydev, 0x8a85, 0x0100, 0x0000);
3058 r8168d_phy_param(phydev, 0x8a88, 0x0100, 0x0000);
b3d7b2f2
HW		 3059
3060 /* uc same-seed solution */
b5e189b4 3061 r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x8000);
b3d7b2f2 3062
b3d7b2f2
HW		 3063 /* Green feature */
3064 rtl_writephy(tp, 0x1f, 0x0003);
76564428
CHL		 3065 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3066 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
b3d7b2f2
HW		 3067 rtl_writephy(tp, 0x1f, 0x0000);
3068}
3069
c46863ab
HK		 3070static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3071{
a2928d28 3072 phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0);
c46863ab
HK		 3073}
3074
a1ead2ec
HK		 3075static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3076{
3077 struct phy_device *phydev = tp->phydev;
3078
a2928d28
HK		 3079 phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0);
3080 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6));
8bfdce1d
HK		 3081 r8168g_phy_param(phydev, 0x8084, 0x6000, 0x0000);
3082 phy_modify_paged(phydev, 0x0a43, 0x10, 0x0000, 0x1003);
a1ead2ec
HK		 3083}
3084
c558386b
HW		 3085static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3086{
a2928d28
HK		 3087 int ret;
3088
c558386b
HW		 3089 rtl_apply_firmware(tp);
3090
a2928d28
HK		 3091 ret = phy_read_paged(tp->phydev, 0x0a46, 0x10);
3092 if (ret & BIT(8))
3093 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0);
3094 else
3095 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15));
c558386b 3096
a2928d28
HK		 3097 ret = phy_read_paged(tp->phydev, 0x0a46, 0x13);
3098 if (ret & BIT(8))
1a03bb53 3099 phy_modify_paged(tp->phydev, 0x0c41, 0x15, 0, BIT(1));
a2928d28 3100 else
1a03bb53 3101 phy_modify_paged(tp->phydev, 0x0c41, 0x15, BIT(1), 0);
c558386b 3102
41f44d13 3103 /* Enable PHY auto speed down */
a2928d28 3104 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
c558386b 3105
a1ead2ec 3106 rtl8168g_phy_adjust_10m_aldps(tp);
fe7524c0 3107
41f44d13 3108 /* EEE auto-fallback function */
a2928d28 3109 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
c558386b 3110
41f44d13 3111 /* Enable UC LPF tune function */
8bfdce1d 3112 r8168g_phy_param(tp->phydev, 0x8012, 0x0000, 0x8000);
41f44d13 3113
a2928d28 3114 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
41f44d13 3115
fe7524c0 3116 /* Improve SWR Efficiency */
3117 rtl_writephy(tp, 0x1f, 0x0bcd);
3118 rtl_writephy(tp, 0x14, 0x5065);
3119 rtl_writephy(tp, 0x14, 0xd065);
3120 rtl_writephy(tp, 0x1f, 0x0bc8);
3121 rtl_writephy(tp, 0x11, 0x5655);
3122 rtl_writephy(tp, 0x1f, 0x0bcd);
3123 rtl_writephy(tp, 0x14, 0x1065);
3124 rtl_writephy(tp, 0x14, 0x9065);
3125 rtl_writephy(tp, 0x14, 0x1065);
a2928d28 3126 rtl_writephy(tp, 0x1f, 0x0000);
fe7524c0 3127
c46863ab 3128 rtl8168g_disable_aldps(tp);
df6f1856 3129 rtl8168g_config_eee_phy(tp);
b6c7fa40 3130 rtl_enable_eee(tp);
c558386b
HW		 3131}
3132
57538c4a 3133static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3134{
3135 rtl_apply_firmware(tp);
df6f1856 3136 rtl8168g_config_eee_phy(tp);
b6c7fa40 3137 rtl_enable_eee(tp);
57538c4a 3138}
3139
6e1d0b89
CHL		 3140static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3141{
8bfdce1d 3142 struct phy_device *phydev = tp->phydev;
6e1d0b89
CHL		 3143 u16 dout_tapbin;
3144 u32 data;
3145
3146 rtl_apply_firmware(tp);
3147
3148 /* CHN EST parameters adjust - giga master */
8bfdce1d
HK		 3149 r8168g_phy_param(phydev, 0x809b, 0xf800, 0x8000);
3150 r8168g_phy_param(phydev, 0x80a2, 0xff00, 0x8000);
3151 r8168g_phy_param(phydev, 0x80a4, 0xff00, 0x8500);
3152 r8168g_phy_param(phydev, 0x809c, 0xff00, 0xbd00);
6e1d0b89
CHL		 3153
3154 /* CHN EST parameters adjust - giga slave */
8bfdce1d
HK		 3155 r8168g_phy_param(phydev, 0x80ad, 0xf800, 0x7000);
3156 r8168g_phy_param(phydev, 0x80b4, 0xff00, 0x5000);
3157 r8168g_phy_param(phydev, 0x80ac, 0xff00, 0x4000);
6e1d0b89
CHL		 3158
3159 /* CHN EST parameters adjust - fnet */
8bfdce1d
HK		 3160 r8168g_phy_param(phydev, 0x808e, 0xff00, 0x1200);
3161 r8168g_phy_param(phydev, 0x8090, 0xff00, 0xe500);
3162 r8168g_phy_param(phydev, 0x8092, 0xff00, 0x9f00);
6e1d0b89
CHL		 3163
3164 /* enable R-tune & PGA-retune function */
3165 dout_tapbin = 0;
8bfdce1d 3166 data = phy_read_paged(phydev, 0x0a46, 0x13);
6e1d0b89
CHL		 3167 data &= 3;
3168 data <<= 2;
3169 dout_tapbin |= data;
8bfdce1d 3170 data = phy_read_paged(phydev, 0x0a46, 0x12);
6e1d0b89
CHL		 3171 data &= 0xc000;
3172 data >>= 14;
3173 dout_tapbin |= data;
3174 dout_tapbin = ~(dout_tapbin^0x08);
3175 dout_tapbin <<= 12;
3176 dout_tapbin &= 0xf000;
8bfdce1d
HK		 3177
3178 r8168g_phy_param(phydev, 0x827a, 0xf000, dout_tapbin);
3179 r8168g_phy_param(phydev, 0x827b, 0xf000, dout_tapbin);
3180 r8168g_phy_param(phydev, 0x827c, 0xf000, dout_tapbin);
3181 r8168g_phy_param(phydev, 0x827d, 0xf000, dout_tapbin);
3182 r8168g_phy_param(phydev, 0x0811, 0x0000, 0x0800);
3183 phy_modify_paged(phydev, 0x0a42, 0x16, 0x0000, 0x0002);
6e1d0b89
CHL		 3184
3185 /* enable GPHY 10M */
a2928d28 3186 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
6e1d0b89
CHL		 3187
3188 /* SAR ADC performance */
a2928d28 3189 phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14));
6e1d0b89 3190
8bfdce1d
HK		 3191 r8168g_phy_param(phydev, 0x803f, 0x3000, 0x0000);
3192 r8168g_phy_param(phydev, 0x8047, 0x3000, 0x0000);
3193 r8168g_phy_param(phydev, 0x804f, 0x3000, 0x0000);
3194 r8168g_phy_param(phydev, 0x8057, 0x3000, 0x0000);
3195 r8168g_phy_param(phydev, 0x805f, 0x3000, 0x0000);
3196 r8168g_phy_param(phydev, 0x8067, 0x3000, 0x0000);
3197 r8168g_phy_param(phydev, 0x806f, 0x3000, 0x0000);
6e1d0b89
CHL		 3198
3199 /* disable phy pfm mode */
a2928d28 3200 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
6e1d0b89 3201
c46863ab 3202 rtl8168g_disable_aldps(tp);
b6cef26f 3203 rtl8168h_config_eee_phy(tp);
b6c7fa40 3204 rtl_enable_eee(tp);
6e1d0b89
CHL		 3205}
3206
3207static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3208{
3209 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
8bfdce1d 3210 struct phy_device *phydev = tp->phydev;
6e1d0b89
CHL		 3211 u16 rlen;
3212 u32 data;
3213
3214 rtl_apply_firmware(tp);
3215
3216 /* CHIN EST parameter update */
8bfdce1d 3217 r8168g_phy_param(phydev, 0x808a, 0x003f, 0x000a);
6e1d0b89
CHL		 3218
3219 /* enable R-tune & PGA-retune function */
8bfdce1d
HK		 3220 r8168g_phy_param(phydev, 0x0811, 0x0000, 0x0800);
3221 phy_modify_paged(phydev, 0x0a42, 0x16, 0x0000, 0x0002);
6e1d0b89
CHL		 3222
3223 /* enable GPHY 10M */
a2928d28 3224 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
6e1d0b89
CHL		 3225
3226 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3227 data = r8168_mac_ocp_read(tp, 0xdd02);
3228 ioffset_p3 = ((data & 0x80)>>7);
3229 ioffset_p3 <<= 3;
3230
3231 data = r8168_mac_ocp_read(tp, 0xdd00);
3232 ioffset_p3 |= ((data & (0xe000))>>13);
3233 ioffset_p2 = ((data & (0x1e00))>>9);
3234 ioffset_p1 = ((data & (0x01e0))>>5);
3235 ioffset_p0 = ((data & 0x0010)>>4);
3236 ioffset_p0 <<= 3;
3237 ioffset_p0 |= (data & (0x07));
3238 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3239
05b9687b 3240 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
8bfdce1d
HK		 3241 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f))
3242 phy_write_paged(phydev, 0x0bcf, 0x16, data);
6e1d0b89
CHL		 3243
3244 /* Modify rlen (TX LPF corner frequency) level */
8bfdce1d 3245 data = phy_read_paged(phydev, 0x0bcd, 0x16);
6e1d0b89
CHL		 3246 data &= 0x000f;
3247 rlen = 0;
3248 if (data > 3)
3249 rlen = data - 3;
3250 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
8bfdce1d 3251 phy_write_paged(phydev, 0x0bcd, 0x17, data);
6e1d0b89
CHL		 3252
3253 /* disable phy pfm mode */
8bfdce1d 3254 phy_modify_paged(phydev, 0x0a44, 0x11, BIT(7), 0);
6e1d0b89 3255
c46863ab 3256 rtl8168g_disable_aldps(tp);
df6f1856 3257 rtl8168g_config_eee_phy(tp);
b6c7fa40 3258 rtl_enable_eee(tp);
6e1d0b89
CHL		 3259}
3260
935e2218
CHL		 3261static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3262{
8bfdce1d
HK		 3263 struct phy_device *phydev = tp->phydev;
3264
935e2218 3265 /* Enable PHY auto speed down */
8bfdce1d 3266 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
935e2218 3267
a1ead2ec 3268 rtl8168g_phy_adjust_10m_aldps(tp);
935e2218
CHL		 3269
3270 /* Enable EEE auto-fallback function */
8bfdce1d 3271 phy_modify_paged(phydev, 0x0a4b, 0x11, 0, BIT(2));
935e2218
CHL		 3272
3273 /* Enable UC LPF tune function */
8bfdce1d 3274 r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000);
935e2218
CHL		 3275
3276 /* set rg_sel_sdm_rate */
8bfdce1d 3277 phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14));
935e2218 3278
c46863ab 3279 rtl8168g_disable_aldps(tp);
df6f1856 3280 rtl8168g_config_eee_phy(tp);
b6c7fa40 3281 rtl_enable_eee(tp);
935e2218
CHL		 3282}
3283
3284static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3285{
8bfdce1d
HK		 3286 struct phy_device *phydev = tp->phydev;
3287
a1ead2ec 3288 rtl8168g_phy_adjust_10m_aldps(tp);
935e2218
CHL		 3289
3290 /* Enable UC LPF tune function */
8bfdce1d 3291 r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000);
935e2218
CHL		 3292
3293 /* Set rg_sel_sdm_rate */
a2928d28 3294 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
935e2218
CHL		 3295
3296 /* Channel estimation parameters */
8bfdce1d
HK		 3297 r8168g_phy_param(phydev, 0x80f3, 0xff00, 0x8b00);
3298 r8168g_phy_param(phydev, 0x80f0, 0xff00, 0x3a00);
3299 r8168g_phy_param(phydev, 0x80ef, 0xff00, 0x0500);
3300 r8168g_phy_param(phydev, 0x80f6, 0xff00, 0x6e00);
3301 r8168g_phy_param(phydev, 0x80ec, 0xff00, 0x6800);
3302 r8168g_phy_param(phydev, 0x80ed, 0xff00, 0x7c00);
3303 r8168g_phy_param(phydev, 0x80f2, 0xff00, 0xf400);
3304 r8168g_phy_param(phydev, 0x80f4, 0xff00, 0x8500);
3305 r8168g_phy_param(phydev, 0x8110, 0xff00, 0xa800);
3306 r8168g_phy_param(phydev, 0x810f, 0xff00, 0x1d00);
3307 r8168g_phy_param(phydev, 0x8111, 0xff00, 0xf500);
3308 r8168g_phy_param(phydev, 0x8113, 0xff00, 0x6100);
3309 r8168g_phy_param(phydev, 0x8115, 0xff00, 0x9200);
3310 r8168g_phy_param(phydev, 0x810e, 0xff00, 0x0400);
3311 r8168g_phy_param(phydev, 0x810c, 0xff00, 0x7c00);
3312 r8168g_phy_param(phydev, 0x810b, 0xff00, 0x5a00);
3313 r8168g_phy_param(phydev, 0x80d1, 0xff00, 0xff00);
3314 r8168g_phy_param(phydev, 0x80cd, 0xff00, 0x9e00);
3315 r8168g_phy_param(phydev, 0x80d3, 0xff00, 0x0e00);
3316 r8168g_phy_param(phydev, 0x80d5, 0xff00, 0xca00);
3317 r8168g_phy_param(phydev, 0x80d7, 0xff00, 0x8400);
935e2218
CHL		 3318
3319 /* Force PWM-mode */
3320 rtl_writephy(tp, 0x1f, 0x0bcd);
3321 rtl_writephy(tp, 0x14, 0x5065);
3322 rtl_writephy(tp, 0x14, 0xd065);
3323 rtl_writephy(tp, 0x1f, 0x0bc8);
3324 rtl_writephy(tp, 0x12, 0x00ed);
3325 rtl_writephy(tp, 0x1f, 0x0bcd);
3326 rtl_writephy(tp, 0x14, 0x1065);
3327 rtl_writephy(tp, 0x14, 0x9065);
3328 rtl_writephy(tp, 0x14, 0x1065);
3329 rtl_writephy(tp, 0x1f, 0x0000);
3330
c46863ab 3331 rtl8168g_disable_aldps(tp);
df6f1856 3332 rtl8168g_config_eee_phy(tp);
b6c7fa40 3333 rtl_enable_eee(tp);
935e2218
CHL		 3334}
3335
1287723a
HK		 3336static void rtl8117_hw_phy_config(struct rtl8169_private *tp)
3337{
3338 struct phy_device *phydev = tp->phydev;
3339
3340 /* CHN EST parameters adjust - fnet */
3341 r8168g_phy_param(phydev, 0x808e, 0xff00, 0x4800);
3342 r8168g_phy_param(phydev, 0x8090, 0xff00, 0xcc00);
3343 r8168g_phy_param(phydev, 0x8092, 0xff00, 0xb000);
3344
3345 r8168g_phy_param(phydev, 0x8088, 0xff00, 0x6000);
3346 r8168g_phy_param(phydev, 0x808b, 0x3f00, 0x0b00);
3347 r8168g_phy_param(phydev, 0x808d, 0x1f00, 0x0600);
3348 r8168g_phy_param(phydev, 0x808c, 0xff00, 0xb000);
3349 r8168g_phy_param(phydev, 0x80a0, 0xff00, 0x2800);
3350 r8168g_phy_param(phydev, 0x80a2, 0xff00, 0x5000);
3351 r8168g_phy_param(phydev, 0x809b, 0xf800, 0xb000);
3352 r8168g_phy_param(phydev, 0x809a, 0xff00, 0x4b00);
3353 r8168g_phy_param(phydev, 0x809d, 0x3f00, 0x0800);
3354 r8168g_phy_param(phydev, 0x80a1, 0xff00, 0x7000);
3355 r8168g_phy_param(phydev, 0x809f, 0x1f00, 0x0300);
3356 r8168g_phy_param(phydev, 0x809e, 0xff00, 0x8800);
3357 r8168g_phy_param(phydev, 0x80b2, 0xff00, 0x2200);
3358 r8168g_phy_param(phydev, 0x80ad, 0xf800, 0x9800);
3359 r8168g_phy_param(phydev, 0x80af, 0x3f00, 0x0800);
3360 r8168g_phy_param(phydev, 0x80b3, 0xff00, 0x6f00);
3361 r8168g_phy_param(phydev, 0x80b1, 0x1f00, 0x0300);
3362 r8168g_phy_param(phydev, 0x80b0, 0xff00, 0x9300);
3363
3364 r8168g_phy_param(phydev, 0x8011, 0x0000, 0x0800);
3365
3366 /* enable GPHY 10M */
3367 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3368
3369 r8168g_phy_param(phydev, 0x8016, 0x0000, 0x0400);
3370
3371 rtl8168g_disable_aldps(tp);
3372 rtl8168h_config_eee_phy(tp);
3373 rtl_enable_eee(tp);
3374}
3375
4da19633 3376static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3377{
350f7596 3378 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3379 { 0x1f, 0x0003 },
3380 { 0x08, 0x441d },
3381 { 0x01, 0x9100 },
3382 { 0x1f, 0x0000 }
3383 };
3384
4da19633 3385 rtl_writephy(tp, 0x1f, 0x0000);
3386 rtl_patchphy(tp, 0x11, 1 << 12);
3387 rtl_patchphy(tp, 0x19, 1 << 13);
3388 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3389
1791ad50 3390 rtl_writephy_batch(tp, phy_reg_init);
2857ffb7
FR		 3391}
3392
5a5e4443
HW		 3393static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3394{
5a5e4443 3395 /* Disable ALDPS before ram code */
3a129e3f 3396 phy_write(tp->phydev, 0x18, 0x0310);
eef63cc1 3397 msleep(100);
5a5e4443 3398
953a12cc 3399 rtl_apply_firmware(tp);
5a5e4443 3400
3a129e3f
HK		 3401 phy_write_paged(tp->phydev, 0x0005, 0x1a, 0x0000);
3402 phy_write_paged(tp->phydev, 0x0004, 0x1c, 0x0000);
3403 phy_write_paged(tp->phydev, 0x0001, 0x15, 0x7701);
5a5e4443
HW		 3404}
3405
7e18dca1
HW		 3406static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3407{
7e18dca1 3408 /* Disable ALDPS before setting firmware */
3a129e3f 3409 phy_write(tp->phydev, 0x18, 0x0310);
eef63cc1 3410 msleep(20);
7e18dca1
HW		 3411
3412 rtl_apply_firmware(tp);
3413
3414 /* EEE setting */
724c6fd0 3415 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
7e18dca1
HW		 3416 rtl_writephy(tp, 0x1f, 0x0004);
3417 rtl_writephy(tp, 0x10, 0x401f);
3418 rtl_writephy(tp, 0x19, 0x7030);
3419 rtl_writephy(tp, 0x1f, 0x0000);
3420}
3421
5598bfe5
HW		 3422static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3423{
5598bfe5
HW		 3424 static const struct phy_reg phy_reg_init[] = {
3425 { 0x1f, 0x0004 },
3426 { 0x10, 0xc07f },
3427 { 0x19, 0x7030 },
3428 { 0x1f, 0x0000 }
3429 };
3430
3431 /* Disable ALDPS before ram code */
3a129e3f 3432 phy_write(tp->phydev, 0x18, 0x0310);
eef63cc1 3433 msleep(100);
5598bfe5
HW		 3434
3435 rtl_apply_firmware(tp);
3436
724c6fd0 3437 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
1791ad50 3438 rtl_writephy_batch(tp, phy_reg_init);
5598bfe5 3439
724c6fd0 3440 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
5598bfe5
HW		 3441}
3442
02bf642b
HK		 3443static void rtl8125_1_hw_phy_config(struct rtl8169_private *tp)
3444{
3445 struct phy_device *phydev = tp->phydev;
3446
3447 phy_modify_paged(phydev, 0xad4, 0x10, 0x03ff, 0x0084);
3448 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010);
3449 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x0006);
3450 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006);
3451 phy_modify_paged(phydev, 0xac0, 0x14, 0x0000, 0x1100);
3452 phy_modify_paged(phydev, 0xac8, 0x15, 0xf000, 0x7000);
3453 phy_modify_paged(phydev, 0xad1, 0x14, 0x0000, 0x0400);
3454 phy_modify_paged(phydev, 0xad1, 0x15, 0x0000, 0x03ff);
3455 phy_modify_paged(phydev, 0xad1, 0x16, 0x0000, 0x03ff);
3456
8bfdce1d
HK		 3457 r8168g_phy_param(phydev, 0x80ea, 0xff00, 0xc400);
3458 r8168g_phy_param(phydev, 0x80eb, 0x0700, 0x0300);
3459 r8168g_phy_param(phydev, 0x80f8, 0xff00, 0x1c00);
3460 r8168g_phy_param(phydev, 0x80f1, 0xff00, 0x3000);
3461 r8168g_phy_param(phydev, 0x80fe, 0xff00, 0xa500);
3462 r8168g_phy_param(phydev, 0x8102, 0xff00, 0x5000);
3463 r8168g_phy_param(phydev, 0x8105, 0xff00, 0x3300);
3464 r8168g_phy_param(phydev, 0x8100, 0xff00, 0x7000);
3465 r8168g_phy_param(phydev, 0x8104, 0xff00, 0xf000);
3466 r8168g_phy_param(phydev, 0x8106, 0xff00, 0x6500);
3467 r8168g_phy_param(phydev, 0x80dc, 0xff00, 0xed00);
3468 r8168g_phy_param(phydev, 0x80df, 0x0000, 0x0100);
3469 r8168g_phy_param(phydev, 0x80e1, 0x0100, 0x0000);
02bf642b
HK		 3470
3471 phy_modify_paged(phydev, 0xbf0, 0x13, 0x003f, 0x0038);
8bfdce1d 3472 r8168g_phy_param(phydev, 0x819f, 0xffff, 0xd0b6);
02bf642b
HK		 3473
3474 phy_write_paged(phydev, 0xbc3, 0x12, 0x5555);
3475 phy_modify_paged(phydev, 0xbf0, 0x15, 0x0e00, 0x0a00);
3476 phy_modify_paged(phydev, 0xa5c, 0x10, 0x0400, 0x0000);
3477 phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800);
b3a42e3a
HK		 3478
3479 rtl8125_config_eee_phy(tp);
3480 rtl_enable_eee(tp);
02bf642b
HK		 3481}
3482
3483static void rtl8125_2_hw_phy_config(struct rtl8169_private *tp)
3484{
3485 struct phy_device *phydev = tp->phydev;
3486 int i;
3487
3488 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010);
3489 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x03ff);
3490 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006);
3491 phy_modify_paged(phydev, 0xac0, 0x14, 0x1100, 0x0000);
3492 phy_modify_paged(phydev, 0xacc, 0x10, 0x0003, 0x0002);
3493 phy_modify_paged(phydev, 0xad4, 0x10, 0x00e7, 0x0044);
3494 phy_modify_paged(phydev, 0xac1, 0x12, 0x0080, 0x0000);
3495 phy_modify_paged(phydev, 0xac8, 0x10, 0x0300, 0x0000);
3496 phy_modify_paged(phydev, 0xac5, 0x17, 0x0007, 0x0002);
3497 phy_write_paged(phydev, 0xad4, 0x16, 0x00a8);
3498 phy_write_paged(phydev, 0xac5, 0x16, 0x01ff);
3499 phy_modify_paged(phydev, 0xac8, 0x15, 0x00f0, 0x0030);
3500
3501 phy_write(phydev, 0x1f, 0x0b87);
3502 phy_write(phydev, 0x16, 0x80a2);
3503 phy_write(phydev, 0x17, 0x0153);
3504 phy_write(phydev, 0x16, 0x809c);
3505 phy_write(phydev, 0x17, 0x0153);
3506 phy_write(phydev, 0x1f, 0x0000);
3507
3508 phy_write(phydev, 0x1f, 0x0a43);
3509 phy_write(phydev, 0x13, 0x81B3);
3510 phy_write(phydev, 0x14, 0x0043);
3511 phy_write(phydev, 0x14, 0x00A7);
3512 phy_write(phydev, 0x14, 0x00D6);
3513 phy_write(phydev, 0x14, 0x00EC);
3514 phy_write(phydev, 0x14, 0x00F6);
3515 phy_write(phydev, 0x14, 0x00FB);
3516 phy_write(phydev, 0x14, 0x00FD);
3517 phy_write(phydev, 0x14, 0x00FF);
3518 phy_write(phydev, 0x14, 0x00BB);
3519 phy_write(phydev, 0x14, 0x0058);
3520 phy_write(phydev, 0x14, 0x0029);
3521 phy_write(phydev, 0x14, 0x0013);
3522 phy_write(phydev, 0x14, 0x0009);
3523 phy_write(phydev, 0x14, 0x0004);
3524 phy_write(phydev, 0x14, 0x0002);
3525 for (i = 0; i < 25; i++)
3526 phy_write(phydev, 0x14, 0x0000);
02bf642b
HK		 3527 phy_write(phydev, 0x1f, 0x0000);
3528
8bfdce1d
HK		 3529 r8168g_phy_param(phydev, 0x8257, 0xffff, 0x020F);
3530 r8168g_phy_param(phydev, 0x80ea, 0xffff, 0x7843);
3531
02bf642b
HK		 3532 rtl_apply_firmware(tp);
3533
3534 phy_modify_paged(phydev, 0xd06, 0x14, 0x0000, 0x2000);
3535
8bfdce1d 3536 r8168g_phy_param(phydev, 0x81a2, 0x0000, 0x0100);
02bf642b
HK		 3537
3538 phy_modify_paged(phydev, 0xb54, 0x16, 0xff00, 0xdb00);
3539 phy_modify_paged(phydev, 0xa45, 0x12, 0x0001, 0x0000);
3540 phy_modify_paged(phydev, 0xa5d, 0x12, 0x0000, 0x0020);
3541 phy_modify_paged(phydev, 0xad4, 0x17, 0x0010, 0x0000);
3542 phy_modify_paged(phydev, 0xa86, 0x15, 0x0001, 0x0000);
3543 phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800);
b3a42e3a
HK		 3544
3545 rtl8125_config_eee_phy(tp);
3546 rtl_enable_eee(tp);
02bf642b
HK		 3547}
3548
5615d9f1
FR		 3549static void rtl_hw_phy_config(struct net_device *dev)
3550{
1fcd1658
HK		 3551 static const rtl_generic_fct phy_configs[] = {
3552 /* PCI devices. */
1fcd1658
HK		 3553 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3554 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3555 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3556 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3557 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3558 /* PCI-E devices. */
3559 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3560 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3561 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3562 [RTL_GIGA_MAC_VER_10] = NULL,
3563 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
3564 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
3565 [RTL_GIGA_MAC_VER_13] = NULL,
3566 [RTL_GIGA_MAC_VER_14] = NULL,
3567 [RTL_GIGA_MAC_VER_15] = NULL,
3568 [RTL_GIGA_MAC_VER_16] = NULL,
3569 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
3570 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
3571 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
3572 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
3573 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
afa26427 3574 [RTL_GIGA_MAC_VER_22] = rtl8168c_3_hw_phy_config,
1fcd1658
HK		 3575 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
3576 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
3577 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
3578 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
3579 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
3580 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
3581 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
3582 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
3583 [RTL_GIGA_MAC_VER_31] = NULL,
3584 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
3585 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
3586 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
3587 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
3588 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
3589 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
3590 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
3591 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
3592 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
3593 [RTL_GIGA_MAC_VER_41] = NULL,
3594 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
3595 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
3596 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
3597 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
3598 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
3599 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
3600 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
3601 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
3602 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
3603 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
1287723a 3604 [RTL_GIGA_MAC_VER_52] = rtl8117_hw_phy_config,
02bf642b
HK		 3605 [RTL_GIGA_MAC_VER_60] = rtl8125_1_hw_phy_config,
3606 [RTL_GIGA_MAC_VER_61] = rtl8125_2_hw_phy_config,
1fcd1658 3607 };
5615d9f1 3608 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1 3609
1fcd1658
HK		 3610 if (phy_configs[tp->mac_version])
3611 phy_configs[tp->mac_version](tp);
5615d9f1
FR		 3612}
3613
da78dbff
FR		 3614static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3615{
da78dbff
FR		 3616 if (!test_and_set_bit(flag, tp->wk.flags))
3617 schedule_work(&tp->wk.work);
da78dbff
FR		 3618}
3619
4ff96fa6
FR		 3620static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3621{
5615d9f1 3622 rtl_hw_phy_config(dev);
4ff96fa6 3623
77332894 3624 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
7a67e11d
HK		 3625 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3626 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
49d17512
HK		 3627 netif_dbg(tp, drv, dev,
3628 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1ef7286e 3629 RTL_W8(tp, 0x82, 0x01);
77332894 3630 }
4ff96fa6 3631
5b7ad4b7 3632 /* We may have called phy_speed_down before */
703732f0 3633 phy_speed_up(tp->phydev);
5b7ad4b7 3634
703732f0 3635 genphy_soft_reset(tp->phydev);
4ff96fa6
FR		 3636}
3637
773d2021
FR		 3638static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3639{
da78dbff 3640 rtl_lock_work(tp);
773d2021 3641
df320ed7 3642 rtl_unlock_config_regs(tp);
908ba2bf 3643
1ef7286e
AS		 3644 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
3645 RTL_R32(tp, MAC4);
908ba2bf 3646
1ef7286e
AS		 3647 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3648 RTL_R32(tp, MAC0);
908ba2bf 3649
9ecb9aab 3650 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3651 rtl_rar_exgmac_set(tp, addr);
c28aa385 3652
df320ed7 3653 rtl_lock_config_regs(tp);
773d2021 3654
da78dbff 3655 rtl_unlock_work(tp);
773d2021
FR		 3656}
3657
3658static int rtl_set_mac_address(struct net_device *dev, void *p)
3659{
3660 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 3661 struct device *d = tp_to_dev(tp);
1f7aa2bc 3662 int ret;
773d2021 3663
1f7aa2bc
HK		 3664 ret = eth_mac_addr(dev, p);
3665 if (ret)
3666 return ret;
773d2021 3667
f51d4a10
CHL		 3668 pm_runtime_get_noresume(d);
3669
3670 if (pm_runtime_active(d))
3671 rtl_rar_set(tp, dev->dev_addr);
3672
3673 pm_runtime_put_noidle(d);
773d2021
FR		 3674
3675 return 0;
3676}
3677
e397286b 3678static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8b4ab28d 3679{
703732f0
HK		 3680 struct rtl8169_private *tp = netdev_priv(dev);
3681
69b3c59f
HK		 3682 if (!netif_running(dev))
3683 return -ENODEV;
e397286b 3684
703732f0 3685 return phy_mii_ioctl(tp->phydev, ifr, cmd);
8b4ab28d
FR		 3686}
3687
649b3b8c 3688static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3689{
649b3b8c 3690 switch (tp->mac_version) {
b00e69de
CB		 3691 case RTL_GIGA_MAC_VER_25:
3692 case RTL_GIGA_MAC_VER_26:
649b3b8c 3693 case RTL_GIGA_MAC_VER_29:
3694 case RTL_GIGA_MAC_VER_30:
3695 case RTL_GIGA_MAC_VER_32:
3696 case RTL_GIGA_MAC_VER_33:
3697 case RTL_GIGA_MAC_VER_34:
00222d13 3698 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_61:
1ef7286e 3699 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
649b3b8c 3700 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3701 break;
3702 default:
3703 break;
3704 }
3705}
3706
25e94115 3707static void rtl_pll_power_down(struct rtl8169_private *tp)
065c27c1 3708{
9dbe7896 3709 if (r8168_check_dash(tp))
065c27c1 3710 return;
3711
01dc7fec 3712 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3713 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 3714 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 3715
5ea25b12
HK		 3716 if (device_may_wakeup(tp_to_dev(tp))) {
3717 phy_speed_down(tp->phydev, false);
3718 rtl_wol_suspend_quirk(tp);
065c27c1 3719 return;
5ea25b12 3720 }
065c27c1 3721
065c27c1 3722 switch (tp->mac_version) {
2a71883c 3723 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
73570bf1
HK		 3724 case RTL_GIGA_MAC_VER_37:
3725 case RTL_GIGA_MAC_VER_39:
3726 case RTL_GIGA_MAC_VER_43:
42fde737 3727 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 3728 case RTL_GIGA_MAC_VER_45:
3729 case RTL_GIGA_MAC_VER_46:
73570bf1
HK		 3730 case RTL_GIGA_MAC_VER_47:
3731 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 3732 case RTL_GIGA_MAC_VER_50:
3733 case RTL_GIGA_MAC_VER_51:
1287723a 3734 case RTL_GIGA_MAC_VER_52:
f1bce4ad
HK		 3735 case RTL_GIGA_MAC_VER_60:
3736 case RTL_GIGA_MAC_VER_61:
1ef7286e 3737 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
065c27c1 3738 break;
beb330a4 3739 case RTL_GIGA_MAC_VER_40:
3740 case RTL_GIGA_MAC_VER_41:
935e2218 3741 case RTL_GIGA_MAC_VER_49:
e719b3ea 3742 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
1ef7286e 3743 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
beb330a4 3744 break;
76719ee2
HK		 3745 default:
3746 break;
065c27c1 3747 }
3748}
3749
25e94115 3750static void rtl_pll_power_up(struct rtl8169_private *tp)
065c27c1 3751{
065c27c1 3752 switch (tp->mac_version) {
2a71883c 3753 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
73570bf1
HK		 3754 case RTL_GIGA_MAC_VER_37:
3755 case RTL_GIGA_MAC_VER_39:
3756 case RTL_GIGA_MAC_VER_43:
1ef7286e 3757 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
065c27c1 3758 break;
42fde737 3759 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 3760 case RTL_GIGA_MAC_VER_45:
3761 case RTL_GIGA_MAC_VER_46:
73570bf1
HK		 3762 case RTL_GIGA_MAC_VER_47:
3763 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 3764 case RTL_GIGA_MAC_VER_50:
3765 case RTL_GIGA_MAC_VER_51:
1287723a 3766 case RTL_GIGA_MAC_VER_52:
f1bce4ad
HK		 3767 case RTL_GIGA_MAC_VER_60:
3768 case RTL_GIGA_MAC_VER_61:
1ef7286e 3769 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
6e1d0b89 3770 break;
beb330a4 3771 case RTL_GIGA_MAC_VER_40:
3772 case RTL_GIGA_MAC_VER_41:
935e2218 3773 case RTL_GIGA_MAC_VER_49:
1ef7286e 3774 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
e719b3ea 3775 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
beb330a4 3776 break;
76719ee2
HK		 3777 default:
3778 break;
065c27c1 3779 }
3780
703732f0 3781 phy_resume(tp->phydev);
242cd9b5
HK		 3782 /* give MAC/PHY some time to resume */
3783 msleep(20);
065c27c1 3784}
3785
e542a226
HW		 3786static void rtl_init_rxcfg(struct rtl8169_private *tp)
3787{
e542a226 3788 switch (tp->mac_version) {
e9588eb9 3789 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2a71883c 3790 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
1ef7286e 3791 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
e542a226 3792 break;
2a71883c 3793 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
511cfd58
MS		 3794 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
3795 case RTL_GIGA_MAC_VER_38:
1ef7286e 3796 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
e542a226 3797 break;
1287723a 3798 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
1ef7286e 3799 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
beb330a4 3800 break;
f1bce4ad
HK		 3801 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
3802 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_VLAN_8125 |
3803 RX_DMA_BURST);
3804 break;
e542a226 3805 default:
1ef7286e 3806 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
e542a226
HW		 3807 break;
3808 }
3809}
3810
92fc43b4
HW		 3811static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3812{
9fba0812 3813 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 3814}
3815
d58d46b5
FR		 3816static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3817{
1ef7286e
AS		 3818 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3819 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
d58d46b5
FR		 3820}
3821
3822static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3823{
1ef7286e
AS		 3824 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3825 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
d58d46b5
FR		 3826}
3827
3828static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3829{
1ef7286e 3830 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
d58d46b5
FR		 3831}
3832
3833static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3834{
1ef7286e 3835 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
d58d46b5
FR		 3836}
3837
3838static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3839{
1ef7286e
AS		 3840 RTL_W8(tp, MaxTxPacketSize, 0x3f);
3841 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3842 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
d58d46b5
FR		 3843}
3844
3845static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3846{
1ef7286e
AS		 3847 RTL_W8(tp, MaxTxPacketSize, 0x0c);
3848 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3849 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
d58d46b5
FR		 3850}
3851
d58d46b5
FR		 3852static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3853{
1ef7286e 3854 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
d58d46b5
FR		 3855}
3856
3857static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3858{
1ef7286e 3859 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
d58d46b5
FR		 3860}
3861
485bb1b3 3862static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
d58d46b5 3863{
485bb1b3 3864 rtl_unlock_config_regs(tp);
d58d46b5 3865 switch (tp->mac_version) {
d58d46b5
FR		 3866 case RTL_GIGA_MAC_VER_12:
3867 case RTL_GIGA_MAC_VER_17:
485bb1b3 3868 r8168b_1_hw_jumbo_enable(tp);
d58d46b5 3869 break;
485bb1b3
HK		 3870 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
3871 r8168c_hw_jumbo_enable(tp);
d58d46b5 3872 break;
485bb1b3
HK		 3873 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
3874 r8168dp_hw_jumbo_enable(tp);
d58d46b5 3875 break;
14012c9f 3876 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
485bb1b3
HK		 3877 r8168e_hw_jumbo_enable(tp);
3878 break;
3879 default:
d58d46b5 3880 break;
485bb1b3
HK		 3881 }
3882 rtl_lock_config_regs(tp);
3883}
d58d46b5 3884
485bb1b3
HK		 3885static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3886{
3887 rtl_unlock_config_regs(tp);
3888 switch (tp->mac_version) {
485bb1b3
HK		 3889 case RTL_GIGA_MAC_VER_12:
3890 case RTL_GIGA_MAC_VER_17:
3891 r8168b_1_hw_jumbo_disable(tp);
3892 break;
3893 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
3894 r8168c_hw_jumbo_disable(tp);
3895 break;
3896 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
3897 r8168dp_hw_jumbo_disable(tp);
3898 break;
0fc75219 3899 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
485bb1b3
HK		 3900 r8168e_hw_jumbo_disable(tp);
3901 break;
d58d46b5 3902 default:
d58d46b5
FR		 3903 break;
3904 }
485bb1b3 3905 rtl_lock_config_regs(tp);
d58d46b5
FR		 3906}
3907
4ebcb113
HK		 3908static void rtl_jumbo_config(struct rtl8169_private *tp, int mtu)
3909{
3910 if (mtu > ETH_DATA_LEN)
3911 rtl_hw_jumbo_enable(tp);
3912 else
3913 rtl_hw_jumbo_disable(tp);
3914}
3915
ffc46952
FR		 3916DECLARE_RTL_COND(rtl_chipcmd_cond)
3917{
1ef7286e 3918 return RTL_R8(tp, ChipCmd) & CmdReset;
ffc46952
FR		 3919}
3920
6f43adc8
FR		 3921static void rtl_hw_reset(struct rtl8169_private *tp)
3922{
1ef7286e 3923 RTL_W8(tp, ChipCmd, CmdReset);
6f43adc8 3924
ffc46952 3925 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 3926}
3927
254764e5 3928static void rtl_request_firmware(struct rtl8169_private *tp)
953a12cc 3929{
b6ffd97f 3930 struct rtl_fw *rtl_fw;
953a12cc 3931
254764e5
HK		 3932 /* firmware loaded already or no firmware available */
3933 if (tp->rtl_fw || !tp->fw_name)
3934 return;
953a12cc 3935
b6ffd97f 3936 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
47ad5931
HK		 3937 if (!rtl_fw) {
3938 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n");
3939 return;
3940 }
31bd204f 3941
ce8843ab
HK		 3942 rtl_fw->phy_write = rtl_writephy;
3943 rtl_fw->phy_read = rtl_readphy;
3944 rtl_fw->mac_mcu_write = mac_mcu_write;
3945 rtl_fw->mac_mcu_read = mac_mcu_read;
4edb00f3
HK		 3946 rtl_fw->fw_name = tp->fw_name;
3947 rtl_fw->dev = tp_to_dev(tp);
ce8843ab 3948
47ad5931
HK		 3949 if (rtl_fw_request_firmware(rtl_fw))
3950 kfree(rtl_fw);
3951 else
3952 tp->rtl_fw = rtl_fw;
953a12cc
FR		 3953}
3954
92fc43b4
HW		 3955static void rtl_rx_close(struct rtl8169_private *tp)
3956{
1ef7286e 3957 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 3958}
3959
ffc46952
FR		 3960DECLARE_RTL_COND(rtl_npq_cond)
3961{
1ef7286e 3962 return RTL_R8(tp, TxPoll) & NPQ;
ffc46952
FR		 3963}
3964
3965DECLARE_RTL_COND(rtl_txcfg_empty_cond)
3966{
1ef7286e 3967 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
ffc46952
FR		 3968}
3969
e6de30d6 3970static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4
LT		 3971{
3972 /* Disable interrupts */
811fd301 3973 rtl8169_irq_mask_and_ack(tp);
1da177e4 3974
92fc43b4
HW		 3975 rtl_rx_close(tp);
3976
b2d43e6e
HK		 3977 switch (tp->mac_version) {
3978 case RTL_GIGA_MAC_VER_27:
3979 case RTL_GIGA_MAC_VER_28:
3980 case RTL_GIGA_MAC_VER_31:
ffc46952 3981 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
b2d43e6e
HK		 3982 break;
3983 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1287723a 3984 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
1ef7286e 3985 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
ffc46952 3986 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
b2d43e6e
HK		 3987 break;
3988 default:
1ef7286e 3989 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
92fc43b4 3990 udelay(100);
b2d43e6e 3991 break;
e6de30d6 3992 }
3993
92fc43b4 3994 rtl_hw_reset(tp);
1da177e4
LT		 3995}
3996
05212ba8 3997static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
9cb427b6 3998{
ad5f97fa
HK		 3999 u32 val = TX_DMA_BURST << TxDMAShift |
4000 InterFrameGap << TxInterFrameGapShift;
4001
9e9f33ba 4002 if (rtl_is_8168evl_up(tp))
ad5f97fa
HK		 4003 val |= TXCFG_AUTO_FIFO;
4004
4005 RTL_W32(tp, TxConfig, val);
9cb427b6
FR		 4006}
4007
4fd48c4a 4008static void rtl_set_rx_max_size(struct rtl8169_private *tp)
1da177e4 4009{
4fd48c4a
HK		 4010 /* Low hurts. Let's disable the filtering. */
4011 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
07ce4064
FR		 4012}
4013
1ef7286e 4014static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
7f796d83
FR		 4015{
4016 /*
4017 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4018 * register to be written before TxDescAddrLow to work.
4019 * Switching from MMIO to I/O access fixes the issue as well.
4020 */
1ef7286e
AS		 4021 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4022 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4023 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4024 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4025}
4026
1ef7286e 4027static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
6dccd16b 4028{
34bc0095
HK		 4029 u32 val;
4030
4031 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4032 val = 0x000fff00;
4033 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4034 val = 0x00ffff00;
4035 else
4036 return;
4037
4038 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4039 val |= 0xff;
4040
4041 RTL_W32(tp, 0x7c, val);
6dccd16b
FR		 4042}
4043
e6b763ea
FR		 4044static void rtl_set_rx_mode(struct net_device *dev)
4045{
81cd17a4
HK		 4046 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
4047 /* Multicast hash filter */
4048 u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
e6b763ea 4049 struct rtl8169_private *tp = netdev_priv(dev);
81cd17a4 4050 u32 tmp;
e6b763ea
FR		 4051
4052 if (dev->flags & IFF_PROMISC) {
4053 /* Unconditionally log net taps. */
4054 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
81cd17a4
HK		 4055 rx_mode |= AcceptAllPhys;
4056 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
4057 dev->flags & IFF_ALLMULTI ||
4058 tp->mac_version == RTL_GIGA_MAC_VER_35) {
4059 /* accept all multicasts */
4060 } else if (netdev_mc_empty(dev)) {
4061 rx_mode &= ~AcceptMulticast;
e6b763ea
FR		 4062 } else {
4063 struct netdev_hw_addr *ha;
4064
e6b763ea
FR		 4065 mc_filter[1] = mc_filter[0] = 0;
4066 netdev_for_each_mc_addr(ha, dev) {
81cd17a4
HK		 4067 u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4068 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
4069 }
4070
4071 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4072 tmp = mc_filter[0];
4073 mc_filter[0] = swab32(mc_filter[1]);
4074 mc_filter[1] = swab32(tmp);
e6b763ea
FR		 4075 }
4076 }
4077
4078 if (dev->features & NETIF_F_RXALL)
4079 rx_mode |= (AcceptErr | AcceptRunt);
4080
1ef7286e
AS		 4081 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4082 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
e6b763ea 4083
81cd17a4
HK		 4084 tmp = RTL_R32(tp, RxConfig);
4085 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_MASK) | rx_mode);
e6b763ea
FR		 4086}
4087
ffc46952
FR		 4088DECLARE_RTL_COND(rtl_csiar_cond)
4089{
1ef7286e 4090 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
ffc46952
FR		 4091}
4092
ff1d7331 4093static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
beb1fe18 4094{
ff1d7331 4095 u32 func = PCI_FUNC(tp->pci_dev->devfn);
beb1fe18 4096
1ef7286e
AS		 4097 RTL_W32(tp, CSIDR, value);
4098 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
ff1d7331 4099 CSIAR_BYTE_ENABLE | func << 16);
7e18dca1 4100
ffc46952 4101 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 4102}
4103
ff1d7331 4104static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 4105{
ff1d7331
HK		 4106 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4107
4108 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4109 CSIAR_BYTE_ENABLE);
7e18dca1 4110
ffc46952 4111 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
1ef7286e 4112 RTL_R32(tp, CSIDR) : ~0;
7e18dca1
HW		 4113}
4114
ff1d7331 4115static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
45dd95c4 4116{
ff1d7331
HK		 4117 struct pci_dev *pdev = tp->pci_dev;
4118 u32 csi;
45dd95c4 4119
ff1d7331
HK		 4120 /* According to Realtek the value at config space address 0x070f
4121 * controls the L0s/L1 entrance latency. We try standard ECAM access
4122 * first and if it fails fall back to CSI.
4123 */
4124 if (pdev->cfg_size > 0x070f &&
4125 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4126 return;
4127
4128 netdev_notice_once(tp->dev,
4129 "No native access to PCI extended config space, falling back to CSI\n");
4130 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4131 rtl_csi_write(tp, 0x070c, csi | val << 24);
45dd95c4 4132}
4133
f37658da 4134static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
beb1fe18 4135{
ff1d7331 4136 rtl_csi_access_enable(tp, 0x27);
dacf8154
FR		 4137}
4138
4139struct ephy_info {
4140 unsigned int offset;
4141 u16 mask;
4142 u16 bits;
4143};
4144
1791ad50
HK		 4145static void __rtl_ephy_init(struct rtl8169_private *tp,
4146 const struct ephy_info *e, int len)
dacf8154
FR		 4147{
4148 u16 w;
4149
4150 while (len-- > 0) {
fdf6fc06
FR		 4151 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4152 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 4153 e++;
4154 }
4155}
4156
1791ad50
HK		 4157#define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4158
73c86ee3 4159static void rtl_disable_clock_request(struct rtl8169_private *tp)
b726e493 4160{
73c86ee3 4161 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 4162 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 4163}
4164
73c86ee3 4165static void rtl_enable_clock_request(struct rtl8169_private *tp)
e6de30d6 4166{
73c86ee3 4167 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 4168 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 4169}
4170
c259b7f4 4171static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
b51ecea8 4172{
c259b7f4
HK		 4173 /* work around an issue when PCI reset occurs during L2/L3 state */
4174 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
b51ecea8 4175}
4176
a99790bf
KHF		 4177static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4178{
62b1b3b3
HK		 4179 /* Don't enable ASPM in the chip if OS can't control ASPM */
4180 if (enable && tp->aspm_manageable) {
a99790bf 4181 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
94235460 4182 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
a99790bf
KHF		 4183 } else {
4184 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4185 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4186 }
94235460
KHF		 4187
4188 udelay(10);
a99790bf
KHF		 4189}
4190
6b1bd242
HK		 4191static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4192 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4193{
4194 /* Usage of dynamic vs. static FIFO is controlled by bit
4195 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4196 */
4197 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4198 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4199}
4200
0ebacd12
HK		 4201static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4202 u8 low, u8 high)
4203{
4204 /* FIFO thresholds for pause flow control */
4205 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4206 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4207}
4208
94b5ff74 4209static void rtl_hw_start_8168b(struct rtl8169_private *tp)
219a1e9d 4210{
1ef7286e 4211 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
219a1e9d
FR		 4212}
4213
beb1fe18 4214static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 4215{
1ef7286e 4216 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
b726e493 4217
1ef7286e 4218 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
b726e493 4219
73c86ee3 4220 rtl_disable_clock_request(tp);
219a1e9d
FR		 4221}
4222
beb1fe18 4223static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 4224{
350f7596 4225 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4226 { 0x01, 0, 0x0001 },
4227 { 0x02, 0x0800, 0x1000 },
4228 { 0x03, 0, 0x0042 },
4229 { 0x06, 0x0080, 0x0000 },
4230 { 0x07, 0, 0x2000 }
4231 };
4232
f37658da 4233 rtl_set_def_aspm_entry_latency(tp);
b726e493 4234
1791ad50 4235 rtl_ephy_init(tp, e_info_8168cp);
b726e493 4236
beb1fe18 4237 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4238}
4239
beb1fe18 4240static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 4241{
f37658da 4242 rtl_set_def_aspm_entry_latency(tp);
ef3386f0 4243
1ef7286e 4244 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
ef3386f0
FR		 4245}
4246
beb1fe18 4247static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 4248{
f37658da 4249 rtl_set_def_aspm_entry_latency(tp);
7f3e3d3a 4250
1ef7286e 4251 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
7f3e3d3a
FR		 4252
4253 /* Magic. */
1ef7286e 4254 RTL_W8(tp, DBG_REG, 0x20);
7f3e3d3a
FR		 4255}
4256
beb1fe18 4257static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 4258{
350f7596 4259 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4260 { 0x02, 0x0800, 0x1000 },
4261 { 0x03, 0, 0x0002 },
4262 { 0x06, 0x0080, 0x0000 }
4263 };
4264
f37658da 4265 rtl_set_def_aspm_entry_latency(tp);
b726e493 4266
1ef7286e 4267 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
b726e493 4268
1791ad50 4269 rtl_ephy_init(tp, e_info_8168c_1);
b726e493 4270
beb1fe18 4271 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4272}
4273
beb1fe18 4274static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 4275{
350f7596 4276 static const struct ephy_info e_info_8168c_2[] = {
b726e493 4277 { 0x01, 0, 0x0001 },
a7a92cf8 4278 { 0x03, 0x0400, 0x0020 }
b726e493
FR		 4279 };
4280
f37658da 4281 rtl_set_def_aspm_entry_latency(tp);
b726e493 4282
1791ad50 4283 rtl_ephy_init(tp, e_info_8168c_2);
b726e493 4284
beb1fe18 4285 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4286}
4287
beb1fe18 4288static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 4289{
beb1fe18 4290 rtl_hw_start_8168c_2(tp);
197ff761
FR		 4291}
4292
beb1fe18 4293static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 4294{
f37658da 4295 rtl_set_def_aspm_entry_latency(tp);
6fb07058 4296
beb1fe18 4297 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 4298}
4299
beb1fe18 4300static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 4301{
f37658da 4302 rtl_set_def_aspm_entry_latency(tp);
5b538df9 4303
73c86ee3 4304 rtl_disable_clock_request(tp);
5b538df9
FR		 4305}
4306
beb1fe18 4307static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 4308{
4309 static const struct ephy_info e_info_8168d_4[] = {
1016a4a1
CHL		 4310 { 0x0b, 0x0000, 0x0048 },
4311 { 0x19, 0x0020, 0x0050 },
a7a92cf8
HK		 4312 { 0x0c, 0x0100, 0x0020 },
4313 { 0x10, 0x0004, 0x0000 },
e6de30d6 4314 };
e6de30d6 4315
f37658da 4316 rtl_set_def_aspm_entry_latency(tp);
e6de30d6 4317
1791ad50 4318 rtl_ephy_init(tp, e_info_8168d_4);
e6de30d6 4319
73c86ee3 4320 rtl_enable_clock_request(tp);
e6de30d6 4321}
4322
beb1fe18 4323static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 4324{
70090424 4325 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 4326 { 0x00, 0x0200, 0x0100 },
4327 { 0x00, 0x0000, 0x0004 },
4328 { 0x06, 0x0002, 0x0001 },
4329 { 0x06, 0x0000, 0x0030 },
4330 { 0x07, 0x0000, 0x2000 },
4331 { 0x00, 0x0000, 0x0020 },
4332 { 0x03, 0x5800, 0x2000 },
4333 { 0x03, 0x0000, 0x0001 },
4334 { 0x01, 0x0800, 0x1000 },
4335 { 0x07, 0x0000, 0x4000 },
4336 { 0x1e, 0x0000, 0x2000 },
4337 { 0x19, 0xffff, 0xfe6c },
4338 { 0x0a, 0x0000, 0x0040 }
4339 };
4340
f37658da 4341 rtl_set_def_aspm_entry_latency(tp);
01dc7fec 4342
1791ad50 4343 rtl_ephy_init(tp, e_info_8168e_1);
01dc7fec 4344
73c86ee3 4345 rtl_disable_clock_request(tp);
01dc7fec 4346
4347 /* Reset tx FIFO pointer */
1ef7286e
AS		 4348 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4349 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
01dc7fec 4350
1ef7286e 4351 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
01dc7fec 4352}
4353
beb1fe18 4354static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424
HW		 4355{
4356 static const struct ephy_info e_info_8168e_2[] = {
4357 { 0x09, 0x0000, 0x0080 },
a7a92cf8
HK		 4358 { 0x19, 0x0000, 0x0224 },
4359 { 0x00, 0x0000, 0x0004 },
4360 { 0x0c, 0x3df0, 0x0200 },
70090424
HW		 4361 };
4362
f37658da 4363 rtl_set_def_aspm_entry_latency(tp);
70090424 4364
1791ad50 4365 rtl_ephy_init(tp, e_info_8168e_2);
70090424 4366
724c6fd0
HK		 4367 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4368 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
6b1bd242 4369 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
724c6fd0
HK		 4370 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4371 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
e719b3ea 4372 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
724c6fd0 4373 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
70090424 4374
73c86ee3 4375 rtl_disable_clock_request(tp);
4521e1a9 4376
1ef7286e 4377 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
70090424 4378
cc07d271
HK		 4379 rtl8168_config_eee_mac(tp);
4380
1ef7286e
AS		 4381 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4382 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4383 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
aa1e7d2c
HK		 4384
4385 rtl_hw_aspm_clkreq_enable(tp, true);
70090424
HW		 4386}
4387
5f886e08 4388static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 4389{
f37658da 4390 rtl_set_def_aspm_entry_latency(tp);
c2218925 4391
724c6fd0
HK		 4392 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4393 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
6b1bd242 4394 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4e7e4621 4395 rtl_reset_packet_filter(tp);
e719b3ea
HK		 4396 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4397 rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
724c6fd0
HK		 4398 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4399 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
c2218925 4400
73c86ee3 4401 rtl_disable_clock_request(tp);
4521e1a9 4402
1ef7286e
AS		 4403 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4404 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4405 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4406 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
cc07d271
HK		 4407
4408 rtl8168_config_eee_mac(tp);
c2218925
HW		 4409}
4410
5f886e08
HW		 4411static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4412{
5f886e08
HW		 4413 static const struct ephy_info e_info_8168f_1[] = {
4414 { 0x06, 0x00c0, 0x0020 },
4415 { 0x08, 0x0001, 0x0002 },
4416 { 0x09, 0x0000, 0x0080 },
a7a92cf8
HK		 4417 { 0x19, 0x0000, 0x0224 },
4418 { 0x00, 0x0000, 0x0004 },
4419 { 0x0c, 0x3df0, 0x0200 },
5f886e08
HW		 4420 };
4421
4422 rtl_hw_start_8168f(tp);
4423
1791ad50 4424 rtl_ephy_init(tp, e_info_8168f_1);
5f886e08 4425
724c6fd0 4426 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
5f886e08
HW		 4427}
4428
b3d7b2f2
HW		 4429static void rtl_hw_start_8411(struct rtl8169_private *tp)
4430{
b3d7b2f2
HW		 4431 static const struct ephy_info e_info_8168f_1[] = {
4432 { 0x06, 0x00c0, 0x0020 },
4433 { 0x0f, 0xffff, 0x5200 },
a7a92cf8
HK		 4434 { 0x19, 0x0000, 0x0224 },
4435 { 0x00, 0x0000, 0x0004 },
4436 { 0x0c, 0x3df0, 0x0200 },
b3d7b2f2
HW		 4437 };
4438
4439 rtl_hw_start_8168f(tp);
c259b7f4 4440 rtl_pcie_state_l2l3_disable(tp);
b3d7b2f2 4441
1791ad50 4442 rtl_ephy_init(tp, e_info_8168f_1);
b3d7b2f2 4443
e719b3ea 4444 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
b3d7b2f2
HW		 4445}
4446
5fbea337 4447static void rtl_hw_start_8168g(struct rtl8169_private *tp)
c558386b 4448{
6b1bd242 4449 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
0ebacd12 4450 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
c558386b 4451
f37658da 4452 rtl_set_def_aspm_entry_latency(tp);
c558386b 4453
4e7e4621 4454 rtl_reset_packet_filter(tp);
724c6fd0 4455 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
c558386b 4456
1ef7286e 4457 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
c558386b 4458
724c6fd0
HK		 4459 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4460 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
c558386b 4461
df6f1856
HK		 4462 rtl8168_config_eee_mac(tp);
4463
724c6fd0 4464 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
e719b3ea 4465 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
b51ecea8 4466
c259b7f4 4467 rtl_pcie_state_l2l3_disable(tp);
c558386b
HW		 4468}
4469
5fbea337
CHL		 4470static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
4471{
5fbea337 4472 static const struct ephy_info e_info_8168g_1[] = {
a7a92cf8
HK		 4473 { 0x00, 0x0008, 0x0000 },
4474 { 0x0c, 0x3ff0, 0x0820 },
5fbea337
CHL		 4475 { 0x1e, 0x0000, 0x0001 },
4476 { 0x19, 0x8000, 0x0000 }
4477 };
4478
4479 rtl_hw_start_8168g(tp);
4480
4481 /* disable aspm and clock request before access ephy */
a99790bf 4482 rtl_hw_aspm_clkreq_enable(tp, false);
1791ad50 4483 rtl_ephy_init(tp, e_info_8168g_1);
a99790bf 4484 rtl_hw_aspm_clkreq_enable(tp, true);
5fbea337
CHL		 4485}
4486
57538c4a 4487static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
4488{
57538c4a 4489 static const struct ephy_info e_info_8168g_2[] = {
a7a92cf8
HK		 4490 { 0x00, 0x0008, 0x0000 },
4491 { 0x0c, 0x3ff0, 0x0820 },
4492 { 0x19, 0xffff, 0x7c00 },
4493 { 0x1e, 0xffff, 0x20eb },
4494 { 0x0d, 0xffff, 0x1666 },
4495 { 0x00, 0xffff, 0x10a3 },
4496 { 0x06, 0xffff, 0xf050 },
4497 { 0x04, 0x0000, 0x0010 },
4498 { 0x1d, 0x4000, 0x0000 },
57538c4a 4499 };
4500
5fbea337 4501 rtl_hw_start_8168g(tp);
57538c4a 4502
4503 /* disable aspm and clock request before access ephy */
ebdcebcb 4504 rtl_hw_aspm_clkreq_enable(tp, false);
1791ad50 4505 rtl_ephy_init(tp, e_info_8168g_2);
57538c4a 4506}
4507
45dd95c4 4508static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
4509{
45dd95c4 4510 static const struct ephy_info e_info_8411_2[] = {
a7a92cf8
HK		 4511 { 0x00, 0x0008, 0x0000 },
4512 { 0x0c, 0x37d0, 0x0820 },
4513 { 0x1e, 0x0000, 0x0001 },
4514 { 0x19, 0x8021, 0x0000 },
4515 { 0x1e, 0x0000, 0x2000 },
4516 { 0x0d, 0x0100, 0x0200 },
4517 { 0x00, 0x0000, 0x0080 },
4518 { 0x06, 0x0000, 0x0010 },
4519 { 0x04, 0x0000, 0x0010 },
4520 { 0x1d, 0x0000, 0x4000 },
45dd95c4 4521 };
4522
5fbea337 4523 rtl_hw_start_8168g(tp);
45dd95c4 4524
4525 /* disable aspm and clock request before access ephy */
a99790bf 4526 rtl_hw_aspm_clkreq_enable(tp, false);
1791ad50 4527 rtl_ephy_init(tp, e_info_8411_2);
fe4e8db0
HK		 4528
4529 /* The following Realtek-provided magic fixes an issue with the RX unit
4530 * getting confused after the PHY having been powered-down.
4531 */
4532 r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
4533 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
4534 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
4535 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
4536 r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
4537 r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
4538 r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
4539 r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
4540 mdelay(3);
4541 r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
4542
4543 r8168_mac_ocp_write(tp, 0xF800, 0xE008);
4544 r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
4545 r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
4546 r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
4547 r8168_mac_ocp_write(tp, 0xF808, 0xE027);
4548 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
4549 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
4550 r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
4551 r8168_mac_ocp_write(tp, 0xF810, 0xC602);
4552 r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
4553 r8168_mac_ocp_write(tp, 0xF814, 0x0000);
4554 r8168_mac_ocp_write(tp, 0xF816, 0xC502);
4555 r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
4556 r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
4557 r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
4558 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
4559 r8168_mac_ocp_write(tp, 0xF820, 0x080A);
4560 r8168_mac_ocp_write(tp, 0xF822, 0x6420);
4561 r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
4562 r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
4563 r8168_mac_ocp_write(tp, 0xF828, 0xC516);
4564 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
4565 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
4566 r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
4567 r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
4568 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
4569 r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
4570 r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
4571 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
4572 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
4573 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
4574 r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
4575 r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
4576 r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
4577 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
4578 r8168_mac_ocp_write(tp, 0xF846, 0xC404);
4579 r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
4580 r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
4581 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
4582 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
4583 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
4584 r8168_mac_ocp_write(tp, 0xF852, 0xE434);
4585 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
4586 r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
4587 r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
4588 r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
4589 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
4590 r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
4591 r8168_mac_ocp_write(tp, 0xF860, 0xF007);
4592 r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
4593 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
4594 r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
4595 r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
4596 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
4597 r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
4598 r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
4599 r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
4600 r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
4601 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
4602 r8168_mac_ocp_write(tp, 0xF876, 0xC516);
4603 r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
4604 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
4605 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
4606 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
4607 r8168_mac_ocp_write(tp, 0xF880, 0xC512);
4608 r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
4609 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
4610 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
4611 r8168_mac_ocp_write(tp, 0xF888, 0x483F);
4612 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
4613 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
4614 r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
4615 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
4616 r8168_mac_ocp_write(tp, 0xF892, 0xC505);
4617 r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
4618 r8168_mac_ocp_write(tp, 0xF896, 0xC502);
4619 r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
4620 r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
4621 r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
4622 r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
4623 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
4624 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
4625 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
4626 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
4627 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
4628 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
4629 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
4630 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
4631 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
4632 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
4633 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
4634 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
4635 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
4636 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
4637 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
4638 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
4639 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
4640 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
4641 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
4642 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
4643 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
4644 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
4645 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
4646 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
4647 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
4648 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
4649 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
4650 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
4651 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
4652 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
4653 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
4654
4655 r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
4656
4657 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
4658 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
4659 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
4660 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
4661 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
4662 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
4663 r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
4664
a99790bf 4665 rtl_hw_aspm_clkreq_enable(tp, true);
45dd95c4 4666}
4667
6e1d0b89
CHL		 4668static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
4669{
6e1d0b89
CHL		 4670 static const struct ephy_info e_info_8168h_1[] = {
4671 { 0x1e, 0x0800, 0x0001 },
4672 { 0x1d, 0x0000, 0x0800 },
4673 { 0x05, 0xffff, 0x2089 },
4674 { 0x06, 0xffff, 0x5881 },
a7a92cf8 4675 { 0x04, 0xffff, 0x854a },
6e1d0b89
CHL		 4676 { 0x01, 0xffff, 0x068b }
4677 };
ef712ede 4678 int rg_saw_cnt;
6e1d0b89
CHL		 4679
4680 /* disable aspm and clock request before access ephy */
a99790bf 4681 rtl_hw_aspm_clkreq_enable(tp, false);
1791ad50 4682 rtl_ephy_init(tp, e_info_8168h_1);
6e1d0b89 4683
6b1bd242 4684 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
0ebacd12 4685 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
6e1d0b89 4686
f37658da 4687 rtl_set_def_aspm_entry_latency(tp);
6e1d0b89 4688
4e7e4621 4689 rtl_reset_packet_filter(tp);
6e1d0b89 4690
e719b3ea 4691 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
6e1d0b89 4692
e719b3ea 4693 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
6e1d0b89 4694
724c6fd0 4695 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
6e1d0b89 4696
1ef7286e 4697 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
6e1d0b89 4698
724c6fd0
HK		 4699 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4700 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
6e1d0b89 4701
df6f1856
HK		 4702 rtl8168_config_eee_mac(tp);
4703
1ef7286e
AS		 4704 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4705 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
6e1d0b89 4706
1ef7286e 4707 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
6e1d0b89 4708
e719b3ea 4709 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
6e1d0b89 4710
c259b7f4 4711 rtl_pcie_state_l2l3_disable(tp);
6e1d0b89
CHL		 4712
4713 rtl_writephy(tp, 0x1f, 0x0c42);
58493333 4714 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6e1d0b89
CHL		 4715 rtl_writephy(tp, 0x1f, 0x0000);
4716 if (rg_saw_cnt > 0) {
4717 u16 sw_cnt_1ms_ini;
4718
4719 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
4720 sw_cnt_1ms_ini &= 0x0fff;
ef712ede 4721 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
6e1d0b89
CHL		 4722 }
4723
ef712ede
HK		 4724 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
4725 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
4726 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
4727 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
6e1d0b89
CHL		 4728
4729 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
4730 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
4731 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
4732 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
a99790bf
KHF		 4733
4734 rtl_hw_aspm_clkreq_enable(tp, true);
6e1d0b89
CHL		 4735}
4736
935e2218
CHL		 4737static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
4738{
003609da
CHL		 4739 rtl8168ep_stop_cmac(tp);
4740
6b1bd242 4741 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
0ebacd12 4742 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
935e2218 4743
f37658da 4744 rtl_set_def_aspm_entry_latency(tp);
935e2218 4745
4e7e4621 4746 rtl_reset_packet_filter(tp);
935e2218 4747
e719b3ea 4748 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
935e2218 4749
724c6fd0 4750 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
935e2218 4751
1ef7286e 4752 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
935e2218 4753
724c6fd0
HK		 4754 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4755 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
935e2218 4756
df6f1856
HK		 4757 rtl8168_config_eee_mac(tp);
4758
724c6fd0 4759 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
935e2218 4760
1ef7286e 4761 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
935e2218 4762
c259b7f4 4763 rtl_pcie_state_l2l3_disable(tp);
935e2218
CHL		 4764}
4765
4766static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
4767{
935e2218
CHL		 4768 static const struct ephy_info e_info_8168ep_1[] = {
4769 { 0x00, 0xffff, 0x10ab },
4770 { 0x06, 0xffff, 0xf030 },
4771 { 0x08, 0xffff, 0x2006 },
4772 { 0x0d, 0xffff, 0x1666 },
4773 { 0x0c, 0x3ff0, 0x0000 }
4774 };
4775
4776 /* disable aspm and clock request before access ephy */
a99790bf 4777 rtl_hw_aspm_clkreq_enable(tp, false);
1791ad50 4778 rtl_ephy_init(tp, e_info_8168ep_1);
935e2218
CHL		 4779
4780 rtl_hw_start_8168ep(tp);
a99790bf
KHF		 4781
4782 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 4783}
4784
4785static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
4786{
935e2218
CHL		 4787 static const struct ephy_info e_info_8168ep_2[] = {
4788 { 0x00, 0xffff, 0x10a3 },
4789 { 0x19, 0xffff, 0xfc00 },
4790 { 0x1e, 0xffff, 0x20ea }
4791 };
4792
4793 /* disable aspm and clock request before access ephy */
a99790bf 4794 rtl_hw_aspm_clkreq_enable(tp, false);
1791ad50 4795 rtl_ephy_init(tp, e_info_8168ep_2);
935e2218
CHL		 4796
4797 rtl_hw_start_8168ep(tp);
4798
1ef7286e
AS		 4799 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4800 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
a99790bf
KHF		 4801
4802 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 4803}
4804
4805static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
4806{
935e2218 4807 static const struct ephy_info e_info_8168ep_3[] = {
a7a92cf8
HK		 4808 { 0x00, 0x0000, 0x0080 },
4809 { 0x0d, 0x0100, 0x0200 },
4810 { 0x19, 0x8021, 0x0000 },
4811 { 0x1e, 0x0000, 0x2000 },
935e2218
CHL		 4812 };
4813
4814 /* disable aspm and clock request before access ephy */
a99790bf 4815 rtl_hw_aspm_clkreq_enable(tp, false);
1791ad50 4816 rtl_ephy_init(tp, e_info_8168ep_3);
935e2218
CHL		 4817
4818 rtl_hw_start_8168ep(tp);
4819
1ef7286e
AS		 4820 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4821 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
935e2218 4822
ef712ede
HK		 4823 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
4824 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
4825 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
a99790bf
KHF		 4826
4827 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 4828}
4829
1287723a
HK		 4830static void rtl_hw_start_8117(struct rtl8169_private *tp)
4831{
4832 static const struct ephy_info e_info_8117[] = {
4833 { 0x19, 0x0040, 0x1100 },
4834 { 0x59, 0x0040, 0x1100 },
4835 };
4836 int rg_saw_cnt;
4837
4838 rtl8168ep_stop_cmac(tp);
4839
4840 /* disable aspm and clock request before access ephy */
4841 rtl_hw_aspm_clkreq_enable(tp, false);
4842 rtl_ephy_init(tp, e_info_8117);
4843
4844 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4845 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
4846
4847 rtl_set_def_aspm_entry_latency(tp);
4848
4849 rtl_reset_packet_filter(tp);
4850
4851 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f90);
4852
4853 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
4854
4855 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4856
4857 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4858 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4859
4860 rtl8168_config_eee_mac(tp);
4861
4862 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4863 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4864
4865 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
4866
4867 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4868
4869 rtl_pcie_state_l2l3_disable(tp);
4870
4871 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
4872 if (rg_saw_cnt > 0) {
4873 u16 sw_cnt_1ms_ini;
4874
4875 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
4876 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
4877 }
4878
4879 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
4880 r8168_mac_ocp_write(tp, 0xea80, 0x0003);
4881 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
4882 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
4883
4884 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
4885 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
4886 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
4887 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
4888
229c1e0d
HK		 4889 /* firmware is for MAC only */
4890 rtl_apply_firmware(tp);
4891
1287723a
HK		 4892 rtl_hw_aspm_clkreq_enable(tp, true);
4893}
4894
beb1fe18 4895static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 4896{
350f7596 4897 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 4898 { 0x01, 0, 0x6e65 },
4899 { 0x02, 0, 0x091f },
4900 { 0x03, 0, 0xc2f9 },
4901 { 0x06, 0, 0xafb5 },
4902 { 0x07, 0, 0x0e00 },
4903 { 0x19, 0, 0xec80 },
4904 { 0x01, 0, 0x2e65 },
4905 { 0x01, 0, 0x6e65 }
4906 };
4907 u8 cfg1;
4908
f37658da 4909 rtl_set_def_aspm_entry_latency(tp);
2857ffb7 4910
1ef7286e 4911 RTL_W8(tp, DBG_REG, FIX_NAK_1);
2857ffb7 4912
1ef7286e 4913 RTL_W8(tp, Config1,
2857ffb7 4914 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
1ef7286e 4915 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7 4916
1ef7286e 4917 cfg1 = RTL_R8(tp, Config1);
2857ffb7 4918 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
1ef7286e 4919 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
2857ffb7 4920
1791ad50 4921 rtl_ephy_init(tp, e_info_8102e_1);
2857ffb7
FR		 4922}
4923
beb1fe18 4924static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 4925{
f37658da 4926 rtl_set_def_aspm_entry_latency(tp);
2857ffb7 4927
1ef7286e
AS		 4928 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
4929 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7
FR		 4930}
4931
beb1fe18 4932static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 4933{
beb1fe18 4934 rtl_hw_start_8102e_2(tp);
2857ffb7 4935
fdf6fc06 4936 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 4937}
4938
beb1fe18 4939static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443
HW		 4940{
4941 static const struct ephy_info e_info_8105e_1[] = {
4942 { 0x07, 0, 0x4000 },
4943 { 0x19, 0, 0x0200 },
4944 { 0x19, 0, 0x0020 },
4945 { 0x1e, 0, 0x2000 },
4946 { 0x03, 0, 0x0001 },
4947 { 0x19, 0, 0x0100 },
4948 { 0x19, 0, 0x0004 },
4949 { 0x0a, 0, 0x0020 }
4950 };
4951
cecb5fd7 4952 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 4953 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5a5e4443 4954
cecb5fd7 4955 /* Disable Early Tally Counter */
1ef7286e 4956 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5a5e4443 4957
1ef7286e
AS		 4958 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
4959 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5a5e4443 4960
1791ad50 4961 rtl_ephy_init(tp, e_info_8105e_1);
b51ecea8 4962
c259b7f4 4963 rtl_pcie_state_l2l3_disable(tp);
5a5e4443
HW		 4964}
4965
beb1fe18 4966static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 4967{
beb1fe18 4968 rtl_hw_start_8105e_1(tp);
fdf6fc06 4969 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 4970}
4971
7e18dca1
HW		 4972static void rtl_hw_start_8402(struct rtl8169_private *tp)
4973{
7e18dca1
HW		 4974 static const struct ephy_info e_info_8402[] = {
4975 { 0x19, 0xffff, 0xff64 },
4976 { 0x1e, 0, 0x4000 }
4977 };
4978
f37658da 4979 rtl_set_def_aspm_entry_latency(tp);
7e18dca1
HW		 4980
4981 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 4982 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
7e18dca1 4983
1ef7286e 4984 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7e18dca1 4985
1791ad50 4986 rtl_ephy_init(tp, e_info_8402);
7e18dca1 4987
6b1bd242 4988 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
4e7e4621 4989 rtl_reset_packet_filter(tp);
724c6fd0
HK		 4990 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4991 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4992 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
b51ecea8 4993
c259b7f4 4994 rtl_pcie_state_l2l3_disable(tp);
7e18dca1
HW		 4995}
4996
5598bfe5
HW		 4997static void rtl_hw_start_8106(struct rtl8169_private *tp)
4998{
0866cd15
KHF		 4999 rtl_hw_aspm_clkreq_enable(tp, false);
5000
5598bfe5 5001 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 5002 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5598bfe5 5003
1ef7286e
AS		 5004 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5005 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5006 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
b51ecea8 5007
c259b7f4 5008 rtl_pcie_state_l2l3_disable(tp);
0866cd15 5009 rtl_hw_aspm_clkreq_enable(tp, true);
5598bfe5
HW		 5010}
5011
f1bce4ad
HK		 5012DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
5013{
5014 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
5015}
5016
5017static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
5018{
5019 rtl_pcie_state_l2l3_disable(tp);
5020
5021 RTL_W16(tp, 0x382, 0x221b);
5022 RTL_W8(tp, 0x4500, 0);
5023 RTL_W16(tp, 0x4800, 0);
5024
5025 /* disable UPS */
5026 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
5027
5028 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
5029
5030 r8168_mac_ocp_write(tp, 0xc140, 0xffff);
5031 r8168_mac_ocp_write(tp, 0xc142, 0xffff);
5032
5033 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
5034 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
5035 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
5036
5037 /* disable new tx descriptor format */
5038 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
5039
5040 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
5041 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
5042 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
5043 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
5044 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
5045 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
5046 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
5047 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
5048 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0067);
5049 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00);
5050 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
5051 r8168_mac_ocp_modify(tp, 0xe84c, 0x0000, 0x00c0);
5052 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
5053 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
5054 udelay(1);
5055 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
5056 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
5057
5058 r8168_mac_ocp_write(tp, 0xe098, 0xc302);
5059
5060 rtl_udelay_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
5061
b3a42e3a
HK		 5062 rtl8125_config_eee_mac(tp);
5063
f1bce4ad
HK		 5064 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5065 udelay(10);
5066}
5067
5068static void rtl_hw_start_8125_1(struct rtl8169_private *tp)
5069{
5070 static const struct ephy_info e_info_8125_1[] = {
5071 { 0x01, 0xffff, 0xa812 },
5072 { 0x09, 0xffff, 0x520c },
5073 { 0x04, 0xffff, 0xd000 },
5074 { 0x0d, 0xffff, 0xf702 },
5075 { 0x0a, 0xffff, 0x8653 },
5076 { 0x06, 0xffff, 0x001e },
5077 { 0x08, 0xffff, 0x3595 },
5078 { 0x20, 0xffff, 0x9455 },
5079 { 0x21, 0xffff, 0x99ff },
5080 { 0x02, 0xffff, 0x6046 },
5081 { 0x29, 0xffff, 0xfe00 },
5082 { 0x23, 0xffff, 0xab62 },
5083
5084 { 0x41, 0xffff, 0xa80c },
5085 { 0x49, 0xffff, 0x520c },
5086 { 0x44, 0xffff, 0xd000 },
5087 { 0x4d, 0xffff, 0xf702 },
5088 { 0x4a, 0xffff, 0x8653 },
5089 { 0x46, 0xffff, 0x001e },
5090 { 0x48, 0xffff, 0x3595 },
5091 { 0x60, 0xffff, 0x9455 },
5092 { 0x61, 0xffff, 0x99ff },
5093 { 0x42, 0xffff, 0x6046 },
5094 { 0x69, 0xffff, 0xfe00 },
5095 { 0x63, 0xffff, 0xab62 },
5096 };
5097
5098 rtl_set_def_aspm_entry_latency(tp);
5099
5100 /* disable aspm and clock request before access ephy */
5101 rtl_hw_aspm_clkreq_enable(tp, false);
5102 rtl_ephy_init(tp, e_info_8125_1);
5103
5104 rtl_hw_start_8125_common(tp);
5105}
5106
5107static void rtl_hw_start_8125_2(struct rtl8169_private *tp)
5108{
5109 static const struct ephy_info e_info_8125_2[] = {
5110 { 0x04, 0xffff, 0xd000 },
5111 { 0x0a, 0xffff, 0x8653 },
5112 { 0x23, 0xffff, 0xab66 },
5113 { 0x20, 0xffff, 0x9455 },
5114 { 0x21, 0xffff, 0x99ff },
5115 { 0x29, 0xffff, 0xfe04 },
5116
5117 { 0x44, 0xffff, 0xd000 },
5118 { 0x4a, 0xffff, 0x8653 },
5119 { 0x63, 0xffff, 0xab66 },
5120 { 0x60, 0xffff, 0x9455 },
5121 { 0x61, 0xffff, 0x99ff },
5122 { 0x69, 0xffff, 0xfe04 },
5123 };
5124
5125 rtl_set_def_aspm_entry_latency(tp);
5126
5127 /* disable aspm and clock request before access ephy */
5128 rtl_hw_aspm_clkreq_enable(tp, false);
5129 rtl_ephy_init(tp, e_info_8125_2);
5130
5131 rtl_hw_start_8125_common(tp);
5132}
5133
8344ffff
HK		 5134static void rtl_hw_config(struct rtl8169_private *tp)
5135{
5136 static const rtl_generic_fct hw_configs[] = {
5137 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
5138 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
5139 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
5140 [RTL_GIGA_MAC_VER_10] = NULL,
94b5ff74
HK		 5141 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
5142 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b,
8344ffff
HK		 5143 [RTL_GIGA_MAC_VER_13] = NULL,
5144 [RTL_GIGA_MAC_VER_14] = NULL,
5145 [RTL_GIGA_MAC_VER_15] = NULL,
5146 [RTL_GIGA_MAC_VER_16] = NULL,
94b5ff74 5147 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
8344ffff
HK		 5148 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5149 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5150 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5151 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5152 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5153 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5154 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5155 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5156 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5157 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5158 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5159 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5160 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
0a413e6b 5161 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
8344ffff
HK		 5162 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5163 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5164 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5165 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5166 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5167 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5168 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5169 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5170 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5171 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5172 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5173 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5174 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5175 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5176 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5177 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5178 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5179 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5180 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5181 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
1287723a 5182 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
f1bce4ad
HK		 5183 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125_1,
5184 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125_2,
8344ffff
HK		 5185 };
5186
5187 if (hw_configs[tp->mac_version])
5188 hw_configs[tp->mac_version](tp);
5189}
5190
f1bce4ad
HK		 5191static void rtl_hw_start_8125(struct rtl8169_private *tp)
5192{
5193 int i;
5194
5195 /* disable interrupt coalescing */
5196 for (i = 0xa00; i < 0xb00; i += 4)
5197 RTL_W32(tp, i, 0);
5198
5199 rtl_hw_config(tp);
5200}
5201
8344ffff 5202static void rtl_hw_start_8168(struct rtl8169_private *tp)
07ce4064 5203{
272b2265
HK		 5204 if (rtl_is_8168evl_up(tp))
5205 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5206 else
5207 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
1a964649 5208
8344ffff 5209 rtl_hw_config(tp);
bcf2b868
HK		 5210
5211 /* disable interrupt coalescing */
5212 RTL_W16(tp, IntrMitigate, 0x0000);
1da177e4
LT		 5213}
5214
6c19156e
HK		 5215static void rtl_hw_start_8169(struct rtl8169_private *tp)
5216{
5217 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5218 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
5219
5220 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
5221
5222 tp->cp_cmd |= PCIMulRW;
5223
5224 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5225 tp->mac_version == RTL_GIGA_MAC_VER_03) {
5226 netif_dbg(tp, drv, tp->dev,
5227 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
5228 tp->cp_cmd |= (1 << 14);
5229 }
5230
5231 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5232
5233 rtl8169_set_magic_reg(tp, tp->mac_version);
5234
5235 RTL_W32(tp, RxMissed, 0);
bcf2b868
HK		 5236
5237 /* disable interrupt coalescing */
5238 RTL_W16(tp, IntrMitigate, 0x0000);
6c19156e
HK		 5239}
5240
5241static void rtl_hw_start(struct rtl8169_private *tp)
5242{
5243 rtl_unlock_config_regs(tp);
5244
5245 tp->cp_cmd &= CPCMD_MASK;
5246 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5247
5248 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5249 rtl_hw_start_8169(tp);
f1bce4ad
HK		 5250 else if (rtl_is_8125(tp))
5251 rtl_hw_start_8125(tp);
6c19156e
HK		 5252 else
5253 rtl_hw_start_8168(tp);
5254
5255 rtl_set_rx_max_size(tp);
5256 rtl_set_rx_tx_desc_registers(tp);
5257 rtl_lock_config_regs(tp);
5258
4ebcb113
HK		 5259 rtl_jumbo_config(tp, tp->dev->mtu);
5260
6c19156e 5261 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
7366016d 5262 RTL_R16(tp, CPlusCmd);
6c19156e
HK		 5263 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
5264 rtl_init_rxcfg(tp);
5265 rtl_set_tx_config_registers(tp);
6c19156e 5266 rtl_set_rx_mode(tp->dev);
6c19156e
HK		 5267 rtl_irq_enable(tp);
5268}
5269
1da177e4
LT		 5270static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5271{
d58d46b5
FR		 5272 struct rtl8169_private *tp = netdev_priv(dev);
5273
4ebcb113 5274 rtl_jumbo_config(tp, new_mtu);
d58d46b5 5275
1da177e4 5276 dev->mtu = new_mtu;
350fb32a
MM		 5277 netdev_update_features(dev);
5278
323bb685 5279 return 0;
1da177e4
LT		 5280}
5281
5282static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5283{
95e0918d 5284 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 5285 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5286}
5287
1d0254dd 5288static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
1da177e4
LT		 5289{
5290 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5291
a0750138
AD		 5292 /* Force memory writes to complete before releasing descriptor */
5293 dma_wmb();
5294
1d0254dd 5295 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
1da177e4
LT		 5296}
5297
32879f00
HK		 5298static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5299 struct RxDesc *desc)
1da177e4 5300{
1e1205b7 5301 struct device *d = tp_to_dev(tp);
d3b404c2 5302 int node = dev_to_node(d);
32879f00
HK		 5303 dma_addr_t mapping;
5304 struct page *data;
1da177e4 5305
32879f00 5306 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
6f0333b8
ED		 5307 if (!data)
5308 return NULL;
e9f63f30 5309
32879f00 5310 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
d827d86b
SG		 5311 if (unlikely(dma_mapping_error(d, mapping))) {
5312 if (net_ratelimit())
5313 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
32879f00
HK		 5314 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
5315 return NULL;
d827d86b 5316 }
1da177e4 5317
d731af78
HK		 5318 desc->addr = cpu_to_le64(mapping);
5319 rtl8169_mark_to_asic(desc);
3eafe507 5320
32879f00 5321 return data;
1da177e4
LT		 5322}
5323
5324static void rtl8169_rx_clear(struct rtl8169_private *tp)
5325{
07d3f51f 5326 unsigned int i;
1da177e4 5327
eb2e7f09
HK		 5328 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
5329 dma_unmap_page(tp_to_dev(tp),
5330 le64_to_cpu(tp->RxDescArray[i].addr),
5331 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5332 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
5333 tp->Rx_databuff[i] = NULL;
5334 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
1da177e4
LT		 5335 }
5336}
5337
0ecbe1ca 5338static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 5339{
0ecbe1ca
SG		 5340 desc->opts1 |= cpu_to_le32(RingEnd);
5341}
5b0384f4 5342
0ecbe1ca
SG		 5343static int rtl8169_rx_fill(struct rtl8169_private *tp)
5344{
5345 unsigned int i;
1da177e4 5346
0ecbe1ca 5347 for (i = 0; i < NUM_RX_DESC; i++) {
32879f00 5348 struct page *data;
4ae47c2d 5349
0ecbe1ca 5350 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8 5351 if (!data) {
e4b5c7a5
HK		 5352 rtl8169_rx_clear(tp);
5353 return -ENOMEM;
6f0333b8
ED		 5354 }
5355 tp->Rx_databuff[i] = data;
1da177e4 5356 }
1da177e4 5357
0ecbe1ca 5358 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
0ecbe1ca 5359
e4b5c7a5 5360 return 0;
1da177e4
LT		 5361}
5362
b1127e64 5363static int rtl8169_init_ring(struct rtl8169_private *tp)
1da177e4 5364{
1da177e4
LT		 5365 rtl8169_init_ring_indexes(tp);
5366
b1127e64
HK		 5367 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5368 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
1da177e4 5369
0ecbe1ca 5370 return rtl8169_rx_fill(tp);
1da177e4
LT		 5371}
5372
48addcc9 5373static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 5374 struct TxDesc *desc)
5375{
5376 unsigned int len = tx_skb->len;
5377
48addcc9
SG		 5378 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5379
1da177e4
LT		 5380 desc->opts1 = 0x00;
5381 desc->opts2 = 0x00;
5382 desc->addr = 0x00;
5383 tx_skb->len = 0;
5384}
5385
3eafe507
SG		 5386static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5387 unsigned int n)
1da177e4
LT		 5388{
5389 unsigned int i;
5390
3eafe507
SG		 5391 for (i = 0; i < n; i++) {
5392 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 5393 struct ring_info *tx_skb = tp->tx_skb + entry;
5394 unsigned int len = tx_skb->len;
5395
5396 if (len) {
5397 struct sk_buff *skb = tx_skb->skb;
5398
1e1205b7 5399 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
1da177e4
LT		 5400 tp->TxDescArray + entry);
5401 if (skb) {
7a4b813c 5402 dev_consume_skb_any(skb);
1da177e4
LT		 5403 tx_skb->skb = NULL;
5404 }
1da177e4
LT		 5405 }
5406 }
3eafe507
SG		 5407}
5408
5409static void rtl8169_tx_clear(struct rtl8169_private *tp)
5410{
5411 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4 5412 tp->cur_tx = tp->dirty_tx = 0;
d92060bc 5413 netdev_reset_queue(tp->dev);
1da177e4
LT		 5414}
5415
4422bcd4 5416static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 5417{
c4028958 5418 struct net_device *dev = tp->dev;
56de414c 5419 int i;
1da177e4 5420
da78dbff
FR		 5421 napi_disable(&tp->napi);
5422 netif_stop_queue(dev);
16f11500 5423 synchronize_rcu();
1da177e4 5424
c7c2c39b 5425 rtl8169_hw_reset(tp);
5426
56de414c 5427 for (i = 0; i < NUM_RX_DESC; i++)
1d0254dd 5428 rtl8169_mark_to_asic(tp->RxDescArray + i);
56de414c 5429
1da177e4 5430 rtl8169_tx_clear(tp);
c7c2c39b 5431 rtl8169_init_ring_indexes(tp);
1da177e4 5432
da78dbff 5433 napi_enable(&tp->napi);
61cb532d 5434 rtl_hw_start(tp);
56de414c 5435 netif_wake_queue(dev);
1da177e4
LT		 5436}
5437
0290bd29 5438static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
1da177e4 5439{
da78dbff
FR		 5440 struct rtl8169_private *tp = netdev_priv(dev);
5441
5442 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5443}
5444
734c1409
HK		 5445static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5446{
5447 u32 status = opts0 | len;
5448
5449 if (entry == NUM_TX_DESC - 1)
5450 status |= RingEnd;
5451
5452 return cpu_to_le32(status);
5453}
5454
1da177e4 5455static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5456 u32 *opts)
1da177e4
LT		 5457{
5458 struct skb_shared_info *info = skb_shinfo(skb);
5459 unsigned int cur_frag, entry;
6e1d0b89 5460 struct TxDesc *uninitialized_var(txd);
1e1205b7 5461 struct device *d = tp_to_dev(tp);
1da177e4
LT		 5462
5463 entry = tp->cur_tx;
5464 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 5465 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4 5466 dma_addr_t mapping;
734c1409 5467 u32 len;
1da177e4
LT		 5468 void *addr;
5469
5470 entry = (entry + 1) % NUM_TX_DESC;
5471
5472 txd = tp->TxDescArray + entry;
9e903e08 5473 len = skb_frag_size(frag);
929f6189 5474 addr = skb_frag_address(frag);
48addcc9 5475 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5476 if (unlikely(dma_mapping_error(d, mapping))) {
5477 if (net_ratelimit())
5478 netif_err(tp, drv, tp->dev,
5479 "Failed to map TX fragments DMA!\n");
3eafe507 5480 goto err_out;
d827d86b 5481 }
1da177e4 5482
734c1409 5483 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
2b7b4318 5484 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5485 txd->addr = cpu_to_le64(mapping);
5486
5487 tp->tx_skb[entry].len = len;
5488 }
5489
5490 if (cur_frag) {
5491 tp->tx_skb[entry].skb = skb;
5492 txd->opts1 |= cpu_to_le32(LastFrag);
5493 }
5494
5495 return cur_frag;
3eafe507
SG		 5496
5497err_out:
5498 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5499 return -EIO;
1da177e4
LT		 5500}
5501
b423e9ae 5502static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5503{
5504 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5505}
5506
e974604b 5507/* msdn_giant_send_check()
5508 * According to the document of microsoft, the TCP Pseudo Header excludes the
5509 * packet length for IPv6 TCP large packets.
5510 */
5511static int msdn_giant_send_check(struct sk_buff *skb)
5512{
5513 const struct ipv6hdr *ipv6h;
5514 struct tcphdr *th;
5515 int ret;
5516
5517 ret = skb_cow_head(skb, 0);
5518 if (ret)
5519 return ret;
5520
5521 ipv6h = ipv6_hdr(skb);
5522 th = tcp_hdr(skb);
5523
5524 th->check = 0;
5525 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5526
5527 return ret;
5528}
5529
87945b6d 5530static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
1da177e4 5531{
350fb32a
MM		 5532 u32 mss = skb_shinfo(skb)->gso_size;
5533
2b7b4318
FR		 5534 if (mss) {
5535 opts[0] |= TD_LSO;
5888d3fc 5536 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5537 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5538 const struct iphdr *ip = ip_hdr(skb);
5539
5540 if (ip->protocol == IPPROTO_TCP)
5541 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5542 else if (ip->protocol == IPPROTO_UDP)
5543 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5544 else
5545 WARN_ON_ONCE(1);
5546 }
5888d3fc 5547}
5548
5549static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5550 struct sk_buff *skb, u32 *opts)
5551{
bdfa4ed6 5552 u32 transport_offset = (u32)skb_transport_offset(skb);
5888d3fc 5553 u32 mss = skb_shinfo(skb)->gso_size;
5554
5555 if (mss) {
4ff36466 5556 switch (vlan_get_protocol(skb)) {
e974604b 5557 case htons(ETH_P_IP):
5558 opts[0] |= TD1_GTSENV4;
5559 break;
5560
5561 case htons(ETH_P_IPV6):
5562 if (msdn_giant_send_check(skb))
5563 return false;
5564
5565 opts[0] |= TD1_GTSENV6;
5566 break;
5567
5568 default:
5569 WARN_ON_ONCE(1);
5570 break;
5571 }
5572
bdfa4ed6 5573 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5888d3fc 5574 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
2b7b4318 5575 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
e974604b 5576 u8 ip_protocol;
1da177e4 5577
4ff36466 5578 switch (vlan_get_protocol(skb)) {
e974604b 5579 case htons(ETH_P_IP):
5580 opts[1] |= TD1_IPv4_CS;
5581 ip_protocol = ip_hdr(skb)->protocol;
5582 break;
5583
5584 case htons(ETH_P_IPV6):
5585 opts[1] |= TD1_IPv6_CS;
5586 ip_protocol = ipv6_hdr(skb)->nexthdr;
5587 break;
5588
5589 default:
5590 ip_protocol = IPPROTO_RAW;
5591 break;
5592 }
5593
5594 if (ip_protocol == IPPROTO_TCP)
5595 opts[1] |= TD1_TCP_CS;
5596 else if (ip_protocol == IPPROTO_UDP)
5597 opts[1] |= TD1_UDP_CS;
2b7b4318
FR		 5598 else
5599 WARN_ON_ONCE(1);
e974604b 5600
5601 opts[1] |= transport_offset << TCPHO_SHIFT;
b423e9ae 5602 } else {
5603 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 5604 return !eth_skb_pad(skb);
1da177e4 5605 }
5888d3fc 5606
b423e9ae 5607 return true;
1da177e4
LT		 5608}
5609
76085c9e
HK		 5610static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
5611 unsigned int nr_frags)
5612{
5613 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
5614
5615 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5616 return slots_avail > nr_frags;
5617}
5618
87945b6d
HK		 5619/* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
5620static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
5621{
5622 switch (tp->mac_version) {
5623 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5624 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
5625 return false;
5626 default:
5627 return true;
5628 }
5629}
5630
f1bce4ad
HK		 5631static void rtl8169_doorbell(struct rtl8169_private *tp)
5632{
5633 if (rtl_is_8125(tp))
5634 RTL_W16(tp, TxPoll_8125, BIT(0));
5635 else
5636 RTL_W8(tp, TxPoll, NPQ);
5637}
5638
61357325
SH		 5639static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5640 struct net_device *dev)
1da177e4
LT		 5641{
5642 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 5643 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4 5644 struct TxDesc *txd = tp->TxDescArray + entry;
1e1205b7 5645 struct device *d = tp_to_dev(tp);
1da177e4 5646 dma_addr_t mapping;
734c1409 5647 u32 opts[2], len;
ef143585
HK		 5648 bool stop_queue;
5649 bool door_bell;
3eafe507 5650 int frags;
5b0384f4 5651
76085c9e 5652 if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 5653 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 5654 goto err_stop_0;
1da177e4
LT		 5655 }
5656
5657 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 5658 goto err_stop_0;
5659
355f948a 5660 opts[1] = rtl8169_tx_vlan_tag(skb);
b423e9ae 5661 opts[0] = DescOwn;
5662
87945b6d 5663 if (rtl_chip_supports_csum_v2(tp)) {
96ea772e
HK		 5664 if (!rtl8169_tso_csum_v2(tp, skb, opts))
5665 goto err_dma_0;
87945b6d
HK		 5666 } else {
5667 rtl8169_tso_csum_v1(skb, opts);
e974604b 5668 }
b423e9ae 5669
3eafe507 5670 len = skb_headlen(skb);
48addcc9 5671 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 5672 if (unlikely(dma_mapping_error(d, mapping))) {
5673 if (net_ratelimit())
5674 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 5675 goto err_dma_0;
d827d86b 5676 }
3eafe507
SG		 5677
5678 tp->tx_skb[entry].len = len;
5679 txd->addr = cpu_to_le64(mapping);
1da177e4 5680
2b7b4318 5681 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 5682 if (frags < 0)
5683 goto err_dma_1;
5684 else if (frags)
2b7b4318 5685 opts[0] |= FirstFrag;
3eafe507 5686 else {
2b7b4318 5687 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 5688 tp->tx_skb[entry].skb = skb;
5689 }
5690
2b7b4318
FR		 5691 txd->opts2 = cpu_to_le32(opts[1]);
5692
5047fb5d
RC		 5693 skb_tx_timestamp(skb);
5694
a0750138
AD		 5695 /* Force memory writes to complete before releasing descriptor */
5696 dma_wmb();
1da177e4 5697
ef143585
HK		 5698 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
5699
734c1409 5700 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
1da177e4 5701
a0750138 5702 /* Force all memory writes to complete before notifying device */
4c020a96 5703 wmb();
1da177e4 5704
a0750138
AD		 5705 tp->cur_tx += frags + 1;
5706
ef143585
HK		 5707 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS);
5708 if (unlikely(stop_queue)) {
0255d592
HK		 5709 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5710 * not miss a ring update when it notices a stopped queue.
5711 */
5712 smp_wmb();
5713 netif_stop_queue(dev);
4773f9bd 5714 door_bell = true;
ef143585
HK		 5715 }
5716
5717 if (door_bell)
f1bce4ad 5718 rtl8169_doorbell(tp);
ef143585
HK		 5719
5720 if (unlikely(stop_queue)) {
ae1f23fb
FR		 5721 /* Sync with rtl_tx:
5722 * - publish queue status and cur_tx ring index (write barrier)
5723 * - refresh dirty_tx ring index (read barrier).
5724 * May the current thread have a pessimistic view of the ring
5725 * status and forget to wake up queue, a racing rtl_tx thread
5726 * can't.
5727 */
1e874e04 5728 smp_mb();
76085c9e 5729 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
601ed4d6 5730 netif_start_queue(dev);
1da177e4
LT		 5731 }
5732
61357325 5733 return NETDEV_TX_OK;
1da177e4 5734
3eafe507 5735err_dma_1:
48addcc9 5736 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507 5737err_dma_0:
989c9ba1 5738 dev_kfree_skb_any(skb);
3eafe507
SG		 5739 dev->stats.tx_dropped++;
5740 return NETDEV_TX_OK;
5741
5742err_stop_0:
1da177e4 5743 netif_stop_queue(dev);
cebf8cc7 5744 dev->stats.tx_dropped++;
61357325 5745 return NETDEV_TX_BUSY;
1da177e4
LT		 5746}
5747
e64e0c89
HK		 5748static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
5749 struct net_device *dev,
5750 netdev_features_t features)
5751{
5752 int transport_offset = skb_transport_offset(skb);
5753 struct rtl8169_private *tp = netdev_priv(dev);
5754
5755 if (skb_is_gso(skb)) {
5756 if (transport_offset > GTTCPHO_MAX &&
5757 rtl_chip_supports_csum_v2(tp))
5758 features &= ~NETIF_F_ALL_TSO;
5759 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5760 if (skb->len < ETH_ZLEN) {
5761 switch (tp->mac_version) {
5762 case RTL_GIGA_MAC_VER_11:
5763 case RTL_GIGA_MAC_VER_12:
5764 case RTL_GIGA_MAC_VER_17:
5765 case RTL_GIGA_MAC_VER_34:
5766 features &= ~NETIF_F_CSUM_MASK;
5767 break;
5768 default:
5769 break;
5770 }
5771 }
5772
5773 if (transport_offset > TCPHO_MAX &&
5774 rtl_chip_supports_csum_v2(tp))
5775 features &= ~NETIF_F_CSUM_MASK;
5776 }
5777
5778 return vlan_features_check(skb, features);
5779}
5780
1da177e4
LT		 5781static void rtl8169_pcierr_interrupt(struct net_device *dev)
5782{
5783 struct rtl8169_private *tp = netdev_priv(dev);
5784 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 5785 u16 pci_status, pci_cmd;
5786
5787 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5788 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5789
bf82c189
JP		 5790 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5791 pci_cmd, pci_status);
1da177e4
LT		 5792
5793 /*
5794 * The recovery sequence below admits a very elaborated explanation:
5795 * - it seems to work;
d03902b8
FR		 5796 * - I did not see what else could be done;
5797 * - it makes iop3xx happy.
1da177e4
LT		 5798 *
5799 * Feel free to adjust to your needs.
5800 */
a27993f3 5801 if (pdev->broken_parity_status)
d03902b8
FR		 5802 pci_cmd &= ~PCI_COMMAND_PARITY;
5803 else
5804 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5805
5806 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 5807
5808 pci_write_config_word(pdev, PCI_STATUS,
5809 pci_status & (PCI_STATUS_DETECTED_PARITY |
5810 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5811 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5812
98ddf986 5813 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5814}
5815
5317d5c6
HK		 5816static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
5817 int budget)
1da177e4 5818{
d92060bc 5819 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
1da177e4 5820
1da177e4
LT		 5821 dirty_tx = tp->dirty_tx;
5822 smp_rmb();
5823 tx_left = tp->cur_tx - dirty_tx;
5824
5825 while (tx_left > 0) {
5826 unsigned int entry = dirty_tx % NUM_TX_DESC;
5827 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 5828 u32 status;
5829
1da177e4
LT		 5830 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5831 if (status & DescOwn)
5832 break;
5833
a0750138
AD		 5834 /* This barrier is needed to keep us from reading
5835 * any other fields out of the Tx descriptor until
5836 * we know the status of DescOwn
5837 */
5838 dma_rmb();
5839
1e1205b7 5840 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
48addcc9 5841 tp->TxDescArray + entry);
ae84bc18 5842 if (tx_skb->skb) {
d92060bc
FW		 5843 pkts_compl++;
5844 bytes_compl += tx_skb->skb->len;
5317d5c6 5845 napi_consume_skb(tx_skb->skb, budget);
1da177e4
LT		 5846 tx_skb->skb = NULL;
5847 }
5848 dirty_tx++;
5849 tx_left--;
5850 }
5851
5852 if (tp->dirty_tx != dirty_tx) {
d92060bc
FW		 5853 netdev_completed_queue(dev, pkts_compl, bytes_compl);
5854
5855 u64_stats_update_begin(&tp->tx_stats.syncp);
5856 tp->tx_stats.packets += pkts_compl;
5857 tp->tx_stats.bytes += bytes_compl;
5858 u64_stats_update_end(&tp->tx_stats.syncp);
5859
1da177e4 5860 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 5861 /* Sync with rtl8169_start_xmit:
5862 * - publish dirty_tx ring index (write barrier)
5863 * - refresh cur_tx ring index and queue status (read barrier)
5864 * May the current thread miss the stopped queue condition,
5865 * a racing xmit thread can only have a right view of the
5866 * ring status.
5867 */
1e874e04 5868 smp_mb();
1da177e4 5869 if (netif_queue_stopped(dev) &&
76085c9e 5870 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 5871 netif_wake_queue(dev);
5872 }
d78ae2dc
FR		 5873 /*
5874 * 8168 hack: TxPoll requests are lost when the Tx packets are
5875 * too close. Let's kick an extra TxPoll request when a burst
5876 * of start_xmit activity is detected (if it is not detected,
5877 * it is slow enough). -- FR
5878 */
1ef7286e 5879 if (tp->cur_tx != dirty_tx)
f1bce4ad 5880 rtl8169_doorbell(tp);
1da177e4
LT		 5881 }
5882}
5883
126fa4b9
FR		 5884static inline int rtl8169_fragmented_frame(u32 status)
5885{
5886 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5887}
5888
adea1ac7 5889static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 5890{
1da177e4
LT		 5891 u32 status = opts1 & RxProtoMask;
5892
5893 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 5894 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 5895 skb->ip_summed = CHECKSUM_UNNECESSARY;
5896 else
bc8acf2c 5897 skb_checksum_none_assert(skb);
1da177e4
LT		 5898}
5899
da78dbff 5900static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 5901{
5902 unsigned int cur_rx, rx_left;
6f0333b8 5903 unsigned int count;
1da177e4 5904
1da177e4 5905 cur_rx = tp->cur_rx;
1da177e4 5906
9fba0812 5907 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 5908 unsigned int entry = cur_rx % NUM_RX_DESC;
32879f00 5909 const void *rx_buf = page_address(tp->Rx_databuff[entry]);
126fa4b9 5910 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 5911 u32 status;
5912
6202806e 5913 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 5914 if (status & DescOwn)
5915 break;
a0750138
AD		 5916
5917 /* This barrier is needed to keep us from reading
5918 * any other fields out of the Rx descriptor until
5919 * we know the status of DescOwn
5920 */
5921 dma_rmb();
5922
4dcb7d33 5923 if (unlikely(status & RxRES)) {
bf82c189
JP		 5924 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5925 status);
cebf8cc7 5926 dev->stats.rx_errors++;
1da177e4 5927 if (status & (RxRWT | RxRUNT))
cebf8cc7 5928 dev->stats.rx_length_errors++;
1da177e4 5929 if (status & RxCRC)
cebf8cc7 5930 dev->stats.rx_crc_errors++;
e9588eb9
HK		 5931 if (status & (RxRUNT | RxCRC) && !(status & RxRWT) &&
5932 dev->features & NETIF_F_RXALL) {
6bbe021d 5933 goto process_pkt;
6202806e 5934 }
1da177e4 5935 } else {
fcd4e608 5936 unsigned int pkt_size;
6f0333b8 5937 struct sk_buff *skb;
6bbe021d
BG		 5938
5939process_pkt:
fcd4e608 5940 pkt_size = status & GENMASK(13, 0);
79d0c1d2 5941 if (likely(!(dev->features & NETIF_F_RXFCS)))
fcd4e608 5942 pkt_size -= ETH_FCS_LEN;
126fa4b9
FR		 5943 /*
5944 * The driver does not support incoming fragmented
5945 * frames. They are seen as a symptom of over-mtu
5946 * sized frames.
5947 */
5948 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 5949 dev->stats.rx_dropped++;
5950 dev->stats.rx_length_errors++;
ce11ff5e 5951 goto release_descriptor;
126fa4b9
FR		 5952 }
5953
fcd4e608
HK		 5954 skb = napi_alloc_skb(&tp->napi, pkt_size);
5955 if (unlikely(!skb)) {
6f0333b8 5956 dev->stats.rx_dropped++;
ce11ff5e 5957 goto release_descriptor;
1da177e4
LT		 5958 }
5959
3c95e501
HK		 5960 dma_sync_single_for_cpu(tp_to_dev(tp),
5961 le64_to_cpu(desc->addr),
5962 pkt_size, DMA_FROM_DEVICE);
32879f00
HK		 5963 prefetch(rx_buf);
5964 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
fcd4e608
HK		 5965 skb->tail += pkt_size;
5966 skb->len = pkt_size;
5967
d4ed7463
HK		 5968 dma_sync_single_for_device(tp_to_dev(tp),
5969 le64_to_cpu(desc->addr),
5970 pkt_size, DMA_FROM_DEVICE);
5971
adea1ac7 5972 rtl8169_rx_csum(skb, status);
1da177e4
LT		 5973 skb->protocol = eth_type_trans(skb, dev);
5974
7a8fc77b
FR		 5975 rtl8169_rx_vlan_tag(desc, skb);
5976
39174291 5977 if (skb->pkt_type == PACKET_MULTICAST)
5978 dev->stats.multicast++;
5979
448a2413 5980 napi_gro_receive(&tp->napi, skb);
1da177e4 5981
8027aa24
JW		 5982 u64_stats_update_begin(&tp->rx_stats.syncp);
5983 tp->rx_stats.packets++;
5984 tp->rx_stats.bytes += pkt_size;
5985 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 5986 }
ce11ff5e 5987release_descriptor:
5988 desc->opts2 = 0;
1d0254dd 5989 rtl8169_mark_to_asic(desc);
1da177e4
LT		 5990 }
5991
5992 count = cur_rx - tp->cur_rx;
5993 tp->cur_rx = cur_rx;
5994
1da177e4
LT		 5995 return count;
5996}
5997
07d3f51f 5998static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 5999{
ebcd5daa 6000 struct rtl8169_private *tp = dev_instance;
c1d532d2 6001 u32 status = rtl_get_events(tp);
1da177e4 6002
c1d532d2
HK		 6003 if (!tp->irq_enabled || (status & 0xffff) == 0xffff ||
6004 !(status & tp->irq_mask))
05bbe558 6005 return IRQ_NONE;
1da177e4 6006
38caff5a
HK		 6007 if (unlikely(status & SYSErr)) {
6008 rtl8169_pcierr_interrupt(tp->dev);
6009 goto out;
6010 }
da78dbff 6011
703732f0
HK		 6012 if (status & LinkChg)
6013 phy_mac_interrupt(tp->phydev);
1da177e4 6014
38caff5a
HK		 6015 if (unlikely(status & RxFIFOOver &&
6016 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6017 netif_stop_queue(tp->dev);
6018 /* XXX - Hack alert. See rtl_task(). */
6019 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 6020 }
1da177e4 6021
e62b2fd5
HK		 6022 rtl_irq_disable(tp);
6023 napi_schedule_irqoff(&tp->napi);
38caff5a
HK		 6024out:
6025 rtl_ack_events(tp, status);
1da177e4 6026
38caff5a 6027 return IRQ_HANDLED;
1da177e4
LT		 6028}
6029
4422bcd4
FR		 6030static void rtl_task(struct work_struct *work)
6031{
da78dbff
FR		 6032 static const struct {
6033 int bitnr;
6034 void (*action)(struct rtl8169_private *);
6035 } rtl_work[] = {
da78dbff 6036 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
da78dbff 6037 };
4422bcd4
FR		 6038 struct rtl8169_private *tp =
6039 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 6040 struct net_device *dev = tp->dev;
6041 int i;
6042
6043 rtl_lock_work(tp);
6044
6c4a70c5
FR		 6045 if (!netif_running(dev) ||
6046 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 6047 goto out_unlock;
6048
6049 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6050 bool pending;
6051
da78dbff 6052 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 6053 if (pending)
6054 rtl_work[i].action(tp);
6055 }
4422bcd4 6056
da78dbff
FR		 6057out_unlock:
6058 rtl_unlock_work(tp);
4422bcd4
FR		 6059}
6060
bea3348e 6061static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 6062{
bea3348e
SH		 6063 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6064 struct net_device *dev = tp->dev;
6b839b6c 6065 int work_done;
da78dbff 6066
6b839b6c 6067 work_done = rtl_rx(dev, tp, (u32) budget);
da78dbff 6068
5317d5c6 6069 rtl_tx(dev, tp, budget);
1da177e4 6070
bea3348e 6071 if (work_done < budget) {
6ad20165 6072 napi_complete_done(napi, work_done);
fe716f8a 6073 rtl_irq_enable(tp);
1da177e4
LT		 6074 }
6075
bea3348e 6076 return work_done;
1da177e4 6077}
1da177e4 6078
1ef7286e 6079static void rtl8169_rx_missed(struct net_device *dev)
523a6094
FR		 6080{
6081 struct rtl8169_private *tp = netdev_priv(dev);
6082
6083 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6084 return;
6085
1ef7286e
AS		 6086 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6087 RTL_W32(tp, RxMissed, 0);
523a6094
FR		 6088}
6089
f1e911d5
HK		 6090static void r8169_phylink_handler(struct net_device *ndev)
6091{
6092 struct rtl8169_private *tp = netdev_priv(ndev);
6093
6094 if (netif_carrier_ok(ndev)) {
6095 rtl_link_chg_patch(tp);
6096 pm_request_resume(&tp->pci_dev->dev);
6097 } else {
6098 pm_runtime_idle(&tp->pci_dev->dev);
6099 }
6100
6101 if (net_ratelimit())
703732f0 6102 phy_print_status(tp->phydev);
f1e911d5
HK		 6103}
6104
6105static int r8169_phy_connect(struct rtl8169_private *tp)
6106{
703732f0 6107 struct phy_device *phydev = tp->phydev;
f1e911d5
HK		 6108 phy_interface_t phy_mode;
6109 int ret;
6110
f7ffa9ae 6111 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
f1e911d5
HK		 6112 PHY_INTERFACE_MODE_MII;
6113
6114 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6115 phy_mode);
6116 if (ret)
6117 return ret;
6118
66058b1c 6119 if (!tp->supports_gmii)
f1e911d5
HK		 6120 phy_set_max_speed(phydev, SPEED_100);
6121
9cf9b84c 6122 phy_support_asym_pause(phydev);
f1e911d5
HK		 6123
6124 phy_attached_info(phydev);
6125
6126 return 0;
6127}
6128
1da177e4
LT		 6129static void rtl8169_down(struct net_device *dev)
6130{
6131 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 6132
703732f0 6133 phy_stop(tp->phydev);
f1e911d5 6134
93dd79e8 6135 napi_disable(&tp->napi);
da78dbff 6136 netif_stop_queue(dev);
1da177e4 6137
92fc43b4 6138 rtl8169_hw_reset(tp);
323bb685
SG		 6139 /*
6140 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 6141 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6142 * and napi is disabled (rtl8169_poll).
323bb685 6143 */
1ef7286e 6144 rtl8169_rx_missed(dev);
1da177e4 6145
1da177e4 6146 /* Give a racing hard_start_xmit a few cycles to complete. */
16f11500 6147 synchronize_rcu();
1da177e4 6148
1da177e4
LT		 6149 rtl8169_tx_clear(tp);
6150
6151 rtl8169_rx_clear(tp);
065c27c1 6152
6153 rtl_pll_power_down(tp);
1da177e4
LT		 6154}
6155
6156static int rtl8169_close(struct net_device *dev)
6157{
6158 struct rtl8169_private *tp = netdev_priv(dev);
6159 struct pci_dev *pdev = tp->pci_dev;
6160
e1759441
RW		 6161 pm_runtime_get_sync(&pdev->dev);
6162
cecb5fd7 6163 /* Update counters before going down */
e71c9ce2 6164 rtl8169_update_counters(tp);
355423d0 6165
da78dbff 6166 rtl_lock_work(tp);
6ad56901
KHF		 6167 /* Clear all task flags */
6168 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
da78dbff 6169
1da177e4 6170 rtl8169_down(dev);
da78dbff 6171 rtl_unlock_work(tp);
1da177e4 6172
4ea72445
L		 6173 cancel_work_sync(&tp->wk.work);
6174
703732f0 6175 phy_disconnect(tp->phydev);
f1e911d5 6176
ebcd5daa 6177 pci_free_irq(pdev, 0, tp);
1da177e4 6178
82553bb6
SG		 6179 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6180 tp->RxPhyAddr);
6181 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6182 tp->TxPhyAddr);
1da177e4
LT		 6183 tp->TxDescArray = NULL;
6184 tp->RxDescArray = NULL;
6185
e1759441
RW		 6186 pm_runtime_put_sync(&pdev->dev);
6187
1da177e4
LT		 6188 return 0;
6189}
6190
dc1c00ce
FR		 6191#ifdef CONFIG_NET_POLL_CONTROLLER
6192static void rtl8169_netpoll(struct net_device *dev)
6193{
6194 struct rtl8169_private *tp = netdev_priv(dev);
6195
6d8b8349 6196 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
dc1c00ce
FR		 6197}
6198#endif
6199
df43ac78
FR		 6200static int rtl_open(struct net_device *dev)
6201{
6202 struct rtl8169_private *tp = netdev_priv(dev);
df43ac78
FR		 6203 struct pci_dev *pdev = tp->pci_dev;
6204 int retval = -ENOMEM;
6205
6206 pm_runtime_get_sync(&pdev->dev);
6207
6208 /*
e75d6606 6209 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 6210 * dma_alloc_coherent provides more.
6211 */
6212 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6213 &tp->TxPhyAddr, GFP_KERNEL);
6214 if (!tp->TxDescArray)
6215 goto err_pm_runtime_put;
6216
6217 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6218 &tp->RxPhyAddr, GFP_KERNEL);
6219 if (!tp->RxDescArray)
6220 goto err_free_tx_0;
6221
b1127e64 6222 retval = rtl8169_init_ring(tp);
df43ac78
FR		 6223 if (retval < 0)
6224 goto err_free_rx_1;
6225
df43ac78
FR		 6226 rtl_request_firmware(tp);
6227
ebcd5daa 6228 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6c6aa15f 6229 dev->name);
df43ac78
FR		 6230 if (retval < 0)
6231 goto err_release_fw_2;
6232
f1e911d5
HK		 6233 retval = r8169_phy_connect(tp);
6234 if (retval)
6235 goto err_free_irq;
6236
df43ac78
FR		 6237 rtl_lock_work(tp);
6238
6239 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6240
6241 napi_enable(&tp->napi);
6242
6243 rtl8169_init_phy(dev, tp);
6244
df43ac78
FR		 6245 rtl_pll_power_up(tp);
6246
61cb532d 6247 rtl_hw_start(tp);
df43ac78 6248
e71c9ce2 6249 if (!rtl8169_init_counter_offsets(tp))
6e85d5ad
CV		 6250 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6251
703732f0 6252 phy_start(tp->phydev);
df43ac78
FR		 6253 netif_start_queue(dev);
6254
6255 rtl_unlock_work(tp);
6256
a92a0849 6257 pm_runtime_put_sync(&pdev->dev);
df43ac78
FR		 6258out:
6259 return retval;
6260
f1e911d5
HK		 6261err_free_irq:
6262 pci_free_irq(pdev, 0, tp);
df43ac78
FR		 6263err_release_fw_2:
6264 rtl_release_firmware(tp);
6265 rtl8169_rx_clear(tp);
6266err_free_rx_1:
6267 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6268 tp->RxPhyAddr);
6269 tp->RxDescArray = NULL;
6270err_free_tx_0:
6271 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6272 tp->TxPhyAddr);
6273 tp->TxDescArray = NULL;
6274err_pm_runtime_put:
6275 pm_runtime_put_noidle(&pdev->dev);
6276 goto out;
6277}
6278
bc1f4470 6279static void
8027aa24 6280rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 6281{
6282 struct rtl8169_private *tp = netdev_priv(dev);
f09cf4b7 6283 struct pci_dev *pdev = tp->pci_dev;
42020320 6284 struct rtl8169_counters *counters = tp->counters;
8027aa24 6285 unsigned int start;
1da177e4 6286
f09cf4b7
CHL		 6287 pm_runtime_get_noresume(&pdev->dev);
6288
6289 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
1ef7286e 6290 rtl8169_rx_missed(dev);
5b0384f4 6291
8027aa24 6292 do {
57a7744e 6293 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
8027aa24
JW		 6294 stats->rx_packets = tp->rx_stats.packets;
6295 stats->rx_bytes = tp->rx_stats.bytes;
57a7744e 6296 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
8027aa24 6297
8027aa24 6298 do {
57a7744e 6299 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
8027aa24
JW		 6300 stats->tx_packets = tp->tx_stats.packets;
6301 stats->tx_bytes = tp->tx_stats.bytes;
57a7744e 6302 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
8027aa24
JW		 6303
6304 stats->rx_dropped = dev->stats.rx_dropped;
6305 stats->tx_dropped = dev->stats.tx_dropped;
6306 stats->rx_length_errors = dev->stats.rx_length_errors;
6307 stats->rx_errors = dev->stats.rx_errors;
6308 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6309 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6310 stats->rx_missed_errors = dev->stats.rx_missed_errors;
d7d2d89d 6311 stats->multicast = dev->stats.multicast;
8027aa24 6312
6e85d5ad 6313 /*
ed72a9bb 6314 * Fetch additional counter values missing in stats collected by driver
6e85d5ad
CV		 6315 * from tally counters.
6316 */
f09cf4b7 6317 if (pm_runtime_active(&pdev->dev))
e71c9ce2 6318 rtl8169_update_counters(tp);
6e85d5ad
CV		 6319
6320 /*
6321 * Subtract values fetched during initalization.
6322 * See rtl8169_init_counter_offsets for a description why we do that.
6323 */
42020320 6324 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6e85d5ad 6325 le64_to_cpu(tp->tc_offset.tx_errors);
42020320 6326 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6e85d5ad 6327 le32_to_cpu(tp->tc_offset.tx_multi_collision);
42020320 6328 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6e85d5ad
CV		 6329 le16_to_cpu(tp->tc_offset.tx_aborted);
6330
f09cf4b7 6331 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 6332}
6333
861ab440 6334static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 6335{
065c27c1 6336 struct rtl8169_private *tp = netdev_priv(dev);
6337
5d06a99f 6338 if (!netif_running(dev))
861ab440 6339 return;
5d06a99f 6340
703732f0 6341 phy_stop(tp->phydev);
5d06a99f 6342 netif_device_detach(dev);
da78dbff
FR		 6343
6344 rtl_lock_work(tp);
6345 napi_disable(&tp->napi);
6ad56901
KHF		 6346 /* Clear all task flags */
6347 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6348
da78dbff
FR		 6349 rtl_unlock_work(tp);
6350
6351 rtl_pll_power_down(tp);
861ab440
RW		 6352}
6353
6354#ifdef CONFIG_PM
6355
6356static int rtl8169_suspend(struct device *device)
6357{
0f07bd85 6358 struct net_device *dev = dev_get_drvdata(device);
ac8bd9e1 6359 struct rtl8169_private *tp = netdev_priv(dev);
5d06a99f 6360
861ab440 6361 rtl8169_net_suspend(dev);
ac8bd9e1 6362 clk_disable_unprepare(tp->clk);
1371fa6d 6363
5d06a99f
FR		 6364 return 0;
6365}
6366
e1759441
RW		 6367static void __rtl8169_resume(struct net_device *dev)
6368{
065c27c1 6369 struct rtl8169_private *tp = netdev_priv(dev);
6370
e1759441 6371 netif_device_attach(dev);
065c27c1 6372
6373 rtl_pll_power_up(tp);
92bad850 6374 rtl8169_init_phy(dev, tp);
065c27c1 6375
703732f0 6376 phy_start(tp->phydev);
f1e911d5 6377
cff4c162
AS		 6378 rtl_lock_work(tp);
6379 napi_enable(&tp->napi);
6c4a70c5 6380 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
58ba566c 6381 rtl_reset_work(tp);
cff4c162 6382 rtl_unlock_work(tp);
e1759441
RW		 6383}
6384
861ab440 6385static int rtl8169_resume(struct device *device)
5d06a99f 6386{
0f07bd85 6387 struct net_device *dev = dev_get_drvdata(device);
ac8bd9e1
HG		 6388 struct rtl8169_private *tp = netdev_priv(dev);
6389
59715171
HK		 6390 rtl_rar_set(tp, dev->dev_addr);
6391
ac8bd9e1 6392 clk_prepare_enable(tp->clk);
5d06a99f 6393
e1759441
RW		 6394 if (netif_running(dev))
6395 __rtl8169_resume(dev);
5d06a99f 6396
e1759441
RW		 6397 return 0;
6398}
6399
6400static int rtl8169_runtime_suspend(struct device *device)
6401{
0f07bd85 6402 struct net_device *dev = dev_get_drvdata(device);
e1759441
RW		 6403 struct rtl8169_private *tp = netdev_priv(dev);
6404
07df5bd8 6405 if (!tp->TxDescArray)
e1759441
RW		 6406 return 0;
6407
da78dbff 6408 rtl_lock_work(tp);
e1759441 6409 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 6410 rtl_unlock_work(tp);
e1759441
RW		 6411
6412 rtl8169_net_suspend(dev);
6413
f09cf4b7 6414 /* Update counters before going runtime suspend */
1ef7286e 6415 rtl8169_rx_missed(dev);
e71c9ce2 6416 rtl8169_update_counters(tp);
f09cf4b7 6417
e1759441
RW		 6418 return 0;
6419}
6420
6421static int rtl8169_runtime_resume(struct device *device)
6422{
0f07bd85 6423 struct net_device *dev = dev_get_drvdata(device);
e1759441 6424 struct rtl8169_private *tp = netdev_priv(dev);
59715171 6425
f51d4a10 6426 rtl_rar_set(tp, dev->dev_addr);
e1759441
RW		 6427
6428 if (!tp->TxDescArray)
6429 return 0;
6430
da78dbff 6431 rtl_lock_work(tp);
e1759441 6432 __rtl8169_set_wol(tp, tp->saved_wolopts);
da78dbff 6433 rtl_unlock_work(tp);
e1759441
RW		 6434
6435 __rtl8169_resume(dev);
5d06a99f 6436
5d06a99f
FR		 6437 return 0;
6438}
6439
e1759441
RW		 6440static int rtl8169_runtime_idle(struct device *device)
6441{
0f07bd85 6442 struct net_device *dev = dev_get_drvdata(device);
e1759441 6443
a92a0849
HK		 6444 if (!netif_running(dev) || !netif_carrier_ok(dev))
6445 pm_schedule_suspend(device, 10000);
6446
6447 return -EBUSY;
e1759441
RW		 6448}
6449
47145210 6450static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 6451 .suspend = rtl8169_suspend,
6452 .resume = rtl8169_resume,
6453 .freeze = rtl8169_suspend,
6454 .thaw = rtl8169_resume,
6455 .poweroff = rtl8169_suspend,
6456 .restore = rtl8169_resume,
6457 .runtime_suspend = rtl8169_runtime_suspend,
6458 .runtime_resume = rtl8169_runtime_resume,
6459 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 6460};
6461
6462#define RTL8169_PM_OPS (&rtl8169_pm_ops)
6463
6464#else /* !CONFIG_PM */
6465
6466#define RTL8169_PM_OPS NULL
6467
6468#endif /* !CONFIG_PM */
6469
649b3b8c 6470static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6471{
649b3b8c 6472 /* WoL fails with 8168b when the receiver is disabled. */
6473 switch (tp->mac_version) {
6474 case RTL_GIGA_MAC_VER_11:
6475 case RTL_GIGA_MAC_VER_12:
6476 case RTL_GIGA_MAC_VER_17:
6477 pci_clear_master(tp->pci_dev);
6478
1ef7286e 6479 RTL_W8(tp, ChipCmd, CmdRxEnb);
649b3b8c 6480 /* PCI commit */
1ef7286e 6481 RTL_R8(tp, ChipCmd);
649b3b8c 6482 break;
6483 default:
6484 break;
6485 }
6486}
6487
1765f95d
FR		 6488static void rtl_shutdown(struct pci_dev *pdev)
6489{
861ab440 6490 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 6491 struct rtl8169_private *tp = netdev_priv(dev);
861ab440
RW		 6492
6493 rtl8169_net_suspend(dev);
1765f95d 6494
cecb5fd7 6495 /* Restore original MAC address */
cc098dc7
IV		 6496 rtl_rar_set(tp, dev->perm_addr);
6497
92fc43b4 6498 rtl8169_hw_reset(tp);
4bb3f522 6499
861ab440 6500 if (system_state == SYSTEM_POWER_OFF) {
433f9d0d 6501 if (tp->saved_wolopts) {
649b3b8c 6502 rtl_wol_suspend_quirk(tp);
6503 rtl_wol_shutdown_quirk(tp);
ca52efd5 6504 }
6505
861ab440
RW		 6506 pci_wake_from_d3(pdev, true);
6507 pci_set_power_state(pdev, PCI_D3hot);
6508 }
6509}
5d06a99f 6510
baf63293 6511static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 6512{
6513 struct net_device *dev = pci_get_drvdata(pdev);
6514 struct rtl8169_private *tp = netdev_priv(dev);
6515
9dbe7896 6516 if (r8168_check_dash(tp))
e27566ed 6517 rtl8168_driver_stop(tp);
e27566ed 6518
ad1be8d3
DN		 6519 netif_napi_del(&tp->napi);
6520
e27566ed 6521 unregister_netdev(dev);
703732f0 6522 mdiobus_unregister(tp->phydev->mdio.bus);
e27566ed
FR		 6523
6524 rtl_release_firmware(tp);
6525
6526 if (pci_dev_run_wake(pdev))
6527 pm_runtime_get_noresume(&pdev->dev);
6528
6529 /* restore original MAC address */
6530 rtl_rar_set(tp, dev->perm_addr);
e27566ed
FR		 6531}
6532
fa9c385e 6533static const struct net_device_ops rtl_netdev_ops = {
df43ac78 6534 .ndo_open = rtl_open,
fa9c385e
FR		 6535 .ndo_stop = rtl8169_close,
6536 .ndo_get_stats64 = rtl8169_get_stats64,
6537 .ndo_start_xmit = rtl8169_start_xmit,
e64e0c89 6538 .ndo_features_check = rtl8169_features_check,
fa9c385e
FR		 6539 .ndo_tx_timeout = rtl8169_tx_timeout,
6540 .ndo_validate_addr = eth_validate_addr,
6541 .ndo_change_mtu = rtl8169_change_mtu,
6542 .ndo_fix_features = rtl8169_fix_features,
6543 .ndo_set_features = rtl8169_set_features,
6544 .ndo_set_mac_address = rtl_set_mac_address,
6545 .ndo_do_ioctl = rtl8169_ioctl,
6546 .ndo_set_rx_mode = rtl_set_rx_mode,
6547#ifdef CONFIG_NET_POLL_CONTROLLER
6548 .ndo_poll_controller = rtl8169_netpoll,
6549#endif
6550
6551};
6552
ec9a4088
HK		 6553static void rtl_set_irq_mask(struct rtl8169_private *tp)
6554{
6555 tp->irq_mask = RTL_EVENT_NAPI | LinkChg;
6556
6557 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6558 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
6559 else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
6560 /* special workaround needed */
6561 tp->irq_mask |= RxFIFOOver;
6562 else
6563 tp->irq_mask |= RxOverflow;
6564}
6565
6c6aa15f 6566static int rtl_alloc_irq(struct rtl8169_private *tp)
31fa8b18 6567{
6c6aa15f 6568 unsigned int flags;
31fa8b18 6569
003bd5b4
HK		 6570 switch (tp->mac_version) {
6571 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
df320ed7 6572 rtl_unlock_config_regs(tp);
1ef7286e 6573 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
df320ed7 6574 rtl_lock_config_regs(tp);
003bd5b4
HK		 6575 /* fall through */
6576 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_24:
6c6aa15f 6577 flags = PCI_IRQ_LEGACY;
003bd5b4
HK		 6578 break;
6579 default:
6c6aa15f 6580 flags = PCI_IRQ_ALL_TYPES;
003bd5b4 6581 break;
31fa8b18 6582 }
6c6aa15f
HK		 6583
6584 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
31fa8b18
FR		 6585}
6586
04c7788c
TR		 6587static void rtl_read_mac_address(struct rtl8169_private *tp,
6588 u8 mac_addr[ETH_ALEN])
6589{
6590 /* Get MAC address */
9e9f33ba
HK		 6591 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
6592 u32 value = rtl_eri_read(tp, 0xe0);
6593
deedf1fe
TR		 6594 mac_addr[0] = (value >> 0) & 0xff;
6595 mac_addr[1] = (value >> 8) & 0xff;
6596 mac_addr[2] = (value >> 16) & 0xff;
6597 mac_addr[3] = (value >> 24) & 0xff;
6598
724c6fd0 6599 value = rtl_eri_read(tp, 0xe4);
deedf1fe
TR		 6600 mac_addr[4] = (value >> 0) & 0xff;
6601 mac_addr[5] = (value >> 8) & 0xff;
f1bce4ad
HK		 6602 } else if (rtl_is_8125(tp)) {
6603 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
04c7788c
TR		 6604 }
6605}
6606
c558386b
HW		 6607DECLARE_RTL_COND(rtl_link_list_ready_cond)
6608{
1ef7286e 6609 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
c558386b
HW		 6610}
6611
6612DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6613{
1ef7286e 6614 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
c558386b
HW		 6615}
6616
f1e911d5
HK		 6617static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6618{
6619 struct rtl8169_private *tp = mii_bus->priv;
6620
6621 if (phyaddr > 0)
6622 return -ENODEV;
6623
6624 return rtl_readphy(tp, phyreg);
6625}
6626
6627static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6628 int phyreg, u16 val)
6629{
6630 struct rtl8169_private *tp = mii_bus->priv;
6631
6632 if (phyaddr > 0)
6633 return -ENODEV;
6634
6635 rtl_writephy(tp, phyreg, val);
6636
6637 return 0;
6638}
6639
6640static int r8169_mdio_register(struct rtl8169_private *tp)
6641{
6642 struct pci_dev *pdev = tp->pci_dev;
f1e911d5
HK		 6643 struct mii_bus *new_bus;
6644 int ret;
6645
6646 new_bus = devm_mdiobus_alloc(&pdev->dev);
6647 if (!new_bus)
6648 return -ENOMEM;
6649
6650 new_bus->name = "r8169";
6651 new_bus->priv = tp;
6652 new_bus->parent = &pdev->dev;
6653 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
a195016a 6654 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
f1e911d5
HK		 6655
6656 new_bus->read = r8169_mdio_read_reg;
6657 new_bus->write = r8169_mdio_write_reg;
6658
6659 ret = mdiobus_register(new_bus);
6660 if (ret)
6661 return ret;
6662
703732f0
HK		 6663 tp->phydev = mdiobus_get_phy(new_bus, 0);
6664 if (!tp->phydev) {
f1e911d5
HK		 6665 mdiobus_unregister(new_bus);
6666 return -ENODEV;
6667 }
6668
242cd9b5 6669 /* PHY will be woken up in rtl_open() */
703732f0 6670 phy_suspend(tp->phydev);
f1e911d5
HK		 6671
6672 return 0;
6673}
6674
baf63293 6675static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b 6676{
c558386b
HW		 6677 tp->ocp_base = OCP_STD_PHY_BASE;
6678
1ef7286e 6679 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
c558386b
HW		 6680
6681 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6682 return;
6683
6684 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6685 return;
6686
1ef7286e 6687 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
c558386b 6688 msleep(1);
1ef7286e 6689 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
c558386b 6690
ef712ede 6691 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
c558386b
HW		 6692
6693 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6694 return;
6695
ef712ede 6696 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
c558386b 6697
7160be2d 6698 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
c558386b
HW		 6699}
6700
f1bce4ad
HK		 6701static void rtl_hw_init_8125(struct rtl8169_private *tp)
6702{
6703 tp->ocp_base = OCP_STD_PHY_BASE;
6704
6705 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6706
6707 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6708 return;
6709
6710 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6711 msleep(1);
6712 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6713
6714 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
6715
6716 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6717 return;
6718
6719 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
6720 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
6721 r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
6722
6723 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6724}
6725
baf63293 6726static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 6727{
6728 switch (tp->mac_version) {
1287723a 6729 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
29ec0482
HK		 6730 rtl8168ep_stop_cmac(tp);
6731 /* fall through */
2a71883c 6732 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
003609da
CHL		 6733 rtl_hw_init_8168g(tp);
6734 break;
f1bce4ad
HK		 6735 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
6736 rtl_hw_init_8125(tp);
6737 break;
c558386b
HW		 6738 default:
6739 break;
6740 }
6741}
6742
abe8b2f7
HK		 6743static int rtl_jumbo_max(struct rtl8169_private *tp)
6744{
6745 /* Non-GBit versions don't support jumbo frames */
6746 if (!tp->supports_gmii)
6747 return JUMBO_1K;
6748
6749 switch (tp->mac_version) {
6750 /* RTL8169 */
e9588eb9 6751 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
abe8b2f7
HK		 6752 return JUMBO_7K;
6753 /* RTL8168b */
6754 case RTL_GIGA_MAC_VER_11:
6755 case RTL_GIGA_MAC_VER_12:
6756 case RTL_GIGA_MAC_VER_17:
6757 return JUMBO_4K;
6758 /* RTL8168c */
6759 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
6760 return JUMBO_6K;
6761 default:
6762 return JUMBO_9K;
6763 }
6764}
6765
c2f6f3ee
HG		 6766static void rtl_disable_clk(void *data)
6767{
6768 clk_disable_unprepare(data);
6769}
6770
b779daea
HK		 6771static int rtl_get_ether_clk(struct rtl8169_private *tp)
6772{
6773 struct device *d = tp_to_dev(tp);
6774 struct clk *clk;
6775 int rc;
6776
6777 clk = devm_clk_get(d, "ether_clk");
6778 if (IS_ERR(clk)) {
6779 rc = PTR_ERR(clk);
6780 if (rc == -ENOENT)
6781 /* clk-core allows NULL (for suspend / resume) */
6782 rc = 0;
6783 else if (rc != -EPROBE_DEFER)
6784 dev_err(d, "failed to get clk: %d\n", rc);
6785 } else {
6786 tp->clk = clk;
6787 rc = clk_prepare_enable(clk);
6788 if (rc)
6789 dev_err(d, "failed to enable clk: %d\n", rc);
6790 else
6791 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
6792 }
6793
6794 return rc;
6795}
6796
c782e204
HK		 6797static void rtl_init_mac_address(struct rtl8169_private *tp)
6798{
6799 struct net_device *dev = tp->dev;
6800 u8 *mac_addr = dev->dev_addr;
ce37115e 6801 int rc;
c782e204
HK		 6802
6803 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
6804 if (!rc)
6805 goto done;
6806
6807 rtl_read_mac_address(tp, mac_addr);
6808 if (is_valid_ether_addr(mac_addr))
6809 goto done;
6810
ce37115e 6811 rtl_read_mac_from_reg(tp, mac_addr, MAC0);
c782e204
HK		 6812 if (is_valid_ether_addr(mac_addr))
6813 goto done;
6814
6815 eth_hw_addr_random(dev);
6816 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
6817done:
6818 rtl_rar_set(tp, mac_addr);
6819}
6820
929a031d 6821static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3b6cf25d 6822{
3b6cf25d 6823 struct rtl8169_private *tp;
3b6cf25d 6824 struct net_device *dev;
c782e204 6825 int chipset, region;
abe8b2f7 6826 int jumbo_max, rc;
3b6cf25d 6827
4c45d24a
HK		 6828 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
6829 if (!dev)
6830 return -ENOMEM;
3b6cf25d
FR		 6831
6832 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 6833 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 6834 tp = netdev_priv(dev);
6835 tp->dev = dev;
6836 tp->pci_dev = pdev;
6837 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
145a40e8 6838 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
7ec3f872 6839 tp->eee_adv = -1;
3b6cf25d 6840
c2f6f3ee 6841 /* Get the *optional* external "ether_clk" used on some boards */
b779daea
HK		 6842 rc = rtl_get_ether_clk(tp);
6843 if (rc)
6844 return rc;
c2f6f3ee 6845
b75bb8a5
HK		 6846 /* Disable ASPM completely as that cause random device stop working
6847 * problems as well as full system hangs for some PCIe devices users.
6848 */
62b1b3b3
HK		 6849 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
6850 PCIE_LINK_STATE_L1);
6851 tp->aspm_manageable = !rc;
b75bb8a5 6852
3b6cf25d 6853 /* enable device (incl. PCI PM wakeup and hotplug setup) */
4c45d24a 6854 rc = pcim_enable_device(pdev);
3b6cf25d 6855 if (rc < 0) {
22148df0 6856 dev_err(&pdev->dev, "enable failure\n");
4c45d24a 6857 return rc;
3b6cf25d
FR		 6858 }
6859
4c45d24a 6860 if (pcim_set_mwi(pdev) < 0)
22148df0 6861 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
3b6cf25d 6862
c8d48d9c
HK		 6863 /* use first MMIO region */
6864 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
6865 if (region < 0) {
22148df0 6866 dev_err(&pdev->dev, "no MMIO resource found\n");
4c45d24a 6867 return -ENODEV;
3b6cf25d
FR		 6868 }
6869
6870 /* check for weird/broken PCI region reporting */
6871 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
22148df0 6872 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
4c45d24a 6873 return -ENODEV;
3b6cf25d
FR		 6874 }
6875
93a00d4d 6876 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
3b6cf25d 6877 if (rc < 0) {
22148df0 6878 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
4c45d24a 6879 return rc;
3b6cf25d
FR		 6880 }
6881
93a00d4d 6882 tp->mmio_addr = pcim_iomap_table(pdev)[region];
3b6cf25d 6883
3b6cf25d 6884 /* Identify chip attached to board */
b4cc2dcc
HK		 6885 rtl8169_get_mac_version(tp);
6886 if (tp->mac_version == RTL_GIGA_MAC_NONE)
6887 return -ENODEV;
3b6cf25d 6888
0ae0974e 6889 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
27896c83 6890
10b63e85 6891 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
3c18cbe3 6892 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
27896c83 6893 dev->features |= NETIF_F_HIGHDMA;
27896c83 6894
3b6cf25d
FR		 6895 rtl_init_rxcfg(tp);
6896
de20e12f 6897 rtl8169_irq_mask_and_ack(tp);
3b6cf25d 6898
c558386b
HW		 6899 rtl_hw_initialize(tp);
6900
3b6cf25d
FR		 6901 rtl_hw_reset(tp);
6902
3b6cf25d
FR		 6903 pci_set_master(pdev);
6904
3b6cf25d 6905 chipset = tp->mac_version;
3b6cf25d 6906
6c6aa15f
HK		 6907 rc = rtl_alloc_irq(tp);
6908 if (rc < 0) {
22148df0 6909 dev_err(&pdev->dev, "Can't allocate interrupt\n");
6c6aa15f
HK		 6910 return rc;
6911 }
3b6cf25d 6912
3b6cf25d 6913 mutex_init(&tp->wk.mutex);
5c41e78f 6914 INIT_WORK(&tp->wk.work, rtl_task);
340fea3d
KM		 6915 u64_stats_init(&tp->rx_stats.syncp);
6916 u64_stats_init(&tp->tx_stats.syncp);
3b6cf25d 6917
c782e204 6918 rtl_init_mac_address(tp);
3b6cf25d 6919
7ad24ea4 6920 dev->ethtool_ops = &rtl8169_ethtool_ops;
3b6cf25d 6921
37621493 6922 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
3b6cf25d 6923
93681cd7
HK		 6924 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6925 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
6926 NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d 6927 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
f646968f
PM		 6928 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
6929 NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 6930 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6931 NETIF_F_HIGHDMA;
2d0ec544 6932 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
3b6cf25d 6933
dc161162
HK		 6934 tp->cp_cmd |= RxChkSum;
6935 /* RTL8125 uses register RxConfig for VLAN offloading config */
6936 if (!rtl_is_8125(tp))
6937 tp->cp_cmd |= RxVlan;
929a031d 6938 /*
6939 * Pretend we are using VLANs; This bypasses a nasty bug where
6940 * Interrupts stop flowing on high load on 8110SCd controllers.
6941 */
3b6cf25d 6942 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
929a031d 6943 /* Disallow toggling */
f646968f 6944 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d 6945
0170d594 6946 if (rtl_chip_supports_csum_v2(tp)) {
e974604b 6947 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
93681cd7 6948 dev->features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
0170d594
HK		 6949 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2;
6950 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2;
6951 } else {
6952 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1;
6953 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1;
6954 }
5888d3fc 6955
a0783cd0
CV		 6956 /* RTL8168e-vl and one RTL8168c variant are known to have a
6957 * HW issue with TSO.
6958 */
6959 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
6960 tp->mac_version == RTL_GIGA_MAC_VER_22) {
a7eb6a4f
HH		 6961 dev->vlan_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG);
6962 dev->hw_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG);
6963 dev->features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG);
93681cd7
HK		 6964 }
6965
3b6cf25d
FR		 6966 dev->hw_features |= NETIF_F_RXALL;
6967 dev->hw_features |= NETIF_F_RXFCS;
6968
c7315a95
JW		 6969 /* MTU range: 60 - hw-specific max */
6970 dev->min_mtu = ETH_ZLEN;
abe8b2f7
HK		 6971 jumbo_max = rtl_jumbo_max(tp);
6972 dev->max_mtu = jumbo_max;
c7315a95 6973
ec9a4088 6974 rtl_set_irq_mask(tp);
9fa0a8e1 6975
254764e5 6976 tp->fw_name = rtl_chip_infos[chipset].fw_name;
3b6cf25d 6977
4c45d24a
HK		 6978 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
6979 &tp->counters_phys_addr,
6980 GFP_KERNEL);
4cf964af
HK		 6981 if (!tp->counters)
6982 return -ENOMEM;
42020320 6983
19c9ea36
HK		 6984 pci_set_drvdata(pdev, dev);
6985
f1e911d5
HK		 6986 rc = r8169_mdio_register(tp);
6987 if (rc)
4cf964af 6988 return rc;
3b6cf25d 6989
07df5bd8
HK		 6990 /* chip gets powered up in rtl_open() */
6991 rtl_pll_power_down(tp);
6992
f1e911d5
HK		 6993 rc = register_netdev(dev);
6994 if (rc)
6995 goto err_mdio_unregister;
6996
55d2ad7b 6997 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
2d6c5a61 6998 rtl_chip_infos[chipset].name, dev->dev_addr,
55d2ad7b 6999 (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
29274991 7000 pci_irq_vector(pdev, 0));
abe8b2f7
HK		 7001
7002 if (jumbo_max > JUMBO_1K)
7003 netif_info(tp, probe, dev,
7004 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7005 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7006 "ok" : "ko");
3b6cf25d 7007
9dbe7896 7008 if (r8168_check_dash(tp))
3b6cf25d 7009 rtl8168_driver_start(tp);
3b6cf25d 7010
a92a0849
HK		 7011 if (pci_dev_run_wake(pdev))
7012 pm_runtime_put_sync(&pdev->dev);
7013
4c45d24a 7014 return 0;
f1e911d5
HK		 7015
7016err_mdio_unregister:
703732f0 7017 mdiobus_unregister(tp->phydev->mdio.bus);
f1e911d5 7018 return rc;
3b6cf25d
FR		 7019}
7020
1da177e4
LT		 7021static struct pci_driver rtl8169_pci_driver = {
7022 .name = MODULENAME,
7023 .id_table = rtl8169_pci_tbl,
3b6cf25d 7024 .probe = rtl_init_one,
baf63293 7025 .remove = rtl_remove_one,
1765f95d 7026 .shutdown = rtl_shutdown,
861ab440 7027 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 7028};
7029
3eeb7da9 7030module_pci_driver(rtl8169_pci_driver);
Linux 6.x block layer and io_uring tree(s)