projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
r8169: don't try to read counters if chip is in a PCI power-save state
[linux-2.6-block.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
c2f6f3ee 16#include <linux/clk.h>
1da177e4
LT		 17#include <linux/delay.h>
18#include <linux/ethtool.h>
f1e911d5 19#include <linux/phy.h>
1da177e4
LT		 20#include <linux/if_vlan.h>
21#include <linux/crc32.h>
22#include <linux/in.h>
098b01ad 23#include <linux/io.h>
1da177e4
LT		 24#include <linux/ip.h>
25#include <linux/tcp.h>
a6b7a407 26#include <linux/interrupt.h>
1da177e4 27#include <linux/dma-mapping.h>
e1759441 28#include <linux/pm_runtime.h>
bca03d5f 29#include <linux/firmware.h>
70c71606 30#include <linux/prefetch.h>
e974604b 31#include <linux/ipv6.h>
32#include <net/ip6_checksum.h>
1da177e4 33
1da177e4 34#define MODULENAME "r8169"
1da177e4 35
bca03d5f 36#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
37#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 38#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
39#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 40#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 41#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
42#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 43#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 44#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 45#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45dd95c4 46#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
5598bfe5 47#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
58152cd4 48#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
beb330a4 49#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
57538c4a 50#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
6e1d0b89
CHL		 51#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
52#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
53#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
54#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
bca03d5f 55
b57b7e5a 56#define R8169_MSG_DEFAULT \
f0e837d9 57 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 58
1da177e4
LT		 59/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
60 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 61static const int multicast_filter_limit = 32;
1da177e4 62
aee77e4a 63#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 64#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
65
66#define R8169_REGS_SIZE 256
1d0254dd 67#define R8169_RX_BUF_SIZE (SZ_16K - 1)
1da177e4 68#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 69#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 70#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
71#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
72
1da177e4 73/* write/read MMIO register */
1ef7286e
AS		 74#define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
75#define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
76#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
77#define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
78#define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
79#define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
1da177e4
LT		 80
81enum mac_version {
85bffe6c
FR		 82 RTL_GIGA_MAC_VER_01 = 0,
83 RTL_GIGA_MAC_VER_02,
84 RTL_GIGA_MAC_VER_03,
85 RTL_GIGA_MAC_VER_04,
86 RTL_GIGA_MAC_VER_05,
87 RTL_GIGA_MAC_VER_06,
88 RTL_GIGA_MAC_VER_07,
89 RTL_GIGA_MAC_VER_08,
90 RTL_GIGA_MAC_VER_09,
91 RTL_GIGA_MAC_VER_10,
92 RTL_GIGA_MAC_VER_11,
93 RTL_GIGA_MAC_VER_12,
94 RTL_GIGA_MAC_VER_13,
95 RTL_GIGA_MAC_VER_14,
96 RTL_GIGA_MAC_VER_15,
97 RTL_GIGA_MAC_VER_16,
98 RTL_GIGA_MAC_VER_17,
99 RTL_GIGA_MAC_VER_18,
100 RTL_GIGA_MAC_VER_19,
101 RTL_GIGA_MAC_VER_20,
102 RTL_GIGA_MAC_VER_21,
103 RTL_GIGA_MAC_VER_22,
104 RTL_GIGA_MAC_VER_23,
105 RTL_GIGA_MAC_VER_24,
106 RTL_GIGA_MAC_VER_25,
107 RTL_GIGA_MAC_VER_26,
108 RTL_GIGA_MAC_VER_27,
109 RTL_GIGA_MAC_VER_28,
110 RTL_GIGA_MAC_VER_29,
111 RTL_GIGA_MAC_VER_30,
112 RTL_GIGA_MAC_VER_31,
113 RTL_GIGA_MAC_VER_32,
114 RTL_GIGA_MAC_VER_33,
70090424 115 RTL_GIGA_MAC_VER_34,
c2218925
HW		 116 RTL_GIGA_MAC_VER_35,
117 RTL_GIGA_MAC_VER_36,
7e18dca1 118 RTL_GIGA_MAC_VER_37,
b3d7b2f2 119 RTL_GIGA_MAC_VER_38,
5598bfe5 120 RTL_GIGA_MAC_VER_39,
c558386b
HW		 121 RTL_GIGA_MAC_VER_40,
122 RTL_GIGA_MAC_VER_41,
57538c4a 123 RTL_GIGA_MAC_VER_42,
58152cd4 124 RTL_GIGA_MAC_VER_43,
45dd95c4 125 RTL_GIGA_MAC_VER_44,
6e1d0b89
CHL		 126 RTL_GIGA_MAC_VER_45,
127 RTL_GIGA_MAC_VER_46,
128 RTL_GIGA_MAC_VER_47,
129 RTL_GIGA_MAC_VER_48,
935e2218
CHL		 130 RTL_GIGA_MAC_VER_49,
131 RTL_GIGA_MAC_VER_50,
132 RTL_GIGA_MAC_VER_51,
85bffe6c 133 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 134};
135
d58d46b5
FR		 136#define JUMBO_1K ETH_DATA_LEN
137#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
138#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
139#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
140#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
141
3c6bee1d 142static const struct {
1da177e4 143 const char *name;
953a12cc 144 const char *fw_name;
85bffe6c
FR		 145} rtl_chip_infos[] = {
146 /* PCI devices. */
abe8b2f7
HK		 147 [RTL_GIGA_MAC_VER_01] = {"RTL8169" },
148 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
149 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
150 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
151 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
152 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
85bffe6c 153 /* PCI-E devices. */
abe8b2f7
HK		 154 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
155 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
156 [RTL_GIGA_MAC_VER_09] = {"RTL8102e" },
157 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
158 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
159 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
160 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
161 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
162 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
163 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
164 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
165 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
166 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
167 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
168 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
169 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
170 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
171 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
172 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
173 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
174 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
175 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
176 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
177 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
178 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
179 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
180 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
181 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
182 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
183 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
184 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
185 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
186 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
187 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
188 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
189 [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g", FIRMWARE_8168G_3},
190 [RTL_GIGA_MAC_VER_43] = {"RTL8106e", FIRMWARE_8106E_2},
191 [RTL_GIGA_MAC_VER_44] = {"RTL8411", FIRMWARE_8411_2 },
192 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
193 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
194 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
195 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
196 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
197 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
198 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
953a12cc
FR		 199};
200
bcf0bf90
FR		 201enum cfg_version {
202 RTL_CFG_0 = 0x00,
203 RTL_CFG_1,
204 RTL_CFG_2
205};
206
9baa3c34 207static const struct pci_device_id rtl8169_pci_tbl[] = {
36352991
KHF		 208 { PCI_VDEVICE(REALTEK, 0x2502), RTL_CFG_1 },
209 { PCI_VDEVICE(REALTEK, 0x2600), RTL_CFG_1 },
6f0d3088
HK		 210 { PCI_VDEVICE(REALTEK, 0x8129), RTL_CFG_0 },
211 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_2 },
212 { PCI_VDEVICE(REALTEK, 0x8161), RTL_CFG_1 },
213 { PCI_VDEVICE(REALTEK, 0x8167), RTL_CFG_0 },
214 { PCI_VDEVICE(REALTEK, 0x8168), RTL_CFG_1 },
215 { PCI_VDEVICE(NCUBE, 0x8168), RTL_CFG_1 },
216 { PCI_VDEVICE(REALTEK, 0x8169), RTL_CFG_0 },
217 { PCI_VENDOR_ID_DLINK, 0x4300,
218 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
219 { PCI_VDEVICE(DLINK, 0x4300), RTL_CFG_0 },
220 { PCI_VDEVICE(DLINK, 0x4302), RTL_CFG_0 },
221 { PCI_VDEVICE(AT, 0xc107), RTL_CFG_0 },
222 { PCI_VDEVICE(USR, 0x0116), RTL_CFG_0 },
bcf0bf90
FR		 223 { PCI_VENDOR_ID_LINKSYS, 0x1032,
224 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 225 { 0x0001, 0x8168,
226 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
6f0d3088 227 {}
1da177e4
LT		 228};
229
230MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
231
27896c83 232static int use_dac = -1;
b57b7e5a
SH		 233static struct {
234 u32 msg_enable;
235} debug = { -1 };
1da177e4 236
07d3f51f
FR		 237enum rtl_registers {
238 MAC0 = 0, /* Ethernet hardware address. */
773d2021 239 MAC4 = 4,
07d3f51f
FR		 240 MAR0 = 8, /* Multicast filter. */
241 CounterAddrLow = 0x10,
242 CounterAddrHigh = 0x14,
243 TxDescStartAddrLow = 0x20,
244 TxDescStartAddrHigh = 0x24,
245 TxHDescStartAddrLow = 0x28,
246 TxHDescStartAddrHigh = 0x2c,
247 FLASH = 0x30,
248 ERSR = 0x36,
249 ChipCmd = 0x37,
250 TxPoll = 0x38,
251 IntrMask = 0x3c,
252 IntrStatus = 0x3e,
4f6b00e5 253
07d3f51f 254 TxConfig = 0x40,
4f6b00e5
HW		 255#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
256#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 257
4f6b00e5
HW		 258 RxConfig = 0x44,
259#define RX128_INT_EN (1 << 15) /* 8111c and later */
260#define RX_MULTI_EN (1 << 14) /* 8111c only */
261#define RXCFG_FIFO_SHIFT 13
262 /* No threshold before first PCI xfer */
263#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 264#define RX_EARLY_OFF (1 << 11)
4f6b00e5
HW		 265#define RXCFG_DMA_SHIFT 8
266 /* Unlimited maximum PCI burst. */
267#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 268
07d3f51f
FR		 269 RxMissed = 0x4c,
270 Cfg9346 = 0x50,
271 Config0 = 0x51,
272 Config1 = 0x52,
273 Config2 = 0x53,
d387b427
FR		 274#define PME_SIGNAL (1 << 5) /* 8168c and later */
275
07d3f51f
FR		 276 Config3 = 0x54,
277 Config4 = 0x55,
278 Config5 = 0x56,
279 MultiIntr = 0x5c,
280 PHYAR = 0x60,
07d3f51f
FR		 281 PHYstatus = 0x6c,
282 RxMaxSize = 0xda,
283 CPlusCmd = 0xe0,
284 IntrMitigate = 0xe2,
50970831
FR		 285
286#define RTL_COALESCE_MASK 0x0f
287#define RTL_COALESCE_SHIFT 4
288#define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
289#define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
290
07d3f51f
FR		 291 RxDescAddrLow = 0xe4,
292 RxDescAddrHigh = 0xe8,
f0298f81 293 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
294
295#define NoEarlyTx 0x3f /* Max value : no early transmit. */
296
297 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
298
299#define TxPacketMax (8064 >> 7)
3090bd9a 300#define EarlySize 0x27
f0298f81 301
07d3f51f
FR		 302 FuncEvent = 0xf0,
303 FuncEventMask = 0xf4,
304 FuncPresetState = 0xf8,
935e2218
CHL		 305 IBCR0 = 0xf8,
306 IBCR2 = 0xf9,
307 IBIMR0 = 0xfa,
308 IBISR0 = 0xfb,
07d3f51f 309 FuncForceEvent = 0xfc,
1da177e4
LT		 310};
311
f162a5d1
FR		 312enum rtl8168_8101_registers {
313 CSIDR = 0x64,
314 CSIAR = 0x68,
315#define CSIAR_FLAG 0x80000000
316#define CSIAR_WRITE_CMD 0x80000000
ff1d7331
HK		 317#define CSIAR_BYTE_ENABLE 0x0000f000
318#define CSIAR_ADDR_MASK 0x00000fff
065c27c1 319 PMCH = 0x6f,
f162a5d1
FR		 320 EPHYAR = 0x80,
321#define EPHYAR_FLAG 0x80000000
322#define EPHYAR_WRITE_CMD 0x80000000
323#define EPHYAR_REG_MASK 0x1f
324#define EPHYAR_REG_SHIFT 16
325#define EPHYAR_DATA_MASK 0xffff
5a5e4443 326 DLLPR = 0xd0,
4f6b00e5 327#define PFM_EN (1 << 6)
6e1d0b89 328#define TX_10M_PS_EN (1 << 7)
f162a5d1
FR		 329 DBG_REG = 0xd1,
330#define FIX_NAK_1 (1 << 4)
331#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 332 TWSI = 0xd2,
333 MCU = 0xd3,
4f6b00e5 334#define NOW_IS_OOB (1 << 7)
c558386b
HW		 335#define TX_EMPTY (1 << 5)
336#define RX_EMPTY (1 << 4)
337#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 338#define EN_NDP (1 << 3)
339#define EN_OOB_RESET (1 << 2)
c558386b 340#define LINK_LIST_RDY (1 << 1)
daf9df6d 341 EFUSEAR = 0xdc,
342#define EFUSEAR_FLAG 0x80000000
343#define EFUSEAR_WRITE_CMD 0x80000000
344#define EFUSEAR_READ_CMD 0x00000000
345#define EFUSEAR_REG_MASK 0x03ff
346#define EFUSEAR_REG_SHIFT 8
347#define EFUSEAR_DATA_MASK 0xff
6e1d0b89
CHL		 348 MISC_1 = 0xf2,
349#define PFM_D3COLD_EN (1 << 6)
f162a5d1
FR		 350};
351
c0e45c1c 352enum rtl8168_registers {
4f6b00e5
HW		 353 LED_FREQ = 0x1a,
354 EEE_LED = 0x1b,
b646d900 355 ERIDR = 0x70,
356 ERIAR = 0x74,
357#define ERIAR_FLAG 0x80000000
358#define ERIAR_WRITE_CMD 0x80000000
359#define ERIAR_READ_CMD 0x00000000
360#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 361#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 362#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
363#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
364#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
935e2218 365#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
4f6b00e5
HW		 366#define ERIAR_MASK_SHIFT 12
367#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
368#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
6e1d0b89 369#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
c558386b 370#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 371#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 372 EPHY_RXER_NUM = 0x7c,
373 OCPDR = 0xb0, /* OCP GPHY access */
374#define OCPDR_WRITE_CMD 0x80000000
375#define OCPDR_READ_CMD 0x00000000
376#define OCPDR_REG_MASK 0x7f
377#define OCPDR_GPHY_REG_SHIFT 16
378#define OCPDR_DATA_MASK 0xffff
379 OCPAR = 0xb4,
380#define OCPAR_FLAG 0x80000000
381#define OCPAR_GPHY_WRITE_CMD 0x8000f060
382#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 383 GPHY_OCP = 0xb8,
01dc7fec 384 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
385 MISC = 0xf0, /* 8168e only. */
cecb5fd7 386#define TXPLA_RST (1 << 29)
5598bfe5 387#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 388#define PWM_EN (1 << 22)
c558386b 389#define RXDV_GATED_EN (1 << 19)
5598bfe5 390#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 391};
392
07d3f51f 393enum rtl_register_content {
1da177e4 394 /* InterruptStatusBits */
07d3f51f
FR		 395 SYSErr = 0x8000,
396 PCSTimeout = 0x4000,
397 SWInt = 0x0100,
398 TxDescUnavail = 0x0080,
399 RxFIFOOver = 0x0040,
400 LinkChg = 0x0020,
401 RxOverflow = 0x0010,
402 TxErr = 0x0008,
403 TxOK = 0x0004,
404 RxErr = 0x0002,
405 RxOK = 0x0001,
1da177e4
LT		 406
407 /* RxStatusDesc */
e03f33af 408 RxBOVF = (1 << 24),
9dccf611
FR		 409 RxFOVF = (1 << 23),
410 RxRWT = (1 << 22),
411 RxRES = (1 << 21),
412 RxRUNT = (1 << 20),
413 RxCRC = (1 << 19),
1da177e4
LT		 414
415 /* ChipCmdBits */
4f6b00e5 416 StopReq = 0x80,
07d3f51f
FR		 417 CmdReset = 0x10,
418 CmdRxEnb = 0x08,
419 CmdTxEnb = 0x04,
420 RxBufEmpty = 0x01,
1da177e4 421
275391a4
FR		 422 /* TXPoll register p.5 */
423 HPQ = 0x80, /* Poll cmd on the high prio queue */
424 NPQ = 0x40, /* Poll cmd on the low prio queue */
425 FSWInt = 0x01, /* Forced software interrupt */
426
1da177e4 427 /* Cfg9346Bits */
07d3f51f
FR		 428 Cfg9346_Lock = 0x00,
429 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 430
431 /* rx_mode_bits */
07d3f51f
FR		 432 AcceptErr = 0x20,
433 AcceptRunt = 0x10,
434 AcceptBroadcast = 0x08,
435 AcceptMulticast = 0x04,
436 AcceptMyPhys = 0x02,
437 AcceptAllPhys = 0x01,
1687b566 438#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 439
1da177e4
LT		 440 /* TxConfigBits */
441 TxInterFrameGapShift = 24,
442 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
443
5d06a99f 444 /* Config1 register p.24 */
f162a5d1
FR		 445 LEDS1 = (1 << 7),
446 LEDS0 = (1 << 6),
f162a5d1
FR		 447 Speed_down = (1 << 4),
448 MEMMAP = (1 << 3),
449 IOMAP = (1 << 2),
450 VPD = (1 << 1),
5d06a99f
FR		 451 PMEnable = (1 << 0), /* Power Management Enable */
452
6dccd16b 453 /* Config2 register p. 25 */
57538c4a 454 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 455 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 456 PCI_Clock_66MHz = 0x01,
457 PCI_Clock_33MHz = 0x00,
458
61a4dcc2
FR		 459 /* Config3 register p.25 */
460 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
461 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 462 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
b51ecea8 463 Rdy_to_L23 = (1 << 1), /* L23 Enable */
f162a5d1 464 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 465
d58d46b5
FR		 466 /* Config4 register */
467 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
468
5d06a99f 469 /* Config5 register p.27 */
61a4dcc2
FR		 470 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
471 MWF = (1 << 5), /* Accept Multicast wakeup frame */
472 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 473 Spi_en = (1 << 3),
61a4dcc2 474 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 475 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
57538c4a 476 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 477
1da177e4 478 /* CPlusCmd p.31 */
f162a5d1
FR		 479 EnableBist = (1 << 15), // 8168 8101
480 Mac_dbgo_oe = (1 << 14), // 8168 8101
481 Normal_mode = (1 << 13), // unused
482 Force_half_dup = (1 << 12), // 8168 8101
483 Force_rxflow_en = (1 << 11), // 8168 8101
484 Force_txflow_en = (1 << 10), // 8168 8101
485 Cxpl_dbg_sel = (1 << 9), // 8168 8101
486 ASF = (1 << 8), // 8168 8101
487 PktCntrDisable = (1 << 7), // 8168 8101
488 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 489 RxVlan = (1 << 6),
490 RxChkSum = (1 << 5),
491 PCIDAC = (1 << 4),
492 PCIMulRW = (1 << 3),
9a3c81fa 493#define INTT_MASK GENMASK(1, 0)
0e485150
FR		 494 INTT_0 = 0x0000, // 8168
495 INTT_1 = 0x0001, // 8168
496 INTT_2 = 0x0002, // 8168
497 INTT_3 = 0x0003, // 8168
1da177e4
LT		 498
499 /* rtl8169_PHYstatus */
07d3f51f
FR		 500 TBI_Enable = 0x80,
501 TxFlowCtrl = 0x40,
502 RxFlowCtrl = 0x20,
503 _1000bpsF = 0x10,
504 _100bps = 0x08,
505 _10bps = 0x04,
506 LinkStatus = 0x02,
507 FullDup = 0x01,
1da177e4 508
1da177e4 509 /* _TBICSRBit */
07d3f51f 510 TBILinkOK = 0x02000000,
d4a3a0fc 511
6e85d5ad
CV		 512 /* ResetCounterCommand */
513 CounterReset = 0x1,
514
d4a3a0fc 515 /* DumpCounterCommand */
07d3f51f 516 CounterDump = 0x8,
6e1d0b89
CHL		 517
518 /* magic enable v2 */
519 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
1da177e4
LT		 520};
521
2b7b4318
FR		 522enum rtl_desc_bit {
523 /* First doubleword. */
1da177e4
LT		 524 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
525 RingEnd = (1 << 30), /* End of descriptor ring */
526 FirstFrag = (1 << 29), /* First segment of a packet */
527 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 528};
529
530/* Generic case. */
531enum rtl_tx_desc_bit {
532 /* First doubleword. */
533 TD_LSO = (1 << 27), /* Large Send Offload */
534#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 535
2b7b4318
FR		 536 /* Second doubleword. */
537 TxVlanTag = (1 << 17), /* Add VLAN tag */
538};
539
540/* 8169, 8168b and 810x except 8102e. */
541enum rtl_tx_desc_bit_0 {
542 /* First doubleword. */
543#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
544 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
545 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
546 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
547};
548
549/* 8102e, 8168c and beyond. */
550enum rtl_tx_desc_bit_1 {
bdfa4ed6 551 /* First doubleword. */
552 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
e974604b 553 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
bdfa4ed6 554#define GTTCPHO_SHIFT 18
e974604b 555#define GTTCPHO_MAX 0x7fU
bdfa4ed6 556
2b7b4318 557 /* Second doubleword. */
e974604b 558#define TCPHO_SHIFT 18
559#define TCPHO_MAX 0x3ffU
2b7b4318 560#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
e974604b 561 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
562 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
2b7b4318
FR		 563 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
564 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
565};
1da177e4 566
2b7b4318 567enum rtl_rx_desc_bit {
1da177e4
LT		 568 /* Rx private */
569 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
9b60047a 570 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
1da177e4
LT		 571
572#define RxProtoUDP (PID1)
573#define RxProtoTCP (PID0)
574#define RxProtoIP (PID1 | PID0)
575#define RxProtoMask RxProtoIP
576
577 IPFail = (1 << 16), /* IP checksum failed */
578 UDPFail = (1 << 15), /* UDP/IP checksum failed */
579 TCPFail = (1 << 14), /* TCP/IP checksum failed */
580 RxVlanTag = (1 << 16), /* VLAN tag available */
581};
582
583#define RsvdMask 0x3fffc000
12d42c50 584#define CPCMD_QUIRK_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
1da177e4
LT		 585
586struct TxDesc {
6cccd6e7
REB		 587 __le32 opts1;
588 __le32 opts2;
589 __le64 addr;
1da177e4
LT		 590};
591
592struct RxDesc {
6cccd6e7
REB		 593 __le32 opts1;
594 __le32 opts2;
595 __le64 addr;
1da177e4
LT		 596};
597
598struct ring_info {
599 struct sk_buff *skb;
600 u32 len;
1da177e4
LT		 601};
602
355423d0
IV		 603struct rtl8169_counters {
604 __le64 tx_packets;
605 __le64 rx_packets;
606 __le64 tx_errors;
607 __le32 rx_errors;
608 __le16 rx_missed;
609 __le16 align_errors;
610 __le32 tx_one_collision;
611 __le32 tx_multi_collision;
612 __le64 rx_unicast;
613 __le64 rx_broadcast;
614 __le32 rx_multicast;
615 __le16 tx_aborted;
616 __le16 tx_underun;
617};
618
6e85d5ad
CV		 619struct rtl8169_tc_offsets {
620 bool inited;
621 __le64 tx_errors;
622 __le32 tx_multi_collision;
6e85d5ad
CV		 623 __le16 tx_aborted;
624};
625
da78dbff 626enum rtl_flag {
6ad56901 627 RTL_FLAG_TASK_ENABLED = 0,
da78dbff 628 RTL_FLAG_TASK_RESET_PENDING,
da78dbff
FR		 629 RTL_FLAG_MAX
630};
631
8027aa24
JW		 632struct rtl8169_stats {
633 u64 packets;
634 u64 bytes;
635 struct u64_stats_sync syncp;
636};
637
1da177e4
LT		 638struct rtl8169_private {
639 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 640 struct pci_dev *pci_dev;
c4028958 641 struct net_device *dev;
bea3348e 642 struct napi_struct napi;
b57b7e5a 643 u32 msg_enable;
2b7b4318 644 u16 mac_version;
1da177e4
LT		 645 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
646 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 647 u32 dirty_tx;
8027aa24
JW		 648 struct rtl8169_stats rx_stats;
649 struct rtl8169_stats tx_stats;
1da177e4
LT		 650 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
651 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
652 dma_addr_t TxPhyAddr;
653 dma_addr_t RxPhyAddr;
6f0333b8 654 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 655 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4 656 u16 cp_cmd;
da78dbff 657
559c3c04 658 u16 irq_mask;
50970831 659 const struct rtl_coalesce_info *coalesce_info;
c2f6f3ee 660 struct clk *clk;
c0e45c1c 661
662 struct mdio_ops {
24192210
FR		 663 void (*write)(struct rtl8169_private *, int, int);
664 int (*read)(struct rtl8169_private *, int);
c0e45c1c 665 } mdio_ops;
666
d58d46b5
FR		 667 struct jumbo_ops {
668 void (*enable)(struct rtl8169_private *);
669 void (*disable)(struct rtl8169_private *);
670 } jumbo_ops;
671
61cb532d 672 void (*hw_start)(struct rtl8169_private *tp);
5888d3fc 673 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
4422bcd4
FR		 674
675 struct {
da78dbff
FR		 676 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
677 struct mutex mutex;
4422bcd4
FR		 678 struct work_struct work;
679 } wk;
680
f7ffa9ae 681 unsigned supports_gmii:1;
f1e911d5 682 struct mii_bus *mii_bus;
42020320
CV		 683 dma_addr_t counters_phys_addr;
684 struct rtl8169_counters *counters;
6e85d5ad 685 struct rtl8169_tc_offsets tc_offset;
e1759441 686 u32 saved_wolopts;
f1e02ed1 687
b6ffd97f
FR		 688 struct rtl_fw {
689 const struct firmware *fw;
1c361efb
FR		 690
691#define RTL_VER_SIZE 32
692
693 char version[RTL_VER_SIZE];
694
695 struct rtl_fw_phy_action {
696 __le32 *code;
697 size_t size;
698 } phy_action;
b6ffd97f 699 } *rtl_fw;
497888cf 700#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 701
702 u32 ocp_base;
1da177e4
LT		 703};
704
979b6c13 705MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 706MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 707module_param(use_dac, int, 0);
4300e8c7 708MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 709module_param_named(debug, debug.msg_enable, int, 0);
710MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4 711MODULE_LICENSE("GPL");
bca03d5f 712MODULE_FIRMWARE(FIRMWARE_8168D_1);
713MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 714MODULE_FIRMWARE(FIRMWARE_8168E_1);
715MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 716MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 717MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 718MODULE_FIRMWARE(FIRMWARE_8168F_1);
719MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 720MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 721MODULE_FIRMWARE(FIRMWARE_8411_1);
45dd95c4 722MODULE_FIRMWARE(FIRMWARE_8411_2);
5598bfe5 723MODULE_FIRMWARE(FIRMWARE_8106E_1);
58152cd4 724MODULE_FIRMWARE(FIRMWARE_8106E_2);
beb330a4 725MODULE_FIRMWARE(FIRMWARE_8168G_2);
57538c4a 726MODULE_FIRMWARE(FIRMWARE_8168G_3);
6e1d0b89
CHL		 727MODULE_FIRMWARE(FIRMWARE_8168H_1);
728MODULE_FIRMWARE(FIRMWARE_8168H_2);
a3bf5c42
FR		 729MODULE_FIRMWARE(FIRMWARE_8107E_1);
730MODULE_FIRMWARE(FIRMWARE_8107E_2);
1da177e4 731
1e1205b7
HK		 732static inline struct device *tp_to_dev(struct rtl8169_private *tp)
733{
734 return &tp->pci_dev->dev;
735}
736
da78dbff
FR		 737static void rtl_lock_work(struct rtl8169_private *tp)
738{
739 mutex_lock(&tp->wk.mutex);
740}
741
742static void rtl_unlock_work(struct rtl8169_private *tp)
743{
744 mutex_unlock(&tp->wk.mutex);
745}
746
cb73200c 747static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
d58d46b5 748{
cb73200c 749 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
7d7903b2 750 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 751}
752
ffc46952
FR		 753struct rtl_cond {
754 bool (*check)(struct rtl8169_private *);
755 const char *msg;
756};
757
758static void rtl_udelay(unsigned int d)
759{
760 udelay(d);
761}
762
763static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
764 void (*delay)(unsigned int), unsigned int d, int n,
765 bool high)
766{
767 int i;
768
769 for (i = 0; i < n; i++) {
770 delay(d);
771 if (c->check(tp) == high)
772 return true;
773 }
82e316ef
FR		 774 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
775 c->msg, !high, n, d);
ffc46952
FR		 776 return false;
777}
778
779static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
780 const struct rtl_cond *c,
781 unsigned int d, int n)
782{
783 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
784}
785
786static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
787 const struct rtl_cond *c,
788 unsigned int d, int n)
789{
790 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
791}
792
793static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
794 const struct rtl_cond *c,
795 unsigned int d, int n)
796{
797 return rtl_loop_wait(tp, c, msleep, d, n, true);
798}
799
800static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
801 const struct rtl_cond *c,
802 unsigned int d, int n)
803{
804 return rtl_loop_wait(tp, c, msleep, d, n, false);
805}
806
807#define DECLARE_RTL_COND(name) \
808static bool name ## _check(struct rtl8169_private *); \
809 \
810static const struct rtl_cond name = { \
811 .check = name ## _check, \
812 .msg = #name \
813}; \
814 \
815static bool name ## _check(struct rtl8169_private *tp)
816
c558386b
HW		 817static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
818{
819 if (reg & 0xffff0001) {
820 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
821 return true;
822 }
823 return false;
824}
825
826DECLARE_RTL_COND(rtl_ocp_gphy_cond)
827{
1ef7286e 828 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
c558386b
HW		 829}
830
831static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
832{
c558386b
HW		 833 if (rtl_ocp_reg_failure(tp, reg))
834 return;
835
1ef7286e 836 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 837
838 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
839}
840
841static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
842{
c558386b
HW		 843 if (rtl_ocp_reg_failure(tp, reg))
844 return 0;
845
1ef7286e 846 RTL_W32(tp, GPHY_OCP, reg << 15);
c558386b
HW		 847
848 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1ef7286e 849 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
c558386b
HW		 850}
851
c558386b
HW		 852static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
853{
c558386b
HW		 854 if (rtl_ocp_reg_failure(tp, reg))
855 return;
856
1ef7286e 857 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 858}
859
860static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
861{
c558386b
HW		 862 if (rtl_ocp_reg_failure(tp, reg))
863 return 0;
864
1ef7286e 865 RTL_W32(tp, OCPDR, reg << 15);
c558386b 866
1ef7286e 867 return RTL_R32(tp, OCPDR);
c558386b
HW		 868}
869
870#define OCP_STD_PHY_BASE 0xa400
871
872static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
873{
874 if (reg == 0x1f) {
875 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
876 return;
877 }
878
879 if (tp->ocp_base != OCP_STD_PHY_BASE)
880 reg -= 0x10;
881
882 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
883}
884
885static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
886{
887 if (tp->ocp_base != OCP_STD_PHY_BASE)
888 reg -= 0x10;
889
890 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
891}
892
eee3786f 893static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
894{
895 if (reg == 0x1f) {
896 tp->ocp_base = value << 4;
897 return;
898 }
899
900 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
901}
902
903static int mac_mcu_read(struct rtl8169_private *tp, int reg)
904{
905 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
906}
907
ffc46952
FR		 908DECLARE_RTL_COND(rtl_phyar_cond)
909{
1ef7286e 910 return RTL_R32(tp, PHYAR) & 0x80000000;
ffc46952
FR		 911}
912
24192210 913static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 914{
1ef7286e 915 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 916
ffc46952 917 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 918 /*
81a95f04
TT		 919 * According to hardware specs a 20us delay is required after write
920 * complete indication, but before sending next command.
024a07ba 921 */
81a95f04 922 udelay(20);
1da177e4
LT		 923}
924
24192210 925static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 926{
ffc46952 927 int value;
1da177e4 928
1ef7286e 929 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 930
ffc46952 931 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1ef7286e 932 RTL_R32(tp, PHYAR) & 0xffff : ~0;
ffc46952 933
81a95f04
TT		 934 /*
935 * According to hardware specs a 20us delay is required after read
936 * complete indication, but before sending next command.
937 */
938 udelay(20);
939
1da177e4
LT		 940 return value;
941}
942
935e2218
CHL		 943DECLARE_RTL_COND(rtl_ocpar_cond)
944{
1ef7286e 945 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
935e2218
CHL		 946}
947
24192210 948static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 949{
1ef7286e
AS		 950 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
951 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
952 RTL_W32(tp, EPHY_RXER_NUM, 0);
c0e45c1c 953
ffc46952 954 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 955}
956
24192210 957static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 958{
24192210
FR		 959 r8168dp_1_mdio_access(tp, reg,
960 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 961}
962
24192210 963static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 964{
24192210 965 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 966
967 mdelay(1);
1ef7286e
AS		 968 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
969 RTL_W32(tp, EPHY_RXER_NUM, 0);
c0e45c1c 970
ffc46952 971 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1ef7286e 972 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 973}
974
e6de30d6 975#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
976
1ef7286e 977static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
e6de30d6 978{
1ef7286e 979 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 980}
981
1ef7286e 982static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
e6de30d6 983{
1ef7286e 984 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 985}
986
24192210 987static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 988{
1ef7286e 989 r8168dp_2_mdio_start(tp);
e6de30d6 990
24192210 991 r8169_mdio_write(tp, reg, value);
e6de30d6 992
1ef7286e 993 r8168dp_2_mdio_stop(tp);
e6de30d6 994}
995
24192210 996static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 997{
998 int value;
999
1ef7286e 1000 r8168dp_2_mdio_start(tp);
e6de30d6 1001
24192210 1002 value = r8169_mdio_read(tp, reg);
e6de30d6 1003
1ef7286e 1004 r8168dp_2_mdio_stop(tp);
e6de30d6 1005
1006 return value;
1007}
1008
4da19633 1009static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1010{
24192210 1011 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1012}
1013
4da19633 1014static int rtl_readphy(struct rtl8169_private *tp, int location)
1015{
24192210 1016 return tp->mdio_ops.read(tp, location);
4da19633 1017}
1018
1019static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1020{
1021 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1022}
1023
76564428 1024static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1025{
1026 int val;
1027
4da19633 1028 val = rtl_readphy(tp, reg_addr);
76564428 1029 rtl_writephy(tp, reg_addr, (val & ~m) | p);
daf9df6d 1030}
1031
ffc46952
FR		 1032DECLARE_RTL_COND(rtl_ephyar_cond)
1033{
1ef7286e 1034 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
ffc46952
FR		 1035}
1036
fdf6fc06 1037static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1038{
1ef7286e 1039 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
dacf8154
FR		 1040 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1041
ffc46952
FR		 1042 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1043
1044 udelay(10);
dacf8154
FR		 1045}
1046
fdf6fc06 1047static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1048{
1ef7286e 1049 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
dacf8154 1050
ffc46952 1051 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1ef7286e 1052 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1053}
1054
935e2218
CHL		 1055DECLARE_RTL_COND(rtl_eriar_cond)
1056{
1ef7286e 1057 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
935e2218
CHL		 1058}
1059
fdf6fc06
FR		 1060static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1061 u32 val, int type)
133ac40a 1062{
133ac40a 1063 BUG_ON((addr & 3) || (mask == 0));
1ef7286e
AS		 1064 RTL_W32(tp, ERIDR, val);
1065 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
133ac40a 1066
ffc46952 1067 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1068}
1069
fdf6fc06 1070static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1071{
1ef7286e 1072 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
133ac40a 1073
ffc46952 1074 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1ef7286e 1075 RTL_R32(tp, ERIDR) : ~0;
133ac40a
HW		 1076}
1077
706123d0 1078static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
fdf6fc06 1079 u32 m, int type)
133ac40a
HW		 1080{
1081 u32 val;
1082
fdf6fc06
FR		 1083 val = rtl_eri_read(tp, addr, type);
1084 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1085}
1086
935e2218
CHL		 1087static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1088{
1ef7286e 1089 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
935e2218 1090 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1ef7286e 1091 RTL_R32(tp, OCPDR) : ~0;
935e2218
CHL		 1092}
1093
1094static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1095{
1096 return rtl_eri_read(tp, reg, ERIAR_OOB);
1097}
1098
935e2218
CHL		 1099static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1100 u32 data)
1101{
1ef7286e
AS		 1102 RTL_W32(tp, OCPDR, data);
1103 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
935e2218
CHL		 1104 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1105}
1106
1107static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1108 u32 data)
1109{
1110 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1111 data, ERIAR_OOB);
1112}
1113
3c72bf71 1114static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
2a9b4d96
CHL		 1115{
1116 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1117
3c72bf71 1118 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
2a9b4d96
CHL		 1119}
1120
1121#define OOB_CMD_RESET 0x00
1122#define OOB_CMD_DRIVER_START 0x05
1123#define OOB_CMD_DRIVER_STOP 0x06
1124
1125static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1126{
1127 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1128}
1129
3c72bf71 1130DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
2a9b4d96
CHL		 1131{
1132 u16 reg;
1133
1134 reg = rtl8168_get_ocp_reg(tp);
1135
3c72bf71 1136 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
2a9b4d96
CHL		 1137}
1138
935e2218 1139DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
2a9b4d96 1140{
3c72bf71 1141 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
935e2218
CHL		 1142}
1143
1144DECLARE_RTL_COND(rtl_ocp_tx_cond)
1145{
1ef7286e 1146 return RTL_R8(tp, IBISR0) & 0x20;
935e2218 1147}
2a9b4d96 1148
003609da
CHL		 1149static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1150{
1ef7286e 1151 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
086ca23d 1152 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1ef7286e
AS		 1153 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1154 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
003609da
CHL		 1155}
1156
935e2218
CHL		 1157static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1158{
3c72bf71
HK		 1159 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1160 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
2a9b4d96
CHL		 1161}
1162
935e2218 1163static void rtl8168ep_driver_start(struct rtl8169_private *tp)
2a9b4d96 1164{
3c72bf71
HK		 1165 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1166 r8168ep_ocp_write(tp, 0x01, 0x30,
1167 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
935e2218
CHL		 1168 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1169}
1170
1171static void rtl8168_driver_start(struct rtl8169_private *tp)
1172{
1173 switch (tp->mac_version) {
1174 case RTL_GIGA_MAC_VER_27:
1175 case RTL_GIGA_MAC_VER_28:
1176 case RTL_GIGA_MAC_VER_31:
1177 rtl8168dp_driver_start(tp);
1178 break;
1179 case RTL_GIGA_MAC_VER_49:
1180 case RTL_GIGA_MAC_VER_50:
1181 case RTL_GIGA_MAC_VER_51:
1182 rtl8168ep_driver_start(tp);
1183 break;
1184 default:
1185 BUG();
1186 break;
1187 }
1188}
2a9b4d96 1189
935e2218
CHL		 1190static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1191{
3c72bf71
HK		 1192 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1193 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
2a9b4d96
CHL		 1194}
1195
935e2218
CHL		 1196static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1197{
003609da 1198 rtl8168ep_stop_cmac(tp);
3c72bf71
HK		 1199 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1200 r8168ep_ocp_write(tp, 0x01, 0x30,
1201 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
935e2218
CHL		 1202 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1203}
1204
1205static void rtl8168_driver_stop(struct rtl8169_private *tp)
1206{
1207 switch (tp->mac_version) {
1208 case RTL_GIGA_MAC_VER_27:
1209 case RTL_GIGA_MAC_VER_28:
1210 case RTL_GIGA_MAC_VER_31:
1211 rtl8168dp_driver_stop(tp);
1212 break;
1213 case RTL_GIGA_MAC_VER_49:
1214 case RTL_GIGA_MAC_VER_50:
1215 case RTL_GIGA_MAC_VER_51:
1216 rtl8168ep_driver_stop(tp);
1217 break;
1218 default:
1219 BUG();
1220 break;
1221 }
1222}
1223
9dbe7896 1224static bool r8168dp_check_dash(struct rtl8169_private *tp)
2a9b4d96
CHL		 1225{
1226 u16 reg = rtl8168_get_ocp_reg(tp);
1227
3c72bf71 1228 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
2a9b4d96
CHL		 1229}
1230
9dbe7896 1231static bool r8168ep_check_dash(struct rtl8169_private *tp)
935e2218 1232{
3c72bf71 1233 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
935e2218
CHL		 1234}
1235
9dbe7896 1236static bool r8168_check_dash(struct rtl8169_private *tp)
935e2218
CHL		 1237{
1238 switch (tp->mac_version) {
1239 case RTL_GIGA_MAC_VER_27:
1240 case RTL_GIGA_MAC_VER_28:
1241 case RTL_GIGA_MAC_VER_31:
1242 return r8168dp_check_dash(tp);
1243 case RTL_GIGA_MAC_VER_49:
1244 case RTL_GIGA_MAC_VER_50:
1245 case RTL_GIGA_MAC_VER_51:
1246 return r8168ep_check_dash(tp);
1247 default:
9dbe7896 1248 return false;
935e2218
CHL		 1249 }
1250}
1251
c28aa385 1252struct exgmac_reg {
1253 u16 addr;
1254 u16 mask;
1255 u32 val;
1256};
1257
fdf6fc06 1258static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1259 const struct exgmac_reg *r, int len)
1260{
1261 while (len-- > 0) {
fdf6fc06 1262 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1263 r++;
1264 }
1265}
1266
ffc46952
FR		 1267DECLARE_RTL_COND(rtl_efusear_cond)
1268{
1ef7286e 1269 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
ffc46952
FR		 1270}
1271
fdf6fc06 1272static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1273{
1ef7286e 1274 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
daf9df6d 1275
ffc46952 1276 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1ef7286e 1277 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1278}
1279
9085cdfa
FR		 1280static u16 rtl_get_events(struct rtl8169_private *tp)
1281{
1ef7286e 1282 return RTL_R16(tp, IntrStatus);
9085cdfa
FR		 1283}
1284
1285static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1286{
1ef7286e 1287 RTL_W16(tp, IntrStatus, bits);
9085cdfa
FR		 1288}
1289
1290static void rtl_irq_disable(struct rtl8169_private *tp)
1291{
1ef7286e 1292 RTL_W16(tp, IntrMask, 0);
3e990ff5
FR		 1293}
1294
da78dbff
FR		 1295#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1296#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1297#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1298
fe716f8a 1299static void rtl_irq_enable(struct rtl8169_private *tp)
da78dbff 1300{
559c3c04 1301 RTL_W16(tp, IntrMask, tp->irq_mask);
da78dbff
FR		 1302}
1303
811fd301 1304static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1305{
9085cdfa 1306 rtl_irq_disable(tp);
de20e12f
HK		 1307 rtl_ack_events(tp, 0xffff);
1308 /* PCI commit */
1ef7286e 1309 RTL_R8(tp, ChipCmd);
1da177e4
LT		 1310}
1311
70090424
HW		 1312static void rtl_link_chg_patch(struct rtl8169_private *tp)
1313{
70090424 1314 struct net_device *dev = tp->dev;
29a12b49 1315 struct phy_device *phydev = dev->phydev;
70090424
HW		 1316
1317 if (!netif_running(dev))
1318 return;
1319
b3d7b2f2
HW		 1320 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1321 tp->mac_version == RTL_GIGA_MAC_VER_38) {
29a12b49 1322 if (phydev->speed == SPEED_1000) {
fdf6fc06
FR		 1323 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1324 ERIAR_EXGMAC);
1325 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1326 ERIAR_EXGMAC);
29a12b49 1327 } else if (phydev->speed == SPEED_100) {
fdf6fc06
FR		 1328 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1329 ERIAR_EXGMAC);
1330 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1331 ERIAR_EXGMAC);
70090424 1332 } else {
fdf6fc06
FR		 1333 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1334 ERIAR_EXGMAC);
1335 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1336 ERIAR_EXGMAC);
70090424
HW		 1337 }
1338 /* Reset packet filter */
706123d0 1339 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1340 ERIAR_EXGMAC);
706123d0 1341 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1342 ERIAR_EXGMAC);
c2218925
HW		 1343 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1344 tp->mac_version == RTL_GIGA_MAC_VER_36) {
29a12b49 1345 if (phydev->speed == SPEED_1000) {
fdf6fc06
FR		 1346 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1347 ERIAR_EXGMAC);
1348 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1349 ERIAR_EXGMAC);
c2218925 1350 } else {
fdf6fc06
FR		 1351 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1352 ERIAR_EXGMAC);
1353 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1354 ERIAR_EXGMAC);
c2218925 1355 }
7e18dca1 1356 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
29a12b49 1357 if (phydev->speed == SPEED_10) {
fdf6fc06
FR		 1358 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1359 ERIAR_EXGMAC);
1360 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1361 ERIAR_EXGMAC);
7e18dca1 1362 } else {
fdf6fc06
FR		 1363 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1364 ERIAR_EXGMAC);
7e18dca1 1365 }
70090424
HW		 1366 }
1367}
1368
e1759441
RW		 1369#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1370
1371static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1372{
61a4dcc2 1373 u8 options;
e1759441 1374 u32 wolopts = 0;
61a4dcc2 1375
1ef7286e 1376 options = RTL_R8(tp, Config1);
61a4dcc2 1377 if (!(options & PMEnable))
e1759441 1378 return 0;
61a4dcc2 1379
1ef7286e 1380 options = RTL_R8(tp, Config3);
61a4dcc2 1381 if (options & LinkUp)
e1759441 1382 wolopts |= WAKE_PHY;
6e1d0b89 1383 switch (tp->mac_version) {
2a71883c
HK		 1384 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1385 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1386 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1387 wolopts |= WAKE_MAGIC;
1388 break;
1389 default:
1390 if (options & MagicPacket)
1391 wolopts |= WAKE_MAGIC;
1392 break;
1393 }
61a4dcc2 1394
1ef7286e 1395 options = RTL_R8(tp, Config5);
61a4dcc2 1396 if (options & UWF)
e1759441 1397 wolopts |= WAKE_UCAST;
61a4dcc2 1398 if (options & BWF)
e1759441 1399 wolopts |= WAKE_BCAST;
61a4dcc2 1400 if (options & MWF)
e1759441 1401 wolopts |= WAKE_MCAST;
61a4dcc2 1402
e1759441 1403 return wolopts;
61a4dcc2
FR		 1404}
1405
e1759441 1406static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1407{
1408 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1409
da78dbff 1410 rtl_lock_work(tp);
e1759441 1411 wol->supported = WAKE_ANY;
433f9d0d 1412 wol->wolopts = tp->saved_wolopts;
da78dbff 1413 rtl_unlock_work(tp);
e1759441
RW		 1414}
1415
1416static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1417{
6e1d0b89 1418 unsigned int i, tmp;
350f7596 1419 static const struct {
61a4dcc2
FR		 1420 u32 opt;
1421 u16 reg;
1422 u8 mask;
1423 } cfg[] = {
61a4dcc2 1424 { WAKE_PHY, Config3, LinkUp },
61a4dcc2
FR		 1425 { WAKE_UCAST, Config5, UWF },
1426 { WAKE_BCAST, Config5, BWF },
1427 { WAKE_MCAST, Config5, MWF },
6e1d0b89
CHL		 1428 { WAKE_ANY, Config5, LanWake },
1429 { WAKE_MAGIC, Config3, MagicPacket }
61a4dcc2 1430 };
851e6022 1431 u8 options;
61a4dcc2 1432
1ef7286e 1433 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
61a4dcc2 1434
6e1d0b89 1435 switch (tp->mac_version) {
2a71883c
HK		 1436 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1437 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1438 tmp = ARRAY_SIZE(cfg) - 1;
1439 if (wolopts & WAKE_MAGIC)
706123d0 1440 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1441 0x0dc,
1442 ERIAR_MASK_0100,
1443 MagicPacket_v2,
1444 0x0000,
1445 ERIAR_EXGMAC);
1446 else
706123d0 1447 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1448 0x0dc,
1449 ERIAR_MASK_0100,
1450 0x0000,
1451 MagicPacket_v2,
1452 ERIAR_EXGMAC);
1453 break;
1454 default:
1455 tmp = ARRAY_SIZE(cfg);
1456 break;
1457 }
1458
1459 for (i = 0; i < tmp; i++) {
1ef7286e 1460 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
e1759441 1461 if (wolopts & cfg[i].opt)
61a4dcc2 1462 options |= cfg[i].mask;
1ef7286e 1463 RTL_W8(tp, cfg[i].reg, options);
61a4dcc2
FR		 1464 }
1465
851e6022
FR		 1466 switch (tp->mac_version) {
1467 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1ef7286e 1468 options = RTL_R8(tp, Config1) & ~PMEnable;
851e6022
FR		 1469 if (wolopts)
1470 options |= PMEnable;
1ef7286e 1471 RTL_W8(tp, Config1, options);
851e6022
FR		 1472 break;
1473 default:
1ef7286e 1474 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
d387b427
FR		 1475 if (wolopts)
1476 options |= PME_SIGNAL;
1ef7286e 1477 RTL_W8(tp, Config2, options);
851e6022
FR		 1478 break;
1479 }
1480
1ef7286e 1481 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
3bd82645
HK		 1482
1483 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
e1759441
RW		 1484}
1485
1486static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1487{
1488 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 1489 struct device *d = tp_to_dev(tp);
5fa80a32 1490
2f533f6b
HK		 1491 if (wol->wolopts & ~WAKE_ANY)
1492 return -EINVAL;
1493
5fa80a32 1494 pm_runtime_get_noresume(d);
e1759441 1495
da78dbff 1496 rtl_lock_work(tp);
61a4dcc2 1497
2f533f6b 1498 tp->saved_wolopts = wol->wolopts;
433f9d0d 1499
5fa80a32 1500 if (pm_runtime_active(d))
433f9d0d 1501 __rtl8169_set_wol(tp, tp->saved_wolopts);
da78dbff
FR		 1502
1503 rtl_unlock_work(tp);
61a4dcc2 1504
5fa80a32
CHL		 1505 pm_runtime_put_noidle(d);
1506
61a4dcc2
FR		 1507 return 0;
1508}
1509
31bd204f
FR		 1510static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1511{
85bffe6c 1512 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1513}
1514
1da177e4
LT		 1515static void rtl8169_get_drvinfo(struct net_device *dev,
1516 struct ethtool_drvinfo *info)
1517{
1518 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1519 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1520
68aad78c 1521 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
68aad78c 1522 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1523 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1524 if (!IS_ERR_OR_NULL(rtl_fw))
1525 strlcpy(info->fw_version, rtl_fw->version,
1526 sizeof(info->fw_version));
1da177e4
LT		 1527}
1528
1529static int rtl8169_get_regs_len(struct net_device *dev)
1530{
1531 return R8169_REGS_SIZE;
1532}
1533
c8f44aff
MM		 1534static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1535 netdev_features_t features)
1da177e4 1536{
d58d46b5
FR		 1537 struct rtl8169_private *tp = netdev_priv(dev);
1538
2b7b4318 1539 if (dev->mtu > TD_MSS_MAX)
350fb32a 1540 features &= ~NETIF_F_ALL_TSO;
1da177e4 1541
d58d46b5 1542 if (dev->mtu > JUMBO_1K &&
6ed0e08f 1543 tp->mac_version > RTL_GIGA_MAC_VER_06)
d58d46b5
FR		 1544 features &= ~NETIF_F_IP_CSUM;
1545
350fb32a 1546 return features;
1da177e4
LT		 1547}
1548
a3984578
HK		 1549static int rtl8169_set_features(struct net_device *dev,
1550 netdev_features_t features)
1da177e4
LT		 1551{
1552 struct rtl8169_private *tp = netdev_priv(dev);
929a031d 1553 u32 rx_config;
1da177e4 1554
a3984578
HK		 1555 rtl_lock_work(tp);
1556
1ef7286e 1557 rx_config = RTL_R32(tp, RxConfig);
929a031d 1558 if (features & NETIF_F_RXALL)
1559 rx_config |= (AcceptErr | AcceptRunt);
1560 else
1561 rx_config &= ~(AcceptErr | AcceptRunt);
1da177e4 1562
1ef7286e 1563 RTL_W32(tp, RxConfig, rx_config);
350fb32a 1564
929a031d 1565 if (features & NETIF_F_RXCSUM)
1566 tp->cp_cmd |= RxChkSum;
1567 else
1568 tp->cp_cmd &= ~RxChkSum;
6bbe021d 1569
929a031d 1570 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1571 tp->cp_cmd |= RxVlan;
1572 else
1573 tp->cp_cmd &= ~RxVlan;
1574
1ef7286e
AS		 1575 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1576 RTL_R16(tp, CPlusCmd);
1da177e4 1577
da78dbff 1578 rtl_unlock_work(tp);
1da177e4
LT		 1579
1580 return 0;
1581}
1582
810f4893 1583static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 1584{
df8a39de
JP		 1585 return (skb_vlan_tag_present(skb)) ?
1586 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1da177e4
LT		 1587}
1588
7a8fc77b 1589static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1590{
1591 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1592
7a8fc77b 1593 if (opts2 & RxVlanTag)
86a9bad3 1594 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1da177e4
LT		 1595}
1596
1da177e4
LT		 1597static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1598 void *p)
1599{
5b0384f4 1600 struct rtl8169_private *tp = netdev_priv(dev);
15edae91
PW		 1601 u32 __iomem *data = tp->mmio_addr;
1602 u32 *dw = p;
1603 int i;
1da177e4 1604
da78dbff 1605 rtl_lock_work(tp);
15edae91
PW		 1606 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1607 memcpy_fromio(dw++, data++, 4);
da78dbff 1608 rtl_unlock_work(tp);
1da177e4
LT		 1609}
1610
b57b7e5a
SH		 1611static u32 rtl8169_get_msglevel(struct net_device *dev)
1612{
1613 struct rtl8169_private *tp = netdev_priv(dev);
1614
1615 return tp->msg_enable;
1616}
1617
1618static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1619{
1620 struct rtl8169_private *tp = netdev_priv(dev);
1621
1622 tp->msg_enable = value;
1623}
1624
d4a3a0fc
SH		 1625static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1626 "tx_packets",
1627 "rx_packets",
1628 "tx_errors",
1629 "rx_errors",
1630 "rx_missed",
1631 "align_errors",
1632 "tx_single_collisions",
1633 "tx_multi_collisions",
1634 "unicast",
1635 "broadcast",
1636 "multicast",
1637 "tx_aborted",
1638 "tx_underrun",
1639};
1640
b9f2c044 1641static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1642{
b9f2c044
JG		 1643 switch (sset) {
1644 case ETH_SS_STATS:
1645 return ARRAY_SIZE(rtl8169_gstrings);
1646 default:
1647 return -EOPNOTSUPP;
1648 }
d4a3a0fc
SH		 1649}
1650
42020320 1651DECLARE_RTL_COND(rtl_counters_cond)
6e85d5ad 1652{
1ef7286e 1653 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
6e85d5ad
CV		 1654}
1655
e71c9ce2 1656static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
6e85d5ad 1657{
42020320
CV		 1658 dma_addr_t paddr = tp->counters_phys_addr;
1659 u32 cmd;
6e85d5ad 1660
1ef7286e
AS		 1661 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1662 RTL_R32(tp, CounterAddrHigh);
42020320 1663 cmd = (u64)paddr & DMA_BIT_MASK(32);
1ef7286e
AS		 1664 RTL_W32(tp, CounterAddrLow, cmd);
1665 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
6e85d5ad 1666
a78e9366 1667 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
6e85d5ad
CV		 1668}
1669
e71c9ce2 1670static bool rtl8169_reset_counters(struct rtl8169_private *tp)
6e85d5ad 1671{
6e85d5ad
CV		 1672 /*
1673 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1674 * tally counters.
1675 */
1676 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1677 return true;
1678
e71c9ce2 1679 return rtl8169_do_counters(tp, CounterReset);
ffc46952
FR		 1680}
1681
e71c9ce2 1682static bool rtl8169_update_counters(struct rtl8169_private *tp)
d4a3a0fc 1683{
10262b0b
HK		 1684 u8 val = RTL_R8(tp, ChipCmd);
1685
355423d0
IV		 1686 /*
1687 * Some chips are unable to dump tally counters when the receiver
10262b0b 1688 * is disabled. If 0xff chip may be in a PCI power-save state.
355423d0 1689 */
10262b0b 1690 if (!(val & CmdRxEnb) || val == 0xff)
6e85d5ad 1691 return true;
d4a3a0fc 1692
e71c9ce2 1693 return rtl8169_do_counters(tp, CounterDump);
6e85d5ad
CV		 1694}
1695
e71c9ce2 1696static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
6e85d5ad 1697{
42020320 1698 struct rtl8169_counters *counters = tp->counters;
6e85d5ad
CV		 1699 bool ret = false;
1700
1701 /*
1702 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1703 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1704 * reset by a power cycle, while the counter values collected by the
1705 * driver are reset at every driver unload/load cycle.
1706 *
1707 * To make sure the HW values returned by @get_stats64 match the SW
1708 * values, we collect the initial values at first open(*) and use them
1709 * as offsets to normalize the values returned by @get_stats64.
1710 *
1711 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1712 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1713 * set at open time by rtl_hw_start.
1714 */
1715
1716 if (tp->tc_offset.inited)
1717 return true;
1718
1719 /* If both, reset and update fail, propagate to caller. */
e71c9ce2 1720 if (rtl8169_reset_counters(tp))
6e85d5ad
CV		 1721 ret = true;
1722
e71c9ce2 1723 if (rtl8169_update_counters(tp))
6e85d5ad
CV		 1724 ret = true;
1725
42020320
CV		 1726 tp->tc_offset.tx_errors = counters->tx_errors;
1727 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1728 tp->tc_offset.tx_aborted = counters->tx_aborted;
6e85d5ad
CV		 1729 tp->tc_offset.inited = true;
1730
1731 return ret;
d4a3a0fc
SH		 1732}
1733
355423d0
IV		 1734static void rtl8169_get_ethtool_stats(struct net_device *dev,
1735 struct ethtool_stats *stats, u64 *data)
1736{
1737 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 1738 struct device *d = tp_to_dev(tp);
42020320 1739 struct rtl8169_counters *counters = tp->counters;
355423d0
IV		 1740
1741 ASSERT_RTNL();
1742
e0636236
CHL		 1743 pm_runtime_get_noresume(d);
1744
1745 if (pm_runtime_active(d))
e71c9ce2 1746 rtl8169_update_counters(tp);
e0636236
CHL		 1747
1748 pm_runtime_put_noidle(d);
355423d0 1749
42020320
CV		 1750 data[0] = le64_to_cpu(counters->tx_packets);
1751 data[1] = le64_to_cpu(counters->rx_packets);
1752 data[2] = le64_to_cpu(counters->tx_errors);
1753 data[3] = le32_to_cpu(counters->rx_errors);
1754 data[4] = le16_to_cpu(counters->rx_missed);
1755 data[5] = le16_to_cpu(counters->align_errors);
1756 data[6] = le32_to_cpu(counters->tx_one_collision);
1757 data[7] = le32_to_cpu(counters->tx_multi_collision);
1758 data[8] = le64_to_cpu(counters->rx_unicast);
1759 data[9] = le64_to_cpu(counters->rx_broadcast);
1760 data[10] = le32_to_cpu(counters->rx_multicast);
1761 data[11] = le16_to_cpu(counters->tx_aborted);
1762 data[12] = le16_to_cpu(counters->tx_underun);
355423d0
IV		 1763}
1764
d4a3a0fc
SH		 1765static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1766{
1767 switch(stringset) {
1768 case ETH_SS_STATS:
1769 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1770 break;
1771 }
1772}
1773
50970831
FR		 1774/*
1775 * Interrupt coalescing
1776 *
1777 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1778 * > 8169, 8168 and 810x line of chipsets
1779 *
1780 * 8169, 8168, and 8136(810x) serial chipsets support it.
1781 *
1782 * > 2 - the Tx timer unit at gigabit speed
1783 *
1784 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1785 * (0xe0) bit 1 and bit 0.
1786 *
1787 * For 8169
1788 * bit[1:0] \ speed 1000M 100M 10M
1789 * 0 0 320ns 2.56us 40.96us
1790 * 0 1 2.56us 20.48us 327.7us
1791 * 1 0 5.12us 40.96us 655.4us
1792 * 1 1 10.24us 81.92us 1.31ms
1793 *
1794 * For the other
1795 * bit[1:0] \ speed 1000M 100M 10M
1796 * 0 0 5us 2.56us 40.96us
1797 * 0 1 40us 20.48us 327.7us
1798 * 1 0 80us 40.96us 655.4us
1799 * 1 1 160us 81.92us 1.31ms
1800 */
1801
1802/* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1803struct rtl_coalesce_scale {
1804 /* Rx / Tx */
1805 u32 nsecs[2];
1806};
1807
1808/* rx/tx scale factors for all CPlusCmd[0:1] cases */
1809struct rtl_coalesce_info {
1810 u32 speed;
1811 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1812};
1813
1814/* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1815#define rxtx_x1822(r, t) { \
1816 {{(r), (t)}}, \
1817 {{(r)*8, (t)*8}}, \
1818 {{(r)*8*2, (t)*8*2}}, \
1819 {{(r)*8*2*2, (t)*8*2*2}}, \
1820}
1821static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1822 /* speed delays: rx00 tx00 */
1823 { SPEED_10, rxtx_x1822(40960, 40960) },
1824 { SPEED_100, rxtx_x1822( 2560, 2560) },
1825 { SPEED_1000, rxtx_x1822( 320, 320) },
1826 { 0 },
1827};
1828
1829static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1830 /* speed delays: rx00 tx00 */
1831 { SPEED_10, rxtx_x1822(40960, 40960) },
1832 { SPEED_100, rxtx_x1822( 2560, 2560) },
1833 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1834 { 0 },
1835};
1836#undef rxtx_x1822
1837
1838/* get rx/tx scale vector corresponding to current speed */
1839static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1840{
1841 struct rtl8169_private *tp = netdev_priv(dev);
1842 struct ethtool_link_ksettings ecmd;
1843 const struct rtl_coalesce_info *ci;
1844 int rc;
1845
45772433 1846 rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
50970831
FR		 1847 if (rc < 0)
1848 return ERR_PTR(rc);
1849
1850 for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1851 if (ecmd.base.speed == ci->speed) {
1852 return ci;
1853 }
1854 }
1855
1856 return ERR_PTR(-ELNRNG);
1857}
1858
1859static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1860{
1861 struct rtl8169_private *tp = netdev_priv(dev);
50970831
FR		 1862 const struct rtl_coalesce_info *ci;
1863 const struct rtl_coalesce_scale *scale;
1864 struct {
1865 u32 *max_frames;
1866 u32 *usecs;
1867 } coal_settings [] = {
1868 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1869 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1870 }, *p = coal_settings;
1871 int i;
1872 u16 w;
1873
1874 memset(ec, 0, sizeof(*ec));
1875
1876 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1877 ci = rtl_coalesce_info(dev);
1878 if (IS_ERR(ci))
1879 return PTR_ERR(ci);
1880
0ae0974e 1881 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
50970831
FR		 1882
1883 /* read IntrMitigate and adjust according to scale */
1ef7286e 1884 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
50970831
FR		 1885 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1886 w >>= RTL_COALESCE_SHIFT;
1887 *p->usecs = w & RTL_COALESCE_MASK;
1888 }
1889
1890 for (i = 0; i < 2; i++) {
1891 p = coal_settings + i;
1892 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1893
1894 /*
1895 * ethtool_coalesce says it is illegal to set both usecs and
1896 * max_frames to 0.
1897 */
1898 if (!*p->usecs && !*p->max_frames)
1899 *p->max_frames = 1;
1900 }
1901
1902 return 0;
1903}
1904
1905/* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1906static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1907 struct net_device *dev, u32 nsec, u16 *cp01)
1908{
1909 const struct rtl_coalesce_info *ci;
1910 u16 i;
1911
1912 ci = rtl_coalesce_info(dev);
1913 if (IS_ERR(ci))
1914 return ERR_CAST(ci);
1915
1916 for (i = 0; i < 4; i++) {
1917 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1918 ci->scalev[i].nsecs[1]);
1919 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1920 *cp01 = i;
1921 return &ci->scalev[i];
1922 }
1923 }
1924
1925 return ERR_PTR(-EINVAL);
1926}
1927
1928static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1929{
1930 struct rtl8169_private *tp = netdev_priv(dev);
50970831
FR		 1931 const struct rtl_coalesce_scale *scale;
1932 struct {
1933 u32 frames;
1934 u32 usecs;
1935 } coal_settings [] = {
1936 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1937 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1938 }, *p = coal_settings;
1939 u16 w = 0, cp01;
1940 int i;
1941
1942 scale = rtl_coalesce_choose_scale(dev,
1943 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1944 if (IS_ERR(scale))
1945 return PTR_ERR(scale);
1946
1947 for (i = 0; i < 2; i++, p++) {
1948 u32 units;
1949
1950 /*
1951 * accept max_frames=1 we returned in rtl_get_coalesce.
1952 * accept it not only when usecs=0 because of e.g. the following scenario:
1953 *
1954 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1955 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1956 * - then user does `ethtool -C eth0 rx-usecs 100`
1957 *
1958 * since ethtool sends to kernel whole ethtool_coalesce
1959 * settings, if we do not handle rx_usecs=!0, rx_frames=1
1960 * we'll reject it below in `frames % 4 != 0`.
1961 */
1962 if (p->frames == 1) {
1963 p->frames = 0;
1964 }
1965
1966 units = p->usecs * 1000 / scale->nsecs[i];
1967 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1968 return -EINVAL;
1969
1970 w <<= RTL_COALESCE_SHIFT;
1971 w |= units;
1972 w <<= RTL_COALESCE_SHIFT;
1973 w |= p->frames >> 2;
1974 }
1975
1976 rtl_lock_work(tp);
1977
1ef7286e 1978 RTL_W16(tp, IntrMitigate, swab16(w));
50970831 1979
9a3c81fa 1980 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1ef7286e
AS		 1981 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1982 RTL_R16(tp, CPlusCmd);
50970831
FR		 1983
1984 rtl_unlock_work(tp);
1985
1986 return 0;
1987}
1988
7282d491 1989static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1990 .get_drvinfo = rtl8169_get_drvinfo,
1991 .get_regs_len = rtl8169_get_regs_len,
1992 .get_link = ethtool_op_get_link,
50970831
FR		 1993 .get_coalesce = rtl_get_coalesce,
1994 .set_coalesce = rtl_set_coalesce,
b57b7e5a
SH		 1995 .get_msglevel = rtl8169_get_msglevel,
1996 .set_msglevel = rtl8169_set_msglevel,
1da177e4 1997 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1998 .get_wol = rtl8169_get_wol,
1999 .set_wol = rtl8169_set_wol,
d4a3a0fc 2000 .get_strings = rtl8169_get_strings,
b9f2c044 2001 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2002 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2003 .get_ts_info = ethtool_op_get_ts_info,
dd84957e 2004 .nway_reset = phy_ethtool_nway_reset,
45772433
HK		 2005 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2006 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1da177e4
LT		 2007};
2008
b4cc2dcc 2009static void rtl8169_get_mac_version(struct rtl8169_private *tp)
1da177e4 2010{
0e485150
FR		 2011 /*
2012 * The driver currently handles the 8168Bf and the 8168Be identically
2013 * but they can be identified more specifically through the test below
2014 * if needed:
2015 *
1ef7286e 2016 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2017 *
2018 * Same thing for the 8101Eb and the 8101Ec:
2019 *
1ef7286e 2020 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2021 */
3744100e 2022 static const struct rtl_mac_info {
55d2ad7b
HK		 2023 u16 mask;
2024 u16 val;
2025 u16 mac_version;
1da177e4 2026 } mac_info[] = {
935e2218 2027 /* 8168EP family. */
55d2ad7b
HK		 2028 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2029 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2030 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
935e2218 2031
6e1d0b89 2032 /* 8168H family. */
55d2ad7b
HK		 2033 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2034 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
6e1d0b89 2035
c558386b 2036 /* 8168G family. */
55d2ad7b
HK		 2037 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2038 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2039 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2040 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
c558386b 2041
c2218925 2042 /* 8168F family. */
55d2ad7b
HK		 2043 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2044 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2045 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
c2218925 2046
01dc7fec 2047 /* 8168E family. */
55d2ad7b
HK		 2048 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2049 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2050 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
01dc7fec 2051
5b538df9 2052 /* 8168D family. */
55d2ad7b
HK		 2053 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2054 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
5b538df9 2055
e6de30d6 2056 /* 8168DP family. */
55d2ad7b
HK		 2057 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2058 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2059 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
e6de30d6 2060
ef808d50 2061 /* 8168C family. */
55d2ad7b
HK		 2062 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2063 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2064 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2065 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2066 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2067 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2068 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2069
2070 /* 8168B family. */
55d2ad7b
HK		 2071 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2072 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2073 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
e3cf0cc0
FR		 2074
2075 /* 8101 family. */
55d2ad7b
HK		 2076 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2077 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2078 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2079 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2080 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2081 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2082 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2083 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2084 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2085 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2086 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2087 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2088 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2089 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
e3cf0cc0 2090 /* FIXME: where did these entries come from ? -- FR */
55d2ad7b
HK		 2091 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2092 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
e3cf0cc0
FR		 2093
2094 /* 8110 family. */
55d2ad7b
HK		 2095 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2096 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2097 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2098 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2099 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2100 { 0xfc8, 0x000, RTL_GIGA_MAC_VER_01 },
e3cf0cc0 2101
f21b75e9 2102 /* Catch-all */
55d2ad7b 2103 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2104 };
2105 const struct rtl_mac_info *p = mac_info;
55d2ad7b 2106 u16 reg = RTL_R32(tp, TxConfig) >> 20;
1da177e4 2107
e3cf0cc0 2108 while ((reg & p->mask) != p->val)
1da177e4
LT		 2109 p++;
2110 tp->mac_version = p->mac_version;
5d320a20
FR		 2111
2112 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
b4cc2dcc 2113 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
45f1996f
HK		 2114 } else if (!tp->supports_gmii) {
2115 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2116 tp->mac_version = RTL_GIGA_MAC_VER_43;
2117 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2118 tp->mac_version = RTL_GIGA_MAC_VER_47;
2119 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2120 tp->mac_version = RTL_GIGA_MAC_VER_48;
5d320a20 2121 }
1da177e4
LT		 2122}
2123
867763c1
FR		 2124struct phy_reg {
2125 u16 reg;
2126 u16 val;
2127};
2128
4da19633 2129static void rtl_writephy_batch(struct rtl8169_private *tp,
2130 const struct phy_reg *regs, int len)
867763c1
FR		 2131{
2132 while (len-- > 0) {
4da19633 2133 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2134 regs++;
2135 }
2136}
2137
bca03d5f 2138#define PHY_READ 0x00000000
2139#define PHY_DATA_OR 0x10000000
2140#define PHY_DATA_AND 0x20000000
2141#define PHY_BJMPN 0x30000000
eee3786f 2142#define PHY_MDIO_CHG 0x40000000
bca03d5f 2143#define PHY_CLEAR_READCOUNT 0x70000000
2144#define PHY_WRITE 0x80000000
2145#define PHY_READCOUNT_EQ_SKIP 0x90000000
2146#define PHY_COMP_EQ_SKIPN 0xa0000000
2147#define PHY_COMP_NEQ_SKIPN 0xb0000000
2148#define PHY_WRITE_PREVIOUS 0xc0000000
2149#define PHY_SKIPN 0xd0000000
2150#define PHY_DELAY_MS 0xe0000000
bca03d5f 2151
960aee6c
HW		 2152struct fw_info {
2153 u32 magic;
2154 char version[RTL_VER_SIZE];
2155 __le32 fw_start;
2156 __le32 fw_len;
2157 u8 chksum;
2158} __packed;
2159
1c361efb
FR		 2160#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2161
2162static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2163{
b6ffd97f 2164 const struct firmware *fw = rtl_fw->fw;
960aee6c 2165 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2166 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2167 char *version = rtl_fw->version;
2168 bool rc = false;
2169
2170 if (fw->size < FW_OPCODE_SIZE)
2171 goto out;
960aee6c
HW		 2172
2173 if (!fw_info->magic) {
2174 size_t i, size, start;
2175 u8 checksum = 0;
2176
2177 if (fw->size < sizeof(*fw_info))
2178 goto out;
2179
2180 for (i = 0; i < fw->size; i++)
2181 checksum += fw->data[i];
2182 if (checksum != 0)
2183 goto out;
2184
2185 start = le32_to_cpu(fw_info->fw_start);
2186 if (start > fw->size)
2187 goto out;
2188
2189 size = le32_to_cpu(fw_info->fw_len);
2190 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2191 goto out;
2192
2193 memcpy(version, fw_info->version, RTL_VER_SIZE);
2194
2195 pa->code = (__le32 *)(fw->data + start);
2196 pa->size = size;
2197 } else {
1c361efb
FR		 2198 if (fw->size % FW_OPCODE_SIZE)
2199 goto out;
2200
2201 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2202
2203 pa->code = (__le32 *)fw->data;
2204 pa->size = fw->size / FW_OPCODE_SIZE;
2205 }
2206 version[RTL_VER_SIZE - 1] = 0;
2207
2208 rc = true;
2209out:
2210 return rc;
2211}
2212
fd112f2e
FR		 2213static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2214 struct rtl_fw_phy_action *pa)
1c361efb 2215{
fd112f2e 2216 bool rc = false;
1c361efb 2217 size_t index;
bca03d5f 2218
1c361efb
FR		 2219 for (index = 0; index < pa->size; index++) {
2220 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2221 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2222
42b82dc1 2223 switch(action & 0xf0000000) {
2224 case PHY_READ:
2225 case PHY_DATA_OR:
2226 case PHY_DATA_AND:
eee3786f 2227 case PHY_MDIO_CHG:
42b82dc1 2228 case PHY_CLEAR_READCOUNT:
2229 case PHY_WRITE:
2230 case PHY_WRITE_PREVIOUS:
2231 case PHY_DELAY_MS:
2232 break;
2233
2234 case PHY_BJMPN:
2235 if (regno > index) {
fd112f2e 2236 netif_err(tp, ifup, tp->dev,
cecb5fd7 2237 "Out of range of firmware\n");
fd112f2e 2238 goto out;
42b82dc1 2239 }
2240 break;
2241 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2242 if (index + 2 >= pa->size) {
fd112f2e 2243 netif_err(tp, ifup, tp->dev,
cecb5fd7 2244 "Out of range of firmware\n");
fd112f2e 2245 goto out;
42b82dc1 2246 }
2247 break;
2248 case PHY_COMP_EQ_SKIPN:
2249 case PHY_COMP_NEQ_SKIPN:
2250 case PHY_SKIPN:
1c361efb 2251 if (index + 1 + regno >= pa->size) {
fd112f2e 2252 netif_err(tp, ifup, tp->dev,
cecb5fd7 2253 "Out of range of firmware\n");
fd112f2e 2254 goto out;
42b82dc1 2255 }
bca03d5f 2256 break;
2257
42b82dc1 2258 default:
fd112f2e 2259 netif_err(tp, ifup, tp->dev,
42b82dc1 2260 "Invalid action 0x%08x\n", action);
fd112f2e 2261 goto out;
bca03d5f 2262 }
2263 }
fd112f2e
FR		 2264 rc = true;
2265out:
2266 return rc;
2267}
bca03d5f 2268
fd112f2e
FR		 2269static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2270{
2271 struct net_device *dev = tp->dev;
2272 int rc = -EINVAL;
2273
2274 if (!rtl_fw_format_ok(tp, rtl_fw)) {
5c2d2b14 2275 netif_err(tp, ifup, dev, "invalid firmware\n");
fd112f2e
FR		 2276 goto out;
2277 }
2278
2279 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2280 rc = 0;
2281out:
2282 return rc;
2283}
2284
2285static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2286{
2287 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
eee3786f 2288 struct mdio_ops org, *ops = &tp->mdio_ops;
fd112f2e
FR		 2289 u32 predata, count;
2290 size_t index;
2291
2292 predata = count = 0;
eee3786f 2293 org.write = ops->write;
2294 org.read = ops->read;
42b82dc1 2295
1c361efb
FR		 2296 for (index = 0; index < pa->size; ) {
2297 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2298 u32 data = action & 0x0000ffff;
42b82dc1 2299 u32 regno = (action & 0x0fff0000) >> 16;
2300
2301 if (!action)
2302 break;
bca03d5f 2303
2304 switch(action & 0xf0000000) {
42b82dc1 2305 case PHY_READ:
2306 predata = rtl_readphy(tp, regno);
2307 count++;
2308 index++;
2309 break;
2310 case PHY_DATA_OR:
2311 predata |= data;
2312 index++;
2313 break;
2314 case PHY_DATA_AND:
2315 predata &= data;
2316 index++;
2317 break;
2318 case PHY_BJMPN:
2319 index -= regno;
2320 break;
eee3786f 2321 case PHY_MDIO_CHG:
2322 if (data == 0) {
2323 ops->write = org.write;
2324 ops->read = org.read;
2325 } else if (data == 1) {
2326 ops->write = mac_mcu_write;
2327 ops->read = mac_mcu_read;
2328 }
2329
42b82dc1 2330 index++;
2331 break;
2332 case PHY_CLEAR_READCOUNT:
2333 count = 0;
2334 index++;
2335 break;
bca03d5f 2336 case PHY_WRITE:
42b82dc1 2337 rtl_writephy(tp, regno, data);
2338 index++;
2339 break;
2340 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2341 index += (count == data) ? 2 : 1;
bca03d5f 2342 break;
42b82dc1 2343 case PHY_COMP_EQ_SKIPN:
2344 if (predata == data)
2345 index += regno;
2346 index++;
2347 break;
2348 case PHY_COMP_NEQ_SKIPN:
2349 if (predata != data)
2350 index += regno;
2351 index++;
2352 break;
2353 case PHY_WRITE_PREVIOUS:
2354 rtl_writephy(tp, regno, predata);
2355 index++;
2356 break;
2357 case PHY_SKIPN:
2358 index += regno + 1;
2359 break;
2360 case PHY_DELAY_MS:
2361 mdelay(data);
2362 index++;
2363 break;
2364
bca03d5f 2365 default:
2366 BUG();
2367 }
2368 }
eee3786f 2369
2370 ops->write = org.write;
2371 ops->read = org.read;
bca03d5f 2372}
2373
f1e02ed1 2374static void rtl_release_firmware(struct rtl8169_private *tp)
2375{
b6ffd97f
FR		 2376 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2377 release_firmware(tp->rtl_fw->fw);
2378 kfree(tp->rtl_fw);
2379 }
2380 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2381}
2382
953a12cc 2383static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2384{
b6ffd97f 2385 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2386
2387 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
eef63cc1 2388 if (!IS_ERR_OR_NULL(rtl_fw))
b6ffd97f 2389 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2390}
2391
2392static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2393{
2394 if (rtl_readphy(tp, reg) != val)
2395 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2396 else
2397 rtl_apply_firmware(tp);
f1e02ed1 2398}
2399
4da19633 2400static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2401{
350f7596 2402 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2403 { 0x1f, 0x0001 },
2404 { 0x06, 0x006e },
2405 { 0x08, 0x0708 },
2406 { 0x15, 0x4000 },
2407 { 0x18, 0x65c7 },
1da177e4 2408
0b9b571d 2409 { 0x1f, 0x0001 },
2410 { 0x03, 0x00a1 },
2411 { 0x02, 0x0008 },
2412 { 0x01, 0x0120 },
2413 { 0x00, 0x1000 },
2414 { 0x04, 0x0800 },
2415 { 0x04, 0x0000 },
1da177e4 2416
0b9b571d 2417 { 0x03, 0xff41 },
2418 { 0x02, 0xdf60 },
2419 { 0x01, 0x0140 },
2420 { 0x00, 0x0077 },
2421 { 0x04, 0x7800 },
2422 { 0x04, 0x7000 },
2423
2424 { 0x03, 0x802f },
2425 { 0x02, 0x4f02 },
2426 { 0x01, 0x0409 },
2427 { 0x00, 0xf0f9 },
2428 { 0x04, 0x9800 },
2429 { 0x04, 0x9000 },
2430
2431 { 0x03, 0xdf01 },
2432 { 0x02, 0xdf20 },
2433 { 0x01, 0xff95 },
2434 { 0x00, 0xba00 },
2435 { 0x04, 0xa800 },
2436 { 0x04, 0xa000 },
2437
2438 { 0x03, 0xff41 },
2439 { 0x02, 0xdf20 },
2440 { 0x01, 0x0140 },
2441 { 0x00, 0x00bb },
2442 { 0x04, 0xb800 },
2443 { 0x04, 0xb000 },
2444
2445 { 0x03, 0xdf41 },
2446 { 0x02, 0xdc60 },
2447 { 0x01, 0x6340 },
2448 { 0x00, 0x007d },
2449 { 0x04, 0xd800 },
2450 { 0x04, 0xd000 },
2451
2452 { 0x03, 0xdf01 },
2453 { 0x02, 0xdf20 },
2454 { 0x01, 0x100a },
2455 { 0x00, 0xa0ff },
2456 { 0x04, 0xf800 },
2457 { 0x04, 0xf000 },
2458
2459 { 0x1f, 0x0000 },
2460 { 0x0b, 0x0000 },
2461 { 0x00, 0x9200 }
2462 };
1da177e4 2463
4da19633 2464 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2465}
2466
4da19633 2467static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2468{
350f7596 2469 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2470 { 0x1f, 0x0002 },
2471 { 0x01, 0x90d0 },
2472 { 0x1f, 0x0000 }
2473 };
2474
4da19633 2475 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2476}
2477
4da19633 2478static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2479{
2480 struct pci_dev *pdev = tp->pci_dev;
2e955856 2481
ccbae55e
SS		 2482 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2483 (pdev->subsystem_device != 0xe000))
2e955856 2484 return;
2485
4da19633 2486 rtl_writephy(tp, 0x1f, 0x0001);
2487 rtl_writephy(tp, 0x10, 0xf01b);
2488 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2489}
2490
4da19633 2491static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2492{
350f7596 2493 static const struct phy_reg phy_reg_init[] = {
2e955856 2494 { 0x1f, 0x0001 },
2495 { 0x04, 0x0000 },
2496 { 0x03, 0x00a1 },
2497 { 0x02, 0x0008 },
2498 { 0x01, 0x0120 },
2499 { 0x00, 0x1000 },
2500 { 0x04, 0x0800 },
2501 { 0x04, 0x9000 },
2502 { 0x03, 0x802f },
2503 { 0x02, 0x4f02 },
2504 { 0x01, 0x0409 },
2505 { 0x00, 0xf099 },
2506 { 0x04, 0x9800 },
2507 { 0x04, 0xa000 },
2508 { 0x03, 0xdf01 },
2509 { 0x02, 0xdf20 },
2510 { 0x01, 0xff95 },
2511 { 0x00, 0xba00 },
2512 { 0x04, 0xa800 },
2513 { 0x04, 0xf000 },
2514 { 0x03, 0xdf01 },
2515 { 0x02, 0xdf20 },
2516 { 0x01, 0x101a },
2517 { 0x00, 0xa0ff },
2518 { 0x04, 0xf800 },
2519 { 0x04, 0x0000 },
2520 { 0x1f, 0x0000 },
2521
2522 { 0x1f, 0x0001 },
2523 { 0x10, 0xf41b },
2524 { 0x14, 0xfb54 },
2525 { 0x18, 0xf5c7 },
2526 { 0x1f, 0x0000 },
2527
2528 { 0x1f, 0x0001 },
2529 { 0x17, 0x0cc0 },
2530 { 0x1f, 0x0000 }
2531 };
2532
4da19633 2533 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2534
4da19633 2535 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2536}
2537
4da19633 2538static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2539{
350f7596 2540 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2541 { 0x1f, 0x0001 },
2542 { 0x04, 0x0000 },
2543 { 0x03, 0x00a1 },
2544 { 0x02, 0x0008 },
2545 { 0x01, 0x0120 },
2546 { 0x00, 0x1000 },
2547 { 0x04, 0x0800 },
2548 { 0x04, 0x9000 },
2549 { 0x03, 0x802f },
2550 { 0x02, 0x4f02 },
2551 { 0x01, 0x0409 },
2552 { 0x00, 0xf099 },
2553 { 0x04, 0x9800 },
2554 { 0x04, 0xa000 },
2555 { 0x03, 0xdf01 },
2556 { 0x02, 0xdf20 },
2557 { 0x01, 0xff95 },
2558 { 0x00, 0xba00 },
2559 { 0x04, 0xa800 },
2560 { 0x04, 0xf000 },
2561 { 0x03, 0xdf01 },
2562 { 0x02, 0xdf20 },
2563 { 0x01, 0x101a },
2564 { 0x00, 0xa0ff },
2565 { 0x04, 0xf800 },
2566 { 0x04, 0x0000 },
2567 { 0x1f, 0x0000 },
2568
2569 { 0x1f, 0x0001 },
2570 { 0x0b, 0x8480 },
2571 { 0x1f, 0x0000 },
2572
2573 { 0x1f, 0x0001 },
2574 { 0x18, 0x67c7 },
2575 { 0x04, 0x2000 },
2576 { 0x03, 0x002f },
2577 { 0x02, 0x4360 },
2578 { 0x01, 0x0109 },
2579 { 0x00, 0x3022 },
2580 { 0x04, 0x2800 },
2581 { 0x1f, 0x0000 },
2582
2583 { 0x1f, 0x0001 },
2584 { 0x17, 0x0cc0 },
2585 { 0x1f, 0x0000 }
2586 };
2587
4da19633 2588 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2589}
2590
4da19633 2591static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2592{
350f7596 2593 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2594 { 0x10, 0xf41b },
2595 { 0x1f, 0x0000 }
2596 };
2597
4da19633 2598 rtl_writephy(tp, 0x1f, 0x0001);
2599 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2600
4da19633 2601 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2602}
2603
4da19633 2604static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2605{
350f7596 2606 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2607 { 0x1f, 0x0001 },
2608 { 0x10, 0xf41b },
2609 { 0x1f, 0x0000 }
2610 };
2611
4da19633 2612 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2613}
2614
4da19633 2615static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2616{
350f7596 2617 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2618 { 0x1f, 0x0000 },
2619 { 0x1d, 0x0f00 },
2620 { 0x1f, 0x0002 },
2621 { 0x0c, 0x1ec8 },
2622 { 0x1f, 0x0000 }
2623 };
2624
4da19633 2625 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2626}
2627
4da19633 2628static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2629{
350f7596 2630 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2631 { 0x1f, 0x0001 },
2632 { 0x1d, 0x3d98 },
2633 { 0x1f, 0x0000 }
2634 };
2635
4da19633 2636 rtl_writephy(tp, 0x1f, 0x0000);
2637 rtl_patchphy(tp, 0x14, 1 << 5);
2638 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2639
4da19633 2640 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2641}
2642
4da19633 2643static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2644{
350f7596 2645 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2646 { 0x1f, 0x0001 },
2647 { 0x12, 0x2300 },
867763c1
FR		 2648 { 0x1f, 0x0002 },
2649 { 0x00, 0x88d4 },
2650 { 0x01, 0x82b1 },
2651 { 0x03, 0x7002 },
2652 { 0x08, 0x9e30 },
2653 { 0x09, 0x01f0 },
2654 { 0x0a, 0x5500 },
2655 { 0x0c, 0x00c8 },
2656 { 0x1f, 0x0003 },
2657 { 0x12, 0xc096 },
2658 { 0x16, 0x000a },
f50d4275
FR		 2659 { 0x1f, 0x0000 },
2660 { 0x1f, 0x0000 },
2661 { 0x09, 0x2000 },
2662 { 0x09, 0x0000 }
867763c1
FR		 2663 };
2664
4da19633 2665 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2666
4da19633 2667 rtl_patchphy(tp, 0x14, 1 << 5);
2668 rtl_patchphy(tp, 0x0d, 1 << 5);
2669 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2670}
2671
4da19633 2672static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2673{
350f7596 2674 static const struct phy_reg phy_reg_init[] = {
f50d4275 2675 { 0x1f, 0x0001 },
7da97ec9 2676 { 0x12, 0x2300 },
f50d4275
FR		 2677 { 0x03, 0x802f },
2678 { 0x02, 0x4f02 },
2679 { 0x01, 0x0409 },
2680 { 0x00, 0xf099 },
2681 { 0x04, 0x9800 },
2682 { 0x04, 0x9000 },
2683 { 0x1d, 0x3d98 },
7da97ec9
FR		 2684 { 0x1f, 0x0002 },
2685 { 0x0c, 0x7eb8 },
f50d4275
FR		 2686 { 0x06, 0x0761 },
2687 { 0x1f, 0x0003 },
2688 { 0x16, 0x0f0a },
7da97ec9
FR		 2689 { 0x1f, 0x0000 }
2690 };
2691
4da19633 2692 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2693
4da19633 2694 rtl_patchphy(tp, 0x16, 1 << 0);
2695 rtl_patchphy(tp, 0x14, 1 << 5);
2696 rtl_patchphy(tp, 0x0d, 1 << 5);
2697 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2698}
2699
4da19633 2700static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2701{
350f7596 2702 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2703 { 0x1f, 0x0001 },
2704 { 0x12, 0x2300 },
2705 { 0x1d, 0x3d98 },
2706 { 0x1f, 0x0002 },
2707 { 0x0c, 0x7eb8 },
2708 { 0x06, 0x5461 },
2709 { 0x1f, 0x0003 },
2710 { 0x16, 0x0f0a },
2711 { 0x1f, 0x0000 }
2712 };
2713
4da19633 2714 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2715
4da19633 2716 rtl_patchphy(tp, 0x16, 1 << 0);
2717 rtl_patchphy(tp, 0x14, 1 << 5);
2718 rtl_patchphy(tp, 0x0d, 1 << 5);
2719 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2720}
2721
4da19633 2722static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2723{
4da19633 2724 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2725}
2726
bca03d5f 2727static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2728{
350f7596 2729 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2730 /* Channel Estimation */
5b538df9 2731 { 0x1f, 0x0001 },
daf9df6d 2732 { 0x06, 0x4064 },
2733 { 0x07, 0x2863 },
2734 { 0x08, 0x059c },
2735 { 0x09, 0x26b4 },
2736 { 0x0a, 0x6a19 },
2737 { 0x0b, 0xdcc8 },
2738 { 0x10, 0xf06d },
2739 { 0x14, 0x7f68 },
2740 { 0x18, 0x7fd9 },
2741 { 0x1c, 0xf0ff },
2742 { 0x1d, 0x3d9c },
5b538df9 2743 { 0x1f, 0x0003 },
daf9df6d 2744 { 0x12, 0xf49f },
2745 { 0x13, 0x070b },
2746 { 0x1a, 0x05ad },
bca03d5f 2747 { 0x14, 0x94c0 },
2748
2749 /*
2750 * Tx Error Issue
cecb5fd7 2751 * Enhance line driver power
bca03d5f 2752 */
5b538df9 2753 { 0x1f, 0x0002 },
daf9df6d 2754 { 0x06, 0x5561 },
2755 { 0x1f, 0x0005 },
2756 { 0x05, 0x8332 },
bca03d5f 2757 { 0x06, 0x5561 },
2758
2759 /*
2760 * Can not link to 1Gbps with bad cable
2761 * Decrease SNR threshold form 21.07dB to 19.04dB
2762 */
2763 { 0x1f, 0x0001 },
2764 { 0x17, 0x0cc0 },
daf9df6d 2765
5b538df9 2766 { 0x1f, 0x0000 },
bca03d5f 2767 { 0x0d, 0xf880 }
daf9df6d 2768 };
2769
4da19633 2770 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2771
bca03d5f 2772 /*
2773 * Rx Error Issue
2774 * Fine Tune Switching regulator parameter
2775 */
4da19633 2776 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 2777 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2778 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2779
fdf6fc06 2780 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2781 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2782 { 0x1f, 0x0002 },
2783 { 0x05, 0x669a },
2784 { 0x1f, 0x0005 },
2785 { 0x05, 0x8330 },
2786 { 0x06, 0x669a },
2787 { 0x1f, 0x0002 }
2788 };
2789 int val;
2790
4da19633 2791 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2792
4da19633 2793 val = rtl_readphy(tp, 0x0d);
daf9df6d 2794
2795 if ((val & 0x00ff) != 0x006c) {
350f7596 2796 static const u32 set[] = {
daf9df6d 2797 0x0065, 0x0066, 0x0067, 0x0068,
2798 0x0069, 0x006a, 0x006b, 0x006c
2799 };
2800 int i;
2801
4da19633 2802 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2803
2804 val &= 0xff00;
2805 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2806 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2807 }
2808 } else {
350f7596 2809 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2810 { 0x1f, 0x0002 },
2811 { 0x05, 0x6662 },
2812 { 0x1f, 0x0005 },
2813 { 0x05, 0x8330 },
2814 { 0x06, 0x6662 }
2815 };
2816
4da19633 2817 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2818 }
2819
bca03d5f 2820 /* RSET couple improve */
4da19633 2821 rtl_writephy(tp, 0x1f, 0x0002);
2822 rtl_patchphy(tp, 0x0d, 0x0300);
2823 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2824
bca03d5f 2825 /* Fine tune PLL performance */
4da19633 2826 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 2827 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2828 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2829
4da19633 2830 rtl_writephy(tp, 0x1f, 0x0005);
2831 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2832
2833 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2834
4da19633 2835 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2836}
2837
bca03d5f 2838static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2839{
350f7596 2840 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2841 /* Channel Estimation */
daf9df6d 2842 { 0x1f, 0x0001 },
2843 { 0x06, 0x4064 },
2844 { 0x07, 0x2863 },
2845 { 0x08, 0x059c },
2846 { 0x09, 0x26b4 },
2847 { 0x0a, 0x6a19 },
2848 { 0x0b, 0xdcc8 },
2849 { 0x10, 0xf06d },
2850 { 0x14, 0x7f68 },
2851 { 0x18, 0x7fd9 },
2852 { 0x1c, 0xf0ff },
2853 { 0x1d, 0x3d9c },
2854 { 0x1f, 0x0003 },
2855 { 0x12, 0xf49f },
2856 { 0x13, 0x070b },
2857 { 0x1a, 0x05ad },
2858 { 0x14, 0x94c0 },
2859
bca03d5f 2860 /*
2861 * Tx Error Issue
cecb5fd7 2862 * Enhance line driver power
bca03d5f 2863 */
daf9df6d 2864 { 0x1f, 0x0002 },
2865 { 0x06, 0x5561 },
2866 { 0x1f, 0x0005 },
2867 { 0x05, 0x8332 },
bca03d5f 2868 { 0x06, 0x5561 },
2869
2870 /*
2871 * Can not link to 1Gbps with bad cable
2872 * Decrease SNR threshold form 21.07dB to 19.04dB
2873 */
2874 { 0x1f, 0x0001 },
2875 { 0x17, 0x0cc0 },
daf9df6d 2876
2877 { 0x1f, 0x0000 },
bca03d5f 2878 { 0x0d, 0xf880 }
5b538df9
FR		 2879 };
2880
4da19633 2881 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2882
fdf6fc06 2883 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2884 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2885 { 0x1f, 0x0002 },
2886 { 0x05, 0x669a },
5b538df9 2887 { 0x1f, 0x0005 },
daf9df6d 2888 { 0x05, 0x8330 },
2889 { 0x06, 0x669a },
2890
2891 { 0x1f, 0x0002 }
2892 };
2893 int val;
2894
4da19633 2895 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2896
4da19633 2897 val = rtl_readphy(tp, 0x0d);
daf9df6d 2898 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2899 static const u32 set[] = {
daf9df6d 2900 0x0065, 0x0066, 0x0067, 0x0068,
2901 0x0069, 0x006a, 0x006b, 0x006c
2902 };
2903 int i;
2904
4da19633 2905 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2906
2907 val &= 0xff00;
2908 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2909 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2910 }
2911 } else {
350f7596 2912 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2913 { 0x1f, 0x0002 },
2914 { 0x05, 0x2642 },
5b538df9 2915 { 0x1f, 0x0005 },
daf9df6d 2916 { 0x05, 0x8330 },
2917 { 0x06, 0x2642 }
5b538df9
FR		 2918 };
2919
4da19633 2920 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2921 }
2922
bca03d5f 2923 /* Fine tune PLL performance */
4da19633 2924 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 2925 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2926 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2927
bca03d5f 2928 /* Switching regulator Slew rate */
4da19633 2929 rtl_writephy(tp, 0x1f, 0x0002);
2930 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2931
4da19633 2932 rtl_writephy(tp, 0x1f, 0x0005);
2933 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2934
2935 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2936
4da19633 2937 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2938}
2939
4da19633 2940static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2941{
350f7596 2942 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2943 { 0x1f, 0x0002 },
2944 { 0x10, 0x0008 },
2945 { 0x0d, 0x006c },
2946
2947 { 0x1f, 0x0000 },
2948 { 0x0d, 0xf880 },
2949
2950 { 0x1f, 0x0001 },
2951 { 0x17, 0x0cc0 },
2952
2953 { 0x1f, 0x0001 },
2954 { 0x0b, 0xa4d8 },
2955 { 0x09, 0x281c },
2956 { 0x07, 0x2883 },
2957 { 0x0a, 0x6b35 },
2958 { 0x1d, 0x3da4 },
2959 { 0x1c, 0xeffd },
2960 { 0x14, 0x7f52 },
2961 { 0x18, 0x7fc6 },
2962 { 0x08, 0x0601 },
2963 { 0x06, 0x4063 },
2964 { 0x10, 0xf074 },
2965 { 0x1f, 0x0003 },
2966 { 0x13, 0x0789 },
2967 { 0x12, 0xf4bd },
2968 { 0x1a, 0x04fd },
2969 { 0x14, 0x84b0 },
2970 { 0x1f, 0x0000 },
2971 { 0x00, 0x9200 },
2972
2973 { 0x1f, 0x0005 },
2974 { 0x01, 0x0340 },
2975 { 0x1f, 0x0001 },
2976 { 0x04, 0x4000 },
2977 { 0x03, 0x1d21 },
2978 { 0x02, 0x0c32 },
2979 { 0x01, 0x0200 },
2980 { 0x00, 0x5554 },
2981 { 0x04, 0x4800 },
2982 { 0x04, 0x4000 },
2983 { 0x04, 0xf000 },
2984 { 0x03, 0xdf01 },
2985 { 0x02, 0xdf20 },
2986 { 0x01, 0x101a },
2987 { 0x00, 0xa0ff },
2988 { 0x04, 0xf800 },
2989 { 0x04, 0xf000 },
2990 { 0x1f, 0x0000 },
2991
2992 { 0x1f, 0x0007 },
2993 { 0x1e, 0x0023 },
2994 { 0x16, 0x0000 },
2995 { 0x1f, 0x0000 }
2996 };
2997
4da19633 2998 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2999}
3000
e6de30d6 3001static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3002{
3003 static const struct phy_reg phy_reg_init[] = {
3004 { 0x1f, 0x0001 },
3005 { 0x17, 0x0cc0 },
3006
3007 { 0x1f, 0x0007 },
3008 { 0x1e, 0x002d },
3009 { 0x18, 0x0040 },
3010 { 0x1f, 0x0000 }
3011 };
3012
3013 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3014 rtl_patchphy(tp, 0x0d, 1 << 5);
3015}
3016
70090424 3017static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3018{
3019 static const struct phy_reg phy_reg_init[] = {
3020 /* Enable Delay cap */
3021 { 0x1f, 0x0005 },
3022 { 0x05, 0x8b80 },
3023 { 0x06, 0xc896 },
3024 { 0x1f, 0x0000 },
3025
3026 /* Channel estimation fine tune */
3027 { 0x1f, 0x0001 },
3028 { 0x0b, 0x6c20 },
3029 { 0x07, 0x2872 },
3030 { 0x1c, 0xefff },
3031 { 0x1f, 0x0003 },
3032 { 0x14, 0x6420 },
3033 { 0x1f, 0x0000 },
3034
3035 /* Update PFM & 10M TX idle timer */
3036 { 0x1f, 0x0007 },
3037 { 0x1e, 0x002f },
3038 { 0x15, 0x1919 },
3039 { 0x1f, 0x0000 },
3040
3041 { 0x1f, 0x0007 },
3042 { 0x1e, 0x00ac },
3043 { 0x18, 0x0006 },
3044 { 0x1f, 0x0000 }
3045 };
3046
15ecd039
FR		 3047 rtl_apply_firmware(tp);
3048
01dc7fec 3049 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3050
3051 /* DCO enable for 10M IDLE Power */
3052 rtl_writephy(tp, 0x1f, 0x0007);
3053 rtl_writephy(tp, 0x1e, 0x0023);
76564428 3054 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
01dc7fec 3055 rtl_writephy(tp, 0x1f, 0x0000);
3056
3057 /* For impedance matching */
3058 rtl_writephy(tp, 0x1f, 0x0002);
76564428 3059 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3060 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3061
3062 /* PHY auto speed down */
3063 rtl_writephy(tp, 0x1f, 0x0007);
3064 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3065 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
01dc7fec 3066 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3067 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
01dc7fec 3068
3069 rtl_writephy(tp, 0x1f, 0x0005);
3070 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3071 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
01dc7fec 3072 rtl_writephy(tp, 0x1f, 0x0000);
3073
3074 rtl_writephy(tp, 0x1f, 0x0005);
3075 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3076 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
01dc7fec 3077 rtl_writephy(tp, 0x1f, 0x0007);
3078 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3079 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
01dc7fec 3080 rtl_writephy(tp, 0x1f, 0x0006);
3081 rtl_writephy(tp, 0x00, 0x5a00);
3082 rtl_writephy(tp, 0x1f, 0x0000);
3083 rtl_writephy(tp, 0x0d, 0x0007);
3084 rtl_writephy(tp, 0x0e, 0x003c);
3085 rtl_writephy(tp, 0x0d, 0x4007);
3086 rtl_writephy(tp, 0x0e, 0x0000);
3087 rtl_writephy(tp, 0x0d, 0x0000);
3088}
3089
9ecb9aab 3090static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3091{
3092 const u16 w[] = {
3093 addr[0] | (addr[1] << 8),
3094 addr[2] | (addr[3] << 8),
3095 addr[4] | (addr[5] << 8)
3096 };
3097 const struct exgmac_reg e[] = {
3098 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3099 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3100 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3101 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3102 };
3103
3104 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3105}
3106
70090424
HW		 3107static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3108{
3109 static const struct phy_reg phy_reg_init[] = {
3110 /* Enable Delay cap */
3111 { 0x1f, 0x0004 },
3112 { 0x1f, 0x0007 },
3113 { 0x1e, 0x00ac },
3114 { 0x18, 0x0006 },
3115 { 0x1f, 0x0002 },
3116 { 0x1f, 0x0000 },
3117 { 0x1f, 0x0000 },
3118
3119 /* Channel estimation fine tune */
3120 { 0x1f, 0x0003 },
3121 { 0x09, 0xa20f },
3122 { 0x1f, 0x0000 },
3123 { 0x1f, 0x0000 },
3124
3125 /* Green Setting */
3126 { 0x1f, 0x0005 },
3127 { 0x05, 0x8b5b },
3128 { 0x06, 0x9222 },
3129 { 0x05, 0x8b6d },
3130 { 0x06, 0x8000 },
3131 { 0x05, 0x8b76 },
3132 { 0x06, 0x8000 },
3133 { 0x1f, 0x0000 }
3134 };
3135
3136 rtl_apply_firmware(tp);
3137
3138 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3139
3140 /* For 4-corner performance improve */
3141 rtl_writephy(tp, 0x1f, 0x0005);
3142 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3143 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
70090424
HW		 3144 rtl_writephy(tp, 0x1f, 0x0000);
3145
3146 /* PHY auto speed down */
3147 rtl_writephy(tp, 0x1f, 0x0004);
3148 rtl_writephy(tp, 0x1f, 0x0007);
3149 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3150 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
70090424
HW		 3151 rtl_writephy(tp, 0x1f, 0x0002);
3152 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3153 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
70090424
HW		 3154
3155 /* improve 10M EEE waveform */
3156 rtl_writephy(tp, 0x1f, 0x0005);
3157 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3158 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
70090424
HW		 3159 rtl_writephy(tp, 0x1f, 0x0000);
3160
3161 /* Improve 2-pair detection performance */
3162 rtl_writephy(tp, 0x1f, 0x0005);
3163 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3164 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
70090424
HW		 3165 rtl_writephy(tp, 0x1f, 0x0000);
3166
3167 /* EEE setting */
1814d6a8 3168 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
70090424
HW		 3169 rtl_writephy(tp, 0x1f, 0x0005);
3170 rtl_writephy(tp, 0x05, 0x8b85);
1814d6a8 3171 rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
70090424
HW		 3172 rtl_writephy(tp, 0x1f, 0x0004);
3173 rtl_writephy(tp, 0x1f, 0x0007);
3174 rtl_writephy(tp, 0x1e, 0x0020);
1814d6a8 3175 rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
70090424
HW		 3176 rtl_writephy(tp, 0x1f, 0x0002);
3177 rtl_writephy(tp, 0x1f, 0x0000);
3178 rtl_writephy(tp, 0x0d, 0x0007);
3179 rtl_writephy(tp, 0x0e, 0x003c);
3180 rtl_writephy(tp, 0x0d, 0x4007);
1814d6a8 3181 rtl_writephy(tp, 0x0e, 0x0006);
70090424
HW		 3182 rtl_writephy(tp, 0x0d, 0x0000);
3183
3184 /* Green feature */
3185 rtl_writephy(tp, 0x1f, 0x0003);
1814d6a8
HK		 3186 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3187 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
70090424 3188 rtl_writephy(tp, 0x1f, 0x0000);
b399a394
HK		 3189 rtl_writephy(tp, 0x1f, 0x0005);
3190 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3191 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3192
9ecb9aab 3193 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3194 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3195}
3196
5f886e08
HW		 3197static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3198{
3199 /* For 4-corner performance improve */
3200 rtl_writephy(tp, 0x1f, 0x0005);
3201 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3202 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
5f886e08
HW		 3203 rtl_writephy(tp, 0x1f, 0x0000);
3204
3205 /* PHY auto speed down */
3206 rtl_writephy(tp, 0x1f, 0x0007);
3207 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3208 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
5f886e08 3209 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3210 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
5f886e08
HW		 3211
3212 /* Improve 10M EEE waveform */
3213 rtl_writephy(tp, 0x1f, 0x0005);
3214 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3215 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
5f886e08
HW		 3216 rtl_writephy(tp, 0x1f, 0x0000);
3217}
3218
c2218925
HW		 3219static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3220{
3221 static const struct phy_reg phy_reg_init[] = {
3222 /* Channel estimation fine tune */
3223 { 0x1f, 0x0003 },
3224 { 0x09, 0xa20f },
3225 { 0x1f, 0x0000 },
3226
3227 /* Modify green table for giga & fnet */
3228 { 0x1f, 0x0005 },
3229 { 0x05, 0x8b55 },
3230 { 0x06, 0x0000 },
3231 { 0x05, 0x8b5e },
3232 { 0x06, 0x0000 },
3233 { 0x05, 0x8b67 },
3234 { 0x06, 0x0000 },
3235 { 0x05, 0x8b70 },
3236 { 0x06, 0x0000 },
3237 { 0x1f, 0x0000 },
3238 { 0x1f, 0x0007 },
3239 { 0x1e, 0x0078 },
3240 { 0x17, 0x0000 },
3241 { 0x19, 0x00fb },
3242 { 0x1f, 0x0000 },
3243
3244 /* Modify green table for 10M */
3245 { 0x1f, 0x0005 },
3246 { 0x05, 0x8b79 },
3247 { 0x06, 0xaa00 },
3248 { 0x1f, 0x0000 },
3249
3250 /* Disable hiimpedance detection (RTCT) */
3251 { 0x1f, 0x0003 },
3252 { 0x01, 0x328a },
3253 { 0x1f, 0x0000 }
3254 };
3255
3256 rtl_apply_firmware(tp);
3257
3258 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3259
5f886e08 3260 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3261
3262 /* Improve 2-pair detection performance */
3263 rtl_writephy(tp, 0x1f, 0x0005);
3264 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3265 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
c2218925
HW		 3266 rtl_writephy(tp, 0x1f, 0x0000);
3267}
3268
3269static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3270{
3271 rtl_apply_firmware(tp);
3272
5f886e08 3273 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3274}
3275
b3d7b2f2
HW		 3276static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3277{
b3d7b2f2
HW		 3278 static const struct phy_reg phy_reg_init[] = {
3279 /* Channel estimation fine tune */
3280 { 0x1f, 0x0003 },
3281 { 0x09, 0xa20f },
3282 { 0x1f, 0x0000 },
3283
3284 /* Modify green table for giga & fnet */
3285 { 0x1f, 0x0005 },
3286 { 0x05, 0x8b55 },
3287 { 0x06, 0x0000 },
3288 { 0x05, 0x8b5e },
3289 { 0x06, 0x0000 },
3290 { 0x05, 0x8b67 },
3291 { 0x06, 0x0000 },
3292 { 0x05, 0x8b70 },
3293 { 0x06, 0x0000 },
3294 { 0x1f, 0x0000 },
3295 { 0x1f, 0x0007 },
3296 { 0x1e, 0x0078 },
3297 { 0x17, 0x0000 },
3298 { 0x19, 0x00aa },
3299 { 0x1f, 0x0000 },
3300
3301 /* Modify green table for 10M */
3302 { 0x1f, 0x0005 },
3303 { 0x05, 0x8b79 },
3304 { 0x06, 0xaa00 },
3305 { 0x1f, 0x0000 },
3306
3307 /* Disable hiimpedance detection (RTCT) */
3308 { 0x1f, 0x0003 },
3309 { 0x01, 0x328a },
3310 { 0x1f, 0x0000 }
3311 };
3312
3313
3314 rtl_apply_firmware(tp);
3315
3316 rtl8168f_hw_phy_config(tp);
3317
3318 /* Improve 2-pair detection performance */
3319 rtl_writephy(tp, 0x1f, 0x0005);
3320 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3321 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
b3d7b2f2
HW		 3322 rtl_writephy(tp, 0x1f, 0x0000);
3323
3324 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3325
3326 /* Modify green table for giga */
3327 rtl_writephy(tp, 0x1f, 0x0005);
3328 rtl_writephy(tp, 0x05, 0x8b54);
76564428 3329 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3330 rtl_writephy(tp, 0x05, 0x8b5d);
76564428 3331 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3332 rtl_writephy(tp, 0x05, 0x8a7c);
76564428 3333 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3334 rtl_writephy(tp, 0x05, 0x8a7f);
76564428 3335 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
b3d7b2f2 3336 rtl_writephy(tp, 0x05, 0x8a82);
76564428 3337 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3338 rtl_writephy(tp, 0x05, 0x8a85);
76564428 3339 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3340 rtl_writephy(tp, 0x05, 0x8a88);
76564428 3341 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2
HW		 3342 rtl_writephy(tp, 0x1f, 0x0000);
3343
3344 /* uc same-seed solution */
3345 rtl_writephy(tp, 0x1f, 0x0005);
3346 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3347 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
b3d7b2f2
HW		 3348 rtl_writephy(tp, 0x1f, 0x0000);
3349
3350 /* eee setting */
706123d0 3351 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3352 rtl_writephy(tp, 0x1f, 0x0005);
3353 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3354 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
b3d7b2f2
HW		 3355 rtl_writephy(tp, 0x1f, 0x0004);
3356 rtl_writephy(tp, 0x1f, 0x0007);
3357 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3358 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
b3d7b2f2
HW		 3359 rtl_writephy(tp, 0x1f, 0x0000);
3360 rtl_writephy(tp, 0x0d, 0x0007);
3361 rtl_writephy(tp, 0x0e, 0x003c);
3362 rtl_writephy(tp, 0x0d, 0x4007);
3363 rtl_writephy(tp, 0x0e, 0x0000);
3364 rtl_writephy(tp, 0x0d, 0x0000);
3365
3366 /* Green feature */
3367 rtl_writephy(tp, 0x1f, 0x0003);
76564428
CHL		 3368 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3369 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
b3d7b2f2
HW		 3370 rtl_writephy(tp, 0x1f, 0x0000);
3371}
3372
c558386b
HW		 3373static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3374{
c558386b
HW		 3375 rtl_apply_firmware(tp);
3376
41f44d13 3377 rtl_writephy(tp, 0x1f, 0x0a46);
3378 if (rtl_readphy(tp, 0x10) & 0x0100) {
3379 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3380 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
41f44d13 3381 } else {
3382 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3383 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
41f44d13 3384 }
c558386b 3385
41f44d13 3386 rtl_writephy(tp, 0x1f, 0x0a46);
3387 if (rtl_readphy(tp, 0x13) & 0x0100) {
3388 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3389 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
41f44d13 3390 } else {
fe7524c0 3391 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3392 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
41f44d13 3393 }
c558386b 3394
41f44d13 3395 /* Enable PHY auto speed down */
3396 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3397 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
c558386b 3398
fe7524c0 3399 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3400 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
fe7524c0 3401 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3402 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
fe7524c0 3403 rtl_writephy(tp, 0x1f, 0x0a43);
3404 rtl_writephy(tp, 0x13, 0x8084);
76564428
CHL		 3405 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3406 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
fe7524c0 3407
41f44d13 3408 /* EEE auto-fallback function */
3409 rtl_writephy(tp, 0x1f, 0x0a4b);
76564428 3410 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
c558386b 3411
41f44d13 3412 /* Enable UC LPF tune function */
3413 rtl_writephy(tp, 0x1f, 0x0a43);
3414 rtl_writephy(tp, 0x13, 0x8012);
76564428 3415 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
41f44d13 3416
3417 rtl_writephy(tp, 0x1f, 0x0c42);
76564428 3418 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
41f44d13 3419
fe7524c0 3420 /* Improve SWR Efficiency */
3421 rtl_writephy(tp, 0x1f, 0x0bcd);
3422 rtl_writephy(tp, 0x14, 0x5065);
3423 rtl_writephy(tp, 0x14, 0xd065);
3424 rtl_writephy(tp, 0x1f, 0x0bc8);
3425 rtl_writephy(tp, 0x11, 0x5655);
3426 rtl_writephy(tp, 0x1f, 0x0bcd);
3427 rtl_writephy(tp, 0x14, 0x1065);
3428 rtl_writephy(tp, 0x14, 0x9065);
3429 rtl_writephy(tp, 0x14, 0x1065);
3430
1bac1072
DC		 3431 /* Check ALDPS bit, disable it if enabled */
3432 rtl_writephy(tp, 0x1f, 0x0a43);
3433 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3434 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
1bac1072 3435
41f44d13 3436 rtl_writephy(tp, 0x1f, 0x0000);
c558386b
HW		 3437}
3438
57538c4a 3439static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3440{
3441 rtl_apply_firmware(tp);
3442}
3443
6e1d0b89
CHL		 3444static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3445{
3446 u16 dout_tapbin;
3447 u32 data;
3448
3449 rtl_apply_firmware(tp);
3450
3451 /* CHN EST parameters adjust - giga master */
3452 rtl_writephy(tp, 0x1f, 0x0a43);
3453 rtl_writephy(tp, 0x13, 0x809b);
76564428 3454 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
6e1d0b89 3455 rtl_writephy(tp, 0x13, 0x80a2);
76564428 3456 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
6e1d0b89 3457 rtl_writephy(tp, 0x13, 0x80a4);
76564428 3458 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
6e1d0b89 3459 rtl_writephy(tp, 0x13, 0x809c);
76564428 3460 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
6e1d0b89
CHL		 3461 rtl_writephy(tp, 0x1f, 0x0000);
3462
3463 /* CHN EST parameters adjust - giga slave */
3464 rtl_writephy(tp, 0x1f, 0x0a43);
3465 rtl_writephy(tp, 0x13, 0x80ad);
76564428 3466 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
6e1d0b89 3467 rtl_writephy(tp, 0x13, 0x80b4);
76564428 3468 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
6e1d0b89 3469 rtl_writephy(tp, 0x13, 0x80ac);
76564428 3470 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
6e1d0b89
CHL		 3471 rtl_writephy(tp, 0x1f, 0x0000);
3472
3473 /* CHN EST parameters adjust - fnet */
3474 rtl_writephy(tp, 0x1f, 0x0a43);
3475 rtl_writephy(tp, 0x13, 0x808e);
76564428 3476 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
6e1d0b89 3477 rtl_writephy(tp, 0x13, 0x8090);
76564428 3478 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
6e1d0b89 3479 rtl_writephy(tp, 0x13, 0x8092);
76564428 3480 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
6e1d0b89
CHL		 3481 rtl_writephy(tp, 0x1f, 0x0000);
3482
3483 /* enable R-tune & PGA-retune function */
3484 dout_tapbin = 0;
3485 rtl_writephy(tp, 0x1f, 0x0a46);
3486 data = rtl_readphy(tp, 0x13);
3487 data &= 3;
3488 data <<= 2;
3489 dout_tapbin |= data;
3490 data = rtl_readphy(tp, 0x12);
3491 data &= 0xc000;
3492 data >>= 14;
3493 dout_tapbin |= data;
3494 dout_tapbin = ~(dout_tapbin^0x08);
3495 dout_tapbin <<= 12;
3496 dout_tapbin &= 0xf000;
3497 rtl_writephy(tp, 0x1f, 0x0a43);
3498 rtl_writephy(tp, 0x13, 0x827a);
76564428 3499 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3500 rtl_writephy(tp, 0x13, 0x827b);
76564428 3501 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3502 rtl_writephy(tp, 0x13, 0x827c);
76564428 3503 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3504 rtl_writephy(tp, 0x13, 0x827d);
76564428 3505 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89
CHL		 3506
3507 rtl_writephy(tp, 0x1f, 0x0a43);
3508 rtl_writephy(tp, 0x13, 0x0811);
76564428 3509 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3510 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3511 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3512 rtl_writephy(tp, 0x1f, 0x0000);
3513
3514 /* enable GPHY 10M */
3515 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3516 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3517 rtl_writephy(tp, 0x1f, 0x0000);
3518
3519 /* SAR ADC performance */
3520 rtl_writephy(tp, 0x1f, 0x0bca);
76564428 3521 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
6e1d0b89
CHL		 3522 rtl_writephy(tp, 0x1f, 0x0000);
3523
3524 rtl_writephy(tp, 0x1f, 0x0a43);
3525 rtl_writephy(tp, 0x13, 0x803f);
76564428 3526 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3527 rtl_writephy(tp, 0x13, 0x8047);
76564428 3528 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3529 rtl_writephy(tp, 0x13, 0x804f);
76564428 3530 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3531 rtl_writephy(tp, 0x13, 0x8057);
76564428 3532 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3533 rtl_writephy(tp, 0x13, 0x805f);
76564428 3534 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3535 rtl_writephy(tp, 0x13, 0x8067);
76564428 3536 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3537 rtl_writephy(tp, 0x13, 0x806f);
76564428 3538 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89
CHL		 3539 rtl_writephy(tp, 0x1f, 0x0000);
3540
3541 /* disable phy pfm mode */
3542 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 3543 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 3544 rtl_writephy(tp, 0x1f, 0x0000);
3545
3546 /* Check ALDPS bit, disable it if enabled */
3547 rtl_writephy(tp, 0x1f, 0x0a43);
3548 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3549 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 3550
3551 rtl_writephy(tp, 0x1f, 0x0000);
3552}
3553
3554static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3555{
3556 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3557 u16 rlen;
3558 u32 data;
3559
3560 rtl_apply_firmware(tp);
3561
3562 /* CHIN EST parameter update */
3563 rtl_writephy(tp, 0x1f, 0x0a43);
3564 rtl_writephy(tp, 0x13, 0x808a);
76564428 3565 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
6e1d0b89
CHL		 3566 rtl_writephy(tp, 0x1f, 0x0000);
3567
3568 /* enable R-tune & PGA-retune function */
3569 rtl_writephy(tp, 0x1f, 0x0a43);
3570 rtl_writephy(tp, 0x13, 0x0811);
76564428 3571 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3572 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3573 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3574 rtl_writephy(tp, 0x1f, 0x0000);
3575
3576 /* enable GPHY 10M */
3577 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3578 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3579 rtl_writephy(tp, 0x1f, 0x0000);
3580
3581 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3582 data = r8168_mac_ocp_read(tp, 0xdd02);
3583 ioffset_p3 = ((data & 0x80)>>7);
3584 ioffset_p3 <<= 3;
3585
3586 data = r8168_mac_ocp_read(tp, 0xdd00);
3587 ioffset_p3 |= ((data & (0xe000))>>13);
3588 ioffset_p2 = ((data & (0x1e00))>>9);
3589 ioffset_p1 = ((data & (0x01e0))>>5);
3590 ioffset_p0 = ((data & 0x0010)>>4);
3591 ioffset_p0 <<= 3;
3592 ioffset_p0 |= (data & (0x07));
3593 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3594
05b9687b 3595 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
e2e2788e 3596 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
6e1d0b89
CHL		 3597 rtl_writephy(tp, 0x1f, 0x0bcf);
3598 rtl_writephy(tp, 0x16, data);
3599 rtl_writephy(tp, 0x1f, 0x0000);
3600 }
3601
3602 /* Modify rlen (TX LPF corner frequency) level */
3603 rtl_writephy(tp, 0x1f, 0x0bcd);
3604 data = rtl_readphy(tp, 0x16);
3605 data &= 0x000f;
3606 rlen = 0;
3607 if (data > 3)
3608 rlen = data - 3;
3609 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3610 rtl_writephy(tp, 0x17, data);
3611 rtl_writephy(tp, 0x1f, 0x0bcd);
3612 rtl_writephy(tp, 0x1f, 0x0000);
3613
3614 /* disable phy pfm mode */
3615 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 3616 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 3617 rtl_writephy(tp, 0x1f, 0x0000);
3618
3619 /* Check ALDPS bit, disable it if enabled */
3620 rtl_writephy(tp, 0x1f, 0x0a43);
3621 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3622 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 3623
3624 rtl_writephy(tp, 0x1f, 0x0000);
3625}
3626
935e2218
CHL		 3627static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3628{
3629 /* Enable PHY auto speed down */
3630 rtl_writephy(tp, 0x1f, 0x0a44);
3631 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3632 rtl_writephy(tp, 0x1f, 0x0000);
3633
3634 /* patch 10M & ALDPS */
3635 rtl_writephy(tp, 0x1f, 0x0bcc);
3636 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3637 rtl_writephy(tp, 0x1f, 0x0a44);
3638 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3639 rtl_writephy(tp, 0x1f, 0x0a43);
3640 rtl_writephy(tp, 0x13, 0x8084);
3641 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3642 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3643 rtl_writephy(tp, 0x1f, 0x0000);
3644
3645 /* Enable EEE auto-fallback function */
3646 rtl_writephy(tp, 0x1f, 0x0a4b);
3647 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3648 rtl_writephy(tp, 0x1f, 0x0000);
3649
3650 /* Enable UC LPF tune function */
3651 rtl_writephy(tp, 0x1f, 0x0a43);
3652 rtl_writephy(tp, 0x13, 0x8012);
3653 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3654 rtl_writephy(tp, 0x1f, 0x0000);
3655
3656 /* set rg_sel_sdm_rate */
3657 rtl_writephy(tp, 0x1f, 0x0c42);
3658 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3659 rtl_writephy(tp, 0x1f, 0x0000);
3660
3661 /* Check ALDPS bit, disable it if enabled */
3662 rtl_writephy(tp, 0x1f, 0x0a43);
3663 if (rtl_readphy(tp, 0x10) & 0x0004)
3664 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3665
3666 rtl_writephy(tp, 0x1f, 0x0000);
3667}
3668
3669static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3670{
3671 /* patch 10M & ALDPS */
3672 rtl_writephy(tp, 0x1f, 0x0bcc);
3673 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3674 rtl_writephy(tp, 0x1f, 0x0a44);
3675 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3676 rtl_writephy(tp, 0x1f, 0x0a43);
3677 rtl_writephy(tp, 0x13, 0x8084);
3678 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3679 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3680 rtl_writephy(tp, 0x1f, 0x0000);
3681
3682 /* Enable UC LPF tune function */
3683 rtl_writephy(tp, 0x1f, 0x0a43);
3684 rtl_writephy(tp, 0x13, 0x8012);
3685 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3686 rtl_writephy(tp, 0x1f, 0x0000);
3687
3688 /* Set rg_sel_sdm_rate */
3689 rtl_writephy(tp, 0x1f, 0x0c42);
3690 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3691 rtl_writephy(tp, 0x1f, 0x0000);
3692
3693 /* Channel estimation parameters */
3694 rtl_writephy(tp, 0x1f, 0x0a43);
3695 rtl_writephy(tp, 0x13, 0x80f3);
3696 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3697 rtl_writephy(tp, 0x13, 0x80f0);
3698 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3699 rtl_writephy(tp, 0x13, 0x80ef);
3700 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3701 rtl_writephy(tp, 0x13, 0x80f6);
3702 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3703 rtl_writephy(tp, 0x13, 0x80ec);
3704 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3705 rtl_writephy(tp, 0x13, 0x80ed);
3706 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3707 rtl_writephy(tp, 0x13, 0x80f2);
3708 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3709 rtl_writephy(tp, 0x13, 0x80f4);
3710 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3711 rtl_writephy(tp, 0x1f, 0x0a43);
3712 rtl_writephy(tp, 0x13, 0x8110);
3713 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3714 rtl_writephy(tp, 0x13, 0x810f);
3715 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3716 rtl_writephy(tp, 0x13, 0x8111);
3717 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3718 rtl_writephy(tp, 0x13, 0x8113);
3719 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3720 rtl_writephy(tp, 0x13, 0x8115);
3721 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3722 rtl_writephy(tp, 0x13, 0x810e);
3723 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3724 rtl_writephy(tp, 0x13, 0x810c);
3725 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3726 rtl_writephy(tp, 0x13, 0x810b);
3727 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3728 rtl_writephy(tp, 0x1f, 0x0a43);
3729 rtl_writephy(tp, 0x13, 0x80d1);
3730 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3731 rtl_writephy(tp, 0x13, 0x80cd);
3732 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3733 rtl_writephy(tp, 0x13, 0x80d3);
3734 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3735 rtl_writephy(tp, 0x13, 0x80d5);
3736 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3737 rtl_writephy(tp, 0x13, 0x80d7);
3738 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3739
3740 /* Force PWM-mode */
3741 rtl_writephy(tp, 0x1f, 0x0bcd);
3742 rtl_writephy(tp, 0x14, 0x5065);
3743 rtl_writephy(tp, 0x14, 0xd065);
3744 rtl_writephy(tp, 0x1f, 0x0bc8);
3745 rtl_writephy(tp, 0x12, 0x00ed);
3746 rtl_writephy(tp, 0x1f, 0x0bcd);
3747 rtl_writephy(tp, 0x14, 0x1065);
3748 rtl_writephy(tp, 0x14, 0x9065);
3749 rtl_writephy(tp, 0x14, 0x1065);
3750 rtl_writephy(tp, 0x1f, 0x0000);
3751
3752 /* Check ALDPS bit, disable it if enabled */
3753 rtl_writephy(tp, 0x1f, 0x0a43);
3754 if (rtl_readphy(tp, 0x10) & 0x0004)
3755 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3756
3757 rtl_writephy(tp, 0x1f, 0x0000);
3758}
3759
4da19633 3760static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3761{
350f7596 3762 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3763 { 0x1f, 0x0003 },
3764 { 0x08, 0x441d },
3765 { 0x01, 0x9100 },
3766 { 0x1f, 0x0000 }
3767 };
3768
4da19633 3769 rtl_writephy(tp, 0x1f, 0x0000);
3770 rtl_patchphy(tp, 0x11, 1 << 12);
3771 rtl_patchphy(tp, 0x19, 1 << 13);
3772 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3773
4da19633 3774 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 3775}
3776
5a5e4443
HW		 3777static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3778{
3779 static const struct phy_reg phy_reg_init[] = {
3780 { 0x1f, 0x0005 },
3781 { 0x1a, 0x0000 },
3782 { 0x1f, 0x0000 },
3783
3784 { 0x1f, 0x0004 },
3785 { 0x1c, 0x0000 },
3786 { 0x1f, 0x0000 },
3787
3788 { 0x1f, 0x0001 },
3789 { 0x15, 0x7701 },
3790 { 0x1f, 0x0000 }
3791 };
3792
3793 /* Disable ALDPS before ram code */
eef63cc1
FR		 3794 rtl_writephy(tp, 0x1f, 0x0000);
3795 rtl_writephy(tp, 0x18, 0x0310);
3796 msleep(100);
5a5e4443 3797
953a12cc 3798 rtl_apply_firmware(tp);
5a5e4443
HW		 3799
3800 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3801}
3802
7e18dca1
HW		 3803static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3804{
7e18dca1 3805 /* Disable ALDPS before setting firmware */
eef63cc1
FR		 3806 rtl_writephy(tp, 0x1f, 0x0000);
3807 rtl_writephy(tp, 0x18, 0x0310);
3808 msleep(20);
7e18dca1
HW		 3809
3810 rtl_apply_firmware(tp);
3811
3812 /* EEE setting */
fdf6fc06 3813 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 3814 rtl_writephy(tp, 0x1f, 0x0004);
3815 rtl_writephy(tp, 0x10, 0x401f);
3816 rtl_writephy(tp, 0x19, 0x7030);
3817 rtl_writephy(tp, 0x1f, 0x0000);
3818}
3819
5598bfe5
HW		 3820static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3821{
5598bfe5
HW		 3822 static const struct phy_reg phy_reg_init[] = {
3823 { 0x1f, 0x0004 },
3824 { 0x10, 0xc07f },
3825 { 0x19, 0x7030 },
3826 { 0x1f, 0x0000 }
3827 };
3828
3829 /* Disable ALDPS before ram code */
eef63cc1
FR		 3830 rtl_writephy(tp, 0x1f, 0x0000);
3831 rtl_writephy(tp, 0x18, 0x0310);
3832 msleep(100);
5598bfe5
HW		 3833
3834 rtl_apply_firmware(tp);
3835
fdf6fc06 3836 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3837 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3838
fdf6fc06 3839 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3840}
3841
5615d9f1
FR		 3842static void rtl_hw_phy_config(struct net_device *dev)
3843{
3844 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1 3845
5615d9f1
FR		 3846 switch (tp->mac_version) {
3847 case RTL_GIGA_MAC_VER_01:
3848 break;
3849 case RTL_GIGA_MAC_VER_02:
3850 case RTL_GIGA_MAC_VER_03:
4da19633 3851 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 3852 break;
3853 case RTL_GIGA_MAC_VER_04:
4da19633 3854 rtl8169sb_hw_phy_config(tp);
5615d9f1 3855 break;
2e955856 3856 case RTL_GIGA_MAC_VER_05:
4da19633 3857 rtl8169scd_hw_phy_config(tp);
2e955856 3858 break;
8c7006aa 3859 case RTL_GIGA_MAC_VER_06:
4da19633 3860 rtl8169sce_hw_phy_config(tp);
8c7006aa 3861 break;
2857ffb7
FR		 3862 case RTL_GIGA_MAC_VER_07:
3863 case RTL_GIGA_MAC_VER_08:
3864 case RTL_GIGA_MAC_VER_09:
4da19633 3865 rtl8102e_hw_phy_config(tp);
2857ffb7 3866 break;
236b8082 3867 case RTL_GIGA_MAC_VER_11:
4da19633 3868 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 3869 break;
3870 case RTL_GIGA_MAC_VER_12:
4da19633 3871 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 3872 break;
3873 case RTL_GIGA_MAC_VER_17:
4da19633 3874 rtl8168bef_hw_phy_config(tp);
236b8082 3875 break;
867763c1 3876 case RTL_GIGA_MAC_VER_18:
4da19633 3877 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 3878 break;
3879 case RTL_GIGA_MAC_VER_19:
4da19633 3880 rtl8168c_1_hw_phy_config(tp);
867763c1 3881 break;
7da97ec9 3882 case RTL_GIGA_MAC_VER_20:
4da19633 3883 rtl8168c_2_hw_phy_config(tp);
7da97ec9 3884 break;
197ff761 3885 case RTL_GIGA_MAC_VER_21:
4da19633 3886 rtl8168c_3_hw_phy_config(tp);
197ff761 3887 break;
6fb07058 3888 case RTL_GIGA_MAC_VER_22:
4da19633 3889 rtl8168c_4_hw_phy_config(tp);
6fb07058 3890 break;
ef3386f0 3891 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 3892 case RTL_GIGA_MAC_VER_24:
4da19633 3893 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 3894 break;
5b538df9 3895 case RTL_GIGA_MAC_VER_25:
bca03d5f 3896 rtl8168d_1_hw_phy_config(tp);
daf9df6d 3897 break;
3898 case RTL_GIGA_MAC_VER_26:
bca03d5f 3899 rtl8168d_2_hw_phy_config(tp);
daf9df6d 3900 break;
3901 case RTL_GIGA_MAC_VER_27:
4da19633 3902 rtl8168d_3_hw_phy_config(tp);
5b538df9 3903 break;
e6de30d6 3904 case RTL_GIGA_MAC_VER_28:
3905 rtl8168d_4_hw_phy_config(tp);
3906 break;
5a5e4443
HW		 3907 case RTL_GIGA_MAC_VER_29:
3908 case RTL_GIGA_MAC_VER_30:
3909 rtl8105e_hw_phy_config(tp);
3910 break;
cecb5fd7
FR		 3911 case RTL_GIGA_MAC_VER_31:
3912 /* None. */
3913 break;
01dc7fec 3914 case RTL_GIGA_MAC_VER_32:
01dc7fec 3915 case RTL_GIGA_MAC_VER_33:
70090424
HW		 3916 rtl8168e_1_hw_phy_config(tp);
3917 break;
3918 case RTL_GIGA_MAC_VER_34:
3919 rtl8168e_2_hw_phy_config(tp);
01dc7fec 3920 break;
c2218925
HW		 3921 case RTL_GIGA_MAC_VER_35:
3922 rtl8168f_1_hw_phy_config(tp);
3923 break;
3924 case RTL_GIGA_MAC_VER_36:
3925 rtl8168f_2_hw_phy_config(tp);
3926 break;
ef3386f0 3927
7e18dca1
HW		 3928 case RTL_GIGA_MAC_VER_37:
3929 rtl8402_hw_phy_config(tp);
3930 break;
3931
b3d7b2f2
HW		 3932 case RTL_GIGA_MAC_VER_38:
3933 rtl8411_hw_phy_config(tp);
3934 break;
3935
5598bfe5
HW		 3936 case RTL_GIGA_MAC_VER_39:
3937 rtl8106e_hw_phy_config(tp);
3938 break;
3939
c558386b
HW		 3940 case RTL_GIGA_MAC_VER_40:
3941 rtl8168g_1_hw_phy_config(tp);
3942 break;
57538c4a 3943 case RTL_GIGA_MAC_VER_42:
58152cd4 3944 case RTL_GIGA_MAC_VER_43:
45dd95c4 3945 case RTL_GIGA_MAC_VER_44:
57538c4a 3946 rtl8168g_2_hw_phy_config(tp);
3947 break;
6e1d0b89
CHL		 3948 case RTL_GIGA_MAC_VER_45:
3949 case RTL_GIGA_MAC_VER_47:
3950 rtl8168h_1_hw_phy_config(tp);
3951 break;
3952 case RTL_GIGA_MAC_VER_46:
3953 case RTL_GIGA_MAC_VER_48:
3954 rtl8168h_2_hw_phy_config(tp);
3955 break;
c558386b 3956
935e2218
CHL		 3957 case RTL_GIGA_MAC_VER_49:
3958 rtl8168ep_1_hw_phy_config(tp);
3959 break;
3960 case RTL_GIGA_MAC_VER_50:
3961 case RTL_GIGA_MAC_VER_51:
3962 rtl8168ep_2_hw_phy_config(tp);
3963 break;
3964
c558386b 3965 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 3966 default:
3967 break;
3968 }
3969}
3970
da78dbff
FR		 3971static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3972{
da78dbff
FR		 3973 if (!test_and_set_bit(flag, tp->wk.flags))
3974 schedule_work(&tp->wk.work);
da78dbff
FR		 3975}
3976
2544bfc0
FR		 3977static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3978{
2544bfc0 3979 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
e397286b 3980 (RTL_R8(tp, PHYstatus) & TBI_Enable);
2544bfc0
FR		 3981}
3982
4ff96fa6
FR		 3983static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3984{
5615d9f1 3985 rtl_hw_phy_config(dev);
4ff96fa6 3986
77332894 3987 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
7a67e11d
HK		 3988 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3989 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
49d17512
HK		 3990 netif_dbg(tp, drv, dev,
3991 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1ef7286e 3992 RTL_W8(tp, 0x82, 0x01);
77332894 3993 }
4ff96fa6 3994
5b7ad4b7
HK		 3995 /* We may have called phy_speed_down before */
3996 phy_speed_up(dev->phydev);
3997
f75222bc 3998 genphy_soft_reset(dev->phydev);
10bc6a60 3999
9003b369 4000 /* It was reported that several chips end up with 10MBit/Half on a
10bc6a60 4001 * 1GBit link after resuming from S3. For whatever reason the PHY on
9003b369 4002 * these chips doesn't properly start a renegotiation when soft-reset.
10bc6a60
HK		 4003 * Explicitly requesting a renegotiation fixes this.
4004 */
9003b369 4005 if (dev->phydev->autoneg == AUTONEG_ENABLE)
10bc6a60 4006 phy_restart_aneg(dev->phydev);
4ff96fa6
FR		 4007}
4008
773d2021
FR		 4009static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4010{
da78dbff 4011 rtl_lock_work(tp);
773d2021 4012
1ef7286e 4013 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
908ba2bf 4014
1ef7286e
AS		 4015 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4016 RTL_R32(tp, MAC4);
908ba2bf 4017
1ef7286e
AS		 4018 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4019 RTL_R32(tp, MAC0);
908ba2bf 4020
9ecb9aab 4021 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4022 rtl_rar_exgmac_set(tp, addr);
c28aa385 4023
1ef7286e 4024 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
773d2021 4025
da78dbff 4026 rtl_unlock_work(tp);
773d2021
FR		 4027}
4028
4029static int rtl_set_mac_address(struct net_device *dev, void *p)
4030{
4031 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 4032 struct device *d = tp_to_dev(tp);
1f7aa2bc 4033 int ret;
773d2021 4034
1f7aa2bc
HK		 4035 ret = eth_mac_addr(dev, p);
4036 if (ret)
4037 return ret;
773d2021 4038
f51d4a10
CHL		 4039 pm_runtime_get_noresume(d);
4040
4041 if (pm_runtime_active(d))
4042 rtl_rar_set(tp, dev->dev_addr);
4043
4044 pm_runtime_put_noidle(d);
773d2021
FR		 4045
4046 return 0;
4047}
4048
e397286b 4049static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8b4ab28d 4050{
69b3c59f
HK		 4051 if (!netif_running(dev))
4052 return -ENODEV;
e397286b 4053
69b3c59f 4054 return phy_mii_ioctl(dev->phydev, ifr, cmd);
8b4ab28d
FR		 4055}
4056
baf63293 4057static void rtl_init_mdio_ops(struct rtl8169_private *tp)
c0e45c1c 4058{
4059 struct mdio_ops *ops = &tp->mdio_ops;
4060
4061 switch (tp->mac_version) {
4062 case RTL_GIGA_MAC_VER_27:
4063 ops->write = r8168dp_1_mdio_write;
4064 ops->read = r8168dp_1_mdio_read;
4065 break;
e6de30d6 4066 case RTL_GIGA_MAC_VER_28:
4804b3b3 4067 case RTL_GIGA_MAC_VER_31:
e6de30d6 4068 ops->write = r8168dp_2_mdio_write;
4069 ops->read = r8168dp_2_mdio_read;
4070 break;
2a71883c 4071 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
c558386b
HW		 4072 ops->write = r8168g_mdio_write;
4073 ops->read = r8168g_mdio_read;
4074 break;
c0e45c1c 4075 default:
4076 ops->write = r8169_mdio_write;
4077 ops->read = r8169_mdio_read;
4078 break;
4079 }
4080}
4081
649b3b8c 4082static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4083{
649b3b8c 4084 switch (tp->mac_version) {
b00e69de
CB		 4085 case RTL_GIGA_MAC_VER_25:
4086 case RTL_GIGA_MAC_VER_26:
649b3b8c 4087 case RTL_GIGA_MAC_VER_29:
4088 case RTL_GIGA_MAC_VER_30:
4089 case RTL_GIGA_MAC_VER_32:
4090 case RTL_GIGA_MAC_VER_33:
4091 case RTL_GIGA_MAC_VER_34:
2a71883c 4092 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
1ef7286e 4093 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
649b3b8c 4094 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4095 break;
4096 default:
4097 break;
4098 }
4099}
4100
4101static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4102{
649f0837
HK		 4103 struct phy_device *phydev;
4104
4105 if (!__rtl8169_get_wol(tp))
649b3b8c 4106 return false;
4107
649f0837
HK		 4108 /* phydev may not be attached to netdevice */
4109 phydev = mdiobus_get_phy(tp->mii_bus, 0);
4110
4111 phy_speed_down(phydev, false);
649b3b8c 4112 rtl_wol_suspend_quirk(tp);
4113
4114 return true;
4115}
4116
065c27c1 4117static void r8168_pll_power_down(struct rtl8169_private *tp)
4118{
9dbe7896 4119 if (r8168_check_dash(tp))
065c27c1 4120 return;
4121
01dc7fec 4122 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4123 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4124 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4125
649b3b8c 4126 if (rtl_wol_pll_power_down(tp))
065c27c1 4127 return;
065c27c1 4128
065c27c1 4129 switch (tp->mac_version) {
2a71883c 4130 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
73570bf1
HK		 4131 case RTL_GIGA_MAC_VER_37:
4132 case RTL_GIGA_MAC_VER_39:
4133 case RTL_GIGA_MAC_VER_43:
42fde737 4134 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4135 case RTL_GIGA_MAC_VER_45:
4136 case RTL_GIGA_MAC_VER_46:
73570bf1
HK		 4137 case RTL_GIGA_MAC_VER_47:
4138 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4139 case RTL_GIGA_MAC_VER_50:
4140 case RTL_GIGA_MAC_VER_51:
1ef7286e 4141 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
065c27c1 4142 break;
beb330a4 4143 case RTL_GIGA_MAC_VER_40:
4144 case RTL_GIGA_MAC_VER_41:
935e2218 4145 case RTL_GIGA_MAC_VER_49:
706123d0 4146 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
beb330a4 4147 0xfc000000, ERIAR_EXGMAC);
1ef7286e 4148 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
beb330a4 4149 break;
065c27c1 4150 }
4151}
4152
4153static void r8168_pll_power_up(struct rtl8169_private *tp)
4154{
065c27c1 4155 switch (tp->mac_version) {
2a71883c 4156 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
73570bf1
HK		 4157 case RTL_GIGA_MAC_VER_37:
4158 case RTL_GIGA_MAC_VER_39:
4159 case RTL_GIGA_MAC_VER_43:
1ef7286e 4160 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
065c27c1 4161 break;
42fde737 4162 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4163 case RTL_GIGA_MAC_VER_45:
4164 case RTL_GIGA_MAC_VER_46:
73570bf1
HK		 4165 case RTL_GIGA_MAC_VER_47:
4166 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4167 case RTL_GIGA_MAC_VER_50:
4168 case RTL_GIGA_MAC_VER_51:
1ef7286e 4169 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
6e1d0b89 4170 break;
beb330a4 4171 case RTL_GIGA_MAC_VER_40:
4172 case RTL_GIGA_MAC_VER_41:
935e2218 4173 case RTL_GIGA_MAC_VER_49:
1ef7286e 4174 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
706123d0 4175 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
beb330a4 4176 0x00000000, ERIAR_EXGMAC);
4177 break;
065c27c1 4178 }
4179
242cd9b5
HK		 4180 phy_resume(tp->dev->phydev);
4181 /* give MAC/PHY some time to resume */
4182 msleep(20);
065c27c1 4183}
4184
065c27c1 4185static void rtl_pll_power_down(struct rtl8169_private *tp)
4186{
4f447d29
HK		 4187 switch (tp->mac_version) {
4188 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4189 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4190 break;
4191 default:
4192 r8168_pll_power_down(tp);
4193 }
065c27c1 4194}
4195
4196static void rtl_pll_power_up(struct rtl8169_private *tp)
4197{
065c27c1 4198 switch (tp->mac_version) {
4f447d29
HK		 4199 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4200 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
065c27c1 4201 break;
065c27c1 4202 default:
4f447d29 4203 r8168_pll_power_up(tp);
065c27c1 4204 }
4205}
4206
e542a226
HW		 4207static void rtl_init_rxcfg(struct rtl8169_private *tp)
4208{
e542a226 4209 switch (tp->mac_version) {
2a71883c
HK		 4210 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4211 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
1ef7286e 4212 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
e542a226 4213 break;
2a71883c 4214 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
511cfd58
MS		 4215 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4216 case RTL_GIGA_MAC_VER_38:
1ef7286e 4217 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
e542a226 4218 break;
2a71883c 4219 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1ef7286e 4220 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
beb330a4 4221 break;
e542a226 4222 default:
1ef7286e 4223 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
e542a226
HW		 4224 break;
4225 }
4226}
4227
92fc43b4
HW		 4228static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4229{
9fba0812 4230 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 4231}
4232
d58d46b5
FR		 4233static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4234{
eda40b8c
HK		 4235 if (tp->jumbo_ops.enable) {
4236 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4237 tp->jumbo_ops.enable(tp);
4238 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4239 }
d58d46b5
FR		 4240}
4241
4242static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4243{
eda40b8c
HK		 4244 if (tp->jumbo_ops.disable) {
4245 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4246 tp->jumbo_ops.disable(tp);
4247 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4248 }
d58d46b5
FR		 4249}
4250
4251static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4252{
1ef7286e
AS		 4253 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4254 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
cb73200c 4255 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 4256}
4257
4258static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4259{
1ef7286e
AS		 4260 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4261 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
8d98aa39 4262 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
d58d46b5
FR		 4263}
4264
4265static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4266{
1ef7286e 4267 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
d58d46b5
FR		 4268}
4269
4270static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4271{
1ef7286e 4272 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
d58d46b5
FR		 4273}
4274
4275static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4276{
1ef7286e
AS		 4277 RTL_W8(tp, MaxTxPacketSize, 0x3f);
4278 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4279 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
cb73200c 4280 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 4281}
4282
4283static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4284{
1ef7286e
AS		 4285 RTL_W8(tp, MaxTxPacketSize, 0x0c);
4286 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4287 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
8d98aa39 4288 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
d58d46b5
FR		 4289}
4290
4291static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4292{
cb73200c 4293 rtl_tx_performance_tweak(tp,
f65d539c 4294 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 4295}
4296
4297static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4298{
cb73200c 4299 rtl_tx_performance_tweak(tp,
8d98aa39 4300 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 4301}
4302
4303static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4304{
d58d46b5
FR		 4305 r8168b_0_hw_jumbo_enable(tp);
4306
1ef7286e 4307 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
d58d46b5
FR		 4308}
4309
4310static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4311{
d58d46b5
FR		 4312 r8168b_0_hw_jumbo_disable(tp);
4313
1ef7286e 4314 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
d58d46b5
FR		 4315}
4316
baf63293 4317static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
d58d46b5
FR		 4318{
4319 struct jumbo_ops *ops = &tp->jumbo_ops;
4320
4321 switch (tp->mac_version) {
4322 case RTL_GIGA_MAC_VER_11:
4323 ops->disable = r8168b_0_hw_jumbo_disable;
4324 ops->enable = r8168b_0_hw_jumbo_enable;
4325 break;
4326 case RTL_GIGA_MAC_VER_12:
4327 case RTL_GIGA_MAC_VER_17:
4328 ops->disable = r8168b_1_hw_jumbo_disable;
4329 ops->enable = r8168b_1_hw_jumbo_enable;
4330 break;
4331 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4332 case RTL_GIGA_MAC_VER_19:
4333 case RTL_GIGA_MAC_VER_20:
4334 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4335 case RTL_GIGA_MAC_VER_22:
4336 case RTL_GIGA_MAC_VER_23:
4337 case RTL_GIGA_MAC_VER_24:
4338 case RTL_GIGA_MAC_VER_25:
4339 case RTL_GIGA_MAC_VER_26:
4340 ops->disable = r8168c_hw_jumbo_disable;
4341 ops->enable = r8168c_hw_jumbo_enable;
4342 break;
4343 case RTL_GIGA_MAC_VER_27:
4344 case RTL_GIGA_MAC_VER_28:
4345 ops->disable = r8168dp_hw_jumbo_disable;
4346 ops->enable = r8168dp_hw_jumbo_enable;
4347 break;
4348 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4349 case RTL_GIGA_MAC_VER_32:
4350 case RTL_GIGA_MAC_VER_33:
4351 case RTL_GIGA_MAC_VER_34:
4352 ops->disable = r8168e_hw_jumbo_disable;
4353 ops->enable = r8168e_hw_jumbo_enable;
4354 break;
4355
4356 /*
4357 * No action needed for jumbo frames with 8169.
4358 * No jumbo for 810x at all.
4359 */
2a71883c 4360 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
d58d46b5
FR		 4361 default:
4362 ops->disable = NULL;
4363 ops->enable = NULL;
4364 break;
4365 }
4366}
4367
ffc46952
FR		 4368DECLARE_RTL_COND(rtl_chipcmd_cond)
4369{
1ef7286e 4370 return RTL_R8(tp, ChipCmd) & CmdReset;
ffc46952
FR		 4371}
4372
6f43adc8
FR		 4373static void rtl_hw_reset(struct rtl8169_private *tp)
4374{
1ef7286e 4375 RTL_W8(tp, ChipCmd, CmdReset);
6f43adc8 4376
ffc46952 4377 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 4378}
4379
b6ffd97f 4380static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4381{
b6ffd97f
FR		 4382 struct rtl_fw *rtl_fw;
4383 const char *name;
4384 int rc = -ENOMEM;
953a12cc 4385
b6ffd97f
FR		 4386 name = rtl_lookup_firmware_name(tp);
4387 if (!name)
4388 goto out_no_firmware;
953a12cc 4389
b6ffd97f
FR		 4390 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4391 if (!rtl_fw)
4392 goto err_warn;
31bd204f 4393
1e1205b7 4394 rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
b6ffd97f
FR		 4395 if (rc < 0)
4396 goto err_free;
4397
fd112f2e
FR		 4398 rc = rtl_check_firmware(tp, rtl_fw);
4399 if (rc < 0)
4400 goto err_release_firmware;
4401
b6ffd97f
FR		 4402 tp->rtl_fw = rtl_fw;
4403out:
4404 return;
4405
fd112f2e
FR		 4406err_release_firmware:
4407 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4408err_free:
4409 kfree(rtl_fw);
4410err_warn:
4411 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4412 name, rc);
4413out_no_firmware:
4414 tp->rtl_fw = NULL;
4415 goto out;
4416}
4417
4418static void rtl_request_firmware(struct rtl8169_private *tp)
4419{
4420 if (IS_ERR(tp->rtl_fw))
4421 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4422}
4423
92fc43b4
HW		 4424static void rtl_rx_close(struct rtl8169_private *tp)
4425{
1ef7286e 4426 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4427}
4428
ffc46952
FR		 4429DECLARE_RTL_COND(rtl_npq_cond)
4430{
1ef7286e 4431 return RTL_R8(tp, TxPoll) & NPQ;
ffc46952
FR		 4432}
4433
4434DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4435{
1ef7286e 4436 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
ffc46952
FR		 4437}
4438
e6de30d6 4439static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4
LT		 4440{
4441 /* Disable interrupts */
811fd301 4442 rtl8169_irq_mask_and_ack(tp);
1da177e4 4443
92fc43b4
HW		 4444 rtl_rx_close(tp);
4445
b2d43e6e
HK		 4446 switch (tp->mac_version) {
4447 case RTL_GIGA_MAC_VER_27:
4448 case RTL_GIGA_MAC_VER_28:
4449 case RTL_GIGA_MAC_VER_31:
ffc46952 4450 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
b2d43e6e
HK		 4451 break;
4452 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4453 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1ef7286e 4454 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
ffc46952 4455 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
b2d43e6e
HK		 4456 break;
4457 default:
1ef7286e 4458 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
92fc43b4 4459 udelay(100);
b2d43e6e 4460 break;
e6de30d6 4461 }
4462
92fc43b4 4463 rtl_hw_reset(tp);
1da177e4
LT		 4464}
4465
05212ba8 4466static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
9cb427b6 4467{
ad5f97fa
HK		 4468 u32 val = TX_DMA_BURST << TxDMAShift |
4469 InterFrameGap << TxInterFrameGapShift;
4470
4471 if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4472 tp->mac_version != RTL_GIGA_MAC_VER_39)
4473 val |= TXCFG_AUTO_FIFO;
4474
4475 RTL_W32(tp, TxConfig, val);
9cb427b6
FR		 4476}
4477
4fd48c4a 4478static void rtl_set_rx_max_size(struct rtl8169_private *tp)
1da177e4 4479{
4fd48c4a
HK		 4480 /* Low hurts. Let's disable the filtering. */
4481 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
07ce4064
FR		 4482}
4483
1ef7286e 4484static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
7f796d83
FR		 4485{
4486 /*
4487 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4488 * register to be written before TxDescAddrLow to work.
4489 * Switching from MMIO to I/O access fixes the issue as well.
4490 */
1ef7286e
AS		 4491 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4492 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4493 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4494 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4495}
4496
1ef7286e 4497static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
6dccd16b 4498{
34bc0095
HK		 4499 u32 val;
4500
4501 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4502 val = 0x000fff00;
4503 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4504 val = 0x00ffff00;
4505 else
4506 return;
4507
4508 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4509 val |= 0xff;
4510
4511 RTL_W32(tp, 0x7c, val);
6dccd16b
FR		 4512}
4513
e6b763ea
FR		 4514static void rtl_set_rx_mode(struct net_device *dev)
4515{
4516 struct rtl8169_private *tp = netdev_priv(dev);
e6b763ea
FR		 4517 u32 mc_filter[2]; /* Multicast hash filter */
4518 int rx_mode;
4519 u32 tmp = 0;
4520
4521 if (dev->flags & IFF_PROMISC) {
4522 /* Unconditionally log net taps. */
4523 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4524 rx_mode =
4525 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4526 AcceptAllPhys;
4527 mc_filter[1] = mc_filter[0] = 0xffffffff;
4528 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4529 (dev->flags & IFF_ALLMULTI)) {
4530 /* Too many to filter perfectly -- accept all multicasts. */
4531 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4532 mc_filter[1] = mc_filter[0] = 0xffffffff;
4533 } else {
4534 struct netdev_hw_addr *ha;
4535
4536 rx_mode = AcceptBroadcast | AcceptMyPhys;
4537 mc_filter[1] = mc_filter[0] = 0;
4538 netdev_for_each_mc_addr(ha, dev) {
4539 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4540 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4541 rx_mode |= AcceptMulticast;
4542 }
4543 }
4544
4545 if (dev->features & NETIF_F_RXALL)
4546 rx_mode |= (AcceptErr | AcceptRunt);
4547
1ef7286e 4548 tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
e6b763ea
FR		 4549
4550 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4551 u32 data = mc_filter[0];
4552
4553 mc_filter[0] = swab32(mc_filter[1]);
4554 mc_filter[1] = swab32(data);
4555 }
4556
0481776b
NW		 4557 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4558 mc_filter[1] = mc_filter[0] = 0xffffffff;
4559
1ef7286e
AS		 4560 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4561 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
e6b763ea 4562
1ef7286e 4563 RTL_W32(tp, RxConfig, tmp);
e6b763ea
FR		 4564}
4565
52f8560e
HK		 4566static void rtl_hw_start(struct rtl8169_private *tp)
4567{
4568 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4569
4570 tp->hw_start(tp);
4571
4572 rtl_set_rx_max_size(tp);
4573 rtl_set_rx_tx_desc_registers(tp);
52f8560e
HK		 4574 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4575
4576 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4577 RTL_R8(tp, IntrMask);
4578 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
05212ba8 4579 rtl_init_rxcfg(tp);
f74dd480 4580 rtl_set_tx_config_registers(tp);
05212ba8 4581
52f8560e
HK		 4582 rtl_set_rx_mode(tp->dev);
4583 /* no early-rx interrupts */
4584 RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
fe716f8a 4585 rtl_irq_enable(tp);
52f8560e
HK		 4586}
4587
61cb532d 4588static void rtl_hw_start_8169(struct rtl8169_private *tp)
07ce4064 4589{
0ae0974e 4590 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
61cb532d 4591 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
9cb427b6 4592
1ef7286e 4593 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
1da177e4 4594
0ae0974e 4595 tp->cp_cmd |= PCIMulRW;
1da177e4 4596
cecb5fd7
FR		 4597 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4598 tp->mac_version == RTL_GIGA_MAC_VER_03) {
49d17512
HK		 4599 netif_dbg(tp, drv, tp->dev,
4600 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
bcf0bf90 4601 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4602 }
4603
1ef7286e 4604 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
bcf0bf90 4605
1ef7286e 4606 rtl8169_set_magic_reg(tp, tp->mac_version);
6dccd16b 4607
1da177e4
LT		 4608 /*
4609 * Undocumented corner. Supposedly:
4610 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4611 */
1ef7286e 4612 RTL_W16(tp, IntrMitigate, 0x0000);
1da177e4 4613
1ef7286e 4614 RTL_W32(tp, RxMissed, 0);
07ce4064 4615}
1da177e4 4616
ffc46952
FR		 4617DECLARE_RTL_COND(rtl_csiar_cond)
4618{
1ef7286e 4619 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
ffc46952
FR		 4620}
4621
ff1d7331 4622static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
beb1fe18 4623{
ff1d7331 4624 u32 func = PCI_FUNC(tp->pci_dev->devfn);
beb1fe18 4625
1ef7286e
AS		 4626 RTL_W32(tp, CSIDR, value);
4627 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
ff1d7331 4628 CSIAR_BYTE_ENABLE | func << 16);
7e18dca1 4629
ffc46952 4630 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 4631}
4632
ff1d7331 4633static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 4634{
ff1d7331
HK		 4635 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4636
4637 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4638 CSIAR_BYTE_ENABLE);
7e18dca1 4639
ffc46952 4640 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
1ef7286e 4641 RTL_R32(tp, CSIDR) : ~0;
7e18dca1
HW		 4642}
4643
ff1d7331 4644static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
45dd95c4 4645{
ff1d7331
HK		 4646 struct pci_dev *pdev = tp->pci_dev;
4647 u32 csi;
45dd95c4 4648
ff1d7331
HK		 4649 /* According to Realtek the value at config space address 0x070f
4650 * controls the L0s/L1 entrance latency. We try standard ECAM access
4651 * first and if it fails fall back to CSI.
4652 */
4653 if (pdev->cfg_size > 0x070f &&
4654 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4655 return;
4656
4657 netdev_notice_once(tp->dev,
4658 "No native access to PCI extended config space, falling back to CSI\n");
4659 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4660 rtl_csi_write(tp, 0x070c, csi | val << 24);
45dd95c4 4661}
4662
f37658da 4663static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
beb1fe18 4664{
ff1d7331 4665 rtl_csi_access_enable(tp, 0x27);
dacf8154
FR		 4666}
4667
4668struct ephy_info {
4669 unsigned int offset;
4670 u16 mask;
4671 u16 bits;
4672};
4673
fdf6fc06
FR		 4674static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4675 int len)
dacf8154
FR		 4676{
4677 u16 w;
4678
4679 while (len-- > 0) {
fdf6fc06
FR		 4680 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4681 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 4682 e++;
4683 }
4684}
4685
73c86ee3 4686static void rtl_disable_clock_request(struct rtl8169_private *tp)
b726e493 4687{
73c86ee3 4688 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 4689 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 4690}
4691
73c86ee3 4692static void rtl_enable_clock_request(struct rtl8169_private *tp)
e6de30d6 4693{
73c86ee3 4694 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 4695 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 4696}
4697
b51ecea8 4698static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
4699{
b51ecea8 4700 u8 data;
4701
1ef7286e 4702 data = RTL_R8(tp, Config3);
b51ecea8 4703
4704 if (enable)
4705 data |= Rdy_to_L23;
4706 else
4707 data &= ~Rdy_to_L23;
4708
1ef7286e 4709 RTL_W8(tp, Config3, data);
b51ecea8 4710}
4711
a99790bf
KHF		 4712static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4713{
4714 if (enable) {
a99790bf 4715 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
94235460 4716 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
a99790bf
KHF		 4717 } else {
4718 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4719 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4720 }
94235460
KHF		 4721
4722 udelay(10);
a99790bf
KHF		 4723}
4724
beb1fe18 4725static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 4726{
1ef7286e 4727 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
b726e493 4728
12d42c50 4729 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4730 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
b726e493 4731
faf1e785 4732 if (tp->dev->mtu <= ETH_DATA_LEN) {
8d98aa39 4733 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
faf1e785 4734 PCI_EXP_DEVCTL_NOSNOOP_EN);
4735 }
219a1e9d
FR		 4736}
4737
beb1fe18 4738static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 4739{
beb1fe18 4740 rtl_hw_start_8168bb(tp);
b726e493 4741
1ef7286e 4742 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
b726e493 4743
1ef7286e 4744 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
219a1e9d
FR		 4745}
4746
beb1fe18 4747static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 4748{
1ef7286e 4749 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
b726e493 4750
1ef7286e 4751 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
b726e493 4752
faf1e785 4753 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4754 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
b726e493 4755
73c86ee3 4756 rtl_disable_clock_request(tp);
b726e493 4757
12d42c50 4758 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4759 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
219a1e9d
FR		 4760}
4761
beb1fe18 4762static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 4763{
350f7596 4764 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4765 { 0x01, 0, 0x0001 },
4766 { 0x02, 0x0800, 0x1000 },
4767 { 0x03, 0, 0x0042 },
4768 { 0x06, 0x0080, 0x0000 },
4769 { 0x07, 0, 0x2000 }
4770 };
4771
f37658da 4772 rtl_set_def_aspm_entry_latency(tp);
b726e493 4773
fdf6fc06 4774 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 4775
beb1fe18 4776 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4777}
4778
beb1fe18 4779static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 4780{
f37658da 4781 rtl_set_def_aspm_entry_latency(tp);
ef3386f0 4782
1ef7286e 4783 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
ef3386f0 4784
faf1e785 4785 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4786 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
ef3386f0 4787
12d42c50 4788 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4789 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
ef3386f0
FR		 4790}
4791
beb1fe18 4792static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 4793{
f37658da 4794 rtl_set_def_aspm_entry_latency(tp);
7f3e3d3a 4795
1ef7286e 4796 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
7f3e3d3a
FR		 4797
4798 /* Magic. */
1ef7286e 4799 RTL_W8(tp, DBG_REG, 0x20);
7f3e3d3a 4800
1ef7286e 4801 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
7f3e3d3a 4802
faf1e785 4803 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4804 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
7f3e3d3a 4805
12d42c50 4806 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4807 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
7f3e3d3a
FR		 4808}
4809
beb1fe18 4810static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 4811{
350f7596 4812 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4813 { 0x02, 0x0800, 0x1000 },
4814 { 0x03, 0, 0x0002 },
4815 { 0x06, 0x0080, 0x0000 }
4816 };
4817
f37658da 4818 rtl_set_def_aspm_entry_latency(tp);
b726e493 4819
1ef7286e 4820 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
b726e493 4821
fdf6fc06 4822 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 4823
beb1fe18 4824 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4825}
4826
beb1fe18 4827static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 4828{
350f7596 4829 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4830 { 0x01, 0, 0x0001 },
4831 { 0x03, 0x0400, 0x0220 }
4832 };
4833
f37658da 4834 rtl_set_def_aspm_entry_latency(tp);
b726e493 4835
fdf6fc06 4836 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 4837
beb1fe18 4838 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4839}
4840
beb1fe18 4841static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 4842{
beb1fe18 4843 rtl_hw_start_8168c_2(tp);
197ff761
FR		 4844}
4845
beb1fe18 4846static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 4847{
f37658da 4848 rtl_set_def_aspm_entry_latency(tp);
6fb07058 4849
beb1fe18 4850 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 4851}
4852
beb1fe18 4853static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 4854{
f37658da 4855 rtl_set_def_aspm_entry_latency(tp);
5b538df9 4856
73c86ee3 4857 rtl_disable_clock_request(tp);
5b538df9 4858
1ef7286e 4859 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5b538df9 4860
faf1e785 4861 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4862 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5b538df9 4863
12d42c50 4864 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4865 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5b538df9
FR		 4866}
4867
beb1fe18 4868static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 4869{
f37658da 4870 rtl_set_def_aspm_entry_latency(tp);
4804b3b3 4871
faf1e785 4872 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4873 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4804b3b3 4874
1ef7286e 4875 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4804b3b3 4876
73c86ee3 4877 rtl_disable_clock_request(tp);
4804b3b3 4878}
4879
beb1fe18 4880static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 4881{
4882 static const struct ephy_info e_info_8168d_4[] = {
1016a4a1
CHL		 4883 { 0x0b, 0x0000, 0x0048 },
4884 { 0x19, 0x0020, 0x0050 },
4885 { 0x0c, 0x0100, 0x0020 }
e6de30d6 4886 };
e6de30d6 4887
f37658da 4888 rtl_set_def_aspm_entry_latency(tp);
e6de30d6 4889
8d98aa39 4890 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
e6de30d6 4891
1ef7286e 4892 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
e6de30d6 4893
1016a4a1 4894 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
e6de30d6 4895
73c86ee3 4896 rtl_enable_clock_request(tp);
e6de30d6 4897}
4898
beb1fe18 4899static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 4900{
70090424 4901 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 4902 { 0x00, 0x0200, 0x0100 },
4903 { 0x00, 0x0000, 0x0004 },
4904 { 0x06, 0x0002, 0x0001 },
4905 { 0x06, 0x0000, 0x0030 },
4906 { 0x07, 0x0000, 0x2000 },
4907 { 0x00, 0x0000, 0x0020 },
4908 { 0x03, 0x5800, 0x2000 },
4909 { 0x03, 0x0000, 0x0001 },
4910 { 0x01, 0x0800, 0x1000 },
4911 { 0x07, 0x0000, 0x4000 },
4912 { 0x1e, 0x0000, 0x2000 },
4913 { 0x19, 0xffff, 0xfe6c },
4914 { 0x0a, 0x0000, 0x0040 }
4915 };
4916
f37658da 4917 rtl_set_def_aspm_entry_latency(tp);
01dc7fec 4918
fdf6fc06 4919 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 4920
faf1e785 4921 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4922 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
01dc7fec 4923
1ef7286e 4924 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
01dc7fec 4925
73c86ee3 4926 rtl_disable_clock_request(tp);
01dc7fec 4927
4928 /* Reset tx FIFO pointer */
1ef7286e
AS		 4929 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4930 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
01dc7fec 4931
1ef7286e 4932 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
01dc7fec 4933}
4934
beb1fe18 4935static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424
HW		 4936{
4937 static const struct ephy_info e_info_8168e_2[] = {
4938 { 0x09, 0x0000, 0x0080 },
4939 { 0x19, 0x0000, 0x0224 }
4940 };
4941
f37658da 4942 rtl_set_def_aspm_entry_latency(tp);
70090424 4943
fdf6fc06 4944 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424 4945
faf1e785 4946 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4947 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
70090424 4948
fdf6fc06
FR		 4949 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4950 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4951 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4952 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4953 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4954 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
706123d0
CHL		 4955 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4956 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 4957
1ef7286e 4958 RTL_W8(tp, MaxTxPacketSize, EarlySize);
70090424 4959
73c86ee3 4960 rtl_disable_clock_request(tp);
4521e1a9 4961
1ef7286e 4962 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
70090424
HW		 4963
4964 /* Adjust EEE LED frequency */
1ef7286e 4965 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
70090424 4966
1ef7286e
AS		 4967 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4968 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4969 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
aa1e7d2c
HK		 4970
4971 rtl_hw_aspm_clkreq_enable(tp, true);
70090424
HW		 4972}
4973
5f886e08 4974static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 4975{
f37658da 4976 rtl_set_def_aspm_entry_latency(tp);
c2218925 4977
8d98aa39 4978 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
c2218925 4979
fdf6fc06
FR		 4980 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4981 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4982 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4983 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
706123d0
CHL		 4984 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4985 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4986 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4987 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 4988 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4989 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925 4990
1ef7286e 4991 RTL_W8(tp, MaxTxPacketSize, EarlySize);
c2218925 4992
73c86ee3 4993 rtl_disable_clock_request(tp);
4521e1a9 4994
1ef7286e
AS		 4995 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4996 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4997 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4998 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
c2218925
HW		 4999}
5000
5f886e08
HW		 5001static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5002{
5f886e08
HW		 5003 static const struct ephy_info e_info_8168f_1[] = {
5004 { 0x06, 0x00c0, 0x0020 },
5005 { 0x08, 0x0001, 0x0002 },
5006 { 0x09, 0x0000, 0x0080 },
5007 { 0x19, 0x0000, 0x0224 }
5008 };
5009
5010 rtl_hw_start_8168f(tp);
5011
fdf6fc06 5012 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5013
706123d0 5014 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5015
5016 /* Adjust EEE LED frequency */
1ef7286e 5017 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5f886e08
HW		 5018}
5019
b3d7b2f2
HW		 5020static void rtl_hw_start_8411(struct rtl8169_private *tp)
5021{
b3d7b2f2
HW		 5022 static const struct ephy_info e_info_8168f_1[] = {
5023 { 0x06, 0x00c0, 0x0020 },
5024 { 0x0f, 0xffff, 0x5200 },
5025 { 0x1e, 0x0000, 0x4000 },
5026 { 0x19, 0x0000, 0x0224 }
5027 };
5028
5029 rtl_hw_start_8168f(tp);
b51ecea8 5030 rtl_pcie_state_l2l3_enable(tp, false);
b3d7b2f2 5031
fdf6fc06 5032 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 5033
706123d0 5034 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 5035}
5036
5fbea337 5037static void rtl_hw_start_8168g(struct rtl8169_private *tp)
c558386b 5038{
c558386b
HW		 5039 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5040 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5041 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5042 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5043
f37658da 5044 rtl_set_def_aspm_entry_latency(tp);
c558386b 5045
8d98aa39 5046 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
c558386b 5047
706123d0
CHL		 5048 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5049 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
beb330a4 5050 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
c558386b 5051
1ef7286e
AS		 5052 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5053 RTL_W8(tp, MaxTxPacketSize, EarlySize);
c558386b
HW		 5054
5055 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5056 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5057
5058 /* Adjust EEE LED frequency */
1ef7286e 5059 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
c558386b 5060
706123d0
CHL		 5061 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5062 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
b51ecea8 5063
5064 rtl_pcie_state_l2l3_enable(tp, false);
c558386b
HW		 5065}
5066
5fbea337
CHL		 5067static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5068{
5fbea337
CHL		 5069 static const struct ephy_info e_info_8168g_1[] = {
5070 { 0x00, 0x0000, 0x0008 },
5071 { 0x0c, 0x37d0, 0x0820 },
5072 { 0x1e, 0x0000, 0x0001 },
5073 { 0x19, 0x8000, 0x0000 }
5074 };
5075
5076 rtl_hw_start_8168g(tp);
5077
5078 /* disable aspm and clock request before access ephy */
a99790bf 5079 rtl_hw_aspm_clkreq_enable(tp, false);
5fbea337 5080 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
a99790bf 5081 rtl_hw_aspm_clkreq_enable(tp, true);
5fbea337
CHL		 5082}
5083
57538c4a 5084static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5085{
57538c4a 5086 static const struct ephy_info e_info_8168g_2[] = {
5087 { 0x00, 0x0000, 0x0008 },
5088 { 0x0c, 0x3df0, 0x0200 },
5089 { 0x19, 0xffff, 0xfc00 },
5090 { 0x1e, 0xffff, 0x20eb }
5091 };
5092
5fbea337 5093 rtl_hw_start_8168g(tp);
57538c4a 5094
5095 /* disable aspm and clock request before access ephy */
1ef7286e
AS		 5096 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5097 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
57538c4a 5098 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5099}
5100
45dd95c4 5101static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5102{
45dd95c4 5103 static const struct ephy_info e_info_8411_2[] = {
5104 { 0x00, 0x0000, 0x0008 },
5105 { 0x0c, 0x3df0, 0x0200 },
5106 { 0x0f, 0xffff, 0x5200 },
5107 { 0x19, 0x0020, 0x0000 },
5108 { 0x1e, 0x0000, 0x2000 }
5109 };
5110
5fbea337 5111 rtl_hw_start_8168g(tp);
45dd95c4 5112
5113 /* disable aspm and clock request before access ephy */
a99790bf 5114 rtl_hw_aspm_clkreq_enable(tp, false);
45dd95c4 5115 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
a99790bf 5116 rtl_hw_aspm_clkreq_enable(tp, true);
45dd95c4 5117}
5118
6e1d0b89
CHL		 5119static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5120{
72521ea0 5121 int rg_saw_cnt;
6e1d0b89
CHL		 5122 u32 data;
5123 static const struct ephy_info e_info_8168h_1[] = {
5124 { 0x1e, 0x0800, 0x0001 },
5125 { 0x1d, 0x0000, 0x0800 },
5126 { 0x05, 0xffff, 0x2089 },
5127 { 0x06, 0xffff, 0x5881 },
5128 { 0x04, 0xffff, 0x154a },
5129 { 0x01, 0xffff, 0x068b }
5130 };
5131
5132 /* disable aspm and clock request before access ephy */
a99790bf 5133 rtl_hw_aspm_clkreq_enable(tp, false);
6e1d0b89
CHL		 5134 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5135
6e1d0b89
CHL		 5136 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5137 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5138 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5139 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5140
f37658da 5141 rtl_set_def_aspm_entry_latency(tp);
6e1d0b89 5142
8d98aa39 5143 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
6e1d0b89 5144
706123d0
CHL		 5145 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5146 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6e1d0b89 5147
706123d0 5148 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6e1d0b89 5149
706123d0 5150 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6e1d0b89
CHL		 5151
5152 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5153
1ef7286e
AS		 5154 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5155 RTL_W8(tp, MaxTxPacketSize, EarlySize);
6e1d0b89
CHL		 5156
5157 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5158 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5159
5160 /* Adjust EEE LED frequency */
1ef7286e 5161 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
6e1d0b89 5162
1ef7286e
AS		 5163 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5164 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
6e1d0b89 5165
1ef7286e 5166 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
6e1d0b89 5167
706123d0 5168 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6e1d0b89
CHL		 5169
5170 rtl_pcie_state_l2l3_enable(tp, false);
5171
5172 rtl_writephy(tp, 0x1f, 0x0c42);
58493333 5173 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6e1d0b89
CHL		 5174 rtl_writephy(tp, 0x1f, 0x0000);
5175 if (rg_saw_cnt > 0) {
5176 u16 sw_cnt_1ms_ini;
5177
5178 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5179 sw_cnt_1ms_ini &= 0x0fff;
5180 data = r8168_mac_ocp_read(tp, 0xd412);
a2cb7ec0 5181 data &= ~0x0fff;
6e1d0b89
CHL		 5182 data |= sw_cnt_1ms_ini;
5183 r8168_mac_ocp_write(tp, 0xd412, data);
5184 }
5185
5186 data = r8168_mac_ocp_read(tp, 0xe056);
a2cb7ec0
CHL		 5187 data &= ~0xf0;
5188 data |= 0x70;
6e1d0b89
CHL		 5189 r8168_mac_ocp_write(tp, 0xe056, data);
5190
5191 data = r8168_mac_ocp_read(tp, 0xe052);
a2cb7ec0
CHL		 5192 data &= ~0x6000;
5193 data |= 0x8008;
6e1d0b89
CHL		 5194 r8168_mac_ocp_write(tp, 0xe052, data);
5195
5196 data = r8168_mac_ocp_read(tp, 0xe0d6);
a2cb7ec0 5197 data &= ~0x01ff;
6e1d0b89
CHL		 5198 data |= 0x017f;
5199 r8168_mac_ocp_write(tp, 0xe0d6, data);
5200
5201 data = r8168_mac_ocp_read(tp, 0xd420);
a2cb7ec0 5202 data &= ~0x0fff;
6e1d0b89
CHL		 5203 data |= 0x047f;
5204 r8168_mac_ocp_write(tp, 0xd420, data);
5205
5206 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5207 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5208 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5209 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
a99790bf
KHF		 5210
5211 rtl_hw_aspm_clkreq_enable(tp, true);
6e1d0b89
CHL		 5212}
5213
935e2218
CHL		 5214static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5215{
003609da
CHL		 5216 rtl8168ep_stop_cmac(tp);
5217
935e2218
CHL		 5218 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5219 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5220 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5221 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5222
f37658da 5223 rtl_set_def_aspm_entry_latency(tp);
935e2218 5224
8d98aa39 5225 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
935e2218
CHL		 5226
5227 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5228 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5229
5230 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5231
5232 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5233
1ef7286e
AS		 5234 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5235 RTL_W8(tp, MaxTxPacketSize, EarlySize);
935e2218
CHL		 5236
5237 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5238 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5239
5240 /* Adjust EEE LED frequency */
1ef7286e 5241 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
935e2218
CHL		 5242
5243 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5244
1ef7286e 5245 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
935e2218
CHL		 5246
5247 rtl_pcie_state_l2l3_enable(tp, false);
5248}
5249
5250static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5251{
935e2218
CHL		 5252 static const struct ephy_info e_info_8168ep_1[] = {
5253 { 0x00, 0xffff, 0x10ab },
5254 { 0x06, 0xffff, 0xf030 },
5255 { 0x08, 0xffff, 0x2006 },
5256 { 0x0d, 0xffff, 0x1666 },
5257 { 0x0c, 0x3ff0, 0x0000 }
5258 };
5259
5260 /* disable aspm and clock request before access ephy */
a99790bf 5261 rtl_hw_aspm_clkreq_enable(tp, false);
935e2218
CHL		 5262 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5263
5264 rtl_hw_start_8168ep(tp);
a99790bf
KHF		 5265
5266 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5267}
5268
5269static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5270{
935e2218
CHL		 5271 static const struct ephy_info e_info_8168ep_2[] = {
5272 { 0x00, 0xffff, 0x10a3 },
5273 { 0x19, 0xffff, 0xfc00 },
5274 { 0x1e, 0xffff, 0x20ea }
5275 };
5276
5277 /* disable aspm and clock request before access ephy */
a99790bf 5278 rtl_hw_aspm_clkreq_enable(tp, false);
935e2218
CHL		 5279 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5280
5281 rtl_hw_start_8168ep(tp);
5282
1ef7286e
AS		 5283 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5284 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
a99790bf
KHF		 5285
5286 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5287}
5288
5289static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5290{
935e2218
CHL		 5291 u32 data;
5292 static const struct ephy_info e_info_8168ep_3[] = {
5293 { 0x00, 0xffff, 0x10a3 },
5294 { 0x19, 0xffff, 0x7c00 },
5295 { 0x1e, 0xffff, 0x20eb },
5296 { 0x0d, 0xffff, 0x1666 }
5297 };
5298
5299 /* disable aspm and clock request before access ephy */
a99790bf 5300 rtl_hw_aspm_clkreq_enable(tp, false);
935e2218
CHL		 5301 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5302
5303 rtl_hw_start_8168ep(tp);
5304
1ef7286e
AS		 5305 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5306 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
935e2218
CHL		 5307
5308 data = r8168_mac_ocp_read(tp, 0xd3e2);
5309 data &= 0xf000;
5310 data |= 0x0271;
5311 r8168_mac_ocp_write(tp, 0xd3e2, data);
5312
5313 data = r8168_mac_ocp_read(tp, 0xd3e4);
5314 data &= 0xff00;
5315 r8168_mac_ocp_write(tp, 0xd3e4, data);
5316
5317 data = r8168_mac_ocp_read(tp, 0xe860);
5318 data |= 0x0080;
5319 r8168_mac_ocp_write(tp, 0xe860, data);
a99790bf
KHF		 5320
5321 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5322}
5323
61cb532d 5324static void rtl_hw_start_8168(struct rtl8169_private *tp)
07ce4064 5325{
1ef7286e 5326 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
2dd99530 5327
0ae0974e
HK		 5328 tp->cp_cmd &= ~INTT_MASK;
5329 tp->cp_cmd |= PktCntrDisable | INTT_1;
1ef7286e 5330 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2dd99530 5331
1ef7286e 5332 RTL_W16(tp, IntrMitigate, 0x5151);
2dd99530 5333
0e485150 5334 /* Work around for RxFIFO overflow. */
811fd301 5335 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
559c3c04
HK		 5336 tp->irq_mask |= RxFIFOOver;
5337 tp->irq_mask &= ~RxOverflow;
0e485150
FR		 5338 }
5339
219a1e9d
FR		 5340 switch (tp->mac_version) {
5341 case RTL_GIGA_MAC_VER_11:
beb1fe18 5342 rtl_hw_start_8168bb(tp);
4804b3b3 5343 break;
219a1e9d
FR		 5344
5345 case RTL_GIGA_MAC_VER_12:
5346 case RTL_GIGA_MAC_VER_17:
beb1fe18 5347 rtl_hw_start_8168bef(tp);
4804b3b3 5348 break;
219a1e9d
FR		 5349
5350 case RTL_GIGA_MAC_VER_18:
beb1fe18 5351 rtl_hw_start_8168cp_1(tp);
4804b3b3 5352 break;
219a1e9d
FR		 5353
5354 case RTL_GIGA_MAC_VER_19:
beb1fe18 5355 rtl_hw_start_8168c_1(tp);
4804b3b3 5356 break;
219a1e9d
FR		 5357
5358 case RTL_GIGA_MAC_VER_20:
beb1fe18 5359 rtl_hw_start_8168c_2(tp);
4804b3b3 5360 break;
219a1e9d 5361
197ff761 5362 case RTL_GIGA_MAC_VER_21:
beb1fe18 5363 rtl_hw_start_8168c_3(tp);
4804b3b3 5364 break;
197ff761 5365
6fb07058 5366 case RTL_GIGA_MAC_VER_22:
beb1fe18 5367 rtl_hw_start_8168c_4(tp);
4804b3b3 5368 break;
6fb07058 5369
ef3386f0 5370 case RTL_GIGA_MAC_VER_23:
beb1fe18 5371 rtl_hw_start_8168cp_2(tp);
4804b3b3 5372 break;
ef3386f0 5373
7f3e3d3a 5374 case RTL_GIGA_MAC_VER_24:
beb1fe18 5375 rtl_hw_start_8168cp_3(tp);
4804b3b3 5376 break;
7f3e3d3a 5377
5b538df9 5378 case RTL_GIGA_MAC_VER_25:
daf9df6d 5379 case RTL_GIGA_MAC_VER_26:
5380 case RTL_GIGA_MAC_VER_27:
beb1fe18 5381 rtl_hw_start_8168d(tp);
4804b3b3 5382 break;
5b538df9 5383
e6de30d6 5384 case RTL_GIGA_MAC_VER_28:
beb1fe18 5385 rtl_hw_start_8168d_4(tp);
4804b3b3 5386 break;
cecb5fd7 5387
4804b3b3 5388 case RTL_GIGA_MAC_VER_31:
beb1fe18 5389 rtl_hw_start_8168dp(tp);
4804b3b3 5390 break;
5391
01dc7fec 5392 case RTL_GIGA_MAC_VER_32:
5393 case RTL_GIGA_MAC_VER_33:
beb1fe18 5394 rtl_hw_start_8168e_1(tp);
70090424
HW		 5395 break;
5396 case RTL_GIGA_MAC_VER_34:
beb1fe18 5397 rtl_hw_start_8168e_2(tp);
01dc7fec 5398 break;
e6de30d6 5399
c2218925
HW		 5400 case RTL_GIGA_MAC_VER_35:
5401 case RTL_GIGA_MAC_VER_36:
beb1fe18 5402 rtl_hw_start_8168f_1(tp);
c2218925
HW		 5403 break;
5404
b3d7b2f2
HW		 5405 case RTL_GIGA_MAC_VER_38:
5406 rtl_hw_start_8411(tp);
5407 break;
5408
c558386b
HW		 5409 case RTL_GIGA_MAC_VER_40:
5410 case RTL_GIGA_MAC_VER_41:
5411 rtl_hw_start_8168g_1(tp);
5412 break;
57538c4a 5413 case RTL_GIGA_MAC_VER_42:
5414 rtl_hw_start_8168g_2(tp);
5415 break;
c558386b 5416
45dd95c4 5417 case RTL_GIGA_MAC_VER_44:
5418 rtl_hw_start_8411_2(tp);
5419 break;
5420
6e1d0b89
CHL		 5421 case RTL_GIGA_MAC_VER_45:
5422 case RTL_GIGA_MAC_VER_46:
5423 rtl_hw_start_8168h_1(tp);
5424 break;
5425
935e2218
CHL		 5426 case RTL_GIGA_MAC_VER_49:
5427 rtl_hw_start_8168ep_1(tp);
5428 break;
5429
5430 case RTL_GIGA_MAC_VER_50:
5431 rtl_hw_start_8168ep_2(tp);
5432 break;
5433
5434 case RTL_GIGA_MAC_VER_51:
5435 rtl_hw_start_8168ep_3(tp);
5436 break;
5437
219a1e9d 5438 default:
49d17512
HK		 5439 netif_err(tp, drv, tp->dev,
5440 "unknown chipset (mac_version = %d)\n",
5441 tp->mac_version);
4804b3b3 5442 break;
219a1e9d 5443 }
07ce4064 5444}
1da177e4 5445
beb1fe18 5446static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 5447{
350f7596 5448 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5449 { 0x01, 0, 0x6e65 },
5450 { 0x02, 0, 0x091f },
5451 { 0x03, 0, 0xc2f9 },
5452 { 0x06, 0, 0xafb5 },
5453 { 0x07, 0, 0x0e00 },
5454 { 0x19, 0, 0xec80 },
5455 { 0x01, 0, 0x2e65 },
5456 { 0x01, 0, 0x6e65 }
5457 };
5458 u8 cfg1;
5459
f37658da 5460 rtl_set_def_aspm_entry_latency(tp);
2857ffb7 5461
1ef7286e 5462 RTL_W8(tp, DBG_REG, FIX_NAK_1);
2857ffb7 5463
8d98aa39 5464 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
2857ffb7 5465
1ef7286e 5466 RTL_W8(tp, Config1,
2857ffb7 5467 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
1ef7286e 5468 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7 5469
1ef7286e 5470 cfg1 = RTL_R8(tp, Config1);
2857ffb7 5471 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
1ef7286e 5472 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
2857ffb7 5473
fdf6fc06 5474 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 5475}
5476
beb1fe18 5477static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 5478{
f37658da 5479 rtl_set_def_aspm_entry_latency(tp);
2857ffb7 5480
8d98aa39 5481 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
2857ffb7 5482
1ef7286e
AS		 5483 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5484 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7
FR		 5485}
5486
beb1fe18 5487static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 5488{
beb1fe18 5489 rtl_hw_start_8102e_2(tp);
2857ffb7 5490
fdf6fc06 5491 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 5492}
5493
beb1fe18 5494static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443
HW		 5495{
5496 static const struct ephy_info e_info_8105e_1[] = {
5497 { 0x07, 0, 0x4000 },
5498 { 0x19, 0, 0x0200 },
5499 { 0x19, 0, 0x0020 },
5500 { 0x1e, 0, 0x2000 },
5501 { 0x03, 0, 0x0001 },
5502 { 0x19, 0, 0x0100 },
5503 { 0x19, 0, 0x0004 },
5504 { 0x0a, 0, 0x0020 }
5505 };
5506
cecb5fd7 5507 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 5508 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5a5e4443 5509
cecb5fd7 5510 /* Disable Early Tally Counter */
1ef7286e 5511 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5a5e4443 5512
1ef7286e
AS		 5513 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5514 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5a5e4443 5515
fdf6fc06 5516 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
b51ecea8 5517
5518 rtl_pcie_state_l2l3_enable(tp, false);
5a5e4443
HW		 5519}
5520
beb1fe18 5521static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 5522{
beb1fe18 5523 rtl_hw_start_8105e_1(tp);
fdf6fc06 5524 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 5525}
5526
7e18dca1
HW		 5527static void rtl_hw_start_8402(struct rtl8169_private *tp)
5528{
7e18dca1
HW		 5529 static const struct ephy_info e_info_8402[] = {
5530 { 0x19, 0xffff, 0xff64 },
5531 { 0x1e, 0, 0x4000 }
5532 };
5533
f37658da 5534 rtl_set_def_aspm_entry_latency(tp);
7e18dca1
HW		 5535
5536 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 5537 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
7e18dca1 5538
1ef7286e 5539 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7e18dca1 5540
fdf6fc06 5541 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1 5542
8d98aa39 5543 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
7e18dca1 5544
fdf6fc06
FR		 5545 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5546 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
706123d0
CHL		 5547 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5548 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 5549 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5550 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
706123d0 5551 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
b51ecea8 5552
5553 rtl_pcie_state_l2l3_enable(tp, false);
7e18dca1
HW		 5554}
5555
5598bfe5
HW		 5556static void rtl_hw_start_8106(struct rtl8169_private *tp)
5557{
0866cd15
KHF		 5558 rtl_hw_aspm_clkreq_enable(tp, false);
5559
5598bfe5 5560 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 5561 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5598bfe5 5562
1ef7286e
AS		 5563 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5564 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5565 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
b51ecea8 5566
5567 rtl_pcie_state_l2l3_enable(tp, false);
0866cd15 5568 rtl_hw_aspm_clkreq_enable(tp, true);
5598bfe5
HW		 5569}
5570
61cb532d 5571static void rtl_hw_start_8101(struct rtl8169_private *tp)
07ce4064 5572{
da78dbff 5573 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
559c3c04 5574 tp->irq_mask &= ~RxFIFOOver;
811fd301 5575
cecb5fd7 5576 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 5577 tp->mac_version == RTL_GIGA_MAC_VER_16)
61cb532d 5578 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
8200bc72 5579 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 5580
1ef7286e 5581 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
1a964649 5582
12d42c50 5583 tp->cp_cmd &= CPCMD_QUIRK_MASK;
1ef7286e 5584 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1a964649 5585
2857ffb7
FR		 5586 switch (tp->mac_version) {
5587 case RTL_GIGA_MAC_VER_07:
beb1fe18 5588 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 5589 break;
5590
5591 case RTL_GIGA_MAC_VER_08:
beb1fe18 5592 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 5593 break;
5594
5595 case RTL_GIGA_MAC_VER_09:
beb1fe18 5596 rtl_hw_start_8102e_2(tp);
2857ffb7 5597 break;
5a5e4443
HW		 5598
5599 case RTL_GIGA_MAC_VER_29:
beb1fe18 5600 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 5601 break;
5602 case RTL_GIGA_MAC_VER_30:
beb1fe18 5603 rtl_hw_start_8105e_2(tp);
5a5e4443 5604 break;
7e18dca1
HW		 5605
5606 case RTL_GIGA_MAC_VER_37:
5607 rtl_hw_start_8402(tp);
5608 break;
5598bfe5
HW		 5609
5610 case RTL_GIGA_MAC_VER_39:
5611 rtl_hw_start_8106(tp);
5612 break;
58152cd4 5613 case RTL_GIGA_MAC_VER_43:
5614 rtl_hw_start_8168g_2(tp);
5615 break;
6e1d0b89
CHL		 5616 case RTL_GIGA_MAC_VER_47:
5617 case RTL_GIGA_MAC_VER_48:
5618 rtl_hw_start_8168h_1(tp);
5619 break;
cdf1a608
FR		 5620 }
5621
1ef7286e 5622 RTL_W16(tp, IntrMitigate, 0x0000);
1da177e4
LT		 5623}
5624
5625static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5626{
d58d46b5
FR		 5627 struct rtl8169_private *tp = netdev_priv(dev);
5628
d58d46b5
FR		 5629 if (new_mtu > ETH_DATA_LEN)
5630 rtl_hw_jumbo_enable(tp);
5631 else
5632 rtl_hw_jumbo_disable(tp);
5633
1da177e4 5634 dev->mtu = new_mtu;
350fb32a
MM		 5635 netdev_update_features(dev);
5636
323bb685 5637 return 0;
1da177e4
LT		 5638}
5639
5640static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5641{
95e0918d 5642 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 5643 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5644}
5645
6f0333b8
ED		 5646static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5647 void **data_buff, struct RxDesc *desc)
1da177e4 5648{
1d0254dd
HK		 5649 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5650 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
48addcc9 5651
6f0333b8
ED		 5652 kfree(*data_buff);
5653 *data_buff = NULL;
1da177e4
LT		 5654 rtl8169_make_unusable_by_asic(desc);
5655}
5656
1d0254dd 5657static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
1da177e4
LT		 5658{
5659 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5660
a0750138
AD		 5661 /* Force memory writes to complete before releasing descriptor */
5662 dma_wmb();
5663
1d0254dd 5664 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
1da177e4
LT		 5665}
5666
6f0333b8
ED		 5667static inline void *rtl8169_align(void *data)
5668{
5669 return (void *)ALIGN((long)data, 16);
5670}
5671
0ecbe1ca
SG		 5672static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5673 struct RxDesc *desc)
1da177e4 5674{
6f0333b8 5675 void *data;
1da177e4 5676 dma_addr_t mapping;
1e1205b7 5677 struct device *d = tp_to_dev(tp);
d3b404c2 5678 int node = dev_to_node(d);
1da177e4 5679
1d0254dd 5680 data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
6f0333b8
ED		 5681 if (!data)
5682 return NULL;
e9f63f30 5683
6f0333b8
ED		 5684 if (rtl8169_align(data) != data) {
5685 kfree(data);
1d0254dd 5686 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
6f0333b8
ED		 5687 if (!data)
5688 return NULL;
5689 }
3eafe507 5690
1d0254dd 5691 mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
231aee63 5692 DMA_FROM_DEVICE);
d827d86b
SG		 5693 if (unlikely(dma_mapping_error(d, mapping))) {
5694 if (net_ratelimit())
5695 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 5696 goto err_out;
d827d86b 5697 }
1da177e4 5698
d731af78
HK		 5699 desc->addr = cpu_to_le64(mapping);
5700 rtl8169_mark_to_asic(desc);
6f0333b8 5701 return data;
3eafe507
SG		 5702
5703err_out:
5704 kfree(data);
5705 return NULL;
1da177e4
LT		 5706}
5707
5708static void rtl8169_rx_clear(struct rtl8169_private *tp)
5709{
07d3f51f 5710 unsigned int i;
1da177e4
LT		 5711
5712 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 5713 if (tp->Rx_databuff[i]) {
5714 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 5715 tp->RxDescArray + i);
5716 }
5717 }
5718}
5719
0ecbe1ca 5720static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 5721{
0ecbe1ca
SG		 5722 desc->opts1 |= cpu_to_le32(RingEnd);
5723}
5b0384f4 5724
0ecbe1ca
SG		 5725static int rtl8169_rx_fill(struct rtl8169_private *tp)
5726{
5727 unsigned int i;
1da177e4 5728
0ecbe1ca
SG		 5729 for (i = 0; i < NUM_RX_DESC; i++) {
5730 void *data;
4ae47c2d 5731
0ecbe1ca 5732 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 5733 if (!data) {
5734 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 5735 goto err_out;
6f0333b8
ED		 5736 }
5737 tp->Rx_databuff[i] = data;
1da177e4 5738 }
1da177e4 5739
0ecbe1ca
SG		 5740 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5741 return 0;
5742
5743err_out:
5744 rtl8169_rx_clear(tp);
5745 return -ENOMEM;
1da177e4
LT		 5746}
5747
b1127e64 5748static int rtl8169_init_ring(struct rtl8169_private *tp)
1da177e4 5749{
1da177e4
LT		 5750 rtl8169_init_ring_indexes(tp);
5751
b1127e64
HK		 5752 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5753 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
1da177e4 5754
0ecbe1ca 5755 return rtl8169_rx_fill(tp);
1da177e4
LT		 5756}
5757
48addcc9 5758static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 5759 struct TxDesc *desc)
5760{
5761 unsigned int len = tx_skb->len;
5762
48addcc9
SG		 5763 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5764
1da177e4
LT		 5765 desc->opts1 = 0x00;
5766 desc->opts2 = 0x00;
5767 desc->addr = 0x00;
5768 tx_skb->len = 0;
5769}
5770
3eafe507
SG		 5771static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5772 unsigned int n)
1da177e4
LT		 5773{
5774 unsigned int i;
5775
3eafe507
SG		 5776 for (i = 0; i < n; i++) {
5777 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 5778 struct ring_info *tx_skb = tp->tx_skb + entry;
5779 unsigned int len = tx_skb->len;
5780
5781 if (len) {
5782 struct sk_buff *skb = tx_skb->skb;
5783
1e1205b7 5784 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
1da177e4
LT		 5785 tp->TxDescArray + entry);
5786 if (skb) {
7a4b813c 5787 dev_consume_skb_any(skb);
1da177e4
LT		 5788 tx_skb->skb = NULL;
5789 }
1da177e4
LT		 5790 }
5791 }
3eafe507
SG		 5792}
5793
5794static void rtl8169_tx_clear(struct rtl8169_private *tp)
5795{
5796 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4 5797 tp->cur_tx = tp->dirty_tx = 0;
d92060bc 5798 netdev_reset_queue(tp->dev);
1da177e4
LT		 5799}
5800
4422bcd4 5801static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 5802{
c4028958 5803 struct net_device *dev = tp->dev;
56de414c 5804 int i;
1da177e4 5805
da78dbff
FR		 5806 napi_disable(&tp->napi);
5807 netif_stop_queue(dev);
16f11500 5808 synchronize_rcu();
1da177e4 5809
c7c2c39b 5810 rtl8169_hw_reset(tp);
5811
56de414c 5812 for (i = 0; i < NUM_RX_DESC; i++)
1d0254dd 5813 rtl8169_mark_to_asic(tp->RxDescArray + i);
56de414c 5814
1da177e4 5815 rtl8169_tx_clear(tp);
c7c2c39b 5816 rtl8169_init_ring_indexes(tp);
1da177e4 5817
da78dbff 5818 napi_enable(&tp->napi);
61cb532d 5819 rtl_hw_start(tp);
56de414c 5820 netif_wake_queue(dev);
1da177e4
LT		 5821}
5822
5823static void rtl8169_tx_timeout(struct net_device *dev)
5824{
da78dbff
FR		 5825 struct rtl8169_private *tp = netdev_priv(dev);
5826
5827 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5828}
5829
734c1409
HK		 5830static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5831{
5832 u32 status = opts0 | len;
5833
5834 if (entry == NUM_TX_DESC - 1)
5835 status |= RingEnd;
5836
5837 return cpu_to_le32(status);
5838}
5839
1da177e4 5840static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5841 u32 *opts)
1da177e4
LT		 5842{
5843 struct skb_shared_info *info = skb_shinfo(skb);
5844 unsigned int cur_frag, entry;
6e1d0b89 5845 struct TxDesc *uninitialized_var(txd);
1e1205b7 5846 struct device *d = tp_to_dev(tp);
1da177e4
LT		 5847
5848 entry = tp->cur_tx;
5849 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 5850 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4 5851 dma_addr_t mapping;
734c1409 5852 u32 len;
1da177e4
LT		 5853 void *addr;
5854
5855 entry = (entry + 1) % NUM_TX_DESC;
5856
5857 txd = tp->TxDescArray + entry;
9e903e08 5858 len = skb_frag_size(frag);
929f6189 5859 addr = skb_frag_address(frag);
48addcc9 5860 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5861 if (unlikely(dma_mapping_error(d, mapping))) {
5862 if (net_ratelimit())
5863 netif_err(tp, drv, tp->dev,
5864 "Failed to map TX fragments DMA!\n");
3eafe507 5865 goto err_out;
d827d86b 5866 }
1da177e4 5867
734c1409 5868 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
2b7b4318 5869 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5870 txd->addr = cpu_to_le64(mapping);
5871
5872 tp->tx_skb[entry].len = len;
5873 }
5874
5875 if (cur_frag) {
5876 tp->tx_skb[entry].skb = skb;
5877 txd->opts1 |= cpu_to_le32(LastFrag);
5878 }
5879
5880 return cur_frag;
3eafe507
SG		 5881
5882err_out:
5883 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5884 return -EIO;
1da177e4
LT		 5885}
5886
b423e9ae 5887static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5888{
5889 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5890}
5891
e974604b 5892static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5893 struct net_device *dev);
5894/* r8169_csum_workaround()
5895 * The hw limites the value the transport offset. When the offset is out of the
5896 * range, calculate the checksum by sw.
5897 */
5898static void r8169_csum_workaround(struct rtl8169_private *tp,
5899 struct sk_buff *skb)
5900{
5901 if (skb_shinfo(skb)->gso_size) {
5902 netdev_features_t features = tp->dev->features;
5903 struct sk_buff *segs, *nskb;
5904
5905 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5906 segs = skb_gso_segment(skb, features);
5907 if (IS_ERR(segs) || !segs)
5908 goto drop;
5909
5910 do {
5911 nskb = segs;
5912 segs = segs->next;
5913 nskb->next = NULL;
5914 rtl8169_start_xmit(nskb, tp->dev);
5915 } while (segs);
5916
eb781397 5917 dev_consume_skb_any(skb);
e974604b 5918 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5919 if (skb_checksum_help(skb) < 0)
5920 goto drop;
5921
5922 rtl8169_start_xmit(skb, tp->dev);
5923 } else {
5924 struct net_device_stats *stats;
5925
5926drop:
5927 stats = &tp->dev->stats;
5928 stats->tx_dropped++;
eb781397 5929 dev_kfree_skb_any(skb);
e974604b 5930 }
5931}
5932
5933/* msdn_giant_send_check()
5934 * According to the document of microsoft, the TCP Pseudo Header excludes the
5935 * packet length for IPv6 TCP large packets.
5936 */
5937static int msdn_giant_send_check(struct sk_buff *skb)
5938{
5939 const struct ipv6hdr *ipv6h;
5940 struct tcphdr *th;
5941 int ret;
5942
5943 ret = skb_cow_head(skb, 0);
5944 if (ret)
5945 return ret;
5946
5947 ipv6h = ipv6_hdr(skb);
5948 th = tcp_hdr(skb);
5949
5950 th->check = 0;
5951 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5952
5953 return ret;
5954}
5955
5888d3fc 5956static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
5957 struct sk_buff *skb, u32 *opts)
1da177e4 5958{
350fb32a
MM		 5959 u32 mss = skb_shinfo(skb)->gso_size;
5960
2b7b4318
FR		 5961 if (mss) {
5962 opts[0] |= TD_LSO;
5888d3fc 5963 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5964 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5965 const struct iphdr *ip = ip_hdr(skb);
5966
5967 if (ip->protocol == IPPROTO_TCP)
5968 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5969 else if (ip->protocol == IPPROTO_UDP)
5970 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5971 else
5972 WARN_ON_ONCE(1);
5973 }
5974
5975 return true;
5976}
5977
5978static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5979 struct sk_buff *skb, u32 *opts)
5980{
bdfa4ed6 5981 u32 transport_offset = (u32)skb_transport_offset(skb);
5888d3fc 5982 u32 mss = skb_shinfo(skb)->gso_size;
5983
5984 if (mss) {
e974604b 5985 if (transport_offset > GTTCPHO_MAX) {
5986 netif_warn(tp, tx_err, tp->dev,
5987 "Invalid transport offset 0x%x for TSO\n",
5988 transport_offset);
5989 return false;
5990 }
5991
4ff36466 5992 switch (vlan_get_protocol(skb)) {
e974604b 5993 case htons(ETH_P_IP):
5994 opts[0] |= TD1_GTSENV4;
5995 break;
5996
5997 case htons(ETH_P_IPV6):
5998 if (msdn_giant_send_check(skb))
5999 return false;
6000
6001 opts[0] |= TD1_GTSENV6;
6002 break;
6003
6004 default:
6005 WARN_ON_ONCE(1);
6006 break;
6007 }
6008
bdfa4ed6 6009 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5888d3fc 6010 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
2b7b4318 6011 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
e974604b 6012 u8 ip_protocol;
1da177e4 6013
b423e9ae 6014 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 6015 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
b423e9ae 6016
e974604b 6017 if (transport_offset > TCPHO_MAX) {
6018 netif_warn(tp, tx_err, tp->dev,
6019 "Invalid transport offset 0x%x\n",
6020 transport_offset);
6021 return false;
6022 }
6023
4ff36466 6024 switch (vlan_get_protocol(skb)) {
e974604b 6025 case htons(ETH_P_IP):
6026 opts[1] |= TD1_IPv4_CS;
6027 ip_protocol = ip_hdr(skb)->protocol;
6028 break;
6029
6030 case htons(ETH_P_IPV6):
6031 opts[1] |= TD1_IPv6_CS;
6032 ip_protocol = ipv6_hdr(skb)->nexthdr;
6033 break;
6034
6035 default:
6036 ip_protocol = IPPROTO_RAW;
6037 break;
6038 }
6039
6040 if (ip_protocol == IPPROTO_TCP)
6041 opts[1] |= TD1_TCP_CS;
6042 else if (ip_protocol == IPPROTO_UDP)
6043 opts[1] |= TD1_UDP_CS;
2b7b4318
FR		 6044 else
6045 WARN_ON_ONCE(1);
e974604b 6046
6047 opts[1] |= transport_offset << TCPHO_SHIFT;
b423e9ae 6048 } else {
6049 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 6050 return !eth_skb_pad(skb);
1da177e4 6051 }
5888d3fc 6052
b423e9ae 6053 return true;
1da177e4
LT		 6054}
6055
76085c9e
HK		 6056static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
6057 unsigned int nr_frags)
6058{
6059 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
6060
6061 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
6062 return slots_avail > nr_frags;
6063}
6064
61357325
SH		 6065static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6066 struct net_device *dev)
1da177e4
LT		 6067{
6068 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 6069 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4 6070 struct TxDesc *txd = tp->TxDescArray + entry;
1e1205b7 6071 struct device *d = tp_to_dev(tp);
1da177e4 6072 dma_addr_t mapping;
734c1409 6073 u32 opts[2], len;
2e6eedb4 6074 bool stop_queue;
3eafe507 6075 int frags;
5b0384f4 6076
76085c9e 6077 if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 6078 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 6079 goto err_stop_0;
1da177e4
LT		 6080 }
6081
6082 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 6083 goto err_stop_0;
6084
b423e9ae 6085 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6086 opts[0] = DescOwn;
6087
e974604b 6088 if (!tp->tso_csum(tp, skb, opts)) {
6089 r8169_csum_workaround(tp, skb);
6090 return NETDEV_TX_OK;
6091 }
b423e9ae 6092
3eafe507 6093 len = skb_headlen(skb);
48addcc9 6094 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 6095 if (unlikely(dma_mapping_error(d, mapping))) {
6096 if (net_ratelimit())
6097 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 6098 goto err_dma_0;
d827d86b 6099 }
3eafe507
SG		 6100
6101 tp->tx_skb[entry].len = len;
6102 txd->addr = cpu_to_le64(mapping);
1da177e4 6103
2b7b4318 6104 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 6105 if (frags < 0)
6106 goto err_dma_1;
6107 else if (frags)
2b7b4318 6108 opts[0] |= FirstFrag;
3eafe507 6109 else {
2b7b4318 6110 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 6111 tp->tx_skb[entry].skb = skb;
6112 }
6113
2b7b4318
FR		 6114 txd->opts2 = cpu_to_le32(opts[1]);
6115
5047fb5d
RC		 6116 skb_tx_timestamp(skb);
6117
a0750138
AD		 6118 /* Force memory writes to complete before releasing descriptor */
6119 dma_wmb();
1da177e4 6120
734c1409 6121 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
1da177e4 6122
a0750138 6123 /* Force all memory writes to complete before notifying device */
4c020a96 6124 wmb();
1da177e4 6125
a0750138
AD		 6126 tp->cur_tx += frags + 1;
6127
2e6eedb4
HK		 6128 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS);
6129 if (unlikely(stop_queue))
6130 netif_stop_queue(dev);
1da177e4 6131
bd7153bd 6132 if (__netdev_sent_queue(dev, skb->len, skb->xmit_more))
2e6eedb4 6133 RTL_W8(tp, TxPoll, NPQ);
da78dbff 6134
2e6eedb4 6135 if (unlikely(stop_queue)) {
ae1f23fb
FR		 6136 /* Sync with rtl_tx:
6137 * - publish queue status and cur_tx ring index (write barrier)
6138 * - refresh dirty_tx ring index (read barrier).
6139 * May the current thread have a pessimistic view of the ring
6140 * status and forget to wake up queue, a racing rtl_tx thread
6141 * can't.
6142 */
1e874e04 6143 smp_mb();
76085c9e 6144 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
1da177e4
LT		 6145 netif_wake_queue(dev);
6146 }
6147
61357325 6148 return NETDEV_TX_OK;
1da177e4 6149
3eafe507 6150err_dma_1:
48addcc9 6151 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507 6152err_dma_0:
989c9ba1 6153 dev_kfree_skb_any(skb);
3eafe507
SG		 6154 dev->stats.tx_dropped++;
6155 return NETDEV_TX_OK;
6156
6157err_stop_0:
1da177e4 6158 netif_stop_queue(dev);
cebf8cc7 6159 dev->stats.tx_dropped++;
61357325 6160 return NETDEV_TX_BUSY;
1da177e4
LT		 6161}
6162
6163static void rtl8169_pcierr_interrupt(struct net_device *dev)
6164{
6165 struct rtl8169_private *tp = netdev_priv(dev);
6166 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 6167 u16 pci_status, pci_cmd;
6168
6169 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6170 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6171
bf82c189
JP		 6172 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6173 pci_cmd, pci_status);
1da177e4
LT		 6174
6175 /*
6176 * The recovery sequence below admits a very elaborated explanation:
6177 * - it seems to work;
d03902b8
FR		 6178 * - I did not see what else could be done;
6179 * - it makes iop3xx happy.
1da177e4
LT		 6180 *
6181 * Feel free to adjust to your needs.
6182 */
a27993f3 6183 if (pdev->broken_parity_status)
d03902b8
FR		 6184 pci_cmd &= ~PCI_COMMAND_PARITY;
6185 else
6186 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6187
6188 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 6189
6190 pci_write_config_word(pdev, PCI_STATUS,
6191 pci_status & (PCI_STATUS_DETECTED_PARITY |
6192 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6193 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6194
6195 /* The infamous DAC f*ckup only happens at boot time */
9fba0812 6196 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
bf82c189 6197 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4 6198 tp->cp_cmd &= ~PCIDAC;
1ef7286e 6199 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1da177e4 6200 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 6201 }
6202
e6de30d6 6203 rtl8169_hw_reset(tp);
d03902b8 6204
98ddf986 6205 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 6206}
6207
5317d5c6
HK		 6208static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
6209 int budget)
1da177e4 6210{
d92060bc 6211 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
1da177e4 6212
1da177e4
LT		 6213 dirty_tx = tp->dirty_tx;
6214 smp_rmb();
6215 tx_left = tp->cur_tx - dirty_tx;
6216
6217 while (tx_left > 0) {
6218 unsigned int entry = dirty_tx % NUM_TX_DESC;
6219 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 6220 u32 status;
6221
1da177e4
LT		 6222 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6223 if (status & DescOwn)
6224 break;
6225
a0750138
AD		 6226 /* This barrier is needed to keep us from reading
6227 * any other fields out of the Tx descriptor until
6228 * we know the status of DescOwn
6229 */
6230 dma_rmb();
6231
1e1205b7 6232 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
48addcc9 6233 tp->TxDescArray + entry);
1da177e4 6234 if (status & LastFrag) {
d92060bc
FW		 6235 pkts_compl++;
6236 bytes_compl += tx_skb->skb->len;
5317d5c6 6237 napi_consume_skb(tx_skb->skb, budget);
1da177e4
LT		 6238 tx_skb->skb = NULL;
6239 }
6240 dirty_tx++;
6241 tx_left--;
6242 }
6243
6244 if (tp->dirty_tx != dirty_tx) {
d92060bc
FW		 6245 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6246
6247 u64_stats_update_begin(&tp->tx_stats.syncp);
6248 tp->tx_stats.packets += pkts_compl;
6249 tp->tx_stats.bytes += bytes_compl;
6250 u64_stats_update_end(&tp->tx_stats.syncp);
6251
1da177e4 6252 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 6253 /* Sync with rtl8169_start_xmit:
6254 * - publish dirty_tx ring index (write barrier)
6255 * - refresh cur_tx ring index and queue status (read barrier)
6256 * May the current thread miss the stopped queue condition,
6257 * a racing xmit thread can only have a right view of the
6258 * ring status.
6259 */
1e874e04 6260 smp_mb();
1da177e4 6261 if (netif_queue_stopped(dev) &&
76085c9e 6262 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 6263 netif_wake_queue(dev);
6264 }
d78ae2dc
FR		 6265 /*
6266 * 8168 hack: TxPoll requests are lost when the Tx packets are
6267 * too close. Let's kick an extra TxPoll request when a burst
6268 * of start_xmit activity is detected (if it is not detected,
6269 * it is slow enough). -- FR
6270 */
1ef7286e
AS		 6271 if (tp->cur_tx != dirty_tx)
6272 RTL_W8(tp, TxPoll, NPQ);
1da177e4
LT		 6273 }
6274}
6275
126fa4b9
FR		 6276static inline int rtl8169_fragmented_frame(u32 status)
6277{
6278 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6279}
6280
adea1ac7 6281static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 6282{
1da177e4
LT		 6283 u32 status = opts1 & RxProtoMask;
6284
6285 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 6286 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 6287 skb->ip_summed = CHECKSUM_UNNECESSARY;
6288 else
bc8acf2c 6289 skb_checksum_none_assert(skb);
1da177e4
LT		 6290}
6291
6f0333b8
ED		 6292static struct sk_buff *rtl8169_try_rx_copy(void *data,
6293 struct rtl8169_private *tp,
6294 int pkt_size,
6295 dma_addr_t addr)
1da177e4 6296{
b449655f 6297 struct sk_buff *skb;
1e1205b7 6298 struct device *d = tp_to_dev(tp);
b449655f 6299
6f0333b8 6300 data = rtl8169_align(data);
48addcc9 6301 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8 6302 prefetch(data);
e2338f86 6303 skb = napi_alloc_skb(&tp->napi, pkt_size);
6f0333b8 6304 if (skb)
8a67aa86 6305 skb_copy_to_linear_data(skb, data, pkt_size);
48addcc9
SG		 6306 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6307
6f0333b8 6308 return skb;
1da177e4
LT		 6309}
6310
da78dbff 6311static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 6312{
6313 unsigned int cur_rx, rx_left;
6f0333b8 6314 unsigned int count;
1da177e4 6315
1da177e4 6316 cur_rx = tp->cur_rx;
1da177e4 6317
9fba0812 6318 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 6319 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 6320 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 6321 u32 status;
6322
6202806e 6323 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 6324 if (status & DescOwn)
6325 break;
a0750138
AD		 6326
6327 /* This barrier is needed to keep us from reading
6328 * any other fields out of the Rx descriptor until
6329 * we know the status of DescOwn
6330 */
6331 dma_rmb();
6332
4dcb7d33 6333 if (unlikely(status & RxRES)) {
bf82c189
JP		 6334 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6335 status);
cebf8cc7 6336 dev->stats.rx_errors++;
1da177e4 6337 if (status & (RxRWT | RxRUNT))
cebf8cc7 6338 dev->stats.rx_length_errors++;
1da177e4 6339 if (status & RxCRC)
cebf8cc7 6340 dev->stats.rx_crc_errors++;
6202806e
HK		 6341 /* RxFOVF is a reserved bit on later chip versions */
6342 if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6343 status & RxFOVF) {
da78dbff 6344 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 6345 dev->stats.rx_fifo_errors++;
6202806e
HK		 6346 } else if (status & (RxRUNT | RxCRC) &&
6347 !(status & RxRWT) &&
6348 dev->features & NETIF_F_RXALL) {
6bbe021d 6349 goto process_pkt;
6202806e 6350 }
1da177e4 6351 } else {
6f0333b8 6352 struct sk_buff *skb;
6bbe021d
BG		 6353 dma_addr_t addr;
6354 int pkt_size;
6355
6356process_pkt:
6357 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 6358 if (likely(!(dev->features & NETIF_F_RXFCS)))
6359 pkt_size = (status & 0x00003fff) - 4;
6360 else
6361 pkt_size = status & 0x00003fff;
1da177e4 6362
126fa4b9
FR		 6363 /*
6364 * The driver does not support incoming fragmented
6365 * frames. They are seen as a symptom of over-mtu
6366 * sized frames.
6367 */
6368 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 6369 dev->stats.rx_dropped++;
6370 dev->stats.rx_length_errors++;
ce11ff5e 6371 goto release_descriptor;
126fa4b9
FR		 6372 }
6373
6f0333b8
ED		 6374 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6375 tp, pkt_size, addr);
6f0333b8
ED		 6376 if (!skb) {
6377 dev->stats.rx_dropped++;
ce11ff5e 6378 goto release_descriptor;
1da177e4
LT		 6379 }
6380
adea1ac7 6381 rtl8169_rx_csum(skb, status);
1da177e4
LT		 6382 skb_put(skb, pkt_size);
6383 skb->protocol = eth_type_trans(skb, dev);
6384
7a8fc77b
FR		 6385 rtl8169_rx_vlan_tag(desc, skb);
6386
39174291 6387 if (skb->pkt_type == PACKET_MULTICAST)
6388 dev->stats.multicast++;
6389
56de414c 6390 napi_gro_receive(&tp->napi, skb);
1da177e4 6391
8027aa24
JW		 6392 u64_stats_update_begin(&tp->rx_stats.syncp);
6393 tp->rx_stats.packets++;
6394 tp->rx_stats.bytes += pkt_size;
6395 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 6396 }
ce11ff5e 6397release_descriptor:
6398 desc->opts2 = 0;
1d0254dd 6399 rtl8169_mark_to_asic(desc);
1da177e4
LT		 6400 }
6401
6402 count = cur_rx - tp->cur_rx;
6403 tp->cur_rx = cur_rx;
6404
1da177e4
LT		 6405 return count;
6406}
6407
07d3f51f 6408static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 6409{
ebcd5daa 6410 struct rtl8169_private *tp = dev_instance;
05bbe558 6411 u16 status = rtl_get_events(tp);
e782410e 6412 u16 irq_mask = RTL_R16(tp, IntrMask);
1da177e4 6413
e782410e 6414 if (status == 0xffff || !(status & irq_mask))
05bbe558 6415 return IRQ_NONE;
1da177e4 6416
38caff5a
HK		 6417 if (unlikely(status & SYSErr)) {
6418 rtl8169_pcierr_interrupt(tp->dev);
6419 goto out;
6420 }
da78dbff 6421
ee28b30c 6422 if (status & LinkChg && tp->dev->phydev)
38caff5a 6423 phy_mac_interrupt(tp->dev->phydev);
1da177e4 6424
38caff5a
HK		 6425 if (unlikely(status & RxFIFOOver &&
6426 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6427 netif_stop_queue(tp->dev);
6428 /* XXX - Hack alert. See rtl_task(). */
6429 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 6430 }
1da177e4 6431
38caff5a
HK		 6432 if (status & RTL_EVENT_NAPI) {
6433 rtl_irq_disable(tp);
6434 napi_schedule_irqoff(&tp->napi);
6435 }
6436out:
6437 rtl_ack_events(tp, status);
1da177e4 6438
38caff5a 6439 return IRQ_HANDLED;
1da177e4
LT		 6440}
6441
4422bcd4
FR		 6442static void rtl_task(struct work_struct *work)
6443{
da78dbff
FR		 6444 static const struct {
6445 int bitnr;
6446 void (*action)(struct rtl8169_private *);
6447 } rtl_work[] = {
da78dbff 6448 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
da78dbff 6449 };
4422bcd4
FR		 6450 struct rtl8169_private *tp =
6451 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 6452 struct net_device *dev = tp->dev;
6453 int i;
6454
6455 rtl_lock_work(tp);
6456
6c4a70c5
FR		 6457 if (!netif_running(dev) ||
6458 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 6459 goto out_unlock;
6460
6461 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6462 bool pending;
6463
da78dbff 6464 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 6465 if (pending)
6466 rtl_work[i].action(tp);
6467 }
4422bcd4 6468
da78dbff
FR		 6469out_unlock:
6470 rtl_unlock_work(tp);
4422bcd4
FR		 6471}
6472
bea3348e 6473static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 6474{
bea3348e
SH		 6475 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6476 struct net_device *dev = tp->dev;
6b839b6c 6477 int work_done;
da78dbff 6478
6b839b6c 6479 work_done = rtl_rx(dev, tp, (u32) budget);
da78dbff 6480
5317d5c6 6481 rtl_tx(dev, tp, budget);
1da177e4 6482
bea3348e 6483 if (work_done < budget) {
6ad20165 6484 napi_complete_done(napi, work_done);
fe716f8a 6485 rtl_irq_enable(tp);
1da177e4
LT		 6486 }
6487
bea3348e 6488 return work_done;
1da177e4 6489}
1da177e4 6490
1ef7286e 6491static void rtl8169_rx_missed(struct net_device *dev)
523a6094
FR		 6492{
6493 struct rtl8169_private *tp = netdev_priv(dev);
6494
6495 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6496 return;
6497
1ef7286e
AS		 6498 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6499 RTL_W32(tp, RxMissed, 0);
523a6094
FR		 6500}
6501
f1e911d5
HK		 6502static void r8169_phylink_handler(struct net_device *ndev)
6503{
6504 struct rtl8169_private *tp = netdev_priv(ndev);
6505
6506 if (netif_carrier_ok(ndev)) {
6507 rtl_link_chg_patch(tp);
6508 pm_request_resume(&tp->pci_dev->dev);
6509 } else {
6510 pm_runtime_idle(&tp->pci_dev->dev);
6511 }
6512
6513 if (net_ratelimit())
6514 phy_print_status(ndev->phydev);
6515}
6516
6517static int r8169_phy_connect(struct rtl8169_private *tp)
6518{
6519 struct phy_device *phydev = mdiobus_get_phy(tp->mii_bus, 0);
6520 phy_interface_t phy_mode;
6521 int ret;
6522
f7ffa9ae 6523 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
f1e911d5
HK		 6524 PHY_INTERFACE_MODE_MII;
6525
6526 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6527 phy_mode);
6528 if (ret)
6529 return ret;
6530
f7ffa9ae 6531 if (!tp->supports_gmii)
f1e911d5
HK		 6532 phy_set_max_speed(phydev, SPEED_100);
6533
6534 /* Ensure to advertise everything, incl. pause */
3c1bcc86 6535 linkmode_copy(phydev->advertising, phydev->supported);
f1e911d5
HK		 6536
6537 phy_attached_info(phydev);
6538
6539 return 0;
6540}
6541
1da177e4
LT		 6542static void rtl8169_down(struct net_device *dev)
6543{
6544 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 6545
f1e911d5
HK		 6546 phy_stop(dev->phydev);
6547
93dd79e8 6548 napi_disable(&tp->napi);
da78dbff 6549 netif_stop_queue(dev);
1da177e4 6550
92fc43b4 6551 rtl8169_hw_reset(tp);
323bb685
SG		 6552 /*
6553 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 6554 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6555 * and napi is disabled (rtl8169_poll).
323bb685 6556 */
1ef7286e 6557 rtl8169_rx_missed(dev);
1da177e4 6558
1da177e4 6559 /* Give a racing hard_start_xmit a few cycles to complete. */
16f11500 6560 synchronize_rcu();
1da177e4 6561
1da177e4
LT		 6562 rtl8169_tx_clear(tp);
6563
6564 rtl8169_rx_clear(tp);
065c27c1 6565
6566 rtl_pll_power_down(tp);
1da177e4
LT		 6567}
6568
6569static int rtl8169_close(struct net_device *dev)
6570{
6571 struct rtl8169_private *tp = netdev_priv(dev);
6572 struct pci_dev *pdev = tp->pci_dev;
6573
e1759441
RW		 6574 pm_runtime_get_sync(&pdev->dev);
6575
cecb5fd7 6576 /* Update counters before going down */
e71c9ce2 6577 rtl8169_update_counters(tp);
355423d0 6578
da78dbff 6579 rtl_lock_work(tp);
6ad56901
KHF		 6580 /* Clear all task flags */
6581 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
da78dbff 6582
1da177e4 6583 rtl8169_down(dev);
da78dbff 6584 rtl_unlock_work(tp);
1da177e4 6585
4ea72445
L		 6586 cancel_work_sync(&tp->wk.work);
6587
f1e911d5
HK		 6588 phy_disconnect(dev->phydev);
6589
ebcd5daa 6590 pci_free_irq(pdev, 0, tp);
1da177e4 6591
82553bb6
SG		 6592 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6593 tp->RxPhyAddr);
6594 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6595 tp->TxPhyAddr);
1da177e4
LT		 6596 tp->TxDescArray = NULL;
6597 tp->RxDescArray = NULL;
6598
e1759441
RW		 6599 pm_runtime_put_sync(&pdev->dev);
6600
1da177e4
LT		 6601 return 0;
6602}
6603
dc1c00ce
FR		 6604#ifdef CONFIG_NET_POLL_CONTROLLER
6605static void rtl8169_netpoll(struct net_device *dev)
6606{
6607 struct rtl8169_private *tp = netdev_priv(dev);
6608
6d8b8349 6609 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
dc1c00ce
FR		 6610}
6611#endif
6612
df43ac78
FR		 6613static int rtl_open(struct net_device *dev)
6614{
6615 struct rtl8169_private *tp = netdev_priv(dev);
df43ac78
FR		 6616 struct pci_dev *pdev = tp->pci_dev;
6617 int retval = -ENOMEM;
6618
6619 pm_runtime_get_sync(&pdev->dev);
6620
6621 /*
e75d6606 6622 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 6623 * dma_alloc_coherent provides more.
6624 */
6625 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6626 &tp->TxPhyAddr, GFP_KERNEL);
6627 if (!tp->TxDescArray)
6628 goto err_pm_runtime_put;
6629
6630 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6631 &tp->RxPhyAddr, GFP_KERNEL);
6632 if (!tp->RxDescArray)
6633 goto err_free_tx_0;
6634
b1127e64 6635 retval = rtl8169_init_ring(tp);
df43ac78
FR		 6636 if (retval < 0)
6637 goto err_free_rx_1;
6638
6639 INIT_WORK(&tp->wk.work, rtl_task);
6640
6641 smp_mb();
6642
6643 rtl_request_firmware(tp);
6644
ebcd5daa 6645 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6c6aa15f 6646 dev->name);
df43ac78
FR		 6647 if (retval < 0)
6648 goto err_release_fw_2;
6649
f1e911d5
HK		 6650 retval = r8169_phy_connect(tp);
6651 if (retval)
6652 goto err_free_irq;
6653
df43ac78
FR		 6654 rtl_lock_work(tp);
6655
6656 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6657
6658 napi_enable(&tp->napi);
6659
6660 rtl8169_init_phy(dev, tp);
6661
df43ac78
FR		 6662 rtl_pll_power_up(tp);
6663
61cb532d 6664 rtl_hw_start(tp);
df43ac78 6665
e71c9ce2 6666 if (!rtl8169_init_counter_offsets(tp))
6e85d5ad
CV		 6667 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6668
f1e911d5 6669 phy_start(dev->phydev);
df43ac78
FR		 6670 netif_start_queue(dev);
6671
6672 rtl_unlock_work(tp);
6673
a92a0849 6674 pm_runtime_put_sync(&pdev->dev);
df43ac78
FR		 6675out:
6676 return retval;
6677
f1e911d5
HK		 6678err_free_irq:
6679 pci_free_irq(pdev, 0, tp);
df43ac78
FR		 6680err_release_fw_2:
6681 rtl_release_firmware(tp);
6682 rtl8169_rx_clear(tp);
6683err_free_rx_1:
6684 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6685 tp->RxPhyAddr);
6686 tp->RxDescArray = NULL;
6687err_free_tx_0:
6688 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6689 tp->TxPhyAddr);
6690 tp->TxDescArray = NULL;
6691err_pm_runtime_put:
6692 pm_runtime_put_noidle(&pdev->dev);
6693 goto out;
6694}
6695
bc1f4470 6696static void
8027aa24 6697rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 6698{
6699 struct rtl8169_private *tp = netdev_priv(dev);
f09cf4b7 6700 struct pci_dev *pdev = tp->pci_dev;
42020320 6701 struct rtl8169_counters *counters = tp->counters;
8027aa24 6702 unsigned int start;
1da177e4 6703
f09cf4b7
CHL		 6704 pm_runtime_get_noresume(&pdev->dev);
6705
6706 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
1ef7286e 6707 rtl8169_rx_missed(dev);
5b0384f4 6708
8027aa24 6709 do {
57a7744e 6710 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
8027aa24
JW		 6711 stats->rx_packets = tp->rx_stats.packets;
6712 stats->rx_bytes = tp->rx_stats.bytes;
57a7744e 6713 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
8027aa24 6714
8027aa24 6715 do {
57a7744e 6716 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
8027aa24
JW		 6717 stats->tx_packets = tp->tx_stats.packets;
6718 stats->tx_bytes = tp->tx_stats.bytes;
57a7744e 6719 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
8027aa24
JW		 6720
6721 stats->rx_dropped = dev->stats.rx_dropped;
6722 stats->tx_dropped = dev->stats.tx_dropped;
6723 stats->rx_length_errors = dev->stats.rx_length_errors;
6724 stats->rx_errors = dev->stats.rx_errors;
6725 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6726 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6727 stats->rx_missed_errors = dev->stats.rx_missed_errors;
d7d2d89d 6728 stats->multicast = dev->stats.multicast;
8027aa24 6729
6e85d5ad
CV		 6730 /*
6731 * Fetch additonal counter values missing in stats collected by driver
6732 * from tally counters.
6733 */
f09cf4b7 6734 if (pm_runtime_active(&pdev->dev))
e71c9ce2 6735 rtl8169_update_counters(tp);
6e85d5ad
CV		 6736
6737 /*
6738 * Subtract values fetched during initalization.
6739 * See rtl8169_init_counter_offsets for a description why we do that.
6740 */
42020320 6741 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6e85d5ad 6742 le64_to_cpu(tp->tc_offset.tx_errors);
42020320 6743 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6e85d5ad 6744 le32_to_cpu(tp->tc_offset.tx_multi_collision);
42020320 6745 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6e85d5ad
CV		 6746 le16_to_cpu(tp->tc_offset.tx_aborted);
6747
f09cf4b7 6748 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 6749}
6750
861ab440 6751static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 6752{
065c27c1 6753 struct rtl8169_private *tp = netdev_priv(dev);
6754
5d06a99f 6755 if (!netif_running(dev))
861ab440 6756 return;
5d06a99f 6757
f1e911d5 6758 phy_stop(dev->phydev);
5d06a99f 6759 netif_device_detach(dev);
da78dbff
FR		 6760
6761 rtl_lock_work(tp);
6762 napi_disable(&tp->napi);
6ad56901
KHF		 6763 /* Clear all task flags */
6764 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6765
da78dbff
FR		 6766 rtl_unlock_work(tp);
6767
6768 rtl_pll_power_down(tp);
861ab440
RW		 6769}
6770
6771#ifdef CONFIG_PM
6772
6773static int rtl8169_suspend(struct device *device)
6774{
0f07bd85 6775 struct net_device *dev = dev_get_drvdata(device);
ac8bd9e1 6776 struct rtl8169_private *tp = netdev_priv(dev);
5d06a99f 6777
861ab440 6778 rtl8169_net_suspend(dev);
ac8bd9e1 6779 clk_disable_unprepare(tp->clk);
1371fa6d 6780
5d06a99f
FR		 6781 return 0;
6782}
6783
e1759441
RW		 6784static void __rtl8169_resume(struct net_device *dev)
6785{
065c27c1 6786 struct rtl8169_private *tp = netdev_priv(dev);
6787
e1759441 6788 netif_device_attach(dev);
065c27c1 6789
6790 rtl_pll_power_up(tp);
92bad850 6791 rtl8169_init_phy(dev, tp);
065c27c1 6792
f1e911d5
HK		 6793 phy_start(tp->dev->phydev);
6794
cff4c162
AS		 6795 rtl_lock_work(tp);
6796 napi_enable(&tp->napi);
6c4a70c5 6797 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 6798 rtl_unlock_work(tp);
da78dbff 6799
98ddf986 6800 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 6801}
6802
861ab440 6803static int rtl8169_resume(struct device *device)
5d06a99f 6804{
0f07bd85 6805 struct net_device *dev = dev_get_drvdata(device);
ac8bd9e1
HG		 6806 struct rtl8169_private *tp = netdev_priv(dev);
6807
6808 clk_prepare_enable(tp->clk);
5d06a99f 6809
e1759441
RW		 6810 if (netif_running(dev))
6811 __rtl8169_resume(dev);
5d06a99f 6812
e1759441
RW		 6813 return 0;
6814}
6815
6816static int rtl8169_runtime_suspend(struct device *device)
6817{
0f07bd85 6818 struct net_device *dev = dev_get_drvdata(device);
e1759441
RW		 6819 struct rtl8169_private *tp = netdev_priv(dev);
6820
07df5bd8 6821 if (!tp->TxDescArray)
e1759441
RW		 6822 return 0;
6823
da78dbff 6824 rtl_lock_work(tp);
e1759441 6825 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 6826 rtl_unlock_work(tp);
e1759441
RW		 6827
6828 rtl8169_net_suspend(dev);
6829
f09cf4b7 6830 /* Update counters before going runtime suspend */
1ef7286e 6831 rtl8169_rx_missed(dev);
e71c9ce2 6832 rtl8169_update_counters(tp);
f09cf4b7 6833
e1759441
RW		 6834 return 0;
6835}
6836
6837static int rtl8169_runtime_resume(struct device *device)
6838{
0f07bd85 6839 struct net_device *dev = dev_get_drvdata(device);
e1759441 6840 struct rtl8169_private *tp = netdev_priv(dev);
f51d4a10 6841 rtl_rar_set(tp, dev->dev_addr);
e1759441
RW		 6842
6843 if (!tp->TxDescArray)
6844 return 0;
6845
da78dbff 6846 rtl_lock_work(tp);
e1759441 6847 __rtl8169_set_wol(tp, tp->saved_wolopts);
da78dbff 6848 rtl_unlock_work(tp);
e1759441
RW		 6849
6850 __rtl8169_resume(dev);
5d06a99f 6851
5d06a99f
FR		 6852 return 0;
6853}
6854
e1759441
RW		 6855static int rtl8169_runtime_idle(struct device *device)
6856{
0f07bd85 6857 struct net_device *dev = dev_get_drvdata(device);
e1759441 6858
a92a0849
HK		 6859 if (!netif_running(dev) || !netif_carrier_ok(dev))
6860 pm_schedule_suspend(device, 10000);
6861
6862 return -EBUSY;
e1759441
RW		 6863}
6864
47145210 6865static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 6866 .suspend = rtl8169_suspend,
6867 .resume = rtl8169_resume,
6868 .freeze = rtl8169_suspend,
6869 .thaw = rtl8169_resume,
6870 .poweroff = rtl8169_suspend,
6871 .restore = rtl8169_resume,
6872 .runtime_suspend = rtl8169_runtime_suspend,
6873 .runtime_resume = rtl8169_runtime_resume,
6874 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 6875};
6876
6877#define RTL8169_PM_OPS (&rtl8169_pm_ops)
6878
6879#else /* !CONFIG_PM */
6880
6881#define RTL8169_PM_OPS NULL
6882
6883#endif /* !CONFIG_PM */
6884
649b3b8c 6885static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6886{
649b3b8c 6887 /* WoL fails with 8168b when the receiver is disabled. */
6888 switch (tp->mac_version) {
6889 case RTL_GIGA_MAC_VER_11:
6890 case RTL_GIGA_MAC_VER_12:
6891 case RTL_GIGA_MAC_VER_17:
6892 pci_clear_master(tp->pci_dev);
6893
1ef7286e 6894 RTL_W8(tp, ChipCmd, CmdRxEnb);
649b3b8c 6895 /* PCI commit */
1ef7286e 6896 RTL_R8(tp, ChipCmd);
649b3b8c 6897 break;
6898 default:
6899 break;
6900 }
6901}
6902
1765f95d
FR		 6903static void rtl_shutdown(struct pci_dev *pdev)
6904{
861ab440 6905 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 6906 struct rtl8169_private *tp = netdev_priv(dev);
861ab440
RW		 6907
6908 rtl8169_net_suspend(dev);
1765f95d 6909
cecb5fd7 6910 /* Restore original MAC address */
cc098dc7
IV		 6911 rtl_rar_set(tp, dev->perm_addr);
6912
92fc43b4 6913 rtl8169_hw_reset(tp);
4bb3f522 6914
861ab440 6915 if (system_state == SYSTEM_POWER_OFF) {
433f9d0d 6916 if (tp->saved_wolopts) {
649b3b8c 6917 rtl_wol_suspend_quirk(tp);
6918 rtl_wol_shutdown_quirk(tp);
ca52efd5 6919 }
6920
861ab440
RW		 6921 pci_wake_from_d3(pdev, true);
6922 pci_set_power_state(pdev, PCI_D3hot);
6923 }
6924}
5d06a99f 6925
baf63293 6926static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 6927{
6928 struct net_device *dev = pci_get_drvdata(pdev);
6929 struct rtl8169_private *tp = netdev_priv(dev);
6930
9dbe7896 6931 if (r8168_check_dash(tp))
e27566ed 6932 rtl8168_driver_stop(tp);
e27566ed 6933
ad1be8d3
DN		 6934 netif_napi_del(&tp->napi);
6935
e27566ed 6936 unregister_netdev(dev);
f1e911d5 6937 mdiobus_unregister(tp->mii_bus);
e27566ed
FR		 6938
6939 rtl_release_firmware(tp);
6940
6941 if (pci_dev_run_wake(pdev))
6942 pm_runtime_get_noresume(&pdev->dev);
6943
6944 /* restore original MAC address */
6945 rtl_rar_set(tp, dev->perm_addr);
e27566ed
FR		 6946}
6947
fa9c385e 6948static const struct net_device_ops rtl_netdev_ops = {
df43ac78 6949 .ndo_open = rtl_open,
fa9c385e
FR		 6950 .ndo_stop = rtl8169_close,
6951 .ndo_get_stats64 = rtl8169_get_stats64,
6952 .ndo_start_xmit = rtl8169_start_xmit,
6953 .ndo_tx_timeout = rtl8169_tx_timeout,
6954 .ndo_validate_addr = eth_validate_addr,
6955 .ndo_change_mtu = rtl8169_change_mtu,
6956 .ndo_fix_features = rtl8169_fix_features,
6957 .ndo_set_features = rtl8169_set_features,
6958 .ndo_set_mac_address = rtl_set_mac_address,
6959 .ndo_do_ioctl = rtl8169_ioctl,
6960 .ndo_set_rx_mode = rtl_set_rx_mode,
6961#ifdef CONFIG_NET_POLL_CONTROLLER
6962 .ndo_poll_controller = rtl8169_netpoll,
6963#endif
6964
6965};
6966
31fa8b18 6967static const struct rtl_cfg_info {
61cb532d 6968 void (*hw_start)(struct rtl8169_private *tp);
559c3c04 6969 u16 irq_mask;
14967f94 6970 unsigned int has_gmii:1;
50970831 6971 const struct rtl_coalesce_info *coalesce_info;
31fa8b18
FR		 6972} rtl_cfg_infos [] = {
6973 [RTL_CFG_0] = {
6974 .hw_start = rtl_hw_start_8169,
559c3c04 6975 .irq_mask = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
14967f94 6976 .has_gmii = 1,
50970831 6977 .coalesce_info = rtl_coalesce_info_8169,
31fa8b18
FR		 6978 },
6979 [RTL_CFG_1] = {
6980 .hw_start = rtl_hw_start_8168,
559c3c04 6981 .irq_mask = LinkChg | RxOverflow,
14967f94 6982 .has_gmii = 1,
50970831 6983 .coalesce_info = rtl_coalesce_info_8168_8136,
31fa8b18
FR		 6984 },
6985 [RTL_CFG_2] = {
6986 .hw_start = rtl_hw_start_8101,
559c3c04 6987 .irq_mask = LinkChg | RxOverflow | RxFIFOOver,
50970831 6988 .coalesce_info = rtl_coalesce_info_8168_8136,
31fa8b18
FR		 6989 }
6990};
6991
6c6aa15f 6992static int rtl_alloc_irq(struct rtl8169_private *tp)
31fa8b18 6993{
6c6aa15f 6994 unsigned int flags;
31fa8b18 6995
d49c88d7 6996 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1ef7286e
AS		 6997 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
6998 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6999 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
6c6aa15f 7000 flags = PCI_IRQ_LEGACY;
d49c88d7 7001 } else {
6c6aa15f 7002 flags = PCI_IRQ_ALL_TYPES;
31fa8b18 7003 }
6c6aa15f
HK		 7004
7005 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
31fa8b18
FR		 7006}
7007
c558386b
HW		 7008DECLARE_RTL_COND(rtl_link_list_ready_cond)
7009{
1ef7286e 7010 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
c558386b
HW		 7011}
7012
7013DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7014{
1ef7286e 7015 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
c558386b
HW		 7016}
7017
f1e911d5
HK		 7018static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
7019{
7020 struct rtl8169_private *tp = mii_bus->priv;
7021
7022 if (phyaddr > 0)
7023 return -ENODEV;
7024
7025 return rtl_readphy(tp, phyreg);
7026}
7027
7028static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
7029 int phyreg, u16 val)
7030{
7031 struct rtl8169_private *tp = mii_bus->priv;
7032
7033 if (phyaddr > 0)
7034 return -ENODEV;
7035
7036 rtl_writephy(tp, phyreg, val);
7037
7038 return 0;
7039}
7040
7041static int r8169_mdio_register(struct rtl8169_private *tp)
7042{
7043 struct pci_dev *pdev = tp->pci_dev;
7044 struct phy_device *phydev;
7045 struct mii_bus *new_bus;
7046 int ret;
7047
7048 new_bus = devm_mdiobus_alloc(&pdev->dev);
7049 if (!new_bus)
7050 return -ENOMEM;
7051
7052 new_bus->name = "r8169";
7053 new_bus->priv = tp;
7054 new_bus->parent = &pdev->dev;
7055 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7056 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7057 PCI_DEVID(pdev->bus->number, pdev->devfn));
7058
7059 new_bus->read = r8169_mdio_read_reg;
7060 new_bus->write = r8169_mdio_write_reg;
7061
7062 ret = mdiobus_register(new_bus);
7063 if (ret)
7064 return ret;
7065
7066 phydev = mdiobus_get_phy(new_bus, 0);
7067 if (!phydev) {
7068 mdiobus_unregister(new_bus);
7069 return -ENODEV;
7070 }
7071
242cd9b5
HK		 7072 /* PHY will be woken up in rtl_open() */
7073 phy_suspend(phydev);
7074
f1e911d5
HK		 7075 tp->mii_bus = new_bus;
7076
7077 return 0;
7078}
7079
baf63293 7080static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b 7081{
c558386b
HW		 7082 u32 data;
7083
7084 tp->ocp_base = OCP_STD_PHY_BASE;
7085
1ef7286e 7086 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
c558386b
HW		 7087
7088 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7089 return;
7090
7091 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7092 return;
7093
1ef7286e 7094 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
c558386b 7095 msleep(1);
1ef7286e 7096 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
c558386b 7097
5f8bcce9 7098 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 7099 data &= ~(1 << 14);
7100 r8168_mac_ocp_write(tp, 0xe8de, data);
7101
7102 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7103 return;
7104
5f8bcce9 7105 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 7106 data |= (1 << 15);
7107 r8168_mac_ocp_write(tp, 0xe8de, data);
7108
7109 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7110 return;
7111}
7112
003609da
CHL		 7113static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7114{
7115 rtl8168ep_stop_cmac(tp);
7116 rtl_hw_init_8168g(tp);
7117}
7118
baf63293 7119static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 7120{
7121 switch (tp->mac_version) {
2a71883c 7122 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
003609da
CHL		 7123 rtl_hw_init_8168g(tp);
7124 break;
2a71883c 7125 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
003609da 7126 rtl_hw_init_8168ep(tp);
c558386b 7127 break;
c558386b
HW		 7128 default:
7129 break;
7130 }
7131}
7132
eb88f5f7
HK		 7133/* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
7134static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
7135{
7136 switch (tp->mac_version) {
7137 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7138 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
7139 return false;
7140 default:
7141 return true;
7142 }
7143}
7144
abe8b2f7
HK		 7145static int rtl_jumbo_max(struct rtl8169_private *tp)
7146{
7147 /* Non-GBit versions don't support jumbo frames */
7148 if (!tp->supports_gmii)
7149 return JUMBO_1K;
7150
7151 switch (tp->mac_version) {
7152 /* RTL8169 */
7153 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7154 return JUMBO_7K;
7155 /* RTL8168b */
7156 case RTL_GIGA_MAC_VER_11:
7157 case RTL_GIGA_MAC_VER_12:
7158 case RTL_GIGA_MAC_VER_17:
7159 return JUMBO_4K;
7160 /* RTL8168c */
7161 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7162 return JUMBO_6K;
7163 default:
7164 return JUMBO_9K;
7165 }
7166}
7167
c2f6f3ee
HG		 7168static void rtl_disable_clk(void *data)
7169{
7170 clk_disable_unprepare(data);
7171}
7172
929a031d 7173static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3b6cf25d
FR		 7174{
7175 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3b6cf25d 7176 struct rtl8169_private *tp;
3b6cf25d 7177 struct net_device *dev;
c8d48d9c 7178 int chipset, region, i;
abe8b2f7 7179 int jumbo_max, rc;
3b6cf25d 7180
4c45d24a
HK		 7181 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7182 if (!dev)
7183 return -ENOMEM;
3b6cf25d
FR		 7184
7185 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 7186 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 7187 tp = netdev_priv(dev);
7188 tp->dev = dev;
7189 tp->pci_dev = pdev;
7190 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
f7ffa9ae 7191 tp->supports_gmii = cfg->has_gmii;
3b6cf25d 7192
c2f6f3ee
HG		 7193 /* Get the *optional* external "ether_clk" used on some boards */
7194 tp->clk = devm_clk_get(&pdev->dev, "ether_clk");
7195 if (IS_ERR(tp->clk)) {
7196 rc = PTR_ERR(tp->clk);
7197 if (rc == -ENOENT) {
7198 /* clk-core allows NULL (for suspend / resume) */
7199 tp->clk = NULL;
7200 } else if (rc == -EPROBE_DEFER) {
7201 return rc;
7202 } else {
7203 dev_err(&pdev->dev, "failed to get clk: %d\n", rc);
7204 return rc;
7205 }
7206 } else {
7207 rc = clk_prepare_enable(tp->clk);
7208 if (rc) {
7209 dev_err(&pdev->dev, "failed to enable clk: %d\n", rc);
7210 return rc;
7211 }
7212
7213 rc = devm_add_action_or_reset(&pdev->dev, rtl_disable_clk,
7214 tp->clk);
7215 if (rc)
7216 return rc;
7217 }
7218
3b6cf25d 7219 /* enable device (incl. PCI PM wakeup and hotplug setup) */
4c45d24a 7220 rc = pcim_enable_device(pdev);
3b6cf25d 7221 if (rc < 0) {
22148df0 7222 dev_err(&pdev->dev, "enable failure\n");
4c45d24a 7223 return rc;
3b6cf25d
FR		 7224 }
7225
4c45d24a 7226 if (pcim_set_mwi(pdev) < 0)
22148df0 7227 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
3b6cf25d 7228
c8d48d9c
HK		 7229 /* use first MMIO region */
7230 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7231 if (region < 0) {
22148df0 7232 dev_err(&pdev->dev, "no MMIO resource found\n");
4c45d24a 7233 return -ENODEV;
3b6cf25d
FR		 7234 }
7235
7236 /* check for weird/broken PCI region reporting */
7237 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
22148df0 7238 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
4c45d24a 7239 return -ENODEV;
3b6cf25d
FR		 7240 }
7241
93a00d4d 7242 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
3b6cf25d 7243 if (rc < 0) {
22148df0 7244 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
4c45d24a 7245 return rc;
3b6cf25d
FR		 7246 }
7247
93a00d4d 7248 tp->mmio_addr = pcim_iomap_table(pdev)[region];
3b6cf25d 7249
3b6cf25d 7250 /* Identify chip attached to board */
b4cc2dcc
HK		 7251 rtl8169_get_mac_version(tp);
7252 if (tp->mac_version == RTL_GIGA_MAC_NONE)
7253 return -ENODEV;
3b6cf25d 7254
e397286b
HK		 7255 if (rtl_tbi_enabled(tp)) {
7256 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7257 return -ENODEV;
7258 }
7259
0ae0974e 7260 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
27896c83 7261
a0456790
HK		 7262 if (sizeof(dma_addr_t) > 4 && (use_dac == 1 || (use_dac == -1 &&
7263 tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
7264 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
27896c83
AB		 7265
7266 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
7267 if (!pci_is_pcie(pdev))
7268 tp->cp_cmd |= PCIDAC;
7269 dev->features |= NETIF_F_HIGHDMA;
7270 } else {
7271 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7272 if (rc < 0) {
22148df0 7273 dev_err(&pdev->dev, "DMA configuration failed\n");
4c45d24a 7274 return rc;
27896c83
AB		 7275 }
7276 }
7277
3b6cf25d
FR		 7278 rtl_init_rxcfg(tp);
7279
de20e12f 7280 rtl8169_irq_mask_and_ack(tp);
3b6cf25d 7281
c558386b
HW		 7282 rtl_hw_initialize(tp);
7283
3b6cf25d
FR		 7284 rtl_hw_reset(tp);
7285
3b6cf25d
FR		 7286 pci_set_master(pdev);
7287
3b6cf25d 7288 rtl_init_mdio_ops(tp);
3b6cf25d
FR		 7289 rtl_init_jumbo_ops(tp);
7290
3b6cf25d 7291 chipset = tp->mac_version;
3b6cf25d 7292
6c6aa15f
HK		 7293 rc = rtl_alloc_irq(tp);
7294 if (rc < 0) {
22148df0 7295 dev_err(&pdev->dev, "Can't allocate interrupt\n");
6c6aa15f
HK		 7296 return rc;
7297 }
3b6cf25d 7298
18041b52 7299 tp->saved_wolopts = __rtl8169_get_wol(tp);
7edf6d31 7300
3b6cf25d 7301 mutex_init(&tp->wk.mutex);
340fea3d
KM		 7302 u64_stats_init(&tp->rx_stats.syncp);
7303 u64_stats_init(&tp->tx_stats.syncp);
3b6cf25d
FR		 7304
7305 /* Get MAC address */
b2d43e6e 7306 switch (tp->mac_version) {
353af85e 7307 u8 mac_addr[ETH_ALEN] __aligned(4);
b2d43e6e
HK		 7308 case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7309 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
05b9687b 7310 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
353af85e 7311 *(u16 *)&mac_addr[4] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
6e1d0b89 7312
353af85e
HK		 7313 if (is_valid_ether_addr(mac_addr))
7314 rtl_rar_set(tp, mac_addr);
b2d43e6e
HK		 7315 break;
7316 default:
7317 break;
6e1d0b89 7318 }
3b6cf25d 7319 for (i = 0; i < ETH_ALEN; i++)
1ef7286e 7320 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
3b6cf25d 7321
7ad24ea4 7322 dev->ethtool_ops = &rtl8169_ethtool_ops;
3b6cf25d 7323
37621493 7324 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
3b6cf25d
FR		 7325
7326 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7327 * properly for all devices */
7328 dev->features |= NETIF_F_RXCSUM |
f646968f 7329 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7330
7331 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
f646968f
PM		 7332 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7333 NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7334 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7335 NETIF_F_HIGHDMA;
2d0ec544 7336 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
3b6cf25d 7337
929a031d 7338 tp->cp_cmd |= RxChkSum | RxVlan;
7339
7340 /*
7341 * Pretend we are using VLANs; This bypasses a nasty bug where
7342 * Interrupts stop flowing on high load on 8110SCd controllers.
7343 */
3b6cf25d 7344 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
929a031d 7345 /* Disallow toggling */
f646968f 7346 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d 7347
eb88f5f7 7348 if (rtl_chip_supports_csum_v2(tp)) {
5888d3fc 7349 tp->tso_csum = rtl8169_tso_csum_v2;
e974604b 7350 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
eb88f5f7
HK		 7351 } else {
7352 tp->tso_csum = rtl8169_tso_csum_v1;
a4328ddb 7353 }
5888d3fc 7354
3b6cf25d
FR		 7355 dev->hw_features |= NETIF_F_RXALL;
7356 dev->hw_features |= NETIF_F_RXFCS;
7357
c7315a95
JW		 7358 /* MTU range: 60 - hw-specific max */
7359 dev->min_mtu = ETH_ZLEN;
abe8b2f7
HK		 7360 jumbo_max = rtl_jumbo_max(tp);
7361 dev->max_mtu = jumbo_max;
c7315a95 7362
3b6cf25d 7363 tp->hw_start = cfg->hw_start;
559c3c04 7364 tp->irq_mask = RTL_EVENT_NAPI | cfg->irq_mask;
50970831 7365 tp->coalesce_info = cfg->coalesce_info;
3b6cf25d 7366
3b6cf25d
FR		 7367 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7368
4c45d24a
HK		 7369 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7370 &tp->counters_phys_addr,
7371 GFP_KERNEL);
4cf964af
HK		 7372 if (!tp->counters)
7373 return -ENOMEM;
42020320 7374
19c9ea36
HK		 7375 pci_set_drvdata(pdev, dev);
7376
f1e911d5
HK		 7377 rc = r8169_mdio_register(tp);
7378 if (rc)
4cf964af 7379 return rc;
3b6cf25d 7380
07df5bd8
HK		 7381 /* chip gets powered up in rtl_open() */
7382 rtl_pll_power_down(tp);
7383
f1e911d5
HK		 7384 rc = register_netdev(dev);
7385 if (rc)
7386 goto err_mdio_unregister;
7387
55d2ad7b 7388 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
2d6c5a61 7389 rtl_chip_infos[chipset].name, dev->dev_addr,
55d2ad7b 7390 (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
29274991 7391 pci_irq_vector(pdev, 0));
abe8b2f7
HK		 7392
7393 if (jumbo_max > JUMBO_1K)
7394 netif_info(tp, probe, dev,
7395 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7396 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7397 "ok" : "ko");
3b6cf25d 7398
9dbe7896 7399 if (r8168_check_dash(tp))
3b6cf25d 7400 rtl8168_driver_start(tp);
3b6cf25d 7401
a92a0849
HK		 7402 if (pci_dev_run_wake(pdev))
7403 pm_runtime_put_sync(&pdev->dev);
7404
4c45d24a 7405 return 0;
f1e911d5
HK		 7406
7407err_mdio_unregister:
7408 mdiobus_unregister(tp->mii_bus);
7409 return rc;
3b6cf25d
FR		 7410}
7411
1da177e4
LT		 7412static struct pci_driver rtl8169_pci_driver = {
7413 .name = MODULENAME,
7414 .id_table = rtl8169_pci_tbl,
3b6cf25d 7415 .probe = rtl_init_one,
baf63293 7416 .remove = rtl_remove_one,
1765f95d 7417 .shutdown = rtl_shutdown,
861ab440 7418 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 7419};
7420
3eeb7da9 7421module_pci_driver(rtl8169_pci_driver);
Linux 6.x block layer and io_uring tree(s)