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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[linux-2.6-block.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic_hw.c
CommitLineData
af19b491 1/*
40839129
SV		 2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2010 QLogic Corporation
af19b491 4 *
40839129 5 * See LICENSE.qlcnic for copyright and licensing details.
af19b491
AKS		 6 */
7
8#include "qlcnic.h"
15087c2b 9#include "qlcnic_hdr.h"
af19b491 10
5a0e3ad6 11#include <linux/slab.h>
af19b491 12#include <net/ip.h>
18f2f616 13#include <linux/bitops.h>
af19b491
AKS		 14
15#define MASK(n) ((1ULL<<(n))-1)
16#define OCM_WIN_P3P(addr) (addr & 0xffc0000)
17
18#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
19
20#define CRB_BLK(off) ((off >> 20) & 0x3f)
21#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
22#define CRB_WINDOW_2M (0x130060)
23#define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
24#define CRB_INDIRECT_2M (0x1e0000UL)
25
15087c2b
SC		 26struct qlcnic_ms_reg_ctrl {
27 u32 ocm_window;
28 u32 control;
29 u32 hi;
30 u32 low;
31 u32 rd[4];
32 u32 wd[4];
33 u64 off;
34};
af19b491
AKS		 35
36#ifndef readq
37static inline u64 readq(void __iomem *addr)
38{
39 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
40}
41#endif
42
43#ifndef writeq
44static inline void writeq(u64 val, void __iomem *addr)
45{
46 writel(((u32) (val)), (addr));
47 writel(((u32) (val >> 32)), (addr + 4));
48}
49#endif
50
c477ebd8 51static struct crb_128M_2M_block_map
af19b491
AKS		 52crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
53 {{{0, 0, 0, 0} } }, /* 0: PCI */
54 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
55 {1, 0x0110000, 0x0120000, 0x130000},
56 {1, 0x0120000, 0x0122000, 0x124000},
57 {1, 0x0130000, 0x0132000, 0x126000},
58 {1, 0x0140000, 0x0142000, 0x128000},
59 {1, 0x0150000, 0x0152000, 0x12a000},
60 {1, 0x0160000, 0x0170000, 0x110000},
61 {1, 0x0170000, 0x0172000, 0x12e000},
62 {0, 0x0000000, 0x0000000, 0x000000},
63 {0, 0x0000000, 0x0000000, 0x000000},
64 {0, 0x0000000, 0x0000000, 0x000000},
65 {0, 0x0000000, 0x0000000, 0x000000},
66 {0, 0x0000000, 0x0000000, 0x000000},
67 {0, 0x0000000, 0x0000000, 0x000000},
68 {1, 0x01e0000, 0x01e0800, 0x122000},
69 {0, 0x0000000, 0x0000000, 0x000000} } },
70 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
71 {{{0, 0, 0, 0} } }, /* 3: */
72 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
73 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
74 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
75 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
76 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
77 {0, 0x0000000, 0x0000000, 0x000000},
78 {0, 0x0000000, 0x0000000, 0x000000},
79 {0, 0x0000000, 0x0000000, 0x000000},
80 {0, 0x0000000, 0x0000000, 0x000000},
81 {0, 0x0000000, 0x0000000, 0x000000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {1, 0x08f0000, 0x08f2000, 0x172000} } },
92 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {0, 0x0000000, 0x0000000, 0x000000},
95 {0, 0x0000000, 0x0000000, 0x000000},
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {1, 0x09f0000, 0x09f2000, 0x176000} } },
108 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {0, 0x0000000, 0x0000000, 0x000000},
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
124 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
140 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
141 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
142 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
143 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
144 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
145 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
146 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
147 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
148 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
149 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
150 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
151 {{{0, 0, 0, 0} } }, /* 23: */
152 {{{0, 0, 0, 0} } }, /* 24: */
153 {{{0, 0, 0, 0} } }, /* 25: */
154 {{{0, 0, 0, 0} } }, /* 26: */
155 {{{0, 0, 0, 0} } }, /* 27: */
156 {{{0, 0, 0, 0} } }, /* 28: */
157 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
158 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
159 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
160 {{{0} } }, /* 32: PCI */
161 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
162 {1, 0x2110000, 0x2120000, 0x130000},
163 {1, 0x2120000, 0x2122000, 0x124000},
164 {1, 0x2130000, 0x2132000, 0x126000},
165 {1, 0x2140000, 0x2142000, 0x128000},
166 {1, 0x2150000, 0x2152000, 0x12a000},
167 {1, 0x2160000, 0x2170000, 0x110000},
168 {1, 0x2170000, 0x2172000, 0x12e000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000} } },
177 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
178 {{{0} } }, /* 35: */
179 {{{0} } }, /* 36: */
180 {{{0} } }, /* 37: */
181 {{{0} } }, /* 38: */
182 {{{0} } }, /* 39: */
183 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
184 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
185 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
186 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
187 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
188 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
189 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
190 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
191 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
192 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
193 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
194 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
195 {{{0} } }, /* 52: */
196 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
197 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
198 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
199 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
200 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
201 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
202 {{{0} } }, /* 59: I2C0 */
203 {{{0} } }, /* 60: I2C1 */
204 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
205 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
206 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
207};
208
209/*
210 * top 12 bits of crb internal address (hub, agent)
211 */
212static const unsigned crb_hub_agt[64] = {
213 0,
214 QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
215 QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
216 QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
217 0,
218 QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
219 QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
220 QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
221 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
222 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
223 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
224 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
225 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
226 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
227 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
228 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
229 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
230 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
231 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
232 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
233 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
234 QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
235 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
236 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
237 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
238 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
239 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
240 0,
241 QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
242 QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
243 0,
244 QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
245 0,
246 QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
247 QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
248 0,
249 0,
250 0,
251 0,
252 0,
253 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
254 0,
255 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
256 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
257 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
258 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
259 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
260 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
261 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
262 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
263 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
264 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
265 0,
266 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
267 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
268 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
269 QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
270 0,
271 QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
272 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
273 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
274 0,
275 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
276 0,
277};
278
15087c2b
SC		 279static const u32 msi_tgt_status[8] = {
280 ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1,
281 ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3,
282 ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5,
283 ISR_INT_TARGET_STATUS_F6, ISR_INT_TARGET_STATUS_F7
284};
285
af19b491
AKS		 286/* PCI Windowing for DDR regions. */
287
288#define QLCNIC_PCIE_SEM_TIMEOUT 10000
289
15087c2b
SC		 290static void qlcnic_read_window_reg(u32 addr, void __iomem *bar0, u32 *data)
291{
292 u32 dest;
293 void __iomem *val;
294
295 dest = addr & 0xFFFF0000;
296 val = bar0 + QLCNIC_FW_DUMP_REG1;
297 writel(dest, val);
298 readl(val);
299 val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
300 *data = readl(val);
301}
302
303static void qlcnic_write_window_reg(u32 addr, void __iomem *bar0, u32 data)
304{
305 u32 dest;
306 void __iomem *val;
307
308 dest = addr & 0xFFFF0000;
309 val = bar0 + QLCNIC_FW_DUMP_REG1;
310 writel(dest, val);
311 readl(val);
312 val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
313 writel(data, val);
314 readl(val);
315}
316
af19b491
AKS		 317int
318qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
319{
320 int done = 0, timeout = 0;
321
322 while (!done) {
323 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)));
324 if (done == 1)
325 break;
65b5b420
AKS		 326 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) {
327 dev_err(&adapter->pdev->dev,
091754a1
SC		 328 "Failed to acquire sem=%d lock; holdby=%d\n",
329 sem, id_reg ? QLCRD32(adapter, id_reg) : -1);
af19b491 330 return -EIO;
65b5b420 331 }
af19b491
AKS		 332 msleep(1);
333 }
334
335 if (id_reg)
336 QLCWR32(adapter, id_reg, adapter->portnum);
337
338 return 0;
339}
340
341void
342qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
343{
344 QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
345}
346
15087c2b
SC		 347static int qlcnic_ind_rd(struct qlcnic_adapter *adapter, u32 addr)
348{
349 u32 data;
350
351 if (qlcnic_82xx_check(adapter))
352 qlcnic_read_window_reg(addr, adapter->ahw->pci_base0, &data);
353 else
354 return -EIO;
355 return data;
356}
357
358static void qlcnic_ind_wr(struct qlcnic_adapter *adapter, u32 addr, u32 data)
359{
360 if (qlcnic_82xx_check(adapter))
361 qlcnic_write_window_reg(addr, adapter->ahw->pci_base0, data);
362}
363
af19b491
AKS		 364static int
365qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
366 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
367{
368 u32 i, producer, consumer;
369 struct qlcnic_cmd_buffer *pbuf;
370 struct cmd_desc_type0 *cmd_desc;
371 struct qlcnic_host_tx_ring *tx_ring;
372
373 i = 0;
374
8a15ad1f 375 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
af19b491
AKS		 376 return -EIO;
377
378 tx_ring = adapter->tx_ring;
379 __netif_tx_lock_bh(tx_ring->txq);
380
381 producer = tx_ring->producer;
382 consumer = tx_ring->sw_consumer;
383
384 if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
385 netif_tx_stop_queue(tx_ring->txq);
ef71ff83
RB		 386 smp_mb();
387 if (qlcnic_tx_avail(tx_ring) > nr_desc) {
388 if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH)
389 netif_tx_wake_queue(tx_ring->txq);
390 } else {
391 adapter->stats.xmit_off++;
392 __netif_tx_unlock_bh(tx_ring->txq);
393 return -EBUSY;
394 }
af19b491
AKS		 395 }
396
397 do {
398 cmd_desc = &cmd_desc_arr[i];
399
400 pbuf = &tx_ring->cmd_buf_arr[producer];
401 pbuf->skb = NULL;
402 pbuf->frag_count = 0;
403
404 memcpy(&tx_ring->desc_head[producer],
405 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
406
407 producer = get_next_index(producer, tx_ring->num_desc);
408 i++;
409
410 } while (i != nr_desc);
411
412 tx_ring->producer = producer;
413
5ad6ff9d 414 qlcnic_update_cmd_producer(tx_ring);
af19b491
AKS		 415
416 __netif_tx_unlock_bh(tx_ring->txq);
417
418 return 0;
419}
420
421static int
422qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
7e56cac4 423 __le16 vlan_id, unsigned op)
af19b491
AKS		 424{
425 struct qlcnic_nic_req req;
426 struct qlcnic_mac_req *mac_req;
7e56cac4 427 struct qlcnic_vlan_req *vlan_req;
af19b491
AKS		 428 u64 word;
429
430 memset(&req, 0, sizeof(struct qlcnic_nic_req));
431 req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
432
433 word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
434 req.req_hdr = cpu_to_le64(word);
435
436 mac_req = (struct qlcnic_mac_req *)&req.words[0];
437 mac_req->op = op;
438 memcpy(mac_req->mac_addr, addr, 6);
439
7e56cac4
SC		 440 vlan_req = (struct qlcnic_vlan_req *)&req.words[1];
441 vlan_req->vlan_id = vlan_id;
03c5d770 442
af19b491
AKS		 443 return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
444}
445
215faf9c 446static int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, const u8 *addr)
af19b491
AKS		 447{
448 struct list_head *head;
449 struct qlcnic_mac_list_s *cur;
450
451 /* look up if already exists */
9ab17b39 452 list_for_each(head, &adapter->mac_list) {
af19b491 453 cur = list_entry(head, struct qlcnic_mac_list_s, list);
9ab17b39 454 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
af19b491 455 return 0;
af19b491
AKS		 456 }
457
458 cur = kzalloc(sizeof(struct qlcnic_mac_list_s), GFP_ATOMIC);
459 if (cur == NULL) {
460 dev_err(&adapter->netdev->dev,
461 "failed to add mac address filter\n");
462 return -ENOMEM;
463 }
464 memcpy(cur->mac_addr, addr, ETH_ALEN);
af19b491 465
42f65cba 466 if (qlcnic_sre_macaddr_change(adapter,
03c5d770 467 cur->mac_addr, 0, QLCNIC_MAC_ADD)) {
42f65cba
AKS		 468 kfree(cur);
469 return -EIO;
470 }
471
472 list_add_tail(&cur->list, &adapter->mac_list);
473 return 0;
af19b491
AKS		 474}
475
476void qlcnic_set_multi(struct net_device *netdev)
477{
478 struct qlcnic_adapter *adapter = netdev_priv(netdev);
22bedad3 479 struct netdev_hw_addr *ha;
215faf9c
JP		 480 static const u8 bcast_addr[ETH_ALEN] = {
481 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
482 };
af19b491 483 u32 mode = VPORT_MISS_MODE_DROP;
af19b491 484
8a15ad1f 485 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
a55cb185
AKS		 486 return;
487
9ab17b39
SC		 488 qlcnic_nic_add_mac(adapter, adapter->mac_addr);
489 qlcnic_nic_add_mac(adapter, bcast_addr);
af19b491
AKS		 490
491 if (netdev->flags & IFF_PROMISC) {
ee07c1a7
RB		 492 if (!(adapter->flags & QLCNIC_PROMISC_DISABLED))
493 mode = VPORT_MISS_MODE_ACCEPT_ALL;
af19b491
AKS		 494 goto send_fw_cmd;
495 }
496
497 if ((netdev->flags & IFF_ALLMULTI) ||
79788450 498 (netdev_mc_count(netdev) > adapter->ahw->max_mc_count)) {
af19b491
AKS		 499 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
500 goto send_fw_cmd;
501 }
502
4cd24eaf 503 if (!netdev_mc_empty(netdev)) {
22bedad3
JP		 504 netdev_for_each_mc_addr(ha, netdev) {
505 qlcnic_nic_add_mac(adapter, ha->addr);
af19b491
AKS		 506 }
507 }
508
509send_fw_cmd:
e5dcf6dc
SC		 510 if (mode == VPORT_MISS_MODE_ACCEPT_ALL) {
511 qlcnic_alloc_lb_filters_mem(adapter);
512 adapter->mac_learn = 1;
513 } else {
514 adapter->mac_learn = 0;
515 }
516
af19b491 517 qlcnic_nic_set_promisc(adapter, mode);
af19b491
AKS		 518}
519
520int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
521{
522 struct qlcnic_nic_req req;
523 u64 word;
524
525 memset(&req, 0, sizeof(struct qlcnic_nic_req));
526
527 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
528
b1fc6d3c 529 word = QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE |
af19b491
AKS		 530 ((u64)adapter->portnum << 16);
531 req.req_hdr = cpu_to_le64(word);
532
533 req.words[0] = cpu_to_le64(mode);
534
535 return qlcnic_send_cmd_descs(adapter,
536 (struct cmd_desc_type0 *)&req, 1);
537}
538
539void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
540{
541 struct qlcnic_mac_list_s *cur;
542 struct list_head *head = &adapter->mac_list;
543
544 while (!list_empty(head)) {
545 cur = list_entry(head->next, struct qlcnic_mac_list_s, list);
546 qlcnic_sre_macaddr_change(adapter,
03c5d770 547 cur->mac_addr, 0, QLCNIC_MAC_DEL);
af19b491
AKS		 548 list_del(&cur->list);
549 kfree(cur);
550 }
551}
552
b5e5492c
AKS		 553void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter)
554{
555 struct qlcnic_filter *tmp_fil;
556 struct hlist_node *tmp_hnode, *n;
557 struct hlist_head *head;
558 int i;
559
560 for (i = 0; i < adapter->fhash.fmax; i++) {
561 head = &(adapter->fhash.fhead[i]);
562
563 hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode)
564 {
565 if (jiffies >
566 (QLCNIC_FILTER_AGE * HZ + tmp_fil->ftime)) {
567 qlcnic_sre_macaddr_change(adapter,
03c5d770
AKS		 568 tmp_fil->faddr, tmp_fil->vlan_id,
569 tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
570 QLCNIC_MAC_DEL);
b5e5492c
AKS		 571 spin_lock_bh(&adapter->mac_learn_lock);
572 adapter->fhash.fnum--;
573 hlist_del(&tmp_fil->fnode);
574 spin_unlock_bh(&adapter->mac_learn_lock);
575 kfree(tmp_fil);
576 }
577 }
578 }
579}
580
581void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter)
582{
583 struct qlcnic_filter *tmp_fil;
584 struct hlist_node *tmp_hnode, *n;
585 struct hlist_head *head;
586 int i;
587
588 for (i = 0; i < adapter->fhash.fmax; i++) {
589 head = &(adapter->fhash.fhead[i]);
590
591 hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode) {
03c5d770
AKS		 592 qlcnic_sre_macaddr_change(adapter, tmp_fil->faddr,
593 tmp_fil->vlan_id, tmp_fil->vlan_id ?
594 QLCNIC_MAC_VLAN_DEL : QLCNIC_MAC_DEL);
b5e5492c
AKS		 595 spin_lock_bh(&adapter->mac_learn_lock);
596 adapter->fhash.fnum--;
597 hlist_del(&tmp_fil->fnode);
598 spin_unlock_bh(&adapter->mac_learn_lock);
599 kfree(tmp_fil);
600 }
601 }
602}
603
6d973cb1 604static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u8 flag)
22c8c934
SC		 605{
606 struct qlcnic_nic_req req;
607 int rv;
608
609 memset(&req, 0, sizeof(struct qlcnic_nic_req));
610
611 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
612 req.req_hdr = cpu_to_le64(QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
613 ((u64) adapter->portnum << 16) | ((u64) 0x1 << 32));
614
615 req.words[0] = cpu_to_le64(flag);
616
617 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
618 if (rv != 0)
619 dev_err(&adapter->pdev->dev, "%sting loopback mode failed\n",
620 flag ? "Set" : "Reset");
621 return rv;
622}
623
624int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
625{
626 if (qlcnic_set_fw_loopback(adapter, mode))
627 return -EIO;
628
629 if (qlcnic_nic_set_promisc(adapter, VPORT_MISS_MODE_ACCEPT_ALL)) {
ad567b8f 630 qlcnic_set_fw_loopback(adapter, 0);
22c8c934
SC		 631 return -EIO;
632 }
633
634 msleep(1000);
635 return 0;
636}
637
638void qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter)
639{
640 int mode = VPORT_MISS_MODE_DROP;
641 struct net_device *netdev = adapter->netdev;
642
643 qlcnic_set_fw_loopback(adapter, 0);
644
645 if (netdev->flags & IFF_PROMISC)
646 mode = VPORT_MISS_MODE_ACCEPT_ALL;
647 else if (netdev->flags & IFF_ALLMULTI)
648 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
649
650 qlcnic_nic_set_promisc(adapter, mode);
651 msleep(1000);
652}
653
af19b491
AKS		 654/*
655 * Send the interrupt coalescing parameter set by ethtool to the card.
656 */
657int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter)
658{
659 struct qlcnic_nic_req req;
8816d009 660 int rv;
af19b491
AKS		 661
662 memset(&req, 0, sizeof(struct qlcnic_nic_req));
663
664 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
665
8816d009
AC		 666 req.req_hdr = cpu_to_le64(QLCNIC_CONFIG_INTR_COALESCE |
667 ((u64) adapter->portnum << 16));
af19b491 668
8816d009
AC		 669 req.words[0] = cpu_to_le64(((u64) adapter->ahw->coal.flag) << 32);
670 req.words[2] = cpu_to_le64(adapter->ahw->coal.rx_packets |
671 ((u64) adapter->ahw->coal.rx_time_us) << 16);
672 req.words[5] = cpu_to_le64(adapter->ahw->coal.timer_out |
673 ((u64) adapter->ahw->coal.type) << 32 |
674 ((u64) adapter->ahw->coal.sts_ring_mask) << 40);
af19b491
AKS		 675 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
676 if (rv != 0)
677 dev_err(&adapter->netdev->dev,
678 "Could not send interrupt coalescing parameters\n");
af19b491
AKS		 679 return rv;
680}
681
682int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
683{
684 struct qlcnic_nic_req req;
685 u64 word;
686 int rv;
687
b56421d0
RB		 688 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
689 return 0;
690
af19b491
AKS		 691 memset(&req, 0, sizeof(struct qlcnic_nic_req));
692
693 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
694
695 word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
696 req.req_hdr = cpu_to_le64(word);
697
698 req.words[0] = cpu_to_le64(enable);
699
700 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
701 if (rv != 0)
702 dev_err(&adapter->netdev->dev,
703 "Could not send configure hw lro request\n");
704
af19b491
AKS		 705 return rv;
706}
707
2e9d722d 708int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable)
af19b491
AKS		 709{
710 struct qlcnic_nic_req req;
711 u64 word;
712 int rv;
713
714 if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
715 return 0;
716
717 memset(&req, 0, sizeof(struct qlcnic_nic_req));
718
719 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
720
721 word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
722 ((u64)adapter->portnum << 16);
723 req.req_hdr = cpu_to_le64(word);
724
725 req.words[0] = cpu_to_le64(enable);
726
727 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
728 if (rv != 0)
729 dev_err(&adapter->netdev->dev,
730 "Could not send configure bridge mode request\n");
731
732 adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
733
734 return rv;
735}
736
737
738#define RSS_HASHTYPE_IP_TCP 0x3
739
740int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
741{
742 struct qlcnic_nic_req req;
743 u64 word;
744 int i, rv;
745
215faf9c
JP		 746 static const u64 key[] = {
747 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
748 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
749 0x255b0ec26d5a56daULL
750 };
af19b491
AKS		 751
752 memset(&req, 0, sizeof(struct qlcnic_nic_req));
753 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
754
755 word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
756 req.req_hdr = cpu_to_le64(word);
757
758 /*
759 * RSS request:
760 * bits 3-0: hash_method
761 * 5-4: hash_type_ipv4
762 * 7-6: hash_type_ipv6
763 * 8: enable
764 * 9: use indirection table
765 * 47-10: reserved
766 * 63-48: indirection table mask
767 */
768 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
769 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
770 ((u64)(enable & 0x1) << 8) |
771 ((0x7ULL) << 48);
772 req.words[0] = cpu_to_le64(word);
773 for (i = 0; i < 5; i++)
774 req.words[i+1] = cpu_to_le64(key[i]);
775
776 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
777 if (rv != 0)
778 dev_err(&adapter->netdev->dev, "could not configure RSS\n");
779
780 return rv;
781}
782
b501595c 783int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, int cmd)
af19b491
AKS		 784{
785 struct qlcnic_nic_req req;
b501595c 786 struct qlcnic_ipaddr *ipa;
af19b491
AKS		 787 u64 word;
788 int rv;
789
790 memset(&req, 0, sizeof(struct qlcnic_nic_req));
791 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
792
793 word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
794 req.req_hdr = cpu_to_le64(word);
795
796 req.words[0] = cpu_to_le64(cmd);
b501595c
SC		 797 ipa = (struct qlcnic_ipaddr *)&req.words[1];
798 ipa->ipv4 = ip;
af19b491
AKS		 799
800 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
801 if (rv != 0)
802 dev_err(&adapter->netdev->dev,
803 "could not notify %s IP 0x%x reuqest\n",
804 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
805
806 return rv;
807}
808
809int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable)
810{
811 struct qlcnic_nic_req req;
812 u64 word;
813 int rv;
814
815 memset(&req, 0, sizeof(struct qlcnic_nic_req));
816 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
817
818 word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
819 req.req_hdr = cpu_to_le64(word);
820 req.words[0] = cpu_to_le64(enable | (enable << 8));
821
822 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
823 if (rv != 0)
824 dev_err(&adapter->netdev->dev,
825 "could not configure link notification\n");
826
827 return rv;
828}
829
830int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
831{
832 struct qlcnic_nic_req req;
833 u64 word;
834 int rv;
835
b56421d0
RB		 836 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
837 return 0;
838
af19b491
AKS		 839 memset(&req, 0, sizeof(struct qlcnic_nic_req));
840 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
841
842 word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
843 ((u64)adapter->portnum << 16) |
844 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
845
846 req.req_hdr = cpu_to_le64(word);
847
848 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
849 if (rv != 0)
850 dev_err(&adapter->netdev->dev,
851 "could not cleanup lro flows\n");
852
853 return rv;
854}
855
856/*
857 * qlcnic_change_mtu - Change the Maximum Transfer Unit
858 * @returns 0 on success, negative on failure
859 */
860
861int qlcnic_change_mtu(struct net_device *netdev, int mtu)
862{
863 struct qlcnic_adapter *adapter = netdev_priv(netdev);
864 int rc = 0;
865
ff1b1bf8 866 if (mtu < P3P_MIN_MTU || mtu > P3P_MAX_MTU) {
0bd9e6a9 867 dev_err(&adapter->netdev->dev, "%d bytes < mtu < %d bytes"
ff1b1bf8 868 " not supported\n", P3P_MAX_MTU, P3P_MIN_MTU);
af19b491
AKS		 869 return -EINVAL;
870 }
871
872 rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
873
874 if (!rc)
875 netdev->mtu = mtu;
876
877 return rc;
878}
879
135d84a9 880
c8f44aff
MM		 881netdev_features_t qlcnic_fix_features(struct net_device *netdev,
882 netdev_features_t features)
135d84a9
MM		 883{
884 struct qlcnic_adapter *adapter = netdev_priv(netdev);
885
886 if ((adapter->flags & QLCNIC_ESWITCH_ENABLED)) {
c8f44aff 887 netdev_features_t changed = features ^ netdev->features;
135d84a9
MM		 888 features ^= changed & (NETIF_F_ALL_CSUM | NETIF_F_RXCSUM);
889 }
890
891 if (!(features & NETIF_F_RXCSUM))
892 features &= ~NETIF_F_LRO;
893
894 return features;
895}
896
897
c8f44aff 898int qlcnic_set_features(struct net_device *netdev, netdev_features_t features)
135d84a9
MM		 899{
900 struct qlcnic_adapter *adapter = netdev_priv(netdev);
c8f44aff 901 netdev_features_t changed = netdev->features ^ features;
135d84a9
MM		 902 int hw_lro = (features & NETIF_F_LRO) ? QLCNIC_LRO_ENABLED : 0;
903
904 if (!(changed & NETIF_F_LRO))
905 return 0;
906
907 netdev->features = features ^ NETIF_F_LRO;
908
909 if (qlcnic_config_hw_lro(adapter, hw_lro))
910 return -EIO;
911
912 if ((hw_lro == 0) && qlcnic_send_lro_cleanup(adapter))
913 return -EIO;
914
915 return 0;
916}
917
af19b491
AKS		 918/*
919 * Changes the CRB window to the specified window.
920 */
921 /* Returns < 0 if off is not valid,
922 * 1 if window access is needed. 'off' is set to offset from
923 * CRB space in 128M pci map
924 * 0 if no window access is needed. 'off' is set to 2M addr
925 * In: 'off' is offset from base in 128M pci map
926 */
15087c2b
SC		 927static int qlcnic_pci_get_crb_addr_2M(struct qlcnic_hardware_context *ahw,
928 ulong off, void __iomem **addr)
af19b491
AKS		 929{
930 const struct crb_128M_2M_sub_block_map *m;
931
932 if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
933 return -EINVAL;
934
935 off -= QLCNIC_PCI_CRBSPACE;
936
937 /*
938 * Try direct map
939 */
940 m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
941
942 if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
15087c2b 943 *addr = ahw->pci_base0 + m->start_2M +
af19b491
AKS		 944 (off - m->start_128M);
945 return 0;
946 }
947
948 /*
949 * Not in direct map, use crb window
950 */
15087c2b 951 *addr = ahw->pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
af19b491
AKS		 952 return 1;
953}
954
955/*
956 * In: 'off' is offset from CRB space in 128M pci map
957 * Out: 'off' is 2M pci map addr
958 * side effect: lock crb window
959 */
4de57826 960static int
af19b491
AKS		 961qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
962{
963 u32 window;
b1fc6d3c 964 void __iomem *addr = adapter->ahw->pci_base0 + CRB_WINDOW_2M;
af19b491
AKS		 965
966 off -= QLCNIC_PCI_CRBSPACE;
967
968 window = CRB_HI(off);
4de57826
AKS		 969 if (window == 0) {
970 dev_err(&adapter->pdev->dev, "Invalid offset 0x%lx\n", off);
971 return -EIO;
972 }
af19b491 973
af19b491
AKS		 974 writel(window, addr);
975 if (readl(addr) != window) {
976 if (printk_ratelimit())
977 dev_warn(&adapter->pdev->dev,
978 "failed to set CRB window to %d off 0x%lx\n",
979 window, off);
4de57826 980 return -EIO;
af19b491 981 }
4de57826 982 return 0;
af19b491
AKS		 983}
984
985int
986qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off, u32 data)
987{
988 unsigned long flags;
989 int rv;
990 void __iomem *addr = NULL;
991
15087c2b 992 rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr);
af19b491
AKS		 993
994 if (rv == 0) {
995 writel(data, addr);
996 return 0;
997 }
998
999 if (rv > 0) {
1000 /* indirect access */
b1fc6d3c 1001 write_lock_irqsave(&adapter->ahw->crb_lock, flags);
af19b491 1002 crb_win_lock(adapter);
4de57826
AKS		 1003 rv = qlcnic_pci_set_crbwindow_2M(adapter, off);
1004 if (!rv)
1005 writel(data, addr);
af19b491 1006 crb_win_unlock(adapter);
b1fc6d3c 1007 write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
4de57826 1008 return rv;
af19b491
AKS		 1009 }
1010
1011 dev_err(&adapter->pdev->dev,
1012 "%s: invalid offset: 0x%016lx\n", __func__, off);
1013 dump_stack();
1014 return -EIO;
1015}
1016
15087c2b 1017int qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off)
af19b491
AKS		 1018{
1019 unsigned long flags;
1020 int rv;
4de57826 1021 u32 data = -1;
af19b491
AKS		 1022 void __iomem *addr = NULL;
1023
15087c2b 1024 rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr);
af19b491
AKS		 1025
1026 if (rv == 0)
1027 return readl(addr);
1028
1029 if (rv > 0) {
1030 /* indirect access */
b1fc6d3c 1031 write_lock_irqsave(&adapter->ahw->crb_lock, flags);
af19b491 1032 crb_win_lock(adapter);
4de57826
AKS		 1033 if (!qlcnic_pci_set_crbwindow_2M(adapter, off))
1034 data = readl(addr);
af19b491 1035 crb_win_unlock(adapter);
b1fc6d3c 1036 write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
af19b491
AKS		 1037 return data;
1038 }
1039
1040 dev_err(&adapter->pdev->dev,
1041 "%s: invalid offset: 0x%016lx\n", __func__, off);
1042 dump_stack();
1043 return -1;
1044}
1045
1046
15087c2b
SC		 1047void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *ahw,
1048 u32 offset)
af19b491
AKS		 1049{
1050 void __iomem *addr = NULL;
1051
15087c2b 1052 WARN_ON(qlcnic_pci_get_crb_addr_2M(ahw, offset, &addr));
af19b491
AKS		 1053
1054 return addr;
1055}
1056
15087c2b
SC		 1057static int qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter,
1058 u32 window, u64 off, u64 *data, int op)
af19b491 1059{
0c39aa48 1060 void __iomem *addr;
af19b491
AKS		 1061 u32 start;
1062
b1fc6d3c 1063 mutex_lock(&adapter->ahw->mem_lock);
af19b491 1064
15087c2b
SC		 1065 writel(window, adapter->ahw->ocm_win_crb);
1066 /* read back to flush */
1067 readl(adapter->ahw->ocm_win_crb);
1068 start = QLCNIC_PCI_OCM0_2M + off;
af19b491 1069
b1fc6d3c 1070 addr = adapter->ahw->pci_base0 + start;
af19b491 1071
af19b491
AKS		 1072 if (op == 0) /* read */
1073 *data = readq(addr);
1074 else /* write */
1075 writeq(*data, addr);
1076
15087c2b
SC		 1077 /* Set window to 0 */
1078 writel(0, adapter->ahw->ocm_win_crb);
1079 readl(adapter->ahw->ocm_win_crb);
af19b491 1080
15087c2b
SC		 1081 mutex_unlock(&adapter->ahw->mem_lock);
1082 return 0;
af19b491
AKS		 1083}
1084
897e8c7c
DP		 1085void
1086qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
1087{
b1fc6d3c 1088 void __iomem *addr = adapter->ahw->pci_base0 +
897e8c7c
DP		 1089 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
1090
b1fc6d3c 1091 mutex_lock(&adapter->ahw->mem_lock);
897e8c7c 1092 *data = readq(addr);
b1fc6d3c 1093 mutex_unlock(&adapter->ahw->mem_lock);
897e8c7c
DP		 1094}
1095
1096void
1097qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
1098{
b1fc6d3c 1099 void __iomem *addr = adapter->ahw->pci_base0 +
897e8c7c
DP		 1100 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
1101
b1fc6d3c 1102 mutex_lock(&adapter->ahw->mem_lock);
897e8c7c 1103 writeq(data, addr);
b1fc6d3c 1104 mutex_unlock(&adapter->ahw->mem_lock);
897e8c7c
DP		 1105}
1106
15087c2b
SC		 1107
1108
1109/* Set MS memory control data for different adapters */
1110static void qlcnic_set_ms_controls(struct qlcnic_adapter *adapter, u64 off,
1111 struct qlcnic_ms_reg_ctrl *ms)
1112{
1113 ms->control = QLCNIC_MS_CTRL;
1114 ms->low = QLCNIC_MS_ADDR_LO;
1115 ms->hi = QLCNIC_MS_ADDR_HI;
1116 if (off & 0xf) {
1117 ms->wd[0] = QLCNIC_MS_WRTDATA_LO;
1118 ms->rd[0] = QLCNIC_MS_RDDATA_LO;
1119 ms->wd[1] = QLCNIC_MS_WRTDATA_HI;
1120 ms->rd[1] = QLCNIC_MS_RDDATA_HI;
1121 ms->wd[2] = QLCNIC_MS_WRTDATA_ULO;
1122 ms->wd[3] = QLCNIC_MS_WRTDATA_UHI;
1123 ms->rd[2] = QLCNIC_MS_RDDATA_ULO;
1124 ms->rd[3] = QLCNIC_MS_RDDATA_UHI;
1125 } else {
1126 ms->wd[0] = QLCNIC_MS_WRTDATA_ULO;
1127 ms->rd[0] = QLCNIC_MS_RDDATA_ULO;
1128 ms->wd[1] = QLCNIC_MS_WRTDATA_UHI;
1129 ms->rd[1] = QLCNIC_MS_RDDATA_UHI;
1130 ms->wd[2] = QLCNIC_MS_WRTDATA_LO;
1131 ms->wd[3] = QLCNIC_MS_WRTDATA_HI;
1132 ms->rd[2] = QLCNIC_MS_RDDATA_LO;
1133 ms->rd[3] = QLCNIC_MS_RDDATA_HI;
1134 }
1135
1136 ms->ocm_window = OCM_WIN_P3P(off);
1137 ms->off = GET_MEM_OFFS_2M(off);
1138}
1139
1140int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
af19b491 1141{
15087c2b 1142 int j, ret = 0;
af19b491 1143 u32 temp, off8;
15087c2b 1144 struct qlcnic_ms_reg_ctrl ms;
af19b491
AKS		 1145
1146 /* Only 64-bit aligned access */
1147 if (off & 7)
1148 return -EIO;
1149
15087c2b
SC		 1150 memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl));
1151 if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1152 QLCNIC_ADDR_QDR_NET_MAX) ||
1153 ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET,
1154 QLCNIC_ADDR_DDR_NET_MAX)))
1155 return -EIO;
af19b491 1156
15087c2b 1157 qlcnic_set_ms_controls(adapter, off, &ms);
af19b491
AKS		 1158
1159 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
15087c2b
SC		 1160 return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window,
1161 ms.off, &data, 1);
af19b491 1162
b47acacd 1163 off8 = off & ~0xf;
af19b491 1164
b1fc6d3c 1165 mutex_lock(&adapter->ahw->mem_lock);
af19b491 1166
15087c2b
SC		 1167 qlcnic_ind_wr(adapter, ms.low, off8);
1168 qlcnic_ind_wr(adapter, ms.hi, 0);
af19b491 1169
15087c2b
SC		 1170 qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE);
1171 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE);
af19b491 1172
b47acacd 1173 for (j = 0; j < MAX_CTL_CHECK; j++) {
15087c2b 1174 temp = qlcnic_ind_rd(adapter, ms.control);
b47acacd
DP		 1175 if ((temp & TA_CTL_BUSY) == 0)
1176 break;
1177 }
af19b491 1178
b47acacd
DP		 1179 if (j >= MAX_CTL_CHECK) {
1180 ret = -EIO;
1181 goto done;
af19b491
AKS		 1182 }
1183
15087c2b
SC		 1184 /* This is the modify part of read-modify-write */
1185 qlcnic_ind_wr(adapter, ms.wd[0], qlcnic_ind_rd(adapter, ms.rd[0]));
1186 qlcnic_ind_wr(adapter, ms.wd[1], qlcnic_ind_rd(adapter, ms.rd[1]));
1187 /* This is the write part of read-modify-write */
1188 qlcnic_ind_wr(adapter, ms.wd[2], data & 0xffffffff);
1189 qlcnic_ind_wr(adapter, ms.wd[3], (data >> 32) & 0xffffffff);
af19b491 1190
15087c2b
SC		 1191 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_ENABLE);
1192 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_START);
af19b491
AKS		 1193
1194 for (j = 0; j < MAX_CTL_CHECK; j++) {
15087c2b 1195 temp = qlcnic_ind_rd(adapter, ms.control);
af19b491
AKS		 1196 if ((temp & TA_CTL_BUSY) == 0)
1197 break;
1198 }
1199
1200 if (j >= MAX_CTL_CHECK) {
1201 if (printk_ratelimit())
1202 dev_err(&adapter->pdev->dev,
1203 "failed to write through agent\n");
1204 ret = -EIO;
1205 } else
1206 ret = 0;
1207
1208done:
b1fc6d3c 1209 mutex_unlock(&adapter->ahw->mem_lock);
af19b491
AKS		 1210
1211 return ret;
1212}
1213
15087c2b 1214int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
af19b491
AKS		 1215{
1216 int j, ret;
1217 u32 temp, off8;
b47acacd 1218 u64 val;
15087c2b 1219 struct qlcnic_ms_reg_ctrl ms;
af19b491
AKS		 1220
1221 /* Only 64-bit aligned access */
1222 if (off & 7)
1223 return -EIO;
15087c2b
SC		 1224 if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1225 QLCNIC_ADDR_QDR_NET_MAX) ||
1226 ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET,
1227 QLCNIC_ADDR_DDR_NET_MAX)))
1228 return -EIO;
af19b491 1229
15087c2b
SC		 1230 memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl));
1231 qlcnic_set_ms_controls(adapter, off, &ms);
af19b491 1232
15087c2b
SC		 1233 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1234 return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window,
1235 ms.off, data, 0);
af19b491 1236
15087c2b 1237 mutex_lock(&adapter->ahw->mem_lock);
af19b491 1238
b47acacd 1239 off8 = off & ~0xf;
af19b491 1240
15087c2b
SC		 1241 qlcnic_ind_wr(adapter, ms.low, off8);
1242 qlcnic_ind_wr(adapter, ms.hi, 0);
af19b491 1243
15087c2b
SC		 1244 qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE);
1245 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE);
af19b491
AKS		 1246
1247 for (j = 0; j < MAX_CTL_CHECK; j++) {
15087c2b 1248 temp = qlcnic_ind_rd(adapter, ms.control);
af19b491
AKS		 1249 if ((temp & TA_CTL_BUSY) == 0)
1250 break;
1251 }
1252
1253 if (j >= MAX_CTL_CHECK) {
1254 if (printk_ratelimit())
1255 dev_err(&adapter->pdev->dev,
1256 "failed to read through agent\n");
1257 ret = -EIO;
1258 } else {
af19b491 1259
15087c2b 1260 temp = qlcnic_ind_rd(adapter, ms.rd[3]);
af19b491 1261 val = (u64)temp << 32;
15087c2b 1262 val |= qlcnic_ind_rd(adapter, ms.rd[2]);
af19b491
AKS		 1263 *data = val;
1264 ret = 0;
1265 }
1266
b1fc6d3c 1267 mutex_unlock(&adapter->ahw->mem_lock);
af19b491
AKS		 1268
1269 return ret;
1270}
1271
1272int qlcnic_get_board_info(struct qlcnic_adapter *adapter)
1273{
1274 int offset, board_type, magic;
1275 struct pci_dev *pdev = adapter->pdev;
1276
1277 offset = QLCNIC_FW_MAGIC_OFFSET;
1278 if (qlcnic_rom_fast_read(adapter, offset, &magic))
1279 return -EIO;
1280
1281 if (magic != QLCNIC_BDINFO_MAGIC) {
1282 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1283 magic);
1284 return -EIO;
1285 }
1286
1287 offset = QLCNIC_BRDTYPE_OFFSET;
1288 if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1289 return -EIO;
1290
b1fc6d3c 1291 adapter->ahw->board_type = board_type;
af19b491 1292
ff1b1bf8 1293 if (board_type == QLCNIC_BRDTYPE_P3P_4_GB_MM) {
af19b491
AKS		 1294 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I);
1295 if ((gpio & 0x8000) == 0)
ff1b1bf8 1296 board_type = QLCNIC_BRDTYPE_P3P_10G_TP;
af19b491
AKS		 1297 }
1298
1299 switch (board_type) {
ff1b1bf8
SV		 1300 case QLCNIC_BRDTYPE_P3P_HMEZ:
1301 case QLCNIC_BRDTYPE_P3P_XG_LOM:
1302 case QLCNIC_BRDTYPE_P3P_10G_CX4:
1303 case QLCNIC_BRDTYPE_P3P_10G_CX4_LP:
1304 case QLCNIC_BRDTYPE_P3P_IMEZ:
1305 case QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS:
1306 case QLCNIC_BRDTYPE_P3P_10G_SFP_CT:
1307 case QLCNIC_BRDTYPE_P3P_10G_SFP_QT:
1308 case QLCNIC_BRDTYPE_P3P_10G_XFP:
1309 case QLCNIC_BRDTYPE_P3P_10000_BASE_T:
b1fc6d3c 1310 adapter->ahw->port_type = QLCNIC_XGBE;
af19b491 1311 break;
ff1b1bf8
SV		 1312 case QLCNIC_BRDTYPE_P3P_REF_QG:
1313 case QLCNIC_BRDTYPE_P3P_4_GB:
1314 case QLCNIC_BRDTYPE_P3P_4_GB_MM:
b1fc6d3c 1315 adapter->ahw->port_type = QLCNIC_GBE;
af19b491 1316 break;
ff1b1bf8 1317 case QLCNIC_BRDTYPE_P3P_10G_TP:
b1fc6d3c 1318 adapter->ahw->port_type = (adapter->portnum < 2) ?
af19b491
AKS		 1319 QLCNIC_XGBE : QLCNIC_GBE;
1320 break;
1321 default:
1322 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
b1fc6d3c 1323 adapter->ahw->port_type = QLCNIC_XGBE;
af19b491
AKS		 1324 break;
1325 }
1326
1327 return 0;
1328}
1329
1330int
1331qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1332{
1333 u32 wol_cfg;
1334
1335 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV);
1336 if (wol_cfg & (1UL << adapter->portnum)) {
1337 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG);
1338 if (wol_cfg & (1 << adapter->portnum))
1339 return 1;
1340 }
1341
1342 return 0;
1343}
897d3596
SC		 1344
1345int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1346{
1347 struct qlcnic_nic_req req;
1348 int rv;
1349 u64 word;
1350
1351 memset(&req, 0, sizeof(struct qlcnic_nic_req));
1352 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1353
1354 word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1355 req.req_hdr = cpu_to_le64(word);
1356
1357 req.words[0] = cpu_to_le64((u64)rate << 32);
1358 req.words[1] = cpu_to_le64(state);
1359
1360 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1361 if (rv)
1362 dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1363
1364 return rv;
1365}
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