Commit | Line | Data |
---|---|---|
af19b491 | 1 | /* |
40839129 | 2 | * QLogic qlcnic NIC Driver |
577ae39d | 3 | * Copyright (c) 2009-2013 QLogic Corporation |
af19b491 | 4 | * |
40839129 | 5 | * See LICENSE.qlcnic for copyright and licensing details. |
af19b491 AKS |
6 | */ |
7 | ||
8 | #include "qlcnic.h" | |
15087c2b | 9 | #include "qlcnic_hdr.h" |
af19b491 | 10 | |
5a0e3ad6 | 11 | #include <linux/slab.h> |
af19b491 | 12 | #include <net/ip.h> |
18f2f616 | 13 | #include <linux/bitops.h> |
af19b491 AKS |
14 | |
15 | #define MASK(n) ((1ULL<<(n))-1) | |
16 | #define OCM_WIN_P3P(addr) (addr & 0xffc0000) | |
17 | ||
18 | #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) | |
19 | ||
20 | #define CRB_BLK(off) ((off >> 20) & 0x3f) | |
21 | #define CRB_SUBBLK(off) ((off >> 16) & 0xf) | |
22 | #define CRB_WINDOW_2M (0x130060) | |
23 | #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000)) | |
24 | #define CRB_INDIRECT_2M (0x1e0000UL) | |
25 | ||
15087c2b SC |
26 | struct qlcnic_ms_reg_ctrl { |
27 | u32 ocm_window; | |
28 | u32 control; | |
29 | u32 hi; | |
30 | u32 low; | |
31 | u32 rd[4]; | |
32 | u32 wd[4]; | |
33 | u64 off; | |
34 | }; | |
af19b491 AKS |
35 | |
36 | #ifndef readq | |
37 | static inline u64 readq(void __iomem *addr) | |
38 | { | |
39 | return readl(addr) | (((u64) readl(addr + 4)) << 32LL); | |
40 | } | |
41 | #endif | |
42 | ||
43 | #ifndef writeq | |
44 | static inline void writeq(u64 val, void __iomem *addr) | |
45 | { | |
46 | writel(((u32) (val)), (addr)); | |
47 | writel(((u32) (val >> 32)), (addr + 4)); | |
48 | } | |
49 | #endif | |
50 | ||
c477ebd8 | 51 | static struct crb_128M_2M_block_map |
af19b491 AKS |
52 | crb_128M_2M_map[64] __cacheline_aligned_in_smp = { |
53 | {{{0, 0, 0, 0} } }, /* 0: PCI */ | |
54 | {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */ | |
55 | {1, 0x0110000, 0x0120000, 0x130000}, | |
56 | {1, 0x0120000, 0x0122000, 0x124000}, | |
57 | {1, 0x0130000, 0x0132000, 0x126000}, | |
58 | {1, 0x0140000, 0x0142000, 0x128000}, | |
59 | {1, 0x0150000, 0x0152000, 0x12a000}, | |
60 | {1, 0x0160000, 0x0170000, 0x110000}, | |
61 | {1, 0x0170000, 0x0172000, 0x12e000}, | |
62 | {0, 0x0000000, 0x0000000, 0x000000}, | |
63 | {0, 0x0000000, 0x0000000, 0x000000}, | |
64 | {0, 0x0000000, 0x0000000, 0x000000}, | |
65 | {0, 0x0000000, 0x0000000, 0x000000}, | |
66 | {0, 0x0000000, 0x0000000, 0x000000}, | |
67 | {0, 0x0000000, 0x0000000, 0x000000}, | |
68 | {1, 0x01e0000, 0x01e0800, 0x122000}, | |
69 | {0, 0x0000000, 0x0000000, 0x000000} } }, | |
70 | {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */ | |
71 | {{{0, 0, 0, 0} } }, /* 3: */ | |
72 | {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */ | |
73 | {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */ | |
74 | {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */ | |
75 | {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */ | |
76 | {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */ | |
77 | {0, 0x0000000, 0x0000000, 0x000000}, | |
78 | {0, 0x0000000, 0x0000000, 0x000000}, | |
79 | {0, 0x0000000, 0x0000000, 0x000000}, | |
80 | {0, 0x0000000, 0x0000000, 0x000000}, | |
81 | {0, 0x0000000, 0x0000000, 0x000000}, | |
82 | {0, 0x0000000, 0x0000000, 0x000000}, | |
83 | {0, 0x0000000, 0x0000000, 0x000000}, | |
84 | {0, 0x0000000, 0x0000000, 0x000000}, | |
85 | {0, 0x0000000, 0x0000000, 0x000000}, | |
86 | {0, 0x0000000, 0x0000000, 0x000000}, | |
87 | {0, 0x0000000, 0x0000000, 0x000000}, | |
88 | {0, 0x0000000, 0x0000000, 0x000000}, | |
89 | {0, 0x0000000, 0x0000000, 0x000000}, | |
90 | {0, 0x0000000, 0x0000000, 0x000000}, | |
91 | {1, 0x08f0000, 0x08f2000, 0x172000} } }, | |
92 | {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/ | |
93 | {0, 0x0000000, 0x0000000, 0x000000}, | |
94 | {0, 0x0000000, 0x0000000, 0x000000}, | |
95 | {0, 0x0000000, 0x0000000, 0x000000}, | |
96 | {0, 0x0000000, 0x0000000, 0x000000}, | |
97 | {0, 0x0000000, 0x0000000, 0x000000}, | |
98 | {0, 0x0000000, 0x0000000, 0x000000}, | |
99 | {0, 0x0000000, 0x0000000, 0x000000}, | |
100 | {0, 0x0000000, 0x0000000, 0x000000}, | |
101 | {0, 0x0000000, 0x0000000, 0x000000}, | |
102 | {0, 0x0000000, 0x0000000, 0x000000}, | |
103 | {0, 0x0000000, 0x0000000, 0x000000}, | |
104 | {0, 0x0000000, 0x0000000, 0x000000}, | |
105 | {0, 0x0000000, 0x0000000, 0x000000}, | |
106 | {0, 0x0000000, 0x0000000, 0x000000}, | |
107 | {1, 0x09f0000, 0x09f2000, 0x176000} } }, | |
108 | {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/ | |
109 | {0, 0x0000000, 0x0000000, 0x000000}, | |
110 | {0, 0x0000000, 0x0000000, 0x000000}, | |
111 | {0, 0x0000000, 0x0000000, 0x000000}, | |
112 | {0, 0x0000000, 0x0000000, 0x000000}, | |
113 | {0, 0x0000000, 0x0000000, 0x000000}, | |
114 | {0, 0x0000000, 0x0000000, 0x000000}, | |
115 | {0, 0x0000000, 0x0000000, 0x000000}, | |
116 | {0, 0x0000000, 0x0000000, 0x000000}, | |
117 | {0, 0x0000000, 0x0000000, 0x000000}, | |
118 | {0, 0x0000000, 0x0000000, 0x000000}, | |
119 | {0, 0x0000000, 0x0000000, 0x000000}, | |
120 | {0, 0x0000000, 0x0000000, 0x000000}, | |
121 | {0, 0x0000000, 0x0000000, 0x000000}, | |
122 | {0, 0x0000000, 0x0000000, 0x000000}, | |
123 | {1, 0x0af0000, 0x0af2000, 0x17a000} } }, | |
124 | {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/ | |
125 | {0, 0x0000000, 0x0000000, 0x000000}, | |
126 | {0, 0x0000000, 0x0000000, 0x000000}, | |
127 | {0, 0x0000000, 0x0000000, 0x000000}, | |
128 | {0, 0x0000000, 0x0000000, 0x000000}, | |
129 | {0, 0x0000000, 0x0000000, 0x000000}, | |
130 | {0, 0x0000000, 0x0000000, 0x000000}, | |
131 | {0, 0x0000000, 0x0000000, 0x000000}, | |
132 | {0, 0x0000000, 0x0000000, 0x000000}, | |
133 | {0, 0x0000000, 0x0000000, 0x000000}, | |
134 | {0, 0x0000000, 0x0000000, 0x000000}, | |
135 | {0, 0x0000000, 0x0000000, 0x000000}, | |
136 | {0, 0x0000000, 0x0000000, 0x000000}, | |
137 | {0, 0x0000000, 0x0000000, 0x000000}, | |
138 | {0, 0x0000000, 0x0000000, 0x000000}, | |
139 | {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, | |
140 | {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */ | |
141 | {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */ | |
142 | {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */ | |
143 | {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */ | |
144 | {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */ | |
145 | {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */ | |
146 | {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */ | |
147 | {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */ | |
148 | {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */ | |
149 | {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */ | |
150 | {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */ | |
151 | {{{0, 0, 0, 0} } }, /* 23: */ | |
152 | {{{0, 0, 0, 0} } }, /* 24: */ | |
153 | {{{0, 0, 0, 0} } }, /* 25: */ | |
154 | {{{0, 0, 0, 0} } }, /* 26: */ | |
155 | {{{0, 0, 0, 0} } }, /* 27: */ | |
156 | {{{0, 0, 0, 0} } }, /* 28: */ | |
157 | {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */ | |
158 | {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */ | |
159 | {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */ | |
160 | {{{0} } }, /* 32: PCI */ | |
161 | {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */ | |
162 | {1, 0x2110000, 0x2120000, 0x130000}, | |
163 | {1, 0x2120000, 0x2122000, 0x124000}, | |
164 | {1, 0x2130000, 0x2132000, 0x126000}, | |
165 | {1, 0x2140000, 0x2142000, 0x128000}, | |
166 | {1, 0x2150000, 0x2152000, 0x12a000}, | |
167 | {1, 0x2160000, 0x2170000, 0x110000}, | |
168 | {1, 0x2170000, 0x2172000, 0x12e000}, | |
169 | {0, 0x0000000, 0x0000000, 0x000000}, | |
170 | {0, 0x0000000, 0x0000000, 0x000000}, | |
171 | {0, 0x0000000, 0x0000000, 0x000000}, | |
172 | {0, 0x0000000, 0x0000000, 0x000000}, | |
173 | {0, 0x0000000, 0x0000000, 0x000000}, | |
174 | {0, 0x0000000, 0x0000000, 0x000000}, | |
175 | {0, 0x0000000, 0x0000000, 0x000000}, | |
176 | {0, 0x0000000, 0x0000000, 0x000000} } }, | |
177 | {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */ | |
178 | {{{0} } }, /* 35: */ | |
179 | {{{0} } }, /* 36: */ | |
180 | {{{0} } }, /* 37: */ | |
181 | {{{0} } }, /* 38: */ | |
182 | {{{0} } }, /* 39: */ | |
183 | {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */ | |
184 | {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */ | |
185 | {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */ | |
186 | {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */ | |
187 | {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */ | |
188 | {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */ | |
189 | {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */ | |
190 | {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */ | |
191 | {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */ | |
192 | {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */ | |
193 | {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */ | |
194 | {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */ | |
195 | {{{0} } }, /* 52: */ | |
196 | {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */ | |
197 | {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */ | |
198 | {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */ | |
199 | {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */ | |
200 | {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */ | |
201 | {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */ | |
202 | {{{0} } }, /* 59: I2C0 */ | |
203 | {{{0} } }, /* 60: I2C1 */ | |
204 | {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */ | |
205 | {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */ | |
206 | {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */ | |
207 | }; | |
208 | ||
209 | /* | |
210 | * top 12 bits of crb internal address (hub, agent) | |
211 | */ | |
212 | static const unsigned crb_hub_agt[64] = { | |
213 | 0, | |
214 | QLCNIC_HW_CRB_HUB_AGT_ADR_PS, | |
215 | QLCNIC_HW_CRB_HUB_AGT_ADR_MN, | |
216 | QLCNIC_HW_CRB_HUB_AGT_ADR_MS, | |
217 | 0, | |
218 | QLCNIC_HW_CRB_HUB_AGT_ADR_SRE, | |
219 | QLCNIC_HW_CRB_HUB_AGT_ADR_NIU, | |
220 | QLCNIC_HW_CRB_HUB_AGT_ADR_QMN, | |
221 | QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0, | |
222 | QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1, | |
223 | QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2, | |
224 | QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3, | |
225 | QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q, | |
226 | QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR, | |
227 | QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB, | |
228 | QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4, | |
229 | QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA, | |
230 | QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0, | |
231 | QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1, | |
232 | QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2, | |
233 | QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3, | |
234 | QLCNIC_HW_CRB_HUB_AGT_ADR_PGND, | |
235 | QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI, | |
236 | QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0, | |
237 | QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1, | |
238 | QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2, | |
239 | QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3, | |
240 | 0, | |
241 | QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI, | |
242 | QLCNIC_HW_CRB_HUB_AGT_ADR_SN, | |
243 | 0, | |
244 | QLCNIC_HW_CRB_HUB_AGT_ADR_EG, | |
245 | 0, | |
246 | QLCNIC_HW_CRB_HUB_AGT_ADR_PS, | |
247 | QLCNIC_HW_CRB_HUB_AGT_ADR_CAM, | |
248 | 0, | |
249 | 0, | |
250 | 0, | |
251 | 0, | |
252 | 0, | |
253 | QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR, | |
254 | 0, | |
255 | QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1, | |
256 | QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2, | |
257 | QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3, | |
258 | QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4, | |
259 | QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5, | |
260 | QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6, | |
261 | QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7, | |
262 | QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA, | |
263 | QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q, | |
264 | QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB, | |
265 | 0, | |
266 | QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0, | |
267 | QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8, | |
268 | QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9, | |
269 | QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0, | |
270 | 0, | |
271 | QLCNIC_HW_CRB_HUB_AGT_ADR_SMB, | |
272 | QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0, | |
273 | QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1, | |
274 | 0, | |
275 | QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC, | |
276 | 0, | |
277 | }; | |
278 | ||
15087c2b SC |
279 | static const u32 msi_tgt_status[8] = { |
280 | ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1, | |
281 | ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3, | |
282 | ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5, | |
283 | ISR_INT_TARGET_STATUS_F6, ISR_INT_TARGET_STATUS_F7 | |
284 | }; | |
285 | ||
af19b491 AKS |
286 | /* PCI Windowing for DDR regions. */ |
287 | ||
288 | #define QLCNIC_PCIE_SEM_TIMEOUT 10000 | |
289 | ||
15087c2b SC |
290 | static void qlcnic_read_window_reg(u32 addr, void __iomem *bar0, u32 *data) |
291 | { | |
292 | u32 dest; | |
293 | void __iomem *val; | |
294 | ||
295 | dest = addr & 0xFFFF0000; | |
296 | val = bar0 + QLCNIC_FW_DUMP_REG1; | |
297 | writel(dest, val); | |
298 | readl(val); | |
299 | val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr); | |
300 | *data = readl(val); | |
301 | } | |
302 | ||
303 | static void qlcnic_write_window_reg(u32 addr, void __iomem *bar0, u32 data) | |
304 | { | |
305 | u32 dest; | |
306 | void __iomem *val; | |
307 | ||
308 | dest = addr & 0xFFFF0000; | |
309 | val = bar0 + QLCNIC_FW_DUMP_REG1; | |
310 | writel(dest, val); | |
311 | readl(val); | |
312 | val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr); | |
313 | writel(data, val); | |
314 | readl(val); | |
315 | } | |
316 | ||
af19b491 AKS |
317 | int |
318 | qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg) | |
319 | { | |
320 | int done = 0, timeout = 0; | |
321 | ||
322 | while (!done) { | |
323 | done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem))); | |
324 | if (done == 1) | |
325 | break; | |
65b5b420 AKS |
326 | if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) { |
327 | dev_err(&adapter->pdev->dev, | |
091754a1 SC |
328 | "Failed to acquire sem=%d lock; holdby=%d\n", |
329 | sem, id_reg ? QLCRD32(adapter, id_reg) : -1); | |
af19b491 | 330 | return -EIO; |
65b5b420 | 331 | } |
af19b491 AKS |
332 | msleep(1); |
333 | } | |
334 | ||
335 | if (id_reg) | |
336 | QLCWR32(adapter, id_reg, adapter->portnum); | |
337 | ||
338 | return 0; | |
339 | } | |
340 | ||
341 | void | |
342 | qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem) | |
343 | { | |
344 | QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem))); | |
345 | } | |
346 | ||
7f966452 | 347 | int qlcnic_ind_rd(struct qlcnic_adapter *adapter, u32 addr) |
15087c2b SC |
348 | { |
349 | u32 data; | |
350 | ||
351 | if (qlcnic_82xx_check(adapter)) | |
352 | qlcnic_read_window_reg(addr, adapter->ahw->pci_base0, &data); | |
7f966452 SC |
353 | else { |
354 | data = qlcnic_83xx_rd_reg_indirect(adapter, addr); | |
355 | if (data == -EIO) | |
356 | return -EIO; | |
357 | } | |
15087c2b SC |
358 | return data; |
359 | } | |
360 | ||
7f966452 | 361 | void qlcnic_ind_wr(struct qlcnic_adapter *adapter, u32 addr, u32 data) |
15087c2b SC |
362 | { |
363 | if (qlcnic_82xx_check(adapter)) | |
364 | qlcnic_write_window_reg(addr, adapter->ahw->pci_base0, data); | |
7f966452 SC |
365 | else |
366 | qlcnic_83xx_wrt_reg_indirect(adapter, addr, data); | |
15087c2b SC |
367 | } |
368 | ||
af19b491 AKS |
369 | static int |
370 | qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter, | |
371 | struct cmd_desc_type0 *cmd_desc_arr, int nr_desc) | |
372 | { | |
5d17f36b | 373 | u32 i, producer; |
af19b491 AKS |
374 | struct qlcnic_cmd_buffer *pbuf; |
375 | struct cmd_desc_type0 *cmd_desc; | |
376 | struct qlcnic_host_tx_ring *tx_ring; | |
377 | ||
378 | i = 0; | |
379 | ||
8a15ad1f | 380 | if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) |
af19b491 AKS |
381 | return -EIO; |
382 | ||
383 | tx_ring = adapter->tx_ring; | |
384 | __netif_tx_lock_bh(tx_ring->txq); | |
385 | ||
386 | producer = tx_ring->producer; | |
af19b491 AKS |
387 | |
388 | if (nr_desc >= qlcnic_tx_avail(tx_ring)) { | |
389 | netif_tx_stop_queue(tx_ring->txq); | |
ef71ff83 RB |
390 | smp_mb(); |
391 | if (qlcnic_tx_avail(tx_ring) > nr_desc) { | |
392 | if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH) | |
393 | netif_tx_wake_queue(tx_ring->txq); | |
394 | } else { | |
395 | adapter->stats.xmit_off++; | |
396 | __netif_tx_unlock_bh(tx_ring->txq); | |
397 | return -EBUSY; | |
398 | } | |
af19b491 AKS |
399 | } |
400 | ||
401 | do { | |
402 | cmd_desc = &cmd_desc_arr[i]; | |
403 | ||
404 | pbuf = &tx_ring->cmd_buf_arr[producer]; | |
405 | pbuf->skb = NULL; | |
406 | pbuf->frag_count = 0; | |
407 | ||
408 | memcpy(&tx_ring->desc_head[producer], | |
5d17f36b | 409 | cmd_desc, sizeof(struct cmd_desc_type0)); |
af19b491 AKS |
410 | |
411 | producer = get_next_index(producer, tx_ring->num_desc); | |
412 | i++; | |
413 | ||
414 | } while (i != nr_desc); | |
415 | ||
416 | tx_ring->producer = producer; | |
417 | ||
5ad6ff9d | 418 | qlcnic_update_cmd_producer(tx_ring); |
af19b491 AKS |
419 | |
420 | __netif_tx_unlock_bh(tx_ring->txq); | |
421 | ||
422 | return 0; | |
423 | } | |
424 | ||
7e2cf4fe SC |
425 | int qlcnic_82xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr, |
426 | __le16 vlan_id, u8 op) | |
af19b491 AKS |
427 | { |
428 | struct qlcnic_nic_req req; | |
429 | struct qlcnic_mac_req *mac_req; | |
7e56cac4 | 430 | struct qlcnic_vlan_req *vlan_req; |
af19b491 AKS |
431 | u64 word; |
432 | ||
433 | memset(&req, 0, sizeof(struct qlcnic_nic_req)); | |
434 | req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23); | |
435 | ||
436 | word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16); | |
437 | req.req_hdr = cpu_to_le64(word); | |
438 | ||
439 | mac_req = (struct qlcnic_mac_req *)&req.words[0]; | |
440 | mac_req->op = op; | |
441 | memcpy(mac_req->mac_addr, addr, 6); | |
442 | ||
7e56cac4 SC |
443 | vlan_req = (struct qlcnic_vlan_req *)&req.words[1]; |
444 | vlan_req->vlan_id = vlan_id; | |
03c5d770 | 445 | |
af19b491 AKS |
446 | return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); |
447 | } | |
448 | ||
fe1adc6b JK |
449 | int qlcnic_nic_del_mac(struct qlcnic_adapter *adapter, const u8 *addr) |
450 | { | |
451 | struct list_head *head; | |
452 | struct qlcnic_mac_list_s *cur; | |
453 | int err = -EINVAL; | |
454 | ||
455 | /* Delete MAC from the existing list */ | |
456 | list_for_each(head, &adapter->mac_list) { | |
457 | cur = list_entry(head, struct qlcnic_mac_list_s, list); | |
458 | if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) { | |
459 | err = qlcnic_sre_macaddr_change(adapter, cur->mac_addr, | |
460 | 0, QLCNIC_MAC_DEL); | |
461 | if (err) | |
462 | return err; | |
463 | list_del(&cur->list); | |
464 | kfree(cur); | |
465 | return err; | |
466 | } | |
467 | } | |
468 | return err; | |
469 | } | |
470 | ||
471 | int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, const u8 *addr) | |
af19b491 AKS |
472 | { |
473 | struct list_head *head; | |
474 | struct qlcnic_mac_list_s *cur; | |
475 | ||
476 | /* look up if already exists */ | |
9ab17b39 | 477 | list_for_each(head, &adapter->mac_list) { |
af19b491 | 478 | cur = list_entry(head, struct qlcnic_mac_list_s, list); |
9ab17b39 | 479 | if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) |
af19b491 | 480 | return 0; |
af19b491 AKS |
481 | } |
482 | ||
483 | cur = kzalloc(sizeof(struct qlcnic_mac_list_s), GFP_ATOMIC); | |
b2adaca9 | 484 | if (cur == NULL) |
af19b491 | 485 | return -ENOMEM; |
b2adaca9 | 486 | |
af19b491 | 487 | memcpy(cur->mac_addr, addr, ETH_ALEN); |
af19b491 | 488 | |
42f65cba | 489 | if (qlcnic_sre_macaddr_change(adapter, |
03c5d770 | 490 | cur->mac_addr, 0, QLCNIC_MAC_ADD)) { |
42f65cba AKS |
491 | kfree(cur); |
492 | return -EIO; | |
493 | } | |
494 | ||
495 | list_add_tail(&cur->list, &adapter->mac_list); | |
496 | return 0; | |
af19b491 AKS |
497 | } |
498 | ||
499 | void qlcnic_set_multi(struct net_device *netdev) | |
500 | { | |
501 | struct qlcnic_adapter *adapter = netdev_priv(netdev); | |
22bedad3 | 502 | struct netdev_hw_addr *ha; |
215faf9c JP |
503 | static const u8 bcast_addr[ETH_ALEN] = { |
504 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff | |
505 | }; | |
af19b491 | 506 | u32 mode = VPORT_MISS_MODE_DROP; |
af19b491 | 507 | |
8a15ad1f | 508 | if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) |
a55cb185 AKS |
509 | return; |
510 | ||
9ab17b39 SC |
511 | qlcnic_nic_add_mac(adapter, adapter->mac_addr); |
512 | qlcnic_nic_add_mac(adapter, bcast_addr); | |
af19b491 AKS |
513 | |
514 | if (netdev->flags & IFF_PROMISC) { | |
ee07c1a7 RB |
515 | if (!(adapter->flags & QLCNIC_PROMISC_DISABLED)) |
516 | mode = VPORT_MISS_MODE_ACCEPT_ALL; | |
af19b491 AKS |
517 | goto send_fw_cmd; |
518 | } | |
519 | ||
520 | if ((netdev->flags & IFF_ALLMULTI) || | |
79788450 | 521 | (netdev_mc_count(netdev) > adapter->ahw->max_mc_count)) { |
af19b491 AKS |
522 | mode = VPORT_MISS_MODE_ACCEPT_MULTI; |
523 | goto send_fw_cmd; | |
524 | } | |
525 | ||
4cd24eaf | 526 | if (!netdev_mc_empty(netdev)) { |
22bedad3 JP |
527 | netdev_for_each_mc_addr(ha, netdev) { |
528 | qlcnic_nic_add_mac(adapter, ha->addr); | |
af19b491 AKS |
529 | } |
530 | } | |
531 | ||
532 | send_fw_cmd: | |
fe1adc6b | 533 | if (mode == VPORT_MISS_MODE_ACCEPT_ALL && !adapter->fdb_mac_learn) { |
e5dcf6dc | 534 | qlcnic_alloc_lb_filters_mem(adapter); |
fe1adc6b | 535 | adapter->drv_mac_learn = true; |
e5dcf6dc | 536 | } else { |
fe1adc6b | 537 | adapter->drv_mac_learn = false; |
e5dcf6dc SC |
538 | } |
539 | ||
af19b491 | 540 | qlcnic_nic_set_promisc(adapter, mode); |
af19b491 AKS |
541 | } |
542 | ||
7e2cf4fe | 543 | int qlcnic_82xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode) |
af19b491 AKS |
544 | { |
545 | struct qlcnic_nic_req req; | |
546 | u64 word; | |
547 | ||
548 | memset(&req, 0, sizeof(struct qlcnic_nic_req)); | |
549 | ||
550 | req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); | |
551 | ||
b1fc6d3c | 552 | word = QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE | |
af19b491 AKS |
553 | ((u64)adapter->portnum << 16); |
554 | req.req_hdr = cpu_to_le64(word); | |
555 | ||
556 | req.words[0] = cpu_to_le64(mode); | |
557 | ||
558 | return qlcnic_send_cmd_descs(adapter, | |
559 | (struct cmd_desc_type0 *)&req, 1); | |
560 | } | |
561 | ||
562 | void qlcnic_free_mac_list(struct qlcnic_adapter *adapter) | |
563 | { | |
564 | struct qlcnic_mac_list_s *cur; | |
565 | struct list_head *head = &adapter->mac_list; | |
566 | ||
567 | while (!list_empty(head)) { | |
568 | cur = list_entry(head->next, struct qlcnic_mac_list_s, list); | |
569 | qlcnic_sre_macaddr_change(adapter, | |
03c5d770 | 570 | cur->mac_addr, 0, QLCNIC_MAC_DEL); |
af19b491 AKS |
571 | list_del(&cur->list); |
572 | kfree(cur); | |
573 | } | |
574 | } | |
575 | ||
b5e5492c AKS |
576 | void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter) |
577 | { | |
578 | struct qlcnic_filter *tmp_fil; | |
b67bfe0d | 579 | struct hlist_node *n; |
b5e5492c | 580 | struct hlist_head *head; |
53643a75 SS |
581 | int i; |
582 | unsigned long time; | |
7f966452 | 583 | u8 cmd; |
b5e5492c | 584 | |
7f966452 | 585 | for (i = 0; i < adapter->fhash.fbucket_size; i++) { |
b5e5492c | 586 | head = &(adapter->fhash.fhead[i]); |
b67bfe0d | 587 | hlist_for_each_entry_safe(tmp_fil, n, head, fnode) { |
7f966452 SC |
588 | cmd = tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL : |
589 | QLCNIC_MAC_DEL; | |
590 | time = tmp_fil->ftime; | |
591 | if (jiffies > (QLCNIC_FILTER_AGE * HZ + time)) { | |
b5e5492c | 592 | qlcnic_sre_macaddr_change(adapter, |
7f966452 SC |
593 | tmp_fil->faddr, |
594 | tmp_fil->vlan_id, | |
595 | cmd); | |
b5e5492c AKS |
596 | spin_lock_bh(&adapter->mac_learn_lock); |
597 | adapter->fhash.fnum--; | |
598 | hlist_del(&tmp_fil->fnode); | |
599 | spin_unlock_bh(&adapter->mac_learn_lock); | |
600 | kfree(tmp_fil); | |
601 | } | |
602 | } | |
603 | } | |
53643a75 SS |
604 | for (i = 0; i < adapter->rx_fhash.fbucket_size; i++) { |
605 | head = &(adapter->rx_fhash.fhead[i]); | |
606 | ||
b67bfe0d | 607 | hlist_for_each_entry_safe(tmp_fil, n, head, fnode) |
53643a75 SS |
608 | { |
609 | time = tmp_fil->ftime; | |
610 | if (jiffies > (QLCNIC_FILTER_AGE * HZ + time)) { | |
611 | spin_lock_bh(&adapter->rx_mac_learn_lock); | |
612 | adapter->rx_fhash.fnum--; | |
613 | hlist_del(&tmp_fil->fnode); | |
614 | spin_unlock_bh(&adapter->rx_mac_learn_lock); | |
615 | kfree(tmp_fil); | |
616 | } | |
617 | } | |
618 | } | |
b5e5492c AKS |
619 | } |
620 | ||
621 | void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter) | |
622 | { | |
623 | struct qlcnic_filter *tmp_fil; | |
b67bfe0d | 624 | struct hlist_node *n; |
b5e5492c AKS |
625 | struct hlist_head *head; |
626 | int i; | |
7f966452 | 627 | u8 cmd; |
b5e5492c | 628 | |
7f966452 | 629 | for (i = 0; i < adapter->fhash.fbucket_size; i++) { |
b5e5492c | 630 | head = &(adapter->fhash.fhead[i]); |
b67bfe0d | 631 | hlist_for_each_entry_safe(tmp_fil, n, head, fnode) { |
7f966452 SC |
632 | cmd = tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL : |
633 | QLCNIC_MAC_DEL; | |
634 | qlcnic_sre_macaddr_change(adapter, | |
635 | tmp_fil->faddr, | |
636 | tmp_fil->vlan_id, | |
637 | cmd); | |
b5e5492c AKS |
638 | spin_lock_bh(&adapter->mac_learn_lock); |
639 | adapter->fhash.fnum--; | |
640 | hlist_del(&tmp_fil->fnode); | |
641 | spin_unlock_bh(&adapter->mac_learn_lock); | |
642 | kfree(tmp_fil); | |
643 | } | |
644 | } | |
645 | } | |
646 | ||
6d973cb1 | 647 | static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u8 flag) |
22c8c934 SC |
648 | { |
649 | struct qlcnic_nic_req req; | |
650 | int rv; | |
651 | ||
652 | memset(&req, 0, sizeof(struct qlcnic_nic_req)); | |
653 | ||
654 | req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); | |
655 | req.req_hdr = cpu_to_le64(QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK | | |
656 | ((u64) adapter->portnum << 16) | ((u64) 0x1 << 32)); | |
657 | ||
658 | req.words[0] = cpu_to_le64(flag); | |
659 | ||
660 | rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); | |
661 | if (rv != 0) | |
662 | dev_err(&adapter->pdev->dev, "%sting loopback mode failed\n", | |
663 | flag ? "Set" : "Reset"); | |
664 | return rv; | |
665 | } | |
666 | ||
7e2cf4fe | 667 | int qlcnic_82xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode) |
22c8c934 SC |
668 | { |
669 | if (qlcnic_set_fw_loopback(adapter, mode)) | |
670 | return -EIO; | |
671 | ||
7e2cf4fe SC |
672 | if (qlcnic_nic_set_promisc(adapter, |
673 | VPORT_MISS_MODE_ACCEPT_ALL)) { | |
ad567b8f | 674 | qlcnic_set_fw_loopback(adapter, 0); |
22c8c934 SC |
675 | return -EIO; |
676 | } | |
677 | ||
678 | msleep(1000); | |
679 | return 0; | |
680 | } | |
681 | ||
7e2cf4fe | 682 | int qlcnic_82xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode) |
22c8c934 | 683 | { |
22c8c934 SC |
684 | struct net_device *netdev = adapter->netdev; |
685 | ||
7e2cf4fe | 686 | mode = VPORT_MISS_MODE_DROP; |
22c8c934 SC |
687 | qlcnic_set_fw_loopback(adapter, 0); |
688 | ||
689 | if (netdev->flags & IFF_PROMISC) | |
690 | mode = VPORT_MISS_MODE_ACCEPT_ALL; | |
691 | else if (netdev->flags & IFF_ALLMULTI) | |
692 | mode = VPORT_MISS_MODE_ACCEPT_MULTI; | |
693 | ||
694 | qlcnic_nic_set_promisc(adapter, mode); | |
695 | msleep(1000); | |
7e2cf4fe | 696 | return 0; |
22c8c934 SC |
697 | } |
698 | ||
af19b491 AKS |
699 | /* |
700 | * Send the interrupt coalescing parameter set by ethtool to the card. | |
701 | */ | |
7e2cf4fe | 702 | void qlcnic_82xx_config_intr_coalesce(struct qlcnic_adapter *adapter) |
af19b491 AKS |
703 | { |
704 | struct qlcnic_nic_req req; | |
8816d009 | 705 | int rv; |
af19b491 AKS |
706 | |
707 | memset(&req, 0, sizeof(struct qlcnic_nic_req)); | |
708 | ||
709 | req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); | |
710 | ||
8816d009 AC |
711 | req.req_hdr = cpu_to_le64(QLCNIC_CONFIG_INTR_COALESCE | |
712 | ((u64) adapter->portnum << 16)); | |
af19b491 | 713 | |
8816d009 AC |
714 | req.words[0] = cpu_to_le64(((u64) adapter->ahw->coal.flag) << 32); |
715 | req.words[2] = cpu_to_le64(adapter->ahw->coal.rx_packets | | |
716 | ((u64) adapter->ahw->coal.rx_time_us) << 16); | |
717 | req.words[5] = cpu_to_le64(adapter->ahw->coal.timer_out | | |
718 | ((u64) adapter->ahw->coal.type) << 32 | | |
719 | ((u64) adapter->ahw->coal.sts_ring_mask) << 40); | |
af19b491 AKS |
720 | rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); |
721 | if (rv != 0) | |
722 | dev_err(&adapter->netdev->dev, | |
723 | "Could not send interrupt coalescing parameters\n"); | |
af19b491 AKS |
724 | } |
725 | ||
776e7bde SS |
726 | #define QLCNIC_ENABLE_IPV4_LRO 1 |
727 | #define QLCNIC_ENABLE_IPV6_LRO 2 | |
728 | #define QLCNIC_NO_DEST_IPV4_CHECK (1 << 8) | |
729 | #define QLCNIC_NO_DEST_IPV6_CHECK (2 << 8) | |
730 | ||
7e2cf4fe | 731 | int qlcnic_82xx_config_hw_lro(struct qlcnic_adapter *adapter, int enable) |
af19b491 AKS |
732 | { |
733 | struct qlcnic_nic_req req; | |
734 | u64 word; | |
735 | int rv; | |
736 | ||
b56421d0 RB |
737 | if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) |
738 | return 0; | |
739 | ||
af19b491 AKS |
740 | memset(&req, 0, sizeof(struct qlcnic_nic_req)); |
741 | ||
742 | req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); | |
743 | ||
744 | word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16); | |
745 | req.req_hdr = cpu_to_le64(word); | |
746 | ||
776e7bde SS |
747 | word = 0; |
748 | if (enable) { | |
749 | word = QLCNIC_ENABLE_IPV4_LRO | QLCNIC_NO_DEST_IPV4_CHECK; | |
750 | if (adapter->ahw->capabilities2 & QLCNIC_FW_CAP2_HW_LRO_IPV6) | |
751 | word |= QLCNIC_ENABLE_IPV6_LRO | | |
752 | QLCNIC_NO_DEST_IPV6_CHECK; | |
753 | } | |
754 | ||
755 | req.words[0] = cpu_to_le64(word); | |
af19b491 AKS |
756 | |
757 | rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); | |
758 | if (rv != 0) | |
759 | dev_err(&adapter->netdev->dev, | |
760 | "Could not send configure hw lro request\n"); | |
761 | ||
af19b491 AKS |
762 | return rv; |
763 | } | |
764 | ||
2e9d722d | 765 | int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable) |
af19b491 AKS |
766 | { |
767 | struct qlcnic_nic_req req; | |
768 | u64 word; | |
769 | int rv; | |
770 | ||
771 | if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable) | |
772 | return 0; | |
773 | ||
774 | memset(&req, 0, sizeof(struct qlcnic_nic_req)); | |
775 | ||
776 | req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); | |
777 | ||
778 | word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING | | |
779 | ((u64)adapter->portnum << 16); | |
780 | req.req_hdr = cpu_to_le64(word); | |
781 | ||
782 | req.words[0] = cpu_to_le64(enable); | |
783 | ||
784 | rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); | |
785 | if (rv != 0) | |
786 | dev_err(&adapter->netdev->dev, | |
787 | "Could not send configure bridge mode request\n"); | |
788 | ||
789 | adapter->flags ^= QLCNIC_BRIDGE_ENABLED; | |
790 | ||
791 | return rv; | |
792 | } | |
793 | ||
794 | ||
efbcb1b2 SS |
795 | #define QLCNIC_RSS_HASHTYPE_IP_TCP 0x3 |
796 | #define QLCNIC_ENABLE_TYPE_C_RSS BIT_10 | |
797 | #define QLCNIC_RSS_FEATURE_FLAG (1ULL << 63) | |
798 | #define QLCNIC_RSS_IND_TABLE_MASK 0x7ULL | |
af19b491 | 799 | |
7e2cf4fe | 800 | int qlcnic_82xx_config_rss(struct qlcnic_adapter *adapter, int enable) |
af19b491 AKS |
801 | { |
802 | struct qlcnic_nic_req req; | |
803 | u64 word; | |
804 | int i, rv; | |
805 | ||
215faf9c JP |
806 | static const u64 key[] = { |
807 | 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL, | |
808 | 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL, | |
809 | 0x255b0ec26d5a56daULL | |
810 | }; | |
af19b491 AKS |
811 | |
812 | memset(&req, 0, sizeof(struct qlcnic_nic_req)); | |
813 | req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); | |
814 | ||
815 | word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16); | |
816 | req.req_hdr = cpu_to_le64(word); | |
817 | ||
818 | /* | |
819 | * RSS request: | |
820 | * bits 3-0: hash_method | |
821 | * 5-4: hash_type_ipv4 | |
822 | * 7-6: hash_type_ipv6 | |
823 | * 8: enable | |
824 | * 9: use indirection table | |
efbcb1b2 SS |
825 | * 10: type-c rss |
826 | * 11: udp rss | |
827 | * 47-12: reserved | |
828 | * 62-48: indirection table mask | |
829 | * 63: feature flag | |
af19b491 | 830 | */ |
efbcb1b2 SS |
831 | word = ((u64)(QLCNIC_RSS_HASHTYPE_IP_TCP & 0x3) << 4) | |
832 | ((u64)(QLCNIC_RSS_HASHTYPE_IP_TCP & 0x3) << 6) | | |
af19b491 | 833 | ((u64)(enable & 0x1) << 8) | |
efbcb1b2 SS |
834 | ((u64)QLCNIC_RSS_IND_TABLE_MASK << 48) | |
835 | (u64)QLCNIC_ENABLE_TYPE_C_RSS | | |
836 | (u64)QLCNIC_RSS_FEATURE_FLAG; | |
837 | ||
af19b491 AKS |
838 | req.words[0] = cpu_to_le64(word); |
839 | for (i = 0; i < 5; i++) | |
840 | req.words[i+1] = cpu_to_le64(key[i]); | |
841 | ||
842 | rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); | |
843 | if (rv != 0) | |
844 | dev_err(&adapter->netdev->dev, "could not configure RSS\n"); | |
845 | ||
846 | return rv; | |
847 | } | |
848 | ||
7e2cf4fe SC |
849 | void qlcnic_82xx_config_ipaddr(struct qlcnic_adapter *adapter, |
850 | __be32 ip, int cmd) | |
af19b491 AKS |
851 | { |
852 | struct qlcnic_nic_req req; | |
b501595c | 853 | struct qlcnic_ipaddr *ipa; |
af19b491 AKS |
854 | u64 word; |
855 | int rv; | |
856 | ||
857 | memset(&req, 0, sizeof(struct qlcnic_nic_req)); | |
858 | req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); | |
859 | ||
860 | word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16); | |
861 | req.req_hdr = cpu_to_le64(word); | |
862 | ||
863 | req.words[0] = cpu_to_le64(cmd); | |
b501595c SC |
864 | ipa = (struct qlcnic_ipaddr *)&req.words[1]; |
865 | ipa->ipv4 = ip; | |
af19b491 AKS |
866 | |
867 | rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); | |
868 | if (rv != 0) | |
869 | dev_err(&adapter->netdev->dev, | |
870 | "could not notify %s IP 0x%x reuqest\n", | |
871 | (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip); | |
af19b491 AKS |
872 | } |
873 | ||
7e2cf4fe | 874 | int qlcnic_82xx_linkevent_request(struct qlcnic_adapter *adapter, int enable) |
af19b491 AKS |
875 | { |
876 | struct qlcnic_nic_req req; | |
877 | u64 word; | |
878 | int rv; | |
af19b491 AKS |
879 | memset(&req, 0, sizeof(struct qlcnic_nic_req)); |
880 | req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); | |
881 | ||
882 | word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16); | |
883 | req.req_hdr = cpu_to_le64(word); | |
884 | req.words[0] = cpu_to_le64(enable | (enable << 8)); | |
af19b491 AKS |
885 | rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); |
886 | if (rv != 0) | |
887 | dev_err(&adapter->netdev->dev, | |
888 | "could not configure link notification\n"); | |
889 | ||
890 | return rv; | |
891 | } | |
892 | ||
893 | int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter) | |
894 | { | |
895 | struct qlcnic_nic_req req; | |
896 | u64 word; | |
897 | int rv; | |
898 | ||
b56421d0 RB |
899 | if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) |
900 | return 0; | |
901 | ||
af19b491 AKS |
902 | memset(&req, 0, sizeof(struct qlcnic_nic_req)); |
903 | req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); | |
904 | ||
905 | word = QLCNIC_H2C_OPCODE_LRO_REQUEST | | |
906 | ((u64)adapter->portnum << 16) | | |
907 | ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ; | |
908 | ||
909 | req.req_hdr = cpu_to_le64(word); | |
910 | ||
911 | rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); | |
912 | if (rv != 0) | |
913 | dev_err(&adapter->netdev->dev, | |
914 | "could not cleanup lro flows\n"); | |
915 | ||
916 | return rv; | |
917 | } | |
918 | ||
919 | /* | |
920 | * qlcnic_change_mtu - Change the Maximum Transfer Unit | |
921 | * @returns 0 on success, negative on failure | |
922 | */ | |
923 | ||
924 | int qlcnic_change_mtu(struct net_device *netdev, int mtu) | |
925 | { | |
926 | struct qlcnic_adapter *adapter = netdev_priv(netdev); | |
927 | int rc = 0; | |
928 | ||
ff1b1bf8 | 929 | if (mtu < P3P_MIN_MTU || mtu > P3P_MAX_MTU) { |
0bd9e6a9 | 930 | dev_err(&adapter->netdev->dev, "%d bytes < mtu < %d bytes" |
ff1b1bf8 | 931 | " not supported\n", P3P_MAX_MTU, P3P_MIN_MTU); |
af19b491 AKS |
932 | return -EINVAL; |
933 | } | |
934 | ||
935 | rc = qlcnic_fw_cmd_set_mtu(adapter, mtu); | |
936 | ||
937 | if (!rc) | |
938 | netdev->mtu = mtu; | |
939 | ||
940 | return rc; | |
941 | } | |
942 | ||
135d84a9 | 943 | |
c8f44aff MM |
944 | netdev_features_t qlcnic_fix_features(struct net_device *netdev, |
945 | netdev_features_t features) | |
135d84a9 MM |
946 | { |
947 | struct qlcnic_adapter *adapter = netdev_priv(netdev); | |
948 | ||
22fd5ab4 M |
949 | if ((adapter->flags & QLCNIC_ESWITCH_ENABLED) && |
950 | qlcnic_82xx_check(adapter)) { | |
c8f44aff | 951 | netdev_features_t changed = features ^ netdev->features; |
135d84a9 MM |
952 | features ^= changed & (NETIF_F_ALL_CSUM | NETIF_F_RXCSUM); |
953 | } | |
954 | ||
955 | if (!(features & NETIF_F_RXCSUM)) | |
956 | features &= ~NETIF_F_LRO; | |
957 | ||
958 | return features; | |
959 | } | |
960 | ||
961 | ||
c8f44aff | 962 | int qlcnic_set_features(struct net_device *netdev, netdev_features_t features) |
135d84a9 MM |
963 | { |
964 | struct qlcnic_adapter *adapter = netdev_priv(netdev); | |
c8f44aff | 965 | netdev_features_t changed = netdev->features ^ features; |
135d84a9 MM |
966 | int hw_lro = (features & NETIF_F_LRO) ? QLCNIC_LRO_ENABLED : 0; |
967 | ||
968 | if (!(changed & NETIF_F_LRO)) | |
969 | return 0; | |
970 | ||
7e38d04b | 971 | netdev->features ^= NETIF_F_LRO; |
135d84a9 MM |
972 | |
973 | if (qlcnic_config_hw_lro(adapter, hw_lro)) | |
974 | return -EIO; | |
975 | ||
283c1c68 M |
976 | if (!hw_lro && qlcnic_82xx_check(adapter)) { |
977 | if (qlcnic_send_lro_cleanup(adapter)) | |
978 | return -EIO; | |
979 | } | |
135d84a9 MM |
980 | |
981 | return 0; | |
982 | } | |
983 | ||
af19b491 AKS |
984 | /* |
985 | * Changes the CRB window to the specified window. | |
986 | */ | |
987 | /* Returns < 0 if off is not valid, | |
988 | * 1 if window access is needed. 'off' is set to offset from | |
989 | * CRB space in 128M pci map | |
990 | * 0 if no window access is needed. 'off' is set to 2M addr | |
991 | * In: 'off' is offset from base in 128M pci map | |
992 | */ | |
15087c2b SC |
993 | static int qlcnic_pci_get_crb_addr_2M(struct qlcnic_hardware_context *ahw, |
994 | ulong off, void __iomem **addr) | |
af19b491 AKS |
995 | { |
996 | const struct crb_128M_2M_sub_block_map *m; | |
997 | ||
998 | if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE)) | |
999 | return -EINVAL; | |
1000 | ||
1001 | off -= QLCNIC_PCI_CRBSPACE; | |
1002 | ||
1003 | /* | |
1004 | * Try direct map | |
1005 | */ | |
1006 | m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)]; | |
1007 | ||
1008 | if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) { | |
15087c2b | 1009 | *addr = ahw->pci_base0 + m->start_2M + |
af19b491 AKS |
1010 | (off - m->start_128M); |
1011 | return 0; | |
1012 | } | |
1013 | ||
1014 | /* | |
1015 | * Not in direct map, use crb window | |
1016 | */ | |
15087c2b | 1017 | *addr = ahw->pci_base0 + CRB_INDIRECT_2M + (off & MASK(16)); |
af19b491 AKS |
1018 | return 1; |
1019 | } | |
1020 | ||
1021 | /* | |
1022 | * In: 'off' is offset from CRB space in 128M pci map | |
1023 | * Out: 'off' is 2M pci map addr | |
1024 | * side effect: lock crb window | |
1025 | */ | |
4de57826 | 1026 | static int |
af19b491 AKS |
1027 | qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off) |
1028 | { | |
1029 | u32 window; | |
b1fc6d3c | 1030 | void __iomem *addr = adapter->ahw->pci_base0 + CRB_WINDOW_2M; |
af19b491 AKS |
1031 | |
1032 | off -= QLCNIC_PCI_CRBSPACE; | |
1033 | ||
1034 | window = CRB_HI(off); | |
4de57826 AKS |
1035 | if (window == 0) { |
1036 | dev_err(&adapter->pdev->dev, "Invalid offset 0x%lx\n", off); | |
1037 | return -EIO; | |
1038 | } | |
af19b491 | 1039 | |
af19b491 AKS |
1040 | writel(window, addr); |
1041 | if (readl(addr) != window) { | |
1042 | if (printk_ratelimit()) | |
1043 | dev_warn(&adapter->pdev->dev, | |
1044 | "failed to set CRB window to %d off 0x%lx\n", | |
1045 | window, off); | |
4de57826 | 1046 | return -EIO; |
af19b491 | 1047 | } |
4de57826 | 1048 | return 0; |
af19b491 AKS |
1049 | } |
1050 | ||
7e2cf4fe SC |
1051 | int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off, |
1052 | u32 data) | |
af19b491 AKS |
1053 | { |
1054 | unsigned long flags; | |
1055 | int rv; | |
1056 | void __iomem *addr = NULL; | |
1057 | ||
15087c2b | 1058 | rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr); |
af19b491 AKS |
1059 | |
1060 | if (rv == 0) { | |
1061 | writel(data, addr); | |
1062 | return 0; | |
1063 | } | |
1064 | ||
1065 | if (rv > 0) { | |
1066 | /* indirect access */ | |
b1fc6d3c | 1067 | write_lock_irqsave(&adapter->ahw->crb_lock, flags); |
af19b491 | 1068 | crb_win_lock(adapter); |
4de57826 AKS |
1069 | rv = qlcnic_pci_set_crbwindow_2M(adapter, off); |
1070 | if (!rv) | |
1071 | writel(data, addr); | |
af19b491 | 1072 | crb_win_unlock(adapter); |
b1fc6d3c | 1073 | write_unlock_irqrestore(&adapter->ahw->crb_lock, flags); |
4de57826 | 1074 | return rv; |
af19b491 AKS |
1075 | } |
1076 | ||
1077 | dev_err(&adapter->pdev->dev, | |
1078 | "%s: invalid offset: 0x%016lx\n", __func__, off); | |
1079 | dump_stack(); | |
1080 | return -EIO; | |
1081 | } | |
1082 | ||
7e2cf4fe | 1083 | int qlcnic_82xx_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off) |
af19b491 AKS |
1084 | { |
1085 | unsigned long flags; | |
1086 | int rv; | |
4de57826 | 1087 | u32 data = -1; |
af19b491 AKS |
1088 | void __iomem *addr = NULL; |
1089 | ||
15087c2b | 1090 | rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr); |
af19b491 AKS |
1091 | |
1092 | if (rv == 0) | |
1093 | return readl(addr); | |
1094 | ||
1095 | if (rv > 0) { | |
1096 | /* indirect access */ | |
b1fc6d3c | 1097 | write_lock_irqsave(&adapter->ahw->crb_lock, flags); |
af19b491 | 1098 | crb_win_lock(adapter); |
4de57826 AKS |
1099 | if (!qlcnic_pci_set_crbwindow_2M(adapter, off)) |
1100 | data = readl(addr); | |
af19b491 | 1101 | crb_win_unlock(adapter); |
b1fc6d3c | 1102 | write_unlock_irqrestore(&adapter->ahw->crb_lock, flags); |
af19b491 AKS |
1103 | return data; |
1104 | } | |
1105 | ||
1106 | dev_err(&adapter->pdev->dev, | |
1107 | "%s: invalid offset: 0x%016lx\n", __func__, off); | |
1108 | dump_stack(); | |
1109 | return -1; | |
1110 | } | |
1111 | ||
15087c2b SC |
1112 | void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *ahw, |
1113 | u32 offset) | |
af19b491 AKS |
1114 | { |
1115 | void __iomem *addr = NULL; | |
1116 | ||
15087c2b | 1117 | WARN_ON(qlcnic_pci_get_crb_addr_2M(ahw, offset, &addr)); |
af19b491 AKS |
1118 | |
1119 | return addr; | |
1120 | } | |
1121 | ||
15087c2b SC |
1122 | static int qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter, |
1123 | u32 window, u64 off, u64 *data, int op) | |
af19b491 | 1124 | { |
0c39aa48 | 1125 | void __iomem *addr; |
af19b491 AKS |
1126 | u32 start; |
1127 | ||
b1fc6d3c | 1128 | mutex_lock(&adapter->ahw->mem_lock); |
af19b491 | 1129 | |
15087c2b SC |
1130 | writel(window, adapter->ahw->ocm_win_crb); |
1131 | /* read back to flush */ | |
1132 | readl(adapter->ahw->ocm_win_crb); | |
1133 | start = QLCNIC_PCI_OCM0_2M + off; | |
af19b491 | 1134 | |
b1fc6d3c | 1135 | addr = adapter->ahw->pci_base0 + start; |
af19b491 | 1136 | |
af19b491 AKS |
1137 | if (op == 0) /* read */ |
1138 | *data = readq(addr); | |
1139 | else /* write */ | |
1140 | writeq(*data, addr); | |
1141 | ||
15087c2b SC |
1142 | /* Set window to 0 */ |
1143 | writel(0, adapter->ahw->ocm_win_crb); | |
1144 | readl(adapter->ahw->ocm_win_crb); | |
af19b491 | 1145 | |
15087c2b SC |
1146 | mutex_unlock(&adapter->ahw->mem_lock); |
1147 | return 0; | |
af19b491 AKS |
1148 | } |
1149 | ||
897e8c7c DP |
1150 | void |
1151 | qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data) | |
1152 | { | |
b1fc6d3c | 1153 | void __iomem *addr = adapter->ahw->pci_base0 + |
897e8c7c DP |
1154 | QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM); |
1155 | ||
b1fc6d3c | 1156 | mutex_lock(&adapter->ahw->mem_lock); |
897e8c7c | 1157 | *data = readq(addr); |
b1fc6d3c | 1158 | mutex_unlock(&adapter->ahw->mem_lock); |
897e8c7c DP |
1159 | } |
1160 | ||
1161 | void | |
1162 | qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data) | |
1163 | { | |
b1fc6d3c | 1164 | void __iomem *addr = adapter->ahw->pci_base0 + |
897e8c7c DP |
1165 | QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM); |
1166 | ||
b1fc6d3c | 1167 | mutex_lock(&adapter->ahw->mem_lock); |
897e8c7c | 1168 | writeq(data, addr); |
b1fc6d3c | 1169 | mutex_unlock(&adapter->ahw->mem_lock); |
897e8c7c DP |
1170 | } |
1171 | ||
15087c2b SC |
1172 | |
1173 | ||
1174 | /* Set MS memory control data for different adapters */ | |
1175 | static void qlcnic_set_ms_controls(struct qlcnic_adapter *adapter, u64 off, | |
1176 | struct qlcnic_ms_reg_ctrl *ms) | |
1177 | { | |
1178 | ms->control = QLCNIC_MS_CTRL; | |
1179 | ms->low = QLCNIC_MS_ADDR_LO; | |
1180 | ms->hi = QLCNIC_MS_ADDR_HI; | |
1181 | if (off & 0xf) { | |
1182 | ms->wd[0] = QLCNIC_MS_WRTDATA_LO; | |
1183 | ms->rd[0] = QLCNIC_MS_RDDATA_LO; | |
1184 | ms->wd[1] = QLCNIC_MS_WRTDATA_HI; | |
1185 | ms->rd[1] = QLCNIC_MS_RDDATA_HI; | |
1186 | ms->wd[2] = QLCNIC_MS_WRTDATA_ULO; | |
1187 | ms->wd[3] = QLCNIC_MS_WRTDATA_UHI; | |
1188 | ms->rd[2] = QLCNIC_MS_RDDATA_ULO; | |
1189 | ms->rd[3] = QLCNIC_MS_RDDATA_UHI; | |
1190 | } else { | |
1191 | ms->wd[0] = QLCNIC_MS_WRTDATA_ULO; | |
1192 | ms->rd[0] = QLCNIC_MS_RDDATA_ULO; | |
1193 | ms->wd[1] = QLCNIC_MS_WRTDATA_UHI; | |
1194 | ms->rd[1] = QLCNIC_MS_RDDATA_UHI; | |
1195 | ms->wd[2] = QLCNIC_MS_WRTDATA_LO; | |
1196 | ms->wd[3] = QLCNIC_MS_WRTDATA_HI; | |
1197 | ms->rd[2] = QLCNIC_MS_RDDATA_LO; | |
1198 | ms->rd[3] = QLCNIC_MS_RDDATA_HI; | |
1199 | } | |
1200 | ||
1201 | ms->ocm_window = OCM_WIN_P3P(off); | |
1202 | ms->off = GET_MEM_OFFS_2M(off); | |
1203 | } | |
1204 | ||
1205 | int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data) | |
af19b491 | 1206 | { |
15087c2b | 1207 | int j, ret = 0; |
af19b491 | 1208 | u32 temp, off8; |
15087c2b | 1209 | struct qlcnic_ms_reg_ctrl ms; |
af19b491 AKS |
1210 | |
1211 | /* Only 64-bit aligned access */ | |
1212 | if (off & 7) | |
1213 | return -EIO; | |
1214 | ||
15087c2b SC |
1215 | memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl)); |
1216 | if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET, | |
1217 | QLCNIC_ADDR_QDR_NET_MAX) || | |
1218 | ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, | |
1219 | QLCNIC_ADDR_DDR_NET_MAX))) | |
1220 | return -EIO; | |
af19b491 | 1221 | |
15087c2b | 1222 | qlcnic_set_ms_controls(adapter, off, &ms); |
af19b491 AKS |
1223 | |
1224 | if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX)) | |
15087c2b SC |
1225 | return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window, |
1226 | ms.off, &data, 1); | |
af19b491 | 1227 | |
b47acacd | 1228 | off8 = off & ~0xf; |
af19b491 | 1229 | |
b1fc6d3c | 1230 | mutex_lock(&adapter->ahw->mem_lock); |
af19b491 | 1231 | |
15087c2b SC |
1232 | qlcnic_ind_wr(adapter, ms.low, off8); |
1233 | qlcnic_ind_wr(adapter, ms.hi, 0); | |
af19b491 | 1234 | |
15087c2b SC |
1235 | qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE); |
1236 | qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE); | |
af19b491 | 1237 | |
b47acacd | 1238 | for (j = 0; j < MAX_CTL_CHECK; j++) { |
15087c2b | 1239 | temp = qlcnic_ind_rd(adapter, ms.control); |
b47acacd DP |
1240 | if ((temp & TA_CTL_BUSY) == 0) |
1241 | break; | |
1242 | } | |
af19b491 | 1243 | |
b47acacd DP |
1244 | if (j >= MAX_CTL_CHECK) { |
1245 | ret = -EIO; | |
1246 | goto done; | |
af19b491 AKS |
1247 | } |
1248 | ||
15087c2b SC |
1249 | /* This is the modify part of read-modify-write */ |
1250 | qlcnic_ind_wr(adapter, ms.wd[0], qlcnic_ind_rd(adapter, ms.rd[0])); | |
1251 | qlcnic_ind_wr(adapter, ms.wd[1], qlcnic_ind_rd(adapter, ms.rd[1])); | |
1252 | /* This is the write part of read-modify-write */ | |
1253 | qlcnic_ind_wr(adapter, ms.wd[2], data & 0xffffffff); | |
1254 | qlcnic_ind_wr(adapter, ms.wd[3], (data >> 32) & 0xffffffff); | |
af19b491 | 1255 | |
15087c2b SC |
1256 | qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_ENABLE); |
1257 | qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_START); | |
af19b491 AKS |
1258 | |
1259 | for (j = 0; j < MAX_CTL_CHECK; j++) { | |
15087c2b | 1260 | temp = qlcnic_ind_rd(adapter, ms.control); |
af19b491 AKS |
1261 | if ((temp & TA_CTL_BUSY) == 0) |
1262 | break; | |
1263 | } | |
1264 | ||
1265 | if (j >= MAX_CTL_CHECK) { | |
1266 | if (printk_ratelimit()) | |
1267 | dev_err(&adapter->pdev->dev, | |
1268 | "failed to write through agent\n"); | |
1269 | ret = -EIO; | |
1270 | } else | |
1271 | ret = 0; | |
1272 | ||
1273 | done: | |
b1fc6d3c | 1274 | mutex_unlock(&adapter->ahw->mem_lock); |
af19b491 AKS |
1275 | |
1276 | return ret; | |
1277 | } | |
1278 | ||
15087c2b | 1279 | int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data) |
af19b491 AKS |
1280 | { |
1281 | int j, ret; | |
1282 | u32 temp, off8; | |
b47acacd | 1283 | u64 val; |
15087c2b | 1284 | struct qlcnic_ms_reg_ctrl ms; |
af19b491 AKS |
1285 | |
1286 | /* Only 64-bit aligned access */ | |
1287 | if (off & 7) | |
1288 | return -EIO; | |
15087c2b SC |
1289 | if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET, |
1290 | QLCNIC_ADDR_QDR_NET_MAX) || | |
1291 | ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, | |
1292 | QLCNIC_ADDR_DDR_NET_MAX))) | |
1293 | return -EIO; | |
af19b491 | 1294 | |
15087c2b SC |
1295 | memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl)); |
1296 | qlcnic_set_ms_controls(adapter, off, &ms); | |
af19b491 | 1297 | |
15087c2b SC |
1298 | if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX)) |
1299 | return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window, | |
1300 | ms.off, data, 0); | |
af19b491 | 1301 | |
15087c2b | 1302 | mutex_lock(&adapter->ahw->mem_lock); |
af19b491 | 1303 | |
b47acacd | 1304 | off8 = off & ~0xf; |
af19b491 | 1305 | |
15087c2b SC |
1306 | qlcnic_ind_wr(adapter, ms.low, off8); |
1307 | qlcnic_ind_wr(adapter, ms.hi, 0); | |
af19b491 | 1308 | |
15087c2b SC |
1309 | qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE); |
1310 | qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE); | |
af19b491 AKS |
1311 | |
1312 | for (j = 0; j < MAX_CTL_CHECK; j++) { | |
15087c2b | 1313 | temp = qlcnic_ind_rd(adapter, ms.control); |
af19b491 AKS |
1314 | if ((temp & TA_CTL_BUSY) == 0) |
1315 | break; | |
1316 | } | |
1317 | ||
1318 | if (j >= MAX_CTL_CHECK) { | |
1319 | if (printk_ratelimit()) | |
1320 | dev_err(&adapter->pdev->dev, | |
1321 | "failed to read through agent\n"); | |
1322 | ret = -EIO; | |
1323 | } else { | |
af19b491 | 1324 | |
15087c2b | 1325 | temp = qlcnic_ind_rd(adapter, ms.rd[3]); |
af19b491 | 1326 | val = (u64)temp << 32; |
15087c2b | 1327 | val |= qlcnic_ind_rd(adapter, ms.rd[2]); |
af19b491 AKS |
1328 | *data = val; |
1329 | ret = 0; | |
1330 | } | |
1331 | ||
b1fc6d3c | 1332 | mutex_unlock(&adapter->ahw->mem_lock); |
af19b491 AKS |
1333 | |
1334 | return ret; | |
1335 | } | |
1336 | ||
7e2cf4fe | 1337 | int qlcnic_82xx_get_board_info(struct qlcnic_adapter *adapter) |
af19b491 AKS |
1338 | { |
1339 | int offset, board_type, magic; | |
1340 | struct pci_dev *pdev = adapter->pdev; | |
1341 | ||
1342 | offset = QLCNIC_FW_MAGIC_OFFSET; | |
1343 | if (qlcnic_rom_fast_read(adapter, offset, &magic)) | |
1344 | return -EIO; | |
1345 | ||
1346 | if (magic != QLCNIC_BDINFO_MAGIC) { | |
1347 | dev_err(&pdev->dev, "invalid board config, magic=%08x\n", | |
1348 | magic); | |
1349 | return -EIO; | |
1350 | } | |
1351 | ||
1352 | offset = QLCNIC_BRDTYPE_OFFSET; | |
1353 | if (qlcnic_rom_fast_read(adapter, offset, &board_type)) | |
1354 | return -EIO; | |
1355 | ||
b1fc6d3c | 1356 | adapter->ahw->board_type = board_type; |
af19b491 | 1357 | |
ff1b1bf8 | 1358 | if (board_type == QLCNIC_BRDTYPE_P3P_4_GB_MM) { |
af19b491 AKS |
1359 | u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I); |
1360 | if ((gpio & 0x8000) == 0) | |
ff1b1bf8 | 1361 | board_type = QLCNIC_BRDTYPE_P3P_10G_TP; |
af19b491 AKS |
1362 | } |
1363 | ||
1364 | switch (board_type) { | |
ff1b1bf8 SV |
1365 | case QLCNIC_BRDTYPE_P3P_HMEZ: |
1366 | case QLCNIC_BRDTYPE_P3P_XG_LOM: | |
1367 | case QLCNIC_BRDTYPE_P3P_10G_CX4: | |
1368 | case QLCNIC_BRDTYPE_P3P_10G_CX4_LP: | |
1369 | case QLCNIC_BRDTYPE_P3P_IMEZ: | |
1370 | case QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS: | |
1371 | case QLCNIC_BRDTYPE_P3P_10G_SFP_CT: | |
1372 | case QLCNIC_BRDTYPE_P3P_10G_SFP_QT: | |
1373 | case QLCNIC_BRDTYPE_P3P_10G_XFP: | |
1374 | case QLCNIC_BRDTYPE_P3P_10000_BASE_T: | |
b1fc6d3c | 1375 | adapter->ahw->port_type = QLCNIC_XGBE; |
af19b491 | 1376 | break; |
ff1b1bf8 SV |
1377 | case QLCNIC_BRDTYPE_P3P_REF_QG: |
1378 | case QLCNIC_BRDTYPE_P3P_4_GB: | |
1379 | case QLCNIC_BRDTYPE_P3P_4_GB_MM: | |
b1fc6d3c | 1380 | adapter->ahw->port_type = QLCNIC_GBE; |
af19b491 | 1381 | break; |
ff1b1bf8 | 1382 | case QLCNIC_BRDTYPE_P3P_10G_TP: |
b1fc6d3c | 1383 | adapter->ahw->port_type = (adapter->portnum < 2) ? |
af19b491 AKS |
1384 | QLCNIC_XGBE : QLCNIC_GBE; |
1385 | break; | |
1386 | default: | |
1387 | dev_err(&pdev->dev, "unknown board type %x\n", board_type); | |
b1fc6d3c | 1388 | adapter->ahw->port_type = QLCNIC_XGBE; |
af19b491 AKS |
1389 | break; |
1390 | } | |
1391 | ||
1392 | return 0; | |
1393 | } | |
1394 | ||
1395 | int | |
1396 | qlcnic_wol_supported(struct qlcnic_adapter *adapter) | |
1397 | { | |
1398 | u32 wol_cfg; | |
1399 | ||
1400 | wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV); | |
1401 | if (wol_cfg & (1UL << adapter->portnum)) { | |
1402 | wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG); | |
1403 | if (wol_cfg & (1 << adapter->portnum)) | |
1404 | return 1; | |
1405 | } | |
1406 | ||
1407 | return 0; | |
1408 | } | |
897d3596 | 1409 | |
7e2cf4fe | 1410 | int qlcnic_82xx_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate) |
897d3596 SC |
1411 | { |
1412 | struct qlcnic_nic_req req; | |
1413 | int rv; | |
1414 | u64 word; | |
1415 | ||
1416 | memset(&req, 0, sizeof(struct qlcnic_nic_req)); | |
1417 | req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); | |
1418 | ||
1419 | word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16); | |
1420 | req.req_hdr = cpu_to_le64(word); | |
1421 | ||
dbab22c1 | 1422 | req.words[0] = cpu_to_le64(((u64)rate << 32) | adapter->portnum); |
897d3596 SC |
1423 | req.words[1] = cpu_to_le64(state); |
1424 | ||
1425 | rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); | |
1426 | if (rv) | |
1427 | dev_err(&adapter->pdev->dev, "LED configuration failed.\n"); | |
1428 | ||
1429 | return rv; | |
1430 | } | |
7e2cf4fe SC |
1431 | |
1432 | void qlcnic_82xx_get_func_no(struct qlcnic_adapter *adapter) | |
1433 | { | |
1434 | void __iomem *msix_base_addr; | |
1435 | u32 func; | |
1436 | u32 msix_base; | |
1437 | ||
1438 | pci_read_config_dword(adapter->pdev, QLCNIC_MSIX_TABLE_OFFSET, &func); | |
1439 | msix_base_addr = adapter->ahw->pci_base0 + QLCNIC_MSIX_BASE; | |
1440 | msix_base = readl(msix_base_addr); | |
1441 | func = (func - msix_base) / QLCNIC_MSIX_TBL_PGSIZE; | |
1442 | adapter->ahw->pci_func = func; | |
1443 | } | |
1444 | ||
1445 | void qlcnic_82xx_read_crb(struct qlcnic_adapter *adapter, char *buf, | |
1446 | loff_t offset, size_t size) | |
1447 | { | |
1448 | u32 data; | |
1449 | u64 qmdata; | |
1450 | ||
1451 | if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) { | |
1452 | qlcnic_pci_camqm_read_2M(adapter, offset, &qmdata); | |
1453 | memcpy(buf, &qmdata, size); | |
1454 | } else { | |
1455 | data = QLCRD32(adapter, offset); | |
1456 | memcpy(buf, &data, size); | |
1457 | } | |
1458 | } | |
1459 | ||
1460 | void qlcnic_82xx_write_crb(struct qlcnic_adapter *adapter, char *buf, | |
1461 | loff_t offset, size_t size) | |
1462 | { | |
1463 | u32 data; | |
1464 | u64 qmdata; | |
1465 | ||
1466 | if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) { | |
1467 | memcpy(&qmdata, buf, size); | |
1468 | qlcnic_pci_camqm_write_2M(adapter, offset, qmdata); | |
1469 | } else { | |
1470 | memcpy(&data, buf, size); | |
1471 | QLCWR32(adapter, offset, data); | |
1472 | } | |
1473 | } | |
1474 | ||
1475 | int qlcnic_82xx_api_lock(struct qlcnic_adapter *adapter) | |
1476 | { | |
1477 | return qlcnic_pcie_sem_lock(adapter, 5, 0); | |
1478 | } | |
1479 | ||
1480 | void qlcnic_82xx_api_unlock(struct qlcnic_adapter *adapter) | |
1481 | { | |
1482 | qlcnic_pcie_sem_unlock(adapter, 5); | |
1483 | } |