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qlcnic: 83xx register dump routines
[linux-2.6-block.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic_hw.c
CommitLineData
af19b491 1/*
40839129
SV		 2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2010 QLogic Corporation
af19b491 4 *
40839129 5 * See LICENSE.qlcnic for copyright and licensing details.
af19b491
AKS		 6 */
7
8#include "qlcnic.h"
15087c2b 9#include "qlcnic_hdr.h"
af19b491 10
5a0e3ad6 11#include <linux/slab.h>
af19b491 12#include <net/ip.h>
18f2f616 13#include <linux/bitops.h>
af19b491
AKS		 14
15#define MASK(n) ((1ULL<<(n))-1)
16#define OCM_WIN_P3P(addr) (addr & 0xffc0000)
17
18#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
19
20#define CRB_BLK(off) ((off >> 20) & 0x3f)
21#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
22#define CRB_WINDOW_2M (0x130060)
23#define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
24#define CRB_INDIRECT_2M (0x1e0000UL)
25
15087c2b
SC		 26struct qlcnic_ms_reg_ctrl {
27 u32 ocm_window;
28 u32 control;
29 u32 hi;
30 u32 low;
31 u32 rd[4];
32 u32 wd[4];
33 u64 off;
34};
af19b491
AKS		 35
36#ifndef readq
37static inline u64 readq(void __iomem *addr)
38{
39 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
40}
41#endif
42
43#ifndef writeq
44static inline void writeq(u64 val, void __iomem *addr)
45{
46 writel(((u32) (val)), (addr));
47 writel(((u32) (val >> 32)), (addr + 4));
48}
49#endif
50
c477ebd8 51static struct crb_128M_2M_block_map
af19b491
AKS		 52crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
53 {{{0, 0, 0, 0} } }, /* 0: PCI */
54 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
55 {1, 0x0110000, 0x0120000, 0x130000},
56 {1, 0x0120000, 0x0122000, 0x124000},
57 {1, 0x0130000, 0x0132000, 0x126000},
58 {1, 0x0140000, 0x0142000, 0x128000},
59 {1, 0x0150000, 0x0152000, 0x12a000},
60 {1, 0x0160000, 0x0170000, 0x110000},
61 {1, 0x0170000, 0x0172000, 0x12e000},
62 {0, 0x0000000, 0x0000000, 0x000000},
63 {0, 0x0000000, 0x0000000, 0x000000},
64 {0, 0x0000000, 0x0000000, 0x000000},
65 {0, 0x0000000, 0x0000000, 0x000000},
66 {0, 0x0000000, 0x0000000, 0x000000},
67 {0, 0x0000000, 0x0000000, 0x000000},
68 {1, 0x01e0000, 0x01e0800, 0x122000},
69 {0, 0x0000000, 0x0000000, 0x000000} } },
70 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
71 {{{0, 0, 0, 0} } }, /* 3: */
72 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
73 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
74 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
75 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
76 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
77 {0, 0x0000000, 0x0000000, 0x000000},
78 {0, 0x0000000, 0x0000000, 0x000000},
79 {0, 0x0000000, 0x0000000, 0x000000},
80 {0, 0x0000000, 0x0000000, 0x000000},
81 {0, 0x0000000, 0x0000000, 0x000000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {1, 0x08f0000, 0x08f2000, 0x172000} } },
92 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {0, 0x0000000, 0x0000000, 0x000000},
95 {0, 0x0000000, 0x0000000, 0x000000},
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {1, 0x09f0000, 0x09f2000, 0x176000} } },
108 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {0, 0x0000000, 0x0000000, 0x000000},
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
124 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
140 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
141 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
142 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
143 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
144 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
145 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
146 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
147 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
148 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
149 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
150 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
151 {{{0, 0, 0, 0} } }, /* 23: */
152 {{{0, 0, 0, 0} } }, /* 24: */
153 {{{0, 0, 0, 0} } }, /* 25: */
154 {{{0, 0, 0, 0} } }, /* 26: */
155 {{{0, 0, 0, 0} } }, /* 27: */
156 {{{0, 0, 0, 0} } }, /* 28: */
157 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
158 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
159 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
160 {{{0} } }, /* 32: PCI */
161 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
162 {1, 0x2110000, 0x2120000, 0x130000},
163 {1, 0x2120000, 0x2122000, 0x124000},
164 {1, 0x2130000, 0x2132000, 0x126000},
165 {1, 0x2140000, 0x2142000, 0x128000},
166 {1, 0x2150000, 0x2152000, 0x12a000},
167 {1, 0x2160000, 0x2170000, 0x110000},
168 {1, 0x2170000, 0x2172000, 0x12e000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000} } },
177 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
178 {{{0} } }, /* 35: */
179 {{{0} } }, /* 36: */
180 {{{0} } }, /* 37: */
181 {{{0} } }, /* 38: */
182 {{{0} } }, /* 39: */
183 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
184 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
185 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
186 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
187 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
188 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
189 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
190 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
191 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
192 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
193 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
194 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
195 {{{0} } }, /* 52: */
196 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
197 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
198 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
199 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
200 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
201 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
202 {{{0} } }, /* 59: I2C0 */
203 {{{0} } }, /* 60: I2C1 */
204 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
205 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
206 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
207};
208
209/*
210 * top 12 bits of crb internal address (hub, agent)
211 */
212static const unsigned crb_hub_agt[64] = {
213 0,
214 QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
215 QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
216 QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
217 0,
218 QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
219 QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
220 QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
221 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
222 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
223 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
224 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
225 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
226 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
227 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
228 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
229 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
230 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
231 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
232 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
233 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
234 QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
235 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
236 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
237 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
238 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
239 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
240 0,
241 QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
242 QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
243 0,
244 QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
245 0,
246 QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
247 QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
248 0,
249 0,
250 0,
251 0,
252 0,
253 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
254 0,
255 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
256 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
257 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
258 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
259 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
260 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
261 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
262 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
263 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
264 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
265 0,
266 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
267 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
268 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
269 QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
270 0,
271 QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
272 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
273 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
274 0,
275 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
276 0,
277};
278
15087c2b
SC		 279static const u32 msi_tgt_status[8] = {
280 ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1,
281 ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3,
282 ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5,
283 ISR_INT_TARGET_STATUS_F6, ISR_INT_TARGET_STATUS_F7
284};
285
af19b491
AKS		 286/* PCI Windowing for DDR regions. */
287
288#define QLCNIC_PCIE_SEM_TIMEOUT 10000
289
15087c2b
SC		 290static void qlcnic_read_window_reg(u32 addr, void __iomem *bar0, u32 *data)
291{
292 u32 dest;
293 void __iomem *val;
294
295 dest = addr & 0xFFFF0000;
296 val = bar0 + QLCNIC_FW_DUMP_REG1;
297 writel(dest, val);
298 readl(val);
299 val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
300 *data = readl(val);
301}
302
303static void qlcnic_write_window_reg(u32 addr, void __iomem *bar0, u32 data)
304{
305 u32 dest;
306 void __iomem *val;
307
308 dest = addr & 0xFFFF0000;
309 val = bar0 + QLCNIC_FW_DUMP_REG1;
310 writel(dest, val);
311 readl(val);
312 val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
313 writel(data, val);
314 readl(val);
315}
316
af19b491
AKS		 317int
318qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
319{
320 int done = 0, timeout = 0;
321
322 while (!done) {
323 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)));
324 if (done == 1)
325 break;
65b5b420
AKS		 326 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) {
327 dev_err(&adapter->pdev->dev,
091754a1
SC		 328 "Failed to acquire sem=%d lock; holdby=%d\n",
329 sem, id_reg ? QLCRD32(adapter, id_reg) : -1);
af19b491 330 return -EIO;
65b5b420 331 }
af19b491
AKS		 332 msleep(1);
333 }
334
335 if (id_reg)
336 QLCWR32(adapter, id_reg, adapter->portnum);
337
338 return 0;
339}
340
341void
342qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
343{
344 QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
345}
346
7f966452 347int qlcnic_ind_rd(struct qlcnic_adapter *adapter, u32 addr)
15087c2b
SC		 348{
349 u32 data;
350
351 if (qlcnic_82xx_check(adapter))
352 qlcnic_read_window_reg(addr, adapter->ahw->pci_base0, &data);
7f966452
SC		 353 else {
354 data = qlcnic_83xx_rd_reg_indirect(adapter, addr);
355 if (data == -EIO)
356 return -EIO;
357 }
15087c2b
SC		 358 return data;
359}
360
7f966452 361void qlcnic_ind_wr(struct qlcnic_adapter *adapter, u32 addr, u32 data)
15087c2b
SC		 362{
363 if (qlcnic_82xx_check(adapter))
364 qlcnic_write_window_reg(addr, adapter->ahw->pci_base0, data);
7f966452
SC		 365 else
366 qlcnic_83xx_wrt_reg_indirect(adapter, addr, data);
15087c2b
SC		 367}
368
af19b491
AKS		 369static int
370qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
371 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
372{
5d17f36b 373 u32 i, producer;
af19b491
AKS		 374 struct qlcnic_cmd_buffer *pbuf;
375 struct cmd_desc_type0 *cmd_desc;
376 struct qlcnic_host_tx_ring *tx_ring;
377
378 i = 0;
379
8a15ad1f 380 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
af19b491
AKS		 381 return -EIO;
382
383 tx_ring = adapter->tx_ring;
384 __netif_tx_lock_bh(tx_ring->txq);
385
386 producer = tx_ring->producer;
af19b491
AKS		 387
388 if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
389 netif_tx_stop_queue(tx_ring->txq);
ef71ff83
RB		 390 smp_mb();
391 if (qlcnic_tx_avail(tx_ring) > nr_desc) {
392 if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH)
393 netif_tx_wake_queue(tx_ring->txq);
394 } else {
395 adapter->stats.xmit_off++;
396 __netif_tx_unlock_bh(tx_ring->txq);
397 return -EBUSY;
398 }
af19b491
AKS		 399 }
400
401 do {
402 cmd_desc = &cmd_desc_arr[i];
403
404 pbuf = &tx_ring->cmd_buf_arr[producer];
405 pbuf->skb = NULL;
406 pbuf->frag_count = 0;
407
408 memcpy(&tx_ring->desc_head[producer],
5d17f36b 409 cmd_desc, sizeof(struct cmd_desc_type0));
af19b491
AKS		 410
411 producer = get_next_index(producer, tx_ring->num_desc);
412 i++;
413
414 } while (i != nr_desc);
415
416 tx_ring->producer = producer;
417
5ad6ff9d 418 qlcnic_update_cmd_producer(tx_ring);
af19b491
AKS		 419
420 __netif_tx_unlock_bh(tx_ring->txq);
421
422 return 0;
423}
424
7e2cf4fe
SC		 425int qlcnic_82xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
426 __le16 vlan_id, u8 op)
af19b491
AKS		 427{
428 struct qlcnic_nic_req req;
429 struct qlcnic_mac_req *mac_req;
7e56cac4 430 struct qlcnic_vlan_req *vlan_req;
af19b491
AKS		 431 u64 word;
432
433 memset(&req, 0, sizeof(struct qlcnic_nic_req));
434 req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
435
436 word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
437 req.req_hdr = cpu_to_le64(word);
438
439 mac_req = (struct qlcnic_mac_req *)&req.words[0];
440 mac_req->op = op;
441 memcpy(mac_req->mac_addr, addr, 6);
442
7e56cac4
SC		 443 vlan_req = (struct qlcnic_vlan_req *)&req.words[1];
444 vlan_req->vlan_id = vlan_id;
03c5d770 445
af19b491
AKS		 446 return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
447}
448
215faf9c 449static int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, const u8 *addr)
af19b491
AKS		 450{
451 struct list_head *head;
452 struct qlcnic_mac_list_s *cur;
453
454 /* look up if already exists */
9ab17b39 455 list_for_each(head, &adapter->mac_list) {
af19b491 456 cur = list_entry(head, struct qlcnic_mac_list_s, list);
9ab17b39 457 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
af19b491 458 return 0;
af19b491
AKS		 459 }
460
461 cur = kzalloc(sizeof(struct qlcnic_mac_list_s), GFP_ATOMIC);
462 if (cur == NULL) {
463 dev_err(&adapter->netdev->dev,
464 "failed to add mac address filter\n");
465 return -ENOMEM;
466 }
467 memcpy(cur->mac_addr, addr, ETH_ALEN);
af19b491 468
42f65cba 469 if (qlcnic_sre_macaddr_change(adapter,
03c5d770 470 cur->mac_addr, 0, QLCNIC_MAC_ADD)) {
42f65cba
AKS		 471 kfree(cur);
472 return -EIO;
473 }
474
475 list_add_tail(&cur->list, &adapter->mac_list);
476 return 0;
af19b491
AKS		 477}
478
479void qlcnic_set_multi(struct net_device *netdev)
480{
481 struct qlcnic_adapter *adapter = netdev_priv(netdev);
22bedad3 482 struct netdev_hw_addr *ha;
215faf9c
JP		 483 static const u8 bcast_addr[ETH_ALEN] = {
484 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
485 };
af19b491 486 u32 mode = VPORT_MISS_MODE_DROP;
af19b491 487
8a15ad1f 488 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
a55cb185
AKS		 489 return;
490
9ab17b39
SC		 491 qlcnic_nic_add_mac(adapter, adapter->mac_addr);
492 qlcnic_nic_add_mac(adapter, bcast_addr);
af19b491
AKS		 493
494 if (netdev->flags & IFF_PROMISC) {
ee07c1a7
RB		 495 if (!(adapter->flags & QLCNIC_PROMISC_DISABLED))
496 mode = VPORT_MISS_MODE_ACCEPT_ALL;
af19b491
AKS		 497 goto send_fw_cmd;
498 }
499
500 if ((netdev->flags & IFF_ALLMULTI) ||
79788450 501 (netdev_mc_count(netdev) > adapter->ahw->max_mc_count)) {
af19b491
AKS		 502 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
503 goto send_fw_cmd;
504 }
505
4cd24eaf 506 if (!netdev_mc_empty(netdev)) {
22bedad3
JP		 507 netdev_for_each_mc_addr(ha, netdev) {
508 qlcnic_nic_add_mac(adapter, ha->addr);
af19b491
AKS		 509 }
510 }
511
512send_fw_cmd:
e5dcf6dc
SC		 513 if (mode == VPORT_MISS_MODE_ACCEPT_ALL) {
514 qlcnic_alloc_lb_filters_mem(adapter);
515 adapter->mac_learn = 1;
516 } else {
517 adapter->mac_learn = 0;
518 }
519
af19b491 520 qlcnic_nic_set_promisc(adapter, mode);
af19b491
AKS		 521}
522
7e2cf4fe 523int qlcnic_82xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
af19b491
AKS		 524{
525 struct qlcnic_nic_req req;
526 u64 word;
527
528 memset(&req, 0, sizeof(struct qlcnic_nic_req));
529
530 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
531
b1fc6d3c 532 word = QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE |
af19b491
AKS		 533 ((u64)adapter->portnum << 16);
534 req.req_hdr = cpu_to_le64(word);
535
536 req.words[0] = cpu_to_le64(mode);
537
538 return qlcnic_send_cmd_descs(adapter,
539 (struct cmd_desc_type0 *)&req, 1);
540}
541
542void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
543{
544 struct qlcnic_mac_list_s *cur;
545 struct list_head *head = &adapter->mac_list;
546
547 while (!list_empty(head)) {
548 cur = list_entry(head->next, struct qlcnic_mac_list_s, list);
549 qlcnic_sre_macaddr_change(adapter,
03c5d770 550 cur->mac_addr, 0, QLCNIC_MAC_DEL);
af19b491
AKS		 551 list_del(&cur->list);
552 kfree(cur);
553 }
554}
555
b5e5492c
AKS		 556void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter)
557{
558 struct qlcnic_filter *tmp_fil;
559 struct hlist_node *tmp_hnode, *n;
560 struct hlist_head *head;
7f966452
SC		 561 int i, time;
562 u8 cmd;
b5e5492c 563
7f966452 564 for (i = 0; i < adapter->fhash.fbucket_size; i++) {
b5e5492c 565 head = &(adapter->fhash.fhead[i]);
7f966452
SC		 566 hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode) {
567 cmd = tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
568 QLCNIC_MAC_DEL;
569 time = tmp_fil->ftime;
570 if (jiffies > (QLCNIC_FILTER_AGE * HZ + time)) {
b5e5492c 571 qlcnic_sre_macaddr_change(adapter,
7f966452
SC		 572 tmp_fil->faddr,
573 tmp_fil->vlan_id,
574 cmd);
b5e5492c
AKS		 575 spin_lock_bh(&adapter->mac_learn_lock);
576 adapter->fhash.fnum--;
577 hlist_del(&tmp_fil->fnode);
578 spin_unlock_bh(&adapter->mac_learn_lock);
579 kfree(tmp_fil);
580 }
581 }
582 }
583}
584
585void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter)
586{
587 struct qlcnic_filter *tmp_fil;
588 struct hlist_node *tmp_hnode, *n;
589 struct hlist_head *head;
590 int i;
7f966452 591 u8 cmd;
b5e5492c 592
7f966452 593 for (i = 0; i < adapter->fhash.fbucket_size; i++) {
b5e5492c 594 head = &(adapter->fhash.fhead[i]);
b5e5492c 595 hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode) {
7f966452
SC		 596 cmd = tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
597 QLCNIC_MAC_DEL;
598 qlcnic_sre_macaddr_change(adapter,
599 tmp_fil->faddr,
600 tmp_fil->vlan_id,
601 cmd);
b5e5492c
AKS		 602 spin_lock_bh(&adapter->mac_learn_lock);
603 adapter->fhash.fnum--;
604 hlist_del(&tmp_fil->fnode);
605 spin_unlock_bh(&adapter->mac_learn_lock);
606 kfree(tmp_fil);
607 }
608 }
609}
610
6d973cb1 611static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u8 flag)
22c8c934
SC		 612{
613 struct qlcnic_nic_req req;
614 int rv;
615
616 memset(&req, 0, sizeof(struct qlcnic_nic_req));
617
618 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
619 req.req_hdr = cpu_to_le64(QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
620 ((u64) adapter->portnum << 16) | ((u64) 0x1 << 32));
621
622 req.words[0] = cpu_to_le64(flag);
623
624 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
625 if (rv != 0)
626 dev_err(&adapter->pdev->dev, "%sting loopback mode failed\n",
627 flag ? "Set" : "Reset");
628 return rv;
629}
630
7e2cf4fe 631int qlcnic_82xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
22c8c934
SC		 632{
633 if (qlcnic_set_fw_loopback(adapter, mode))
634 return -EIO;
635
7e2cf4fe
SC		 636 if (qlcnic_nic_set_promisc(adapter,
637 VPORT_MISS_MODE_ACCEPT_ALL)) {
ad567b8f 638 qlcnic_set_fw_loopback(adapter, 0);
22c8c934
SC		 639 return -EIO;
640 }
641
642 msleep(1000);
643 return 0;
644}
645
7e2cf4fe 646int qlcnic_82xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
22c8c934 647{
22c8c934
SC		 648 struct net_device *netdev = adapter->netdev;
649
7e2cf4fe 650 mode = VPORT_MISS_MODE_DROP;
22c8c934
SC		 651 qlcnic_set_fw_loopback(adapter, 0);
652
653 if (netdev->flags & IFF_PROMISC)
654 mode = VPORT_MISS_MODE_ACCEPT_ALL;
655 else if (netdev->flags & IFF_ALLMULTI)
656 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
657
658 qlcnic_nic_set_promisc(adapter, mode);
659 msleep(1000);
7e2cf4fe 660 return 0;
22c8c934
SC		 661}
662
af19b491
AKS		 663/*
664 * Send the interrupt coalescing parameter set by ethtool to the card.
665 */
7e2cf4fe 666void qlcnic_82xx_config_intr_coalesce(struct qlcnic_adapter *adapter)
af19b491
AKS		 667{
668 struct qlcnic_nic_req req;
8816d009 669 int rv;
af19b491
AKS		 670
671 memset(&req, 0, sizeof(struct qlcnic_nic_req));
672
673 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
674
8816d009
AC		 675 req.req_hdr = cpu_to_le64(QLCNIC_CONFIG_INTR_COALESCE |
676 ((u64) adapter->portnum << 16));
af19b491 677
8816d009
AC		 678 req.words[0] = cpu_to_le64(((u64) adapter->ahw->coal.flag) << 32);
679 req.words[2] = cpu_to_le64(adapter->ahw->coal.rx_packets |
680 ((u64) adapter->ahw->coal.rx_time_us) << 16);
681 req.words[5] = cpu_to_le64(adapter->ahw->coal.timer_out |
682 ((u64) adapter->ahw->coal.type) << 32 |
683 ((u64) adapter->ahw->coal.sts_ring_mask) << 40);
af19b491
AKS		 684 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
685 if (rv != 0)
686 dev_err(&adapter->netdev->dev,
687 "Could not send interrupt coalescing parameters\n");
af19b491
AKS		 688}
689
7e2cf4fe 690int qlcnic_82xx_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
af19b491
AKS		 691{
692 struct qlcnic_nic_req req;
693 u64 word;
694 int rv;
695
b56421d0
RB		 696 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
697 return 0;
698
af19b491
AKS		 699 memset(&req, 0, sizeof(struct qlcnic_nic_req));
700
701 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
702
703 word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
704 req.req_hdr = cpu_to_le64(word);
705
706 req.words[0] = cpu_to_le64(enable);
707
708 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
709 if (rv != 0)
710 dev_err(&adapter->netdev->dev,
711 "Could not send configure hw lro request\n");
712
af19b491
AKS		 713 return rv;
714}
715
2e9d722d 716int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable)
af19b491
AKS		 717{
718 struct qlcnic_nic_req req;
719 u64 word;
720 int rv;
721
722 if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
723 return 0;
724
725 memset(&req, 0, sizeof(struct qlcnic_nic_req));
726
727 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
728
729 word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
730 ((u64)adapter->portnum << 16);
731 req.req_hdr = cpu_to_le64(word);
732
733 req.words[0] = cpu_to_le64(enable);
734
735 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
736 if (rv != 0)
737 dev_err(&adapter->netdev->dev,
738 "Could not send configure bridge mode request\n");
739
740 adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
741
742 return rv;
743}
744
745
746#define RSS_HASHTYPE_IP_TCP 0x3
747
7e2cf4fe 748int qlcnic_82xx_config_rss(struct qlcnic_adapter *adapter, int enable)
af19b491
AKS		 749{
750 struct qlcnic_nic_req req;
751 u64 word;
752 int i, rv;
753
215faf9c
JP		 754 static const u64 key[] = {
755 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
756 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
757 0x255b0ec26d5a56daULL
758 };
af19b491
AKS		 759
760 memset(&req, 0, sizeof(struct qlcnic_nic_req));
761 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
762
763 word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
764 req.req_hdr = cpu_to_le64(word);
765
766 /*
767 * RSS request:
768 * bits 3-0: hash_method
769 * 5-4: hash_type_ipv4
770 * 7-6: hash_type_ipv6
771 * 8: enable
772 * 9: use indirection table
773 * 47-10: reserved
774 * 63-48: indirection table mask
775 */
776 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
777 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
778 ((u64)(enable & 0x1) << 8) |
779 ((0x7ULL) << 48);
780 req.words[0] = cpu_to_le64(word);
781 for (i = 0; i < 5; i++)
782 req.words[i+1] = cpu_to_le64(key[i]);
783
784 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
785 if (rv != 0)
786 dev_err(&adapter->netdev->dev, "could not configure RSS\n");
787
788 return rv;
789}
790
7e2cf4fe
SC		 791void qlcnic_82xx_config_ipaddr(struct qlcnic_adapter *adapter,
792 __be32 ip, int cmd)
af19b491
AKS		 793{
794 struct qlcnic_nic_req req;
b501595c 795 struct qlcnic_ipaddr *ipa;
af19b491
AKS		 796 u64 word;
797 int rv;
798
799 memset(&req, 0, sizeof(struct qlcnic_nic_req));
800 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
801
802 word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
803 req.req_hdr = cpu_to_le64(word);
804
805 req.words[0] = cpu_to_le64(cmd);
b501595c
SC		 806 ipa = (struct qlcnic_ipaddr *)&req.words[1];
807 ipa->ipv4 = ip;
af19b491
AKS		 808
809 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
810 if (rv != 0)
811 dev_err(&adapter->netdev->dev,
812 "could not notify %s IP 0x%x reuqest\n",
813 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
af19b491
AKS		 814}
815
7e2cf4fe 816int qlcnic_82xx_linkevent_request(struct qlcnic_adapter *adapter, int enable)
af19b491
AKS		 817{
818 struct qlcnic_nic_req req;
819 u64 word;
820 int rv;
af19b491
AKS		 821 memset(&req, 0, sizeof(struct qlcnic_nic_req));
822 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
823
824 word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
825 req.req_hdr = cpu_to_le64(word);
826 req.words[0] = cpu_to_le64(enable | (enable << 8));
af19b491
AKS		 827 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
828 if (rv != 0)
829 dev_err(&adapter->netdev->dev,
830 "could not configure link notification\n");
831
832 return rv;
833}
834
835int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
836{
837 struct qlcnic_nic_req req;
838 u64 word;
839 int rv;
840
b56421d0
RB		 841 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
842 return 0;
843
af19b491
AKS		 844 memset(&req, 0, sizeof(struct qlcnic_nic_req));
845 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
846
847 word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
848 ((u64)adapter->portnum << 16) |
849 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
850
851 req.req_hdr = cpu_to_le64(word);
852
853 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
854 if (rv != 0)
855 dev_err(&adapter->netdev->dev,
856 "could not cleanup lro flows\n");
857
858 return rv;
859}
860
861/*
862 * qlcnic_change_mtu - Change the Maximum Transfer Unit
863 * @returns 0 on success, negative on failure
864 */
865
866int qlcnic_change_mtu(struct net_device *netdev, int mtu)
867{
868 struct qlcnic_adapter *adapter = netdev_priv(netdev);
869 int rc = 0;
870
ff1b1bf8 871 if (mtu < P3P_MIN_MTU || mtu > P3P_MAX_MTU) {
0bd9e6a9 872 dev_err(&adapter->netdev->dev, "%d bytes < mtu < %d bytes"
ff1b1bf8 873 " not supported\n", P3P_MAX_MTU, P3P_MIN_MTU);
af19b491
AKS		 874 return -EINVAL;
875 }
876
877 rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
878
879 if (!rc)
880 netdev->mtu = mtu;
881
882 return rc;
883}
884
135d84a9 885
c8f44aff
MM		 886netdev_features_t qlcnic_fix_features(struct net_device *netdev,
887 netdev_features_t features)
135d84a9
MM		 888{
889 struct qlcnic_adapter *adapter = netdev_priv(netdev);
890
891 if ((adapter->flags & QLCNIC_ESWITCH_ENABLED)) {
c8f44aff 892 netdev_features_t changed = features ^ netdev->features;
135d84a9
MM		 893 features ^= changed & (NETIF_F_ALL_CSUM | NETIF_F_RXCSUM);
894 }
895
896 if (!(features & NETIF_F_RXCSUM))
897 features &= ~NETIF_F_LRO;
898
899 return features;
900}
901
902
c8f44aff 903int qlcnic_set_features(struct net_device *netdev, netdev_features_t features)
135d84a9
MM		 904{
905 struct qlcnic_adapter *adapter = netdev_priv(netdev);
c8f44aff 906 netdev_features_t changed = netdev->features ^ features;
135d84a9
MM		 907 int hw_lro = (features & NETIF_F_LRO) ? QLCNIC_LRO_ENABLED : 0;
908
909 if (!(changed & NETIF_F_LRO))
910 return 0;
911
912 netdev->features = features ^ NETIF_F_LRO;
913
914 if (qlcnic_config_hw_lro(adapter, hw_lro))
915 return -EIO;
916
917 if ((hw_lro == 0) && qlcnic_send_lro_cleanup(adapter))
918 return -EIO;
919
920 return 0;
921}
922
af19b491
AKS		 923/*
924 * Changes the CRB window to the specified window.
925 */
926 /* Returns < 0 if off is not valid,
927 * 1 if window access is needed. 'off' is set to offset from
928 * CRB space in 128M pci map
929 * 0 if no window access is needed. 'off' is set to 2M addr
930 * In: 'off' is offset from base in 128M pci map
931 */
15087c2b
SC		 932static int qlcnic_pci_get_crb_addr_2M(struct qlcnic_hardware_context *ahw,
933 ulong off, void __iomem **addr)
af19b491
AKS		 934{
935 const struct crb_128M_2M_sub_block_map *m;
936
937 if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
938 return -EINVAL;
939
940 off -= QLCNIC_PCI_CRBSPACE;
941
942 /*
943 * Try direct map
944 */
945 m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
946
947 if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
15087c2b 948 *addr = ahw->pci_base0 + m->start_2M +
af19b491
AKS		 949 (off - m->start_128M);
950 return 0;
951 }
952
953 /*
954 * Not in direct map, use crb window
955 */
15087c2b 956 *addr = ahw->pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
af19b491
AKS		 957 return 1;
958}
959
960/*
961 * In: 'off' is offset from CRB space in 128M pci map
962 * Out: 'off' is 2M pci map addr
963 * side effect: lock crb window
964 */
4de57826 965static int
af19b491
AKS		 966qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
967{
968 u32 window;
b1fc6d3c 969 void __iomem *addr = adapter->ahw->pci_base0 + CRB_WINDOW_2M;
af19b491
AKS		 970
971 off -= QLCNIC_PCI_CRBSPACE;
972
973 window = CRB_HI(off);
4de57826
AKS		 974 if (window == 0) {
975 dev_err(&adapter->pdev->dev, "Invalid offset 0x%lx\n", off);
976 return -EIO;
977 }
af19b491 978
af19b491
AKS		 979 writel(window, addr);
980 if (readl(addr) != window) {
981 if (printk_ratelimit())
982 dev_warn(&adapter->pdev->dev,
983 "failed to set CRB window to %d off 0x%lx\n",
984 window, off);
4de57826 985 return -EIO;
af19b491 986 }
4de57826 987 return 0;
af19b491
AKS		 988}
989
7e2cf4fe
SC		 990int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off,
991 u32 data)
af19b491
AKS		 992{
993 unsigned long flags;
994 int rv;
995 void __iomem *addr = NULL;
996
15087c2b 997 rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr);
af19b491
AKS		 998
999 if (rv == 0) {
1000 writel(data, addr);
1001 return 0;
1002 }
1003
1004 if (rv > 0) {
1005 /* indirect access */
b1fc6d3c 1006 write_lock_irqsave(&adapter->ahw->crb_lock, flags);
af19b491 1007 crb_win_lock(adapter);
4de57826
AKS		 1008 rv = qlcnic_pci_set_crbwindow_2M(adapter, off);
1009 if (!rv)
1010 writel(data, addr);
af19b491 1011 crb_win_unlock(adapter);
b1fc6d3c 1012 write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
4de57826 1013 return rv;
af19b491
AKS		 1014 }
1015
1016 dev_err(&adapter->pdev->dev,
1017 "%s: invalid offset: 0x%016lx\n", __func__, off);
1018 dump_stack();
1019 return -EIO;
1020}
1021
7e2cf4fe 1022int qlcnic_82xx_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off)
af19b491
AKS		 1023{
1024 unsigned long flags;
1025 int rv;
4de57826 1026 u32 data = -1;
af19b491
AKS		 1027 void __iomem *addr = NULL;
1028
15087c2b 1029 rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr);
af19b491
AKS		 1030
1031 if (rv == 0)
1032 return readl(addr);
1033
1034 if (rv > 0) {
1035 /* indirect access */
b1fc6d3c 1036 write_lock_irqsave(&adapter->ahw->crb_lock, flags);
af19b491 1037 crb_win_lock(adapter);
4de57826
AKS		 1038 if (!qlcnic_pci_set_crbwindow_2M(adapter, off))
1039 data = readl(addr);
af19b491 1040 crb_win_unlock(adapter);
b1fc6d3c 1041 write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
af19b491
AKS		 1042 return data;
1043 }
1044
1045 dev_err(&adapter->pdev->dev,
1046 "%s: invalid offset: 0x%016lx\n", __func__, off);
1047 dump_stack();
1048 return -1;
1049}
1050
15087c2b
SC		 1051void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *ahw,
1052 u32 offset)
af19b491
AKS		 1053{
1054 void __iomem *addr = NULL;
1055
15087c2b 1056 WARN_ON(qlcnic_pci_get_crb_addr_2M(ahw, offset, &addr));
af19b491
AKS		 1057
1058 return addr;
1059}
1060
15087c2b
SC		 1061static int qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter,
1062 u32 window, u64 off, u64 *data, int op)
af19b491 1063{
0c39aa48 1064 void __iomem *addr;
af19b491
AKS		 1065 u32 start;
1066
b1fc6d3c 1067 mutex_lock(&adapter->ahw->mem_lock);
af19b491 1068
15087c2b
SC		 1069 writel(window, adapter->ahw->ocm_win_crb);
1070 /* read back to flush */
1071 readl(adapter->ahw->ocm_win_crb);
1072 start = QLCNIC_PCI_OCM0_2M + off;
af19b491 1073
b1fc6d3c 1074 addr = adapter->ahw->pci_base0 + start;
af19b491 1075
af19b491
AKS		 1076 if (op == 0) /* read */
1077 *data = readq(addr);
1078 else /* write */
1079 writeq(*data, addr);
1080
15087c2b
SC		 1081 /* Set window to 0 */
1082 writel(0, adapter->ahw->ocm_win_crb);
1083 readl(adapter->ahw->ocm_win_crb);
af19b491 1084
15087c2b
SC		 1085 mutex_unlock(&adapter->ahw->mem_lock);
1086 return 0;
af19b491
AKS		 1087}
1088
897e8c7c
DP		 1089void
1090qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
1091{
b1fc6d3c 1092 void __iomem *addr = adapter->ahw->pci_base0 +
897e8c7c
DP		 1093 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
1094
b1fc6d3c 1095 mutex_lock(&adapter->ahw->mem_lock);
897e8c7c 1096 *data = readq(addr);
b1fc6d3c 1097 mutex_unlock(&adapter->ahw->mem_lock);
897e8c7c
DP		 1098}
1099
1100void
1101qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
1102{
b1fc6d3c 1103 void __iomem *addr = adapter->ahw->pci_base0 +
897e8c7c
DP		 1104 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
1105
b1fc6d3c 1106 mutex_lock(&adapter->ahw->mem_lock);
897e8c7c 1107 writeq(data, addr);
b1fc6d3c 1108 mutex_unlock(&adapter->ahw->mem_lock);
897e8c7c
DP		 1109}
1110
15087c2b
SC		 1111
1112
1113/* Set MS memory control data for different adapters */
1114static void qlcnic_set_ms_controls(struct qlcnic_adapter *adapter, u64 off,
1115 struct qlcnic_ms_reg_ctrl *ms)
1116{
1117 ms->control = QLCNIC_MS_CTRL;
1118 ms->low = QLCNIC_MS_ADDR_LO;
1119 ms->hi = QLCNIC_MS_ADDR_HI;
1120 if (off & 0xf) {
1121 ms->wd[0] = QLCNIC_MS_WRTDATA_LO;
1122 ms->rd[0] = QLCNIC_MS_RDDATA_LO;
1123 ms->wd[1] = QLCNIC_MS_WRTDATA_HI;
1124 ms->rd[1] = QLCNIC_MS_RDDATA_HI;
1125 ms->wd[2] = QLCNIC_MS_WRTDATA_ULO;
1126 ms->wd[3] = QLCNIC_MS_WRTDATA_UHI;
1127 ms->rd[2] = QLCNIC_MS_RDDATA_ULO;
1128 ms->rd[3] = QLCNIC_MS_RDDATA_UHI;
1129 } else {
1130 ms->wd[0] = QLCNIC_MS_WRTDATA_ULO;
1131 ms->rd[0] = QLCNIC_MS_RDDATA_ULO;
1132 ms->wd[1] = QLCNIC_MS_WRTDATA_UHI;
1133 ms->rd[1] = QLCNIC_MS_RDDATA_UHI;
1134 ms->wd[2] = QLCNIC_MS_WRTDATA_LO;
1135 ms->wd[3] = QLCNIC_MS_WRTDATA_HI;
1136 ms->rd[2] = QLCNIC_MS_RDDATA_LO;
1137 ms->rd[3] = QLCNIC_MS_RDDATA_HI;
1138 }
1139
1140 ms->ocm_window = OCM_WIN_P3P(off);
1141 ms->off = GET_MEM_OFFS_2M(off);
1142}
1143
1144int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
af19b491 1145{
15087c2b 1146 int j, ret = 0;
af19b491 1147 u32 temp, off8;
15087c2b 1148 struct qlcnic_ms_reg_ctrl ms;
af19b491
AKS		 1149
1150 /* Only 64-bit aligned access */
1151 if (off & 7)
1152 return -EIO;
1153
15087c2b
SC		 1154 memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl));
1155 if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1156 QLCNIC_ADDR_QDR_NET_MAX) ||
1157 ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET,
1158 QLCNIC_ADDR_DDR_NET_MAX)))
1159 return -EIO;
af19b491 1160
15087c2b 1161 qlcnic_set_ms_controls(adapter, off, &ms);
af19b491
AKS		 1162
1163 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
15087c2b
SC		 1164 return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window,
1165 ms.off, &data, 1);
af19b491 1166
b47acacd 1167 off8 = off & ~0xf;
af19b491 1168
b1fc6d3c 1169 mutex_lock(&adapter->ahw->mem_lock);
af19b491 1170
15087c2b
SC		 1171 qlcnic_ind_wr(adapter, ms.low, off8);
1172 qlcnic_ind_wr(adapter, ms.hi, 0);
af19b491 1173
15087c2b
SC		 1174 qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE);
1175 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE);
af19b491 1176
b47acacd 1177 for (j = 0; j < MAX_CTL_CHECK; j++) {
15087c2b 1178 temp = qlcnic_ind_rd(adapter, ms.control);
b47acacd
DP		 1179 if ((temp & TA_CTL_BUSY) == 0)
1180 break;
1181 }
af19b491 1182
b47acacd
DP		 1183 if (j >= MAX_CTL_CHECK) {
1184 ret = -EIO;
1185 goto done;
af19b491
AKS		 1186 }
1187
15087c2b
SC		 1188 /* This is the modify part of read-modify-write */
1189 qlcnic_ind_wr(adapter, ms.wd[0], qlcnic_ind_rd(adapter, ms.rd[0]));
1190 qlcnic_ind_wr(adapter, ms.wd[1], qlcnic_ind_rd(adapter, ms.rd[1]));
1191 /* This is the write part of read-modify-write */
1192 qlcnic_ind_wr(adapter, ms.wd[2], data & 0xffffffff);
1193 qlcnic_ind_wr(adapter, ms.wd[3], (data >> 32) & 0xffffffff);
af19b491 1194
15087c2b
SC		 1195 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_ENABLE);
1196 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_START);
af19b491
AKS		 1197
1198 for (j = 0; j < MAX_CTL_CHECK; j++) {
15087c2b 1199 temp = qlcnic_ind_rd(adapter, ms.control);
af19b491
AKS		 1200 if ((temp & TA_CTL_BUSY) == 0)
1201 break;
1202 }
1203
1204 if (j >= MAX_CTL_CHECK) {
1205 if (printk_ratelimit())
1206 dev_err(&adapter->pdev->dev,
1207 "failed to write through agent\n");
1208 ret = -EIO;
1209 } else
1210 ret = 0;
1211
1212done:
b1fc6d3c 1213 mutex_unlock(&adapter->ahw->mem_lock);
af19b491
AKS		 1214
1215 return ret;
1216}
1217
15087c2b 1218int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
af19b491
AKS		 1219{
1220 int j, ret;
1221 u32 temp, off8;
b47acacd 1222 u64 val;
15087c2b 1223 struct qlcnic_ms_reg_ctrl ms;
af19b491
AKS		 1224
1225 /* Only 64-bit aligned access */
1226 if (off & 7)
1227 return -EIO;
15087c2b
SC		 1228 if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1229 QLCNIC_ADDR_QDR_NET_MAX) ||
1230 ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET,
1231 QLCNIC_ADDR_DDR_NET_MAX)))
1232 return -EIO;
af19b491 1233
15087c2b
SC		 1234 memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl));
1235 qlcnic_set_ms_controls(adapter, off, &ms);
af19b491 1236
15087c2b
SC		 1237 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1238 return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window,
1239 ms.off, data, 0);
af19b491 1240
15087c2b 1241 mutex_lock(&adapter->ahw->mem_lock);
af19b491 1242
b47acacd 1243 off8 = off & ~0xf;
af19b491 1244
15087c2b
SC		 1245 qlcnic_ind_wr(adapter, ms.low, off8);
1246 qlcnic_ind_wr(adapter, ms.hi, 0);
af19b491 1247
15087c2b
SC		 1248 qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE);
1249 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE);
af19b491
AKS		 1250
1251 for (j = 0; j < MAX_CTL_CHECK; j++) {
15087c2b 1252 temp = qlcnic_ind_rd(adapter, ms.control);
af19b491
AKS		 1253 if ((temp & TA_CTL_BUSY) == 0)
1254 break;
1255 }
1256
1257 if (j >= MAX_CTL_CHECK) {
1258 if (printk_ratelimit())
1259 dev_err(&adapter->pdev->dev,
1260 "failed to read through agent\n");
1261 ret = -EIO;
1262 } else {
af19b491 1263
15087c2b 1264 temp = qlcnic_ind_rd(adapter, ms.rd[3]);
af19b491 1265 val = (u64)temp << 32;
15087c2b 1266 val |= qlcnic_ind_rd(adapter, ms.rd[2]);
af19b491
AKS		 1267 *data = val;
1268 ret = 0;
1269 }
1270
b1fc6d3c 1271 mutex_unlock(&adapter->ahw->mem_lock);
af19b491
AKS		 1272
1273 return ret;
1274}
1275
7e2cf4fe 1276int qlcnic_82xx_get_board_info(struct qlcnic_adapter *adapter)
af19b491
AKS		 1277{
1278 int offset, board_type, magic;
1279 struct pci_dev *pdev = adapter->pdev;
1280
1281 offset = QLCNIC_FW_MAGIC_OFFSET;
1282 if (qlcnic_rom_fast_read(adapter, offset, &magic))
1283 return -EIO;
1284
1285 if (magic != QLCNIC_BDINFO_MAGIC) {
1286 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1287 magic);
1288 return -EIO;
1289 }
1290
1291 offset = QLCNIC_BRDTYPE_OFFSET;
1292 if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1293 return -EIO;
1294
b1fc6d3c 1295 adapter->ahw->board_type = board_type;
af19b491 1296
ff1b1bf8 1297 if (board_type == QLCNIC_BRDTYPE_P3P_4_GB_MM) {
af19b491
AKS		 1298 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I);
1299 if ((gpio & 0x8000) == 0)
ff1b1bf8 1300 board_type = QLCNIC_BRDTYPE_P3P_10G_TP;
af19b491
AKS		 1301 }
1302
1303 switch (board_type) {
ff1b1bf8
SV		 1304 case QLCNIC_BRDTYPE_P3P_HMEZ:
1305 case QLCNIC_BRDTYPE_P3P_XG_LOM:
1306 case QLCNIC_BRDTYPE_P3P_10G_CX4:
1307 case QLCNIC_BRDTYPE_P3P_10G_CX4_LP:
1308 case QLCNIC_BRDTYPE_P3P_IMEZ:
1309 case QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS:
1310 case QLCNIC_BRDTYPE_P3P_10G_SFP_CT:
1311 case QLCNIC_BRDTYPE_P3P_10G_SFP_QT:
1312 case QLCNIC_BRDTYPE_P3P_10G_XFP:
1313 case QLCNIC_BRDTYPE_P3P_10000_BASE_T:
b1fc6d3c 1314 adapter->ahw->port_type = QLCNIC_XGBE;
af19b491 1315 break;
ff1b1bf8
SV		 1316 case QLCNIC_BRDTYPE_P3P_REF_QG:
1317 case QLCNIC_BRDTYPE_P3P_4_GB:
1318 case QLCNIC_BRDTYPE_P3P_4_GB_MM:
b1fc6d3c 1319 adapter->ahw->port_type = QLCNIC_GBE;
af19b491 1320 break;
ff1b1bf8 1321 case QLCNIC_BRDTYPE_P3P_10G_TP:
b1fc6d3c 1322 adapter->ahw->port_type = (adapter->portnum < 2) ?
af19b491
AKS		 1323 QLCNIC_XGBE : QLCNIC_GBE;
1324 break;
1325 default:
1326 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
b1fc6d3c 1327 adapter->ahw->port_type = QLCNIC_XGBE;
af19b491
AKS		 1328 break;
1329 }
1330
1331 return 0;
1332}
1333
1334int
1335qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1336{
1337 u32 wol_cfg;
1338
1339 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV);
1340 if (wol_cfg & (1UL << adapter->portnum)) {
1341 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG);
1342 if (wol_cfg & (1 << adapter->portnum))
1343 return 1;
1344 }
1345
1346 return 0;
1347}
897d3596 1348
7e2cf4fe 1349int qlcnic_82xx_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
897d3596
SC		 1350{
1351 struct qlcnic_nic_req req;
1352 int rv;
1353 u64 word;
1354
1355 memset(&req, 0, sizeof(struct qlcnic_nic_req));
1356 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1357
1358 word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1359 req.req_hdr = cpu_to_le64(word);
1360
1361 req.words[0] = cpu_to_le64((u64)rate << 32);
1362 req.words[1] = cpu_to_le64(state);
1363
1364 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1365 if (rv)
1366 dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1367
1368 return rv;
1369}
7e2cf4fe
SC		 1370
1371void qlcnic_82xx_get_func_no(struct qlcnic_adapter *adapter)
1372{
1373 void __iomem *msix_base_addr;
1374 u32 func;
1375 u32 msix_base;
1376
1377 pci_read_config_dword(adapter->pdev, QLCNIC_MSIX_TABLE_OFFSET, &func);
1378 msix_base_addr = adapter->ahw->pci_base0 + QLCNIC_MSIX_BASE;
1379 msix_base = readl(msix_base_addr);
1380 func = (func - msix_base) / QLCNIC_MSIX_TBL_PGSIZE;
1381 adapter->ahw->pci_func = func;
1382}
1383
1384void qlcnic_82xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
1385 loff_t offset, size_t size)
1386{
1387 u32 data;
1388 u64 qmdata;
1389
1390 if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) {
1391 qlcnic_pci_camqm_read_2M(adapter, offset, &qmdata);
1392 memcpy(buf, &qmdata, size);
1393 } else {
1394 data = QLCRD32(adapter, offset);
1395 memcpy(buf, &data, size);
1396 }
1397}
1398
1399void qlcnic_82xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
1400 loff_t offset, size_t size)
1401{
1402 u32 data;
1403 u64 qmdata;
1404
1405 if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) {
1406 memcpy(&qmdata, buf, size);
1407 qlcnic_pci_camqm_write_2M(adapter, offset, qmdata);
1408 } else {
1409 memcpy(&data, buf, size);
1410 QLCWR32(adapter, offset, data);
1411 }
1412}
1413
1414int qlcnic_82xx_api_lock(struct qlcnic_adapter *adapter)
1415{
1416 return qlcnic_pcie_sem_lock(adapter, 5, 0);
1417}
1418
1419void qlcnic_82xx_api_unlock(struct qlcnic_adapter *adapter)
1420{
1421 qlcnic_pcie_sem_unlock(adapter, 5);
1422}
Linux 6.x block layer and io_uring tree(s)