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qlcnic: 83xx data path routines
[linux-2.6-block.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic_ctx.c
CommitLineData
af19b491 1/*
40839129
SV		 2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2010 QLogic Corporation
af19b491 4 *
40839129 5 * See LICENSE.qlcnic for copyright and licensing details.
af19b491
AKS		 6 */
7
8#include "qlcnic.h"
9
7e2cf4fe
SC		 10static const struct qlcnic_mailbox_metadata qlcnic_mbx_tbl[] = {
11 {QLCNIC_CMD_CREATE_RX_CTX, 4, 1},
12 {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
13 {QLCNIC_CMD_CREATE_TX_CTX, 4, 1},
14 {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
15 {QLCNIC_CMD_INTRPT_TEST, 4, 1},
16 {QLCNIC_CMD_SET_MTU, 4, 1},
17 {QLCNIC_CMD_READ_PHY, 4, 2},
18 {QLCNIC_CMD_WRITE_PHY, 5, 1},
19 {QLCNIC_CMD_READ_HW_REG, 4, 1},
20 {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
21 {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
22 {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
23 {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
24 {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
25 {QLCNIC_CMD_GET_PCI_INFO, 4, 1},
26 {QLCNIC_CMD_GET_NIC_INFO, 4, 1},
27 {QLCNIC_CMD_SET_NIC_INFO, 4, 1},
28 {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
29 {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
30 {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
31 {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
32 {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
33 {QLCNIC_CMD_GET_MAC_STATS, 4, 1},
34 {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
35 {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
36 {QLCNIC_CMD_CONFIG_PORT, 4, 1},
37 {QLCNIC_CMD_TEMP_SIZE, 4, 4},
38 {QLCNIC_CMD_GET_TEMP_HDR, 4, 1},
39 {QLCNIC_CMD_SET_DRV_VER, 4, 1},
40};
41
42static inline u32 qlcnic_get_cmd_signature(struct qlcnic_hardware_context *ahw)
43{
44 return (ahw->pci_func & 0xff) | ((ahw->fw_hal_version & 0xff) << 8) |
45 (0xcafe << 16);
46}
47
48/* Allocate mailbox registers */
49int qlcnic_82xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
50 struct qlcnic_adapter *adapter, u32 type)
51{
52 int i, size;
53 const struct qlcnic_mailbox_metadata *mbx_tbl;
54
55 mbx_tbl = qlcnic_mbx_tbl;
56 size = ARRAY_SIZE(qlcnic_mbx_tbl);
57 for (i = 0; i < size; i++) {
58 if (type == mbx_tbl[i].cmd) {
59 mbx->req.num = mbx_tbl[i].in_args;
60 mbx->rsp.num = mbx_tbl[i].out_args;
61 mbx->req.arg = kcalloc(mbx->req.num,
62 sizeof(u32), GFP_ATOMIC);
63 if (!mbx->req.arg)
64 return -ENOMEM;
65 mbx->rsp.arg = kcalloc(mbx->rsp.num,
66 sizeof(u32), GFP_ATOMIC);
67 if (!mbx->rsp.arg) {
68 kfree(mbx->req.arg);
69 mbx->req.arg = NULL;
70 return -ENOMEM;
71 }
72 memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
73 memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
74 mbx->req.arg[0] = type;
75 break;
76 }
77 }
78 return 0;
79}
80
81/* Free up mailbox registers */
82void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd)
83{
84 kfree(cmd->req.arg);
85 cmd->req.arg = NULL;
86 kfree(cmd->rsp.arg);
87 cmd->rsp.arg = NULL;
88}
89
bff57d8e
SC		 90static int qlcnic_is_valid_nic_func(struct qlcnic_adapter *adapter, u8 pci_func)
91{
92 int i;
93
94 for (i = 0; i < adapter->ahw->act_pci_func; i++) {
95 if (adapter->npars[i].pci_func == pci_func)
96 return i;
97 }
98
99 return -1;
100}
101
af19b491
AKS		 102static u32
103qlcnic_poll_rsp(struct qlcnic_adapter *adapter)
104{
105 u32 rsp;
106 int timeout = 0;
107
108 do {
109 /* give atleast 1ms for firmware to respond */
68b3f28c 110 mdelay(1);
af19b491
AKS		 111
112 if (++timeout > QLCNIC_OS_CRB_RETRY_COUNT)
113 return QLCNIC_CDRP_RSP_TIMEOUT;
114
115 rsp = QLCRD32(adapter, QLCNIC_CDRP_CRB_OFFSET);
116 } while (!QLCNIC_CDRP_IS_RSP(rsp));
117
118 return rsp;
119}
120
7e2cf4fe
SC		 121int qlcnic_82xx_issue_cmd(struct qlcnic_adapter *adapter,
122 struct qlcnic_cmd_args *cmd)
af19b491 123{
7e2cf4fe 124 int i;
af19b491
AKS		 125 u32 rsp;
126 u32 signature;
af19b491 127 struct pci_dev *pdev = adapter->pdev;
7777de9a 128 struct qlcnic_hardware_context *ahw = adapter->ahw;
af19b491 129
7e2cf4fe 130 signature = qlcnic_get_cmd_signature(ahw);
af19b491
AKS		 131
132 /* Acquire semaphore before accessing CRB */
7777de9a 133 if (qlcnic_api_lock(adapter)) {
7e2cf4fe
SC		 134 cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT;
135 return cmd->rsp.arg[0];
7777de9a 136 }
af19b491
AKS		 137
138 QLCWR32(adapter, QLCNIC_SIGN_CRB_OFFSET, signature);
7e2cf4fe
SC		 139 for (i = 1; i < QLCNIC_CDRP_MAX_ARGS; i++)
140 QLCWR32(adapter, QLCNIC_CDRP_ARG(i), cmd->req.arg[i]);
7777de9a 141 QLCWR32(adapter, QLCNIC_CDRP_CRB_OFFSET,
7e2cf4fe 142 QLCNIC_CDRP_FORM_CMD(cmd->req.arg[0]));
af19b491
AKS		 143 rsp = qlcnic_poll_rsp(adapter);
144
145 if (rsp == QLCNIC_CDRP_RSP_TIMEOUT) {
7e2cf4fe
SC		 146 dev_err(&pdev->dev, "card response timeout.\n");
147 cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT;
af19b491 148 } else if (rsp == QLCNIC_CDRP_RSP_FAIL) {
7e2cf4fe
SC		 149 cmd->rsp.arg[0] = QLCRD32(adapter, QLCNIC_CDRP_ARG(1));
150 dev_err(&pdev->dev, "failed card response code:0x%x\n",
151 cmd->rsp.arg[0]);
152 } else if (rsp == QLCNIC_CDRP_RSP_OK)
153 cmd->rsp.arg[0] = QLCNIC_RCODE_SUCCESS;
154
155 for (i = 1; i < cmd->rsp.num; i++)
156 cmd->rsp.arg[i] = QLCRD32(adapter, QLCNIC_CDRP_ARG(i));
af19b491
AKS		 157
158 /* Release semaphore */
159 qlcnic_api_unlock(adapter);
7e2cf4fe 160 return cmd->rsp.arg[0];
18f2f616
AC		 161}
162
163int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter)
164{
7e2cf4fe 165 int err = 0;
18f2f616 166 void *tmp_addr;
7777de9a 167 struct qlcnic_cmd_args cmd;
18f2f616
AC		 168 dma_addr_t tmp_addr_t = 0;
169
7e2cf4fe
SC		 170 tmp_addr = dma_alloc_coherent(&adapter->pdev->dev, 0x1000,
171 &tmp_addr_t, GFP_KERNEL);
18f2f616
AC		 172 if (!tmp_addr) {
173 dev_err(&adapter->pdev->dev,
174 "Can't get memory for FW dump template\n");
175 return -ENOMEM;
176 }
18f2f616 177
7e2cf4fe
SC		 178 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_TEMP_HDR)) {
179 err = -ENOMEM;
180 goto free_mem;
63507592
SS		 181 }
182
7e2cf4fe
SC		 183 cmd.req.arg[1] = LSD(tmp_addr_t);
184 cmd.req.arg[2] = MSD(tmp_addr_t);
185 cmd.req.arg[3] = 0x1000;
186 err = qlcnic_issue_cmd(adapter, &cmd);
187
188
189 qlcnic_free_mbx_args(&cmd);
190
191free_mem:
192 dma_free_coherent(&adapter->pdev->dev, 0x1000, tmp_addr, tmp_addr_t);
193
18f2f616
AC		 194 return err;
195}
196
af19b491
AKS		 197int
198qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu)
199{
7e2cf4fe 200 int err = 0;
7777de9a 201 struct qlcnic_cmd_args cmd;
b1fc6d3c 202 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
af19b491 203
7e2cf4fe
SC		 204 if (recv_ctx->state != QLCNIC_HOST_CTX_STATE_ACTIVE)
205 return err;
206 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_MTU);
207 cmd.req.arg[1] = recv_ctx->context_id;
208 cmd.req.arg[2] = mtu;
af19b491 209
7e2cf4fe
SC		 210 err = qlcnic_issue_cmd(adapter, &cmd);
211 if (err) {
212 dev_err(&adapter->pdev->dev, "Failed to set mtu\n");
213 err = -EIO;
214 }
215 qlcnic_free_mbx_args(&cmd);
216 return err;
af19b491
AKS		 217}
218
7e2cf4fe 219int qlcnic_82xx_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter)
af19b491
AKS		 220{
221 void *addr;
222 struct qlcnic_hostrq_rx_ctx *prq;
223 struct qlcnic_cardrsp_rx_ctx *prsp;
224 struct qlcnic_hostrq_rds_ring *prq_rds;
225 struct qlcnic_hostrq_sds_ring *prq_sds;
226 struct qlcnic_cardrsp_rds_ring *prsp_rds;
227 struct qlcnic_cardrsp_sds_ring *prsp_sds;
228 struct qlcnic_host_rds_ring *rds_ring;
229 struct qlcnic_host_sds_ring *sds_ring;
7777de9a 230 struct qlcnic_cmd_args cmd;
af19b491
AKS		 231
232 dma_addr_t hostrq_phys_addr, cardrsp_phys_addr;
233 u64 phys_addr;
234
b1fc6d3c 235 u8 i, nrds_rings, nsds_rings;
7e2cf4fe 236 u16 temp_u16;
af19b491 237 size_t rq_size, rsp_size;
2e9d722d 238 u32 cap, reg, val, reg2;
af19b491
AKS		 239 int err;
240
b1fc6d3c 241 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
af19b491
AKS		 242
243 nrds_rings = adapter->max_rds_rings;
244 nsds_rings = adapter->max_sds_rings;
245
246 rq_size =
247 SIZEOF_HOSTRQ_RX(struct qlcnic_hostrq_rx_ctx, nrds_rings,
248 nsds_rings);
249 rsp_size =
250 SIZEOF_CARDRSP_RX(struct qlcnic_cardrsp_rx_ctx, nrds_rings,
251 nsds_rings);
252
b1fc6d3c
AC		 253 addr = dma_alloc_coherent(&adapter->pdev->dev, rq_size,
254 &hostrq_phys_addr, GFP_KERNEL);
af19b491
AKS		 255 if (addr == NULL)
256 return -ENOMEM;
43d620c8 257 prq = addr;
af19b491 258
b1fc6d3c
AC		 259 addr = dma_alloc_coherent(&adapter->pdev->dev, rsp_size,
260 &cardrsp_phys_addr, GFP_KERNEL);
af19b491
AKS		 261 if (addr == NULL) {
262 err = -ENOMEM;
263 goto out_free_rq;
264 }
43d620c8 265 prsp = addr;
af19b491
AKS		 266
267 prq->host_rsp_dma_addr = cpu_to_le64(cardrsp_phys_addr);
268
8f891387 269 cap = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN
270 | QLCNIC_CAP0_VALIDOFF);
af19b491
AKS		 271 cap |= (QLCNIC_CAP0_JUMBO_CONTIGUOUS | QLCNIC_CAP0_LRO_CONTIGUOUS);
272
7e2cf4fe
SC		 273 temp_u16 = offsetof(struct qlcnic_hostrq_rx_ctx, msix_handler);
274 prq->valid_field_offset = cpu_to_le16(temp_u16);
8f891387 275 prq->txrx_sds_binding = nsds_rings - 1;
276
af19b491
AKS		 277 prq->capabilities[0] = cpu_to_le32(cap);
278 prq->host_int_crb_mode =
279 cpu_to_le32(QLCNIC_HOST_INT_CRB_MODE_SHARED);
280 prq->host_rds_crb_mode =
281 cpu_to_le32(QLCNIC_HOST_RDS_CRB_MODE_UNIQUE);
282
283 prq->num_rds_rings = cpu_to_le16(nrds_rings);
284 prq->num_sds_rings = cpu_to_le16(nsds_rings);
b1fc6d3c 285 prq->rds_ring_offset = 0;
af19b491
AKS		 286
287 val = le32_to_cpu(prq->rds_ring_offset) +
288 (sizeof(struct qlcnic_hostrq_rds_ring) * nrds_rings);
289 prq->sds_ring_offset = cpu_to_le32(val);
290
291 prq_rds = (struct qlcnic_hostrq_rds_ring *)(prq->data +
292 le32_to_cpu(prq->rds_ring_offset));
293
294 for (i = 0; i < nrds_rings; i++) {
295
296 rds_ring = &recv_ctx->rds_rings[i];
8a15ad1f 297 rds_ring->producer = 0;
af19b491
AKS		 298
299 prq_rds[i].host_phys_addr = cpu_to_le64(rds_ring->phys_addr);
300 prq_rds[i].ring_size = cpu_to_le32(rds_ring->num_desc);
301 prq_rds[i].ring_kind = cpu_to_le32(i);
302 prq_rds[i].buff_size = cpu_to_le64(rds_ring->dma_size);
303 }
304
305 prq_sds = (struct qlcnic_hostrq_sds_ring *)(prq->data +
306 le32_to_cpu(prq->sds_ring_offset));
307
308 for (i = 0; i < nsds_rings; i++) {
309
310 sds_ring = &recv_ctx->sds_rings[i];
8a15ad1f
AKS		 311 sds_ring->consumer = 0;
312 memset(sds_ring->desc_head, 0, STATUS_DESC_RINGSIZE(sds_ring));
af19b491
AKS		 313
314 prq_sds[i].host_phys_addr = cpu_to_le64(sds_ring->phys_addr);
315 prq_sds[i].ring_size = cpu_to_le32(sds_ring->num_desc);
316 prq_sds[i].msi_index = cpu_to_le16(i);
317 }
318
319 phys_addr = hostrq_phys_addr;
7e2cf4fe
SC		 320 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_RX_CTX);
321 cmd.req.arg[1] = MSD(phys_addr);
322 cmd.req.arg[2] = LSD(phys_addr);
323 cmd.req.arg[3] = rq_size;
324 err = qlcnic_issue_cmd(adapter, &cmd);
af19b491
AKS		 325 if (err) {
326 dev_err(&adapter->pdev->dev,
327 "Failed to create rx ctx in firmware%d\n", err);
328 goto out_free_rsp;
329 }
330
af19b491
AKS		 331 prsp_rds = ((struct qlcnic_cardrsp_rds_ring *)
332 &prsp->data[le32_to_cpu(prsp->rds_ring_offset)]);
333
334 for (i = 0; i < le16_to_cpu(prsp->num_rds_rings); i++) {
335 rds_ring = &recv_ctx->rds_rings[i];
336
337 reg = le32_to_cpu(prsp_rds[i].host_producer_crb);
b1fc6d3c 338 rds_ring->crb_rcv_producer = adapter->ahw->pci_base0 + reg;
af19b491
AKS		 339 }
340
341 prsp_sds = ((struct qlcnic_cardrsp_sds_ring *)
342 &prsp->data[le32_to_cpu(prsp->sds_ring_offset)]);
343
344 for (i = 0; i < le16_to_cpu(prsp->num_sds_rings); i++) {
345 sds_ring = &recv_ctx->sds_rings[i];
346
347 reg = le32_to_cpu(prsp_sds[i].host_consumer_crb);
2e9d722d 348 reg2 = le32_to_cpu(prsp_sds[i].interrupt_crb);
af19b491 349
b1fc6d3c
AC		 350 sds_ring->crb_sts_consumer = adapter->ahw->pci_base0 + reg;
351 sds_ring->crb_intr_mask = adapter->ahw->pci_base0 + reg2;
af19b491
AKS		 352 }
353
354 recv_ctx->state = le32_to_cpu(prsp->host_ctx_state);
355 recv_ctx->context_id = le16_to_cpu(prsp->context_id);
356 recv_ctx->virt_port = prsp->virt_port;
357
358out_free_rsp:
b1fc6d3c
AC		 359 dma_free_coherent(&adapter->pdev->dev, rsp_size, prsp,
360 cardrsp_phys_addr);
7e2cf4fe 361 qlcnic_free_mbx_args(&cmd);
af19b491 362out_free_rq:
b1fc6d3c 363 dma_free_coherent(&adapter->pdev->dev, rq_size, prq, hostrq_phys_addr);
af19b491
AKS		 364 return err;
365}
366
367static void
368qlcnic_fw_cmd_destroy_rx_ctx(struct qlcnic_adapter *adapter)
369{
7e2cf4fe 370 int err;
7777de9a 371 struct qlcnic_cmd_args cmd;
b1fc6d3c 372 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
af19b491 373
7e2cf4fe
SC		 374 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX);
375 cmd.req.arg[1] = recv_ctx->context_id;
376 err = qlcnic_issue_cmd(adapter, &cmd);
377 if (err)
af19b491
AKS		 378 dev_err(&adapter->pdev->dev,
379 "Failed to destroy rx ctx in firmware\n");
d626ad4d
AKS		 380
381 recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
7e2cf4fe 382 qlcnic_free_mbx_args(&cmd);
af19b491
AKS		 383}
384
7e2cf4fe
SC		 385int qlcnic_82xx_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter,
386 struct qlcnic_host_tx_ring *tx_ring,
387 int ring)
af19b491
AKS		 388{
389 struct qlcnic_hostrq_tx_ctx *prq;
390 struct qlcnic_hostrq_cds_ring *prq_cds;
391 struct qlcnic_cardrsp_tx_ctx *prsp;
392 void *rq_addr, *rsp_addr;
393 size_t rq_size, rsp_size;
394 u32 temp;
7777de9a 395 struct qlcnic_cmd_args cmd;
af19b491
AKS		 396 int err;
397 u64 phys_addr;
398 dma_addr_t rq_phys_addr, rsp_phys_addr;
af19b491 399
8a15ad1f
AKS		 400 /* reset host resources */
401 tx_ring->producer = 0;
402 tx_ring->sw_consumer = 0;
403 *(tx_ring->hw_consumer) = 0;
404
af19b491 405 rq_size = SIZEOF_HOSTRQ_TX(struct qlcnic_hostrq_tx_ctx);
b1fc6d3c
AC		 406 rq_addr = dma_alloc_coherent(&adapter->pdev->dev, rq_size,
407 &rq_phys_addr, GFP_KERNEL);
af19b491
AKS		 408 if (!rq_addr)
409 return -ENOMEM;
410
411 rsp_size = SIZEOF_CARDRSP_TX(struct qlcnic_cardrsp_tx_ctx);
b1fc6d3c
AC		 412 rsp_addr = dma_alloc_coherent(&adapter->pdev->dev, rsp_size,
413 &rsp_phys_addr, GFP_KERNEL);
af19b491
AKS		 414 if (!rsp_addr) {
415 err = -ENOMEM;
416 goto out_free_rq;
417 }
418
419 memset(rq_addr, 0, rq_size);
43d620c8 420 prq = rq_addr;
af19b491
AKS		 421
422 memset(rsp_addr, 0, rsp_size);
43d620c8 423 prsp = rsp_addr;
af19b491
AKS		 424
425 prq->host_rsp_dma_addr = cpu_to_le64(rsp_phys_addr);
426
427 temp = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN |
428 QLCNIC_CAP0_LSO);
429 prq->capabilities[0] = cpu_to_le32(temp);
430
431 prq->host_int_crb_mode =
432 cpu_to_le32(QLCNIC_HOST_INT_CRB_MODE_SHARED);
7e2cf4fe 433 prq->msi_index = 0;
af19b491
AKS		 434
435 prq->interrupt_ctl = 0;
af19b491
AKS		 436 prq->cmd_cons_dma_addr = cpu_to_le64(tx_ring->hw_cons_phys_addr);
437
438 prq_cds = &prq->cds_ring;
439
440 prq_cds->host_phys_addr = cpu_to_le64(tx_ring->phys_addr);
441 prq_cds->ring_size = cpu_to_le32(tx_ring->num_desc);
442
443 phys_addr = rq_phys_addr;
7e2cf4fe
SC		 444
445 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
446 cmd.req.arg[1] = MSD(phys_addr);
447 cmd.req.arg[2] = LSD(phys_addr);
448 cmd.req.arg[3] = rq_size;
449 err = qlcnic_issue_cmd(adapter, &cmd);
af19b491
AKS		 450
451 if (err == QLCNIC_RCODE_SUCCESS) {
452 temp = le32_to_cpu(prsp->cds_ring.host_producer_crb);
b1fc6d3c 453 tx_ring->crb_cmd_producer = adapter->ahw->pci_base0 + temp;
7e2cf4fe 454 tx_ring->ctx_id = le16_to_cpu(prsp->context_id);
af19b491
AKS		 455 } else {
456 dev_err(&adapter->pdev->dev,
457 "Failed to create tx ctx in firmware%d\n", err);
458 err = -EIO;
459 }
460
b1fc6d3c 461 dma_free_coherent(&adapter->pdev->dev, rsp_size, rsp_addr,
7e2cf4fe 462 rsp_phys_addr);
af19b491
AKS		 463
464out_free_rq:
b1fc6d3c 465 dma_free_coherent(&adapter->pdev->dev, rq_size, rq_addr, rq_phys_addr);
7e2cf4fe 466 qlcnic_free_mbx_args(&cmd);
af19b491
AKS		 467
468 return err;
469}
470
471static void
7e2cf4fe
SC		 472qlcnic_fw_cmd_destroy_tx_ctx(struct qlcnic_adapter *adapter,
473 struct qlcnic_host_tx_ring *tx_ring)
af19b491 474{
7777de9a
AC		 475 struct qlcnic_cmd_args cmd;
476
7e2cf4fe
SC		 477 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX);
478 cmd.req.arg[1] = tx_ring->ctx_id;
479 if (qlcnic_issue_cmd(adapter, &cmd))
af19b491
AKS		 480 dev_err(&adapter->pdev->dev,
481 "Failed to destroy tx ctx in firmware\n");
7e2cf4fe 482 qlcnic_free_mbx_args(&cmd);
af19b491
AKS		 483}
484
485int
7e610caa 486qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config)
af19b491 487{
7e2cf4fe 488 int err;
7777de9a
AC		 489 struct qlcnic_cmd_args cmd;
490
7e2cf4fe
SC		 491 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_PORT);
492 cmd.req.arg[1] = config;
493 err = qlcnic_issue_cmd(adapter, &cmd);
494 qlcnic_free_mbx_args(&cmd);
495 return err;
af19b491
AKS		 496}
497
498int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter)
499{
500 void *addr;
4be41e92 501 int err, ring;
af19b491
AKS		 502 struct qlcnic_recv_context *recv_ctx;
503 struct qlcnic_host_rds_ring *rds_ring;
504 struct qlcnic_host_sds_ring *sds_ring;
505 struct qlcnic_host_tx_ring *tx_ring;
4be41e92 506 __le32 *ptr;
af19b491
AKS		 507
508 struct pci_dev *pdev = adapter->pdev;
509
b1fc6d3c 510 recv_ctx = adapter->recv_ctx;
af19b491 511
4be41e92
SC		 512 for (ring = 0; ring < adapter->max_drv_tx_rings; ring++) {
513 tx_ring = &adapter->tx_ring[ring];
514 ptr = (__le32 *)dma_alloc_coherent(&pdev->dev, sizeof(u32),
515 &tx_ring->hw_cons_phys_addr,
516 GFP_KERNEL);
af19b491 517
4be41e92
SC		 518 if (ptr == NULL) {
519 dev_err(&pdev->dev, "failed to allocate tx consumer\n");
520 return -ENOMEM;
521 }
522 tx_ring->hw_consumer = ptr;
523 /* cmd desc ring */
524 addr = dma_alloc_coherent(&pdev->dev, TX_DESC_RINGSIZE(tx_ring),
525 &tx_ring->phys_addr,
526 GFP_KERNEL);
af19b491 527
4be41e92
SC		 528 if (addr == NULL) {
529 dev_err(&pdev->dev,
530 "failed to allocate tx desc ring\n");
531 err = -ENOMEM;
532 goto err_out_free;
533 }
af19b491 534
4be41e92
SC		 535 tx_ring->desc_head = addr;
536 }
af19b491
AKS		 537
538 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
539 rds_ring = &recv_ctx->rds_rings[ring];
b1fc6d3c 540 addr = dma_alloc_coherent(&adapter->pdev->dev,
af19b491 541 RCV_DESC_RINGSIZE(rds_ring),
b1fc6d3c 542 &rds_ring->phys_addr, GFP_KERNEL);
af19b491
AKS		 543 if (addr == NULL) {
544 dev_err(&pdev->dev,
545 "failed to allocate rds ring [%d]\n", ring);
546 err = -ENOMEM;
547 goto err_out_free;
548 }
43d620c8 549 rds_ring->desc_head = addr;
af19b491
AKS		 550
551 }
552
553 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
554 sds_ring = &recv_ctx->sds_rings[ring];
555
b1fc6d3c 556 addr = dma_alloc_coherent(&adapter->pdev->dev,
af19b491 557 STATUS_DESC_RINGSIZE(sds_ring),
b1fc6d3c 558 &sds_ring->phys_addr, GFP_KERNEL);
af19b491
AKS		 559 if (addr == NULL) {
560 dev_err(&pdev->dev,
561 "failed to allocate sds ring [%d]\n", ring);
562 err = -ENOMEM;
563 goto err_out_free;
564 }
43d620c8 565 sds_ring->desc_head = addr;
af19b491
AKS		 566 }
567
af19b491
AKS		 568 return 0;
569
570err_out_free:
571 qlcnic_free_hw_resources(adapter);
572 return err;
573}
574
7e2cf4fe 575int qlcnic_fw_create_ctx(struct qlcnic_adapter *dev)
af19b491 576{
7e2cf4fe 577 int i, err, ring;
8a15ad1f 578
7e2cf4fe
SC		 579 if (dev->flags & QLCNIC_NEED_FLR) {
580 pci_reset_function(dev->pdev);
581 dev->flags &= ~QLCNIC_NEED_FLR;
b0044bcf 582 }
c21fd48c 583
7e2cf4fe 584 err = qlcnic_fw_cmd_create_rx_ctx(dev);
8a15ad1f
AKS		 585 if (err)
586 return err;
587
7e2cf4fe
SC		 588 for (ring = 0; ring < dev->max_drv_tx_rings; ring++) {
589 err = qlcnic_fw_cmd_create_tx_ctx(dev,
590 &dev->tx_ring[ring],
591 ring);
592 if (err) {
593 qlcnic_fw_cmd_destroy_rx_ctx(dev);
594 if (ring == 0)
595 return err;
596
597 for (i = 0; i < ring; i++)
598 qlcnic_fw_cmd_destroy_tx_ctx(dev,
599 &dev->tx_ring[i]);
600
601 return err;
602 }
8a15ad1f 603 }
af19b491 604
7e2cf4fe 605 set_bit(__QLCNIC_FW_ATTACHED, &dev->state);
8a15ad1f
AKS		 606 return 0;
607}
af19b491 608
8a15ad1f
AKS		 609void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter)
610{
7e2cf4fe
SC		 611 int ring;
612
af19b491
AKS		 613 if (test_and_clear_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) {
614 qlcnic_fw_cmd_destroy_rx_ctx(adapter);
7e2cf4fe
SC		 615 for (ring = 0; ring < adapter->max_drv_tx_rings; ring++)
616 qlcnic_fw_cmd_destroy_tx_ctx(adapter,
617 &adapter->tx_ring[ring]);
af19b491 618 /* Allow dma queues to drain after context reset */
68b3f28c 619 mdelay(20);
af19b491 620 }
8a15ad1f
AKS		 621}
622
623void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter)
624{
625 struct qlcnic_recv_context *recv_ctx;
626 struct qlcnic_host_rds_ring *rds_ring;
627 struct qlcnic_host_sds_ring *sds_ring;
628 struct qlcnic_host_tx_ring *tx_ring;
629 int ring;
af19b491 630
b1fc6d3c 631 recv_ctx = adapter->recv_ctx;
af19b491 632
4be41e92
SC		 633 for (ring = 0; ring < adapter->max_drv_tx_rings; ring++) {
634 tx_ring = &adapter->tx_ring[ring];
635 if (tx_ring->hw_consumer != NULL) {
636 dma_free_coherent(&adapter->pdev->dev, sizeof(u32),
637 tx_ring->hw_consumer,
638 tx_ring->hw_cons_phys_addr);
af19b491 639
4be41e92
SC		 640 tx_ring->hw_consumer = NULL;
641 }
642
643 if (tx_ring->desc_head != NULL) {
644 dma_free_coherent(&adapter->pdev->dev,
645 TX_DESC_RINGSIZE(tx_ring),
646 tx_ring->desc_head,
647 tx_ring->phys_addr);
648 tx_ring->desc_head = NULL;
649 }
af19b491
AKS		 650 }
651
652 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
653 rds_ring = &recv_ctx->rds_rings[ring];
654
655 if (rds_ring->desc_head != NULL) {
b1fc6d3c 656 dma_free_coherent(&adapter->pdev->dev,
af19b491
AKS		 657 RCV_DESC_RINGSIZE(rds_ring),
658 rds_ring->desc_head,
659 rds_ring->phys_addr);
660 rds_ring->desc_head = NULL;
661 }
662 }
663
664 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
665 sds_ring = &recv_ctx->sds_rings[ring];
666
667 if (sds_ring->desc_head != NULL) {
b1fc6d3c 668 dma_free_coherent(&adapter->pdev->dev,
af19b491
AKS		 669 STATUS_DESC_RINGSIZE(sds_ring),
670 sds_ring->desc_head,
671 sds_ring->phys_addr);
672 sds_ring->desc_head = NULL;
673 }
674 }
675}
676
2e9d722d 677
7e2cf4fe 678int qlcnic_82xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac)
2e9d722d 679{
7e2cf4fe 680 int err, i;
7777de9a 681 struct qlcnic_cmd_args cmd;
7e2cf4fe 682 u32 mac_low, mac_high;
7777de9a 683
7e2cf4fe
SC		 684 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
685 cmd.req.arg[1] = adapter->ahw->pci_func | BIT_8;
686 err = qlcnic_issue_cmd(adapter, &cmd);
2e9d722d 687
7e2cf4fe
SC		 688 if (err == QLCNIC_RCODE_SUCCESS) {
689 mac_low = cmd.rsp.arg[1];
690 mac_high = cmd.rsp.arg[2];
691
692 for (i = 0; i < 2; i++)
693 mac[i] = (u8) (mac_high >> ((1 - i) * 8));
694 for (i = 2; i < 6; i++)
695 mac[i] = (u8) (mac_low >> ((5 - i) * 8));
696 } else {
2e9d722d
AC		 697 dev_err(&adapter->pdev->dev,
698 "Failed to get mac address%d\n", err);
699 err = -EIO;
700 }
7e2cf4fe 701 qlcnic_free_mbx_args(&cmd);
2e9d722d
AC		 702 return err;
703}
704
705/* Get info of a NIC partition */
7e2cf4fe
SC		 706int qlcnic_82xx_get_nic_info(struct qlcnic_adapter *adapter,
707 struct qlcnic_info *npar_info, u8 func_id)
2e9d722d
AC		 708{
709 int err;
710 dma_addr_t nic_dma_t;
7e2cf4fe 711 const struct qlcnic_info_le *nic_info;
2e9d722d 712 void *nic_info_addr;
7777de9a 713 struct qlcnic_cmd_args cmd;
7e2cf4fe 714 size_t nic_size = sizeof(struct qlcnic_info_le);
2e9d722d 715
b1fc6d3c
AC		 716 nic_info_addr = dma_alloc_coherent(&adapter->pdev->dev, nic_size,
717 &nic_dma_t, GFP_KERNEL);
2e9d722d
AC		 718 if (!nic_info_addr)
719 return -ENOMEM;
720 memset(nic_info_addr, 0, nic_size);
721
43d620c8 722 nic_info = nic_info_addr;
2e9d722d 723
7e2cf4fe
SC		 724 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
725 cmd.req.arg[1] = MSD(nic_dma_t);
726 cmd.req.arg[2] = LSD(nic_dma_t);
727 cmd.req.arg[3] = (func_id << 16 | nic_size);
728 err = qlcnic_issue_cmd(adapter, &cmd);
729 if (err != QLCNIC_RCODE_SUCCESS) {
730 dev_err(&adapter->pdev->dev,
731 "Failed to get nic info%d\n", err);
732 err = -EIO;
733 } else {
cea8975e
AC		 734 npar_info->pci_func = le16_to_cpu(nic_info->pci_func);
735 npar_info->op_mode = le16_to_cpu(nic_info->op_mode);
7e2cf4fe
SC		 736 npar_info->min_tx_bw = le16_to_cpu(nic_info->min_tx_bw);
737 npar_info->max_tx_bw = le16_to_cpu(nic_info->max_tx_bw);
346fe763
RB		 738 npar_info->phys_port = le16_to_cpu(nic_info->phys_port);
739 npar_info->switch_mode = le16_to_cpu(nic_info->switch_mode);
740 npar_info->max_tx_ques = le16_to_cpu(nic_info->max_tx_ques);
741 npar_info->max_rx_ques = le16_to_cpu(nic_info->max_rx_ques);
346fe763
RB		 742 npar_info->capabilities = le32_to_cpu(nic_info->capabilities);
743 npar_info->max_mtu = le16_to_cpu(nic_info->max_mtu);
2e9d722d
AC		 744 }
745
b1fc6d3c 746 dma_free_coherent(&adapter->pdev->dev, nic_size, nic_info_addr,
7e2cf4fe
SC		 747 nic_dma_t);
748 qlcnic_free_mbx_args(&cmd);
749
2e9d722d
AC		 750 return err;
751}
752
753/* Configure a NIC partition */
7e2cf4fe
SC		 754int qlcnic_82xx_set_nic_info(struct qlcnic_adapter *adapter,
755 struct qlcnic_info *nic)
2e9d722d
AC		 756{
757 int err = -EIO;
2e9d722d
AC		 758 dma_addr_t nic_dma_t;
759 void *nic_info_addr;
7777de9a 760 struct qlcnic_cmd_args cmd;
63507592
SS		 761 struct qlcnic_info_le *nic_info;
762 size_t nic_size = sizeof(struct qlcnic_info_le);
2e9d722d 763
79788450 764 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
2e9d722d
AC		 765 return err;
766
b1fc6d3c
AC		 767 nic_info_addr = dma_alloc_coherent(&adapter->pdev->dev, nic_size,
768 &nic_dma_t, GFP_KERNEL);
2e9d722d
AC		 769 if (!nic_info_addr)
770 return -ENOMEM;
771
772 memset(nic_info_addr, 0, nic_size);
43d620c8 773 nic_info = nic_info_addr;
2e9d722d
AC		 774
775 nic_info->pci_func = cpu_to_le16(nic->pci_func);
776 nic_info->op_mode = cpu_to_le16(nic->op_mode);
777 nic_info->phys_port = cpu_to_le16(nic->phys_port);
778 nic_info->switch_mode = cpu_to_le16(nic->switch_mode);
779 nic_info->capabilities = cpu_to_le32(nic->capabilities);
780 nic_info->max_mac_filters = nic->max_mac_filters;
781 nic_info->max_tx_ques = cpu_to_le16(nic->max_tx_ques);
782 nic_info->max_rx_ques = cpu_to_le16(nic->max_rx_ques);
783 nic_info->min_tx_bw = cpu_to_le16(nic->min_tx_bw);
784 nic_info->max_tx_bw = cpu_to_le16(nic->max_tx_bw);
785
7e2cf4fe
SC		 786 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
787 cmd.req.arg[1] = MSD(nic_dma_t);
788 cmd.req.arg[2] = LSD(nic_dma_t);
789 cmd.req.arg[3] = ((nic->pci_func << 16) | nic_size);
790 err = qlcnic_issue_cmd(adapter, &cmd);
2e9d722d
AC		 791
792 if (err != QLCNIC_RCODE_SUCCESS) {
793 dev_err(&adapter->pdev->dev,
794 "Failed to set nic info%d\n", err);
795 err = -EIO;
796 }
797
b1fc6d3c
AC		 798 dma_free_coherent(&adapter->pdev->dev, nic_size, nic_info_addr,
799 nic_dma_t);
7e2cf4fe
SC		 800 qlcnic_free_mbx_args(&cmd);
801
2e9d722d
AC		 802 return err;
803}
804
805/* Get PCI Info of a partition */
7e2cf4fe
SC		 806int qlcnic_82xx_get_pci_info(struct qlcnic_adapter *adapter,
807 struct qlcnic_pci_info *pci_info)
2e9d722d
AC		 808{
809 int err = 0, i;
7777de9a 810 struct qlcnic_cmd_args cmd;
2e9d722d 811 dma_addr_t pci_info_dma_t;
63507592 812 struct qlcnic_pci_info_le *npar;
2e9d722d 813 void *pci_info_addr;
63507592 814 size_t npar_size = sizeof(struct qlcnic_pci_info_le);
2e9d722d
AC		 815 size_t pci_size = npar_size * QLCNIC_MAX_PCI_FUNC;
816
b1fc6d3c
AC		 817 pci_info_addr = dma_alloc_coherent(&adapter->pdev->dev, pci_size,
818 &pci_info_dma_t, GFP_KERNEL);
2e9d722d
AC		 819 if (!pci_info_addr)
820 return -ENOMEM;
821 memset(pci_info_addr, 0, pci_size);
822
43d620c8 823 npar = pci_info_addr;
7e2cf4fe
SC		 824 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
825 cmd.req.arg[1] = MSD(pci_info_dma_t);
826 cmd.req.arg[2] = LSD(pci_info_dma_t);
827 cmd.req.arg[3] = pci_size;
828 err = qlcnic_issue_cmd(adapter, &cmd);
2e9d722d 829
bff57d8e 830 adapter->ahw->act_pci_func = 0;
2e9d722d 831 if (err == QLCNIC_RCODE_SUCCESS) {
346fe763 832 for (i = 0; i < QLCNIC_MAX_PCI_FUNC; i++, npar++, pci_info++) {
a1c0c459
SC		 833 pci_info->id = le16_to_cpu(npar->id);
834 pci_info->active = le16_to_cpu(npar->active);
835 pci_info->type = le16_to_cpu(npar->type);
bff57d8e
SC		 836 if (pci_info->type == QLCNIC_TYPE_NIC)
837 adapter->ahw->act_pci_func++;
346fe763 838 pci_info->default_port =
a1c0c459 839 le16_to_cpu(npar->default_port);
346fe763 840 pci_info->tx_min_bw =
a1c0c459 841 le16_to_cpu(npar->tx_min_bw);
346fe763 842 pci_info->tx_max_bw =
a1c0c459 843 le16_to_cpu(npar->tx_max_bw);
346fe763 844 memcpy(pci_info->mac, npar->mac, ETH_ALEN);
2e9d722d
AC		 845 }
846 } else {
847 dev_err(&adapter->pdev->dev,
848 "Failed to get PCI Info%d\n", err);
2e9d722d
AC		 849 err = -EIO;
850 }
2e9d722d 851
b1fc6d3c 852 dma_free_coherent(&adapter->pdev->dev, pci_size, pci_info_addr,
2e9d722d 853 pci_info_dma_t);
7e2cf4fe
SC		 854 qlcnic_free_mbx_args(&cmd);
855
2e9d722d
AC		 856 return err;
857}
858
2e9d722d
AC		 859/* Configure eSwitch for port mirroring */
860int qlcnic_config_port_mirroring(struct qlcnic_adapter *adapter, u8 id,
861 u8 enable_mirroring, u8 pci_func)
862{
863 int err = -EIO;
864 u32 arg1;
7777de9a 865 struct qlcnic_cmd_args cmd;
2e9d722d 866
79788450
SC		 867 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC ||
868 !(adapter->eswitch[id].flags & QLCNIC_SWITCH_ENABLE))
2e9d722d
AC		 869 return err;
870
871 arg1 = id | (enable_mirroring ? BIT_4 : 0);
872 arg1 |= pci_func << 8;
873
7e2cf4fe
SC		 874 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORTMIRRORING);
875 cmd.req.arg[1] = arg1;
876 err = qlcnic_issue_cmd(adapter, &cmd);
2e9d722d 877
7e2cf4fe 878 if (err != QLCNIC_RCODE_SUCCESS)
2e9d722d
AC		 879 dev_err(&adapter->pdev->dev,
880 "Failed to configure port mirroring%d on eswitch:%d\n",
881 pci_func, id);
7e2cf4fe 882 else
2e9d722d
AC		 883 dev_info(&adapter->pdev->dev,
884 "Configured eSwitch %d for port mirroring:%d\n",
885 id, pci_func);
7e2cf4fe 886 qlcnic_free_mbx_args(&cmd);
2e9d722d
AC		 887
888 return err;
889}
890
b6021212
AKS		 891int qlcnic_get_port_stats(struct qlcnic_adapter *adapter, const u8 func,
892 const u8 rx_tx, struct __qlcnic_esw_statistics *esw_stats) {
893
63507592
SS		 894 size_t stats_size = sizeof(struct qlcnic_esw_stats_le);
895 struct qlcnic_esw_stats_le *stats;
b6021212
AKS		 896 dma_addr_t stats_dma_t;
897 void *stats_addr;
898 u32 arg1;
7777de9a 899 struct qlcnic_cmd_args cmd;
b6021212
AKS		 900 int err;
901
902 if (esw_stats == NULL)
903 return -ENOMEM;
904
79788450
SC		 905 if ((adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) &&
906 (func != adapter->ahw->pci_func)) {
b6021212
AKS		 907 dev_err(&adapter->pdev->dev,
908 "Not privilege to query stats for func=%d", func);
909 return -EIO;
910 }
911
b1fc6d3c
AC		 912 stats_addr = dma_alloc_coherent(&adapter->pdev->dev, stats_size,
913 &stats_dma_t, GFP_KERNEL);
b6021212
AKS		 914 if (!stats_addr) {
915 dev_err(&adapter->pdev->dev, "Unable to allocate memory\n");
916 return -ENOMEM;
917 }
918 memset(stats_addr, 0, stats_size);
919
920 arg1 = func | QLCNIC_STATS_VERSION << 8 | QLCNIC_STATS_PORT << 12;
921 arg1 |= rx_tx << 15 | stats_size << 16;
922
7e2cf4fe
SC		 923 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_ESWITCH_STATS);
924 cmd.req.arg[1] = arg1;
925 cmd.req.arg[2] = MSD(stats_dma_t);
926 cmd.req.arg[3] = LSD(stats_dma_t);
927 err = qlcnic_issue_cmd(adapter, &cmd);
b6021212 928
63e74e9c 929 if (!err) {
43d620c8 930 stats = stats_addr;
63e74e9c
AKS		 931 esw_stats->context_id = le16_to_cpu(stats->context_id);
932 esw_stats->version = le16_to_cpu(stats->version);
933 esw_stats->size = le16_to_cpu(stats->size);
934 esw_stats->multicast_frames =
935 le64_to_cpu(stats->multicast_frames);
936 esw_stats->broadcast_frames =
937 le64_to_cpu(stats->broadcast_frames);
938 esw_stats->unicast_frames = le64_to_cpu(stats->unicast_frames);
939 esw_stats->dropped_frames = le64_to_cpu(stats->dropped_frames);
940 esw_stats->local_frames = le64_to_cpu(stats->local_frames);
941 esw_stats->errors = le64_to_cpu(stats->errors);
942 esw_stats->numbytes = le64_to_cpu(stats->numbytes);
943 }
b6021212 944
b1fc6d3c 945 dma_free_coherent(&adapter->pdev->dev, stats_size, stats_addr,
b6021212 946 stats_dma_t);
7e2cf4fe
SC		 947 qlcnic_free_mbx_args(&cmd);
948
b6021212
AKS		 949 return err;
950}
951
54a8997c
JK		 952/* This routine will retrieve the MAC statistics from firmware */
953int qlcnic_get_mac_stats(struct qlcnic_adapter *adapter,
954 struct qlcnic_mac_statistics *mac_stats)
955{
63507592 956 struct qlcnic_mac_statistics_le *stats;
54a8997c 957 struct qlcnic_cmd_args cmd;
63507592 958 size_t stats_size = sizeof(struct qlcnic_mac_statistics_le);
54a8997c
JK		 959 dma_addr_t stats_dma_t;
960 void *stats_addr;
961 int err;
962
7e2cf4fe
SC		 963 if (mac_stats == NULL)
964 return -ENOMEM;
965
54a8997c
JK		 966 stats_addr = dma_alloc_coherent(&adapter->pdev->dev, stats_size,
967 &stats_dma_t, GFP_KERNEL);
968 if (!stats_addr) {
969 dev_err(&adapter->pdev->dev,
970 "%s: Unable to allocate memory.\n", __func__);
971 return -ENOMEM;
972 }
973 memset(stats_addr, 0, stats_size);
7e2cf4fe
SC		 974 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_MAC_STATS);
975 cmd.req.arg[1] = stats_size << 16;
976 cmd.req.arg[2] = MSD(stats_dma_t);
977 cmd.req.arg[3] = LSD(stats_dma_t);
978 err = qlcnic_issue_cmd(adapter, &cmd);
54a8997c
JK		 979 if (!err) {
980 stats = stats_addr;
981 mac_stats->mac_tx_frames = le64_to_cpu(stats->mac_tx_frames);
982 mac_stats->mac_tx_bytes = le64_to_cpu(stats->mac_tx_bytes);
983 mac_stats->mac_tx_mcast_pkts =
984 le64_to_cpu(stats->mac_tx_mcast_pkts);
985 mac_stats->mac_tx_bcast_pkts =
986 le64_to_cpu(stats->mac_tx_bcast_pkts);
987 mac_stats->mac_rx_frames = le64_to_cpu(stats->mac_rx_frames);
988 mac_stats->mac_rx_bytes = le64_to_cpu(stats->mac_rx_bytes);
989 mac_stats->mac_rx_mcast_pkts =
990 le64_to_cpu(stats->mac_rx_mcast_pkts);
991 mac_stats->mac_rx_length_error =
992 le64_to_cpu(stats->mac_rx_length_error);
993 mac_stats->mac_rx_length_small =
994 le64_to_cpu(stats->mac_rx_length_small);
995 mac_stats->mac_rx_length_large =
996 le64_to_cpu(stats->mac_rx_length_large);
997 mac_stats->mac_rx_jabber = le64_to_cpu(stats->mac_rx_jabber);
998 mac_stats->mac_rx_dropped = le64_to_cpu(stats->mac_rx_dropped);
999 mac_stats->mac_rx_crc_error = le64_to_cpu(stats->mac_rx_crc_error);
7e2cf4fe
SC		 1000 } else {
1001 dev_err(&adapter->pdev->dev,
1002 "%s: Get mac stats failed, err=%d.\n", __func__, err);
54a8997c
JK		 1003 }
1004
1005 dma_free_coherent(&adapter->pdev->dev, stats_size, stats_addr,
1006 stats_dma_t);
7e2cf4fe
SC		 1007
1008 qlcnic_free_mbx_args(&cmd);
1009
54a8997c
JK		 1010 return err;
1011}
1012
b6021212
AKS		 1013int qlcnic_get_eswitch_stats(struct qlcnic_adapter *adapter, const u8 eswitch,
1014 const u8 rx_tx, struct __qlcnic_esw_statistics *esw_stats) {
1015
1016 struct __qlcnic_esw_statistics port_stats;
1017 u8 i;
1018 int ret = -EIO;
1019
1020 if (esw_stats == NULL)
1021 return -ENOMEM;
79788450 1022 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
b6021212
AKS		 1023 return -EIO;
1024 if (adapter->npars == NULL)
1025 return -EIO;
1026
ef182805 1027 memset(esw_stats, 0, sizeof(u64));
54a8997c
JK		 1028 esw_stats->unicast_frames = QLCNIC_STATS_NOT_AVAIL;
1029 esw_stats->multicast_frames = QLCNIC_STATS_NOT_AVAIL;
1030 esw_stats->broadcast_frames = QLCNIC_STATS_NOT_AVAIL;
1031 esw_stats->dropped_frames = QLCNIC_STATS_NOT_AVAIL;
1032 esw_stats->errors = QLCNIC_STATS_NOT_AVAIL;
1033 esw_stats->local_frames = QLCNIC_STATS_NOT_AVAIL;
1034 esw_stats->numbytes = QLCNIC_STATS_NOT_AVAIL;
b6021212
AKS		 1035 esw_stats->context_id = eswitch;
1036
bff57d8e 1037 for (i = 0; i < adapter->ahw->act_pci_func; i++) {
b6021212
AKS		 1038 if (adapter->npars[i].phy_port != eswitch)
1039 continue;
1040
1041 memset(&port_stats, 0, sizeof(struct __qlcnic_esw_statistics));
bff57d8e
SC		 1042 if (qlcnic_get_port_stats(adapter, adapter->npars[i].pci_func,
1043 rx_tx, &port_stats))
b6021212
AKS		 1044 continue;
1045
1046 esw_stats->size = port_stats.size;
1047 esw_stats->version = port_stats.version;
ef182805
AKS		 1048 QLCNIC_ADD_ESW_STATS(esw_stats->unicast_frames,
1049 port_stats.unicast_frames);
1050 QLCNIC_ADD_ESW_STATS(esw_stats->multicast_frames,
1051 port_stats.multicast_frames);
1052 QLCNIC_ADD_ESW_STATS(esw_stats->broadcast_frames,
1053 port_stats.broadcast_frames);
1054 QLCNIC_ADD_ESW_STATS(esw_stats->dropped_frames,
1055 port_stats.dropped_frames);
1056 QLCNIC_ADD_ESW_STATS(esw_stats->errors,
1057 port_stats.errors);
1058 QLCNIC_ADD_ESW_STATS(esw_stats->local_frames,
1059 port_stats.local_frames);
1060 QLCNIC_ADD_ESW_STATS(esw_stats->numbytes,
1061 port_stats.numbytes);
b6021212
AKS		 1062 ret = 0;
1063 }
1064 return ret;
1065}
1066
1067int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, const u8 func_esw,
1068 const u8 port, const u8 rx_tx)
1069{
7e2cf4fe 1070 int err;
b6021212 1071 u32 arg1;
7777de9a 1072 struct qlcnic_cmd_args cmd;
b6021212 1073
79788450 1074 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
b6021212
AKS		 1075 return -EIO;
1076
1077 if (func_esw == QLCNIC_STATS_PORT) {
1078 if (port >= QLCNIC_MAX_PCI_FUNC)
1079 goto err_ret;
1080 } else if (func_esw == QLCNIC_STATS_ESWITCH) {
1081 if (port >= QLCNIC_NIU_MAX_XG_PORTS)
1082 goto err_ret;
1083 } else {
1084 goto err_ret;
1085 }
1086
1087 if (rx_tx > QLCNIC_QUERY_TX_COUNTER)
1088 goto err_ret;
1089
1090 arg1 = port | QLCNIC_STATS_VERSION << 8 | func_esw << 12;
1091 arg1 |= BIT_14 | rx_tx << 15;
1092
7e2cf4fe
SC		 1093 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_ESWITCH_STATS);
1094 cmd.req.arg[1] = arg1;
1095 err = qlcnic_issue_cmd(adapter, &cmd);
1096 qlcnic_free_mbx_args(&cmd);
1097 return err;
b6021212
AKS		 1098
1099err_ret:
7e2cf4fe
SC		 1100 dev_err(&adapter->pdev->dev,
1101 "Invalid args func_esw %d port %d rx_ctx %d\n",
1102 func_esw, port, rx_tx);
b6021212
AKS		 1103 return -EIO;
1104}
4e8acb01
RB		 1105
1106static int
1107__qlcnic_get_eswitch_port_config(struct qlcnic_adapter *adapter,
1108 u32 *arg1, u32 *arg2)
1109{
1110 int err = -EIO;
7777de9a 1111 struct qlcnic_cmd_args cmd;
4e8acb01
RB		 1112 u8 pci_func;
1113 pci_func = (*arg1 >> 8);
7777de9a 1114
7e2cf4fe
SC		 1115 qlcnic_alloc_mbx_args(&cmd, adapter,
1116 QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG);
1117 cmd.req.arg[1] = *arg1;
1118 err = qlcnic_issue_cmd(adapter, &cmd);
1119 *arg1 = cmd.rsp.arg[1];
1120 *arg2 = cmd.rsp.arg[2];
1121 qlcnic_free_mbx_args(&cmd);
4e8acb01 1122
7e2cf4fe 1123 if (err == QLCNIC_RCODE_SUCCESS)
4e8acb01 1124 dev_info(&adapter->pdev->dev,
7e2cf4fe
SC		 1125 "eSwitch port config for pci func %d\n", pci_func);
1126 else
4e8acb01 1127 dev_err(&adapter->pdev->dev,
7373373d
RB		 1128 "Failed to get eswitch port config for pci func %d\n",
1129 pci_func);
4e8acb01
RB		 1130 return err;
1131}
1132/* Configure eSwitch port
1133op_mode = 0 for setting default port behavior
1134op_mode = 1 for setting vlan id
1135op_mode = 2 for deleting vlan id
1136op_type = 0 for vlan_id
1137op_type = 1 for port vlan_id
1138*/
1139int qlcnic_config_switch_port(struct qlcnic_adapter *adapter,
1140 struct qlcnic_esw_func_cfg *esw_cfg)
1141{
bff57d8e 1142 int err = -EIO, index;
4e8acb01 1143 u32 arg1, arg2 = 0;
7777de9a 1144 struct qlcnic_cmd_args cmd;
4e8acb01
RB		 1145 u8 pci_func;
1146
79788450 1147 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
4e8acb01
RB		 1148 return err;
1149 pci_func = esw_cfg->pci_func;
bff57d8e
SC		 1150 index = qlcnic_is_valid_nic_func(adapter, pci_func);
1151 if (index < 0)
1152 return err;
1153 arg1 = (adapter->npars[index].phy_port & BIT_0);
4e8acb01
RB		 1154 arg1 |= (pci_func << 8);
1155
1156 if (__qlcnic_get_eswitch_port_config(adapter, &arg1, &arg2))
1157 return err;
1158 arg1 &= ~(0x0ff << 8);
1159 arg1 |= (pci_func << 8);
1160 arg1 &= ~(BIT_2 | BIT_3);
1161 switch (esw_cfg->op_mode) {
1162 case QLCNIC_PORT_DEFAULTS:
1163 arg1 |= (BIT_4 | BIT_6 | BIT_7);
1164 arg2 |= (BIT_0 | BIT_1);
79788450 1165 if (adapter->ahw->capabilities & QLCNIC_FW_CAPABILITY_TSO)
4e8acb01
RB		 1166 arg2 |= (BIT_2 | BIT_3);
1167 if (!(esw_cfg->discard_tagged))
1168 arg1 &= ~BIT_4;
1169 if (!(esw_cfg->promisc_mode))
1170 arg1 &= ~BIT_6;
7373373d 1171 if (!(esw_cfg->mac_override))
4e8acb01
RB		 1172 arg1 &= ~BIT_7;
1173 if (!(esw_cfg->mac_anti_spoof))
1174 arg2 &= ~BIT_0;
1175 if (!(esw_cfg->offload_flags & BIT_0))
1176 arg2 &= ~(BIT_1 | BIT_2 | BIT_3);
1177 if (!(esw_cfg->offload_flags & BIT_1))
1178 arg2 &= ~BIT_2;
1179 if (!(esw_cfg->offload_flags & BIT_2))
1180 arg2 &= ~BIT_3;
1181 break;
1182 case QLCNIC_ADD_VLAN:
1183 arg1 |= (BIT_2 | BIT_5);
1184 arg1 |= (esw_cfg->vlan_id << 16);
1185 break;
1186 case QLCNIC_DEL_VLAN:
1187 arg1 |= (BIT_3 | BIT_5);
1188 arg1 &= ~(0x0ffff << 16);
e9a47700 1189 break;
4e8acb01
RB		 1190 default:
1191 return err;
1192 }
1193
7e2cf4fe
SC		 1194 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_ESWITCH);
1195 cmd.req.arg[1] = arg1;
1196 cmd.req.arg[2] = arg2;
1197 err = qlcnic_issue_cmd(adapter, &cmd);
1198 qlcnic_free_mbx_args(&cmd);
4e8acb01 1199
7e2cf4fe 1200 if (err != QLCNIC_RCODE_SUCCESS)
4e8acb01 1201 dev_err(&adapter->pdev->dev,
7373373d 1202 "Failed to configure eswitch pci func %d\n", pci_func);
7e2cf4fe 1203 else
4e8acb01 1204 dev_info(&adapter->pdev->dev,
7e2cf4fe 1205 "Configured eSwitch for pci func %d\n", pci_func);
4e8acb01
RB		 1206
1207 return err;
1208}
1209
1210int
1211qlcnic_get_eswitch_port_config(struct qlcnic_adapter *adapter,
1212 struct qlcnic_esw_func_cfg *esw_cfg)
1213{
1214 u32 arg1, arg2;
bff57d8e 1215 int index;
4e8acb01 1216 u8 phy_port;
bff57d8e
SC		 1217
1218 if (adapter->ahw->op_mode == QLCNIC_MGMT_FUNC) {
1219 index = qlcnic_is_valid_nic_func(adapter, esw_cfg->pci_func);
1220 if (index < 0)
1221 return -EIO;
1222 phy_port = adapter->npars[index].phy_port;
1223 } else {
79788450 1224 phy_port = adapter->ahw->physical_port;
bff57d8e 1225 }
4e8acb01
RB		 1226 arg1 = phy_port;
1227 arg1 |= (esw_cfg->pci_func << 8);
1228 if (__qlcnic_get_eswitch_port_config(adapter, &arg1, &arg2))
1229 return -EIO;
1230
1231 esw_cfg->discard_tagged = !!(arg1 & BIT_4);
1232 esw_cfg->host_vlan_tag = !!(arg1 & BIT_5);
1233 esw_cfg->promisc_mode = !!(arg1 & BIT_6);
7373373d 1234 esw_cfg->mac_override = !!(arg1 & BIT_7);
4e8acb01
RB		 1235 esw_cfg->vlan_id = LSW(arg1 >> 16);
1236 esw_cfg->mac_anti_spoof = (arg2 & 0x1);
1237 esw_cfg->offload_flags = ((arg2 >> 1) & 0x7);
1238
1239 return 0;
1240}
Linux 6.x block layer and io_uring tree(s)