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qlcnic: Fix TSS/RSS ring validation logic.
[linux-2.6-block.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic_83xx_init.c
CommitLineData
577ae39d
JK		 1/*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
f8468331 8#include "qlcnic_sriov.h"
629263ac
SC		 9#include "qlcnic.h"
10#include "qlcnic_hw.h"
11
81d0aeb0
SC		 12/* Reset template definitions */
13#define QLC_83XX_RESTART_TEMPLATE_SIZE 0x2000
14#define QLC_83XX_RESET_TEMPLATE_ADDR 0x4F0000
15#define QLC_83XX_RESET_SEQ_VERSION 0x0101
16
17#define QLC_83XX_OPCODE_NOP 0x0000
18#define QLC_83XX_OPCODE_WRITE_LIST 0x0001
19#define QLC_83XX_OPCODE_READ_WRITE_LIST 0x0002
20#define QLC_83XX_OPCODE_POLL_LIST 0x0004
21#define QLC_83XX_OPCODE_POLL_WRITE_LIST 0x0008
22#define QLC_83XX_OPCODE_READ_MODIFY_WRITE 0x0010
23#define QLC_83XX_OPCODE_SEQ_PAUSE 0x0020
24#define QLC_83XX_OPCODE_SEQ_END 0x0040
25#define QLC_83XX_OPCODE_TMPL_END 0x0080
26#define QLC_83XX_OPCODE_POLL_READ_LIST 0x0100
27
c0d79cd0
MC		 28/* EPORT control registers */
29#define QLC_83XX_RESET_CONTROL 0x28084E50
30#define QLC_83XX_RESET_REG 0x28084E60
31#define QLC_83XX_RESET_PORT0 0x28084E70
32#define QLC_83XX_RESET_PORT1 0x28084E80
33#define QLC_83XX_RESET_PORT2 0x28084E90
34#define QLC_83XX_RESET_PORT3 0x28084EA0
35#define QLC_83XX_RESET_SRESHIM 0x28084EB0
36#define QLC_83XX_RESET_EPGSHIM 0x28084EC0
37#define QLC_83XX_RESET_ETHERPCS 0x28084ED0
38
629263ac 39static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter);
629263ac
SC		 40static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev);
41static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter);
42
81d0aeb0
SC		 43/* Template header */
44struct qlc_83xx_reset_hdr {
a96227e6 45#if defined(__LITTLE_ENDIAN)
81d0aeb0
SC		 46 u16 version;
47 u16 signature;
48 u16 size;
49 u16 entries;
50 u16 hdr_size;
51 u16 checksum;
52 u16 init_offset;
53 u16 start_offset;
a96227e6
SS		 54#elif defined(__BIG_ENDIAN)
55 u16 signature;
56 u16 version;
57 u16 entries;
58 u16 size;
59 u16 checksum;
60 u16 hdr_size;
61 u16 start_offset;
62 u16 init_offset;
63#endif
81d0aeb0
SC		 64} __packed;
65
66/* Command entry header. */
67struct qlc_83xx_entry_hdr {
a96227e6
SS		 68#if defined(__LITTLE_ENDIAN)
69 u16 cmd;
70 u16 size;
71 u16 count;
72 u16 delay;
73#elif defined(__BIG_ENDIAN)
74 u16 size;
75 u16 cmd;
76 u16 delay;
77 u16 count;
78#endif
81d0aeb0
SC		 79} __packed;
80
81/* Generic poll command */
82struct qlc_83xx_poll {
83 u32 mask;
84 u32 status;
85} __packed;
86
87/* Read modify write command */
88struct qlc_83xx_rmw {
89 u32 mask;
90 u32 xor_value;
91 u32 or_value;
a96227e6 92#if defined(__LITTLE_ENDIAN)
81d0aeb0
SC		 93 u8 shl;
94 u8 shr;
95 u8 index_a;
96 u8 rsvd;
a96227e6
SS		 97#elif defined(__BIG_ENDIAN)
98 u8 rsvd;
99 u8 index_a;
100 u8 shr;
101 u8 shl;
102#endif
81d0aeb0
SC		 103} __packed;
104
105/* Generic command with 2 DWORD */
106struct qlc_83xx_entry {
107 u32 arg1;
108 u32 arg2;
109} __packed;
110
111/* Generic command with 4 DWORD */
112struct qlc_83xx_quad_entry {
113 u32 dr_addr;
114 u32 dr_value;
115 u32 ar_addr;
116 u32 ar_value;
117} __packed;
629263ac
SC		 118static const char *const qlc_83xx_idc_states[] = {
119 "Unknown",
120 "Cold",
121 "Init",
122 "Ready",
123 "Need Reset",
124 "Need Quiesce",
125 "Failed",
126 "Quiesce"
127};
128
629263ac
SC		 129static int
130qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter)
131{
132 u32 val;
133
134 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
135 if ((val & 0xFFFF))
136 return 1;
137 else
138 return 0;
139}
140
141static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter)
142{
143 u32 cur, prev;
144 cur = adapter->ahw->idc.curr_state;
145 prev = adapter->ahw->idc.prev_state;
146
147 dev_info(&adapter->pdev->dev,
148 "current state = %s, prev state = %s\n",
149 adapter->ahw->idc.name[cur],
150 adapter->ahw->idc.name[prev]);
151}
152
153static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter,
154 u8 mode, int lock)
155{
156 u32 val;
157 int seconds;
158
159 if (lock) {
160 if (qlcnic_83xx_lock_driver(adapter))
161 return -EBUSY;
162 }
163
f036e4f4
RB		 164 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
165 val |= (adapter->portnum & 0xf);
629263ac
SC		 166 val |= mode << 7;
167 if (mode)
168 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
169 else
170 seconds = jiffies / HZ;
171
172 val |= seconds << 8;
173 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val);
174 adapter->ahw->idc.sec_counter = jiffies / HZ;
175
176 if (lock)
177 qlcnic_83xx_unlock_driver(adapter);
178
179 return 0;
180}
181
182static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter)
183{
184 u32 val;
185
186 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION);
187 val = val & ~(0x3 << (adapter->portnum * 2));
188 val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2));
189 QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val);
190}
191
192static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter,
193 int lock)
194{
195 u32 val;
196
197 if (lock) {
198 if (qlcnic_83xx_lock_driver(adapter))
199 return -EBUSY;
200 }
201
202 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
203 val = val & ~0xFF;
204 val = val | QLC_83XX_IDC_MAJOR_VERSION;
205 QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val);
206
207 if (lock)
208 qlcnic_83xx_unlock_driver(adapter);
209
210 return 0;
211}
212
213static int
214qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter,
215 int status, int lock)
216{
217 u32 val;
218
219 if (lock) {
220 if (qlcnic_83xx_lock_driver(adapter))
221 return -EBUSY;
222 }
223
224 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
225
226 if (status)
227 val = val | (1 << adapter->portnum);
228 else
229 val = val & ~(1 << adapter->portnum);
230
231 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
232 qlcnic_83xx_idc_update_minor_version(adapter);
233
234 if (lock)
235 qlcnic_83xx_unlock_driver(adapter);
236
237 return 0;
238}
239
240static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter)
241{
242 u32 val;
243 u8 version;
244
245 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
246 version = val & 0xFF;
247
248 if (version != QLC_83XX_IDC_MAJOR_VERSION) {
249 dev_info(&adapter->pdev->dev,
250 "%s:mismatch. version 0x%x, expected version 0x%x\n",
251 __func__, version, QLC_83XX_IDC_MAJOR_VERSION);
252 return -EIO;
253 }
254
255 return 0;
256}
257
258static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter,
259 int lock)
260{
261 u32 val;
262
263 if (lock) {
264 if (qlcnic_83xx_lock_driver(adapter))
265 return -EBUSY;
266 }
267
268 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0);
269 /* Clear gracefull reset bit */
270 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
271 val &= ~QLC_83XX_IDC_GRACEFULL_RESET;
272 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
273
274 if (lock)
275 qlcnic_83xx_unlock_driver(adapter);
276
277 return 0;
278}
279
280static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter,
281 int flag, int lock)
282{
283 u32 val;
284
285 if (lock) {
286 if (qlcnic_83xx_lock_driver(adapter))
287 return -EBUSY;
288 }
289
290 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
291 if (flag)
292 val = val | (1 << adapter->portnum);
293 else
294 val = val & ~(1 << adapter->portnum);
295 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val);
296
297 if (lock)
298 qlcnic_83xx_unlock_driver(adapter);
299
300 return 0;
301}
302
303static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter,
304 int time_limit)
305{
306 u64 seconds;
307
308 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
309 if (seconds <= time_limit)
310 return 0;
311 else
312 return -EBUSY;
313}
314
315/**
316 * qlcnic_83xx_idc_check_reset_ack_reg
317 *
318 * @adapter: adapter structure
319 *
320 * Check ACK wait limit and clear the functions which failed to ACK
321 *
322 * Return 0 if all functions have acknowledged the reset request.
323 **/
324static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter)
325{
326 int timeout;
327 u32 ack, presence, val;
328
329 timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
330 ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
331 presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
332 dev_info(&adapter->pdev->dev,
333 "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence);
334 if (!((ack & presence) == presence)) {
335 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) {
336 /* Clear functions which failed to ACK */
337 dev_info(&adapter->pdev->dev,
338 "%s: ACK wait exceeds time limit\n", __func__);
339 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
340 val = val & ~(ack ^ presence);
341 if (qlcnic_83xx_lock_driver(adapter))
342 return -EBUSY;
343 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
344 dev_info(&adapter->pdev->dev,
345 "%s: updated drv presence reg = 0x%x\n",
346 __func__, val);
347 qlcnic_83xx_unlock_driver(adapter);
348 return 0;
349
350 } else {
351 return 1;
352 }
353 } else {
354 dev_info(&adapter->pdev->dev,
355 "%s: Reset ACK received from all functions\n",
356 __func__);
357 return 0;
358 }
359}
360
361/**
362 * qlcnic_83xx_idc_tx_soft_reset
363 *
364 * @adapter: adapter structure
365 *
366 * Handle context deletion and recreation request from transmit routine
367 *
368 * Returns -EBUSY or Success (0)
369 *
370 **/
371static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter)
372{
373 struct net_device *netdev = adapter->netdev;
374
375 if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
376 return -EBUSY;
377
378 netif_device_detach(netdev);
379 qlcnic_down(adapter, netdev);
380 qlcnic_up(adapter, netdev);
381 netif_device_attach(netdev);
382 clear_bit(__QLCNIC_RESETTING, &adapter->state);
383 dev_err(&adapter->pdev->dev, "%s:\n", __func__);
384
629263ac
SC		 385 return 0;
386}
387
388/**
389 * qlcnic_83xx_idc_detach_driver
390 *
391 * @adapter: adapter structure
392 * Detach net interface, stop TX and cleanup resources before the HW reset.
393 * Returns: None
394 *
395 **/
396static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter)
397{
398 int i;
399 struct net_device *netdev = adapter->netdev;
400
401 netif_device_detach(netdev);
068a8d19 402 qlcnic_83xx_detach_mailbox_work(adapter);
f036e4f4 403
629263ac 404 /* Disable mailbox interrupt */
f036e4f4 405 qlcnic_83xx_disable_mbx_intr(adapter);
629263ac
SC		 406 qlcnic_down(adapter, netdev);
407 for (i = 0; i < adapter->ahw->num_msix; i++) {
408 adapter->ahw->intr_tbl[i].id = i;
409 adapter->ahw->intr_tbl[i].enabled = 0;
410 adapter->ahw->intr_tbl[i].src = 0;
411 }
f036e4f4
RB		 412
413 if (qlcnic_sriov_pf_check(adapter))
414 qlcnic_sriov_pf_reset(adapter);
629263ac
SC		 415}
416
417/**
418 * qlcnic_83xx_idc_attach_driver
419 *
420 * @adapter: adapter structure
421 *
422 * Re-attach and re-enable net interface
423 * Returns: None
424 *
425 **/
426static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter)
427{
428 struct net_device *netdev = adapter->netdev;
429
430 if (netif_running(netdev)) {
431 if (qlcnic_up(adapter, netdev))
432 goto done;
433 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
434 }
435done:
436 netif_device_attach(netdev);
629263ac
SC		 437}
438
439static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter,
440 int lock)
441{
442 if (lock) {
443 if (qlcnic_83xx_lock_driver(adapter))
444 return -EBUSY;
445 }
446
447 qlcnic_83xx_idc_clear_registers(adapter, 0);
448 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED);
449 if (lock)
450 qlcnic_83xx_unlock_driver(adapter);
451
452 qlcnic_83xx_idc_log_state_history(adapter);
453 dev_info(&adapter->pdev->dev, "Device will enter failed state\n");
454
455 return 0;
456}
457
458static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter,
459 int lock)
460{
461 if (lock) {
462 if (qlcnic_83xx_lock_driver(adapter))
463 return -EBUSY;
464 }
465
466 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT);
467
468 if (lock)
469 qlcnic_83xx_unlock_driver(adapter);
470
471 return 0;
472}
473
474static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter,
475 int lock)
476{
477 if (lock) {
478 if (qlcnic_83xx_lock_driver(adapter))
479 return -EBUSY;
480 }
481
482 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
483 QLC_83XX_IDC_DEV_NEED_QUISCENT);
484
485 if (lock)
486 qlcnic_83xx_unlock_driver(adapter);
487
488 return 0;
489}
490
491static int
492qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock)
493{
494 if (lock) {
495 if (qlcnic_83xx_lock_driver(adapter))
496 return -EBUSY;
497 }
498
499 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
500 QLC_83XX_IDC_DEV_NEED_RESET);
501
502 if (lock)
503 qlcnic_83xx_unlock_driver(adapter);
504
505 return 0;
506}
507
508static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter,
509 int lock)
510{
511 if (lock) {
512 if (qlcnic_83xx_lock_driver(adapter))
513 return -EBUSY;
514 }
515
516 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY);
517 if (lock)
518 qlcnic_83xx_unlock_driver(adapter);
519
520 return 0;
521}
522
523/**
524 * qlcnic_83xx_idc_find_reset_owner_id
525 *
526 * @adapter: adapter structure
527 *
528 * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE.
529 * Within the same class, function with lowest PCI ID assumes ownership
530 *
531 * Returns: reset owner id or failure indication (-EIO)
532 *
533 **/
534static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter)
535{
536 u32 reg, reg1, reg2, i, j, owner, class;
537
538 reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1);
539 reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2);
540 owner = QLCNIC_TYPE_NIC;
541 i = 0;
542 j = 0;
543 reg = reg1;
544
545 do {
546 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3);
547 if (class == owner)
548 break;
549 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) {
550 reg = reg2;
551 j = 0;
552 } else {
553 j++;
554 }
555
556 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) {
557 if (owner == QLCNIC_TYPE_NIC)
558 owner = QLCNIC_TYPE_ISCSI;
559 else if (owner == QLCNIC_TYPE_ISCSI)
560 owner = QLCNIC_TYPE_FCOE;
561 else if (owner == QLCNIC_TYPE_FCOE)
562 return -EIO;
563 reg = reg1;
564 j = 0;
565 i = 0;
566 }
567 } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS);
568
569 return i;
570}
571
572static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock)
573{
574 int ret = 0;
575
576 ret = qlcnic_83xx_restart_hw(adapter);
577
578 if (ret) {
579 qlcnic_83xx_idc_enter_failed_state(adapter, lock);
580 } else {
581 qlcnic_83xx_idc_clear_registers(adapter, lock);
582 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock);
583 }
584
585 return ret;
586}
587
588static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter)
589{
590 u32 status;
591
592 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1);
593
594 if (status & QLCNIC_RCODE_FATAL_ERROR) {
595 dev_err(&adapter->pdev->dev,
596 "peg halt status1=0x%x\n", status);
597 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) {
598 dev_err(&adapter->pdev->dev,
599 "On board active cooling fan failed. "
600 "Device has been halted.\n");
601 dev_err(&adapter->pdev->dev,
602 "Replace the adapter.\n");
603 return -EIO;
604 }
605 }
606
607 return 0;
608}
609
486a5bc7 610int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter)
629263ac 611{
f036e4f4
RB		 612 int err;
613
068a8d19
MC		 614 qlcnic_83xx_reinit_mbx_work(adapter->ahw->mailbox);
615 qlcnic_83xx_enable_mbx_interrupt(adapter);
616
d5fcff04
HM		 617 /* register for NIC IDC AEN Events */
618 qlcnic_83xx_register_nic_idc_func(adapter, 1);
619
f036e4f4
RB		 620 err = qlcnic_sriov_pf_reinit(adapter);
621 if (err)
622 return err;
623
e5c4e6c6 624 qlcnic_83xx_enable_mbx_interrupt(adapter);
629263ac
SC		 625
626 if (qlcnic_83xx_configure_opmode(adapter)) {
627 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
628 return -EIO;
629 }
630
631 if (adapter->nic_ops->init_driver(adapter)) {
632 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
633 return -EIO;
634 }
635
24866d15
HM		 636 if (adapter->portnum == 0)
637 qlcnic_set_drv_version(adapter);
14d385b9 638
1de899d3 639 qlcnic_dcb_get_info(adapter->dcb);
629263ac
SC		 640 qlcnic_83xx_idc_attach_driver(adapter);
641
642 return 0;
643}
644
645static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter)
646{
536faa61
SC		 647 struct qlcnic_hardware_context *ahw = adapter->ahw;
648
629263ac 649 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1);
629263ac
SC		 650 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
651 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
536faa61
SC		 652
653 ahw->idc.quiesce_req = 0;
654 ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
655 ahw->idc.err_code = 0;
656 ahw->idc.collect_dump = 0;
657 ahw->reset_context = 0;
658 adapter->tx_timeo_cnt = 0;
099907fa 659 ahw->idc.delay_reset = 0;
536faa61
SC		 660
661 clear_bit(__QLCNIC_RESETTING, &adapter->state);
629263ac
SC		 662}
663
664/**
665 * qlcnic_83xx_idc_ready_state_entry
666 *
667 * @adapter: adapter structure
668 *
669 * Perform ready state initialization, this routine will get invoked only
670 * once from READY state.
671 *
672 * Returns: Error code or Success(0)
673 *
674 **/
675int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter)
676{
677 struct qlcnic_hardware_context *ahw = adapter->ahw;
678
679 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) {
680 qlcnic_83xx_idc_update_idc_params(adapter);
681 /* Re-attach the device if required */
682 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
683 (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) {
684 if (qlcnic_83xx_idc_reattach_driver(adapter))
685 return -EIO;
686 }
687 }
688
689 return 0;
690}
691
d71170fb
SC		 692/**
693 * qlcnic_83xx_idc_vnic_pf_entry
694 *
695 * @adapter: adapter structure
696 *
697 * Ensure vNIC mode privileged function starts only after vNIC mode is
698 * enabled by management function.
699 * If vNIC mode is ready, start initialization.
700 *
701 * Returns: -EIO or 0
702 *
703 **/
704int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter)
705{
706 u32 state;
707 struct qlcnic_hardware_context *ahw = adapter->ahw;
708
709 /* Privileged function waits till mgmt function enables VNIC mode */
710 state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE);
711 if (state != QLCNIC_DEV_NPAR_OPER) {
712 if (!ahw->idc.vnic_wait_limit--) {
713 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
714 return -EIO;
715 }
716 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n");
717 return -EIO;
718
719 } else {
720 /* Perform one time initialization from ready state */
721 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) {
722 qlcnic_83xx_idc_update_idc_params(adapter);
723
724 /* If the previous state is UNKNOWN, device will be
725 already attached properly by Init routine*/
726 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) {
727 if (qlcnic_83xx_idc_reattach_driver(adapter))
728 return -EIO;
729 }
730 adapter->ahw->idc.vnic_state = QLCNIC_DEV_NPAR_OPER;
731 dev_info(&adapter->pdev->dev, "vNIC mode enabled\n");
732 }
733 }
734
735 return 0;
736}
737
629263ac
SC		 738static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter)
739{
740 adapter->ahw->idc.err_code = -EIO;
741 dev_err(&adapter->pdev->dev,
742 "%s: Device in unknown state\n", __func__);
743 return 0;
744}
745
746/**
747 * qlcnic_83xx_idc_cold_state
748 *
749 * @adapter: adapter structure
750 *
751 * If HW is up and running device will enter READY state.
752 * If firmware image from host needs to be loaded, device is
753 * forced to start with the file firmware image.
754 *
755 * Returns: Error code or Success(0)
756 *
757 **/
758static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter)
759{
760 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0);
761 qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0);
762
763 if (qlcnic_load_fw_file) {
764 qlcnic_83xx_idc_restart_hw(adapter, 0);
765 } else {
766 if (qlcnic_83xx_check_hw_status(adapter)) {
767 qlcnic_83xx_idc_enter_failed_state(adapter, 0);
768 return -EIO;
769 } else {
770 qlcnic_83xx_idc_enter_ready_state(adapter, 0);
771 }
772 }
773 return 0;
774}
775
776/**
777 * qlcnic_83xx_idc_init_state
778 *
779 * @adapter: adapter structure
780 *
781 * Reset owner will restart the device from this state.
782 * Device will enter failed state if it remains
783 * in this state for more than DEV_INIT time limit.
784 *
785 * Returns: Error code or Success(0)
786 *
787 **/
788static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter)
789{
790 int timeout, ret = 0;
791 u32 owner;
792
793 timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
794 if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) {
795 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
796 if (adapter->ahw->pci_func == owner)
797 ret = qlcnic_83xx_idc_restart_hw(adapter, 1);
798 } else {
799 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout);
629263ac
SC		 800 }
801
802 return ret;
803}
804
805/**
806 * qlcnic_83xx_idc_ready_state
807 *
808 * @adapter: adapter structure
809 *
810 * Perform IDC protocol specicifed actions after monitoring device state and
811 * events.
812 *
813 * Returns: Error code or Success(0)
814 *
815 **/
816static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter)
817{
629263ac 818 struct qlcnic_hardware_context *ahw = adapter->ahw;
068a8d19 819 struct qlcnic_mailbox *mbx = ahw->mailbox;
629263ac 820 int ret = 0;
891e71b1 821 u32 owner;
068a8d19 822 u32 val;
629263ac
SC		 823
824 /* Perform NIC configuration based ready state entry actions */
825 if (ahw->idc.state_entry(adapter))
826 return -EIO;
827
828 if (qlcnic_check_temp(adapter)) {
829 if (ahw->temp == QLCNIC_TEMP_PANIC) {
830 qlcnic_83xx_idc_check_fan_failure(adapter);
831 dev_err(&adapter->pdev->dev,
832 "Error: device temperature %d above limits\n",
833 adapter->ahw->temp);
068a8d19 834 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
629263ac
SC		 835 set_bit(__QLCNIC_RESETTING, &adapter->state);
836 qlcnic_83xx_idc_detach_driver(adapter);
837 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
838 return -EIO;
839 }
840 }
841
842 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
843 ret = qlcnic_83xx_check_heartbeat(adapter);
844 if (ret) {
845 adapter->flags |= QLCNIC_FW_HANG;
846 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
068a8d19 847 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
629263ac
SC		 848 set_bit(__QLCNIC_RESETTING, &adapter->state);
849 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
891e71b1
PP		 850 } else {
851 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
852 if (ahw->pci_func == owner)
853 qlcnic_dump_fw(adapter);
629263ac
SC		 854 }
855 return -EIO;
856 }
857
858 if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) {
068a8d19
MC		 859 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
860
629263ac
SC		 861 /* Move to need reset state and prepare for reset */
862 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
863 return ret;
864 }
865
866 /* Check for soft reset request */
867 if (ahw->reset_context &&
868 !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
536faa61 869 adapter->ahw->reset_context = 0;
629263ac
SC		 870 qlcnic_83xx_idc_tx_soft_reset(adapter);
871 return ret;
872 }
873
874 /* Move to need quiesce state if requested */
875 if (adapter->ahw->idc.quiesce_req) {
876 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1);
877 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
878 return ret;
879 }
880
881 return ret;
882}
883
884/**
885 * qlcnic_83xx_idc_need_reset_state
886 *
887 * @adapter: adapter structure
888 *
889 * Device will remain in this state until:
890 * Reset request ACK's are recieved from all the functions
891 * Wait time exceeds max time limit
892 *
893 * Returns: Error code or Success(0)
894 *
895 **/
896static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter)
897{
068a8d19 898 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
629263ac
SC		 899 int ret = 0;
900
901 if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) {
629263ac
SC		 902 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
903 set_bit(__QLCNIC_RESETTING, &adapter->state);
068a8d19 904 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
34e8c406 905 if (adapter->ahw->nic_mode == QLCNIC_VNIC_MODE)
d71170fb 906 qlcnic_83xx_disable_vnic_mode(adapter, 1);
099907fa
SC		 907
908 if (qlcnic_check_diag_status(adapter)) {
909 dev_info(&adapter->pdev->dev,
910 "%s: Wait for diag completion\n", __func__);
911 adapter->ahw->idc.delay_reset = 1;
912 return 0;
913 } else {
914 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
915 qlcnic_83xx_idc_detach_driver(adapter);
916 }
629263ac
SC		 917 }
918
099907fa 919 if (qlcnic_check_diag_status(adapter)) {
629263ac 920 dev_info(&adapter->pdev->dev,
099907fa
SC		 921 "%s: Wait for diag completion\n", __func__);
922 return -1;
923 } else {
924 if (adapter->ahw->idc.delay_reset) {
925 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
926 qlcnic_83xx_idc_detach_driver(adapter);
927 adapter->ahw->idc.delay_reset = 0;
928 }
929
930 /* Check for ACK from other functions */
931 ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter);
932 if (ret) {
933 dev_info(&adapter->pdev->dev,
934 "%s: Waiting for reset ACK\n", __func__);
935 return -1;
936 }
629263ac
SC		 937 }
938
939 /* Transit to INIT state and restart the HW */
940 qlcnic_83xx_idc_enter_init_state(adapter, 1);
941
942 return ret;
943}
944
945static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter)
946{
947 dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__);
948 return 0;
949}
950
951static int qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter)
952{
953 dev_err(&adapter->pdev->dev, "%s: please restart!!\n", __func__);
536faa61 954 clear_bit(__QLCNIC_RESETTING, &adapter->state);
629263ac
SC		 955 adapter->ahw->idc.err_code = -EIO;
956
957 return 0;
958}
959
960static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter)
961{
962 dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__);
963 return 0;
964}
965
966static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter,
967 u32 state)
968{
969 u32 cur, prev, next;
970
971 cur = adapter->ahw->idc.curr_state;
972 prev = adapter->ahw->idc.prev_state;
973 next = state;
974
975 if ((next < QLC_83XX_IDC_DEV_COLD) ||
976 (next > QLC_83XX_IDC_DEV_QUISCENT)) {
977 dev_err(&adapter->pdev->dev,
978 "%s: curr %d, prev %d, next state %d is invalid\n",
979 __func__, cur, prev, state);
980 return 1;
981 }
982
983 if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) &&
984 (prev == QLC_83XX_IDC_DEV_UNKNOWN)) {
985 if ((next != QLC_83XX_IDC_DEV_COLD) &&
986 (next != QLC_83XX_IDC_DEV_READY)) {
987 dev_err(&adapter->pdev->dev,
988 "%s: failed, cur %d prev %d next %d\n",
989 __func__, cur, prev, next);
990 return 1;
991 }
992 }
993
994 if (next == QLC_83XX_IDC_DEV_INIT) {
995 if ((prev != QLC_83XX_IDC_DEV_INIT) &&
996 (prev != QLC_83XX_IDC_DEV_COLD) &&
997 (prev != QLC_83XX_IDC_DEV_NEED_RESET)) {
998 dev_err(&adapter->pdev->dev,
999 "%s: failed, cur %d prev %d next %d\n",
1000 __func__, cur, prev, next);
1001 return 1;
1002 }
1003 }
1004
1005 return 0;
1006}
1007
1008static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter)
1009{
1010 if (adapter->fhash.fnum)
1011 qlcnic_prune_lb_filters(adapter);
1012}
1013
1014/**
1015 * qlcnic_83xx_idc_poll_dev_state
1016 *
1017 * @work: kernel work queue structure used to schedule the function
1018 *
1019 * Poll device state periodically and perform state specific
1020 * actions defined by Inter Driver Communication (IDC) protocol.
1021 *
1022 * Returns: None
1023 *
1024 **/
1025void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work)
1026{
1027 struct qlcnic_adapter *adapter;
1028 u32 state;
1029
1030 adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
1031 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1032
1033 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1034 qlcnic_83xx_idc_log_state_history(adapter);
1035 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1036 } else {
1037 adapter->ahw->idc.curr_state = state;
1038 }
1039
1040 switch (adapter->ahw->idc.curr_state) {
1041 case QLC_83XX_IDC_DEV_READY:
1042 qlcnic_83xx_idc_ready_state(adapter);
1043 break;
1044 case QLC_83XX_IDC_DEV_NEED_RESET:
1045 qlcnic_83xx_idc_need_reset_state(adapter);
1046 break;
1047 case QLC_83XX_IDC_DEV_NEED_QUISCENT:
1048 qlcnic_83xx_idc_need_quiesce_state(adapter);
1049 break;
1050 case QLC_83XX_IDC_DEV_FAILED:
1051 qlcnic_83xx_idc_failed_state(adapter);
1052 return;
1053 case QLC_83XX_IDC_DEV_INIT:
1054 qlcnic_83xx_idc_init_state(adapter);
1055 break;
1056 case QLC_83XX_IDC_DEV_QUISCENT:
1057 qlcnic_83xx_idc_quiesce_state(adapter);
1058 break;
1059 default:
1060 qlcnic_83xx_idc_unknown_state(adapter);
1061 return;
1062 }
1063 adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state;
1064 qlcnic_83xx_periodic_tasks(adapter);
1065
891e71b1
PP		 1066 /* Do not reschedule if firmaware is in hanged state and auto
1067 * recovery is disabled
1068 */
1069 if ((adapter->flags & QLCNIC_FW_HANG) && !qlcnic_auto_fw_reset)
1070 return;
1071
629263ac
SC		 1072 /* Re-schedule the function */
1073 if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status))
1074 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
1075 adapter->ahw->idc.delay);
1076}
1077
1078static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter)
1079{
1080 u32 idc_params, val;
1081
1082 if (qlcnic_83xx_lockless_flash_read32(adapter,
1083 QLC_83XX_IDC_FLASH_PARAM_ADDR,
1084 (u8 *)&idc_params, 1)) {
1085 dev_info(&adapter->pdev->dev,
1086 "%s:failed to get IDC params from flash\n", __func__);
1087 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
1088 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
1089 } else {
1090 adapter->dev_init_timeo = idc_params & 0xFFFF;
1091 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF);
1092 }
1093
1094 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1095 adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN;
1096 adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
1097 adapter->ahw->idc.err_code = 0;
1098 adapter->ahw->idc.collect_dump = 0;
1099 adapter->ahw->idc.name = (char **)qlc_83xx_idc_states;
1100
1101 clear_bit(__QLCNIC_RESETTING, &adapter->state);
629263ac
SC		 1102 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1103
1104 /* Check if reset recovery is disabled */
1105 if (!qlcnic_auto_fw_reset) {
1106 /* Propagate do not reset request to other functions */
1107 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1108 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1109 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1110 }
1111}
1112
1113static int
1114qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter)
1115{
1116 u32 state, val;
1117
1118 if (qlcnic_83xx_lock_driver(adapter))
1119 return -EIO;
1120
1121 /* Clear driver lock register */
1122 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0);
1123 if (qlcnic_83xx_idc_update_major_version(adapter, 0)) {
1124 qlcnic_83xx_unlock_driver(adapter);
1125 return -EIO;
1126 }
1127
1128 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1129 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1130 qlcnic_83xx_unlock_driver(adapter);
1131 return -EIO;
1132 }
1133
1134 if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) {
1135 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
1136 QLC_83XX_IDC_DEV_COLD);
1137 state = QLC_83XX_IDC_DEV_COLD;
1138 }
1139
1140 adapter->ahw->idc.curr_state = state;
1141 /* First to load function should cold boot the device */
1142 if (state == QLC_83XX_IDC_DEV_COLD)
1143 qlcnic_83xx_idc_cold_state_handler(adapter);
1144
1145 /* Check if reset recovery is enabled */
1146 if (qlcnic_auto_fw_reset) {
1147 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1148 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1149 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1150 }
1151
1152 qlcnic_83xx_unlock_driver(adapter);
1153
1154 return 0;
1155}
1156
486a5bc7 1157int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter)
629263ac 1158{
81d0aeb0
SC		 1159 int ret = -EIO;
1160
629263ac
SC		 1161 qlcnic_83xx_setup_idc_parameters(adapter);
1162
81d0aeb0
SC		 1163 if (qlcnic_83xx_get_reset_instruction_template(adapter))
1164 return ret;
1165
629263ac
SC		 1166 if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) {
1167 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter))
1168 return -EIO;
1169 } else {
1170 if (qlcnic_83xx_idc_check_major_version(adapter))
1171 return -EIO;
1172 }
1173
1174 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
1175
1176 return 0;
1177}
1178
1179void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter)
1180{
1181 int id;
1182 u32 val;
1183
1184 while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1185 usleep_range(10000, 11000);
1186
1187 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1188 id = id & 0xFF;
1189
1190 if (id == adapter->portnum) {
1191 dev_err(&adapter->pdev->dev,
1192 "%s: wait for lock recovery.. %d\n", __func__, id);
1193 msleep(20);
1194 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1195 id = id & 0xFF;
1196 }
1197
1198 /* Clear driver presence bit */
1199 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
1200 val = val & ~(1 << adapter->portnum);
1201 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
1202 clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1203 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1204
1205 cancel_delayed_work_sync(&adapter->fw_work);
1206}
1207
1208void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key)
1209{
1210 u32 val;
1211
068a8d19
MC		 1212 if (qlcnic_sriov_vf_check(adapter))
1213 return;
1214
629263ac
SC		 1215 if (qlcnic_83xx_lock_driver(adapter)) {
1216 dev_err(&adapter->pdev->dev,
1217 "%s:failed, please retry\n", __func__);
1218 return;
1219 }
1220
1221 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1222 if ((val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) ||
1223 !qlcnic_auto_fw_reset) {
1224 dev_err(&adapter->pdev->dev,
1225 "%s:failed, device in non reset mode\n", __func__);
1226 qlcnic_83xx_unlock_driver(adapter);
1227 return;
1228 }
1229
1230 if (key == QLCNIC_FORCE_FW_RESET) {
1231 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1232 val = val | QLC_83XX_IDC_GRACEFULL_RESET;
1233 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1234 } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) {
1235 adapter->ahw->idc.collect_dump = 1;
1236 }
1237
1238 qlcnic_83xx_unlock_driver(adapter);
1239 return;
1240}
1241
1242static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter)
1243{
1244 u8 *p_cache;
1245 u32 src, size;
1246 u64 dest;
1247 int ret = -EIO;
1248
1249 src = QLC_83XX_BOOTLOADER_FLASH_ADDR;
1250 dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR);
1251 size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE);
1252
1253 /* alignment check */
1254 if (size & 0xF)
1255 size = (size + 16) & ~0xF;
1256
1257 p_cache = kzalloc(size, GFP_KERNEL);
b2adaca9 1258 if (p_cache == NULL)
629263ac 1259 return -ENOMEM;
b2adaca9 1260
629263ac
SC		 1261 ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache,
1262 size / sizeof(u32));
1263 if (ret) {
1264 kfree(p_cache);
1265 return ret;
1266 }
1267 /* 16 byte write to MS memory */
1268 ret = qlcnic_83xx_ms_mem_write128(adapter, dest, (u32 *)p_cache,
1269 size / 16);
1270 if (ret) {
1271 kfree(p_cache);
1272 return ret;
1273 }
1274 kfree(p_cache);
1275
1276 return ret;
1277}
1278
1279static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter)
1280{
7000078a
PP		 1281 struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info;
1282 const struct firmware *fw = fw_info->fw;
629263ac 1283 u32 dest, *p_cache;
7000078a 1284 int i, ret = -EIO;
629263ac
SC		 1285 u8 data[16];
1286 size_t size;
7000078a 1287 u64 addr;
629263ac
SC		 1288
1289 dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR);
7000078a
PP		 1290 size = (fw->size & ~0xF);
1291 p_cache = (u32 *)fw->data;
629263ac
SC		 1292 addr = (u64)dest;
1293
1294 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1295 (u32 *)p_cache, size / 16);
1296 if (ret) {
1297 dev_err(&adapter->pdev->dev, "MS memory write failed\n");
7000078a
PP		 1298 release_firmware(fw);
1299 fw_info->fw = NULL;
629263ac
SC		 1300 return -EIO;
1301 }
1302
1303 /* alignment check */
7000078a 1304 if (fw->size & 0xF) {
629263ac 1305 addr = dest + size;
7000078a
PP		 1306 for (i = 0; i < (fw->size & 0xF); i++)
1307 data[i] = fw->data[size + i];
629263ac
SC		 1308 for (; i < 16; i++)
1309 data[i] = 0;
1310 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1311 (u32 *)data, 1);
1312 if (ret) {
1313 dev_err(&adapter->pdev->dev,
1314 "MS memory write failed\n");
7000078a
PP		 1315 release_firmware(fw);
1316 fw_info->fw = NULL;
629263ac
SC		 1317 return -EIO;
1318 }
1319 }
7000078a
PP		 1320 release_firmware(fw);
1321 fw_info->fw = NULL;
629263ac
SC		 1322
1323 return 0;
1324}
1325
1326static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter)
1327{
1328 int i, j;
1329 u32 val = 0, val1 = 0, reg = 0;
4bd8e738 1330 int err = 0;
629263ac 1331
4bd8e738
HM		 1332 val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG, &err);
1333 if (err == -EIO)
1334 return;
629263ac
SC		 1335 dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val);
1336
1337 for (j = 0; j < 2; j++) {
1338 if (j == 0) {
1339 dev_info(&adapter->pdev->dev,
1340 "Port 0 RxB Pause Threshold Regs[TC7..TC0]:");
1341 reg = QLC_83XX_PORT0_THRESHOLD;
1342 } else if (j == 1) {
1343 dev_info(&adapter->pdev->dev,
1344 "Port 1 RxB Pause Threshold Regs[TC7..TC0]:");
1345 reg = QLC_83XX_PORT1_THRESHOLD;
1346 }
1347 for (i = 0; i < 8; i++) {
4bd8e738
HM		 1348 val = QLCRD32(adapter, reg + (i * 0x4), &err);
1349 if (err == -EIO)
1350 return;
629263ac
SC		 1351 dev_info(&adapter->pdev->dev, "0x%x ", val);
1352 }
1353 dev_info(&adapter->pdev->dev, "\n");
1354 }
1355
1356 for (j = 0; j < 2; j++) {
1357 if (j == 0) {
1358 dev_info(&adapter->pdev->dev,
1359 "Port 0 RxB TC Max Cell Registers[4..1]:");
1360 reg = QLC_83XX_PORT0_TC_MC_REG;
1361 } else if (j == 1) {
1362 dev_info(&adapter->pdev->dev,
1363 "Port 1 RxB TC Max Cell Registers[4..1]:");
1364 reg = QLC_83XX_PORT1_TC_MC_REG;
1365 }
1366 for (i = 0; i < 4; i++) {
4bd8e738
HM		 1367 val = QLCRD32(adapter, reg + (i * 0x4), &err);
1368 if (err == -EIO)
1369 return;
1370 dev_info(&adapter->pdev->dev, "0x%x ", val);
629263ac
SC		 1371 }
1372 dev_info(&adapter->pdev->dev, "\n");
1373 }
1374
1375 for (j = 0; j < 2; j++) {
1376 if (j == 0) {
1377 dev_info(&adapter->pdev->dev,
1378 "Port 0 RxB Rx TC Stats[TC7..TC0]:");
1379 reg = QLC_83XX_PORT0_TC_STATS;
1380 } else if (j == 1) {
1381 dev_info(&adapter->pdev->dev,
1382 "Port 1 RxB Rx TC Stats[TC7..TC0]:");
1383 reg = QLC_83XX_PORT1_TC_STATS;
1384 }
1385 for (i = 7; i >= 0; i--) {
4bd8e738
HM		 1386 val = QLCRD32(adapter, reg, &err);
1387 if (err == -EIO)
1388 return;
629263ac
SC		 1389 val &= ~(0x7 << 29); /* Reset bits 29 to 31 */
1390 QLCWR32(adapter, reg, (val | (i << 29)));
4bd8e738
HM		 1391 val = QLCRD32(adapter, reg, &err);
1392 if (err == -EIO)
1393 return;
629263ac
SC		 1394 dev_info(&adapter->pdev->dev, "0x%x ", val);
1395 }
1396 dev_info(&adapter->pdev->dev, "\n");
1397 }
1398
4bd8e738
HM		 1399 val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, &err);
1400 if (err == -EIO)
1401 return;
1402 val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, &err);
1403 if (err == -EIO)
1404 return;
629263ac
SC		 1405 dev_info(&adapter->pdev->dev,
1406 "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n",
1407 val, val1);
1408}
1409
81d0aeb0 1410
629263ac
SC		 1411static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter)
1412{
1413 u32 reg = 0, i, j;
1414
1415 if (qlcnic_83xx_lock_driver(adapter)) {
1416 dev_err(&adapter->pdev->dev,
1417 "%s:failed to acquire driver lock\n", __func__);
1418 return;
1419 }
1420
1421 qlcnic_83xx_dump_pause_control_regs(adapter);
1422 QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0);
1423
1424 for (j = 0; j < 2; j++) {
1425 if (j == 0)
1426 reg = QLC_83XX_PORT0_THRESHOLD;
1427 else if (j == 1)
1428 reg = QLC_83XX_PORT1_THRESHOLD;
1429
1430 for (i = 0; i < 8; i++)
1431 QLCWR32(adapter, reg + (i * 0x4), 0x0);
1432 }
1433
1434 for (j = 0; j < 2; j++) {
1435 if (j == 0)
1436 reg = QLC_83XX_PORT0_TC_MC_REG;
1437 else if (j == 1)
1438 reg = QLC_83XX_PORT1_TC_MC_REG;
1439
1440 for (i = 0; i < 4; i++)
1441 QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF);
1442 }
1443
1444 QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0);
1445 QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0);
1446 dev_info(&adapter->pdev->dev,
1447 "Disabled pause frames successfully on all ports\n");
1448 qlcnic_83xx_unlock_driver(adapter);
1449}
1450
c0d79cd0
MC		 1451static void qlcnic_83xx_take_eport_out_of_reset(struct qlcnic_adapter *adapter)
1452{
1453 QLCWR32(adapter, QLC_83XX_RESET_REG, 0);
1454 QLCWR32(adapter, QLC_83XX_RESET_PORT0, 0);
1455 QLCWR32(adapter, QLC_83XX_RESET_PORT1, 0);
1456 QLCWR32(adapter, QLC_83XX_RESET_PORT2, 0);
1457 QLCWR32(adapter, QLC_83XX_RESET_PORT3, 0);
1458 QLCWR32(adapter, QLC_83XX_RESET_SRESHIM, 0);
1459 QLCWR32(adapter, QLC_83XX_RESET_EPGSHIM, 0);
1460 QLCWR32(adapter, QLC_83XX_RESET_ETHERPCS, 0);
1461 QLCWR32(adapter, QLC_83XX_RESET_CONTROL, 1);
1462}
1463
629263ac
SC		 1464static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev)
1465{
1466 u32 heartbeat, peg_status;
4bd8e738 1467 int retries, ret = -EIO, err = 0;
629263ac
SC		 1468
1469 retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT;
1470 p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev,
1471 QLCNIC_PEG_ALIVE_COUNTER);
1472
1473 do {
1474 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS);
1475 heartbeat = QLC_SHARED_REG_RD32(p_dev,
1476 QLCNIC_PEG_ALIVE_COUNTER);
1477 if (heartbeat != p_dev->heartbeat) {
1478 ret = QLCNIC_RCODE_SUCCESS;
1479 break;
1480 }
1481 } while (--retries);
1482
1483 if (ret) {
1484 dev_err(&p_dev->pdev->dev, "firmware hang detected\n");
c0d79cd0 1485 qlcnic_83xx_take_eport_out_of_reset(p_dev);
629263ac
SC		 1486 qlcnic_83xx_disable_pause_frames(p_dev);
1487 peg_status = QLC_SHARED_REG_RD32(p_dev,
1488 QLCNIC_PEG_HALT_STATUS1);
1489 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n"
1490 "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n"
1491 "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n"
1492 "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n"
1493 "PEG_NET_4_PC: 0x%x\n", peg_status,
1494 QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2),
4bd8e738
HM		 1495 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0, &err),
1496 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1, &err),
1497 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2, &err),
1498 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3, &err),
1499 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4, &err));
629263ac
SC		 1500
1501 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67)
1502 dev_err(&p_dev->pdev->dev,
1503 "Device is being reset err code 0x00006700.\n");
1504 }
1505
1506 return ret;
1507}
1508
1509static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev)
1510{
1511 int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT;
1512 u32 val;
1513
1514 do {
1515 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE);
1516 if (val == QLC_83XX_CMDPEG_COMPLETE)
1517 return 0;
1518 msleep(QLCNIC_CMDPEG_CHECK_DELAY);
1519 } while (--retries);
1520
1521 dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val);
1522 return -EIO;
1523}
1524
1525int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev)
1526{
1527 int err;
1528
1529 err = qlcnic_83xx_check_cmd_peg_status(p_dev);
1530 if (err)
1531 return err;
1532
1533 err = qlcnic_83xx_check_heartbeat(p_dev);
1534 if (err)
1535 return err;
1536
1537 return err;
1538}
1539
81d0aeb0
SC		 1540static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr,
1541 int duration, u32 mask, u32 status)
1542{
4bd8e738 1543 int timeout_error, err = 0;
81d0aeb0 1544 u32 value;
81d0aeb0
SC		 1545 u8 retries;
1546
4bd8e738
HM		 1547 value = QLCRD32(p_dev, addr, &err);
1548 if (err == -EIO)
1549 return err;
81d0aeb0
SC		 1550 retries = duration / 10;
1551
1552 do {
1553 if ((value & mask) != status) {
1554 timeout_error = 1;
1555 msleep(duration / 10);
4bd8e738
HM		 1556 value = QLCRD32(p_dev, addr, &err);
1557 if (err == -EIO)
1558 return err;
81d0aeb0
SC		 1559 } else {
1560 timeout_error = 0;
1561 break;
1562 }
1563 } while (retries--);
1564
1565 if (timeout_error) {
1566 p_dev->ahw->reset.seq_error++;
1567 dev_err(&p_dev->pdev->dev,
1568 "%s: Timeout Err, entry_num = %d\n",
1569 __func__, p_dev->ahw->reset.seq_index);
1570 dev_err(&p_dev->pdev->dev,
1571 "0x%08x 0x%08x 0x%08x\n",
1572 value, mask, status);
1573 }
1574
1575 return timeout_error;
1576}
1577
1578static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev)
1579{
1580 u32 sum = 0;
1581 u16 *buff = (u16 *)p_dev->ahw->reset.buff;
1582 int count = p_dev->ahw->reset.hdr->size / sizeof(u16);
1583
1584 while (count-- > 0)
1585 sum += *buff++;
1586
1587 while (sum >> 16)
1588 sum = (sum & 0xFFFF) + (sum >> 16);
1589
1590 if (~sum) {
1591 return 0;
1592 } else {
1593 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1594 return -1;
1595 }
1596}
1597
1598int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev)
1599{
81d0aeb0 1600 struct qlcnic_hardware_context *ahw = p_dev->ahw;
486a5bc7
RB		 1601 u32 addr, count, prev_ver, curr_ver;
1602 u8 *p_buff;
1603
1604 if (ahw->reset.buff != NULL) {
1605 prev_ver = p_dev->fw_version;
1606 curr_ver = qlcnic_83xx_get_fw_version(p_dev);
1607 if (curr_ver > prev_ver)
1608 kfree(ahw->reset.buff);
1609 else
1610 return 0;
1611 }
81d0aeb0
SC		 1612
1613 ahw->reset.seq_error = 0;
1614 ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL);
b2adaca9 1615 if (p_dev->ahw->reset.buff == NULL)
81d0aeb0 1616 return -ENOMEM;
b2adaca9 1617
81d0aeb0
SC		 1618 p_buff = p_dev->ahw->reset.buff;
1619 addr = QLC_83XX_RESET_TEMPLATE_ADDR;
1620 count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32);
1621
1622 /* Copy template header from flash */
1623 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1624 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1625 return -EIO;
1626 }
1627 ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff;
1628 addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size;
1629 p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1630 count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32);
1631
1632 /* Copy rest of the template */
1633 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1634 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1635 return -EIO;
1636 }
1637
1638 if (qlcnic_83xx_reset_template_checksum(p_dev))
1639 return -EIO;
1640 /* Get Stop, Start and Init command offsets */
1641 ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset;
1642 ahw->reset.start_offset = ahw->reset.buff +
1643 ahw->reset.hdr->start_offset;
1644 ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1645 return 0;
1646}
1647
1648/* Read Write HW register command */
1649static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev,
1650 u32 raddr, u32 waddr)
1651{
4bd8e738
HM		 1652 int err = 0;
1653 u32 value;
81d0aeb0 1654
4bd8e738
HM		 1655 value = QLCRD32(p_dev, raddr, &err);
1656 if (err == -EIO)
1657 return;
81d0aeb0
SC		 1658 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1659}
1660
1661/* Read Modify Write HW register command */
1662static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev,
1663 u32 raddr, u32 waddr,
1664 struct qlc_83xx_rmw *p_rmw_hdr)
1665{
4bd8e738
HM		 1666 int err = 0;
1667 u32 value;
81d0aeb0 1668
4bd8e738 1669 if (p_rmw_hdr->index_a) {
81d0aeb0 1670 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a];
4bd8e738
HM		 1671 } else {
1672 value = QLCRD32(p_dev, raddr, &err);
1673 if (err == -EIO)
1674 return;
1675 }
81d0aeb0
SC		 1676
1677 value &= p_rmw_hdr->mask;
1678 value <<= p_rmw_hdr->shl;
1679 value >>= p_rmw_hdr->shr;
1680 value |= p_rmw_hdr->or_value;
1681 value ^= p_rmw_hdr->xor_value;
1682 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1683}
1684
1685/* Write HW register command */
1686static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev,
1687 struct qlc_83xx_entry_hdr *p_hdr)
1688{
1689 int i;
1690 struct qlc_83xx_entry *entry;
1691
1692 entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1693 sizeof(struct qlc_83xx_entry_hdr));
1694
1695 for (i = 0; i < p_hdr->count; i++, entry++) {
1696 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1,
1697 entry->arg2);
1698 if (p_hdr->delay)
1699 udelay((u32)(p_hdr->delay));
1700 }
1701}
1702
1703/* Read and Write instruction */
1704static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev,
1705 struct qlc_83xx_entry_hdr *p_hdr)
1706{
1707 int i;
1708 struct qlc_83xx_entry *entry;
1709
1710 entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1711 sizeof(struct qlc_83xx_entry_hdr));
1712
1713 for (i = 0; i < p_hdr->count; i++, entry++) {
1714 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1,
1715 entry->arg2);
1716 if (p_hdr->delay)
1717 udelay((u32)(p_hdr->delay));
1718 }
1719}
1720
1721/* Poll HW register command */
1722static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev,
1723 struct qlc_83xx_entry_hdr *p_hdr)
1724{
1725 long delay;
1726 struct qlc_83xx_entry *entry;
1727 struct qlc_83xx_poll *poll;
4bd8e738 1728 int i, err = 0;
81d0aeb0
SC		 1729 unsigned long arg1, arg2;
1730
1731 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1732 sizeof(struct qlc_83xx_entry_hdr));
1733
1734 entry = (struct qlc_83xx_entry *)((char *)poll +
1735 sizeof(struct qlc_83xx_poll));
1736 delay = (long)p_hdr->delay;
1737
1738 if (!delay) {
1739 for (i = 0; i < p_hdr->count; i++, entry++)
1740 qlcnic_83xx_poll_reg(p_dev, entry->arg1,
1741 delay, poll->mask,
1742 poll->status);
1743 } else {
1744 for (i = 0; i < p_hdr->count; i++, entry++) {
1745 arg1 = entry->arg1;
1746 arg2 = entry->arg2;
1747 if (delay) {
1748 if (qlcnic_83xx_poll_reg(p_dev,
1749 arg1, delay,
1750 poll->mask,
1751 poll->status)){
4bd8e738
HM		 1752 QLCRD32(p_dev, arg1, &err);
1753 if (err == -EIO)
1754 return;
1755 QLCRD32(p_dev, arg2, &err);
1756 if (err == -EIO)
1757 return;
81d0aeb0
SC		 1758 }
1759 }
1760 }
1761 }
1762}
1763
1764/* Poll and write HW register command */
1765static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev,
1766 struct qlc_83xx_entry_hdr *p_hdr)
1767{
1768 int i;
1769 long delay;
1770 struct qlc_83xx_quad_entry *entry;
1771 struct qlc_83xx_poll *poll;
1772
1773 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1774 sizeof(struct qlc_83xx_entry_hdr));
1775 entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1776 sizeof(struct qlc_83xx_poll));
1777 delay = (long)p_hdr->delay;
1778
1779 for (i = 0; i < p_hdr->count; i++, entry++) {
1780 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr,
1781 entry->dr_value);
1782 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1783 entry->ar_value);
1784 if (delay)
1785 qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1786 poll->mask, poll->status);
1787 }
1788}
1789
1790/* Read Modify Write register command */
1791static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev,
1792 struct qlc_83xx_entry_hdr *p_hdr)
1793{
1794 int i;
1795 struct qlc_83xx_entry *entry;
1796 struct qlc_83xx_rmw *rmw_hdr;
1797
1798 rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr +
1799 sizeof(struct qlc_83xx_entry_hdr));
1800
1801 entry = (struct qlc_83xx_entry *)((char *)rmw_hdr +
1802 sizeof(struct qlc_83xx_rmw));
1803
1804 for (i = 0; i < p_hdr->count; i++, entry++) {
1805 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1,
1806 entry->arg2, rmw_hdr);
1807 if (p_hdr->delay)
1808 udelay((u32)(p_hdr->delay));
1809 }
1810}
1811
1812static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr)
1813{
1814 if (p_hdr->delay)
1815 mdelay((u32)((long)p_hdr->delay));
1816}
1817
1818/* Read and poll register command */
1819static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev,
1820 struct qlc_83xx_entry_hdr *p_hdr)
1821{
1822 long delay;
4bd8e738 1823 int index, i, j, err;
81d0aeb0
SC		 1824 struct qlc_83xx_quad_entry *entry;
1825 struct qlc_83xx_poll *poll;
1826 unsigned long addr;
1827
1828 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1829 sizeof(struct qlc_83xx_entry_hdr));
1830
1831 entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1832 sizeof(struct qlc_83xx_poll));
1833 delay = (long)p_hdr->delay;
1834
1835 for (i = 0; i < p_hdr->count; i++, entry++) {
1836 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1837 entry->ar_value);
1838 if (delay) {
1839 if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1840 poll->mask, poll->status)){
1841 index = p_dev->ahw->reset.array_index;
1842 addr = entry->dr_addr;
4bd8e738
HM		 1843 j = QLCRD32(p_dev, addr, &err);
1844 if (err == -EIO)
1845 return;
1846
81d0aeb0
SC		 1847 p_dev->ahw->reset.array[index++] = j;
1848
1849 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES)
1850 p_dev->ahw->reset.array_index = 1;
1851 }
1852 }
1853 }
1854}
1855
1856static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev)
1857{
1858 p_dev->ahw->reset.seq_end = 1;
1859}
1860
1861static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev)
1862{
1863 p_dev->ahw->reset.template_end = 1;
1864 if (p_dev->ahw->reset.seq_error == 0)
1865 dev_err(&p_dev->pdev->dev,
1866 "HW restart process completed successfully.\n");
1867 else
1868 dev_err(&p_dev->pdev->dev,
1869 "HW restart completed with timeout errors.\n");
1870}
1871
1872/**
1873* qlcnic_83xx_exec_template_cmd
1874*
1875* @p_dev: adapter structure
1876* @p_buff: Poiter to instruction template
1877*
1878* Template provides instructions to stop, restart and initalize firmware.
1879* These instructions are abstracted as a series of read, write and
1880* poll operations on hardware registers. Register information and operation
1881* specifics are not exposed to the driver. Driver reads the template from
1882* flash and executes the instructions located at pre-defined offsets.
1883*
1884* Returns: None
1885* */
1886static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev,
1887 char *p_buff)
1888{
1889 int index, entries;
1890 struct qlc_83xx_entry_hdr *p_hdr;
1891 char *entry = p_buff;
1892
1893 p_dev->ahw->reset.seq_end = 0;
1894 p_dev->ahw->reset.template_end = 0;
1895 entries = p_dev->ahw->reset.hdr->entries;
1896 index = p_dev->ahw->reset.seq_index;
1897
1898 for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) {
1899 p_hdr = (struct qlc_83xx_entry_hdr *)entry;
1900
1901 switch (p_hdr->cmd) {
1902 case QLC_83XX_OPCODE_NOP:
1903 break;
1904 case QLC_83XX_OPCODE_WRITE_LIST:
1905 qlcnic_83xx_write_list(p_dev, p_hdr);
1906 break;
1907 case QLC_83XX_OPCODE_READ_WRITE_LIST:
1908 qlcnic_83xx_read_write_list(p_dev, p_hdr);
1909 break;
1910 case QLC_83XX_OPCODE_POLL_LIST:
1911 qlcnic_83xx_poll_list(p_dev, p_hdr);
1912 break;
1913 case QLC_83XX_OPCODE_POLL_WRITE_LIST:
1914 qlcnic_83xx_poll_write_list(p_dev, p_hdr);
1915 break;
1916 case QLC_83XX_OPCODE_READ_MODIFY_WRITE:
1917 qlcnic_83xx_read_modify_write(p_dev, p_hdr);
1918 break;
1919 case QLC_83XX_OPCODE_SEQ_PAUSE:
1920 qlcnic_83xx_pause(p_hdr);
1921 break;
1922 case QLC_83XX_OPCODE_SEQ_END:
1923 qlcnic_83xx_seq_end(p_dev);
1924 break;
1925 case QLC_83XX_OPCODE_TMPL_END:
1926 qlcnic_83xx_template_end(p_dev);
1927 break;
1928 case QLC_83XX_OPCODE_POLL_READ_LIST:
1929 qlcnic_83xx_poll_read_list(p_dev, p_hdr);
1930 break;
1931 default:
1932 dev_err(&p_dev->pdev->dev,
1933 "%s: Unknown opcode 0x%04x in template %d\n",
1934 __func__, p_hdr->cmd, index);
1935 break;
1936 }
1937 entry += p_hdr->size;
1938 }
1939 p_dev->ahw->reset.seq_index = index;
1940}
1941
1942static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev)
1943{
1944 p_dev->ahw->reset.seq_index = 0;
1945
1946 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset);
1947 if (p_dev->ahw->reset.seq_end != 1)
1948 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1949}
1950
1951static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev)
1952{
1953 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset);
1954 if (p_dev->ahw->reset.template_end != 1)
1955 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1956}
1957
1958static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev)
1959{
1960 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset);
1961 if (p_dev->ahw->reset.seq_end != 1)
1962 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1963}
1964
629263ac
SC		 1965static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter)
1966{
7000078a 1967 struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info;
629263ac
SC		 1968 int err = -EIO;
1969
7000078a 1970 if (request_firmware(&fw_info->fw, fw_info->fw_file_name,
fef349ce 1971 &(adapter->pdev->dev))) {
629263ac
SC		 1972 dev_err(&adapter->pdev->dev,
1973 "No file FW image, loading flash FW image.\n");
1974 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1975 QLC_83XX_BOOT_FROM_FLASH);
1976 } else {
1977 if (qlcnic_83xx_copy_fw_file(adapter))
1978 return err;
1979 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1980 QLC_83XX_BOOT_FROM_FILE);
1981 }
1982
1983 return 0;
1984}
1985
1986static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter)
1987{
4e60ac46 1988 u32 val;
629263ac
SC		 1989 int err = -EIO;
1990
81d0aeb0 1991 qlcnic_83xx_stop_hw(adapter);
4e60ac46
SC		 1992
1993 /* Collect FW register dump if required */
1994 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1995 if (!(val & QLC_83XX_IDC_GRACEFULL_RESET))
1996 qlcnic_dump_fw(adapter);
81d0aeb0
SC		 1997 qlcnic_83xx_init_hw(adapter);
1998
629263ac
SC		 1999 if (qlcnic_83xx_copy_bootloader(adapter))
2000 return err;
2001 /* Boot either flash image or firmware image from host file system */
2002 if (qlcnic_load_fw_file) {
2003 if (qlcnic_83xx_load_fw_image_from_host(adapter))
2004 return err;
2005 } else {
2006 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
2007 QLC_83XX_BOOT_FROM_FLASH);
2008 }
2009
81d0aeb0 2010 qlcnic_83xx_start_hw(adapter);
629263ac
SC		 2011 if (qlcnic_83xx_check_hw_status(adapter))
2012 return -EIO;
2013
2014 return 0;
2015}
2016
629263ac
SC		 2017int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter)
2018{
2019 int err;
2020 struct qlcnic_info nic_info;
2021 struct qlcnic_hardware_context *ahw = adapter->ahw;
2022
2023 memset(&nic_info, 0, sizeof(struct qlcnic_info));
2024 err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
2025 if (err)
2026 return -EIO;
2027
2028 ahw->physical_port = (u8) nic_info.phys_port;
2029 ahw->switch_mode = nic_info.switch_mode;
2030 ahw->max_tx_ques = nic_info.max_tx_ques;
2031 ahw->max_rx_ques = nic_info.max_rx_ques;
2032 ahw->capabilities = nic_info.capabilities;
2033 ahw->max_mac_filters = nic_info.max_mac_filters;
2034 ahw->max_mtu = nic_info.max_mtu;
2035
34e8c406
HM		 2036 adapter->max_tx_rings = ahw->max_tx_ques;
2037 adapter->max_sds_rings = ahw->max_rx_ques;
35dafcb0
SC		 2038 /* eSwitch capability indicates vNIC mode.
2039 * vNIC and SRIOV are mutually exclusive operational modes.
2040 * If SR-IOV capability is detected, SR-IOV physical function
2041 * will get initialized in default mode.
2042 * SR-IOV virtual function initialization follows a
2043 * different code path and opmode.
2044 * SRIOV mode has precedence over vNIC mode.
02feda17 2045 */
35dafcb0
SC		 2046 if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state))
2047 return QLC_83XX_DEFAULT_OPMODE;
02feda17 2048
35dafcb0 2049 if (ahw->capabilities & QLC_83XX_ESWITCH_CAPABILITY)
34e8c406 2050 return QLCNIC_VNIC_MODE;
629263ac 2051
35dafcb0 2052 return QLC_83XX_DEFAULT_OPMODE;
629263ac
SC		 2053}
2054
02feda17 2055int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter)
629263ac 2056{
35dafcb0 2057 struct qlcnic_hardware_context *ahw = adapter->ahw;
629263ac
SC		 2058 int ret;
2059
2060 ret = qlcnic_83xx_get_nic_configuration(adapter);
2061 if (ret == -EIO)
2062 return -EIO;
2063
34e8c406
HM		 2064 if (ret == QLCNIC_VNIC_MODE) {
2065 ahw->nic_mode = QLCNIC_VNIC_MODE;
2066
d71170fb
SC		 2067 if (qlcnic_83xx_config_vnic_opmode(adapter))
2068 return -EIO;
35dafcb0 2069
34e8c406 2070 adapter->max_sds_rings = QLCNIC_MAX_VNIC_SDS_RINGS;
18afc102 2071 adapter->max_tx_rings = QLCNIC_MAX_VNIC_TX_RINGS;
35dafcb0 2072 } else if (ret == QLC_83XX_DEFAULT_OPMODE) {
34e8c406 2073 ahw->nic_mode = QLCNIC_DEFAULT_MODE;
35dafcb0
SC		 2074 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver;
2075 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry;
f9566265
HM		 2076 adapter->max_sds_rings = QLCNIC_MAX_SDS_RINGS;
2077 adapter->max_tx_rings = QLCNIC_MAX_TX_RINGS;
35dafcb0
SC		 2078 } else {
2079 return -EIO;
629263ac
SC		 2080 }
2081
2082 return 0;
2083}
2084
2085static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter)
2086{
2087 struct qlcnic_hardware_context *ahw = adapter->ahw;
2088
2089 if (ahw->port_type == QLCNIC_XGBE) {
2090 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G;
2091 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
2092 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2093 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2094
2095 } else if (ahw->port_type == QLCNIC_GBE) {
2096 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G;
2097 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2098 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2099 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G;
2100 }
2101 adapter->num_txd = MAX_CMD_DESCRIPTORS;
2102 adapter->max_rds_rings = MAX_RDS_RINGS;
2103}
2104
2105static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter)
2106{
2107 int err = -EIO;
2108
4e60ac46 2109 qlcnic_83xx_get_minidump_template(adapter);
629263ac
SC		 2110 if (qlcnic_83xx_get_port_info(adapter))
2111 return err;
2112
2113 qlcnic_83xx_config_buff_descriptors(adapter);
2114 adapter->ahw->msix_supported = !!qlcnic_use_msi_x;
2115 adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
2116
2117 dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
2118 adapter->ahw->fw_hal_version);
2119
2120 return 0;
2121}
2122
2123#define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1))
2124static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter)
2125{
2126 struct qlcnic_cmd_args cmd;
2127 u32 presence_mask, audit_mask;
2128 int status;
2129
2130 presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
2131 audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
2132
2133 if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) {
b6b4316c
SS		 2134 status = qlcnic_alloc_mbx_args(&cmd, adapter,
2135 QLCNIC_CMD_STOP_NIC_FUNC);
2136 if (status)
2137 return;
2138
629263ac
SC		 2139 cmd.req.arg[1] = BIT_31;
2140 status = qlcnic_issue_cmd(adapter, &cmd);
2141 if (status)
2142 dev_err(&adapter->pdev->dev,
2143 "Failed to clean up the function resources\n");
2144 qlcnic_free_mbx_args(&cmd);
2145 }
2146}
2147
7000078a
PP		 2148static int qlcnic_83xx_get_fw_info(struct qlcnic_adapter *adapter)
2149{
2150 struct qlcnic_hardware_context *ahw = adapter->ahw;
2151 struct pci_dev *pdev = adapter->pdev;
2152 struct qlc_83xx_fw_info *fw_info;
2153 int err = 0;
2154
2155 ahw->fw_info = kzalloc(sizeof(*fw_info), GFP_KERNEL);
2156 if (!ahw->fw_info) {
2157 err = -ENOMEM;
2158 } else {
2159 fw_info = ahw->fw_info;
2160 switch (pdev->device) {
2161 case PCI_DEVICE_ID_QLOGIC_QLE834X:
2162 strncpy(fw_info->fw_file_name, QLC_83XX_FW_FILE_NAME,
2163 QLC_FW_FILE_NAME_LEN);
2164 break;
2165 case PCI_DEVICE_ID_QLOGIC_QLE844X:
2166 strncpy(fw_info->fw_file_name, QLC_84XX_FW_FILE_NAME,
2167 QLC_FW_FILE_NAME_LEN);
2168 break;
2169 default:
2170 dev_err(&pdev->dev, "%s: Invalid device id\n",
2171 __func__);
2172 err = -EINVAL;
2173 break;
2174 }
2175 }
2176
2177 return err;
2178}
2179
34e8c406
HM		 2180static void qlcnic_83xx_init_rings(struct qlcnic_adapter *adapter)
2181{
18afc102
HM		 2182 u8 rx_cnt = QLCNIC_DEF_SDS_RINGS;
2183 u8 tx_cnt = QLCNIC_DEF_TX_RINGS;
2184
34e8c406
HM		 2185 adapter->max_tx_rings = QLCNIC_MAX_TX_RINGS;
2186 adapter->max_sds_rings = QLCNIC_MAX_SDS_RINGS;
2187
18afc102
HM		 2188 if (!adapter->ahw->msix_supported) {
2189 rx_cnt = QLCNIC_SINGLE_RING;
2190 tx_cnt = QLCNIC_SINGLE_RING;
2191 }
34e8c406
HM		 2192
2193 /* compute and set drv sds rings */
18afc102
HM		 2194 qlcnic_set_tx_ring_count(adapter, tx_cnt);
2195 qlcnic_set_sds_ring_count(adapter, rx_cnt);
34e8c406 2196}
7000078a 2197
f8468331 2198int qlcnic_83xx_init(struct qlcnic_adapter *adapter, int pci_using_dac)
629263ac
SC		 2199{
2200 struct qlcnic_hardware_context *ahw = adapter->ahw;
1de899d3 2201 struct qlcnic_dcb *dcb;
068a8d19 2202 int err = 0;
629263ac 2203
068a8d19 2204 ahw->msix_supported = !!qlcnic_use_msi_x;
34e8c406
HM		 2205
2206 qlcnic_83xx_init_rings(adapter);
2207
068a8d19
MC		 2208 err = qlcnic_83xx_init_mailbox_work(adapter);
2209 if (err)
2210 goto exit;
f8468331 2211
068a8d19
MC		 2212 if (qlcnic_sriov_vf_check(adapter)) {
2213 err = qlcnic_sriov_vf_init(adapter, pci_using_dac);
2214 if (err)
2215 goto detach_mbx;
2216 else
2217 return err;
2218 }
629263ac 2219
78ea2d97
SC		 2220 if (qlcnic_83xx_read_flash_descriptor_table(adapter) ||
2221 qlcnic_83xx_read_flash_mfg_id(adapter)) {
2222 dev_err(&adapter->pdev->dev, "Failed reading flash mfg id\n");
2223 err = -ENOTRECOVERABLE;
2224 goto detach_mbx;
2225 }
2226
068a8d19
MC		 2227 err = qlcnic_83xx_check_hw_status(adapter);
2228 if (err)
2229 goto detach_mbx;
2230
7000078a 2231 err = qlcnic_83xx_get_fw_info(adapter);
b5acb255
MC		 2232 if (err)
2233 goto detach_mbx;
2234
7000078a
PP		 2235 err = qlcnic_83xx_idc_init(adapter);
2236 if (err)
78ea2d97 2237 goto detach_mbx;
7000078a 2238
34e8c406 2239 err = qlcnic_setup_intr(adapter);
068a8d19
MC		 2240 if (err) {
2241 dev_err(&adapter->pdev->dev, "Failed to setup interrupt\n");
2242 goto disable_intr;
2243 }
2244
2245 err = qlcnic_83xx_setup_mbx_intr(adapter);
2246 if (err)
2247 goto disable_mbx_intr;
629263ac 2248
629263ac
SC		 2249 qlcnic_83xx_clear_function_resources(adapter);
2250
c70a3175
JK		 2251 INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
2252
d5fcff04
HM		 2253 /* register for NIC IDC AEN Events */
2254 qlcnic_83xx_register_nic_idc_func(adapter, 1);
2255
629263ac 2256 /* Configure default, SR-IOV or Virtual NIC mode of operation */
068a8d19
MC		 2257 err = qlcnic_83xx_configure_opmode(adapter);
2258 if (err)
2259 goto disable_mbx_intr;
629263ac 2260
34e8c406 2261
629263ac 2262 /* Perform operating mode specific initialization */
068a8d19
MC		 2263 err = adapter->nic_ops->init_driver(adapter);
2264 if (err)
2265 goto disable_mbx_intr;
629263ac 2266
1de899d3
SC		 2267 dcb = adapter->dcb;
2268
2269 if (dcb && qlcnic_dcb_attach(dcb))
2270 qlcnic_clear_dcb_ops(dcb);
14d385b9 2271
629263ac
SC		 2272 /* Periodically monitor device status */
2273 qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work);
068a8d19 2274 return 0;
629263ac 2275
068a8d19
MC		 2276disable_mbx_intr:
2277 qlcnic_83xx_free_mbx_intr(adapter);
2278
2279disable_intr:
2280 qlcnic_teardown_intr(adapter);
2281
2282detach_mbx:
2283 qlcnic_83xx_detach_mailbox_work(adapter);
2284 qlcnic_83xx_free_mailbox(ahw->mailbox);
78ea2d97 2285 ahw->mailbox = NULL;
068a8d19
MC		 2286exit:
2287 return err;
629263ac 2288}
9ce226fa
PP		 2289
2290void qlcnic_83xx_aer_stop_poll_work(struct qlcnic_adapter *adapter)
2291{
2292 struct qlcnic_hardware_context *ahw = adapter->ahw;
2293 struct qlc_83xx_idc *idc = &ahw->idc;
2294
2295 clear_bit(QLC_83XX_MBX_READY, &idc->status);
2296 cancel_delayed_work_sync(&adapter->fw_work);
2297
34e8c406 2298 if (ahw->nic_mode == QLCNIC_VNIC_MODE)
9ce226fa
PP		 2299 qlcnic_83xx_disable_vnic_mode(adapter, 1);
2300
2301 qlcnic_83xx_idc_detach_driver(adapter);
2302 qlcnic_83xx_register_nic_idc_func(adapter, 0);
2303
2304 cancel_delayed_work_sync(&adapter->idc_aen_work);
2305}
2306
2307int qlcnic_83xx_aer_reset(struct qlcnic_adapter *adapter)
2308{
2309 struct qlcnic_hardware_context *ahw = adapter->ahw;
2310 struct qlc_83xx_idc *idc = &ahw->idc;
2311 int ret = 0;
2312 u32 owner;
2313
2314 /* Mark the previous IDC state as NEED_RESET so
2315 * that state_entry() will perform the reattachment
2316 * and bringup the device
2317 */
2318 idc->prev_state = QLC_83XX_IDC_DEV_NEED_RESET;
2319 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
2320 if (ahw->pci_func == owner) {
2321 ret = qlcnic_83xx_restart_hw(adapter);
2322 if (ret < 0)
2323 return ret;
2324 qlcnic_83xx_idc_clear_registers(adapter, 0);
2325 }
2326
2327 ret = idc->state_entry(adapter);
2328 return ret;
2329}
2330
2331void qlcnic_83xx_aer_start_poll_work(struct qlcnic_adapter *adapter)
2332{
2333 struct qlcnic_hardware_context *ahw = adapter->ahw;
2334 struct qlc_83xx_idc *idc = &ahw->idc;
2335 u32 owner;
2336
2337 idc->prev_state = QLC_83XX_IDC_DEV_READY;
2338 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
2339 if (ahw->pci_func == owner)
2340 qlcnic_83xx_idc_enter_ready_state(adapter, 0);
2341
2342 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state, 0);
2343}
Linux 6.x block layer and io_uring tree(s)