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qlcnic: Fix link speed and duplex display for 83xx adapter
[linux-2.6-block.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic_83xx_init.c
CommitLineData
577ae39d
JK		 1/*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
f8468331 8#include "qlcnic_sriov.h"
629263ac
SC		 9#include "qlcnic.h"
10#include "qlcnic_hw.h"
11
81d0aeb0
SC		 12/* Reset template definitions */
13#define QLC_83XX_RESTART_TEMPLATE_SIZE 0x2000
14#define QLC_83XX_RESET_TEMPLATE_ADDR 0x4F0000
15#define QLC_83XX_RESET_SEQ_VERSION 0x0101
16
17#define QLC_83XX_OPCODE_NOP 0x0000
18#define QLC_83XX_OPCODE_WRITE_LIST 0x0001
19#define QLC_83XX_OPCODE_READ_WRITE_LIST 0x0002
20#define QLC_83XX_OPCODE_POLL_LIST 0x0004
21#define QLC_83XX_OPCODE_POLL_WRITE_LIST 0x0008
22#define QLC_83XX_OPCODE_READ_MODIFY_WRITE 0x0010
23#define QLC_83XX_OPCODE_SEQ_PAUSE 0x0020
24#define QLC_83XX_OPCODE_SEQ_END 0x0040
25#define QLC_83XX_OPCODE_TMPL_END 0x0080
26#define QLC_83XX_OPCODE_POLL_READ_LIST 0x0100
27
c0d79cd0
MC		 28/* EPORT control registers */
29#define QLC_83XX_RESET_CONTROL 0x28084E50
30#define QLC_83XX_RESET_REG 0x28084E60
31#define QLC_83XX_RESET_PORT0 0x28084E70
32#define QLC_83XX_RESET_PORT1 0x28084E80
33#define QLC_83XX_RESET_PORT2 0x28084E90
34#define QLC_83XX_RESET_PORT3 0x28084EA0
35#define QLC_83XX_RESET_SRESHIM 0x28084EB0
36#define QLC_83XX_RESET_EPGSHIM 0x28084EC0
37#define QLC_83XX_RESET_ETHERPCS 0x28084ED0
38
629263ac 39static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter);
629263ac
SC		 40static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev);
41static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter);
42
81d0aeb0
SC		 43/* Template header */
44struct qlc_83xx_reset_hdr {
a96227e6 45#if defined(__LITTLE_ENDIAN)
81d0aeb0
SC		 46 u16 version;
47 u16 signature;
48 u16 size;
49 u16 entries;
50 u16 hdr_size;
51 u16 checksum;
52 u16 init_offset;
53 u16 start_offset;
a96227e6
SS		 54#elif defined(__BIG_ENDIAN)
55 u16 signature;
56 u16 version;
57 u16 entries;
58 u16 size;
59 u16 checksum;
60 u16 hdr_size;
61 u16 start_offset;
62 u16 init_offset;
63#endif
81d0aeb0
SC		 64} __packed;
65
66/* Command entry header. */
67struct qlc_83xx_entry_hdr {
a96227e6
SS		 68#if defined(__LITTLE_ENDIAN)
69 u16 cmd;
70 u16 size;
71 u16 count;
72 u16 delay;
73#elif defined(__BIG_ENDIAN)
74 u16 size;
75 u16 cmd;
76 u16 delay;
77 u16 count;
78#endif
81d0aeb0
SC		 79} __packed;
80
81/* Generic poll command */
82struct qlc_83xx_poll {
83 u32 mask;
84 u32 status;
85} __packed;
86
87/* Read modify write command */
88struct qlc_83xx_rmw {
89 u32 mask;
90 u32 xor_value;
91 u32 or_value;
a96227e6 92#if defined(__LITTLE_ENDIAN)
81d0aeb0
SC		 93 u8 shl;
94 u8 shr;
95 u8 index_a;
96 u8 rsvd;
a96227e6
SS		 97#elif defined(__BIG_ENDIAN)
98 u8 rsvd;
99 u8 index_a;
100 u8 shr;
101 u8 shl;
102#endif
81d0aeb0
SC		 103} __packed;
104
105/* Generic command with 2 DWORD */
106struct qlc_83xx_entry {
107 u32 arg1;
108 u32 arg2;
109} __packed;
110
111/* Generic command with 4 DWORD */
112struct qlc_83xx_quad_entry {
113 u32 dr_addr;
114 u32 dr_value;
115 u32 ar_addr;
116 u32 ar_value;
117} __packed;
629263ac
SC		 118static const char *const qlc_83xx_idc_states[] = {
119 "Unknown",
120 "Cold",
121 "Init",
122 "Ready",
123 "Need Reset",
124 "Need Quiesce",
125 "Failed",
126 "Quiesce"
127};
128
629263ac
SC		 129static int
130qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter)
131{
132 u32 val;
133
134 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
135 if ((val & 0xFFFF))
136 return 1;
137 else
138 return 0;
139}
140
141static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter)
142{
143 u32 cur, prev;
144 cur = adapter->ahw->idc.curr_state;
145 prev = adapter->ahw->idc.prev_state;
146
147 dev_info(&adapter->pdev->dev,
148 "current state = %s, prev state = %s\n",
149 adapter->ahw->idc.name[cur],
150 adapter->ahw->idc.name[prev]);
151}
152
153static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter,
154 u8 mode, int lock)
155{
156 u32 val;
157 int seconds;
158
159 if (lock) {
160 if (qlcnic_83xx_lock_driver(adapter))
161 return -EBUSY;
162 }
163
f036e4f4
RB		 164 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
165 val |= (adapter->portnum & 0xf);
629263ac
SC		 166 val |= mode << 7;
167 if (mode)
168 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
169 else
170 seconds = jiffies / HZ;
171
172 val |= seconds << 8;
173 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val);
174 adapter->ahw->idc.sec_counter = jiffies / HZ;
175
176 if (lock)
177 qlcnic_83xx_unlock_driver(adapter);
178
179 return 0;
180}
181
182static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter)
183{
184 u32 val;
185
186 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION);
187 val = val & ~(0x3 << (adapter->portnum * 2));
188 val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2));
189 QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val);
190}
191
192static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter,
193 int lock)
194{
195 u32 val;
196
197 if (lock) {
198 if (qlcnic_83xx_lock_driver(adapter))
199 return -EBUSY;
200 }
201
202 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
203 val = val & ~0xFF;
204 val = val | QLC_83XX_IDC_MAJOR_VERSION;
205 QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val);
206
207 if (lock)
208 qlcnic_83xx_unlock_driver(adapter);
209
210 return 0;
211}
212
213static int
214qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter,
215 int status, int lock)
216{
217 u32 val;
218
219 if (lock) {
220 if (qlcnic_83xx_lock_driver(adapter))
221 return -EBUSY;
222 }
223
224 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
225
226 if (status)
227 val = val | (1 << adapter->portnum);
228 else
229 val = val & ~(1 << adapter->portnum);
230
231 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
232 qlcnic_83xx_idc_update_minor_version(adapter);
233
234 if (lock)
235 qlcnic_83xx_unlock_driver(adapter);
236
237 return 0;
238}
239
240static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter)
241{
242 u32 val;
243 u8 version;
244
245 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
246 version = val & 0xFF;
247
248 if (version != QLC_83XX_IDC_MAJOR_VERSION) {
249 dev_info(&adapter->pdev->dev,
250 "%s:mismatch. version 0x%x, expected version 0x%x\n",
251 __func__, version, QLC_83XX_IDC_MAJOR_VERSION);
252 return -EIO;
253 }
254
255 return 0;
256}
257
258static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter,
259 int lock)
260{
261 u32 val;
262
263 if (lock) {
264 if (qlcnic_83xx_lock_driver(adapter))
265 return -EBUSY;
266 }
267
268 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0);
269 /* Clear gracefull reset bit */
270 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
271 val &= ~QLC_83XX_IDC_GRACEFULL_RESET;
272 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
273
274 if (lock)
275 qlcnic_83xx_unlock_driver(adapter);
276
277 return 0;
278}
279
280static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter,
281 int flag, int lock)
282{
283 u32 val;
284
285 if (lock) {
286 if (qlcnic_83xx_lock_driver(adapter))
287 return -EBUSY;
288 }
289
290 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
291 if (flag)
292 val = val | (1 << adapter->portnum);
293 else
294 val = val & ~(1 << adapter->portnum);
295 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val);
296
297 if (lock)
298 qlcnic_83xx_unlock_driver(adapter);
299
300 return 0;
301}
302
303static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter,
304 int time_limit)
305{
306 u64 seconds;
307
308 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
309 if (seconds <= time_limit)
310 return 0;
311 else
312 return -EBUSY;
313}
314
315/**
316 * qlcnic_83xx_idc_check_reset_ack_reg
317 *
318 * @adapter: adapter structure
319 *
320 * Check ACK wait limit and clear the functions which failed to ACK
321 *
322 * Return 0 if all functions have acknowledged the reset request.
323 **/
324static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter)
325{
326 int timeout;
327 u32 ack, presence, val;
328
329 timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
330 ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
331 presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
332 dev_info(&adapter->pdev->dev,
333 "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence);
334 if (!((ack & presence) == presence)) {
335 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) {
336 /* Clear functions which failed to ACK */
337 dev_info(&adapter->pdev->dev,
338 "%s: ACK wait exceeds time limit\n", __func__);
339 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
340 val = val & ~(ack ^ presence);
341 if (qlcnic_83xx_lock_driver(adapter))
342 return -EBUSY;
343 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
344 dev_info(&adapter->pdev->dev,
345 "%s: updated drv presence reg = 0x%x\n",
346 __func__, val);
347 qlcnic_83xx_unlock_driver(adapter);
348 return 0;
349
350 } else {
351 return 1;
352 }
353 } else {
354 dev_info(&adapter->pdev->dev,
355 "%s: Reset ACK received from all functions\n",
356 __func__);
357 return 0;
358 }
359}
360
361/**
362 * qlcnic_83xx_idc_tx_soft_reset
363 *
364 * @adapter: adapter structure
365 *
366 * Handle context deletion and recreation request from transmit routine
367 *
368 * Returns -EBUSY or Success (0)
369 *
370 **/
371static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter)
372{
373 struct net_device *netdev = adapter->netdev;
374
375 if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
376 return -EBUSY;
377
378 netif_device_detach(netdev);
379 qlcnic_down(adapter, netdev);
380 qlcnic_up(adapter, netdev);
381 netif_device_attach(netdev);
382 clear_bit(__QLCNIC_RESETTING, &adapter->state);
383 dev_err(&adapter->pdev->dev, "%s:\n", __func__);
384
629263ac
SC		 385 return 0;
386}
387
388/**
389 * qlcnic_83xx_idc_detach_driver
390 *
391 * @adapter: adapter structure
392 * Detach net interface, stop TX and cleanup resources before the HW reset.
393 * Returns: None
394 *
395 **/
396static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter)
397{
398 int i;
399 struct net_device *netdev = adapter->netdev;
400
401 netif_device_detach(netdev);
f036e4f4 402
629263ac 403 /* Disable mailbox interrupt */
f036e4f4 404 qlcnic_83xx_disable_mbx_intr(adapter);
629263ac
SC		 405 qlcnic_down(adapter, netdev);
406 for (i = 0; i < adapter->ahw->num_msix; i++) {
407 adapter->ahw->intr_tbl[i].id = i;
408 adapter->ahw->intr_tbl[i].enabled = 0;
409 adapter->ahw->intr_tbl[i].src = 0;
410 }
f036e4f4
RB		 411
412 if (qlcnic_sriov_pf_check(adapter))
413 qlcnic_sriov_pf_reset(adapter);
629263ac
SC		 414}
415
416/**
417 * qlcnic_83xx_idc_attach_driver
418 *
419 * @adapter: adapter structure
420 *
421 * Re-attach and re-enable net interface
422 * Returns: None
423 *
424 **/
425static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter)
426{
427 struct net_device *netdev = adapter->netdev;
428
429 if (netif_running(netdev)) {
430 if (qlcnic_up(adapter, netdev))
431 goto done;
432 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
433 }
434done:
435 netif_device_attach(netdev);
629263ac
SC		 436}
437
438static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter,
439 int lock)
440{
441 if (lock) {
442 if (qlcnic_83xx_lock_driver(adapter))
443 return -EBUSY;
444 }
445
446 qlcnic_83xx_idc_clear_registers(adapter, 0);
447 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED);
448 if (lock)
449 qlcnic_83xx_unlock_driver(adapter);
450
451 qlcnic_83xx_idc_log_state_history(adapter);
452 dev_info(&adapter->pdev->dev, "Device will enter failed state\n");
453
454 return 0;
455}
456
457static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter,
458 int lock)
459{
460 if (lock) {
461 if (qlcnic_83xx_lock_driver(adapter))
462 return -EBUSY;
463 }
464
465 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT);
466
467 if (lock)
468 qlcnic_83xx_unlock_driver(adapter);
469
470 return 0;
471}
472
473static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter,
474 int lock)
475{
476 if (lock) {
477 if (qlcnic_83xx_lock_driver(adapter))
478 return -EBUSY;
479 }
480
481 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
482 QLC_83XX_IDC_DEV_NEED_QUISCENT);
483
484 if (lock)
485 qlcnic_83xx_unlock_driver(adapter);
486
487 return 0;
488}
489
490static int
491qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock)
492{
493 if (lock) {
494 if (qlcnic_83xx_lock_driver(adapter))
495 return -EBUSY;
496 }
497
498 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
499 QLC_83XX_IDC_DEV_NEED_RESET);
500
501 if (lock)
502 qlcnic_83xx_unlock_driver(adapter);
503
504 return 0;
505}
506
507static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter,
508 int lock)
509{
510 if (lock) {
511 if (qlcnic_83xx_lock_driver(adapter))
512 return -EBUSY;
513 }
514
515 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY);
516 if (lock)
517 qlcnic_83xx_unlock_driver(adapter);
518
519 return 0;
520}
521
522/**
523 * qlcnic_83xx_idc_find_reset_owner_id
524 *
525 * @adapter: adapter structure
526 *
527 * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE.
528 * Within the same class, function with lowest PCI ID assumes ownership
529 *
530 * Returns: reset owner id or failure indication (-EIO)
531 *
532 **/
533static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter)
534{
535 u32 reg, reg1, reg2, i, j, owner, class;
536
537 reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1);
538 reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2);
539 owner = QLCNIC_TYPE_NIC;
540 i = 0;
541 j = 0;
542 reg = reg1;
543
544 do {
545 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3);
546 if (class == owner)
547 break;
548 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) {
549 reg = reg2;
550 j = 0;
551 } else {
552 j++;
553 }
554
555 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) {
556 if (owner == QLCNIC_TYPE_NIC)
557 owner = QLCNIC_TYPE_ISCSI;
558 else if (owner == QLCNIC_TYPE_ISCSI)
559 owner = QLCNIC_TYPE_FCOE;
560 else if (owner == QLCNIC_TYPE_FCOE)
561 return -EIO;
562 reg = reg1;
563 j = 0;
564 i = 0;
565 }
566 } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS);
567
568 return i;
569}
570
571static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock)
572{
573 int ret = 0;
574
575 ret = qlcnic_83xx_restart_hw(adapter);
576
577 if (ret) {
578 qlcnic_83xx_idc_enter_failed_state(adapter, lock);
579 } else {
580 qlcnic_83xx_idc_clear_registers(adapter, lock);
581 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock);
582 }
583
584 return ret;
585}
586
587static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter)
588{
589 u32 status;
590
591 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1);
592
593 if (status & QLCNIC_RCODE_FATAL_ERROR) {
594 dev_err(&adapter->pdev->dev,
595 "peg halt status1=0x%x\n", status);
596 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) {
597 dev_err(&adapter->pdev->dev,
598 "On board active cooling fan failed. "
599 "Device has been halted.\n");
600 dev_err(&adapter->pdev->dev,
601 "Replace the adapter.\n");
602 return -EIO;
603 }
604 }
605
606 return 0;
607}
608
486a5bc7 609int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter)
629263ac 610{
f036e4f4
RB		 611 int err;
612
d5fcff04
HM		 613 /* register for NIC IDC AEN Events */
614 qlcnic_83xx_register_nic_idc_func(adapter, 1);
615
f036e4f4
RB		 616 err = qlcnic_sriov_pf_reinit(adapter);
617 if (err)
618 return err;
619
629263ac 620 qlcnic_83xx_enable_mbx_intrpt(adapter);
629263ac
SC		 621
622 if (qlcnic_83xx_configure_opmode(adapter)) {
623 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
624 return -EIO;
625 }
626
627 if (adapter->nic_ops->init_driver(adapter)) {
628 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
629 return -EIO;
630 }
631
8af3f33d 632 qlcnic_set_drv_version(adapter);
629263ac
SC		 633 qlcnic_83xx_idc_attach_driver(adapter);
634
635 return 0;
636}
637
638static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter)
639{
536faa61
SC		 640 struct qlcnic_hardware_context *ahw = adapter->ahw;
641
629263ac 642 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1);
629263ac
SC		 643 set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
644 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
645 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
536faa61
SC		 646
647 ahw->idc.quiesce_req = 0;
648 ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
649 ahw->idc.err_code = 0;
650 ahw->idc.collect_dump = 0;
651 ahw->reset_context = 0;
652 adapter->tx_timeo_cnt = 0;
099907fa 653 ahw->idc.delay_reset = 0;
536faa61
SC		 654
655 clear_bit(__QLCNIC_RESETTING, &adapter->state);
629263ac
SC		 656}
657
658/**
659 * qlcnic_83xx_idc_ready_state_entry
660 *
661 * @adapter: adapter structure
662 *
663 * Perform ready state initialization, this routine will get invoked only
664 * once from READY state.
665 *
666 * Returns: Error code or Success(0)
667 *
668 **/
669int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter)
670{
671 struct qlcnic_hardware_context *ahw = adapter->ahw;
672
673 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) {
674 qlcnic_83xx_idc_update_idc_params(adapter);
675 /* Re-attach the device if required */
676 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
677 (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) {
678 if (qlcnic_83xx_idc_reattach_driver(adapter))
679 return -EIO;
680 }
681 }
682
683 return 0;
684}
685
d71170fb
SC		 686/**
687 * qlcnic_83xx_idc_vnic_pf_entry
688 *
689 * @adapter: adapter structure
690 *
691 * Ensure vNIC mode privileged function starts only after vNIC mode is
692 * enabled by management function.
693 * If vNIC mode is ready, start initialization.
694 *
695 * Returns: -EIO or 0
696 *
697 **/
698int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter)
699{
700 u32 state;
701 struct qlcnic_hardware_context *ahw = adapter->ahw;
702
703 /* Privileged function waits till mgmt function enables VNIC mode */
704 state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE);
705 if (state != QLCNIC_DEV_NPAR_OPER) {
706 if (!ahw->idc.vnic_wait_limit--) {
707 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
708 return -EIO;
709 }
710 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n");
711 return -EIO;
712
713 } else {
714 /* Perform one time initialization from ready state */
715 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) {
716 qlcnic_83xx_idc_update_idc_params(adapter);
717
718 /* If the previous state is UNKNOWN, device will be
719 already attached properly by Init routine*/
720 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) {
721 if (qlcnic_83xx_idc_reattach_driver(adapter))
722 return -EIO;
723 }
724 adapter->ahw->idc.vnic_state = QLCNIC_DEV_NPAR_OPER;
725 dev_info(&adapter->pdev->dev, "vNIC mode enabled\n");
726 }
727 }
728
729 return 0;
730}
731
629263ac
SC		 732static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter)
733{
734 adapter->ahw->idc.err_code = -EIO;
735 dev_err(&adapter->pdev->dev,
736 "%s: Device in unknown state\n", __func__);
737 return 0;
738}
739
740/**
741 * qlcnic_83xx_idc_cold_state
742 *
743 * @adapter: adapter structure
744 *
745 * If HW is up and running device will enter READY state.
746 * If firmware image from host needs to be loaded, device is
747 * forced to start with the file firmware image.
748 *
749 * Returns: Error code or Success(0)
750 *
751 **/
752static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter)
753{
754 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0);
755 qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0);
756
757 if (qlcnic_load_fw_file) {
758 qlcnic_83xx_idc_restart_hw(adapter, 0);
759 } else {
760 if (qlcnic_83xx_check_hw_status(adapter)) {
761 qlcnic_83xx_idc_enter_failed_state(adapter, 0);
762 return -EIO;
763 } else {
764 qlcnic_83xx_idc_enter_ready_state(adapter, 0);
765 }
766 }
767 return 0;
768}
769
770/**
771 * qlcnic_83xx_idc_init_state
772 *
773 * @adapter: adapter structure
774 *
775 * Reset owner will restart the device from this state.
776 * Device will enter failed state if it remains
777 * in this state for more than DEV_INIT time limit.
778 *
779 * Returns: Error code or Success(0)
780 *
781 **/
782static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter)
783{
784 int timeout, ret = 0;
785 u32 owner;
786
787 timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
788 if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) {
789 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
790 if (adapter->ahw->pci_func == owner)
791 ret = qlcnic_83xx_idc_restart_hw(adapter, 1);
792 } else {
793 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout);
794 return ret;
795 }
796
797 return ret;
798}
799
800/**
801 * qlcnic_83xx_idc_ready_state
802 *
803 * @adapter: adapter structure
804 *
805 * Perform IDC protocol specicifed actions after monitoring device state and
806 * events.
807 *
808 * Returns: Error code or Success(0)
809 *
810 **/
811static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter)
812{
813 u32 val;
814 struct qlcnic_hardware_context *ahw = adapter->ahw;
815 int ret = 0;
816
817 /* Perform NIC configuration based ready state entry actions */
818 if (ahw->idc.state_entry(adapter))
819 return -EIO;
820
821 if (qlcnic_check_temp(adapter)) {
822 if (ahw->temp == QLCNIC_TEMP_PANIC) {
823 qlcnic_83xx_idc_check_fan_failure(adapter);
824 dev_err(&adapter->pdev->dev,
825 "Error: device temperature %d above limits\n",
826 adapter->ahw->temp);
827 clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status);
828 set_bit(__QLCNIC_RESETTING, &adapter->state);
829 qlcnic_83xx_idc_detach_driver(adapter);
830 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
831 return -EIO;
832 }
833 }
834
835 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
836 ret = qlcnic_83xx_check_heartbeat(adapter);
837 if (ret) {
838 adapter->flags |= QLCNIC_FW_HANG;
839 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
840 clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status);
841 set_bit(__QLCNIC_RESETTING, &adapter->state);
842 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
843 }
844 return -EIO;
845 }
846
847 if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) {
848 /* Move to need reset state and prepare for reset */
849 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
850 return ret;
851 }
852
853 /* Check for soft reset request */
854 if (ahw->reset_context &&
855 !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
536faa61 856 adapter->ahw->reset_context = 0;
629263ac
SC		 857 qlcnic_83xx_idc_tx_soft_reset(adapter);
858 return ret;
859 }
860
861 /* Move to need quiesce state if requested */
862 if (adapter->ahw->idc.quiesce_req) {
863 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1);
864 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
865 return ret;
866 }
867
868 return ret;
869}
870
871/**
872 * qlcnic_83xx_idc_need_reset_state
873 *
874 * @adapter: adapter structure
875 *
876 * Device will remain in this state until:
877 * Reset request ACK's are recieved from all the functions
878 * Wait time exceeds max time limit
879 *
880 * Returns: Error code or Success(0)
881 *
882 **/
883static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter)
884{
885 int ret = 0;
886
887 if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) {
629263ac
SC		 888 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
889 set_bit(__QLCNIC_RESETTING, &adapter->state);
890 clear_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
d71170fb
SC		 891 if (adapter->ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE)
892 qlcnic_83xx_disable_vnic_mode(adapter, 1);
099907fa
SC		 893
894 if (qlcnic_check_diag_status(adapter)) {
895 dev_info(&adapter->pdev->dev,
896 "%s: Wait for diag completion\n", __func__);
897 adapter->ahw->idc.delay_reset = 1;
898 return 0;
899 } else {
900 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
901 qlcnic_83xx_idc_detach_driver(adapter);
902 }
629263ac
SC		 903 }
904
099907fa 905 if (qlcnic_check_diag_status(adapter)) {
629263ac 906 dev_info(&adapter->pdev->dev,
099907fa
SC		 907 "%s: Wait for diag completion\n", __func__);
908 return -1;
909 } else {
910 if (adapter->ahw->idc.delay_reset) {
911 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
912 qlcnic_83xx_idc_detach_driver(adapter);
913 adapter->ahw->idc.delay_reset = 0;
914 }
915
916 /* Check for ACK from other functions */
917 ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter);
918 if (ret) {
919 dev_info(&adapter->pdev->dev,
920 "%s: Waiting for reset ACK\n", __func__);
921 return -1;
922 }
629263ac
SC		 923 }
924
925 /* Transit to INIT state and restart the HW */
926 qlcnic_83xx_idc_enter_init_state(adapter, 1);
927
928 return ret;
929}
930
931static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter)
932{
933 dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__);
934 return 0;
935}
936
937static int qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter)
938{
939 dev_err(&adapter->pdev->dev, "%s: please restart!!\n", __func__);
536faa61 940 clear_bit(__QLCNIC_RESETTING, &adapter->state);
629263ac
SC		 941 adapter->ahw->idc.err_code = -EIO;
942
943 return 0;
944}
945
946static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter)
947{
948 dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__);
949 return 0;
950}
951
952static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter,
953 u32 state)
954{
955 u32 cur, prev, next;
956
957 cur = adapter->ahw->idc.curr_state;
958 prev = adapter->ahw->idc.prev_state;
959 next = state;
960
961 if ((next < QLC_83XX_IDC_DEV_COLD) ||
962 (next > QLC_83XX_IDC_DEV_QUISCENT)) {
963 dev_err(&adapter->pdev->dev,
964 "%s: curr %d, prev %d, next state %d is invalid\n",
965 __func__, cur, prev, state);
966 return 1;
967 }
968
969 if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) &&
970 (prev == QLC_83XX_IDC_DEV_UNKNOWN)) {
971 if ((next != QLC_83XX_IDC_DEV_COLD) &&
972 (next != QLC_83XX_IDC_DEV_READY)) {
973 dev_err(&adapter->pdev->dev,
974 "%s: failed, cur %d prev %d next %d\n",
975 __func__, cur, prev, next);
976 return 1;
977 }
978 }
979
980 if (next == QLC_83XX_IDC_DEV_INIT) {
981 if ((prev != QLC_83XX_IDC_DEV_INIT) &&
982 (prev != QLC_83XX_IDC_DEV_COLD) &&
983 (prev != QLC_83XX_IDC_DEV_NEED_RESET)) {
984 dev_err(&adapter->pdev->dev,
985 "%s: failed, cur %d prev %d next %d\n",
986 __func__, cur, prev, next);
987 return 1;
988 }
989 }
990
991 return 0;
992}
993
994static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter)
995{
996 if (adapter->fhash.fnum)
997 qlcnic_prune_lb_filters(adapter);
998}
999
1000/**
1001 * qlcnic_83xx_idc_poll_dev_state
1002 *
1003 * @work: kernel work queue structure used to schedule the function
1004 *
1005 * Poll device state periodically and perform state specific
1006 * actions defined by Inter Driver Communication (IDC) protocol.
1007 *
1008 * Returns: None
1009 *
1010 **/
1011void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work)
1012{
1013 struct qlcnic_adapter *adapter;
1014 u32 state;
1015
1016 adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
1017 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1018
1019 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1020 qlcnic_83xx_idc_log_state_history(adapter);
1021 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1022 } else {
1023 adapter->ahw->idc.curr_state = state;
1024 }
1025
1026 switch (adapter->ahw->idc.curr_state) {
1027 case QLC_83XX_IDC_DEV_READY:
1028 qlcnic_83xx_idc_ready_state(adapter);
1029 break;
1030 case QLC_83XX_IDC_DEV_NEED_RESET:
1031 qlcnic_83xx_idc_need_reset_state(adapter);
1032 break;
1033 case QLC_83XX_IDC_DEV_NEED_QUISCENT:
1034 qlcnic_83xx_idc_need_quiesce_state(adapter);
1035 break;
1036 case QLC_83XX_IDC_DEV_FAILED:
1037 qlcnic_83xx_idc_failed_state(adapter);
1038 return;
1039 case QLC_83XX_IDC_DEV_INIT:
1040 qlcnic_83xx_idc_init_state(adapter);
1041 break;
1042 case QLC_83XX_IDC_DEV_QUISCENT:
1043 qlcnic_83xx_idc_quiesce_state(adapter);
1044 break;
1045 default:
1046 qlcnic_83xx_idc_unknown_state(adapter);
1047 return;
1048 }
1049 adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state;
1050 qlcnic_83xx_periodic_tasks(adapter);
1051
1052 /* Re-schedule the function */
1053 if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status))
1054 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
1055 adapter->ahw->idc.delay);
1056}
1057
1058static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter)
1059{
1060 u32 idc_params, val;
1061
1062 if (qlcnic_83xx_lockless_flash_read32(adapter,
1063 QLC_83XX_IDC_FLASH_PARAM_ADDR,
1064 (u8 *)&idc_params, 1)) {
1065 dev_info(&adapter->pdev->dev,
1066 "%s:failed to get IDC params from flash\n", __func__);
1067 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
1068 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
1069 } else {
1070 adapter->dev_init_timeo = idc_params & 0xFFFF;
1071 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF);
1072 }
1073
1074 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1075 adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN;
1076 adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
1077 adapter->ahw->idc.err_code = 0;
1078 adapter->ahw->idc.collect_dump = 0;
1079 adapter->ahw->idc.name = (char **)qlc_83xx_idc_states;
1080
1081 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1082 set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
1083 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1084
1085 /* Check if reset recovery is disabled */
1086 if (!qlcnic_auto_fw_reset) {
1087 /* Propagate do not reset request to other functions */
1088 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1089 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1090 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1091 }
1092}
1093
1094static int
1095qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter)
1096{
1097 u32 state, val;
1098
1099 if (qlcnic_83xx_lock_driver(adapter))
1100 return -EIO;
1101
1102 /* Clear driver lock register */
1103 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0);
1104 if (qlcnic_83xx_idc_update_major_version(adapter, 0)) {
1105 qlcnic_83xx_unlock_driver(adapter);
1106 return -EIO;
1107 }
1108
1109 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1110 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1111 qlcnic_83xx_unlock_driver(adapter);
1112 return -EIO;
1113 }
1114
1115 if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) {
1116 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
1117 QLC_83XX_IDC_DEV_COLD);
1118 state = QLC_83XX_IDC_DEV_COLD;
1119 }
1120
1121 adapter->ahw->idc.curr_state = state;
1122 /* First to load function should cold boot the device */
1123 if (state == QLC_83XX_IDC_DEV_COLD)
1124 qlcnic_83xx_idc_cold_state_handler(adapter);
1125
1126 /* Check if reset recovery is enabled */
1127 if (qlcnic_auto_fw_reset) {
1128 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1129 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1130 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1131 }
1132
1133 qlcnic_83xx_unlock_driver(adapter);
1134
1135 return 0;
1136}
1137
486a5bc7 1138int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter)
629263ac 1139{
81d0aeb0
SC		 1140 int ret = -EIO;
1141
629263ac
SC		 1142 qlcnic_83xx_setup_idc_parameters(adapter);
1143
81d0aeb0
SC		 1144 if (qlcnic_83xx_get_reset_instruction_template(adapter))
1145 return ret;
1146
629263ac
SC		 1147 if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) {
1148 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter))
1149 return -EIO;
1150 } else {
1151 if (qlcnic_83xx_idc_check_major_version(adapter))
1152 return -EIO;
1153 }
1154
1155 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
1156
1157 return 0;
1158}
1159
1160void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter)
1161{
1162 int id;
1163 u32 val;
1164
1165 while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1166 usleep_range(10000, 11000);
1167
1168 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1169 id = id & 0xFF;
1170
1171 if (id == adapter->portnum) {
1172 dev_err(&adapter->pdev->dev,
1173 "%s: wait for lock recovery.. %d\n", __func__, id);
1174 msleep(20);
1175 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1176 id = id & 0xFF;
1177 }
1178
1179 /* Clear driver presence bit */
1180 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
1181 val = val & ~(1 << adapter->portnum);
1182 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
1183 clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1184 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1185
1186 cancel_delayed_work_sync(&adapter->fw_work);
1187}
1188
1189void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key)
1190{
1191 u32 val;
1192
1193 if (qlcnic_83xx_lock_driver(adapter)) {
1194 dev_err(&adapter->pdev->dev,
1195 "%s:failed, please retry\n", __func__);
1196 return;
1197 }
1198
1199 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1200 if ((val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) ||
1201 !qlcnic_auto_fw_reset) {
1202 dev_err(&adapter->pdev->dev,
1203 "%s:failed, device in non reset mode\n", __func__);
1204 qlcnic_83xx_unlock_driver(adapter);
1205 return;
1206 }
1207
1208 if (key == QLCNIC_FORCE_FW_RESET) {
1209 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1210 val = val | QLC_83XX_IDC_GRACEFULL_RESET;
1211 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1212 } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) {
1213 adapter->ahw->idc.collect_dump = 1;
1214 }
1215
1216 qlcnic_83xx_unlock_driver(adapter);
1217 return;
1218}
1219
1220static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter)
1221{
1222 u8 *p_cache;
1223 u32 src, size;
1224 u64 dest;
1225 int ret = -EIO;
1226
1227 src = QLC_83XX_BOOTLOADER_FLASH_ADDR;
1228 dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR);
1229 size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE);
1230
1231 /* alignment check */
1232 if (size & 0xF)
1233 size = (size + 16) & ~0xF;
1234
1235 p_cache = kzalloc(size, GFP_KERNEL);
b2adaca9 1236 if (p_cache == NULL)
629263ac 1237 return -ENOMEM;
b2adaca9 1238
629263ac
SC		 1239 ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache,
1240 size / sizeof(u32));
1241 if (ret) {
1242 kfree(p_cache);
1243 return ret;
1244 }
1245 /* 16 byte write to MS memory */
1246 ret = qlcnic_83xx_ms_mem_write128(adapter, dest, (u32 *)p_cache,
1247 size / 16);
1248 if (ret) {
1249 kfree(p_cache);
1250 return ret;
1251 }
1252 kfree(p_cache);
1253
1254 return ret;
1255}
1256
1257static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter)
1258{
1259 u32 dest, *p_cache;
1260 u64 addr;
1261 u8 data[16];
1262 size_t size;
1263 int i, ret = -EIO;
1264
1265 dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR);
1266 size = (adapter->ahw->fw_info.fw->size & ~0xF);
1267 p_cache = (u32 *)adapter->ahw->fw_info.fw->data;
1268 addr = (u64)dest;
1269
1270 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1271 (u32 *)p_cache, size / 16);
1272 if (ret) {
1273 dev_err(&adapter->pdev->dev, "MS memory write failed\n");
1274 release_firmware(adapter->ahw->fw_info.fw);
1275 adapter->ahw->fw_info.fw = NULL;
1276 return -EIO;
1277 }
1278
1279 /* alignment check */
1280 if (adapter->ahw->fw_info.fw->size & 0xF) {
1281 addr = dest + size;
1282 for (i = 0; i < (adapter->ahw->fw_info.fw->size & 0xF); i++)
1283 data[i] = adapter->ahw->fw_info.fw->data[size + i];
1284 for (; i < 16; i++)
1285 data[i] = 0;
1286 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1287 (u32 *)data, 1);
1288 if (ret) {
1289 dev_err(&adapter->pdev->dev,
1290 "MS memory write failed\n");
1291 release_firmware(adapter->ahw->fw_info.fw);
1292 adapter->ahw->fw_info.fw = NULL;
1293 return -EIO;
1294 }
1295 }
1296 release_firmware(adapter->ahw->fw_info.fw);
1297 adapter->ahw->fw_info.fw = NULL;
1298
1299 return 0;
1300}
1301
1302static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter)
1303{
1304 int i, j;
1305 u32 val = 0, val1 = 0, reg = 0;
1306
1307 val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG);
1308 dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val);
1309
1310 for (j = 0; j < 2; j++) {
1311 if (j == 0) {
1312 dev_info(&adapter->pdev->dev,
1313 "Port 0 RxB Pause Threshold Regs[TC7..TC0]:");
1314 reg = QLC_83XX_PORT0_THRESHOLD;
1315 } else if (j == 1) {
1316 dev_info(&adapter->pdev->dev,
1317 "Port 1 RxB Pause Threshold Regs[TC7..TC0]:");
1318 reg = QLC_83XX_PORT1_THRESHOLD;
1319 }
1320 for (i = 0; i < 8; i++) {
1321 val = QLCRD32(adapter, reg + (i * 0x4));
1322 dev_info(&adapter->pdev->dev, "0x%x ", val);
1323 }
1324 dev_info(&adapter->pdev->dev, "\n");
1325 }
1326
1327 for (j = 0; j < 2; j++) {
1328 if (j == 0) {
1329 dev_info(&adapter->pdev->dev,
1330 "Port 0 RxB TC Max Cell Registers[4..1]:");
1331 reg = QLC_83XX_PORT0_TC_MC_REG;
1332 } else if (j == 1) {
1333 dev_info(&adapter->pdev->dev,
1334 "Port 1 RxB TC Max Cell Registers[4..1]:");
1335 reg = QLC_83XX_PORT1_TC_MC_REG;
1336 }
1337 for (i = 0; i < 4; i++) {
1338 val = QLCRD32(adapter, reg + (i * 0x4));
1339 dev_info(&adapter->pdev->dev, "0x%x ", val);
1340 }
1341 dev_info(&adapter->pdev->dev, "\n");
1342 }
1343
1344 for (j = 0; j < 2; j++) {
1345 if (j == 0) {
1346 dev_info(&adapter->pdev->dev,
1347 "Port 0 RxB Rx TC Stats[TC7..TC0]:");
1348 reg = QLC_83XX_PORT0_TC_STATS;
1349 } else if (j == 1) {
1350 dev_info(&adapter->pdev->dev,
1351 "Port 1 RxB Rx TC Stats[TC7..TC0]:");
1352 reg = QLC_83XX_PORT1_TC_STATS;
1353 }
1354 for (i = 7; i >= 0; i--) {
1355 val = QLCRD32(adapter, reg);
1356 val &= ~(0x7 << 29); /* Reset bits 29 to 31 */
1357 QLCWR32(adapter, reg, (val | (i << 29)));
1358 val = QLCRD32(adapter, reg);
1359 dev_info(&adapter->pdev->dev, "0x%x ", val);
1360 }
1361 dev_info(&adapter->pdev->dev, "\n");
1362 }
1363
1364 val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD);
1365 val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD);
1366 dev_info(&adapter->pdev->dev,
1367 "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n",
1368 val, val1);
1369}
1370
81d0aeb0 1371
629263ac
SC		 1372static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter)
1373{
1374 u32 reg = 0, i, j;
1375
1376 if (qlcnic_83xx_lock_driver(adapter)) {
1377 dev_err(&adapter->pdev->dev,
1378 "%s:failed to acquire driver lock\n", __func__);
1379 return;
1380 }
1381
1382 qlcnic_83xx_dump_pause_control_regs(adapter);
1383 QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0);
1384
1385 for (j = 0; j < 2; j++) {
1386 if (j == 0)
1387 reg = QLC_83XX_PORT0_THRESHOLD;
1388 else if (j == 1)
1389 reg = QLC_83XX_PORT1_THRESHOLD;
1390
1391 for (i = 0; i < 8; i++)
1392 QLCWR32(adapter, reg + (i * 0x4), 0x0);
1393 }
1394
1395 for (j = 0; j < 2; j++) {
1396 if (j == 0)
1397 reg = QLC_83XX_PORT0_TC_MC_REG;
1398 else if (j == 1)
1399 reg = QLC_83XX_PORT1_TC_MC_REG;
1400
1401 for (i = 0; i < 4; i++)
1402 QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF);
1403 }
1404
1405 QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0);
1406 QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0);
1407 dev_info(&adapter->pdev->dev,
1408 "Disabled pause frames successfully on all ports\n");
1409 qlcnic_83xx_unlock_driver(adapter);
1410}
1411
c0d79cd0
MC		 1412static void qlcnic_83xx_take_eport_out_of_reset(struct qlcnic_adapter *adapter)
1413{
1414 QLCWR32(adapter, QLC_83XX_RESET_REG, 0);
1415 QLCWR32(adapter, QLC_83XX_RESET_PORT0, 0);
1416 QLCWR32(adapter, QLC_83XX_RESET_PORT1, 0);
1417 QLCWR32(adapter, QLC_83XX_RESET_PORT2, 0);
1418 QLCWR32(adapter, QLC_83XX_RESET_PORT3, 0);
1419 QLCWR32(adapter, QLC_83XX_RESET_SRESHIM, 0);
1420 QLCWR32(adapter, QLC_83XX_RESET_EPGSHIM, 0);
1421 QLCWR32(adapter, QLC_83XX_RESET_ETHERPCS, 0);
1422 QLCWR32(adapter, QLC_83XX_RESET_CONTROL, 1);
1423}
1424
629263ac
SC		 1425static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev)
1426{
1427 u32 heartbeat, peg_status;
1428 int retries, ret = -EIO;
1429
1430 retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT;
1431 p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev,
1432 QLCNIC_PEG_ALIVE_COUNTER);
1433
1434 do {
1435 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS);
1436 heartbeat = QLC_SHARED_REG_RD32(p_dev,
1437 QLCNIC_PEG_ALIVE_COUNTER);
1438 if (heartbeat != p_dev->heartbeat) {
1439 ret = QLCNIC_RCODE_SUCCESS;
1440 break;
1441 }
1442 } while (--retries);
1443
1444 if (ret) {
1445 dev_err(&p_dev->pdev->dev, "firmware hang detected\n");
c0d79cd0 1446 qlcnic_83xx_take_eport_out_of_reset(p_dev);
629263ac
SC		 1447 qlcnic_83xx_disable_pause_frames(p_dev);
1448 peg_status = QLC_SHARED_REG_RD32(p_dev,
1449 QLCNIC_PEG_HALT_STATUS1);
1450 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n"
1451 "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n"
1452 "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n"
1453 "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n"
1454 "PEG_NET_4_PC: 0x%x\n", peg_status,
1455 QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2),
1456 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0),
1457 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1),
1458 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2),
1459 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3),
1460 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4));
1461
1462 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67)
1463 dev_err(&p_dev->pdev->dev,
1464 "Device is being reset err code 0x00006700.\n");
1465 }
1466
1467 return ret;
1468}
1469
1470static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev)
1471{
1472 int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT;
1473 u32 val;
1474
1475 do {
1476 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE);
1477 if (val == QLC_83XX_CMDPEG_COMPLETE)
1478 return 0;
1479 msleep(QLCNIC_CMDPEG_CHECK_DELAY);
1480 } while (--retries);
1481
1482 dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val);
1483 return -EIO;
1484}
1485
1486int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev)
1487{
1488 int err;
1489
1490 err = qlcnic_83xx_check_cmd_peg_status(p_dev);
1491 if (err)
1492 return err;
1493
1494 err = qlcnic_83xx_check_heartbeat(p_dev);
1495 if (err)
1496 return err;
1497
1498 return err;
1499}
1500
81d0aeb0
SC		 1501static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr,
1502 int duration, u32 mask, u32 status)
1503{
1504 u32 value;
1505 int timeout_error;
1506 u8 retries;
1507
1508 value = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1509 retries = duration / 10;
1510
1511 do {
1512 if ((value & mask) != status) {
1513 timeout_error = 1;
1514 msleep(duration / 10);
1515 value = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1516 } else {
1517 timeout_error = 0;
1518 break;
1519 }
1520 } while (retries--);
1521
1522 if (timeout_error) {
1523 p_dev->ahw->reset.seq_error++;
1524 dev_err(&p_dev->pdev->dev,
1525 "%s: Timeout Err, entry_num = %d\n",
1526 __func__, p_dev->ahw->reset.seq_index);
1527 dev_err(&p_dev->pdev->dev,
1528 "0x%08x 0x%08x 0x%08x\n",
1529 value, mask, status);
1530 }
1531
1532 return timeout_error;
1533}
1534
1535static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev)
1536{
1537 u32 sum = 0;
1538 u16 *buff = (u16 *)p_dev->ahw->reset.buff;
1539 int count = p_dev->ahw->reset.hdr->size / sizeof(u16);
1540
1541 while (count-- > 0)
1542 sum += *buff++;
1543
1544 while (sum >> 16)
1545 sum = (sum & 0xFFFF) + (sum >> 16);
1546
1547 if (~sum) {
1548 return 0;
1549 } else {
1550 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1551 return -1;
1552 }
1553}
1554
1555int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev)
1556{
81d0aeb0 1557 struct qlcnic_hardware_context *ahw = p_dev->ahw;
486a5bc7
RB		 1558 u32 addr, count, prev_ver, curr_ver;
1559 u8 *p_buff;
1560
1561 if (ahw->reset.buff != NULL) {
1562 prev_ver = p_dev->fw_version;
1563 curr_ver = qlcnic_83xx_get_fw_version(p_dev);
1564 if (curr_ver > prev_ver)
1565 kfree(ahw->reset.buff);
1566 else
1567 return 0;
1568 }
81d0aeb0
SC		 1569
1570 ahw->reset.seq_error = 0;
1571 ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL);
b2adaca9 1572 if (p_dev->ahw->reset.buff == NULL)
81d0aeb0 1573 return -ENOMEM;
b2adaca9 1574
81d0aeb0
SC		 1575 p_buff = p_dev->ahw->reset.buff;
1576 addr = QLC_83XX_RESET_TEMPLATE_ADDR;
1577 count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32);
1578
1579 /* Copy template header from flash */
1580 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1581 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1582 return -EIO;
1583 }
1584 ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff;
1585 addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size;
1586 p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1587 count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32);
1588
1589 /* Copy rest of the template */
1590 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1591 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1592 return -EIO;
1593 }
1594
1595 if (qlcnic_83xx_reset_template_checksum(p_dev))
1596 return -EIO;
1597 /* Get Stop, Start and Init command offsets */
1598 ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset;
1599 ahw->reset.start_offset = ahw->reset.buff +
1600 ahw->reset.hdr->start_offset;
1601 ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1602 return 0;
1603}
1604
1605/* Read Write HW register command */
1606static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev,
1607 u32 raddr, u32 waddr)
1608{
1609 int value;
1610
1611 value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr);
1612 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1613}
1614
1615/* Read Modify Write HW register command */
1616static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev,
1617 u32 raddr, u32 waddr,
1618 struct qlc_83xx_rmw *p_rmw_hdr)
1619{
1620 int value;
1621
1622 if (p_rmw_hdr->index_a)
1623 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a];
1624 else
1625 value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr);
1626
1627 value &= p_rmw_hdr->mask;
1628 value <<= p_rmw_hdr->shl;
1629 value >>= p_rmw_hdr->shr;
1630 value |= p_rmw_hdr->or_value;
1631 value ^= p_rmw_hdr->xor_value;
1632 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1633}
1634
1635/* Write HW register command */
1636static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev,
1637 struct qlc_83xx_entry_hdr *p_hdr)
1638{
1639 int i;
1640 struct qlc_83xx_entry *entry;
1641
1642 entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1643 sizeof(struct qlc_83xx_entry_hdr));
1644
1645 for (i = 0; i < p_hdr->count; i++, entry++) {
1646 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1,
1647 entry->arg2);
1648 if (p_hdr->delay)
1649 udelay((u32)(p_hdr->delay));
1650 }
1651}
1652
1653/* Read and Write instruction */
1654static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev,
1655 struct qlc_83xx_entry_hdr *p_hdr)
1656{
1657 int i;
1658 struct qlc_83xx_entry *entry;
1659
1660 entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1661 sizeof(struct qlc_83xx_entry_hdr));
1662
1663 for (i = 0; i < p_hdr->count; i++, entry++) {
1664 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1,
1665 entry->arg2);
1666 if (p_hdr->delay)
1667 udelay((u32)(p_hdr->delay));
1668 }
1669}
1670
1671/* Poll HW register command */
1672static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev,
1673 struct qlc_83xx_entry_hdr *p_hdr)
1674{
1675 long delay;
1676 struct qlc_83xx_entry *entry;
1677 struct qlc_83xx_poll *poll;
1678 int i;
1679 unsigned long arg1, arg2;
1680
1681 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1682 sizeof(struct qlc_83xx_entry_hdr));
1683
1684 entry = (struct qlc_83xx_entry *)((char *)poll +
1685 sizeof(struct qlc_83xx_poll));
1686 delay = (long)p_hdr->delay;
1687
1688 if (!delay) {
1689 for (i = 0; i < p_hdr->count; i++, entry++)
1690 qlcnic_83xx_poll_reg(p_dev, entry->arg1,
1691 delay, poll->mask,
1692 poll->status);
1693 } else {
1694 for (i = 0; i < p_hdr->count; i++, entry++) {
1695 arg1 = entry->arg1;
1696 arg2 = entry->arg2;
1697 if (delay) {
1698 if (qlcnic_83xx_poll_reg(p_dev,
1699 arg1, delay,
1700 poll->mask,
1701 poll->status)){
1702 qlcnic_83xx_rd_reg_indirect(p_dev,
1703 arg1);
1704 qlcnic_83xx_rd_reg_indirect(p_dev,
1705 arg2);
1706 }
1707 }
1708 }
1709 }
1710}
1711
1712/* Poll and write HW register command */
1713static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev,
1714 struct qlc_83xx_entry_hdr *p_hdr)
1715{
1716 int i;
1717 long delay;
1718 struct qlc_83xx_quad_entry *entry;
1719 struct qlc_83xx_poll *poll;
1720
1721 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1722 sizeof(struct qlc_83xx_entry_hdr));
1723 entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1724 sizeof(struct qlc_83xx_poll));
1725 delay = (long)p_hdr->delay;
1726
1727 for (i = 0; i < p_hdr->count; i++, entry++) {
1728 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr,
1729 entry->dr_value);
1730 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1731 entry->ar_value);
1732 if (delay)
1733 qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1734 poll->mask, poll->status);
1735 }
1736}
1737
1738/* Read Modify Write register command */
1739static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev,
1740 struct qlc_83xx_entry_hdr *p_hdr)
1741{
1742 int i;
1743 struct qlc_83xx_entry *entry;
1744 struct qlc_83xx_rmw *rmw_hdr;
1745
1746 rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr +
1747 sizeof(struct qlc_83xx_entry_hdr));
1748
1749 entry = (struct qlc_83xx_entry *)((char *)rmw_hdr +
1750 sizeof(struct qlc_83xx_rmw));
1751
1752 for (i = 0; i < p_hdr->count; i++, entry++) {
1753 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1,
1754 entry->arg2, rmw_hdr);
1755 if (p_hdr->delay)
1756 udelay((u32)(p_hdr->delay));
1757 }
1758}
1759
1760static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr)
1761{
1762 if (p_hdr->delay)
1763 mdelay((u32)((long)p_hdr->delay));
1764}
1765
1766/* Read and poll register command */
1767static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev,
1768 struct qlc_83xx_entry_hdr *p_hdr)
1769{
1770 long delay;
1771 int index, i, j;
1772 struct qlc_83xx_quad_entry *entry;
1773 struct qlc_83xx_poll *poll;
1774 unsigned long addr;
1775
1776 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1777 sizeof(struct qlc_83xx_entry_hdr));
1778
1779 entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1780 sizeof(struct qlc_83xx_poll));
1781 delay = (long)p_hdr->delay;
1782
1783 for (i = 0; i < p_hdr->count; i++, entry++) {
1784 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1785 entry->ar_value);
1786 if (delay) {
1787 if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1788 poll->mask, poll->status)){
1789 index = p_dev->ahw->reset.array_index;
1790 addr = entry->dr_addr;
1791 j = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1792 p_dev->ahw->reset.array[index++] = j;
1793
1794 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES)
1795 p_dev->ahw->reset.array_index = 1;
1796 }
1797 }
1798 }
1799}
1800
1801static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev)
1802{
1803 p_dev->ahw->reset.seq_end = 1;
1804}
1805
1806static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev)
1807{
1808 p_dev->ahw->reset.template_end = 1;
1809 if (p_dev->ahw->reset.seq_error == 0)
1810 dev_err(&p_dev->pdev->dev,
1811 "HW restart process completed successfully.\n");
1812 else
1813 dev_err(&p_dev->pdev->dev,
1814 "HW restart completed with timeout errors.\n");
1815}
1816
1817/**
1818* qlcnic_83xx_exec_template_cmd
1819*
1820* @p_dev: adapter structure
1821* @p_buff: Poiter to instruction template
1822*
1823* Template provides instructions to stop, restart and initalize firmware.
1824* These instructions are abstracted as a series of read, write and
1825* poll operations on hardware registers. Register information and operation
1826* specifics are not exposed to the driver. Driver reads the template from
1827* flash and executes the instructions located at pre-defined offsets.
1828*
1829* Returns: None
1830* */
1831static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev,
1832 char *p_buff)
1833{
1834 int index, entries;
1835 struct qlc_83xx_entry_hdr *p_hdr;
1836 char *entry = p_buff;
1837
1838 p_dev->ahw->reset.seq_end = 0;
1839 p_dev->ahw->reset.template_end = 0;
1840 entries = p_dev->ahw->reset.hdr->entries;
1841 index = p_dev->ahw->reset.seq_index;
1842
1843 for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) {
1844 p_hdr = (struct qlc_83xx_entry_hdr *)entry;
1845
1846 switch (p_hdr->cmd) {
1847 case QLC_83XX_OPCODE_NOP:
1848 break;
1849 case QLC_83XX_OPCODE_WRITE_LIST:
1850 qlcnic_83xx_write_list(p_dev, p_hdr);
1851 break;
1852 case QLC_83XX_OPCODE_READ_WRITE_LIST:
1853 qlcnic_83xx_read_write_list(p_dev, p_hdr);
1854 break;
1855 case QLC_83XX_OPCODE_POLL_LIST:
1856 qlcnic_83xx_poll_list(p_dev, p_hdr);
1857 break;
1858 case QLC_83XX_OPCODE_POLL_WRITE_LIST:
1859 qlcnic_83xx_poll_write_list(p_dev, p_hdr);
1860 break;
1861 case QLC_83XX_OPCODE_READ_MODIFY_WRITE:
1862 qlcnic_83xx_read_modify_write(p_dev, p_hdr);
1863 break;
1864 case QLC_83XX_OPCODE_SEQ_PAUSE:
1865 qlcnic_83xx_pause(p_hdr);
1866 break;
1867 case QLC_83XX_OPCODE_SEQ_END:
1868 qlcnic_83xx_seq_end(p_dev);
1869 break;
1870 case QLC_83XX_OPCODE_TMPL_END:
1871 qlcnic_83xx_template_end(p_dev);
1872 break;
1873 case QLC_83XX_OPCODE_POLL_READ_LIST:
1874 qlcnic_83xx_poll_read_list(p_dev, p_hdr);
1875 break;
1876 default:
1877 dev_err(&p_dev->pdev->dev,
1878 "%s: Unknown opcode 0x%04x in template %d\n",
1879 __func__, p_hdr->cmd, index);
1880 break;
1881 }
1882 entry += p_hdr->size;
1883 }
1884 p_dev->ahw->reset.seq_index = index;
1885}
1886
1887static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev)
1888{
1889 p_dev->ahw->reset.seq_index = 0;
1890
1891 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset);
1892 if (p_dev->ahw->reset.seq_end != 1)
1893 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1894}
1895
1896static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev)
1897{
1898 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset);
1899 if (p_dev->ahw->reset.template_end != 1)
1900 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1901}
1902
1903static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev)
1904{
1905 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset);
1906 if (p_dev->ahw->reset.seq_end != 1)
1907 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1908}
1909
629263ac
SC		 1910static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter)
1911{
1912 int err = -EIO;
1913
1914 if (request_firmware(&adapter->ahw->fw_info.fw,
1915 QLC_83XX_FW_FILE_NAME, &(adapter->pdev->dev))) {
1916 dev_err(&adapter->pdev->dev,
1917 "No file FW image, loading flash FW image.\n");
1918 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1919 QLC_83XX_BOOT_FROM_FLASH);
1920 } else {
1921 if (qlcnic_83xx_copy_fw_file(adapter))
1922 return err;
1923 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1924 QLC_83XX_BOOT_FROM_FILE);
1925 }
1926
1927 return 0;
1928}
1929
1930static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter)
1931{
4e60ac46 1932 u32 val;
629263ac
SC		 1933 int err = -EIO;
1934
81d0aeb0 1935 qlcnic_83xx_stop_hw(adapter);
4e60ac46
SC		 1936
1937 /* Collect FW register dump if required */
1938 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1939 if (!(val & QLC_83XX_IDC_GRACEFULL_RESET))
1940 qlcnic_dump_fw(adapter);
81d0aeb0
SC		 1941 qlcnic_83xx_init_hw(adapter);
1942
629263ac
SC		 1943 if (qlcnic_83xx_copy_bootloader(adapter))
1944 return err;
1945 /* Boot either flash image or firmware image from host file system */
1946 if (qlcnic_load_fw_file) {
1947 if (qlcnic_83xx_load_fw_image_from_host(adapter))
1948 return err;
1949 } else {
1950 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1951 QLC_83XX_BOOT_FROM_FLASH);
1952 }
1953
81d0aeb0 1954 qlcnic_83xx_start_hw(adapter);
629263ac
SC		 1955 if (qlcnic_83xx_check_hw_status(adapter))
1956 return -EIO;
1957
1958 return 0;
1959}
1960
1961/**
1962* qlcnic_83xx_config_default_opmode
1963*
1964* @adapter: adapter structure
1965*
1966* Configure default driver operating mode
1967*
1968* Returns: Error code or Success(0)
1969* */
1970int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *adapter)
1971{
1972 u32 op_mode;
1973 struct qlcnic_hardware_context *ahw = adapter->ahw;
1974
1975 qlcnic_get_func_no(adapter);
1976 op_mode = QLCRDX(ahw, QLC_83XX_DRV_OP_MODE);
1977
02feda17
RB		 1978 if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state))
1979 op_mode = QLC_83XX_DEFAULT_OPMODE;
1980
629263ac
SC		 1981 if (op_mode == QLC_83XX_DEFAULT_OPMODE) {
1982 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver;
1983 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry;
1984 } else {
1985 return -EIO;
1986 }
1987
1988 return 0;
1989}
1990
1991int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter)
1992{
1993 int err;
1994 struct qlcnic_info nic_info;
1995 struct qlcnic_hardware_context *ahw = adapter->ahw;
1996
1997 memset(&nic_info, 0, sizeof(struct qlcnic_info));
1998 err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
1999 if (err)
2000 return -EIO;
2001
2002 ahw->physical_port = (u8) nic_info.phys_port;
2003 ahw->switch_mode = nic_info.switch_mode;
2004 ahw->max_tx_ques = nic_info.max_tx_ques;
2005 ahw->max_rx_ques = nic_info.max_rx_ques;
2006 ahw->capabilities = nic_info.capabilities;
2007 ahw->max_mac_filters = nic_info.max_mac_filters;
2008 ahw->max_mtu = nic_info.max_mtu;
2009
02feda17
RB		 2010 /* VNIC mode is detected by BIT_23 in capabilities. This bit is also
2011 * set in case device is SRIOV capable. VNIC and SRIOV are mutually
2012 * exclusive. So in case of sriov capable device load driver in
2013 * default mode
2014 */
2015 if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state)) {
2016 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
2017 return ahw->nic_mode;
2018 }
2019
629263ac
SC		 2020 if (ahw->capabilities & BIT_23)
2021 ahw->nic_mode = QLC_83XX_VIRTUAL_NIC_MODE;
2022 else
2023 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
2024
2025 return ahw->nic_mode;
2026}
2027
02feda17 2028int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter)
629263ac
SC		 2029{
2030 int ret;
2031
2032 ret = qlcnic_83xx_get_nic_configuration(adapter);
2033 if (ret == -EIO)
2034 return -EIO;
2035
d71170fb
SC		 2036 if (ret == QLC_83XX_VIRTUAL_NIC_MODE) {
2037 if (qlcnic_83xx_config_vnic_opmode(adapter))
2038 return -EIO;
2039 } else if (ret == QLC_83XX_DEFAULT_MODE) {
629263ac
SC		 2040 if (qlcnic_83xx_config_default_opmode(adapter))
2041 return -EIO;
2042 }
2043
2044 return 0;
2045}
2046
2047static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter)
2048{
2049 struct qlcnic_hardware_context *ahw = adapter->ahw;
2050
2051 if (ahw->port_type == QLCNIC_XGBE) {
2052 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G;
2053 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
2054 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2055 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2056
2057 } else if (ahw->port_type == QLCNIC_GBE) {
2058 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G;
2059 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2060 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2061 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G;
2062 }
2063 adapter->num_txd = MAX_CMD_DESCRIPTORS;
2064 adapter->max_rds_rings = MAX_RDS_RINGS;
2065}
2066
2067static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter)
2068{
2069 int err = -EIO;
2070
4e60ac46 2071 qlcnic_83xx_get_minidump_template(adapter);
629263ac
SC		 2072 if (qlcnic_83xx_get_port_info(adapter))
2073 return err;
2074
2075 qlcnic_83xx_config_buff_descriptors(adapter);
2076 adapter->ahw->msix_supported = !!qlcnic_use_msi_x;
2077 adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
2078
2079 dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
2080 adapter->ahw->fw_hal_version);
2081
2082 return 0;
2083}
2084
2085#define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1))
2086static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter)
2087{
2088 struct qlcnic_cmd_args cmd;
2089 u32 presence_mask, audit_mask;
2090 int status;
2091
2092 presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
2093 audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
2094
2095 if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) {
b6b4316c
SS		 2096 status = qlcnic_alloc_mbx_args(&cmd, adapter,
2097 QLCNIC_CMD_STOP_NIC_FUNC);
2098 if (status)
2099 return;
2100
629263ac
SC		 2101 cmd.req.arg[1] = BIT_31;
2102 status = qlcnic_issue_cmd(adapter, &cmd);
2103 if (status)
2104 dev_err(&adapter->pdev->dev,
2105 "Failed to clean up the function resources\n");
2106 qlcnic_free_mbx_args(&cmd);
2107 }
2108}
2109
f8468331 2110int qlcnic_83xx_init(struct qlcnic_adapter *adapter, int pci_using_dac)
629263ac
SC		 2111{
2112 struct qlcnic_hardware_context *ahw = adapter->ahw;
2113
f8468331
RB		 2114 if (qlcnic_sriov_vf_check(adapter))
2115 return qlcnic_sriov_vf_init(adapter, pci_using_dac);
2116
629263ac
SC		 2117 if (qlcnic_83xx_check_hw_status(adapter))
2118 return -EIO;
2119
2120 /* Initilaize 83xx mailbox spinlock */
2121 spin_lock_init(&ahw->mbx_lock);
2122
2123 set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
2124 qlcnic_83xx_clear_function_resources(adapter);
2125
c70a3175
JK		 2126 INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
2127
d5fcff04
HM		 2128 /* register for NIC IDC AEN Events */
2129 qlcnic_83xx_register_nic_idc_func(adapter, 1);
2130
629263ac
SC		 2131 if (!qlcnic_83xx_read_flash_descriptor_table(adapter))
2132 qlcnic_83xx_read_flash_mfg_id(adapter);
2133
2134 if (qlcnic_83xx_idc_init(adapter))
2135 return -EIO;
2136
2137 /* Configure default, SR-IOV or Virtual NIC mode of operation */
2138 if (qlcnic_83xx_configure_opmode(adapter))
2139 return -EIO;
2140
2141 /* Perform operating mode specific initialization */
2142 if (adapter->nic_ops->init_driver(adapter))
2143 return -EIO;
2144
629263ac
SC		 2145 /* Periodically monitor device status */
2146 qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work);
2147
2148 return adapter->ahw->idc.err_code;
2149}
Linux 6.x block layer and io_uring tree(s)