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qlcnic: Fix endianess issue in firmware load from file operation
[linux-2.6-block.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic_83xx_init.c
CommitLineData
577ae39d
JK		 1/*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
f8468331 8#include "qlcnic_sriov.h"
629263ac
SC		 9#include "qlcnic.h"
10#include "qlcnic_hw.h"
11
81d0aeb0
SC		 12/* Reset template definitions */
13#define QLC_83XX_RESTART_TEMPLATE_SIZE 0x2000
14#define QLC_83XX_RESET_TEMPLATE_ADDR 0x4F0000
15#define QLC_83XX_RESET_SEQ_VERSION 0x0101
16
17#define QLC_83XX_OPCODE_NOP 0x0000
18#define QLC_83XX_OPCODE_WRITE_LIST 0x0001
19#define QLC_83XX_OPCODE_READ_WRITE_LIST 0x0002
20#define QLC_83XX_OPCODE_POLL_LIST 0x0004
21#define QLC_83XX_OPCODE_POLL_WRITE_LIST 0x0008
22#define QLC_83XX_OPCODE_READ_MODIFY_WRITE 0x0010
23#define QLC_83XX_OPCODE_SEQ_PAUSE 0x0020
24#define QLC_83XX_OPCODE_SEQ_END 0x0040
25#define QLC_83XX_OPCODE_TMPL_END 0x0080
26#define QLC_83XX_OPCODE_POLL_READ_LIST 0x0100
27
c0d79cd0
MC		 28/* EPORT control registers */
29#define QLC_83XX_RESET_CONTROL 0x28084E50
30#define QLC_83XX_RESET_REG 0x28084E60
31#define QLC_83XX_RESET_PORT0 0x28084E70
32#define QLC_83XX_RESET_PORT1 0x28084E80
33#define QLC_83XX_RESET_PORT2 0x28084E90
34#define QLC_83XX_RESET_PORT3 0x28084EA0
35#define QLC_83XX_RESET_SRESHIM 0x28084EB0
36#define QLC_83XX_RESET_EPGSHIM 0x28084EC0
37#define QLC_83XX_RESET_ETHERPCS 0x28084ED0
38
629263ac 39static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter);
629263ac
SC		 40static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev);
41static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter);
21041400 42static int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev);
43static int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *);
44static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *);
629263ac 45
81d0aeb0
SC		 46/* Template header */
47struct qlc_83xx_reset_hdr {
a96227e6 48#if defined(__LITTLE_ENDIAN)
81d0aeb0
SC		 49 u16 version;
50 u16 signature;
51 u16 size;
52 u16 entries;
53 u16 hdr_size;
54 u16 checksum;
55 u16 init_offset;
56 u16 start_offset;
a96227e6
SS		 57#elif defined(__BIG_ENDIAN)
58 u16 signature;
59 u16 version;
60 u16 entries;
61 u16 size;
62 u16 checksum;
63 u16 hdr_size;
64 u16 start_offset;
65 u16 init_offset;
66#endif
81d0aeb0
SC		 67} __packed;
68
69/* Command entry header. */
70struct qlc_83xx_entry_hdr {
a96227e6
SS		 71#if defined(__LITTLE_ENDIAN)
72 u16 cmd;
73 u16 size;
74 u16 count;
75 u16 delay;
76#elif defined(__BIG_ENDIAN)
77 u16 size;
78 u16 cmd;
79 u16 delay;
80 u16 count;
81#endif
81d0aeb0
SC		 82} __packed;
83
84/* Generic poll command */
85struct qlc_83xx_poll {
86 u32 mask;
87 u32 status;
88} __packed;
89
90/* Read modify write command */
91struct qlc_83xx_rmw {
92 u32 mask;
93 u32 xor_value;
94 u32 or_value;
a96227e6 95#if defined(__LITTLE_ENDIAN)
81d0aeb0
SC		 96 u8 shl;
97 u8 shr;
98 u8 index_a;
99 u8 rsvd;
a96227e6
SS		 100#elif defined(__BIG_ENDIAN)
101 u8 rsvd;
102 u8 index_a;
103 u8 shr;
104 u8 shl;
105#endif
81d0aeb0
SC		 106} __packed;
107
108/* Generic command with 2 DWORD */
109struct qlc_83xx_entry {
110 u32 arg1;
111 u32 arg2;
112} __packed;
113
114/* Generic command with 4 DWORD */
115struct qlc_83xx_quad_entry {
116 u32 dr_addr;
117 u32 dr_value;
118 u32 ar_addr;
119 u32 ar_value;
120} __packed;
629263ac
SC		 121static const char *const qlc_83xx_idc_states[] = {
122 "Unknown",
123 "Cold",
124 "Init",
125 "Ready",
126 "Need Reset",
127 "Need Quiesce",
128 "Failed",
129 "Quiesce"
130};
131
629263ac
SC		 132static int
133qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter)
134{
135 u32 val;
136
137 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
138 if ((val & 0xFFFF))
139 return 1;
140 else
141 return 0;
142}
143
144static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter)
145{
146 u32 cur, prev;
147 cur = adapter->ahw->idc.curr_state;
148 prev = adapter->ahw->idc.prev_state;
149
150 dev_info(&adapter->pdev->dev,
151 "current state = %s, prev state = %s\n",
152 adapter->ahw->idc.name[cur],
153 adapter->ahw->idc.name[prev]);
154}
155
156static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter,
157 u8 mode, int lock)
158{
159 u32 val;
160 int seconds;
161
162 if (lock) {
163 if (qlcnic_83xx_lock_driver(adapter))
164 return -EBUSY;
165 }
166
f036e4f4
RB		 167 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
168 val |= (adapter->portnum & 0xf);
629263ac
SC		 169 val |= mode << 7;
170 if (mode)
171 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
172 else
173 seconds = jiffies / HZ;
174
175 val |= seconds << 8;
176 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val);
177 adapter->ahw->idc.sec_counter = jiffies / HZ;
178
179 if (lock)
180 qlcnic_83xx_unlock_driver(adapter);
181
182 return 0;
183}
184
185static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter)
186{
187 u32 val;
188
189 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION);
190 val = val & ~(0x3 << (adapter->portnum * 2));
191 val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2));
192 QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val);
193}
194
195static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter,
196 int lock)
197{
198 u32 val;
199
200 if (lock) {
201 if (qlcnic_83xx_lock_driver(adapter))
202 return -EBUSY;
203 }
204
205 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
206 val = val & ~0xFF;
207 val = val | QLC_83XX_IDC_MAJOR_VERSION;
208 QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val);
209
210 if (lock)
211 qlcnic_83xx_unlock_driver(adapter);
212
213 return 0;
214}
215
216static int
217qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter,
218 int status, int lock)
219{
220 u32 val;
221
222 if (lock) {
223 if (qlcnic_83xx_lock_driver(adapter))
224 return -EBUSY;
225 }
226
227 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
228
229 if (status)
230 val = val | (1 << adapter->portnum);
231 else
232 val = val & ~(1 << adapter->portnum);
233
234 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
235 qlcnic_83xx_idc_update_minor_version(adapter);
236
237 if (lock)
238 qlcnic_83xx_unlock_driver(adapter);
239
240 return 0;
241}
242
243static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter)
244{
245 u32 val;
246 u8 version;
247
248 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
249 version = val & 0xFF;
250
251 if (version != QLC_83XX_IDC_MAJOR_VERSION) {
252 dev_info(&adapter->pdev->dev,
253 "%s:mismatch. version 0x%x, expected version 0x%x\n",
254 __func__, version, QLC_83XX_IDC_MAJOR_VERSION);
255 return -EIO;
256 }
257
258 return 0;
259}
260
261static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter,
262 int lock)
263{
264 u32 val;
265
266 if (lock) {
267 if (qlcnic_83xx_lock_driver(adapter))
268 return -EBUSY;
269 }
270
271 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0);
272 /* Clear gracefull reset bit */
273 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
274 val &= ~QLC_83XX_IDC_GRACEFULL_RESET;
275 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
276
277 if (lock)
278 qlcnic_83xx_unlock_driver(adapter);
279
280 return 0;
281}
282
283static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter,
284 int flag, int lock)
285{
286 u32 val;
287
288 if (lock) {
289 if (qlcnic_83xx_lock_driver(adapter))
290 return -EBUSY;
291 }
292
293 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
294 if (flag)
295 val = val | (1 << adapter->portnum);
296 else
297 val = val & ~(1 << adapter->portnum);
298 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val);
299
300 if (lock)
301 qlcnic_83xx_unlock_driver(adapter);
302
303 return 0;
304}
305
306static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter,
307 int time_limit)
308{
309 u64 seconds;
310
311 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
312 if (seconds <= time_limit)
313 return 0;
314 else
315 return -EBUSY;
316}
317
318/**
319 * qlcnic_83xx_idc_check_reset_ack_reg
320 *
321 * @adapter: adapter structure
322 *
323 * Check ACK wait limit and clear the functions which failed to ACK
324 *
325 * Return 0 if all functions have acknowledged the reset request.
326 **/
327static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter)
328{
329 int timeout;
330 u32 ack, presence, val;
331
332 timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
333 ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
334 presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
335 dev_info(&adapter->pdev->dev,
336 "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence);
337 if (!((ack & presence) == presence)) {
338 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) {
339 /* Clear functions which failed to ACK */
340 dev_info(&adapter->pdev->dev,
341 "%s: ACK wait exceeds time limit\n", __func__);
342 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
343 val = val & ~(ack ^ presence);
344 if (qlcnic_83xx_lock_driver(adapter))
345 return -EBUSY;
346 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
347 dev_info(&adapter->pdev->dev,
348 "%s: updated drv presence reg = 0x%x\n",
349 __func__, val);
350 qlcnic_83xx_unlock_driver(adapter);
351 return 0;
352
353 } else {
354 return 1;
355 }
356 } else {
357 dev_info(&adapter->pdev->dev,
358 "%s: Reset ACK received from all functions\n",
359 __func__);
360 return 0;
361 }
362}
363
364/**
365 * qlcnic_83xx_idc_tx_soft_reset
366 *
367 * @adapter: adapter structure
368 *
369 * Handle context deletion and recreation request from transmit routine
370 *
371 * Returns -EBUSY or Success (0)
372 *
373 **/
374static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter)
375{
376 struct net_device *netdev = adapter->netdev;
377
378 if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
379 return -EBUSY;
380
381 netif_device_detach(netdev);
382 qlcnic_down(adapter, netdev);
383 qlcnic_up(adapter, netdev);
384 netif_device_attach(netdev);
385 clear_bit(__QLCNIC_RESETTING, &adapter->state);
95b3890a 386 netdev_info(adapter->netdev, "%s: soft reset complete.\n", __func__);
629263ac 387
629263ac
SC		 388 return 0;
389}
390
391/**
392 * qlcnic_83xx_idc_detach_driver
393 *
394 * @adapter: adapter structure
395 * Detach net interface, stop TX and cleanup resources before the HW reset.
396 * Returns: None
397 *
398 **/
399static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter)
400{
401 int i;
402 struct net_device *netdev = adapter->netdev;
403
404 netif_device_detach(netdev);
068a8d19 405 qlcnic_83xx_detach_mailbox_work(adapter);
f036e4f4 406
629263ac 407 /* Disable mailbox interrupt */
f036e4f4 408 qlcnic_83xx_disable_mbx_intr(adapter);
629263ac
SC		 409 qlcnic_down(adapter, netdev);
410 for (i = 0; i < adapter->ahw->num_msix; i++) {
411 adapter->ahw->intr_tbl[i].id = i;
412 adapter->ahw->intr_tbl[i].enabled = 0;
413 adapter->ahw->intr_tbl[i].src = 0;
414 }
f036e4f4
RB		 415
416 if (qlcnic_sriov_pf_check(adapter))
417 qlcnic_sriov_pf_reset(adapter);
629263ac
SC		 418}
419
420/**
421 * qlcnic_83xx_idc_attach_driver
422 *
423 * @adapter: adapter structure
424 *
425 * Re-attach and re-enable net interface
426 * Returns: None
427 *
428 **/
429static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter)
430{
431 struct net_device *netdev = adapter->netdev;
432
433 if (netif_running(netdev)) {
434 if (qlcnic_up(adapter, netdev))
435 goto done;
436 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
437 }
438done:
439 netif_device_attach(netdev);
629263ac
SC		 440}
441
442static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter,
443 int lock)
444{
445 if (lock) {
446 if (qlcnic_83xx_lock_driver(adapter))
447 return -EBUSY;
448 }
449
450 qlcnic_83xx_idc_clear_registers(adapter, 0);
451 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED);
452 if (lock)
453 qlcnic_83xx_unlock_driver(adapter);
454
455 qlcnic_83xx_idc_log_state_history(adapter);
456 dev_info(&adapter->pdev->dev, "Device will enter failed state\n");
457
458 return 0;
459}
460
461static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter,
462 int lock)
463{
464 if (lock) {
465 if (qlcnic_83xx_lock_driver(adapter))
466 return -EBUSY;
467 }
468
469 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT);
470
471 if (lock)
472 qlcnic_83xx_unlock_driver(adapter);
473
474 return 0;
475}
476
477static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter,
478 int lock)
479{
480 if (lock) {
481 if (qlcnic_83xx_lock_driver(adapter))
482 return -EBUSY;
483 }
484
485 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
486 QLC_83XX_IDC_DEV_NEED_QUISCENT);
487
488 if (lock)
489 qlcnic_83xx_unlock_driver(adapter);
490
491 return 0;
492}
493
494static int
495qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock)
496{
497 if (lock) {
498 if (qlcnic_83xx_lock_driver(adapter))
499 return -EBUSY;
500 }
501
502 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
503 QLC_83XX_IDC_DEV_NEED_RESET);
504
505 if (lock)
506 qlcnic_83xx_unlock_driver(adapter);
507
508 return 0;
509}
510
511static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter,
512 int lock)
513{
514 if (lock) {
515 if (qlcnic_83xx_lock_driver(adapter))
516 return -EBUSY;
517 }
518
519 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY);
520 if (lock)
521 qlcnic_83xx_unlock_driver(adapter);
522
523 return 0;
524}
525
526/**
527 * qlcnic_83xx_idc_find_reset_owner_id
528 *
529 * @adapter: adapter structure
530 *
531 * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE.
532 * Within the same class, function with lowest PCI ID assumes ownership
533 *
534 * Returns: reset owner id or failure indication (-EIO)
535 *
536 **/
537static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter)
538{
539 u32 reg, reg1, reg2, i, j, owner, class;
540
541 reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1);
542 reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2);
543 owner = QLCNIC_TYPE_NIC;
544 i = 0;
545 j = 0;
546 reg = reg1;
547
548 do {
549 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3);
550 if (class == owner)
551 break;
552 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) {
553 reg = reg2;
554 j = 0;
555 } else {
556 j++;
557 }
558
559 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) {
560 if (owner == QLCNIC_TYPE_NIC)
561 owner = QLCNIC_TYPE_ISCSI;
562 else if (owner == QLCNIC_TYPE_ISCSI)
563 owner = QLCNIC_TYPE_FCOE;
564 else if (owner == QLCNIC_TYPE_FCOE)
565 return -EIO;
566 reg = reg1;
567 j = 0;
568 i = 0;
569 }
570 } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS);
571
572 return i;
573}
574
575static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock)
576{
577 int ret = 0;
578
579 ret = qlcnic_83xx_restart_hw(adapter);
580
581 if (ret) {
582 qlcnic_83xx_idc_enter_failed_state(adapter, lock);
583 } else {
584 qlcnic_83xx_idc_clear_registers(adapter, lock);
585 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock);
586 }
587
588 return ret;
589}
590
591static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter)
592{
593 u32 status;
594
595 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1);
596
597 if (status & QLCNIC_RCODE_FATAL_ERROR) {
598 dev_err(&adapter->pdev->dev,
599 "peg halt status1=0x%x\n", status);
600 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) {
601 dev_err(&adapter->pdev->dev,
602 "On board active cooling fan failed. "
603 "Device has been halted.\n");
604 dev_err(&adapter->pdev->dev,
605 "Replace the adapter.\n");
606 return -EIO;
607 }
608 }
609
610 return 0;
611}
612
486a5bc7 613int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter)
629263ac 614{
f036e4f4
RB		 615 int err;
616
068a8d19
MC		 617 qlcnic_83xx_reinit_mbx_work(adapter->ahw->mailbox);
618 qlcnic_83xx_enable_mbx_interrupt(adapter);
619
9b0fff2a 620 qlcnic_83xx_initialize_nic(adapter, 1);
d5fcff04 621
f036e4f4
RB		 622 err = qlcnic_sriov_pf_reinit(adapter);
623 if (err)
624 return err;
625
e5c4e6c6 626 qlcnic_83xx_enable_mbx_interrupt(adapter);
629263ac
SC		 627
628 if (qlcnic_83xx_configure_opmode(adapter)) {
629 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
630 return -EIO;
631 }
632
633 if (adapter->nic_ops->init_driver(adapter)) {
634 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
635 return -EIO;
636 }
637
24866d15
HM		 638 if (adapter->portnum == 0)
639 qlcnic_set_drv_version(adapter);
14d385b9 640
1de899d3 641 qlcnic_dcb_get_info(adapter->dcb);
629263ac
SC		 642 qlcnic_83xx_idc_attach_driver(adapter);
643
644 return 0;
645}
646
647static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter)
648{
536faa61
SC		 649 struct qlcnic_hardware_context *ahw = adapter->ahw;
650
629263ac 651 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1);
629263ac
SC		 652 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
653 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
536faa61
SC		 654
655 ahw->idc.quiesce_req = 0;
656 ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
657 ahw->idc.err_code = 0;
658 ahw->idc.collect_dump = 0;
659 ahw->reset_context = 0;
660 adapter->tx_timeo_cnt = 0;
099907fa 661 ahw->idc.delay_reset = 0;
536faa61
SC		 662
663 clear_bit(__QLCNIC_RESETTING, &adapter->state);
629263ac
SC		 664}
665
666/**
667 * qlcnic_83xx_idc_ready_state_entry
668 *
669 * @adapter: adapter structure
670 *
671 * Perform ready state initialization, this routine will get invoked only
672 * once from READY state.
673 *
674 * Returns: Error code or Success(0)
675 *
676 **/
677int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter)
678{
679 struct qlcnic_hardware_context *ahw = adapter->ahw;
680
681 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) {
682 qlcnic_83xx_idc_update_idc_params(adapter);
683 /* Re-attach the device if required */
684 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
685 (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) {
686 if (qlcnic_83xx_idc_reattach_driver(adapter))
687 return -EIO;
688 }
689 }
690
691 return 0;
692}
693
d71170fb
SC		 694/**
695 * qlcnic_83xx_idc_vnic_pf_entry
696 *
697 * @adapter: adapter structure
698 *
699 * Ensure vNIC mode privileged function starts only after vNIC mode is
700 * enabled by management function.
701 * If vNIC mode is ready, start initialization.
702 *
703 * Returns: -EIO or 0
704 *
705 **/
706int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter)
707{
708 u32 state;
709 struct qlcnic_hardware_context *ahw = adapter->ahw;
710
711 /* Privileged function waits till mgmt function enables VNIC mode */
712 state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE);
713 if (state != QLCNIC_DEV_NPAR_OPER) {
714 if (!ahw->idc.vnic_wait_limit--) {
715 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
716 return -EIO;
717 }
718 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n");
719 return -EIO;
720
721 } else {
722 /* Perform one time initialization from ready state */
723 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) {
724 qlcnic_83xx_idc_update_idc_params(adapter);
725
726 /* If the previous state is UNKNOWN, device will be
727 already attached properly by Init routine*/
728 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) {
729 if (qlcnic_83xx_idc_reattach_driver(adapter))
730 return -EIO;
731 }
732 adapter->ahw->idc.vnic_state = QLCNIC_DEV_NPAR_OPER;
733 dev_info(&adapter->pdev->dev, "vNIC mode enabled\n");
734 }
735 }
736
737 return 0;
738}
739
629263ac
SC		 740static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter)
741{
742 adapter->ahw->idc.err_code = -EIO;
743 dev_err(&adapter->pdev->dev,
744 "%s: Device in unknown state\n", __func__);
30fa15f6 745 clear_bit(__QLCNIC_RESETTING, &adapter->state);
629263ac
SC		 746 return 0;
747}
748
749/**
750 * qlcnic_83xx_idc_cold_state
751 *
752 * @adapter: adapter structure
753 *
754 * If HW is up and running device will enter READY state.
755 * If firmware image from host needs to be loaded, device is
756 * forced to start with the file firmware image.
757 *
758 * Returns: Error code or Success(0)
759 *
760 **/
761static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter)
762{
763 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0);
764 qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0);
765
766 if (qlcnic_load_fw_file) {
767 qlcnic_83xx_idc_restart_hw(adapter, 0);
768 } else {
769 if (qlcnic_83xx_check_hw_status(adapter)) {
770 qlcnic_83xx_idc_enter_failed_state(adapter, 0);
771 return -EIO;
772 } else {
773 qlcnic_83xx_idc_enter_ready_state(adapter, 0);
774 }
775 }
776 return 0;
777}
778
779/**
780 * qlcnic_83xx_idc_init_state
781 *
782 * @adapter: adapter structure
783 *
784 * Reset owner will restart the device from this state.
785 * Device will enter failed state if it remains
786 * in this state for more than DEV_INIT time limit.
787 *
788 * Returns: Error code or Success(0)
789 *
790 **/
791static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter)
792{
793 int timeout, ret = 0;
794 u32 owner;
795
796 timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
797 if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) {
798 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
799 if (adapter->ahw->pci_func == owner)
800 ret = qlcnic_83xx_idc_restart_hw(adapter, 1);
801 } else {
802 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout);
629263ac
SC		 803 }
804
805 return ret;
806}
807
808/**
809 * qlcnic_83xx_idc_ready_state
810 *
811 * @adapter: adapter structure
812 *
813 * Perform IDC protocol specicifed actions after monitoring device state and
814 * events.
815 *
816 * Returns: Error code or Success(0)
817 *
818 **/
819static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter)
820{
629263ac 821 struct qlcnic_hardware_context *ahw = adapter->ahw;
068a8d19 822 struct qlcnic_mailbox *mbx = ahw->mailbox;
629263ac 823 int ret = 0;
068a8d19 824 u32 val;
629263ac
SC		 825
826 /* Perform NIC configuration based ready state entry actions */
827 if (ahw->idc.state_entry(adapter))
828 return -EIO;
829
830 if (qlcnic_check_temp(adapter)) {
831 if (ahw->temp == QLCNIC_TEMP_PANIC) {
832 qlcnic_83xx_idc_check_fan_failure(adapter);
833 dev_err(&adapter->pdev->dev,
834 "Error: device temperature %d above limits\n",
835 adapter->ahw->temp);
068a8d19 836 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
629263ac
SC		 837 set_bit(__QLCNIC_RESETTING, &adapter->state);
838 qlcnic_83xx_idc_detach_driver(adapter);
839 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
840 return -EIO;
841 }
842 }
843
844 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
845 ret = qlcnic_83xx_check_heartbeat(adapter);
846 if (ret) {
847 adapter->flags |= QLCNIC_FW_HANG;
848 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
068a8d19 849 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
629263ac
SC		 850 set_bit(__QLCNIC_RESETTING, &adapter->state);
851 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
891e71b1 852 } else {
30fa15f6
MC		 853 netdev_info(adapter->netdev, "%s: Auto firmware recovery is disabled\n",
854 __func__);
855 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
629263ac
SC		 856 }
857 return -EIO;
858 }
859
860 if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) {
068a8d19
MC		 861 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
862
629263ac
SC		 863 /* Move to need reset state and prepare for reset */
864 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
865 return ret;
866 }
867
868 /* Check for soft reset request */
869 if (ahw->reset_context &&
870 !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
536faa61 871 adapter->ahw->reset_context = 0;
629263ac
SC		 872 qlcnic_83xx_idc_tx_soft_reset(adapter);
873 return ret;
874 }
875
876 /* Move to need quiesce state if requested */
877 if (adapter->ahw->idc.quiesce_req) {
878 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1);
879 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
880 return ret;
881 }
882
883 return ret;
884}
885
886/**
887 * qlcnic_83xx_idc_need_reset_state
888 *
889 * @adapter: adapter structure
890 *
891 * Device will remain in this state until:
892 * Reset request ACK's are recieved from all the functions
893 * Wait time exceeds max time limit
894 *
895 * Returns: Error code or Success(0)
896 *
897 **/
898static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter)
899{
068a8d19 900 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
629263ac
SC		 901 int ret = 0;
902
903 if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) {
629263ac
SC		 904 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
905 set_bit(__QLCNIC_RESETTING, &adapter->state);
068a8d19 906 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
34e8c406 907 if (adapter->ahw->nic_mode == QLCNIC_VNIC_MODE)
d71170fb 908 qlcnic_83xx_disable_vnic_mode(adapter, 1);
099907fa
SC		 909
910 if (qlcnic_check_diag_status(adapter)) {
911 dev_info(&adapter->pdev->dev,
912 "%s: Wait for diag completion\n", __func__);
913 adapter->ahw->idc.delay_reset = 1;
914 return 0;
915 } else {
916 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
917 qlcnic_83xx_idc_detach_driver(adapter);
918 }
629263ac
SC		 919 }
920
099907fa 921 if (qlcnic_check_diag_status(adapter)) {
629263ac 922 dev_info(&adapter->pdev->dev,
099907fa
SC		 923 "%s: Wait for diag completion\n", __func__);
924 return -1;
925 } else {
926 if (adapter->ahw->idc.delay_reset) {
927 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
928 qlcnic_83xx_idc_detach_driver(adapter);
929 adapter->ahw->idc.delay_reset = 0;
930 }
931
932 /* Check for ACK from other functions */
933 ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter);
934 if (ret) {
935 dev_info(&adapter->pdev->dev,
936 "%s: Waiting for reset ACK\n", __func__);
937 return -1;
938 }
629263ac
SC		 939 }
940
941 /* Transit to INIT state and restart the HW */
942 qlcnic_83xx_idc_enter_init_state(adapter, 1);
943
944 return ret;
945}
946
947static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter)
948{
949 dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__);
950 return 0;
951}
952
30fa15f6 953static void qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter)
629263ac 954{
30fa15f6
MC		 955 struct qlcnic_hardware_context *ahw = adapter->ahw;
956 u32 val, owner;
957
958 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
959 if (val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) {
960 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
961 if (ahw->pci_func == owner) {
962 qlcnic_83xx_stop_hw(adapter);
963 qlcnic_dump_fw(adapter);
964 }
965 }
966
967 netdev_warn(adapter->netdev, "%s: Reboot will be required to recover the adapter!!\n",
968 __func__);
536faa61 969 clear_bit(__QLCNIC_RESETTING, &adapter->state);
30fa15f6 970 ahw->idc.err_code = -EIO;
629263ac 971
30fa15f6 972 return;
629263ac
SC		 973}
974
975static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter)
976{
977 dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__);
978 return 0;
979}
980
981static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter,
982 u32 state)
983{
984 u32 cur, prev, next;
985
986 cur = adapter->ahw->idc.curr_state;
987 prev = adapter->ahw->idc.prev_state;
988 next = state;
989
990 if ((next < QLC_83XX_IDC_DEV_COLD) ||
991 (next > QLC_83XX_IDC_DEV_QUISCENT)) {
992 dev_err(&adapter->pdev->dev,
993 "%s: curr %d, prev %d, next state %d is invalid\n",
994 __func__, cur, prev, state);
995 return 1;
996 }
997
998 if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) &&
999 (prev == QLC_83XX_IDC_DEV_UNKNOWN)) {
1000 if ((next != QLC_83XX_IDC_DEV_COLD) &&
1001 (next != QLC_83XX_IDC_DEV_READY)) {
1002 dev_err(&adapter->pdev->dev,
1003 "%s: failed, cur %d prev %d next %d\n",
1004 __func__, cur, prev, next);
1005 return 1;
1006 }
1007 }
1008
1009 if (next == QLC_83XX_IDC_DEV_INIT) {
1010 if ((prev != QLC_83XX_IDC_DEV_INIT) &&
1011 (prev != QLC_83XX_IDC_DEV_COLD) &&
1012 (prev != QLC_83XX_IDC_DEV_NEED_RESET)) {
1013 dev_err(&adapter->pdev->dev,
1014 "%s: failed, cur %d prev %d next %d\n",
1015 __func__, cur, prev, next);
1016 return 1;
1017 }
1018 }
1019
1020 return 0;
1021}
1022
7f1f6056 1023#ifdef CONFIG_QLCNIC_VXLAN
2b3d7b75
SS		 1024#define QLC_83XX_ENCAP_TYPE_VXLAN BIT_1
1025#define QLC_83XX_MATCH_ENCAP_ID BIT_2
1026#define QLC_83XX_SET_VXLAN_UDP_DPORT BIT_3
1027#define QLC_83XX_VXLAN_UDP_DPORT(PORT) ((PORT & 0xffff) << 16)
1028
1029#define QLCNIC_ENABLE_INGRESS_ENCAP_PARSING 1
1030#define QLCNIC_DISABLE_INGRESS_ENCAP_PARSING 0
1031
1032static int qlcnic_set_vxlan_port(struct qlcnic_adapter *adapter)
1033{
1034 u16 port = adapter->ahw->vxlan_port;
1035 struct qlcnic_cmd_args cmd;
1036 int ret = 0;
1037
1038 memset(&cmd, 0, sizeof(cmd));
1039
1040 ret = qlcnic_alloc_mbx_args(&cmd, adapter,
1041 QLCNIC_CMD_INIT_NIC_FUNC);
1042 if (ret)
1043 return ret;
1044
1045 cmd.req.arg[1] = QLC_83XX_MULTI_TENANCY_INFO;
1046 cmd.req.arg[2] = QLC_83XX_ENCAP_TYPE_VXLAN |
1047 QLC_83XX_SET_VXLAN_UDP_DPORT |
1048 QLC_83XX_VXLAN_UDP_DPORT(port);
1049
1050 ret = qlcnic_issue_cmd(adapter, &cmd);
1051 if (ret)
1052 netdev_err(adapter->netdev,
1053 "Failed to set VXLAN port %d in adapter\n",
1054 port);
1055
1056 qlcnic_free_mbx_args(&cmd);
1057
1058 return ret;
1059}
1060
1061static int qlcnic_set_vxlan_parsing(struct qlcnic_adapter *adapter,
1062 bool state)
1063{
1064 u16 vxlan_port = adapter->ahw->vxlan_port;
1065 struct qlcnic_cmd_args cmd;
1066 int ret = 0;
1067
1068 memset(&cmd, 0, sizeof(cmd));
1069
1070 ret = qlcnic_alloc_mbx_args(&cmd, adapter,
1071 QLCNIC_CMD_SET_INGRESS_ENCAP);
1072 if (ret)
1073 return ret;
1074
1075 cmd.req.arg[1] = state ? QLCNIC_ENABLE_INGRESS_ENCAP_PARSING :
1076 QLCNIC_DISABLE_INGRESS_ENCAP_PARSING;
1077
1078 ret = qlcnic_issue_cmd(adapter, &cmd);
1079 if (ret)
1080 netdev_err(adapter->netdev,
1081 "Failed to %s VXLAN parsing for port %d\n",
1082 state ? "enable" : "disable", vxlan_port);
1083 else
1084 netdev_info(adapter->netdev,
1085 "%s VXLAN parsing for port %d\n",
1086 state ? "Enabled" : "Disabled", vxlan_port);
1087
1088 qlcnic_free_mbx_args(&cmd);
1089
1090 return ret;
1091}
7f1f6056 1092#endif
2b3d7b75 1093
629263ac
SC		 1094static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter)
1095{
1096 if (adapter->fhash.fnum)
1097 qlcnic_prune_lb_filters(adapter);
2b3d7b75 1098
7f1f6056 1099#ifdef CONFIG_QLCNIC_VXLAN
2b3d7b75
SS		 1100 if (adapter->flags & QLCNIC_ADD_VXLAN_PORT) {
1101 if (qlcnic_set_vxlan_port(adapter))
1102 return;
1103
1104 if (qlcnic_set_vxlan_parsing(adapter, true))
1105 return;
1106
1107 adapter->flags &= ~QLCNIC_ADD_VXLAN_PORT;
1108 } else if (adapter->flags & QLCNIC_DEL_VXLAN_PORT) {
1109 if (qlcnic_set_vxlan_parsing(adapter, false))
1110 return;
1111
7f1f6056 1112 adapter->ahw->vxlan_port = 0;
2b3d7b75
SS		 1113 adapter->flags &= ~QLCNIC_DEL_VXLAN_PORT;
1114 }
7f1f6056 1115#endif
629263ac
SC		 1116}
1117
1118/**
1119 * qlcnic_83xx_idc_poll_dev_state
1120 *
1121 * @work: kernel work queue structure used to schedule the function
1122 *
1123 * Poll device state periodically and perform state specific
1124 * actions defined by Inter Driver Communication (IDC) protocol.
1125 *
1126 * Returns: None
1127 *
1128 **/
1129void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work)
1130{
1131 struct qlcnic_adapter *adapter;
1132 u32 state;
1133
1134 adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
1135 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1136
1137 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1138 qlcnic_83xx_idc_log_state_history(adapter);
1139 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1140 } else {
1141 adapter->ahw->idc.curr_state = state;
1142 }
1143
1144 switch (adapter->ahw->idc.curr_state) {
1145 case QLC_83XX_IDC_DEV_READY:
1146 qlcnic_83xx_idc_ready_state(adapter);
1147 break;
1148 case QLC_83XX_IDC_DEV_NEED_RESET:
1149 qlcnic_83xx_idc_need_reset_state(adapter);
1150 break;
1151 case QLC_83XX_IDC_DEV_NEED_QUISCENT:
1152 qlcnic_83xx_idc_need_quiesce_state(adapter);
1153 break;
1154 case QLC_83XX_IDC_DEV_FAILED:
1155 qlcnic_83xx_idc_failed_state(adapter);
1156 return;
1157 case QLC_83XX_IDC_DEV_INIT:
1158 qlcnic_83xx_idc_init_state(adapter);
1159 break;
1160 case QLC_83XX_IDC_DEV_QUISCENT:
1161 qlcnic_83xx_idc_quiesce_state(adapter);
1162 break;
1163 default:
1164 qlcnic_83xx_idc_unknown_state(adapter);
1165 return;
1166 }
1167 adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state;
1168 qlcnic_83xx_periodic_tasks(adapter);
1169
1170 /* Re-schedule the function */
1171 if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status))
1172 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
1173 adapter->ahw->idc.delay);
1174}
1175
1176static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter)
1177{
1178 u32 idc_params, val;
1179
1180 if (qlcnic_83xx_lockless_flash_read32(adapter,
1181 QLC_83XX_IDC_FLASH_PARAM_ADDR,
1182 (u8 *)&idc_params, 1)) {
1183 dev_info(&adapter->pdev->dev,
1184 "%s:failed to get IDC params from flash\n", __func__);
1185 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
1186 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
1187 } else {
1188 adapter->dev_init_timeo = idc_params & 0xFFFF;
1189 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF);
1190 }
1191
1192 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1193 adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN;
1194 adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
1195 adapter->ahw->idc.err_code = 0;
1196 adapter->ahw->idc.collect_dump = 0;
1197 adapter->ahw->idc.name = (char **)qlc_83xx_idc_states;
1198
1199 clear_bit(__QLCNIC_RESETTING, &adapter->state);
629263ac
SC		 1200 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1201
1202 /* Check if reset recovery is disabled */
1203 if (!qlcnic_auto_fw_reset) {
1204 /* Propagate do not reset request to other functions */
1205 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1206 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1207 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1208 }
1209}
1210
1211static int
1212qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter)
1213{
1214 u32 state, val;
1215
1216 if (qlcnic_83xx_lock_driver(adapter))
1217 return -EIO;
1218
1219 /* Clear driver lock register */
1220 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0);
1221 if (qlcnic_83xx_idc_update_major_version(adapter, 0)) {
1222 qlcnic_83xx_unlock_driver(adapter);
1223 return -EIO;
1224 }
1225
1226 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1227 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1228 qlcnic_83xx_unlock_driver(adapter);
1229 return -EIO;
1230 }
1231
1232 if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) {
1233 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
1234 QLC_83XX_IDC_DEV_COLD);
1235 state = QLC_83XX_IDC_DEV_COLD;
1236 }
1237
1238 adapter->ahw->idc.curr_state = state;
1239 /* First to load function should cold boot the device */
1240 if (state == QLC_83XX_IDC_DEV_COLD)
1241 qlcnic_83xx_idc_cold_state_handler(adapter);
1242
1243 /* Check if reset recovery is enabled */
1244 if (qlcnic_auto_fw_reset) {
1245 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1246 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1247 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1248 }
1249
1250 qlcnic_83xx_unlock_driver(adapter);
1251
1252 return 0;
1253}
1254
486a5bc7 1255int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter)
629263ac 1256{
81d0aeb0
SC		 1257 int ret = -EIO;
1258
629263ac
SC		 1259 qlcnic_83xx_setup_idc_parameters(adapter);
1260
81d0aeb0
SC		 1261 if (qlcnic_83xx_get_reset_instruction_template(adapter))
1262 return ret;
1263
629263ac
SC		 1264 if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) {
1265 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter))
1266 return -EIO;
1267 } else {
1268 if (qlcnic_83xx_idc_check_major_version(adapter))
1269 return -EIO;
1270 }
1271
1272 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
1273
1274 return 0;
1275}
1276
1277void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter)
1278{
1279 int id;
1280 u32 val;
1281
1282 while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1283 usleep_range(10000, 11000);
1284
1285 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1286 id = id & 0xFF;
1287
1288 if (id == adapter->portnum) {
1289 dev_err(&adapter->pdev->dev,
1290 "%s: wait for lock recovery.. %d\n", __func__, id);
1291 msleep(20);
1292 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1293 id = id & 0xFF;
1294 }
1295
1296 /* Clear driver presence bit */
1297 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
1298 val = val & ~(1 << adapter->portnum);
1299 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
1300 clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1301 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1302
1303 cancel_delayed_work_sync(&adapter->fw_work);
1304}
1305
1306void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key)
1307{
1308 u32 val;
1309
068a8d19
MC		 1310 if (qlcnic_sriov_vf_check(adapter))
1311 return;
1312
629263ac
SC		 1313 if (qlcnic_83xx_lock_driver(adapter)) {
1314 dev_err(&adapter->pdev->dev,
1315 "%s:failed, please retry\n", __func__);
1316 return;
1317 }
1318
1319 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
30fa15f6
MC		 1320 if (val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) {
1321 netdev_info(adapter->netdev, "%s: Auto firmware recovery is disabled\n",
1322 __func__);
1323 qlcnic_83xx_idc_enter_failed_state(adapter, 0);
629263ac
SC		 1324 qlcnic_83xx_unlock_driver(adapter);
1325 return;
1326 }
1327
1328 if (key == QLCNIC_FORCE_FW_RESET) {
1329 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1330 val = val | QLC_83XX_IDC_GRACEFULL_RESET;
1331 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1332 } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) {
1333 adapter->ahw->idc.collect_dump = 1;
1334 }
1335
1336 qlcnic_83xx_unlock_driver(adapter);
1337 return;
1338}
1339
1340static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter)
1341{
1342 u8 *p_cache;
1343 u32 src, size;
1344 u64 dest;
1345 int ret = -EIO;
1346
1347 src = QLC_83XX_BOOTLOADER_FLASH_ADDR;
1348 dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR);
1349 size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE);
1350
1351 /* alignment check */
1352 if (size & 0xF)
1353 size = (size + 16) & ~0xF;
1354
3fc38e26 1355 p_cache = vzalloc(size);
b2adaca9 1356 if (p_cache == NULL)
629263ac 1357 return -ENOMEM;
b2adaca9 1358
629263ac
SC		 1359 ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache,
1360 size / sizeof(u32));
1361 if (ret) {
3fc38e26 1362 vfree(p_cache);
629263ac
SC		 1363 return ret;
1364 }
1365 /* 16 byte write to MS memory */
8d37ba02
SS		 1366 ret = qlcnic_ms_mem_write128(adapter, dest, (u32 *)p_cache,
1367 size / 16);
629263ac 1368 if (ret) {
3fc38e26 1369 vfree(p_cache);
629263ac
SC		 1370 return ret;
1371 }
3fc38e26 1372 vfree(p_cache);
629263ac
SC		 1373
1374 return ret;
1375}
1376
1377static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter)
1378{
7000078a
PP		 1379 struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info;
1380 const struct firmware *fw = fw_info->fw;
3d8623e6 1381 u32 dest, *p_cache, *temp;
7000078a 1382 int i, ret = -EIO;
3d8623e6 1383 __le32 *temp_le;
629263ac
SC		 1384 u8 data[16];
1385 size_t size;
7000078a 1386 u64 addr;
629263ac 1387
3d8623e6
SS		 1388 temp = kzalloc(fw->size, GFP_KERNEL);
1389 if (!temp) {
1390 release_firmware(fw);
1391 fw_info->fw = NULL;
1392 return -ENOMEM;
1393 }
1394
1395 temp_le = (__le32 *)fw->data;
1396
1397 /* FW image in file is in little endian, swap the data to nullify
1398 * the effect of writel() operation on big endian platform.
1399 */
1400 for (i = 0; i < fw->size / sizeof(u32); i++)
1401 temp[i] = __le32_to_cpu(temp_le[i]);
1402
629263ac 1403 dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR);
7000078a 1404 size = (fw->size & ~0xF);
3d8623e6 1405 p_cache = temp;
629263ac
SC		 1406 addr = (u64)dest;
1407
8d37ba02
SS		 1408 ret = qlcnic_ms_mem_write128(adapter, addr,
1409 p_cache, size / 16);
629263ac
SC		 1410 if (ret) {
1411 dev_err(&adapter->pdev->dev, "MS memory write failed\n");
3d8623e6 1412 goto exit;
629263ac
SC		 1413 }
1414
1415 /* alignment check */
7000078a 1416 if (fw->size & 0xF) {
629263ac 1417 addr = dest + size;
7000078a 1418 for (i = 0; i < (fw->size & 0xF); i++)
3d8623e6 1419 data[i] = temp[size + i];
629263ac
SC		 1420 for (; i < 16; i++)
1421 data[i] = 0;
8d37ba02
SS		 1422 ret = qlcnic_ms_mem_write128(adapter, addr,
1423 (u32 *)data, 1);
629263ac
SC		 1424 if (ret) {
1425 dev_err(&adapter->pdev->dev,
1426 "MS memory write failed\n");
3d8623e6 1427 goto exit;
629263ac
SC		 1428 }
1429 }
3d8623e6
SS		 1430
1431exit:
7000078a
PP		 1432 release_firmware(fw);
1433 fw_info->fw = NULL;
3d8623e6 1434 kfree(temp);
629263ac 1435
3d8623e6 1436 return ret;
629263ac
SC		 1437}
1438
1439static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter)
1440{
1441 int i, j;
1442 u32 val = 0, val1 = 0, reg = 0;
4bd8e738 1443 int err = 0;
629263ac 1444
4bd8e738
HM		 1445 val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG, &err);
1446 if (err == -EIO)
1447 return;
629263ac
SC		 1448 dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val);
1449
1450 for (j = 0; j < 2; j++) {
1451 if (j == 0) {
1452 dev_info(&adapter->pdev->dev,
1453 "Port 0 RxB Pause Threshold Regs[TC7..TC0]:");
1454 reg = QLC_83XX_PORT0_THRESHOLD;
1455 } else if (j == 1) {
1456 dev_info(&adapter->pdev->dev,
1457 "Port 1 RxB Pause Threshold Regs[TC7..TC0]:");
1458 reg = QLC_83XX_PORT1_THRESHOLD;
1459 }
1460 for (i = 0; i < 8; i++) {
4bd8e738
HM		 1461 val = QLCRD32(adapter, reg + (i * 0x4), &err);
1462 if (err == -EIO)
1463 return;
629263ac
SC		 1464 dev_info(&adapter->pdev->dev, "0x%x ", val);
1465 }
1466 dev_info(&adapter->pdev->dev, "\n");
1467 }
1468
1469 for (j = 0; j < 2; j++) {
1470 if (j == 0) {
1471 dev_info(&adapter->pdev->dev,
1472 "Port 0 RxB TC Max Cell Registers[4..1]:");
1473 reg = QLC_83XX_PORT0_TC_MC_REG;
1474 } else if (j == 1) {
1475 dev_info(&adapter->pdev->dev,
1476 "Port 1 RxB TC Max Cell Registers[4..1]:");
1477 reg = QLC_83XX_PORT1_TC_MC_REG;
1478 }
1479 for (i = 0; i < 4; i++) {
4bd8e738
HM		 1480 val = QLCRD32(adapter, reg + (i * 0x4), &err);
1481 if (err == -EIO)
1482 return;
1483 dev_info(&adapter->pdev->dev, "0x%x ", val);
629263ac
SC		 1484 }
1485 dev_info(&adapter->pdev->dev, "\n");
1486 }
1487
1488 for (j = 0; j < 2; j++) {
1489 if (j == 0) {
1490 dev_info(&adapter->pdev->dev,
1491 "Port 0 RxB Rx TC Stats[TC7..TC0]:");
1492 reg = QLC_83XX_PORT0_TC_STATS;
1493 } else if (j == 1) {
1494 dev_info(&adapter->pdev->dev,
1495 "Port 1 RxB Rx TC Stats[TC7..TC0]:");
1496 reg = QLC_83XX_PORT1_TC_STATS;
1497 }
1498 for (i = 7; i >= 0; i--) {
4bd8e738
HM		 1499 val = QLCRD32(adapter, reg, &err);
1500 if (err == -EIO)
1501 return;
629263ac
SC		 1502 val &= ~(0x7 << 29); /* Reset bits 29 to 31 */
1503 QLCWR32(adapter, reg, (val | (i << 29)));
4bd8e738
HM		 1504 val = QLCRD32(adapter, reg, &err);
1505 if (err == -EIO)
1506 return;
629263ac
SC		 1507 dev_info(&adapter->pdev->dev, "0x%x ", val);
1508 }
1509 dev_info(&adapter->pdev->dev, "\n");
1510 }
1511
4bd8e738
HM		 1512 val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, &err);
1513 if (err == -EIO)
1514 return;
1515 val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, &err);
1516 if (err == -EIO)
1517 return;
629263ac
SC		 1518 dev_info(&adapter->pdev->dev,
1519 "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n",
1520 val, val1);
1521}
1522
81d0aeb0 1523
629263ac
SC		 1524static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter)
1525{
1526 u32 reg = 0, i, j;
1527
1528 if (qlcnic_83xx_lock_driver(adapter)) {
1529 dev_err(&adapter->pdev->dev,
1530 "%s:failed to acquire driver lock\n", __func__);
1531 return;
1532 }
1533
1534 qlcnic_83xx_dump_pause_control_regs(adapter);
1535 QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0);
1536
1537 for (j = 0; j < 2; j++) {
1538 if (j == 0)
1539 reg = QLC_83XX_PORT0_THRESHOLD;
1540 else if (j == 1)
1541 reg = QLC_83XX_PORT1_THRESHOLD;
1542
1543 for (i = 0; i < 8; i++)
1544 QLCWR32(adapter, reg + (i * 0x4), 0x0);
1545 }
1546
1547 for (j = 0; j < 2; j++) {
1548 if (j == 0)
1549 reg = QLC_83XX_PORT0_TC_MC_REG;
1550 else if (j == 1)
1551 reg = QLC_83XX_PORT1_TC_MC_REG;
1552
1553 for (i = 0; i < 4; i++)
1554 QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF);
1555 }
1556
1557 QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0);
1558 QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0);
1559 dev_info(&adapter->pdev->dev,
1560 "Disabled pause frames successfully on all ports\n");
1561 qlcnic_83xx_unlock_driver(adapter);
1562}
1563
c0d79cd0
MC		 1564static void qlcnic_83xx_take_eport_out_of_reset(struct qlcnic_adapter *adapter)
1565{
1566 QLCWR32(adapter, QLC_83XX_RESET_REG, 0);
1567 QLCWR32(adapter, QLC_83XX_RESET_PORT0, 0);
1568 QLCWR32(adapter, QLC_83XX_RESET_PORT1, 0);
1569 QLCWR32(adapter, QLC_83XX_RESET_PORT2, 0);
1570 QLCWR32(adapter, QLC_83XX_RESET_PORT3, 0);
1571 QLCWR32(adapter, QLC_83XX_RESET_SRESHIM, 0);
1572 QLCWR32(adapter, QLC_83XX_RESET_EPGSHIM, 0);
1573 QLCWR32(adapter, QLC_83XX_RESET_ETHERPCS, 0);
1574 QLCWR32(adapter, QLC_83XX_RESET_CONTROL, 1);
1575}
1576
629263ac
SC		 1577static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev)
1578{
1579 u32 heartbeat, peg_status;
4bd8e738 1580 int retries, ret = -EIO, err = 0;
629263ac
SC		 1581
1582 retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT;
1583 p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev,
1584 QLCNIC_PEG_ALIVE_COUNTER);
1585
1586 do {
1587 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS);
1588 heartbeat = QLC_SHARED_REG_RD32(p_dev,
1589 QLCNIC_PEG_ALIVE_COUNTER);
1590 if (heartbeat != p_dev->heartbeat) {
1591 ret = QLCNIC_RCODE_SUCCESS;
1592 break;
1593 }
1594 } while (--retries);
1595
1596 if (ret) {
1597 dev_err(&p_dev->pdev->dev, "firmware hang detected\n");
c0d79cd0 1598 qlcnic_83xx_take_eport_out_of_reset(p_dev);
629263ac
SC		 1599 qlcnic_83xx_disable_pause_frames(p_dev);
1600 peg_status = QLC_SHARED_REG_RD32(p_dev,
1601 QLCNIC_PEG_HALT_STATUS1);
1602 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n"
1603 "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n"
1604 "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n"
1605 "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n"
1606 "PEG_NET_4_PC: 0x%x\n", peg_status,
1607 QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2),
4bd8e738
HM		 1608 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0, &err),
1609 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1, &err),
1610 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2, &err),
1611 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3, &err),
1612 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4, &err));
629263ac
SC		 1613
1614 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67)
1615 dev_err(&p_dev->pdev->dev,
1616 "Device is being reset err code 0x00006700.\n");
1617 }
1618
1619 return ret;
1620}
1621
1622static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev)
1623{
1624 int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT;
1625 u32 val;
1626
1627 do {
1628 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE);
1629 if (val == QLC_83XX_CMDPEG_COMPLETE)
1630 return 0;
1631 msleep(QLCNIC_CMDPEG_CHECK_DELAY);
1632 } while (--retries);
1633
1634 dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val);
1635 return -EIO;
1636}
1637
21041400 1638static int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev)
629263ac
SC		 1639{
1640 int err;
1641
1642 err = qlcnic_83xx_check_cmd_peg_status(p_dev);
1643 if (err)
1644 return err;
1645
1646 err = qlcnic_83xx_check_heartbeat(p_dev);
1647 if (err)
1648 return err;
1649
1650 return err;
1651}
1652
81d0aeb0
SC		 1653static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr,
1654 int duration, u32 mask, u32 status)
1655{
4bd8e738 1656 int timeout_error, err = 0;
81d0aeb0 1657 u32 value;
81d0aeb0
SC		 1658 u8 retries;
1659
4bd8e738
HM		 1660 value = QLCRD32(p_dev, addr, &err);
1661 if (err == -EIO)
1662 return err;
81d0aeb0
SC		 1663 retries = duration / 10;
1664
1665 do {
1666 if ((value & mask) != status) {
1667 timeout_error = 1;
1668 msleep(duration / 10);
4bd8e738
HM		 1669 value = QLCRD32(p_dev, addr, &err);
1670 if (err == -EIO)
1671 return err;
81d0aeb0
SC		 1672 } else {
1673 timeout_error = 0;
1674 break;
1675 }
1676 } while (retries--);
1677
1678 if (timeout_error) {
1679 p_dev->ahw->reset.seq_error++;
1680 dev_err(&p_dev->pdev->dev,
1681 "%s: Timeout Err, entry_num = %d\n",
1682 __func__, p_dev->ahw->reset.seq_index);
1683 dev_err(&p_dev->pdev->dev,
1684 "0x%08x 0x%08x 0x%08x\n",
1685 value, mask, status);
1686 }
1687
1688 return timeout_error;
1689}
1690
1691static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev)
1692{
1693 u32 sum = 0;
1694 u16 *buff = (u16 *)p_dev->ahw->reset.buff;
1695 int count = p_dev->ahw->reset.hdr->size / sizeof(u16);
1696
1697 while (count-- > 0)
1698 sum += *buff++;
1699
1700 while (sum >> 16)
1701 sum = (sum & 0xFFFF) + (sum >> 16);
1702
1703 if (~sum) {
1704 return 0;
1705 } else {
1706 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1707 return -1;
1708 }
1709}
1710
21041400 1711static int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev)
81d0aeb0 1712{
81d0aeb0 1713 struct qlcnic_hardware_context *ahw = p_dev->ahw;
486a5bc7
RB		 1714 u32 addr, count, prev_ver, curr_ver;
1715 u8 *p_buff;
1716
1717 if (ahw->reset.buff != NULL) {
1718 prev_ver = p_dev->fw_version;
1719 curr_ver = qlcnic_83xx_get_fw_version(p_dev);
1720 if (curr_ver > prev_ver)
1721 kfree(ahw->reset.buff);
1722 else
1723 return 0;
1724 }
81d0aeb0
SC		 1725
1726 ahw->reset.seq_error = 0;
1727 ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL);
b2adaca9 1728 if (p_dev->ahw->reset.buff == NULL)
81d0aeb0 1729 return -ENOMEM;
b2adaca9 1730
81d0aeb0
SC		 1731 p_buff = p_dev->ahw->reset.buff;
1732 addr = QLC_83XX_RESET_TEMPLATE_ADDR;
1733 count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32);
1734
1735 /* Copy template header from flash */
1736 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1737 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1738 return -EIO;
1739 }
1740 ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff;
1741 addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size;
1742 p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1743 count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32);
1744
1745 /* Copy rest of the template */
1746 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1747 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1748 return -EIO;
1749 }
1750
1751 if (qlcnic_83xx_reset_template_checksum(p_dev))
1752 return -EIO;
1753 /* Get Stop, Start and Init command offsets */
1754 ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset;
1755 ahw->reset.start_offset = ahw->reset.buff +
1756 ahw->reset.hdr->start_offset;
1757 ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1758 return 0;
1759}
1760
1761/* Read Write HW register command */
1762static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev,
1763 u32 raddr, u32 waddr)
1764{
4bd8e738
HM		 1765 int err = 0;
1766 u32 value;
81d0aeb0 1767
4bd8e738
HM		 1768 value = QLCRD32(p_dev, raddr, &err);
1769 if (err == -EIO)
1770 return;
81d0aeb0
SC		 1771 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1772}
1773
1774/* Read Modify Write HW register command */
1775static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev,
1776 u32 raddr, u32 waddr,
1777 struct qlc_83xx_rmw *p_rmw_hdr)
1778{
4bd8e738
HM		 1779 int err = 0;
1780 u32 value;
81d0aeb0 1781
4bd8e738 1782 if (p_rmw_hdr->index_a) {
81d0aeb0 1783 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a];
4bd8e738
HM		 1784 } else {
1785 value = QLCRD32(p_dev, raddr, &err);
1786 if (err == -EIO)
1787 return;
1788 }
81d0aeb0
SC		 1789
1790 value &= p_rmw_hdr->mask;
1791 value <<= p_rmw_hdr->shl;
1792 value >>= p_rmw_hdr->shr;
1793 value |= p_rmw_hdr->or_value;
1794 value ^= p_rmw_hdr->xor_value;
1795 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1796}
1797
1798/* Write HW register command */
1799static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev,
1800 struct qlc_83xx_entry_hdr *p_hdr)
1801{
1802 int i;
1803 struct qlc_83xx_entry *entry;
1804
1805 entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1806 sizeof(struct qlc_83xx_entry_hdr));
1807
1808 for (i = 0; i < p_hdr->count; i++, entry++) {
1809 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1,
1810 entry->arg2);
1811 if (p_hdr->delay)
1812 udelay((u32)(p_hdr->delay));
1813 }
1814}
1815
1816/* Read and Write instruction */
1817static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev,
1818 struct qlc_83xx_entry_hdr *p_hdr)
1819{
1820 int i;
1821 struct qlc_83xx_entry *entry;
1822
1823 entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1824 sizeof(struct qlc_83xx_entry_hdr));
1825
1826 for (i = 0; i < p_hdr->count; i++, entry++) {
1827 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1,
1828 entry->arg2);
1829 if (p_hdr->delay)
1830 udelay((u32)(p_hdr->delay));
1831 }
1832}
1833
1834/* Poll HW register command */
1835static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev,
1836 struct qlc_83xx_entry_hdr *p_hdr)
1837{
1838 long delay;
1839 struct qlc_83xx_entry *entry;
1840 struct qlc_83xx_poll *poll;
4bd8e738 1841 int i, err = 0;
81d0aeb0
SC		 1842 unsigned long arg1, arg2;
1843
1844 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1845 sizeof(struct qlc_83xx_entry_hdr));
1846
1847 entry = (struct qlc_83xx_entry *)((char *)poll +
1848 sizeof(struct qlc_83xx_poll));
1849 delay = (long)p_hdr->delay;
1850
1851 if (!delay) {
1852 for (i = 0; i < p_hdr->count; i++, entry++)
1853 qlcnic_83xx_poll_reg(p_dev, entry->arg1,
1854 delay, poll->mask,
1855 poll->status);
1856 } else {
1857 for (i = 0; i < p_hdr->count; i++, entry++) {
1858 arg1 = entry->arg1;
1859 arg2 = entry->arg2;
1860 if (delay) {
1861 if (qlcnic_83xx_poll_reg(p_dev,
1862 arg1, delay,
1863 poll->mask,
1864 poll->status)){
4bd8e738
HM		 1865 QLCRD32(p_dev, arg1, &err);
1866 if (err == -EIO)
1867 return;
1868 QLCRD32(p_dev, arg2, &err);
1869 if (err == -EIO)
1870 return;
81d0aeb0
SC		 1871 }
1872 }
1873 }
1874 }
1875}
1876
1877/* Poll and write HW register command */
1878static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev,
1879 struct qlc_83xx_entry_hdr *p_hdr)
1880{
1881 int i;
1882 long delay;
1883 struct qlc_83xx_quad_entry *entry;
1884 struct qlc_83xx_poll *poll;
1885
1886 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1887 sizeof(struct qlc_83xx_entry_hdr));
1888 entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1889 sizeof(struct qlc_83xx_poll));
1890 delay = (long)p_hdr->delay;
1891
1892 for (i = 0; i < p_hdr->count; i++, entry++) {
1893 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr,
1894 entry->dr_value);
1895 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1896 entry->ar_value);
1897 if (delay)
1898 qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1899 poll->mask, poll->status);
1900 }
1901}
1902
1903/* Read Modify Write register command */
1904static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev,
1905 struct qlc_83xx_entry_hdr *p_hdr)
1906{
1907 int i;
1908 struct qlc_83xx_entry *entry;
1909 struct qlc_83xx_rmw *rmw_hdr;
1910
1911 rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr +
1912 sizeof(struct qlc_83xx_entry_hdr));
1913
1914 entry = (struct qlc_83xx_entry *)((char *)rmw_hdr +
1915 sizeof(struct qlc_83xx_rmw));
1916
1917 for (i = 0; i < p_hdr->count; i++, entry++) {
1918 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1,
1919 entry->arg2, rmw_hdr);
1920 if (p_hdr->delay)
1921 udelay((u32)(p_hdr->delay));
1922 }
1923}
1924
1925static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr)
1926{
1927 if (p_hdr->delay)
1928 mdelay((u32)((long)p_hdr->delay));
1929}
1930
1931/* Read and poll register command */
1932static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev,
1933 struct qlc_83xx_entry_hdr *p_hdr)
1934{
1935 long delay;
4bd8e738 1936 int index, i, j, err;
81d0aeb0
SC		 1937 struct qlc_83xx_quad_entry *entry;
1938 struct qlc_83xx_poll *poll;
1939 unsigned long addr;
1940
1941 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1942 sizeof(struct qlc_83xx_entry_hdr));
1943
1944 entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1945 sizeof(struct qlc_83xx_poll));
1946 delay = (long)p_hdr->delay;
1947
1948 for (i = 0; i < p_hdr->count; i++, entry++) {
1949 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1950 entry->ar_value);
1951 if (delay) {
1952 if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1953 poll->mask, poll->status)){
1954 index = p_dev->ahw->reset.array_index;
1955 addr = entry->dr_addr;
4bd8e738
HM		 1956 j = QLCRD32(p_dev, addr, &err);
1957 if (err == -EIO)
1958 return;
1959
81d0aeb0
SC		 1960 p_dev->ahw->reset.array[index++] = j;
1961
1962 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES)
1963 p_dev->ahw->reset.array_index = 1;
1964 }
1965 }
1966 }
1967}
1968
1969static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev)
1970{
1971 p_dev->ahw->reset.seq_end = 1;
1972}
1973
1974static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev)
1975{
1976 p_dev->ahw->reset.template_end = 1;
1977 if (p_dev->ahw->reset.seq_error == 0)
1978 dev_err(&p_dev->pdev->dev,
1979 "HW restart process completed successfully.\n");
1980 else
1981 dev_err(&p_dev->pdev->dev,
1982 "HW restart completed with timeout errors.\n");
1983}
1984
1985/**
1986* qlcnic_83xx_exec_template_cmd
1987*
1988* @p_dev: adapter structure
1989* @p_buff: Poiter to instruction template
1990*
1991* Template provides instructions to stop, restart and initalize firmware.
1992* These instructions are abstracted as a series of read, write and
1993* poll operations on hardware registers. Register information and operation
1994* specifics are not exposed to the driver. Driver reads the template from
1995* flash and executes the instructions located at pre-defined offsets.
1996*
1997* Returns: None
1998* */
1999static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev,
2000 char *p_buff)
2001{
2002 int index, entries;
2003 struct qlc_83xx_entry_hdr *p_hdr;
2004 char *entry = p_buff;
2005
2006 p_dev->ahw->reset.seq_end = 0;
2007 p_dev->ahw->reset.template_end = 0;
2008 entries = p_dev->ahw->reset.hdr->entries;
2009 index = p_dev->ahw->reset.seq_index;
2010
2011 for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) {
2012 p_hdr = (struct qlc_83xx_entry_hdr *)entry;
2013
2014 switch (p_hdr->cmd) {
2015 case QLC_83XX_OPCODE_NOP:
2016 break;
2017 case QLC_83XX_OPCODE_WRITE_LIST:
2018 qlcnic_83xx_write_list(p_dev, p_hdr);
2019 break;
2020 case QLC_83XX_OPCODE_READ_WRITE_LIST:
2021 qlcnic_83xx_read_write_list(p_dev, p_hdr);
2022 break;
2023 case QLC_83XX_OPCODE_POLL_LIST:
2024 qlcnic_83xx_poll_list(p_dev, p_hdr);
2025 break;
2026 case QLC_83XX_OPCODE_POLL_WRITE_LIST:
2027 qlcnic_83xx_poll_write_list(p_dev, p_hdr);
2028 break;
2029 case QLC_83XX_OPCODE_READ_MODIFY_WRITE:
2030 qlcnic_83xx_read_modify_write(p_dev, p_hdr);
2031 break;
2032 case QLC_83XX_OPCODE_SEQ_PAUSE:
2033 qlcnic_83xx_pause(p_hdr);
2034 break;
2035 case QLC_83XX_OPCODE_SEQ_END:
2036 qlcnic_83xx_seq_end(p_dev);
2037 break;
2038 case QLC_83XX_OPCODE_TMPL_END:
2039 qlcnic_83xx_template_end(p_dev);
2040 break;
2041 case QLC_83XX_OPCODE_POLL_READ_LIST:
2042 qlcnic_83xx_poll_read_list(p_dev, p_hdr);
2043 break;
2044 default:
2045 dev_err(&p_dev->pdev->dev,
2046 "%s: Unknown opcode 0x%04x in template %d\n",
2047 __func__, p_hdr->cmd, index);
2048 break;
2049 }
2050 entry += p_hdr->size;
2051 }
2052 p_dev->ahw->reset.seq_index = index;
2053}
2054
21041400 2055static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev)
81d0aeb0
SC		 2056{
2057 p_dev->ahw->reset.seq_index = 0;
2058
2059 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset);
2060 if (p_dev->ahw->reset.seq_end != 1)
2061 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
2062}
2063
2064static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev)
2065{
2066 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset);
2067 if (p_dev->ahw->reset.template_end != 1)
2068 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
2069}
2070
2071static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev)
2072{
2073 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset);
2074 if (p_dev->ahw->reset.seq_end != 1)
2075 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
2076}
2077
629263ac
SC		 2078static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter)
2079{
7000078a 2080 struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info;
629263ac
SC		 2081 int err = -EIO;
2082
7000078a 2083 if (request_firmware(&fw_info->fw, fw_info->fw_file_name,
fef349ce 2084 &(adapter->pdev->dev))) {
629263ac
SC		 2085 dev_err(&adapter->pdev->dev,
2086 "No file FW image, loading flash FW image.\n");
2087 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
2088 QLC_83XX_BOOT_FROM_FLASH);
2089 } else {
2090 if (qlcnic_83xx_copy_fw_file(adapter))
2091 return err;
2092 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
2093 QLC_83XX_BOOT_FROM_FILE);
2094 }
2095
2096 return 0;
2097}
2098
2099static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter)
2100{
4e60ac46 2101 u32 val;
629263ac
SC		 2102 int err = -EIO;
2103
81d0aeb0 2104 qlcnic_83xx_stop_hw(adapter);
4e60ac46
SC		 2105
2106 /* Collect FW register dump if required */
2107 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
2108 if (!(val & QLC_83XX_IDC_GRACEFULL_RESET))
2109 qlcnic_dump_fw(adapter);
30fa15f6
MC		 2110
2111 if (val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) {
2112 netdev_info(adapter->netdev, "%s: Auto firmware recovery is disabled\n",
2113 __func__);
2114 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
2115 return err;
2116 }
2117
81d0aeb0
SC		 2118 qlcnic_83xx_init_hw(adapter);
2119
629263ac
SC		 2120 if (qlcnic_83xx_copy_bootloader(adapter))
2121 return err;
2122 /* Boot either flash image or firmware image from host file system */
2123 if (qlcnic_load_fw_file) {
2124 if (qlcnic_83xx_load_fw_image_from_host(adapter))
2125 return err;
2126 } else {
2127 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
2128 QLC_83XX_BOOT_FROM_FLASH);
2129 }
2130
81d0aeb0 2131 qlcnic_83xx_start_hw(adapter);
629263ac
SC		 2132 if (qlcnic_83xx_check_hw_status(adapter))
2133 return -EIO;
2134
2135 return 0;
2136}
2137
21041400 2138static int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter)
629263ac
SC		 2139{
2140 int err;
2141 struct qlcnic_info nic_info;
2142 struct qlcnic_hardware_context *ahw = adapter->ahw;
2143
2144 memset(&nic_info, 0, sizeof(struct qlcnic_info));
2145 err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
2146 if (err)
2147 return -EIO;
2148
2149 ahw->physical_port = (u8) nic_info.phys_port;
2150 ahw->switch_mode = nic_info.switch_mode;
2151 ahw->max_tx_ques = nic_info.max_tx_ques;
2152 ahw->max_rx_ques = nic_info.max_rx_ques;
2153 ahw->capabilities = nic_info.capabilities;
2154 ahw->max_mac_filters = nic_info.max_mac_filters;
2155 ahw->max_mtu = nic_info.max_mtu;
2156
35dafcb0
SC		 2157 /* eSwitch capability indicates vNIC mode.
2158 * vNIC and SRIOV are mutually exclusive operational modes.
2159 * If SR-IOV capability is detected, SR-IOV physical function
2160 * will get initialized in default mode.
2161 * SR-IOV virtual function initialization follows a
2162 * different code path and opmode.
2163 * SRIOV mode has precedence over vNIC mode.
02feda17 2164 */
35dafcb0
SC		 2165 if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state))
2166 return QLC_83XX_DEFAULT_OPMODE;
02feda17 2167
35dafcb0 2168 if (ahw->capabilities & QLC_83XX_ESWITCH_CAPABILITY)
34e8c406 2169 return QLCNIC_VNIC_MODE;
629263ac 2170
35dafcb0 2171 return QLC_83XX_DEFAULT_OPMODE;
629263ac
SC		 2172}
2173
02feda17 2174int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter)
629263ac 2175{
35dafcb0 2176 struct qlcnic_hardware_context *ahw = adapter->ahw;
7b546842 2177 u16 max_sds_rings, max_tx_rings;
629263ac
SC		 2178 int ret;
2179
2180 ret = qlcnic_83xx_get_nic_configuration(adapter);
2181 if (ret == -EIO)
2182 return -EIO;
2183
34e8c406
HM		 2184 if (ret == QLCNIC_VNIC_MODE) {
2185 ahw->nic_mode = QLCNIC_VNIC_MODE;
2186
d71170fb
SC		 2187 if (qlcnic_83xx_config_vnic_opmode(adapter))
2188 return -EIO;
35dafcb0 2189
7b546842
SS		 2190 max_sds_rings = QLCNIC_MAX_VNIC_SDS_RINGS;
2191 max_tx_rings = QLCNIC_MAX_VNIC_TX_RINGS;
35dafcb0 2192 } else if (ret == QLC_83XX_DEFAULT_OPMODE) {
34e8c406 2193 ahw->nic_mode = QLCNIC_DEFAULT_MODE;
35dafcb0
SC		 2194 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver;
2195 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry;
7b546842
SS		 2196 max_sds_rings = QLCNIC_MAX_SDS_RINGS;
2197 max_tx_rings = QLCNIC_MAX_TX_RINGS;
35dafcb0 2198 } else {
c65762fc
SC		 2199 dev_err(&adapter->pdev->dev, "%s: Invalid opmode %d\n",
2200 __func__, ret);
35dafcb0 2201 return -EIO;
629263ac
SC		 2202 }
2203
7b546842
SS		 2204 adapter->max_sds_rings = min(ahw->max_rx_ques, max_sds_rings);
2205 adapter->max_tx_rings = min(ahw->max_tx_ques, max_tx_rings);
2206
629263ac
SC		 2207 return 0;
2208}
2209
2210static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter)
2211{
2212 struct qlcnic_hardware_context *ahw = adapter->ahw;
2213
2214 if (ahw->port_type == QLCNIC_XGBE) {
2215 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G;
2216 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
2217 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2218 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2219
2220 } else if (ahw->port_type == QLCNIC_GBE) {
2221 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G;
2222 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2223 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2224 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G;
2225 }
2226 adapter->num_txd = MAX_CMD_DESCRIPTORS;
2227 adapter->max_rds_rings = MAX_RDS_RINGS;
2228}
2229
2230static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter)
2231{
2232 int err = -EIO;
2233
4e60ac46 2234 qlcnic_83xx_get_minidump_template(adapter);
629263ac
SC		 2235 if (qlcnic_83xx_get_port_info(adapter))
2236 return err;
2237
2238 qlcnic_83xx_config_buff_descriptors(adapter);
2239 adapter->ahw->msix_supported = !!qlcnic_use_msi_x;
2240 adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
2241
2242 dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
2243 adapter->ahw->fw_hal_version);
2244
2245 return 0;
2246}
2247
2248#define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1))
2249static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter)
2250{
2251 struct qlcnic_cmd_args cmd;
2252 u32 presence_mask, audit_mask;
2253 int status;
2254
2255 presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
2256 audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
2257
2258 if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) {
b6b4316c
SS		 2259 status = qlcnic_alloc_mbx_args(&cmd, adapter,
2260 QLCNIC_CMD_STOP_NIC_FUNC);
2261 if (status)
2262 return;
2263
629263ac
SC		 2264 cmd.req.arg[1] = BIT_31;
2265 status = qlcnic_issue_cmd(adapter, &cmd);
2266 if (status)
2267 dev_err(&adapter->pdev->dev,
2268 "Failed to clean up the function resources\n");
2269 qlcnic_free_mbx_args(&cmd);
2270 }
2271}
2272
7000078a
PP		 2273static int qlcnic_83xx_get_fw_info(struct qlcnic_adapter *adapter)
2274{
2275 struct qlcnic_hardware_context *ahw = adapter->ahw;
2276 struct pci_dev *pdev = adapter->pdev;
2277 struct qlc_83xx_fw_info *fw_info;
2278 int err = 0;
2279
2280 ahw->fw_info = kzalloc(sizeof(*fw_info), GFP_KERNEL);
2281 if (!ahw->fw_info) {
2282 err = -ENOMEM;
2283 } else {
2284 fw_info = ahw->fw_info;
2285 switch (pdev->device) {
2286 case PCI_DEVICE_ID_QLOGIC_QLE834X:
2287 strncpy(fw_info->fw_file_name, QLC_83XX_FW_FILE_NAME,
2288 QLC_FW_FILE_NAME_LEN);
2289 break;
2290 case PCI_DEVICE_ID_QLOGIC_QLE844X:
2291 strncpy(fw_info->fw_file_name, QLC_84XX_FW_FILE_NAME,
2292 QLC_FW_FILE_NAME_LEN);
2293 break;
2294 default:
2295 dev_err(&pdev->dev, "%s: Invalid device id\n",
2296 __func__);
2297 err = -EINVAL;
2298 break;
2299 }
2300 }
2301
2302 return err;
2303}
2304
34e8c406
HM		 2305static void qlcnic_83xx_init_rings(struct qlcnic_adapter *adapter)
2306{
18afc102
HM		 2307 u8 rx_cnt = QLCNIC_DEF_SDS_RINGS;
2308 u8 tx_cnt = QLCNIC_DEF_TX_RINGS;
2309
34e8c406
HM		 2310 adapter->max_tx_rings = QLCNIC_MAX_TX_RINGS;
2311 adapter->max_sds_rings = QLCNIC_MAX_SDS_RINGS;
2312
18afc102
HM		 2313 if (!adapter->ahw->msix_supported) {
2314 rx_cnt = QLCNIC_SINGLE_RING;
2315 tx_cnt = QLCNIC_SINGLE_RING;
2316 }
34e8c406
HM		 2317
2318 /* compute and set drv sds rings */
18afc102
HM		 2319 qlcnic_set_tx_ring_count(adapter, tx_cnt);
2320 qlcnic_set_sds_ring_count(adapter, rx_cnt);
34e8c406 2321}
7000078a 2322
f8468331 2323int qlcnic_83xx_init(struct qlcnic_adapter *adapter, int pci_using_dac)
629263ac
SC		 2324{
2325 struct qlcnic_hardware_context *ahw = adapter->ahw;
068a8d19 2326 int err = 0;
629263ac 2327
72ebe349 2328 adapter->rx_mac_learn = false;
068a8d19 2329 ahw->msix_supported = !!qlcnic_use_msi_x;
34e8c406
HM		 2330
2331 qlcnic_83xx_init_rings(adapter);
2332
068a8d19
MC		 2333 err = qlcnic_83xx_init_mailbox_work(adapter);
2334 if (err)
2335 goto exit;
f8468331 2336
068a8d19
MC		 2337 if (qlcnic_sriov_vf_check(adapter)) {
2338 err = qlcnic_sriov_vf_init(adapter, pci_using_dac);
2339 if (err)
2340 goto detach_mbx;
2341 else
2342 return err;
2343 }
629263ac 2344
78ea2d97
SC		 2345 if (qlcnic_83xx_read_flash_descriptor_table(adapter) ||
2346 qlcnic_83xx_read_flash_mfg_id(adapter)) {
2347 dev_err(&adapter->pdev->dev, "Failed reading flash mfg id\n");
2348 err = -ENOTRECOVERABLE;
2349 goto detach_mbx;
2350 }
2351
068a8d19
MC		 2352 err = qlcnic_83xx_check_hw_status(adapter);
2353 if (err)
2354 goto detach_mbx;
2355
7000078a 2356 err = qlcnic_83xx_get_fw_info(adapter);
b5acb255
MC		 2357 if (err)
2358 goto detach_mbx;
2359
7000078a
PP		 2360 err = qlcnic_83xx_idc_init(adapter);
2361 if (err)
78ea2d97 2362 goto detach_mbx;
7000078a 2363
34e8c406 2364 err = qlcnic_setup_intr(adapter);
068a8d19
MC		 2365 if (err) {
2366 dev_err(&adapter->pdev->dev, "Failed to setup interrupt\n");
2367 goto disable_intr;
2368 }
2369
463518a0
SC		 2370 INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
2371
068a8d19
MC		 2372 err = qlcnic_83xx_setup_mbx_intr(adapter);
2373 if (err)
2374 goto disable_mbx_intr;
629263ac 2375
629263ac 2376 qlcnic_83xx_clear_function_resources(adapter);
4d52e1e8 2377 qlcnic_dcb_enable(adapter->dcb);
9b0fff2a 2378 qlcnic_83xx_initialize_nic(adapter, 1);
4d52e1e8 2379 qlcnic_dcb_get_info(adapter->dcb);
d5fcff04 2380
629263ac 2381 /* Configure default, SR-IOV or Virtual NIC mode of operation */
068a8d19
MC		 2382 err = qlcnic_83xx_configure_opmode(adapter);
2383 if (err)
2384 goto disable_mbx_intr;
629263ac 2385
34e8c406 2386
629263ac 2387 /* Perform operating mode specific initialization */
068a8d19
MC		 2388 err = adapter->nic_ops->init_driver(adapter);
2389 if (err)
2390 goto disable_mbx_intr;
629263ac 2391
629263ac
SC		 2392 /* Periodically monitor device status */
2393 qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work);
068a8d19 2394 return 0;
629263ac 2395
068a8d19
MC		 2396disable_mbx_intr:
2397 qlcnic_83xx_free_mbx_intr(adapter);
2398
2399disable_intr:
2400 qlcnic_teardown_intr(adapter);
2401
2402detach_mbx:
2403 qlcnic_83xx_detach_mailbox_work(adapter);
2404 qlcnic_83xx_free_mailbox(ahw->mailbox);
78ea2d97 2405 ahw->mailbox = NULL;
068a8d19
MC		 2406exit:
2407 return err;
629263ac 2408}
9ce226fa
PP		 2409
2410void qlcnic_83xx_aer_stop_poll_work(struct qlcnic_adapter *adapter)
2411{
2412 struct qlcnic_hardware_context *ahw = adapter->ahw;
2413 struct qlc_83xx_idc *idc = &ahw->idc;
2414
2415 clear_bit(QLC_83XX_MBX_READY, &idc->status);
2416 cancel_delayed_work_sync(&adapter->fw_work);
2417
34e8c406 2418 if (ahw->nic_mode == QLCNIC_VNIC_MODE)
9ce226fa
PP		 2419 qlcnic_83xx_disable_vnic_mode(adapter, 1);
2420
2421 qlcnic_83xx_idc_detach_driver(adapter);
9b0fff2a 2422 qlcnic_83xx_initialize_nic(adapter, 0);
9ce226fa
PP		 2423
2424 cancel_delayed_work_sync(&adapter->idc_aen_work);
2425}
2426
2427int qlcnic_83xx_aer_reset(struct qlcnic_adapter *adapter)
2428{
2429 struct qlcnic_hardware_context *ahw = adapter->ahw;
2430 struct qlc_83xx_idc *idc = &ahw->idc;
2431 int ret = 0;
2432 u32 owner;
2433
2434 /* Mark the previous IDC state as NEED_RESET so
2435 * that state_entry() will perform the reattachment
2436 * and bringup the device
2437 */
2438 idc->prev_state = QLC_83XX_IDC_DEV_NEED_RESET;
2439 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
2440 if (ahw->pci_func == owner) {
2441 ret = qlcnic_83xx_restart_hw(adapter);
2442 if (ret < 0)
2443 return ret;
2444 qlcnic_83xx_idc_clear_registers(adapter, 0);
2445 }
2446
2447 ret = idc->state_entry(adapter);
2448 return ret;
2449}
2450
2451void qlcnic_83xx_aer_start_poll_work(struct qlcnic_adapter *adapter)
2452{
2453 struct qlcnic_hardware_context *ahw = adapter->ahw;
2454 struct qlc_83xx_idc *idc = &ahw->idc;
2455 u32 owner;
2456
2457 idc->prev_state = QLC_83XX_IDC_DEV_READY;
2458 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
2459 if (ahw->pci_func == owner)
2460 qlcnic_83xx_idc_enter_ready_state(adapter, 0);
2461
2462 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state, 0);
2463}
Linux 6.x block layer and io_uring tree(s)