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[linux-block.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic_83xx_hw.c
CommitLineData
577ae39d
JK		 1/*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
7f966452
SC		 8#include <linux/if_vlan.h>
9#include <linux/ipv6.h>
10#include <linux/ethtool.h>
11#include <linux/interrupt.h>
9ce226fa 12#include <linux/aer.h>
7f966452 13
a930a463
HP		 14#include "qlcnic.h"
15#include "qlcnic_sriov.h"
16
21041400 17static void __qlcnic_83xx_process_aen(struct qlcnic_adapter *);
18static int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *, u8);
19static void qlcnic_83xx_configure_mac(struct qlcnic_adapter *, u8 *, u8,
20 struct qlcnic_cmd_args *);
21static int qlcnic_83xx_get_port_config(struct qlcnic_adapter *);
22static irqreturn_t qlcnic_83xx_handle_aen(int, void *);
23static pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *,
24 pci_channel_state_t);
25static int qlcnic_83xx_set_port_config(struct qlcnic_adapter *);
26static pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *);
27static void qlcnic_83xx_io_resume(struct pci_dev *);
28static int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *, u8);
29static void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *);
30static int qlcnic_83xx_resume(struct qlcnic_adapter *);
31static int qlcnic_83xx_shutdown(struct pci_dev *);
32static void qlcnic_83xx_get_beacon_state(struct qlcnic_adapter *);
33
7f966452 34#define RSS_HASHTYPE_IP_TCP 0x3
f197a7aa 35#define QLC_83XX_FW_MBX_CMD 0
2f514c52 36#define QLC_SKIP_INACTIVE_PCI_REGS 7
aaecf51c 37#define QLC_MAX_LEGACY_FUNC_SUPP 8
7f966452 38
cd6e7381
JK		 39/* 83xx Module type */
40#define QLC_83XX_MODULE_FIBRE_10GBASE_LRM 0x1 /* 10GBase-LRM */
41#define QLC_83XX_MODULE_FIBRE_10GBASE_LR 0x2 /* 10GBase-LR */
42#define QLC_83XX_MODULE_FIBRE_10GBASE_SR 0x3 /* 10GBase-SR */
43#define QLC_83XX_MODULE_DA_10GE_PASSIVE_CP 0x4 /* 10GE passive
44 * copper(compliant)
45 */
46#define QLC_83XX_MODULE_DA_10GE_ACTIVE_CP 0x5 /* 10GE active limiting
47 * copper(compliant)
48 */
49#define QLC_83XX_MODULE_DA_10GE_LEGACY_CP 0x6 /* 10GE passive copper
50 * (legacy, best effort)
51 */
52#define QLC_83XX_MODULE_FIBRE_1000BASE_SX 0x7 /* 1000Base-SX */
53#define QLC_83XX_MODULE_FIBRE_1000BASE_LX 0x8 /* 1000Base-LX */
54#define QLC_83XX_MODULE_FIBRE_1000BASE_CX 0x9 /* 1000Base-CX */
55#define QLC_83XX_MODULE_TP_1000BASE_T 0xa /* 1000Base-T*/
56#define QLC_83XX_MODULE_DA_1GE_PASSIVE_CP 0xb /* 1GE passive copper
57 * (legacy, best effort)
58 */
59#define QLC_83XX_MODULE_UNKNOWN 0xf /* Unknown module type */
60
61/* Port types */
62#define QLC_83XX_10_CAPABLE BIT_8
63#define QLC_83XX_100_CAPABLE BIT_9
64#define QLC_83XX_1G_CAPABLE BIT_10
65#define QLC_83XX_10G_CAPABLE BIT_11
66#define QLC_83XX_AUTONEG_ENABLE BIT_15
67
7f966452
SC		 68static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
69 {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
70 {QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
71 {QLCNIC_CMD_CREATE_RX_CTX, 136, 27},
72 {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
73 {QLCNIC_CMD_CREATE_TX_CTX, 54, 18},
74 {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
75 {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1},
76 {QLCNIC_CMD_INTRPT_TEST, 22, 12},
77 {QLCNIC_CMD_SET_MTU, 3, 1},
78 {QLCNIC_CMD_READ_PHY, 4, 2},
79 {QLCNIC_CMD_WRITE_PHY, 5, 1},
80 {QLCNIC_CMD_READ_HW_REG, 4, 1},
81 {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
82 {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
83 {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
84 {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
85 {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
2f514c52 86 {QLCNIC_CMD_GET_PCI_INFO, 1, 129},
7f966452
SC		 87 {QLCNIC_CMD_GET_NIC_INFO, 2, 19},
88 {QLCNIC_CMD_SET_NIC_INFO, 32, 1},
89 {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
90 {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
91 {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
92 {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
93 {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
94 {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
95 {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
96 {QLCNIC_CMD_CONFIG_PORT, 4, 1},
97 {QLCNIC_CMD_TEMP_SIZE, 1, 4},
98 {QLCNIC_CMD_GET_TEMP_HDR, 5, 5},
99 {QLCNIC_CMD_GET_LINK_EVENT, 2, 1},
100 {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3},
101 {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1},
102 {QLCNIC_CMD_CONFIGURE_RSS, 14, 1},
103 {QLCNIC_CMD_CONFIGURE_LED, 2, 1},
104 {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1},
105 {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1},
106 {QLCNIC_CMD_GET_STATISTICS, 2, 80},
107 {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1},
108 {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2},
109 {QLCNIC_CMD_GET_LINK_STATUS, 2, 4},
110 {QLCNIC_CMD_IDC_ACK, 5, 1},
2b3d7b75 111 {QLCNIC_CMD_INIT_NIC_FUNC, 3, 1},
7f966452
SC		 112 {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1},
113 {QLCNIC_CMD_SET_LED_CONFIG, 5, 1},
114 {QLCNIC_CMD_GET_LED_CONFIG, 1, 5},
8af3f33d 115 {QLCNIC_CMD_83XX_SET_DRV_VER, 4, 1},
7f966452 116 {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26},
02feda17 117 {QLCNIC_CMD_CONFIG_VPORT, 4, 4},
f197a7aa 118 {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1},
14d385b9 119 {QLCNIC_CMD_DCB_QUERY_CAP, 1, 2},
3720bf79 120 {QLCNIC_CMD_DCB_QUERY_PARAM, 1, 50},
2b3d7b75 121 {QLCNIC_CMD_SET_INGRESS_ENCAP, 2, 1},
d01a6d3c 122 {QLCNIC_CMD_83XX_EXTEND_ISCSI_DUMP_CAP, 4, 1},
7f966452
SC		 123};
124
f8468331 125const u32 qlcnic_83xx_ext_reg_tbl[] = {
7f966452
SC		 126 0x38CC, /* Global Reset */
127 0x38F0, /* Wildcard */
128 0x38FC, /* Informant */
129 0x3038, /* Host MBX ctrl */
130 0x303C, /* FW MBX ctrl */
131 0x355C, /* BOOT LOADER ADDRESS REG */
132 0x3560, /* BOOT LOADER SIZE REG */
133 0x3564, /* FW IMAGE ADDR REG */
134 0x1000, /* MBX intr enable */
135 0x1200, /* Default Intr mask */
136 0x1204, /* Default Interrupt ID */
137 0x3780, /* QLC_83XX_IDC_MAJ_VERSION */
138 0x3784, /* QLC_83XX_IDC_DEV_STATE */
139 0x3788, /* QLC_83XX_IDC_DRV_PRESENCE */
140 0x378C, /* QLC_83XX_IDC_DRV_ACK */
141 0x3790, /* QLC_83XX_IDC_CTRL */
142 0x3794, /* QLC_83XX_IDC_DRV_AUDIT */
143 0x3798, /* QLC_83XX_IDC_MIN_VERSION */
144 0x379C, /* QLC_83XX_RECOVER_DRV_LOCK */
145 0x37A0, /* QLC_83XX_IDC_PF_0 */
146 0x37A4, /* QLC_83XX_IDC_PF_1 */
147 0x37A8, /* QLC_83XX_IDC_PF_2 */
148 0x37AC, /* QLC_83XX_IDC_PF_3 */
149 0x37B0, /* QLC_83XX_IDC_PF_4 */
150 0x37B4, /* QLC_83XX_IDC_PF_5 */
151 0x37B8, /* QLC_83XX_IDC_PF_6 */
152 0x37BC, /* QLC_83XX_IDC_PF_7 */
153 0x37C0, /* QLC_83XX_IDC_PF_8 */
154 0x37C4, /* QLC_83XX_IDC_PF_9 */
155 0x37C8, /* QLC_83XX_IDC_PF_10 */
156 0x37CC, /* QLC_83XX_IDC_PF_11 */
157 0x37D0, /* QLC_83XX_IDC_PF_12 */
158 0x37D4, /* QLC_83XX_IDC_PF_13 */
159 0x37D8, /* QLC_83XX_IDC_PF_14 */
160 0x37DC, /* QLC_83XX_IDC_PF_15 */
161 0x37E0, /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
162 0x37E4, /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
163 0x37F0, /* QLC_83XX_DRV_OP_MODE */
164 0x37F4, /* QLC_83XX_VNIC_STATE */
165 0x3868, /* QLC_83XX_DRV_LOCK */
166 0x386C, /* QLC_83XX_DRV_UNLOCK */
167 0x3504, /* QLC_83XX_DRV_LOCK_ID */
168 0x34A4, /* QLC_83XX_ASIC_TEMP */
169};
170
f8468331 171const u32 qlcnic_83xx_reg_tbl[] = {
7f966452
SC		 172 0x34A8, /* PEG_HALT_STAT1 */
173 0x34AC, /* PEG_HALT_STAT2 */
174 0x34B0, /* FW_HEARTBEAT */
175 0x3500, /* FLASH LOCK_ID */
176 0x3528, /* FW_CAPABILITIES */
177 0x3538, /* Driver active, DRV_REG0 */
178 0x3540, /* Device state, DRV_REG1 */
179 0x3544, /* Driver state, DRV_REG2 */
180 0x3548, /* Driver scratch, DRV_REG3 */
8ab102d6 181 0x354C, /* Device partition info, DRV_REG4 */
7f966452
SC		 182 0x3524, /* Driver IDC ver, DRV_REG5 */
183 0x3550, /* FW_VER_MAJOR */
184 0x3554, /* FW_VER_MINOR */
185 0x3558, /* FW_VER_SUB */
186 0x359C, /* NPAR STATE */
187 0x35FC, /* FW_IMG_VALID */
188 0x3650, /* CMD_PEG_STATE */
189 0x373C, /* RCV_PEG_STATE */
190 0x37B4, /* ASIC TEMP */
191 0x356C, /* FW API */
192 0x3570, /* DRV OP MODE */
193 0x3850, /* FLASH LOCK */
194 0x3854, /* FLASH UNLOCK */
195};
196
197static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = {
198 .read_crb = qlcnic_83xx_read_crb,
199 .write_crb = qlcnic_83xx_write_crb,
200 .read_reg = qlcnic_83xx_rd_reg_indirect,
201 .write_reg = qlcnic_83xx_wrt_reg_indirect,
202 .get_mac_address = qlcnic_83xx_get_mac_address,
203 .setup_intr = qlcnic_83xx_setup_intr,
204 .alloc_mbx_args = qlcnic_83xx_alloc_mbx_args,
e5c4e6c6 205 .mbx_cmd = qlcnic_83xx_issue_cmd,
7f966452
SC		 206 .get_func_no = qlcnic_83xx_get_func_no,
207 .api_lock = qlcnic_83xx_cam_lock,
208 .api_unlock = qlcnic_83xx_cam_unlock,
319ecf12
SC		 209 .add_sysfs = qlcnic_83xx_add_sysfs,
210 .remove_sysfs = qlcnic_83xx_remove_sysfs,
4be41e92 211 .process_lb_rcv_ring_diag = qlcnic_83xx_process_rcv_ring_diag,
7f966452
SC		 212 .create_rx_ctx = qlcnic_83xx_create_rx_ctx,
213 .create_tx_ctx = qlcnic_83xx_create_tx_ctx,
7cb03b23
RB		 214 .del_rx_ctx = qlcnic_83xx_del_rx_ctx,
215 .del_tx_ctx = qlcnic_83xx_del_tx_ctx,
7f966452
SC		 216 .setup_link_event = qlcnic_83xx_setup_link_event,
217 .get_nic_info = qlcnic_83xx_get_nic_info,
218 .get_pci_info = qlcnic_83xx_get_pci_info,
219 .set_nic_info = qlcnic_83xx_set_nic_info,
220 .change_macvlan = qlcnic_83xx_sre_macaddr_change,
4be41e92
SC		 221 .napi_enable = qlcnic_83xx_napi_enable,
222 .napi_disable = qlcnic_83xx_napi_disable,
7f966452
SC		 223 .config_intr_coal = qlcnic_83xx_config_intr_coal,
224 .config_rss = qlcnic_83xx_config_rss,
225 .config_hw_lro = qlcnic_83xx_config_hw_lro,
7f966452
SC		 226 .config_promisc_mode = qlcnic_83xx_nic_set_promisc,
227 .change_l2_filter = qlcnic_83xx_change_l2_filter,
228 .get_board_info = qlcnic_83xx_get_port_info,
52e493d0 229 .set_mac_filter_count = qlcnic_83xx_set_mac_filter_count,
91b7282b 230 .free_mac_list = qlcnic_82xx_free_mac_list,
9ce226fa
PP		 231 .io_error_detected = qlcnic_83xx_io_error_detected,
232 .io_slot_reset = qlcnic_83xx_io_slot_reset,
233 .io_resume = qlcnic_83xx_io_resume,
a0431589 234 .get_beacon_state = qlcnic_83xx_get_beacon_state,
2cc5752e
M		 235 .enable_sds_intr = qlcnic_83xx_enable_sds_intr,
236 .disable_sds_intr = qlcnic_83xx_disable_sds_intr,
237 .enable_tx_intr = qlcnic_83xx_enable_tx_intr,
238 .disable_tx_intr = qlcnic_83xx_disable_tx_intr,
225837a0
SS		 239 .get_saved_state = qlcnic_83xx_get_saved_state,
240 .set_saved_state = qlcnic_83xx_set_saved_state,
241 .cache_tmpl_hdr_values = qlcnic_83xx_cache_tmpl_hdr_values,
242 .get_cap_size = qlcnic_83xx_get_cap_size,
243 .set_sys_info = qlcnic_83xx_set_sys_info,
244 .store_cap_mask = qlcnic_83xx_store_cap_mask,
4bd7ef0b
CM		 245 .encap_rx_offload = qlcnic_83xx_encap_rx_offload,
246 .encap_tx_offload = qlcnic_83xx_encap_tx_offload,
7f966452
SC		 247};
248
249static struct qlcnic_nic_template qlcnic_83xx_ops = {
250 .config_bridged_mode = qlcnic_config_bridged_mode,
251 .config_led = qlcnic_config_led,
629263ac
SC		 252 .request_reset = qlcnic_83xx_idc_request_reset,
253 .cancel_idc_work = qlcnic_83xx_idc_exit,
4be41e92
SC		 254 .napi_add = qlcnic_83xx_napi_add,
255 .napi_del = qlcnic_83xx_napi_del,
7f966452
SC		 256 .config_ipaddr = qlcnic_83xx_config_ipaddr,
257 .clear_legacy_intr = qlcnic_83xx_clear_legacy_intr,
486a5bc7
RB		 258 .shutdown = qlcnic_83xx_shutdown,
259 .resume = qlcnic_83xx_resume,
7f966452
SC		 260};
261
262void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw)
263{
264 ahw->hw_ops = &qlcnic_83xx_hw_ops;
265 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl;
266 ahw->ext_reg_tbl = (u32 *)qlcnic_83xx_ext_reg_tbl;
267}
268
269int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter)
270{
271 u32 fw_major, fw_minor, fw_build;
272 struct pci_dev *pdev = adapter->pdev;
273
274 fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
275 fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
276 fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
277 adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
278
279 dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n",
280 QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build);
281
282 return adapter->fw_version;
283}
284
285static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr)
286{
287 void __iomem *base;
288 u32 val;
289
290 base = adapter->ahw->pci_base0 +
291 QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func);
292 writel(addr, base);
293 val = readl(base);
294 if (val != addr)
295 return -EIO;
296
297 return 0;
298}
299
4bd8e738
HM		 300int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
301 int *err)
7f966452 302{
7f966452
SC		 303 struct qlcnic_hardware_context *ahw = adapter->ahw;
304
4bd8e738
HM		 305 *err = __qlcnic_set_win_base(adapter, (u32) addr);
306 if (!*err) {
7f966452
SC		 307 return QLCRDX(ahw, QLCNIC_WILDCARD);
308 } else {
309 dev_err(&adapter->pdev->dev,
4bd8e738 310 "%s failed, addr = 0x%lx\n", __func__, addr);
7f966452
SC		 311 return -EIO;
312 }
313}
314
315int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
316 u32 data)
317{
318 int err;
319 struct qlcnic_hardware_context *ahw = adapter->ahw;
320
321 err = __qlcnic_set_win_base(adapter, (u32) addr);
322 if (!err) {
323 QLCWRX(ahw, QLCNIC_WILDCARD, data);
324 return 0;
325 } else {
326 dev_err(&adapter->pdev->dev,
327 "%s failed, addr = 0x%x data = 0x%x\n",
328 __func__, (int)addr, data);
329 return err;
330 }
331}
332
cb9327d5 333static void qlcnic_83xx_enable_legacy(struct qlcnic_adapter *adapter)
7f966452 334{
7f966452
SC		 335 struct qlcnic_hardware_context *ahw = adapter->ahw;
336
cb9327d5
HM		 337 /* MSI-X enablement failed, use legacy interrupt */
338 adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR;
339 adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK;
340 adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR;
341 adapter->msix_entries[0].vector = adapter->pdev->irq;
342 dev_info(&adapter->pdev->dev, "using legacy interrupt\n");
343}
344
345static int qlcnic_83xx_calculate_msix_vector(struct qlcnic_adapter *adapter)
346{
347 int num_msix;
348
34e8c406
HM		 349 num_msix = adapter->drv_sds_rings;
350
7f966452
SC		 351 /* account for AEN interrupt MSI-X based interrupts */
352 num_msix += 1;
da6c8063
RB		 353
354 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
34e8c406 355 num_msix += adapter->drv_tx_rings;
da6c8063 356
cb9327d5
HM		 357 return num_msix;
358}
359
360int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter)
361{
362 struct qlcnic_hardware_context *ahw = adapter->ahw;
363 int err, i, num_msix;
364
365 if (adapter->flags & QLCNIC_TSS_RSS) {
366 err = qlcnic_setup_tss_rss_intr(adapter);
367 if (err < 0)
368 return err;
369 num_msix = ahw->num_msix;
370 } else {
371 num_msix = qlcnic_83xx_calculate_msix_vector(adapter);
372
373 err = qlcnic_enable_msix(adapter, num_msix);
374 if (err == -ENOMEM)
375 return err;
376
377 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
378 num_msix = ahw->num_msix;
379 } else {
380 if (qlcnic_sriov_vf_check(adapter))
381 return -EINVAL;
382 num_msix = 1;
42beb3f2 383 adapter->drv_sds_rings = QLCNIC_SINGLE_RING;
cb9327d5
HM		 384 adapter->drv_tx_rings = QLCNIC_SINGLE_RING;
385 }
f8468331 386 }
cb9327d5 387
7f966452 388 /* setup interrupt mapping table for fw */
fad953ce
KC		 389 ahw->intr_tbl =
390 vzalloc(array_size(num_msix,
391 sizeof(struct qlcnic_intrpt_config)));
7f966452
SC		 392 if (!ahw->intr_tbl)
393 return -ENOMEM;
cb9327d5 394
aaecf51c
SC		 395 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
396 if (adapter->ahw->pci_func >= QLC_MAX_LEGACY_FUNC_SUPP) {
397 dev_err(&adapter->pdev->dev, "PCI function number 8 and higher are not supported with legacy interrupt, func 0x%x\n",
398 ahw->pci_func);
399 return -EOPNOTSUPP;
400 }
401
cb9327d5 402 qlcnic_83xx_enable_legacy(adapter);
aaecf51c 403 }
7f966452
SC		 404
405 for (i = 0; i < num_msix; i++) {
406 if (adapter->flags & QLCNIC_MSIX_ENABLED)
407 ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
408 else
409 ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
410 ahw->intr_tbl[i].id = i;
411 ahw->intr_tbl[i].src = 0;
412 }
cb9327d5 413
7f966452
SC		 414 return 0;
415}
416
49fef742 417static inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
ac166700
HM		 418{
419 writel(0, adapter->tgt_mask_reg);
420}
421
49fef742 422static inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter)
45ef92ed 423{
78ea2d97
SC		 424 if (adapter->tgt_mask_reg)
425 writel(1, adapter->tgt_mask_reg);
45ef92ed
HM		 426}
427
49fef742 428static inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
ac166700
HM		 429 *adapter)
430{
431 u32 mask;
432
433 /* Mailbox in MSI-x mode and Legacy Interrupt share the same
434 * source register. We could be here before contexts are created
435 * and sds_ring->crb_intr_mask has not been initialized, calculate
436 * BAR offset for Interrupt Source Register
437 */
438 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
439 writel(0, adapter->ahw->pci_base0 + mask);
440}
441
f036e4f4 442void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
ac166700
HM		 443{
444 u32 mask;
445
446 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
447 writel(1, adapter->ahw->pci_base0 + mask);
f036e4f4 448 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
7f966452
SC		 449}
450
451static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
452 struct qlcnic_cmd_args *cmd)
453{
454 int i;
068a8d19
MC		 455
456 if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
457 return;
458
7f966452
SC		 459 for (i = 0; i < cmd->rsp.num; i++)
460 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
461}
462
463irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
464{
465 u32 intr_val;
466 struct qlcnic_hardware_context *ahw = adapter->ahw;
467 int retries = 0;
468
469 intr_val = readl(adapter->tgt_status_reg);
470
471 if (!QLC_83XX_VALID_INTX_BIT31(intr_val))
472 return IRQ_NONE;
473
474 if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) {
475 adapter->stats.spurious_intr++;
476 return IRQ_NONE;
477 }
ac166700
HM		 478 /* The barrier is required to ensure writes to the registers */
479 wmb();
480
7f966452 481 /* clear the interrupt trigger control register */
f9442ac4 482 writel_relaxed(0, adapter->isr_int_vec);
ac166700 483 intr_val = readl(adapter->isr_int_vec);
7f966452
SC		 484 do {
485 intr_val = readl(adapter->tgt_status_reg);
486 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func)
487 break;
488 retries++;
489 } while (QLC_83XX_VALID_INTX_BIT30(intr_val) &&
490 (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY));
491
ac166700
HM		 492 return IRQ_HANDLED;
493}
494
e5c4e6c6
MC		 495static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox *mbx)
496{
5bf93251 497 mbx->rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
e5c4e6c6
MC		 498 complete(&mbx->completion);
499}
500
ac166700
HM		 501static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter)
502{
068a8d19
MC		 503 u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
504 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
ac166700
HM		 505 unsigned long flags;
506
068a8d19 507 spin_lock_irqsave(&mbx->aen_lock, flags);
ac166700
HM		 508 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
509 if (!(resp & QLCNIC_SET_OWNER))
510 goto out;
511
512 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
068a8d19 513 if (event & QLCNIC_MBX_ASYNC_EVENT) {
d1a1105e 514 __qlcnic_83xx_process_aen(adapter);
068a8d19 515 } else {
5bf93251 516 if (mbx->rsp_status != rsp_status)
068a8d19
MC		 517 qlcnic_83xx_notify_mbx_response(mbx);
518 }
ac166700
HM		 519out:
520 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
068a8d19 521 spin_unlock_irqrestore(&mbx->aen_lock, flags);
ac166700
HM		 522}
523
524irqreturn_t qlcnic_83xx_intr(int irq, void *data)
525{
526 struct qlcnic_adapter *adapter = data;
527 struct qlcnic_host_sds_ring *sds_ring;
528 struct qlcnic_hardware_context *ahw = adapter->ahw;
529
530 if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE)
7f966452 531 return IRQ_NONE;
ac166700
HM		 532
533 qlcnic_83xx_poll_process_aen(adapter);
534
e49df794
M		 535 if (ahw->diag_test) {
536 if (ahw->diag_test == QLCNIC_INTERRUPT_TEST)
537 ahw->diag_cnt++;
ac166700
HM		 538 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
539 return IRQ_HANDLED;
7f966452
SC		 540 }
541
ac166700
HM		 542 if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
543 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
544 } else {
545 sds_ring = &adapter->recv_ctx->sds_rings[0];
546 napi_schedule(&sds_ring->napi);
547 }
7f966452
SC		 548
549 return IRQ_HANDLED;
550}
551
552irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data)
553{
554 struct qlcnic_host_sds_ring *sds_ring = data;
555 struct qlcnic_adapter *adapter = sds_ring->adapter;
556
557 if (adapter->flags & QLCNIC_MSIX_ENABLED)
558 goto done;
559
560 if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE)
561 return IRQ_NONE;
562
563done:
564 adapter->ahw->diag_cnt++;
2cc5752e 565 qlcnic_enable_sds_intr(adapter, sds_ring);
7f966452
SC		 566
567 return IRQ_HANDLED;
568}
569
570void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter)
571{
f036e4f4
RB		 572 u32 num_msix;
573
45ef92ed
HM		 574 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
575 qlcnic_83xx_set_legacy_intr_mask(adapter);
576
f036e4f4 577 qlcnic_83xx_disable_mbx_intr(adapter);
7f966452 578
ac166700
HM		 579 if (adapter->flags & QLCNIC_MSIX_ENABLED)
580 num_msix = adapter->ahw->num_msix - 1;
581 else
582 num_msix = 0;
7f966452 583
ac166700 584 msleep(20);
78ea2d97
SC		 585
586 if (adapter->msix_entries) {
587 synchronize_irq(adapter->msix_entries[num_msix].vector);
588 free_irq(adapter->msix_entries[num_msix].vector, adapter);
589 }
7f966452
SC		 590}
591
592int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter)
593{
594 irq_handler_t handler;
595 u32 val;
7f966452
SC		 596 int err = 0;
597 unsigned long flags = 0;
598
599 if (!(adapter->flags & QLCNIC_MSI_ENABLED) &&
600 !(adapter->flags & QLCNIC_MSIX_ENABLED))
601 flags |= IRQF_SHARED;
602
603 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
604 handler = qlcnic_83xx_handle_aen;
605 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector;
aa2a8034 606 err = request_irq(val, handler, flags, "qlcnic-MB", adapter);
7f966452
SC		 607 if (err) {
608 dev_err(&adapter->pdev->dev,
609 "failed to register MBX interrupt\n");
610 return err;
611 }
ac166700
HM		 612 } else {
613 handler = qlcnic_83xx_intr;
614 val = adapter->msix_entries[0].vector;
615 err = request_irq(val, handler, flags, "qlcnic", adapter);
616 if (err) {
617 dev_err(&adapter->pdev->dev,
618 "failed to register INTx interrupt\n");
619 return err;
620 }
621 qlcnic_83xx_clear_legacy_intr_mask(adapter);
7f966452
SC		 622 }
623
624 /* Enable mailbox interrupt */
e5c4e6c6 625 qlcnic_83xx_enable_mbx_interrupt(adapter);
7f966452
SC		 626
627 return err;
628}
629
630void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter)
631{
632 u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT);
f8468331 633 adapter->ahw->pci_func = (val >> 24) & 0xff;
7f966452
SC		 634}
635
636int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter)
637{
638 void __iomem *addr;
639 u32 val, limit = 0;
640
641 struct qlcnic_hardware_context *ahw = adapter->ahw;
642
643 addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func);
644 do {
645 val = readl(addr);
646 if (val) {
647 /* write the function number to register */
648 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
649 ahw->pci_func);
650 return 0;
651 }
652 usleep_range(1000, 2000);
653 } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT);
654
655 return -EIO;
656}
657
658void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter)
659{
660 void __iomem *addr;
661 u32 val;
662 struct qlcnic_hardware_context *ahw = adapter->ahw;
663
664 addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func);
665 val = readl(addr);
666}
667
668void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
669 loff_t offset, size_t size)
670{
4bd8e738 671 int ret = 0;
7f966452
SC		 672 u32 data;
673
674 if (qlcnic_api_lock(adapter)) {
675 dev_err(&adapter->pdev->dev,
676 "%s: failed to acquire lock. addr offset 0x%x\n",
677 __func__, (u32)offset);
678 return;
679 }
680
4bd8e738 681 data = QLCRD32(adapter, (u32) offset, &ret);
7f966452
SC		 682 qlcnic_api_unlock(adapter);
683
684 if (ret == -EIO) {
685 dev_err(&adapter->pdev->dev,
686 "%s: failed. addr offset 0x%x\n",
687 __func__, (u32)offset);
688 return;
689 }
7f966452
SC		 690 memcpy(buf, &data, size);
691}
692
693void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
694 loff_t offset, size_t size)
695{
696 u32 data;
697
698 memcpy(&data, buf, size);
699 qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data);
700}
701
702int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
703{
cd6e7381 704 struct qlcnic_hardware_context *ahw = adapter->ahw;
7f966452
SC		 705 int status;
706
707 status = qlcnic_83xx_get_port_config(adapter);
708 if (status) {
709 dev_err(&adapter->pdev->dev,
710 "Get Port Info failed\n");
711 } else {
629263ac 712
cd6e7381
JK		 713 if (ahw->port_config & QLC_83XX_10G_CAPABLE) {
714 ahw->port_type = QLCNIC_XGBE;
715 } else if (ahw->port_config & QLC_83XX_10_CAPABLE ||
716 ahw->port_config & QLC_83XX_100_CAPABLE ||
717 ahw->port_config & QLC_83XX_1G_CAPABLE) {
718 ahw->port_type = QLCNIC_GBE;
719 } else {
720 ahw->port_type = QLCNIC_XGBE;
721 }
722
723 if (QLC_83XX_AUTONEG(ahw->port_config))
724 ahw->link_autoneg = AUTONEG_ENABLE;
725
7f966452
SC		 726 }
727 return status;
728}
729
21041400 730static void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *adapter)
52e493d0
JK		 731{
732 struct qlcnic_hardware_context *ahw = adapter->ahw;
2f514c52 733 u16 act_pci_fn = ahw->total_nic_func;
52e493d0
JK		 734 u16 count;
735
736 ahw->max_mc_count = QLC_83XX_MAX_MC_COUNT;
737 if (act_pci_fn <= 2)
738 count = (QLC_83XX_MAX_UC_COUNT - QLC_83XX_MAX_MC_COUNT) /
739 act_pci_fn;
740 else
741 count = (QLC_83XX_LB_MAX_FILTERS - QLC_83XX_MAX_MC_COUNT) /
742 act_pci_fn;
743 ahw->max_uc_count = count;
744}
745
e5c4e6c6 746void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *adapter)
7f966452
SC		 747{
748 u32 val;
749
750 if (adapter->flags & QLCNIC_MSIX_ENABLED)
751 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
752 else
753 val = BIT_2;
629263ac 754
7f966452 755 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
ac166700 756 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
7f966452
SC		 757}
758
759void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter,
760 const struct pci_device_id *ent)
761{
762 u32 op_mode, priv_level;
763 struct qlcnic_hardware_context *ahw = adapter->ahw;
764
7f966452 765 ahw->fw_hal_version = 2;
7f966452
SC		 766 qlcnic_get_func_no(adapter);
767
f8468331
RB		 768 if (qlcnic_sriov_vf_check(adapter)) {
769 qlcnic_sriov_vf_set_ops(adapter);
770 return;
771 }
772
7f966452
SC		 773 /* Determine function privilege level */
774 op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
775 if (op_mode == QLC_83XX_DEFAULT_OPMODE)
776 priv_level = QLCNIC_MGMT_FUNC;
777 else
778 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
779 ahw->pci_func);
780
781 if (priv_level == QLCNIC_NON_PRIV_FUNC) {
782 ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
783 dev_info(&adapter->pdev->dev,
784 "HAL Version: %d Non Privileged function\n",
785 ahw->fw_hal_version);
786 adapter->nic_ops = &qlcnic_vf_ops;
787 } else {
02feda17
RB		 788 if (pci_find_ext_capability(adapter->pdev,
789 PCI_EXT_CAP_ID_SRIOV))
790 set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state);
7f966452
SC		 791 adapter->nic_ops = &qlcnic_83xx_ops;
792 }
793}
794
795static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
796 u32 data[]);
797static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
798 u32 data[]);
799
012ec812
HM		 800void qlcnic_dump_mbx(struct qlcnic_adapter *adapter,
801 struct qlcnic_cmd_args *cmd)
7f966452
SC		 802{
803 int i;
804
068a8d19
MC		 805 if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
806 return;
807
7f966452
SC		 808 dev_info(&adapter->pdev->dev,
809 "Host MBX regs(%d)\n", cmd->req.num);
810 for (i = 0; i < cmd->req.num; i++) {
811 if (i && !(i % 8))
812 pr_info("\n");
813 pr_info("%08x ", cmd->req.arg[i]);
814 }
815 pr_info("\n");
816 dev_info(&adapter->pdev->dev,
817 "FW MBX regs(%d)\n", cmd->rsp.num);
818 for (i = 0; i < cmd->rsp.num; i++) {
819 if (i && !(i % 8))
820 pr_info("\n");
821 pr_info("%08x ", cmd->rsp.arg[i]);
822 }
823 pr_info("\n");
824}
825
60dcbcb0
MC		 826static void qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter *adapter,
827 struct qlcnic_cmd_args *cmd)
65ab999d 828{
068a8d19
MC		 829 struct qlcnic_hardware_context *ahw = adapter->ahw;
830 int opcode = LSW(cmd->req.arg[0]);
831 unsigned long max_loops;
65ab999d 832
068a8d19 833 max_loops = cmd->total_cmds * QLC_83XX_MBX_CMD_LOOP;
65ab999d 834
068a8d19
MC		 835 for (; max_loops; max_loops--) {
836 if (atomic_read(&cmd->rsp_status) ==
837 QLC_83XX_MBX_RESPONSE_ARRIVED)
838 return;
839
840 udelay(1);
841 }
842
843 dev_err(&adapter->pdev->dev,
844 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
845 __func__, opcode, cmd->type, ahw->pci_func, ahw->op_mode);
846 flush_workqueue(ahw->mailbox->work_q);
847 return;
7f966452
SC		 848}
849
e5c4e6c6
MC		 850int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *adapter,
851 struct qlcnic_cmd_args *cmd)
7f966452 852{
068a8d19 853 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
7f966452 854 struct qlcnic_hardware_context *ahw = adapter->ahw;
068a8d19
MC		 855 int cmd_type, err, opcode;
856 unsigned long timeout;
7f966452 857
78ea2d97
SC		 858 if (!mbx)
859 return -EIO;
860
7f966452 861 opcode = LSW(cmd->req.arg[0]);
068a8d19
MC		 862 cmd_type = cmd->type;
863 err = mbx->ops->enqueue_cmd(adapter, cmd, &timeout);
864 if (err) {
865 dev_err(&adapter->pdev->dev,
866 "%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n",
867 __func__, opcode, cmd->type, ahw->pci_func,
868 ahw->op_mode);
869 return err;
7f966452
SC		 870 }
871
068a8d19
MC		 872 switch (cmd_type) {
873 case QLC_83XX_MBX_CMD_WAIT:
874 if (!wait_for_completion_timeout(&cmd->completion, timeout)) {
65ab999d 875 dev_err(&adapter->pdev->dev,
068a8d19
MC		 876 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
877 __func__, opcode, cmd_type, ahw->pci_func,
878 ahw->op_mode);
879 flush_workqueue(mbx->work_q);
7f966452 880 }
068a8d19
MC		 881 break;
882 case QLC_83XX_MBX_CMD_NO_WAIT:
883 return 0;
884 case QLC_83XX_MBX_CMD_BUSY_WAIT:
885 qlcnic_83xx_poll_for_mbx_completion(adapter, cmd);
886 break;
887 default:
888 dev_err(&adapter->pdev->dev,
889 "%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
890 __func__, opcode, cmd_type, ahw->pci_func,
891 ahw->op_mode);
892 qlcnic_83xx_detach_mailbox_work(adapter);
7f966452 893 }
65ab999d 894
068a8d19 895 return cmd->rsp_opcode;
7f966452
SC		 896}
897
898int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
899 struct qlcnic_adapter *adapter, u32 type)
900{
901 int i, size;
902 u32 temp;
903 const struct qlcnic_mailbox_metadata *mbx_tbl;
904
e5c4e6c6 905 memset(mbx, 0, sizeof(struct qlcnic_cmd_args));
7f966452
SC		 906 mbx_tbl = qlcnic_83xx_mbx_tbl;
907 size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl);
908 for (i = 0; i < size; i++) {
909 if (type == mbx_tbl[i].cmd) {
f197a7aa 910 mbx->op_type = QLC_83XX_FW_MBX_CMD;
7f966452
SC		 911 mbx->req.num = mbx_tbl[i].in_args;
912 mbx->rsp.num = mbx_tbl[i].out_args;
913 mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
914 GFP_ATOMIC);
915 if (!mbx->req.arg)
916 return -ENOMEM;
917 mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
918 GFP_ATOMIC);
919 if (!mbx->rsp.arg) {
920 kfree(mbx->req.arg);
921 mbx->req.arg = NULL;
922 return -ENOMEM;
923 }
7f966452
SC		 924 temp = adapter->ahw->fw_hal_version << 29;
925 mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp);
068a8d19 926 mbx->cmd_op = type;
f197a7aa 927 return 0;
7f966452
SC		 928 }
929 }
c65762fc
SC		 930
931 dev_err(&adapter->pdev->dev, "%s: Invalid mailbox command opcode 0x%x\n",
932 __func__, type);
f197a7aa 933 return -EINVAL;
7f966452
SC		 934}
935
936void qlcnic_83xx_idc_aen_work(struct work_struct *work)
937{
938 struct qlcnic_adapter *adapter;
939 struct qlcnic_cmd_args cmd;
940 int i, err = 0;
941
942 adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work);
b6b4316c
SS		 943 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK);
944 if (err)
945 return;
7f966452
SC		 946
947 for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++)
948 cmd.req.arg[i] = adapter->ahw->mbox_aen[i];
949
950 err = qlcnic_issue_cmd(adapter, &cmd);
951 if (err)
952 dev_info(&adapter->pdev->dev,
953 "%s: Mailbox IDC ACK failed.\n", __func__);
954 qlcnic_free_mbx_args(&cmd);
955}
956
957static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
958 u32 data[])
959{
960 dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n",
961 QLCNIC_MBX_RSP(data[0]));
629263ac 962 clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status);
7f966452
SC		 963 return;
964}
965
21041400 966static void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
7f966452 967{
77bead46 968 struct qlcnic_hardware_context *ahw = adapter->ahw;
483202d5 969 u32 event[QLC_83XX_MBX_AEN_CNT];
7f966452 970 int i;
7f966452 971
7f966452
SC		 972 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
973 event[i] = readl(QLCNIC_MBX_FW(ahw, i));
974
975 switch (QLCNIC_MBX_RSP(event[0])) {
976
977 case QLCNIC_MBX_LINK_EVENT:
978 qlcnic_83xx_handle_link_aen(adapter, event);
979 break;
980 case QLCNIC_MBX_COMP_EVENT:
981 qlcnic_83xx_handle_idc_comp_aen(adapter, event);
982 break;
983 case QLCNIC_MBX_REQUEST_EVENT:
984 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
985 adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]);
986 queue_delayed_work(adapter->qlcnic_wq,
987 &adapter->idc_aen_work, 0);
988 break;
989 case QLCNIC_MBX_TIME_EXTEND_EVENT:
77bead46 990 ahw->extend_lb_time = event[1] >> 8 & 0xf;
7f966452 991 break;
f197a7aa
RB		 992 case QLCNIC_MBX_BC_EVENT:
993 qlcnic_sriov_handle_bc_event(adapter, event[1]);
994 break;
7f966452
SC		 995 case QLCNIC_MBX_SFP_INSERT_EVENT:
996 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n",
997 QLCNIC_MBX_RSP(event[0]));
998 break;
999 case QLCNIC_MBX_SFP_REMOVE_EVENT:
1000 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n",
1001 QLCNIC_MBX_RSP(event[0]));
1002 break;
2d8ebcab 1003 case QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT:
1de899d3 1004 qlcnic_dcb_aen_handler(adapter->dcb, (void *)&event[1]);
2d8ebcab 1005 break;
7f966452
SC		 1006 default:
1007 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n",
1008 QLCNIC_MBX_RSP(event[0]));
1009 break;
1010 }
1011
1012 QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
7f966452
SC		 1013}
1014
d1a1105e
RB		 1015static void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
1016{
068a8d19 1017 u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
d1a1105e 1018 struct qlcnic_hardware_context *ahw = adapter->ahw;
068a8d19 1019 struct qlcnic_mailbox *mbx = ahw->mailbox;
d1a1105e
RB		 1020 unsigned long flags;
1021
068a8d19 1022 spin_lock_irqsave(&mbx->aen_lock, flags);
d1a1105e
RB		 1023 resp = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
1024 if (resp & QLCNIC_SET_OWNER) {
1025 event = readl(QLCNIC_MBX_FW(ahw, 0));
068a8d19 1026 if (event & QLCNIC_MBX_ASYNC_EVENT) {
d1a1105e 1027 __qlcnic_83xx_process_aen(adapter);
068a8d19 1028 } else {
5bf93251 1029 if (mbx->rsp_status != rsp_status)
068a8d19
MC		 1030 qlcnic_83xx_notify_mbx_response(mbx);
1031 }
d1a1105e 1032 }
068a8d19 1033 spin_unlock_irqrestore(&mbx->aen_lock, flags);
d1a1105e
RB		 1034}
1035
7ed3ce48
RB		 1036static void qlcnic_83xx_mbx_poll_work(struct work_struct *work)
1037{
1038 struct qlcnic_adapter *adapter;
1039
1040 adapter = container_of(work, struct qlcnic_adapter, mbx_poll_work.work);
1041
1042 if (!test_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
1043 return;
1044
1045 qlcnic_83xx_process_aen(adapter);
1046 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work,
1047 (HZ / 10));
1048}
1049
1050void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *adapter)
1051{
1052 if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
1053 return;
1054
1055 INIT_DELAYED_WORK(&adapter->mbx_poll_work, qlcnic_83xx_mbx_poll_work);
79da4d08 1056 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work, 0);
7ed3ce48
RB		 1057}
1058
1059void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *adapter)
1060{
1061 if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
1062 return;
1063 cancel_delayed_work_sync(&adapter->mbx_poll_work);
1064}
1065
7f966452
SC		 1066static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter)
1067{
1068 int index, i, err, sds_mbx_size;
1069 u32 *buf, intrpt_id, intr_mask;
1070 u16 context_id;
1071 u8 num_sds;
1072 struct qlcnic_cmd_args cmd;
1073 struct qlcnic_host_sds_ring *sds;
1074 struct qlcnic_sds_mbx sds_mbx;
1075 struct qlcnic_add_rings_mbx_out *mbx_out;
1076 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1077 struct qlcnic_hardware_context *ahw = adapter->ahw;
1078
1079 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1080 context_id = recv_ctx->context_id;
34e8c406 1081 num_sds = adapter->drv_sds_rings - QLCNIC_MAX_SDS_RINGS;
7f966452
SC		 1082 ahw->hw_ops->alloc_mbx_args(&cmd, adapter,
1083 QLCNIC_CMD_ADD_RCV_RINGS);
1084 cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16);
1085
1086 /* set up status rings, mbx 2-81 */
1087 index = 2;
34e8c406 1088 for (i = 8; i < adapter->drv_sds_rings; i++) {
7f966452
SC		 1089 memset(&sds_mbx, 0, sds_mbx_size);
1090 sds = &recv_ctx->sds_rings[i];
1091 sds->consumer = 0;
1092 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
a96227e6
SS		 1093 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1094 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
7f966452
SC		 1095 sds_mbx.sds_ring_size = sds->num_desc;
1096
1097 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1098 intrpt_id = ahw->intr_tbl[i].id;
1099 else
1100 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1101
1102 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1103 sds_mbx.intrpt_id = intrpt_id;
1104 else
1105 sds_mbx.intrpt_id = 0xffff;
1106 sds_mbx.intrpt_val = 0;
1107 buf = &cmd.req.arg[index];
1108 memcpy(buf, &sds_mbx, sds_mbx_size);
1109 index += sds_mbx_size / sizeof(u32);
1110 }
1111
1112 /* send the mailbox command */
1113 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1114 if (err) {
1115 dev_err(&adapter->pdev->dev,
1116 "Failed to add rings %d\n", err);
1117 goto out;
1118 }
1119
1120 mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1];
1121 index = 0;
1122 /* status descriptor ring */
34e8c406 1123 for (i = 8; i < adapter->drv_sds_rings; i++) {
7f966452
SC		 1124 sds = &recv_ctx->sds_rings[i];
1125 sds->crb_sts_consumer = ahw->pci_base0 +
1126 mbx_out->host_csmr[index];
1127 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1128 intr_mask = ahw->intr_tbl[i].src;
1129 else
1130 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1131
1132 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1133 index++;
1134 }
1135out:
1136 qlcnic_free_mbx_args(&cmd);
1137 return err;
1138}
1139
7cb03b23
RB		 1140void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter)
1141{
1142 int err;
1143 u32 temp = 0;
1144 struct qlcnic_cmd_args cmd;
1145 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1146
1147 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX))
1148 return;
1149
1150 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1151 cmd.req.arg[0] |= (0x3 << 29);
1152
1153 if (qlcnic_sriov_pf_check(adapter))
1154 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp);
1155
1156 cmd.req.arg[1] = recv_ctx->context_id | temp;
1157 err = qlcnic_issue_cmd(adapter, &cmd);
1158 if (err)
1159 dev_err(&adapter->pdev->dev,
1160 "Failed to destroy rx ctx in firmware\n");
1161
1162 recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
1163 qlcnic_free_mbx_args(&cmd);
1164}
1165
7f966452
SC		 1166int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
1167{
1168 int i, err, index, sds_mbx_size, rds_mbx_size;
1169 u8 num_sds, num_rds;
1170 u32 *buf, intrpt_id, intr_mask, cap = 0;
1171 struct qlcnic_host_sds_ring *sds;
1172 struct qlcnic_host_rds_ring *rds;
1173 struct qlcnic_sds_mbx sds_mbx;
1174 struct qlcnic_rds_mbx rds_mbx;
1175 struct qlcnic_cmd_args cmd;
1176 struct qlcnic_rcv_mbx_out *mbx_out;
1177 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1178 struct qlcnic_hardware_context *ahw = adapter->ahw;
1179 num_rds = adapter->max_rds_rings;
1180
34e8c406
HM		 1181 if (adapter->drv_sds_rings <= QLCNIC_MAX_SDS_RINGS)
1182 num_sds = adapter->drv_sds_rings;
7f966452 1183 else
34e8c406 1184 num_sds = QLCNIC_MAX_SDS_RINGS;
7f966452
SC		 1185
1186 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1187 rds_mbx_size = sizeof(struct qlcnic_rds_mbx);
1188 cap = QLCNIC_CAP0_LEGACY_CONTEXT;
1189
1190 if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP)
1191 cap |= QLC_83XX_FW_CAP_LRO_MSS;
1192
1193 /* set mailbox hdr and capabilities */
b6b4316c
SS		 1194 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1195 QLCNIC_CMD_CREATE_RX_CTX);
1196 if (err)
1197 return err;
7cb03b23
RB		 1198
1199 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1200 cmd.req.arg[0] |= (0x3 << 29);
1201
7f966452
SC		 1202 cmd.req.arg[1] = cap;
1203 cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) |
1204 (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16);
7cb03b23
RB		 1205
1206 if (qlcnic_sriov_pf_check(adapter))
1207 qlcnic_pf_set_interface_id_create_rx_ctx(adapter,
1208 &cmd.req.arg[6]);
7f966452
SC		 1209 /* set up status rings, mbx 8-57/87 */
1210 index = QLC_83XX_HOST_SDS_MBX_IDX;
1211 for (i = 0; i < num_sds; i++) {
1212 memset(&sds_mbx, 0, sds_mbx_size);
1213 sds = &recv_ctx->sds_rings[i];
1214 sds->consumer = 0;
1215 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
a96227e6
SS		 1216 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1217 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
7f966452
SC		 1218 sds_mbx.sds_ring_size = sds->num_desc;
1219 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1220 intrpt_id = ahw->intr_tbl[i].id;
1221 else
1222 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1223 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1224 sds_mbx.intrpt_id = intrpt_id;
1225 else
1226 sds_mbx.intrpt_id = 0xffff;
1227 sds_mbx.intrpt_val = 0;
1228 buf = &cmd.req.arg[index];
1229 memcpy(buf, &sds_mbx, sds_mbx_size);
1230 index += sds_mbx_size / sizeof(u32);
1231 }
1232 /* set up receive rings, mbx 88-111/135 */
1233 index = QLCNIC_HOST_RDS_MBX_IDX;
1234 rds = &recv_ctx->rds_rings[0];
1235 rds->producer = 0;
1236 memset(&rds_mbx, 0, rds_mbx_size);
a96227e6
SS		 1237 rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr);
1238 rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr);
7f966452
SC		 1239 rds_mbx.reg_ring_sz = rds->dma_size;
1240 rds_mbx.reg_ring_len = rds->num_desc;
1241 /* Jumbo ring */
1242 rds = &recv_ctx->rds_rings[1];
1243 rds->producer = 0;
a96227e6
SS		 1244 rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr);
1245 rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr);
7f966452
SC		 1246 rds_mbx.jmb_ring_sz = rds->dma_size;
1247 rds_mbx.jmb_ring_len = rds->num_desc;
1248 buf = &cmd.req.arg[index];
1249 memcpy(buf, &rds_mbx, rds_mbx_size);
1250
1251 /* send the mailbox command */
1252 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1253 if (err) {
1254 dev_err(&adapter->pdev->dev,
1255 "Failed to create Rx ctx in firmware%d\n", err);
1256 goto out;
1257 }
1258 mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1];
1259 recv_ctx->context_id = mbx_out->ctx_id;
1260 recv_ctx->state = mbx_out->state;
1261 recv_ctx->virt_port = mbx_out->vport_id;
1262 dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n",
1263 recv_ctx->context_id, recv_ctx->state);
1264 /* Receive descriptor ring */
1265 /* Standard ring */
1266 rds = &recv_ctx->rds_rings[0];
1267 rds->crb_rcv_producer = ahw->pci_base0 +
1268 mbx_out->host_prod[0].reg_buf;
1269 /* Jumbo ring */
1270 rds = &recv_ctx->rds_rings[1];
1271 rds->crb_rcv_producer = ahw->pci_base0 +
1272 mbx_out->host_prod[0].jmb_buf;
1273 /* status descriptor ring */
1274 for (i = 0; i < num_sds; i++) {
1275 sds = &recv_ctx->sds_rings[i];
1276 sds->crb_sts_consumer = ahw->pci_base0 +
1277 mbx_out->host_csmr[i];
1278 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1279 intr_mask = ahw->intr_tbl[i].src;
1280 else
1281 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1282 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1283 }
1284
34e8c406 1285 if (adapter->drv_sds_rings > QLCNIC_MAX_SDS_RINGS)
7f966452
SC		 1286 err = qlcnic_83xx_add_rings(adapter);
1287out:
1288 qlcnic_free_mbx_args(&cmd);
1289 return err;
1290}
1291
7cb03b23
RB		 1292void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter,
1293 struct qlcnic_host_tx_ring *tx_ring)
1294{
1295 struct qlcnic_cmd_args cmd;
1296 u32 temp = 0;
1297
1298 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX))
1299 return;
1300
1301 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1302 cmd.req.arg[0] |= (0x3 << 29);
1303
1304 if (qlcnic_sriov_pf_check(adapter))
1305 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp);
1306
1307 cmd.req.arg[1] = tx_ring->ctx_id | temp;
1308 if (qlcnic_issue_cmd(adapter, &cmd))
1309 dev_err(&adapter->pdev->dev,
1310 "Failed to destroy tx ctx in firmware\n");
1311 qlcnic_free_mbx_args(&cmd);
1312}
1313
7f966452
SC		 1314int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter,
1315 struct qlcnic_host_tx_ring *tx, int ring)
1316{
1317 int err;
1318 u16 msix_id;
7cb03b23 1319 u32 *buf, intr_mask, temp = 0;
7f966452
SC		 1320 struct qlcnic_cmd_args cmd;
1321 struct qlcnic_tx_mbx mbx;
1322 struct qlcnic_tx_mbx_out *mbx_out;
1323 struct qlcnic_hardware_context *ahw = adapter->ahw;
da6c8063 1324 u32 msix_vector;
7f966452
SC		 1325
1326 /* Reset host resources */
1327 tx->producer = 0;
1328 tx->sw_consumer = 0;
1329 *(tx->hw_consumer) = 0;
1330
1331 memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx));
1332
1333 /* setup mailbox inbox registerss */
a96227e6
SS		 1334 mbx.phys_addr_low = LSD(tx->phys_addr);
1335 mbx.phys_addr_high = MSD(tx->phys_addr);
1336 mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr);
1337 mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr);
7f966452 1338 mbx.size = tx->num_desc;
da6c8063
RB		 1339 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
1340 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
34e8c406 1341 msix_vector = adapter->drv_sds_rings + ring;
da6c8063 1342 else
34e8c406 1343 msix_vector = adapter->drv_sds_rings - 1;
da6c8063
RB		 1344 msix_id = ahw->intr_tbl[msix_vector].id;
1345 } else {
7f966452 1346 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
da6c8063
RB		 1347 }
1348
7f966452
SC		 1349 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1350 mbx.intr_id = msix_id;
1351 else
1352 mbx.intr_id = 0xffff;
1353 mbx.src = 0;
1354
b6b4316c
SS		 1355 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
1356 if (err)
1357 return err;
7cb03b23
RB		 1358
1359 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1360 cmd.req.arg[0] |= (0x3 << 29);
1361
1362 if (qlcnic_sriov_pf_check(adapter))
1363 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp);
1364
7f966452 1365 cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT;
34e8c406
HM		 1366 cmd.req.arg[5] = QLCNIC_SINGLE_RING | temp;
1367
7f966452
SC		 1368 buf = &cmd.req.arg[6];
1369 memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx));
1370 /* send the mailbox command*/
1371 err = qlcnic_issue_cmd(adapter, &cmd);
1372 if (err) {
cb9327d5
HM		 1373 netdev_err(adapter->netdev,
1374 "Failed to create Tx ctx in firmware 0x%x\n", err);
7f966452
SC		 1375 goto out;
1376 }
1377 mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2];
1378 tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod;
1379 tx->ctx_id = mbx_out->ctx_id;
da6c8063
RB		 1380 if ((adapter->flags & QLCNIC_MSIX_ENABLED) &&
1381 !(adapter->flags & QLCNIC_TX_INTR_SHARED)) {
34e8c406 1382 intr_mask = ahw->intr_tbl[adapter->drv_sds_rings + ring].src;
7f966452
SC		 1383 tx->crb_intr_mask = ahw->pci_base0 + intr_mask;
1384 }
cb9327d5
HM		 1385 netdev_info(adapter->netdev,
1386 "Tx Context[0x%x] Created, state:0x%x\n",
1387 tx->ctx_id, mbx_out->state);
7f966452
SC		 1388out:
1389 qlcnic_free_mbx_args(&cmd);
1390 return err;
1391}
1392
13a82b44 1393static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test,
34e8c406 1394 u8 num_sds_ring)
ba4468db
JK		 1395{
1396 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1397 struct qlcnic_host_sds_ring *sds_ring;
1398 struct qlcnic_host_rds_ring *rds_ring;
13a82b44 1399 u16 adapter_state = adapter->is_up;
ba4468db
JK		 1400 u8 ring;
1401 int ret;
1402
1403 netif_device_detach(netdev);
1404
1405 if (netif_running(netdev))
1406 __qlcnic_down(adapter, netdev);
1407
1408 qlcnic_detach(adapter);
1409
34e8c406 1410 adapter->drv_sds_rings = QLCNIC_SINGLE_RING;
ba4468db
JK		 1411 adapter->ahw->diag_test = test;
1412 adapter->ahw->linkup = 0;
1413
1414 ret = qlcnic_attach(adapter);
1415 if (ret) {
1416 netif_device_attach(netdev);
1417 return ret;
1418 }
1419
1420 ret = qlcnic_fw_create_ctx(adapter);
1421 if (ret) {
1422 qlcnic_detach(adapter);
13a82b44 1423 if (adapter_state == QLCNIC_ADAPTER_UP_MAGIC) {
34e8c406 1424 adapter->drv_sds_rings = num_sds_ring;
13a82b44
MC		 1425 qlcnic_attach(adapter);
1426 }
ba4468db
JK		 1427 netif_device_attach(netdev);
1428 return ret;
1429 }
1430
1431 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1432 rds_ring = &adapter->recv_ctx->rds_rings[ring];
1433 qlcnic_post_rx_buffers(adapter, rds_ring, ring);
1434 }
1435
1436 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
34e8c406 1437 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
ba4468db 1438 sds_ring = &adapter->recv_ctx->sds_rings[ring];
2cc5752e 1439 qlcnic_enable_sds_intr(adapter, sds_ring);
ba4468db
JK		 1440 }
1441 }
1442
1443 if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
ba4468db
JK		 1444 adapter->ahw->loopback_state = 0;
1445 adapter->ahw->hw_ops->setup_link_event(adapter, 1);
1446 }
1447
1448 set_bit(__QLCNIC_DEV_UP, &adapter->state);
1449 return 0;
1450}
1451
1452static void qlcnic_83xx_diag_free_res(struct net_device *netdev,
34e8c406 1453 u8 drv_sds_rings)
ba4468db
JK		 1454{
1455 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1456 struct qlcnic_host_sds_ring *sds_ring;
e49df794 1457 int ring;
ba4468db
JK		 1458
1459 clear_bit(__QLCNIC_DEV_UP, &adapter->state);
1460 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
34e8c406 1461 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
ba4468db 1462 sds_ring = &adapter->recv_ctx->sds_rings[ring];
e49df794 1463 if (adapter->flags & QLCNIC_MSIX_ENABLED)
2cc5752e 1464 qlcnic_disable_sds_intr(adapter, sds_ring);
ba4468db
JK		 1465 }
1466 }
1467
1468 qlcnic_fw_destroy_ctx(adapter);
1469 qlcnic_detach(adapter);
1470
ba4468db 1471 adapter->ahw->diag_test = 0;
34e8c406 1472 adapter->drv_sds_rings = drv_sds_rings;
ba4468db
JK		 1473
1474 if (qlcnic_attach(adapter))
1475 goto out;
1476
1477 if (netif_running(netdev))
1478 __qlcnic_up(adapter, netdev);
79da4d08 1479
ba4468db
JK		 1480out:
1481 netif_device_attach(netdev);
1482}
1483
21041400 1484static void qlcnic_83xx_get_beacon_state(struct qlcnic_adapter *adapter)
a0431589
HM		 1485{
1486 struct qlcnic_hardware_context *ahw = adapter->ahw;
1487 struct qlcnic_cmd_args cmd;
1488 u8 beacon_state;
1489 int err = 0;
1490
1491 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LED_CONFIG);
1492 if (!err) {
1493 err = qlcnic_issue_cmd(adapter, &cmd);
1494 if (!err) {
1495 beacon_state = cmd.rsp.arg[4];
1496 if (beacon_state == QLCNIC_BEACON_DISABLE)
1497 ahw->beacon_state = QLC_83XX_BEACON_OFF;
1498 else if (beacon_state == QLC_83XX_ENABLE_BEACON)
1499 ahw->beacon_state = QLC_83XX_BEACON_ON;
1500 }
1501 } else {
1502 netdev_err(adapter->netdev, "Get beacon state failed, err=%d\n",
1503 err);
1504 }
1505
1506 qlcnic_free_mbx_args(&cmd);
1507
1508 return;
1509}
1510
319ecf12
SC		 1511int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state,
1512 u32 beacon)
1513{
1514 struct qlcnic_cmd_args cmd;
1515 u32 mbx_in;
1516 int i, status = 0;
1517
1518 if (state) {
1519 /* Get LED configuration */
b6b4316c
SS		 1520 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1521 QLCNIC_CMD_GET_LED_CONFIG);
1522 if (status)
1523 return status;
1524
319ecf12
SC		 1525 status = qlcnic_issue_cmd(adapter, &cmd);
1526 if (status) {
1527 dev_err(&adapter->pdev->dev,
1528 "Get led config failed.\n");
1529 goto mbx_err;
1530 } else {
1531 for (i = 0; i < 4; i++)
1532 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1];
1533 }
1534 qlcnic_free_mbx_args(&cmd);
1535 /* Set LED Configuration */
1536 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) |
1537 LSW(QLC_83XX_LED_CONFIG);
b6b4316c
SS		 1538 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1539 QLCNIC_CMD_SET_LED_CONFIG);
1540 if (status)
1541 return status;
1542
319ecf12
SC		 1543 cmd.req.arg[1] = mbx_in;
1544 cmd.req.arg[2] = mbx_in;
1545 cmd.req.arg[3] = mbx_in;
1546 if (beacon)
1547 cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON;
1548 status = qlcnic_issue_cmd(adapter, &cmd);
1549 if (status) {
1550 dev_err(&adapter->pdev->dev,
1551 "Set led config failed.\n");
1552 }
1553mbx_err:
1554 qlcnic_free_mbx_args(&cmd);
1555 return status;
1556
1557 } else {
1558 /* Restoring default LED configuration */
b6b4316c
SS		 1559 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1560 QLCNIC_CMD_SET_LED_CONFIG);
1561 if (status)
1562 return status;
1563
319ecf12
SC		 1564 cmd.req.arg[1] = adapter->ahw->mbox_reg[0];
1565 cmd.req.arg[2] = adapter->ahw->mbox_reg[1];
1566 cmd.req.arg[3] = adapter->ahw->mbox_reg[2];
1567 if (beacon)
1568 cmd.req.arg[4] = adapter->ahw->mbox_reg[3];
1569 status = qlcnic_issue_cmd(adapter, &cmd);
1570 if (status)
1571 dev_err(&adapter->pdev->dev,
1572 "Restoring led config failed.\n");
1573 qlcnic_free_mbx_args(&cmd);
1574 return status;
1575 }
1576}
1577
d16951d9
HM		 1578int qlcnic_83xx_set_led(struct net_device *netdev,
1579 enum ethtool_phys_id_state state)
1580{
1581 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1582 int err = -EIO, active = 1;
1583
1584 if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1585 netdev_warn(netdev,
1586 "LED test is not supported in non-privileged mode\n");
1587 return -EOPNOTSUPP;
1588 }
1589
1590 switch (state) {
1591 case ETHTOOL_ID_ACTIVE:
1592 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state))
1593 return -EBUSY;
1594
1595 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1596 break;
1597
1598 err = qlcnic_83xx_config_led(adapter, active, 0);
1599 if (err)
1600 netdev_err(netdev, "Failed to set LED blink state\n");
1601 break;
1602 case ETHTOOL_ID_INACTIVE:
1603 active = 0;
1604
1605 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1606 break;
1607
1608 err = qlcnic_83xx_config_led(adapter, active, 0);
1609 if (err)
1610 netdev_err(netdev, "Failed to reset LED blink state\n");
1611 break;
1612
1613 default:
1614 return -EINVAL;
1615 }
1616
1617 if (!active || err)
1618 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
1619
1620 return err;
1621}
1622
9b0fff2a 1623void qlcnic_83xx_initialize_nic(struct qlcnic_adapter *adapter, int enable)
7f966452
SC		 1624{
1625 struct qlcnic_cmd_args cmd;
1626 int status;
1627
f8468331
RB		 1628 if (qlcnic_sriov_vf_check(adapter))
1629 return;
1630
9b0fff2a 1631 if (enable)
b6b4316c
SS		 1632 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1633 QLCNIC_CMD_INIT_NIC_FUNC);
9b0fff2a 1634 else
b6b4316c
SS		 1635 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1636 QLCNIC_CMD_STOP_NIC_FUNC);
b6b4316c 1637
9b0fff2a
SC		 1638 if (status)
1639 return;
1640
1641 cmd.req.arg[1] = QLC_REGISTER_LB_IDC | QLC_INIT_FW_RESOURCES;
3720bf79
SC		 1642
1643 if (adapter->dcb)
1644 cmd.req.arg[1] |= QLC_REGISTER_DCB_AEN;
1645
7f966452
SC		 1646 status = qlcnic_issue_cmd(adapter, &cmd);
1647 if (status)
1648 dev_err(&adapter->pdev->dev,
1649 "Failed to %s in NIC IDC function event.\n",
1650 (enable ? "register" : "unregister"));
1651
1652 qlcnic_free_mbx_args(&cmd);
1653}
1654
21041400 1655static int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter)
7f966452
SC		 1656{
1657 struct qlcnic_cmd_args cmd;
1658 int err;
1659
b6b4316c
SS		 1660 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG);
1661 if (err)
1662 return err;
1663
7f966452
SC		 1664 cmd.req.arg[1] = adapter->ahw->port_config;
1665 err = qlcnic_issue_cmd(adapter, &cmd);
1666 if (err)
1667 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n");
1668 qlcnic_free_mbx_args(&cmd);
1669 return err;
1670}
1671
21041400 1672static int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter)
7f966452
SC		 1673{
1674 struct qlcnic_cmd_args cmd;
1675 int err;
1676
b6b4316c
SS		 1677 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG);
1678 if (err)
1679 return err;
1680
7f966452
SC		 1681 err = qlcnic_issue_cmd(adapter, &cmd);
1682 if (err)
1683 dev_info(&adapter->pdev->dev, "Get Port config failed\n");
1684 else
1685 adapter->ahw->port_config = cmd.rsp.arg[1];
1686 qlcnic_free_mbx_args(&cmd);
1687 return err;
1688}
1689
1690int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable)
1691{
1692 int err;
1693 u32 temp;
1694 struct qlcnic_cmd_args cmd;
1695
b6b4316c
SS		 1696 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT);
1697 if (err)
1698 return err;
1699
7f966452
SC		 1700 temp = adapter->recv_ctx->context_id << 16;
1701 cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp;
1702 err = qlcnic_issue_cmd(adapter, &cmd);
1703 if (err)
1704 dev_info(&adapter->pdev->dev,
1705 "Setup linkevent mailbox failed\n");
1706 qlcnic_free_mbx_args(&cmd);
1707 return err;
1708}
1709
7cb03b23
RB		 1710static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter,
1711 u32 *interface_id)
1712{
1713 if (qlcnic_sriov_pf_check(adapter)) {
b3f7de83 1714 qlcnic_alloc_lb_filters_mem(adapter);
7cb03b23 1715 qlcnic_pf_set_interface_id_promisc(adapter, interface_id);
72ebe349 1716 adapter->rx_mac_learn = true;
7cb03b23
RB		 1717 } else {
1718 if (!qlcnic_sriov_vf_check(adapter))
1719 *interface_id = adapter->recv_ctx->context_id << 16;
1720 }
1721}
1722
7f966452
SC		 1723int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
1724{
068a8d19 1725 struct qlcnic_cmd_args *cmd = NULL;
7cb03b23 1726 u32 temp = 0;
068a8d19 1727 int err;
7f966452
SC		 1728
1729 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1730 return -EIO;
1731
068a8d19
MC		 1732 cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
1733 if (!cmd)
1734 return -ENOMEM;
1735
1736 err = qlcnic_alloc_mbx_args(cmd, adapter,
b6b4316c
SS		 1737 QLCNIC_CMD_CONFIGURE_MAC_RX_MODE);
1738 if (err)
068a8d19 1739 goto out;
b6b4316c 1740
068a8d19 1741 cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
7cb03b23 1742 qlcnic_83xx_set_interface_id_promisc(adapter, &temp);
9eb0948a
SC		 1743
1744 if (qlcnic_84xx_check(adapter) && qlcnic_sriov_pf_check(adapter))
1745 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1746
154d0c81 1747 cmd->req.arg[1] = mode | temp;
068a8d19
MC		 1748 err = qlcnic_issue_cmd(adapter, cmd);
1749 if (!err)
1750 return err;
7f966452 1751
068a8d19
MC		 1752 qlcnic_free_mbx_args(cmd);
1753
1754out:
1755 kfree(cmd);
7f966452
SC		 1756 return err;
1757}
1758
ba4468db
JK		 1759int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode)
1760{
1761 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1762 struct qlcnic_hardware_context *ahw = adapter->ahw;
34e8c406 1763 u8 drv_sds_rings = adapter->drv_sds_rings;
18afc102 1764 u8 drv_tx_rings = adapter->drv_tx_rings;
34e8c406 1765 int ret = 0, loop = 0;
ba4468db 1766
ba4468db 1767 if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
4690a7e4
SC		 1768 netdev_warn(netdev,
1769 "Loopback test not supported in non privileged mode\n");
b9c11984 1770 return -ENOTSUPP;
ba4468db
JK		 1771 }
1772
4690a7e4
SC		 1773 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1774 netdev_info(netdev, "Device is resetting\n");
ba4468db 1775 return -EBUSY;
4690a7e4
SC		 1776 }
1777
1778 if (qlcnic_get_diag_lock(adapter)) {
1779 netdev_info(netdev, "Device is in diagnostics mode\n");
1780 return -EBUSY;
1781 }
1782
1783 netdev_info(netdev, "%s loopback test in progress\n",
1784 mode == QLCNIC_ILB_MODE ? "internal" : "external");
ba4468db 1785
13a82b44 1786 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST,
34e8c406 1787 drv_sds_rings);
ba4468db
JK		 1788 if (ret)
1789 goto fail_diag_alloc;
1790
1791 ret = qlcnic_83xx_set_lb_mode(adapter, mode);
1792 if (ret)
1793 goto free_diag_res;
1794
1795 /* Poll for link up event before running traffic */
1796 do {
2c4a7878 1797 msleep(QLC_83XX_LB_MSLEEP_COUNT);
d1a1105e 1798
2c4a7878
JK		 1799 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1800 netdev_info(netdev,
1801 "Device is resetting, free LB test resources\n");
b9c11984 1802 ret = -EBUSY;
2c4a7878
JK		 1803 goto free_diag_res;
1804 }
1805 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1806 netdev_info(netdev,
1807 "Firmware didn't sent link up event to loopback request\n");
b9c11984 1808 ret = -ETIMEDOUT;
ba4468db
JK		 1809 qlcnic_83xx_clear_lb_mode(adapter, mode);
1810 goto free_diag_res;
1811 }
1812 } while ((adapter->ahw->linkup && ahw->has_link_events) != 1);
1813
1814 ret = qlcnic_do_lb_test(adapter, mode);
1815
1816 qlcnic_83xx_clear_lb_mode(adapter, mode);
1817
1818free_diag_res:
34e8c406 1819 qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
ba4468db
JK		 1820
1821fail_diag_alloc:
34e8c406 1822 adapter->drv_sds_rings = drv_sds_rings;
18afc102 1823 adapter->drv_tx_rings = drv_tx_rings;
4690a7e4 1824 qlcnic_release_diag_lock(adapter);
ba4468db
JK		 1825 return ret;
1826}
1827
77bead46
MC		 1828static void qlcnic_extend_lb_idc_cmpltn_wait(struct qlcnic_adapter *adapter,
1829 u32 *max_wait_count)
1830{
1831 struct qlcnic_hardware_context *ahw = adapter->ahw;
1832 int temp;
1833
6d3be300 1834 netdev_info(adapter->netdev, "Received loopback IDC time extend event for 0x%x seconds\n",
77bead46
MC		 1835 ahw->extend_lb_time);
1836 temp = ahw->extend_lb_time * 1000;
1837 *max_wait_count += temp / QLC_83XX_LB_MSLEEP_COUNT;
1838 ahw->extend_lb_time = 0;
1839}
1840
21041400 1841static int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
7f966452
SC		 1842{
1843 struct qlcnic_hardware_context *ahw = adapter->ahw;
2c4a7878 1844 struct net_device *netdev = adapter->netdev;
77bead46 1845 u32 config, max_wait_count;
629263ac 1846 int status = 0, loop = 0;
7f966452 1847
77bead46
MC		 1848 ahw->extend_lb_time = 0;
1849 max_wait_count = QLC_83XX_LB_WAIT_COUNT;
7f966452
SC		 1850 status = qlcnic_83xx_get_port_config(adapter);
1851 if (status)
1852 return status;
1853
1854 config = ahw->port_config;
b9c11984
JK		 1855
1856 /* Check if port is already in loopback mode */
1857 if ((config & QLC_83XX_CFG_LOOPBACK_HSS) ||
1858 (config & QLC_83XX_CFG_LOOPBACK_EXT)) {
1859 netdev_err(netdev,
1860 "Port already in Loopback mode.\n");
1861 return -EINPROGRESS;
1862 }
1863
629263ac 1864 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
7f966452
SC		 1865
1866 if (mode == QLCNIC_ILB_MODE)
1867 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS;
1868 if (mode == QLCNIC_ELB_MODE)
1869 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT;
1870
1871 status = qlcnic_83xx_set_port_config(adapter);
1872 if (status) {
2c4a7878
JK		 1873 netdev_err(netdev,
1874 "Failed to Set Loopback Mode = 0x%x.\n",
1875 ahw->port_config);
7f966452 1876 ahw->port_config = config;
629263ac 1877 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
7f966452
SC		 1878 return status;
1879 }
1880
9a05f92b 1881 /* Wait for Link and IDC Completion AEN */
629263ac 1882 do {
2c4a7878 1883 msleep(QLC_83XX_LB_MSLEEP_COUNT);
d1a1105e 1884
2c4a7878
JK		 1885 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1886 netdev_info(netdev,
1887 "Device is resetting, free LB test resources\n");
1888 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
b9c11984 1889 return -EBUSY;
2c4a7878 1890 }
77bead46
MC		 1891
1892 if (ahw->extend_lb_time)
1893 qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1894 &max_wait_count);
1895
1896 if (loop++ > max_wait_count) {
1897 netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1898 __func__);
629263ac 1899 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
9a05f92b 1900 qlcnic_83xx_clear_lb_mode(adapter, mode);
b9c11984 1901 return -ETIMEDOUT;
629263ac
SC		 1902 }
1903 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1904
7f966452
SC		 1905 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1906 QLCNIC_MAC_ADD);
1907 return status;
1908}
1909
21041400 1910static int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
7f966452
SC		 1911{
1912 struct qlcnic_hardware_context *ahw = adapter->ahw;
77bead46 1913 u32 config = ahw->port_config, max_wait_count;
2c4a7878 1914 struct net_device *netdev = adapter->netdev;
629263ac 1915 int status = 0, loop = 0;
7f966452 1916
77bead46
MC		 1917 ahw->extend_lb_time = 0;
1918 max_wait_count = QLC_83XX_LB_WAIT_COUNT;
629263ac 1919 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
7f966452
SC		 1920 if (mode == QLCNIC_ILB_MODE)
1921 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS;
1922 if (mode == QLCNIC_ELB_MODE)
1923 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT;
1924
1925 status = qlcnic_83xx_set_port_config(adapter);
1926 if (status) {
2c4a7878
JK		 1927 netdev_err(netdev,
1928 "Failed to Clear Loopback Mode = 0x%x.\n",
1929 ahw->port_config);
7f966452 1930 ahw->port_config = config;
629263ac 1931 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
7f966452
SC		 1932 return status;
1933 }
1934
9a05f92b 1935 /* Wait for Link and IDC Completion AEN */
629263ac 1936 do {
2c4a7878 1937 msleep(QLC_83XX_LB_MSLEEP_COUNT);
d1a1105e 1938
2c4a7878
JK		 1939 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1940 netdev_info(netdev,
1941 "Device is resetting, free LB test resources\n");
1942 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
b9c11984 1943 return -EBUSY;
2c4a7878
JK		 1944 }
1945
77bead46
MC		 1946 if (ahw->extend_lb_time)
1947 qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1948 &max_wait_count);
1949
1950 if (loop++ > max_wait_count) {
1951 netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1952 __func__);
629263ac 1953 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
b9c11984 1954 return -ETIMEDOUT;
629263ac
SC		 1955 }
1956 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1957
7f966452
SC		 1958 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1959 QLCNIC_MAC_DEL);
1960 return status;
1961}
1962
7cb03b23
RB		 1963static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter,
1964 u32 *interface_id)
1965{
1966 if (qlcnic_sriov_pf_check(adapter)) {
1967 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id);
1968 } else {
1969 if (!qlcnic_sriov_vf_check(adapter))
1970 *interface_id = adapter->recv_ctx->context_id << 16;
1971 }
1972}
1973
7f966452
SC		 1974void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip,
1975 int mode)
1976{
1977 int err;
7cb03b23 1978 u32 temp = 0, temp_ip;
7f966452
SC		 1979 struct qlcnic_cmd_args cmd;
1980
b6b4316c
SS		 1981 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1982 QLCNIC_CMD_CONFIGURE_IP_ADDR);
1983 if (err)
1984 return;
1985
7cb03b23
RB		 1986 qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp);
1987
1988 if (mode == QLCNIC_IP_UP)
7f966452 1989 cmd.req.arg[1] = 1 | temp;
7cb03b23 1990 else
7f966452 1991 cmd.req.arg[1] = 2 | temp;
7f966452 1992
283c1c68
M		 1993 /*
1994 * Adapter needs IP address in network byte order.
1995 * But hardware mailbox registers go through writel(), hence IP address
1996 * gets swapped on big endian architecture.
1997 * To negate swapping of writel() on big endian architecture
1998 * use swab32(value).
1999 */
2000
2001 temp_ip = swab32(ntohl(ip));
2002 memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32));
7f966452
SC		 2003 err = qlcnic_issue_cmd(adapter, &cmd);
2004 if (err != QLCNIC_RCODE_SUCCESS)
2005 dev_err(&adapter->netdev->dev,
2006 "could not notify %s IP 0x%x request\n",
2007 (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
7cb03b23 2008
7f966452
SC		 2009 qlcnic_free_mbx_args(&cmd);
2010}
2011
2012int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode)
2013{
2014 int err;
2015 u32 temp, arg1;
2016 struct qlcnic_cmd_args cmd;
283c1c68
M		 2017 int lro_bit_mask;
2018
2019 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
7f966452
SC		 2020
2021 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2022 return 0;
2023
b6b4316c
SS		 2024 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO);
2025 if (err)
2026 return err;
2027
7f966452 2028 temp = adapter->recv_ctx->context_id << 16;
283c1c68 2029 arg1 = lro_bit_mask | temp;
7f966452
SC		 2030 cmd.req.arg[1] = arg1;
2031
2032 err = qlcnic_issue_cmd(adapter, &cmd);
2033 if (err)
2034 dev_info(&adapter->pdev->dev, "LRO config failed\n");
2035 qlcnic_free_mbx_args(&cmd);
2036
2037 return err;
2038}
2039
2040int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable)
2041{
2042 int err;
2043 u32 word;
2044 struct qlcnic_cmd_args cmd;
2045 const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
2046 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
2047 0x255b0ec26d5a56daULL };
2048
b6b4316c
SS		 2049 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS);
2050 if (err)
2051 return err;
7f966452
SC		 2052 /*
2053 * RSS request:
2054 * bits 3-0: Rsvd
2055 * 5-4: hash_type_ipv4
2056 * 7-6: hash_type_ipv6
2057 * 8: enable
2058 * 9: use indirection table
2059 * 16-31: indirection table mask
2060 */
2061 word = ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
2062 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
2063 ((u32)(enable & 0x1) << 8) |
2064 ((0x7ULL) << 16);
2065 cmd.req.arg[1] = (adapter->recv_ctx->context_id);
2066 cmd.req.arg[2] = word;
2067 memcpy(&cmd.req.arg[4], key, sizeof(key));
2068
2069 err = qlcnic_issue_cmd(adapter, &cmd);
2070
2071 if (err)
2072 dev_info(&adapter->pdev->dev, "RSS config failed\n");
2073 qlcnic_free_mbx_args(&cmd);
2074
2075 return err;
2076
2077}
2078
7cb03b23
RB		 2079static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter,
2080 u32 *interface_id)
2081{
2082 if (qlcnic_sriov_pf_check(adapter)) {
2083 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id);
2084 } else {
2085 if (!qlcnic_sriov_vf_check(adapter))
2086 *interface_id = adapter->recv_ctx->context_id << 16;
2087 }
2088}
2089
7f966452 2090int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
f80bc8fe 2091 u16 vlan_id, u8 op)
7f966452 2092{
068a8d19 2093 struct qlcnic_cmd_args *cmd = NULL;
7f966452 2094 struct qlcnic_macvlan_mbx mv;
068a8d19
MC		 2095 u32 *buf, temp = 0;
2096 int err;
7f966452
SC		 2097
2098 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2099 return -EIO;
2100
068a8d19
MC		 2101 cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
2102 if (!cmd)
2103 return -ENOMEM;
2104
2105 err = qlcnic_alloc_mbx_args(cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN);
7f966452 2106 if (err)
068a8d19
MC		 2107 goto out;
2108
2109 cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
7f966452 2110
91b7282b
RB		 2111 if (vlan_id)
2112 op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ?
2113 QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL;
2114
068a8d19 2115 cmd->req.arg[1] = op | (1 << 8);
7cb03b23 2116 qlcnic_83xx_set_interface_id_macaddr(adapter, &temp);
068a8d19 2117 cmd->req.arg[1] |= temp;
f80bc8fe 2118 mv.vlan = vlan_id;
a96227e6
SS		 2119 mv.mac_addr0 = addr[0];
2120 mv.mac_addr1 = addr[1];
2121 mv.mac_addr2 = addr[2];
2122 mv.mac_addr3 = addr[3];
2123 mv.mac_addr4 = addr[4];
2124 mv.mac_addr5 = addr[5];
068a8d19 2125 buf = &cmd->req.arg[2];
7f966452 2126 memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx));
068a8d19
MC		 2127 err = qlcnic_issue_cmd(adapter, cmd);
2128 if (!err)
2129 return err;
2130
2131 qlcnic_free_mbx_args(cmd);
2132out:
2133 kfree(cmd);
7f966452
SC		 2134 return err;
2135}
2136
2137void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr,
f80bc8fe 2138 u16 vlan_id)
7f966452
SC		 2139{
2140 u8 mac[ETH_ALEN];
2141 memcpy(&mac, addr, ETH_ALEN);
2142 qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD);
2143}
2144
a91e6810
FW		 2145static void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac,
2146 u8 type, struct qlcnic_cmd_args *cmd)
7f966452
SC		 2147{
2148 switch (type) {
2149 case QLCNIC_SET_STATION_MAC:
2150 case QLCNIC_SET_FAC_DEF_MAC:
2151 memcpy(&cmd->req.arg[2], mac, sizeof(u32));
2152 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16));
2153 break;
2154 }
2155 cmd->req.arg[1] = type;
2156}
2157
07a251c8
SS		 2158int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac,
2159 u8 function)
7f966452
SC		 2160{
2161 int err, i;
2162 struct qlcnic_cmd_args cmd;
2163 u32 mac_low, mac_high;
2164
b6b4316c
SS		 2165 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
2166 if (err)
2167 return err;
2168
7f966452
SC		 2169 qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd);
2170 err = qlcnic_issue_cmd(adapter, &cmd);
2171
2172 if (err == QLCNIC_RCODE_SUCCESS) {
2173 mac_low = cmd.rsp.arg[1];
2174 mac_high = cmd.rsp.arg[2];
2175
2176 for (i = 0; i < 2; i++)
2177 mac[i] = (u8) (mac_high >> ((1 - i) * 8));
2178 for (i = 2; i < 6; i++)
2179 mac[i] = (u8) (mac_low >> ((5 - i) * 8));
2180 } else {
2181 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n",
2182 err);
2183 err = -EIO;
2184 }
2185 qlcnic_free_mbx_args(&cmd);
2186 return err;
2187}
2188
a514722a 2189static int qlcnic_83xx_set_rx_intr_coal(struct qlcnic_adapter *adapter)
7f966452 2190{
7f966452 2191 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
a514722a
HM		 2192 struct qlcnic_cmd_args cmd;
2193 u16 temp;
2194 int err;
7f966452 2195
a514722a
HM		 2196 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2197 if (err)
2198 return err;
2199
2200 temp = adapter->recv_ctx->context_id;
2201 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_RX | temp << 16;
2202 temp = coal->rx_time_us;
2203 cmd.req.arg[2] = coal->rx_packets | temp << 16;
2204 cmd.req.arg[3] = coal->flag;
2205
2206 err = qlcnic_issue_cmd(adapter, &cmd);
2207 if (err != QLCNIC_RCODE_SUCCESS)
2208 netdev_err(adapter->netdev,
2209 "failed to set interrupt coalescing parameters\n");
2210
2211 qlcnic_free_mbx_args(&cmd);
2212
2213 return err;
2214}
2215
2216static int qlcnic_83xx_set_tx_intr_coal(struct qlcnic_adapter *adapter)
2217{
2218 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2219 struct qlcnic_cmd_args cmd;
2220 u16 temp;
2221 int err;
7f966452 2222
b6b4316c
SS		 2223 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2224 if (err)
a514722a 2225 return err;
b6b4316c 2226
a514722a
HM		 2227 temp = adapter->tx_ring->ctx_id;
2228 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_TX | temp << 16;
2229 temp = coal->tx_time_us;
2230 cmd.req.arg[2] = coal->tx_packets | temp << 16;
7f966452 2231 cmd.req.arg[3] = coal->flag;
a514722a 2232
7f966452
SC		 2233 err = qlcnic_issue_cmd(adapter, &cmd);
2234 if (err != QLCNIC_RCODE_SUCCESS)
a514722a
HM		 2235 netdev_err(adapter->netdev,
2236 "failed to set interrupt coalescing parameters\n");
2237
7f966452 2238 qlcnic_free_mbx_args(&cmd);
a514722a
HM		 2239
2240 return err;
2241}
2242
2243int qlcnic_83xx_set_rx_tx_intr_coal(struct qlcnic_adapter *adapter)
2244{
2245 int err = 0;
2246
2247 err = qlcnic_83xx_set_rx_intr_coal(adapter);
2248 if (err)
2249 netdev_err(adapter->netdev,
2250 "failed to set Rx coalescing parameters\n");
2251
2252 err = qlcnic_83xx_set_tx_intr_coal(adapter);
2253 if (err)
2254 netdev_err(adapter->netdev,
2255 "failed to set Tx coalescing parameters\n");
2256
2257 return err;
2258}
2259
2260int qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter,
2261 struct ethtool_coalesce *ethcoal)
2262{
2263 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2264 u32 rx_coalesce_usecs, rx_max_frames;
2265 u32 tx_coalesce_usecs, tx_max_frames;
2266 int err;
2267
2268 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2269 return -EIO;
2270
2271 tx_coalesce_usecs = ethcoal->tx_coalesce_usecs;
2272 tx_max_frames = ethcoal->tx_max_coalesced_frames;
2273 rx_coalesce_usecs = ethcoal->rx_coalesce_usecs;
2274 rx_max_frames = ethcoal->rx_max_coalesced_frames;
2275 coal->flag = QLCNIC_INTR_DEFAULT;
2276
2277 if ((coal->rx_time_us == rx_coalesce_usecs) &&
2278 (coal->rx_packets == rx_max_frames)) {
2279 coal->type = QLCNIC_INTR_COAL_TYPE_TX;
2280 coal->tx_time_us = tx_coalesce_usecs;
2281 coal->tx_packets = tx_max_frames;
2282 } else if ((coal->tx_time_us == tx_coalesce_usecs) &&
2283 (coal->tx_packets == tx_max_frames)) {
2284 coal->type = QLCNIC_INTR_COAL_TYPE_RX;
2285 coal->rx_time_us = rx_coalesce_usecs;
2286 coal->rx_packets = rx_max_frames;
2287 } else {
2288 coal->type = QLCNIC_INTR_COAL_TYPE_RX_TX;
2289 coal->rx_time_us = rx_coalesce_usecs;
2290 coal->rx_packets = rx_max_frames;
2291 coal->tx_time_us = tx_coalesce_usecs;
2292 coal->tx_packets = tx_max_frames;
2293 }
2294
2295 switch (coal->type) {
2296 case QLCNIC_INTR_COAL_TYPE_RX:
2297 err = qlcnic_83xx_set_rx_intr_coal(adapter);
2298 break;
2299 case QLCNIC_INTR_COAL_TYPE_TX:
2300 err = qlcnic_83xx_set_tx_intr_coal(adapter);
2301 break;
2302 case QLCNIC_INTR_COAL_TYPE_RX_TX:
2303 err = qlcnic_83xx_set_rx_tx_intr_coal(adapter);
2304 break;
2305 default:
2306 err = -EINVAL;
2307 netdev_err(adapter->netdev,
2308 "Invalid Interrupt coalescing type\n");
2309 break;
2310 }
2311
2312 return err;
7f966452
SC		 2313}
2314
2315static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
2316 u32 data[])
2317{
b1f5037f 2318 struct qlcnic_hardware_context *ahw = adapter->ahw;
7f966452
SC		 2319 u8 link_status, duplex;
2320 /* link speed */
2321 link_status = LSB(data[3]) & 1;
b1f5037f
RB		 2322 if (link_status) {
2323 ahw->link_speed = MSW(data[2]);
2324 duplex = LSB(MSW(data[3]));
2325 if (duplex)
2326 ahw->link_duplex = DUPLEX_FULL;
2327 else
2328 ahw->link_duplex = DUPLEX_HALF;
2329 } else {
2330 ahw->link_speed = SPEED_UNKNOWN;
2331 ahw->link_duplex = DUPLEX_UNKNOWN;
2332 }
2333
2334 ahw->link_autoneg = MSB(MSW(data[3]));
2335 ahw->module_type = MSB(LSW(data[3]));
2336 ahw->has_link_events = 1;
d9c602f0 2337 ahw->lb_mode = data[4] & QLCNIC_LB_MODE_MASK;
7f966452
SC		 2338 qlcnic_advert_link_change(adapter, link_status);
2339}
2340
a91e6810 2341static irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data)
7f966452 2342{
819bfe76 2343 u32 mask, resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
7f966452 2344 struct qlcnic_adapter *adapter = data;
068a8d19 2345 struct qlcnic_mailbox *mbx;
068a8d19 2346 unsigned long flags;
483202d5 2347
068a8d19
MC		 2348 mbx = adapter->ahw->mailbox;
2349 spin_lock_irqsave(&mbx->aen_lock, flags);
483202d5
JK		 2350 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
2351 if (!(resp & QLCNIC_SET_OWNER))
2352 goto out;
ac166700 2353
483202d5 2354 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
819bfe76 2355 if (event & QLCNIC_MBX_ASYNC_EVENT) {
d1a1105e 2356 __qlcnic_83xx_process_aen(adapter);
819bfe76
RB		 2357 } else {
2358 if (mbx->rsp_status != rsp_status)
2359 qlcnic_83xx_notify_mbx_response(mbx);
2360 else
2361 adapter->stats.mbx_spurious_intr++;
2362 }
068a8d19 2363
483202d5
JK		 2364out:
2365 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
2366 writel(0, adapter->ahw->pci_base0 + mask);
068a8d19 2367 spin_unlock_irqrestore(&mbx->aen_lock, flags);
7f966452
SC		 2368 return IRQ_HANDLED;
2369}
2370
7f966452
SC		 2371int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter,
2372 struct qlcnic_info *nic)
2373{
2374 int i, err = -EIO;
2375 struct qlcnic_cmd_args cmd;
2376
2377 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2378 dev_err(&adapter->pdev->dev,
2379 "%s: Error, invoked by non management func\n",
2380 __func__);
2381 return err;
2382 }
2383
b6b4316c
SS		 2384 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
2385 if (err)
2386 return err;
2387
7f966452
SC		 2388 cmd.req.arg[1] = (nic->pci_func << 16);
2389 cmd.req.arg[2] = 0x1 << 16;
2390 cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16);
2391 cmd.req.arg[4] = nic->capabilities;
2392 cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16);
2393 cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16);
2394 cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16);
2395 for (i = 8; i < 32; i++)
2396 cmd.req.arg[i] = 0;
2397
2398 err = qlcnic_issue_cmd(adapter, &cmd);
2399
2400 if (err != QLCNIC_RCODE_SUCCESS) {
2401 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n",
2402 err);
2403 err = -EIO;
2404 }
2405
2406 qlcnic_free_mbx_args(&cmd);
2407
2408 return err;
2409}
2410
2411int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter,
2412 struct qlcnic_info *npar_info, u8 func_id)
2413{
2414 int err;
2415 u32 temp;
2416 u8 op = 0;
2417 struct qlcnic_cmd_args cmd;
8af3f33d 2418 struct qlcnic_hardware_context *ahw = adapter->ahw;
7f966452 2419
b6b4316c
SS		 2420 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
2421 if (err)
2422 return err;
2423
8af3f33d 2424 if (func_id != ahw->pci_func) {
7f966452
SC		 2425 temp = func_id << 16;
2426 cmd.req.arg[1] = op | BIT_31 | temp;
2427 } else {
8af3f33d 2428 cmd.req.arg[1] = ahw->pci_func << 16;
7f966452
SC		 2429 }
2430 err = qlcnic_issue_cmd(adapter, &cmd);
2431 if (err) {
2432 dev_info(&adapter->pdev->dev,
2433 "Failed to get nic info %d\n", err);
2434 goto out;
2435 }
2436
2437 npar_info->op_type = cmd.rsp.arg[1];
2438 npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF;
2439 npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16;
2440 npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF;
2441 npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16;
2442 npar_info->capabilities = cmd.rsp.arg[4];
2443 npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF;
2444 npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16;
2445 npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF;
2446 npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16;
2447 npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF;
2448 npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16;
2449 if (cmd.rsp.arg[8] & 0x1)
2450 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1;
2451 if (cmd.rsp.arg[8] & 0x10000) {
2452 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17;
2453 npar_info->max_linkspeed_reg_offset = temp;
2454 }
d6994ca7
SS		 2455
2456 memcpy(ahw->extra_capability, &cmd.rsp.arg[16],
2457 sizeof(ahw->extra_capability));
7f966452
SC		 2458
2459out:
2460 qlcnic_free_mbx_args(&cmd);
2461 return err;
2462}
2463
2f514c52
JK		 2464int qlcnic_get_pci_func_type(struct qlcnic_adapter *adapter, u16 type,
2465 u16 *nic, u16 *fcoe, u16 *iscsi)
2466{
2467 struct device *dev = &adapter->pdev->dev;
2468 int err = 0;
2469
2470 switch (type) {
2471 case QLCNIC_TYPE_NIC:
2472 (*nic)++;
2473 break;
2474 case QLCNIC_TYPE_FCOE:
2475 (*fcoe)++;
2476 break;
2477 case QLCNIC_TYPE_ISCSI:
2478 (*iscsi)++;
2479 break;
2480 default:
2481 dev_err(dev, "%s: Unknown PCI type[%x]\n",
2482 __func__, type);
2483 err = -EIO;
2484 }
2485
2486 return err;
2487}
2488
7f966452
SC		 2489int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter,
2490 struct qlcnic_pci_info *pci_info)
2491{
ee9e8b6c
MC		 2492 struct qlcnic_hardware_context *ahw = adapter->ahw;
2493 struct device *dev = &adapter->pdev->dev;
2f514c52 2494 u16 nic = 0, fcoe = 0, iscsi = 0;
ee9e8b6c 2495 struct qlcnic_cmd_args cmd;
7f966452
SC		 2496 int i, err = 0, j = 0;
2497 u32 temp;
7f966452 2498
b6b4316c
SS		 2499 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
2500 if (err)
2501 return err;
2502
7f966452
SC		 2503 err = qlcnic_issue_cmd(adapter, &cmd);
2504
2f514c52 2505 ahw->total_nic_func = 0;
7f966452 2506 if (err == QLCNIC_RCODE_SUCCESS) {
ee9e8b6c 2507 ahw->max_pci_func = cmd.rsp.arg[1] & 0xFF;
2f514c52 2508 for (i = 2, j = 0; j < ahw->max_vnic_func; j++, pci_info++) {
7f966452
SC		 2509 pci_info->id = cmd.rsp.arg[i] & 0xFFFF;
2510 pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2511 i++;
2f514c52
JK		 2512 if (!pci_info->active) {
2513 i += QLC_SKIP_INACTIVE_PCI_REGS;
2514 continue;
2515 }
7f966452 2516 pci_info->type = cmd.rsp.arg[i] & 0xFFFF;
2f514c52
JK		 2517 err = qlcnic_get_pci_func_type(adapter, pci_info->type,
2518 &nic, &fcoe, &iscsi);
7f966452
SC		 2519 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2520 pci_info->default_port = temp;
2521 i++;
2522 pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF;
2523 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2524 pci_info->tx_max_bw = temp;
2525 i = i + 2;
2526 memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2);
2527 i++;
2528 memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2);
2529 i = i + 3;
7f966452
SC		 2530 }
2531 } else {
ee9e8b6c 2532 dev_err(dev, "Failed to get PCI Info, error = %d\n", err);
7f966452
SC		 2533 err = -EIO;
2534 }
2535
2f514c52
JK		 2536 ahw->total_nic_func = nic;
2537 ahw->total_pci_func = nic + fcoe + iscsi;
2538 if (ahw->total_nic_func == 0 || ahw->total_pci_func == 0) {
2539 dev_err(dev, "%s: Invalid function count: total nic func[%x], total pci func[%x]\n",
2540 __func__, ahw->total_nic_func, ahw->total_pci_func);
2541 err = -EIO;
2542 }
7f966452
SC		 2543 qlcnic_free_mbx_args(&cmd);
2544
2545 return err;
2546}
2547
2548int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type)
2549{
2550 int i, index, err;
7f966452 2551 u8 max_ints;
e2ab1233 2552 u32 val, temp, type;
7f966452
SC		 2553 struct qlcnic_cmd_args cmd;
2554
7dd90cf1 2555 max_ints = adapter->ahw->num_msix - 1;
b6b4316c
SS		 2556 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT);
2557 if (err)
2558 return err;
2559
7f966452 2560 cmd.req.arg[1] = max_ints;
7cb03b23
RB		 2561
2562 if (qlcnic_sriov_vf_check(adapter))
2563 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16;
2564
7f966452
SC		 2565 for (i = 0, index = 2; i < max_ints; i++) {
2566 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
2567 val = type | (adapter->ahw->intr_tbl[i].type << 4);
2568 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
2569 val |= (adapter->ahw->intr_tbl[i].id << 16);
2570 cmd.req.arg[index++] = val;
2571 }
2572 err = qlcnic_issue_cmd(adapter, &cmd);
2573 if (err) {
2574 dev_err(&adapter->pdev->dev,
2575 "Failed to configure interrupts 0x%x\n", err);
2576 goto out;
2577 }
2578
2579 max_ints = cmd.rsp.arg[1];
2580 for (i = 0, index = 2; i < max_ints; i++, index += 2) {
2581 val = cmd.rsp.arg[index];
2582 if (LSB(val)) {
2583 dev_info(&adapter->pdev->dev,
2584 "Can't configure interrupt %d\n",
2585 adapter->ahw->intr_tbl[i].id);
2586 continue;
2587 }
2588 if (op_type) {
2589 adapter->ahw->intr_tbl[i].id = MSW(val);
2590 adapter->ahw->intr_tbl[i].enabled = 1;
2591 temp = cmd.rsp.arg[index + 1];
2592 adapter->ahw->intr_tbl[i].src = temp;
2593 } else {
2594 adapter->ahw->intr_tbl[i].id = i;
2595 adapter->ahw->intr_tbl[i].enabled = 0;
2596 adapter->ahw->intr_tbl[i].src = 0;
2597 }
2598 }
2599out:
2600 qlcnic_free_mbx_args(&cmd);
2601 return err;
2602}
d865ebb4
SC		 2603
2604int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter)
2605{
2606 int id, timeout = 0;
2607 u32 status = 0;
2608
2609 while (status == 0) {
2610 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
2611 if (status)
2612 break;
2613
2614 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) {
2615 id = QLC_SHARED_REG_RD32(adapter,
2616 QLCNIC_FLASH_LOCK_OWNER);
2617 dev_err(&adapter->pdev->dev,
2618 "%s: failed, lock held by %d\n", __func__, id);
2619 return -EIO;
2620 }
2621 usleep_range(1000, 2000);
2622 }
2623
2624 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum);
2625 return 0;
2626}
2627
2628void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter)
2629{
2630 QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
2631 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF);
2632}
2633
629263ac
SC		 2634int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter,
2635 u32 flash_addr, u8 *p_data,
2636 int count)
d865ebb4 2637{
4bd8e738 2638 u32 word, range, flash_offset, addr = flash_addr, ret;
d865ebb4 2639 ulong indirect_add, direct_window;
4bd8e738 2640 int i, err = 0;
d865ebb4
SC		 2641
2642 flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1);
2643 if (addr & 0x3) {
2644 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2645 return -EIO;
2646 }
2647
2648 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW,
26acc712 2649 (addr & 0xFFFF0000));
d865ebb4
SC		 2650
2651 range = flash_offset + (count * sizeof(u32));
2652 /* Check if data is spread across multiple sectors */
2653 if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2654
2655 /* Multi sector read */
2656 for (i = 0; i < count; i++) {
2657 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
4bd8e738
HM		 2658 ret = QLCRD32(adapter, indirect_add, &err);
2659 if (err == -EIO)
2660 return err;
d865ebb4
SC		 2661
2662 word = ret;
2663 *(u32 *)p_data = word;
2664 p_data = p_data + 4;
2665 addr = addr + 4;
2666 flash_offset = flash_offset + 4;
2667
2668 if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2669 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW;
2670 /* This write is needed once for each sector */
2671 qlcnic_83xx_wrt_reg_indirect(adapter,
2672 direct_window,
2673 (addr));
2674 flash_offset = 0;
2675 }
2676 }
2677 } else {
2678 /* Single sector read */
2679 for (i = 0; i < count; i++) {
2680 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
4bd8e738
HM		 2681 ret = QLCRD32(adapter, indirect_add, &err);
2682 if (err == -EIO)
2683 return err;
d865ebb4
SC		 2684
2685 word = ret;
2686 *(u32 *)p_data = word;
2687 p_data = p_data + 4;
2688 addr = addr + 4;
2689 }
2690 }
2691
2692 return 0;
2693}
2694
2695static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
2696{
2697 u32 status;
2698 int retries = QLC_83XX_FLASH_READ_RETRY_COUNT;
4bd8e738 2699 int err = 0;
d865ebb4
SC		 2700
2701 do {
4bd8e738
HM		 2702 status = QLCRD32(adapter, QLC_83XX_FLASH_STATUS, &err);
2703 if (err == -EIO)
2704 return err;
2705
d865ebb4
SC		 2706 if ((status & QLC_83XX_FLASH_STATUS_READY) ==
2707 QLC_83XX_FLASH_STATUS_READY)
2708 break;
2709
c1b2037f 2710 usleep_range(1000, 1100);
d865ebb4
SC		 2711 } while (--retries);
2712
2713 if (!retries)
2714 return -EIO;
2715
2716 return 0;
2717}
2718
a520030e 2719int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter)
d865ebb4
SC		 2720{
2721 int ret;
2722 u32 cmd;
2723 cmd = adapter->ahw->fdt.write_statusreg_cmd;
2724 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2725 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd));
2726 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2727 adapter->ahw->fdt.write_enable_bits);
2728 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2729 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2730 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2731 if (ret)
2732 return -EIO;
2733
2734 return 0;
2735}
2736
a520030e 2737int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter)
d865ebb4
SC		 2738{
2739 int ret;
2740
2741 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2742 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG |
2743 adapter->ahw->fdt.write_statusreg_cmd));
2744 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2745 adapter->ahw->fdt.write_disable_bits);
2746 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2747 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2748 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2749 if (ret)
2750 return -EIO;
2751
2752 return 0;
2753}
2754
2755int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter)
2756{
4bd8e738
HM		 2757 int ret, err = 0;
2758 u32 mfg_id;
d865ebb4
SC		 2759
2760 if (qlcnic_83xx_lock_flash(adapter))
2761 return -EIO;
2762
2763 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2764 QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL);
2765 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2766 QLC_83XX_FLASH_READ_CTRL);
2767 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2768 if (ret) {
2769 qlcnic_83xx_unlock_flash(adapter);
2770 return -EIO;
2771 }
2772
4bd8e738
HM		 2773 mfg_id = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
2774 if (err == -EIO) {
2775 qlcnic_83xx_unlock_flash(adapter);
2776 return err;
2777 }
d865ebb4
SC		 2778
2779 adapter->flash_mfg_id = (mfg_id & 0xFF);
2780 qlcnic_83xx_unlock_flash(adapter);
2781
2782 return 0;
2783}
2784
2785int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter)
2786{
2787 int count, fdt_size, ret = 0;
2788
2789 fdt_size = sizeof(struct qlcnic_fdt);
2790 count = fdt_size / sizeof(u32);
2791
2792 if (qlcnic_83xx_lock_flash(adapter))
2793 return -EIO;
2794
2795 memset(&adapter->ahw->fdt, 0, fdt_size);
2796 ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION,
2797 (u8 *)&adapter->ahw->fdt,
2798 count);
26acc712 2799 qlcnic_swap32_buffer((u32 *)&adapter->ahw->fdt, count);
d865ebb4
SC		 2800 qlcnic_83xx_unlock_flash(adapter);
2801 return ret;
2802}
2803
2804int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter,
2805 u32 sector_start_addr)
2806{
2807 u32 reversed_addr, addr1, addr2, cmd;
2808 int ret = -EIO;
2809
2810 if (qlcnic_83xx_lock_flash(adapter) != 0)
2811 return -EIO;
2812
2813 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
a520030e 2814 ret = qlcnic_83xx_enable_flash_write(adapter);
d865ebb4
SC		 2815 if (ret) {
2816 qlcnic_83xx_unlock_flash(adapter);
2817 dev_err(&adapter->pdev->dev,
2818 "%s failed at %d\n",
2819 __func__, __LINE__);
2820 return ret;
2821 }
2822 }
2823
2824 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2825 if (ret) {
2826 qlcnic_83xx_unlock_flash(adapter);
2827 dev_err(&adapter->pdev->dev,
2828 "%s: failed at %d\n", __func__, __LINE__);
2829 return -EIO;
2830 }
2831
2832 addr1 = (sector_start_addr & 0xFF) << 16;
2833 addr2 = (sector_start_addr & 0xFF0000) >> 16;
26acc712 2834 reversed_addr = addr1 | addr2 | (sector_start_addr & 0xFF00);
d865ebb4
SC		 2835
2836 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2837 reversed_addr);
2838 cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd;
2839 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id)
2840 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd);
2841 else
2842 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2843 QLC_83XX_FLASH_OEM_ERASE_SIG);
2844 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2845 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2846
2847 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2848 if (ret) {
2849 qlcnic_83xx_unlock_flash(adapter);
2850 dev_err(&adapter->pdev->dev,
2851 "%s: failed at %d\n", __func__, __LINE__);
2852 return -EIO;
2853 }
2854
2855 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
a520030e 2856 ret = qlcnic_83xx_disable_flash_write(adapter);
d865ebb4
SC		 2857 if (ret) {
2858 qlcnic_83xx_unlock_flash(adapter);
2859 dev_err(&adapter->pdev->dev,
2860 "%s: failed at %d\n", __func__, __LINE__);
2861 return ret;
2862 }
2863 }
2864
2865 qlcnic_83xx_unlock_flash(adapter);
2866
2867 return 0;
2868}
2869
2870int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr,
2871 u32 *p_data)
2872{
2873 int ret = -EIO;
2874 u32 addr1 = 0x00800000 | (addr >> 2);
2875
2876 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1);
2877 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data);
2878 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2879 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2880 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2881 if (ret) {
2882 dev_err(&adapter->pdev->dev,
2883 "%s: failed at %d\n", __func__, __LINE__);
2884 return -EIO;
2885 }
2886
2887 return 0;
2888}
2889
2890int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr,
2891 u32 *p_data, int count)
2892{
2893 u32 temp;
4bd8e738 2894 int ret = -EIO, err = 0;
d865ebb4 2895
a520030e
HM		 2896 if ((count < QLC_83XX_FLASH_WRITE_MIN) ||
2897 (count > QLC_83XX_FLASH_WRITE_MAX)) {
d865ebb4
SC		 2898 dev_err(&adapter->pdev->dev,
2899 "%s: Invalid word count\n", __func__);
2900 return -EIO;
2901 }
2902
4bd8e738
HM		 2903 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2904 if (err == -EIO)
2905 return err;
2906
d865ebb4
SC		 2907 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL,
2908 (temp | QLC_83XX_FLASH_SPI_CTRL));
2909 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2910 QLC_83XX_FLASH_ADDR_TEMP_VAL);
2911
2912 /* First DWORD write */
2913 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2914 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2915 QLC_83XX_FLASH_FIRST_MS_PATTERN);
2916 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2917 if (ret) {
2918 dev_err(&adapter->pdev->dev,
2919 "%s: failed at %d\n", __func__, __LINE__);
2920 return -EIO;
2921 }
2922
2923 count--;
2924 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2925 QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL);
2926 /* Second to N-1 DWORD writes */
2927 while (count != 1) {
2928 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2929 *p_data++);
2930 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2931 QLC_83XX_FLASH_SECOND_MS_PATTERN);
2932 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2933 if (ret) {
2934 dev_err(&adapter->pdev->dev,
2935 "%s: failed at %d\n", __func__, __LINE__);
2936 return -EIO;
2937 }
2938 count--;
2939 }
2940
2941 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2942 QLC_83XX_FLASH_ADDR_TEMP_VAL |
2943 (addr >> 2));
2944 /* Last DWORD write */
2945 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2946 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2947 QLC_83XX_FLASH_LAST_MS_PATTERN);
2948 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2949 if (ret) {
2950 dev_err(&adapter->pdev->dev,
2951 "%s: failed at %d\n", __func__, __LINE__);
2952 return -EIO;
2953 }
2954
4bd8e738
HM		 2955 ret = QLCRD32(adapter, QLC_83XX_FLASH_SPI_STATUS, &err);
2956 if (err == -EIO)
2957 return err;
2958
d865ebb4
SC		 2959 if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) {
2960 dev_err(&adapter->pdev->dev, "%s: failed at %d\n",
2961 __func__, __LINE__);
2962 /* Operation failed, clear error bit */
4bd8e738
HM		 2963 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2964 if (err == -EIO)
2965 return err;
2966
d865ebb4
SC		 2967 qlcnic_83xx_wrt_reg_indirect(adapter,
2968 QLC_83XX_FLASH_SPI_CONTROL,
2969 (temp | QLC_83XX_FLASH_SPI_CTRL));
2970 }
2971
2972 return 0;
2973}
629263ac
SC		 2974
2975static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter)
2976{
2977 u32 val, id;
2978
2979 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2980
2981 /* Check if recovery need to be performed by the calling function */
2982 if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) {
2983 val = val & ~0x3F;
2984 val = val | ((adapter->portnum << 2) |
2985 QLC_83XX_NEED_DRV_LOCK_RECOVERY);
2986 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2987 dev_info(&adapter->pdev->dev,
2988 "%s: lock recovery initiated\n", __func__);
2989 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY);
2990 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2991 id = ((val >> 2) & 0xF);
2992 if (id == adapter->portnum) {
2993 val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK;
2994 val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS;
2995 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2996 /* Force release the lock */
2997 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2998 /* Clear recovery bits */
2999 val = val & ~0x3F;
3000 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
3001 dev_info(&adapter->pdev->dev,
3002 "%s: lock recovery completed\n", __func__);
3003 } else {
3004 dev_info(&adapter->pdev->dev,
3005 "%s: func %d to resume lock recovery process\n",
3006 __func__, id);
3007 }
3008 } else {
3009 dev_info(&adapter->pdev->dev,
3010 "%s: lock recovery initiated by other functions\n",
3011 __func__);
3012 }
3013}
3014
3015int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter)
3016{
3017 u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0;
3018 int max_attempt = 0;
3019
3020 while (status == 0) {
3021 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK);
3022 if (status)
3023 break;
3024
3025 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY);
3026 i++;
3027
3028 if (i == 1)
3029 temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
3030
3031 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) {
3032 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
3033 if (val == temp) {
3034 id = val & 0xFF;
3035 dev_info(&adapter->pdev->dev,
3036 "%s: lock to be recovered from %d\n",
3037 __func__, id);
3038 qlcnic_83xx_recover_driver_lock(adapter);
3039 i = 0;
3040 max_attempt++;
3041 } else {
3042 dev_err(&adapter->pdev->dev,
3043 "%s: failed to get lock\n", __func__);
3044 return -EIO;
3045 }
3046 }
3047
3048 /* Force exit from while loop after few attempts */
3049 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) {
3050 dev_err(&adapter->pdev->dev,
3051 "%s: failed to get lock\n", __func__);
3052 return -EIO;
3053 }
3054 }
3055
3056 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
3057 lock_alive_counter = val >> 8;
3058 lock_alive_counter++;
3059 val = lock_alive_counter << 8 | adapter->portnum;
3060 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
3061
3062 return 0;
3063}
3064
3065void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter)
3066{
3067 u32 val, lock_alive_counter, id;
3068
3069 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
3070 id = val & 0xFF;
3071 lock_alive_counter = val >> 8;
3072
3073 if (id != adapter->portnum)
3074 dev_err(&adapter->pdev->dev,
3075 "%s:Warning func %d is unlocking lock owned by %d\n",
3076 __func__, adapter->portnum, id);
3077
3078 val = (lock_alive_counter << 8) | 0xFF;
3079 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
3080 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
3081}
3082
8d37ba02 3083int qlcnic_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr,
629263ac
SC		 3084 u32 *data, u32 count)
3085{
3086 int i, j, ret = 0;
3087 u32 temp;
3088
3089 /* Check alignment */
3090 if (addr & 0xF)
3091 return -EIO;
3092
3093 mutex_lock(&adapter->ahw->mem_lock);
8d37ba02 3094 qlcnic_ind_wr(adapter, QLCNIC_MS_ADDR_HI, 0);
629263ac
SC		 3095
3096 for (i = 0; i < count; i++, addr += 16) {
3097 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET,
3098 QLCNIC_ADDR_QDR_NET_MAX)) ||
3099 (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET,
3100 QLCNIC_ADDR_DDR_NET_MAX)))) {
3101 mutex_unlock(&adapter->ahw->mem_lock);
3102 return -EIO;
3103 }
3104
8d37ba02
SS		 3105 qlcnic_ind_wr(adapter, QLCNIC_MS_ADDR_LO, addr);
3106 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_LO, *data++);
3107 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_HI, *data++);
3108 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_ULO, *data++);
3109 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_UHI, *data++);
3110 qlcnic_ind_wr(adapter, QLCNIC_MS_CTRL, QLCNIC_TA_WRITE_ENABLE);
3111 qlcnic_ind_wr(adapter, QLCNIC_MS_CTRL, QLCNIC_TA_WRITE_START);
629263ac
SC		 3112
3113 for (j = 0; j < MAX_CTL_CHECK; j++) {
8d37ba02 3114 temp = qlcnic_ind_rd(adapter, QLCNIC_MS_CTRL);
4bd8e738 3115
629263ac
SC		 3116 if ((temp & TA_CTL_BUSY) == 0)
3117 break;
3118 }
3119
3120 /* Status check failure */
3121 if (j >= MAX_CTL_CHECK) {
3122 printk_ratelimited(KERN_WARNING
3123 "MS memory write failed\n");
3124 mutex_unlock(&adapter->ahw->mem_lock);
3125 return -EIO;
3126 }
3127 }
3128
3129 mutex_unlock(&adapter->ahw->mem_lock);
3130
3131 return ret;
3132}
81d0aeb0
SC		 3133
3134int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr,
3135 u8 *p_data, int count)
3136{
4bd8e738 3137 u32 word, addr = flash_addr, ret;
81d0aeb0 3138 ulong indirect_addr;
4bd8e738 3139 int i, err = 0;
81d0aeb0
SC		 3140
3141 if (qlcnic_83xx_lock_flash(adapter) != 0)
3142 return -EIO;
3143
3144 if (addr & 0x3) {
3145 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
3146 qlcnic_83xx_unlock_flash(adapter);
3147 return -EIO;
3148 }
3149
3150 for (i = 0; i < count; i++) {
3151 if (qlcnic_83xx_wrt_reg_indirect(adapter,
3152 QLC_83XX_FLASH_DIRECT_WINDOW,
3153 (addr))) {
3154 qlcnic_83xx_unlock_flash(adapter);
3155 return -EIO;
3156 }
3157
3158 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr);
4bd8e738
HM		 3159 ret = QLCRD32(adapter, indirect_addr, &err);
3160 if (err == -EIO)
3161 return err;
3162
81d0aeb0 3163 word = ret;
1403f43a 3164 *(u32 *)p_data = word;
81d0aeb0
SC		 3165 p_data = p_data + 4;
3166 addr = addr + 4;
3167 }
3168
3169 qlcnic_83xx_unlock_flash(adapter);
3170
3171 return 0;
3172}
7e38d04b 3173
f9c3fe2f
CM		 3174void qlcnic_83xx_get_port_type(struct qlcnic_adapter *adapter)
3175{
3176 struct qlcnic_hardware_context *ahw = adapter->ahw;
3177 struct qlcnic_cmd_args cmd;
3178 u32 config;
3179 int err;
3180
3181 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
3182 if (err)
3183 return;
3184
3185 err = qlcnic_issue_cmd(adapter, &cmd);
3186 if (err) {
3187 dev_info(&adapter->pdev->dev,
3188 "Get Link Status Command failed: 0x%x\n", err);
3189 goto out;
3190 } else {
3191 config = cmd.rsp.arg[3];
3192
3193 switch (QLC_83XX_SFP_MODULE_TYPE(config)) {
3194 case QLC_83XX_MODULE_FIBRE_1000BASE_SX:
3195 case QLC_83XX_MODULE_FIBRE_1000BASE_LX:
3196 case QLC_83XX_MODULE_FIBRE_1000BASE_CX:
3197 case QLC_83XX_MODULE_TP_1000BASE_T:
3198 ahw->port_type = QLCNIC_GBE;
3199 break;
3200 default:
3201 ahw->port_type = QLCNIC_XGBE;
3202 }
3203 }
3204out:
3205 qlcnic_free_mbx_args(&cmd);
3206}
3207
7e38d04b
SC		 3208int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter)
3209{
7cb03b23 3210 u8 pci_func;
7e38d04b
SC		 3211 int err;
3212 u32 config = 0, state;
3213 struct qlcnic_cmd_args cmd;
3214 struct qlcnic_hardware_context *ahw = adapter->ahw;
3215
7cb03b23
RB		 3216 if (qlcnic_sriov_vf_check(adapter))
3217 pci_func = adapter->portnum;
3218 else
3219 pci_func = ahw->pci_func;
3220
3221 state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func));
3222 if (!QLC_83xx_FUNC_VAL(state, pci_func)) {
7e38d04b
SC		 3223 dev_info(&adapter->pdev->dev, "link state down\n");
3224 return config;
3225 }
b6b4316c
SS		 3226
3227 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
3228 if (err)
3229 return err;
3230
7e38d04b
SC		 3231 err = qlcnic_issue_cmd(adapter, &cmd);
3232 if (err) {
3233 dev_info(&adapter->pdev->dev,
3234 "Get Link Status Command failed: 0x%x\n", err);
3235 goto out;
3236 } else {
3237 config = cmd.rsp.arg[1];
3238 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) {
3239 case QLC_83XX_10M_LINK:
3240 ahw->link_speed = SPEED_10;
3241 break;
3242 case QLC_83XX_100M_LINK:
3243 ahw->link_speed = SPEED_100;
3244 break;
3245 case QLC_83XX_1G_LINK:
3246 ahw->link_speed = SPEED_1000;
3247 break;
3248 case QLC_83XX_10G_LINK:
3249 ahw->link_speed = SPEED_10000;
3250 break;
3251 default:
3252 ahw->link_speed = 0;
3253 break;
3254 }
3255 config = cmd.rsp.arg[3];
cd6e7381
JK		 3256 switch (QLC_83XX_SFP_MODULE_TYPE(config)) {
3257 case QLC_83XX_MODULE_FIBRE_10GBASE_LRM:
3258 case QLC_83XX_MODULE_FIBRE_10GBASE_LR:
3259 case QLC_83XX_MODULE_FIBRE_10GBASE_SR:
3260 ahw->supported_type = PORT_FIBRE;
3261 ahw->port_type = QLCNIC_XGBE;
3262 break;
3263 case QLC_83XX_MODULE_FIBRE_1000BASE_SX:
3264 case QLC_83XX_MODULE_FIBRE_1000BASE_LX:
3265 case QLC_83XX_MODULE_FIBRE_1000BASE_CX:
3266 ahw->supported_type = PORT_FIBRE;
3267 ahw->port_type = QLCNIC_GBE;
3268 break;
3269 case QLC_83XX_MODULE_TP_1000BASE_T:
3270 ahw->supported_type = PORT_TP;
3271 ahw->port_type = QLCNIC_GBE;
3272 break;
3273 case QLC_83XX_MODULE_DA_10GE_PASSIVE_CP:
3274 case QLC_83XX_MODULE_DA_10GE_ACTIVE_CP:
3275 case QLC_83XX_MODULE_DA_10GE_LEGACY_CP:
3276 case QLC_83XX_MODULE_DA_1GE_PASSIVE_CP:
3277 ahw->supported_type = PORT_DA;
3278 ahw->port_type = QLCNIC_XGBE;
3279 break;
3280 default:
3281 ahw->supported_type = PORT_OTHER;
3282 ahw->port_type = QLCNIC_XGBE;
b938662d 3283 }
7e38d04b
SC		 3284 if (config & 1)
3285 err = 1;
3286 }
3287out:
3288 qlcnic_free_mbx_args(&cmd);
3289 return config;
3290}
3291
49cef10f
PR		 3292int qlcnic_83xx_get_link_ksettings(struct qlcnic_adapter *adapter,
3293 struct ethtool_link_ksettings *ecmd)
7e38d04b 3294{
cd6e7381 3295 struct qlcnic_hardware_context *ahw = adapter->ahw;
7e38d04b
SC		 3296 u32 config = 0;
3297 int status = 0;
49cef10f 3298 u32 supported, advertising;
7e38d04b 3299
78ea2d97
SC		 3300 if (!test_bit(__QLCNIC_MAINTENANCE_MODE, &adapter->state)) {
3301 /* Get port configuration info */
3302 status = qlcnic_83xx_get_port_info(adapter);
3303 /* Get Link Status related info */
3304 config = qlcnic_83xx_test_link(adapter);
3305 ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config);
3306 }
3307
7e38d04b
SC		 3308 /* hard code until there is a way to get it from flash */
3309 ahw->board_type = QLCNIC_BRDTYPE_83XX_10G;
b938662d
HM		 3310
3311 if (netif_running(adapter->netdev) && ahw->has_link_events) {
49cef10f
PR		 3312 ecmd->base.speed = ahw->link_speed;
3313 ecmd->base.duplex = ahw->link_duplex;
3314 ecmd->base.autoneg = ahw->link_autoneg;
b938662d 3315 } else {
49cef10f
PR		 3316 ecmd->base.speed = SPEED_UNKNOWN;
3317 ecmd->base.duplex = DUPLEX_UNKNOWN;
3318 ecmd->base.autoneg = AUTONEG_DISABLE;
b938662d
HM		 3319 }
3320
49cef10f 3321 supported = (SUPPORTED_10baseT_Full |
cd6e7381
JK		 3322 SUPPORTED_100baseT_Full |
3323 SUPPORTED_1000baseT_Full |
3324 SUPPORTED_10000baseT_Full |
3325 SUPPORTED_Autoneg);
3326
49cef10f
PR		 3327 ethtool_convert_link_mode_to_legacy_u32(&advertising,
3328 ecmd->link_modes.advertising);
3329
3330 if (ecmd->base.autoneg == AUTONEG_ENABLE) {
cd6e7381 3331 if (ahw->port_config & QLC_83XX_10_CAPABLE)
49cef10f 3332 advertising |= SUPPORTED_10baseT_Full;
cd6e7381 3333 if (ahw->port_config & QLC_83XX_100_CAPABLE)
49cef10f 3334 advertising |= SUPPORTED_100baseT_Full;
cd6e7381 3335 if (ahw->port_config & QLC_83XX_1G_CAPABLE)
49cef10f 3336 advertising |= SUPPORTED_1000baseT_Full;
cd6e7381 3337 if (ahw->port_config & QLC_83XX_10G_CAPABLE)
49cef10f 3338 advertising |= SUPPORTED_10000baseT_Full;
cd6e7381 3339 if (ahw->port_config & QLC_83XX_AUTONEG_ENABLE)
49cef10f 3340 advertising |= ADVERTISED_Autoneg;
b938662d 3341 } else {
cd6e7381
JK		 3342 switch (ahw->link_speed) {
3343 case SPEED_10:
49cef10f 3344 advertising = SUPPORTED_10baseT_Full;
cd6e7381
JK		 3345 break;
3346 case SPEED_100:
49cef10f 3347 advertising = SUPPORTED_100baseT_Full;
cd6e7381
JK		 3348 break;
3349 case SPEED_1000:
49cef10f 3350 advertising = SUPPORTED_1000baseT_Full;
cd6e7381
JK		 3351 break;
3352 case SPEED_10000:
49cef10f 3353 advertising = SUPPORTED_10000baseT_Full;
cd6e7381
JK		 3354 break;
3355 default:
3356 break;
3357 }
3358
b938662d
HM		 3359 }
3360
3361 switch (ahw->supported_type) {
3362 case PORT_FIBRE:
49cef10f
PR		 3363 supported |= SUPPORTED_FIBRE;
3364 advertising |= ADVERTISED_FIBRE;
3365 ecmd->base.port = PORT_FIBRE;
b938662d
HM		 3366 break;
3367 case PORT_TP:
49cef10f
PR		 3368 supported |= SUPPORTED_TP;
3369 advertising |= ADVERTISED_TP;
3370 ecmd->base.port = PORT_TP;
b938662d 3371 break;
cd6e7381 3372 case PORT_DA:
49cef10f
PR		 3373 supported |= SUPPORTED_FIBRE;
3374 advertising |= ADVERTISED_FIBRE;
3375 ecmd->base.port = PORT_DA;
cd6e7381 3376 break;
b938662d 3377 default:
49cef10f
PR		 3378 supported |= SUPPORTED_FIBRE;
3379 advertising |= ADVERTISED_FIBRE;
3380 ecmd->base.port = PORT_OTHER;
b938662d
HM		 3381 break;
3382 }
49cef10f
PR		 3383 ecmd->base.phy_address = ahw->physical_port;
3384
3385 ethtool_convert_legacy_u32_to_link_mode(ecmd->link_modes.supported,
3386 supported);
3387 ethtool_convert_legacy_u32_to_link_mode(ecmd->link_modes.advertising,
3388 advertising);
3389
7e38d04b
SC		 3390 return status;
3391}
3392
49cef10f
PR		 3393int qlcnic_83xx_set_link_ksettings(struct qlcnic_adapter *adapter,
3394 const struct ethtool_link_ksettings *ecmd)
7e38d04b 3395{
cd6e7381 3396 struct qlcnic_hardware_context *ahw = adapter->ahw;
7e38d04b 3397 u32 config = adapter->ahw->port_config;
cd6e7381 3398 int status = 0;
7e38d04b 3399
cd6e7381 3400 /* 83xx devices do not support Half duplex */
49cef10f
PR		 3401 if (ecmd->base.duplex == DUPLEX_HALF) {
3402 netdev_info(adapter->netdev,
3403 "Half duplex mode not supported\n");
3404 return -EINVAL;
cd6e7381
JK		 3405 }
3406
49cef10f 3407 if (ecmd->base.autoneg) {
cd6e7381
JK		 3408 ahw->port_config |= QLC_83XX_AUTONEG_ENABLE;
3409 ahw->port_config |= (QLC_83XX_100_CAPABLE |
3410 QLC_83XX_1G_CAPABLE |
3411 QLC_83XX_10G_CAPABLE);
3412 } else { /* force speed */
3413 ahw->port_config &= ~QLC_83XX_AUTONEG_ENABLE;
49cef10f 3414 switch (ecmd->base.speed) {
cd6e7381
JK		 3415 case SPEED_10:
3416 ahw->port_config &= ~(QLC_83XX_100_CAPABLE |
3417 QLC_83XX_1G_CAPABLE |
3418 QLC_83XX_10G_CAPABLE);
3419 ahw->port_config |= QLC_83XX_10_CAPABLE;
3420 break;
3421 case SPEED_100:
3422 ahw->port_config &= ~(QLC_83XX_10_CAPABLE |
3423 QLC_83XX_1G_CAPABLE |
3424 QLC_83XX_10G_CAPABLE);
3425 ahw->port_config |= QLC_83XX_100_CAPABLE;
3426 break;
3427 case SPEED_1000:
3428 ahw->port_config &= ~(QLC_83XX_10_CAPABLE |
3429 QLC_83XX_100_CAPABLE |
3430 QLC_83XX_10G_CAPABLE);
3431 ahw->port_config |= QLC_83XX_1G_CAPABLE;
3432 break;
3433 case SPEED_10000:
3434 ahw->port_config &= ~(QLC_83XX_10_CAPABLE |
3435 QLC_83XX_100_CAPABLE |
3436 QLC_83XX_1G_CAPABLE);
3437 ahw->port_config |= QLC_83XX_10G_CAPABLE;
3438 break;
3439 default:
3440 return -EINVAL;
3441 }
7e38d04b 3442 }
7e38d04b
SC		 3443 status = qlcnic_83xx_set_port_config(adapter);
3444 if (status) {
cd6e7381
JK		 3445 netdev_info(adapter->netdev,
3446 "Failed to Set Link Speed and autoneg.\n");
3447 ahw->port_config = config;
7e38d04b 3448 }
cd6e7381 3449
7e38d04b
SC		 3450 return status;
3451}
3452
3453static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd,
3454 u64 *data, int index)
3455{
3456 u32 low, hi;
3457 u64 val;
3458
3459 low = cmd->rsp.arg[index];
3460 hi = cmd->rsp.arg[index + 1];
3461 val = (((u64) low) | (((u64) hi) << 32));
3462 *data++ = val;
3463 return data;
3464}
3465
3466static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter,
3467 struct qlcnic_cmd_args *cmd, u64 *data,
3468 int type, int *ret)
3469{
3470 int err, k, total_regs;
3471
3472 *ret = 0;
3473 err = qlcnic_issue_cmd(adapter, cmd);
3474 if (err != QLCNIC_RCODE_SUCCESS) {
3475 dev_info(&adapter->pdev->dev,
3476 "Error in get statistics mailbox command\n");
3477 *ret = -EIO;
3478 return data;
3479 }
3480 total_regs = cmd->rsp.num;
3481 switch (type) {
3482 case QLC_83XX_STAT_MAC:
3483 /* fill in MAC tx counters */
3484 for (k = 2; k < 28; k += 2)
3485 data = qlcnic_83xx_copy_stats(cmd, data, k);
3486 /* skip 24 bytes of reserved area */
3487 /* fill in MAC rx counters */
3488 for (k += 6; k < 60; k += 2)
3489 data = qlcnic_83xx_copy_stats(cmd, data, k);
3490 /* skip 24 bytes of reserved area */
3491 /* fill in MAC rx frame stats */
3492 for (k += 6; k < 80; k += 2)
3493 data = qlcnic_83xx_copy_stats(cmd, data, k);
52290740
SS		 3494 /* fill in eSwitch stats */
3495 for (; k < total_regs; k += 2)
3496 data = qlcnic_83xx_copy_stats(cmd, data, k);
7e38d04b
SC		 3497 break;
3498 case QLC_83XX_STAT_RX:
3499 for (k = 2; k < 8; k += 2)
3500 data = qlcnic_83xx_copy_stats(cmd, data, k);
3501 /* skip 8 bytes of reserved data */
3502 for (k += 2; k < 24; k += 2)
3503 data = qlcnic_83xx_copy_stats(cmd, data, k);
3504 /* skip 8 bytes containing RE1FBQ error data */
3505 for (k += 2; k < total_regs; k += 2)
3506 data = qlcnic_83xx_copy_stats(cmd, data, k);
3507 break;
3508 case QLC_83XX_STAT_TX:
3509 for (k = 2; k < 10; k += 2)
3510 data = qlcnic_83xx_copy_stats(cmd, data, k);
3511 /* skip 8 bytes of reserved data */
3512 for (k += 2; k < total_regs; k += 2)
3513 data = qlcnic_83xx_copy_stats(cmd, data, k);
3514 break;
3515 default:
3516 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n");
3517 *ret = -EIO;
3518 }
3519 return data;
3520}
3521
3522void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data)
3523{
3524 struct qlcnic_cmd_args cmd;
7bc27a8c 3525 struct net_device *netdev = adapter->netdev;
7e38d04b
SC		 3526 int ret = 0;
3527
b6b4316c
SS		 3528 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS);
3529 if (ret)
3530 return;
7e38d04b
SC		 3531 /* Get Tx stats */
3532 cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16);
3533 cmd.rsp.num = QLC_83XX_TX_STAT_REGS;
3534 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3535 QLC_83XX_STAT_TX, &ret);
3536 if (ret) {
7bc27a8c 3537 netdev_err(netdev, "Error getting Tx stats\n");
7e38d04b
SC		 3538 goto out;
3539 }
3540 /* Get MAC stats */
3541 cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16);
3542 cmd.rsp.num = QLC_83XX_MAC_STAT_REGS;
3543 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3544 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3545 QLC_83XX_STAT_MAC, &ret);
3546 if (ret) {
7bc27a8c 3547 netdev_err(netdev, "Error getting MAC stats\n");
7e38d04b
SC		 3548 goto out;
3549 }
3550 /* Get Rx stats */
3551 cmd.req.arg[1] = adapter->recv_ctx->context_id << 16;
3552 cmd.rsp.num = QLC_83XX_RX_STAT_REGS;
3553 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3554 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3555 QLC_83XX_STAT_RX, &ret);
3556 if (ret)
7bc27a8c 3557 netdev_err(netdev, "Error getting Rx stats\n");
7e38d04b
SC		 3558out:
3559 qlcnic_free_mbx_args(&cmd);
3560}
3561
d01a6d3c
SS		 3562#define QLCNIC_83XX_ADD_PORT0 BIT_0
3563#define QLCNIC_83XX_ADD_PORT1 BIT_1
3564#define QLCNIC_83XX_EXTENDED_MEM_SIZE 13 /* In MB */
3565int qlcnic_83xx_extend_md_capab(struct qlcnic_adapter *adapter)
3566{
3567 struct qlcnic_cmd_args cmd;
3568 int err;
3569
3570 err = qlcnic_alloc_mbx_args(&cmd, adapter,
3571 QLCNIC_CMD_83XX_EXTEND_ISCSI_DUMP_CAP);
3572 if (err)
3573 return err;
3574
3575 cmd.req.arg[1] = (QLCNIC_83XX_ADD_PORT0 | QLCNIC_83XX_ADD_PORT1);
3576 cmd.req.arg[2] = QLCNIC_83XX_EXTENDED_MEM_SIZE;
3577 cmd.req.arg[3] = QLCNIC_83XX_EXTENDED_MEM_SIZE;
3578
3579 err = qlcnic_issue_cmd(adapter, &cmd);
3580 if (err)
3581 dev_err(&adapter->pdev->dev,
3582 "failed to issue extend iSCSI minidump capability\n");
3583
3584 return err;
3585}
3586
7e38d04b
SC		 3587int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter)
3588{
3589 u32 major, minor, sub;
3590
3591 major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
3592 minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
3593 sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
3594
3595 if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) {
3596 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n",
3597 __func__);
3598 return 1;
3599 }
3600 return 0;
3601}
3602
710a1a49 3603inline int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter)
7e38d04b
SC		 3604{
3605 return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) *
710a1a49
PP		 3606 sizeof(*adapter->ahw->ext_reg_tbl)) +
3607 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) *
3608 sizeof(*adapter->ahw->reg_tbl));
7e38d04b
SC		 3609}
3610
3611int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff)
3612{
3613 int i, j = 0;
3614
3615 for (i = QLCNIC_DEV_INFO_SIZE + 1;
3616 j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++)
3617 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j);
3618
3619 for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++)
3620 regs_buff[i++] = QLCRDX(adapter->ahw, j);
3621 return i;
3622}
3623
58ead415 3624int qlcnic_83xx_interrupt_test(struct net_device *netdev)
7e38d04b 3625{
58ead415
JK		 3626 struct qlcnic_adapter *adapter = netdev_priv(netdev);
3627 struct qlcnic_hardware_context *ahw = adapter->ahw;
3628 struct qlcnic_cmd_args cmd;
34e8c406 3629 u8 val, drv_sds_rings = adapter->drv_sds_rings;
18afc102 3630 u8 drv_tx_rings = adapter->drv_tx_rings;
7e38d04b
SC		 3631 u32 data;
3632 u16 intrpt_id, id;
34e8c406 3633 int ret;
58ead415 3634
d1fcc172
MC		 3635 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
3636 netdev_info(netdev, "Device is resetting\n");
3637 return -EBUSY;
3638 }
3639
4690a7e4
SC		 3640 if (qlcnic_get_diag_lock(adapter)) {
3641 netdev_info(netdev, "Device in diagnostics mode\n");
3642 return -EBUSY;
3643 }
58ead415 3644
13a82b44 3645 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST,
34e8c406 3646 drv_sds_rings);
58ead415
JK		 3647 if (ret)
3648 goto fail_diag_irq;
3649
3650 ahw->diag_cnt = 0;
b6b4316c
SS		 3651 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST);
3652 if (ret)
3653 goto fail_diag_irq;
7e38d04b
SC		 3654
3655 if (adapter->flags & QLCNIC_MSIX_ENABLED)
58ead415 3656 intrpt_id = ahw->intr_tbl[0].id;
7e38d04b 3657 else
58ead415 3658 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
7e38d04b 3659
58ead415
JK		 3660 cmd.req.arg[1] = 1;
3661 cmd.req.arg[2] = intrpt_id;
3662 cmd.req.arg[3] = BIT_0;
7e38d04b 3663
58ead415
JK		 3664 ret = qlcnic_issue_cmd(adapter, &cmd);
3665 data = cmd.rsp.arg[2];
7e38d04b
SC		 3666 id = LSW(data);
3667 val = LSB(MSW(data));
3668 if (id != intrpt_id)
3669 dev_info(&adapter->pdev->dev,
3670 "Interrupt generated: 0x%x, requested:0x%x\n",
3671 id, intrpt_id);
3672 if (val)
58ead415 3673 dev_err(&adapter->pdev->dev,
7e38d04b 3674 "Interrupt test error: 0x%x\n", val);
58ead415
JK		 3675 if (ret)
3676 goto done;
3677
3678 msleep(20);
3679 ret = !ahw->diag_cnt;
7e38d04b 3680
58ead415
JK		 3681done:
3682 qlcnic_free_mbx_args(&cmd);
34e8c406 3683 qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
58ead415
JK		 3684
3685fail_diag_irq:
34e8c406 3686 adapter->drv_sds_rings = drv_sds_rings;
18afc102 3687 adapter->drv_tx_rings = drv_tx_rings;
4690a7e4 3688 qlcnic_release_diag_lock(adapter);
7e38d04b
SC		 3689 return ret;
3690}
3691
3692void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter,
3693 struct ethtool_pauseparam *pause)
3694{
3695 struct qlcnic_hardware_context *ahw = adapter->ahw;
3696 int status = 0;
3697 u32 config;
3698
3699 status = qlcnic_83xx_get_port_config(adapter);
3700 if (status) {
3701 dev_err(&adapter->pdev->dev,
3702 "%s: Get Pause Config failed\n", __func__);
3703 return;
3704 }
3705 config = ahw->port_config;
3706 if (config & QLC_83XX_CFG_STD_PAUSE) {
6177a95a
JK		 3707 switch (MSW(config)) {
3708 case QLC_83XX_TX_PAUSE:
3709 pause->tx_pause = 1;
3710 break;
3711 case QLC_83XX_RX_PAUSE:
3712 pause->rx_pause = 1;
3713 break;
3714 case QLC_83XX_TX_RX_PAUSE:
3715 default:
3716 /* Backward compatibility for existing
3717 * flash definitions
3718 */
7e38d04b 3719 pause->tx_pause = 1;
7e38d04b 3720 pause->rx_pause = 1;
6177a95a 3721 }
7e38d04b
SC		 3722 }
3723
3724 if (QLC_83XX_AUTONEG(config))
3725 pause->autoneg = 1;
3726}
3727
3728int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter,
3729 struct ethtool_pauseparam *pause)
3730{
3731 struct qlcnic_hardware_context *ahw = adapter->ahw;
3732 int status = 0;
3733 u32 config;
3734
3735 status = qlcnic_83xx_get_port_config(adapter);
3736 if (status) {
3737 dev_err(&adapter->pdev->dev,
3738 "%s: Get Pause Config failed.\n", __func__);
3739 return status;
3740 }
3741 config = ahw->port_config;
3742
3743 if (ahw->port_type == QLCNIC_GBE) {
3744 if (pause->autoneg)
3745 ahw->port_config |= QLC_83XX_ENABLE_AUTONEG;
3746 if (!pause->autoneg)
3747 ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG;
3748 } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) {
3749 return -EOPNOTSUPP;
3750 }
3751
3752 if (!(config & QLC_83XX_CFG_STD_PAUSE))
3753 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE;
3754
3755 if (pause->rx_pause && pause->tx_pause) {
3756 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE;
3757 } else if (pause->rx_pause && !pause->tx_pause) {
3758 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE;
3759 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE;
3760 } else if (pause->tx_pause && !pause->rx_pause) {
3761 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE;
3762 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE;
3763 } else if (!pause->rx_pause && !pause->tx_pause) {
6177a95a
JK		 3764 ahw->port_config &= ~(QLC_83XX_CFG_STD_TX_RX_PAUSE |
3765 QLC_83XX_CFG_STD_PAUSE);
7e38d04b
SC		 3766 }
3767 status = qlcnic_83xx_set_port_config(adapter);
3768 if (status) {
3769 dev_err(&adapter->pdev->dev,
3770 "%s: Set Pause Config failed.\n", __func__);
3771 ahw->port_config = config;
3772 }
3773 return status;
3774}
3775
3776static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter)
3777{
4bd8e738
HM		 3778 int ret, err = 0;
3779 u32 temp;
7e38d04b
SC		 3780
3781 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
3782 QLC_83XX_FLASH_OEM_READ_SIG);
3783 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
3784 QLC_83XX_FLASH_READ_CTRL);
3785 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
3786 if (ret)
3787 return -EIO;
3788
4bd8e738
HM		 3789 temp = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
3790 if (err == -EIO)
3791 return err;
3792
3793 return temp & 0xFF;
7e38d04b
SC		 3794}
3795
3796int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter)
3797{
3798 int status;
3799
3800 status = qlcnic_83xx_read_flash_status_reg(adapter);
3801 if (status == -EIO) {
3802 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n",
3803 __func__);
3804 return 1;
3805 }
3806 return 0;
3807}
486a5bc7 3808
a91e6810 3809static int qlcnic_83xx_shutdown(struct pci_dev *pdev)
486a5bc7
RB		 3810{
3811 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3812 struct net_device *netdev = adapter->netdev;
3813 int retval;
3814
3815 netif_device_detach(netdev);
3816 qlcnic_cancel_idc_work(adapter);
3817
3818 if (netif_running(netdev))
3819 qlcnic_down(adapter, netdev);
3820
3821 qlcnic_83xx_disable_mbx_intr(adapter);
3822 cancel_delayed_work_sync(&adapter->idc_aen_work);
3823
3824 retval = pci_save_state(pdev);
3825 if (retval)
3826 return retval;
3827
3828 return 0;
3829}
3830
21041400 3831static int qlcnic_83xx_resume(struct qlcnic_adapter *adapter)
486a5bc7
RB		 3832{
3833 struct qlcnic_hardware_context *ahw = adapter->ahw;
3834 struct qlc_83xx_idc *idc = &ahw->idc;
3835 int err = 0;
3836
3837 err = qlcnic_83xx_idc_init(adapter);
3838 if (err)
3839 return err;
3840
34e8c406 3841 if (ahw->nic_mode == QLCNIC_VNIC_MODE) {
486a5bc7
RB		 3842 if (ahw->op_mode == QLCNIC_MGMT_FUNC) {
3843 qlcnic_83xx_set_vnic_opmode(adapter);
3844 } else {
3845 err = qlcnic_83xx_check_vnic_state(adapter);
3846 if (err)
3847 return err;
3848 }
3849 }
3850
3851 err = qlcnic_83xx_idc_reattach_driver(adapter);
3852 if (err)
3853 return err;
3854
3855 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
3856 idc->delay);
3857 return err;
3858}
e5c4e6c6
MC		 3859
3860void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx)
3861{
16735d02 3862 reinit_completion(&mbx->completion);
e5c4e6c6
MC		 3863 set_bit(QLC_83XX_MBX_READY, &mbx->status);
3864}
3865
3866void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx)
3867{
78ea2d97
SC		 3868 if (!mbx)
3869 return;
3870
e5c4e6c6
MC		 3871 destroy_workqueue(mbx->work_q);
3872 kfree(mbx);
3873}
3874
3875static inline void
3876qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter *adapter,
3877 struct qlcnic_cmd_args *cmd)
3878{
3879 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
3880
3881 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
3882 qlcnic_free_mbx_args(cmd);
3883 kfree(cmd);
3884 return;
3885 }
3886 complete(&cmd->completion);
3887}
3888
60dcbcb0 3889static void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter *adapter)
e5c4e6c6
MC		 3890{
3891 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3892 struct list_head *head = &mbx->cmd_q;
3893 struct qlcnic_cmd_args *cmd = NULL;
3894
233ac389 3895 spin_lock_bh(&mbx->queue_lock);
e5c4e6c6
MC		 3896
3897 while (!list_empty(head)) {
3898 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
35570cfe
MC		 3899 dev_info(&adapter->pdev->dev, "%s: Mailbox command 0x%x\n",
3900 __func__, cmd->cmd_op);
e5c4e6c6
MC		 3901 list_del(&cmd->list);
3902 mbx->num_cmds--;
3903 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3904 }
3905
233ac389 3906 spin_unlock_bh(&mbx->queue_lock);
e5c4e6c6
MC		 3907}
3908
60dcbcb0 3909static int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter *adapter)
e5c4e6c6
MC		 3910{
3911 struct qlcnic_hardware_context *ahw = adapter->ahw;
3912 struct qlcnic_mailbox *mbx = ahw->mailbox;
3913 u32 host_mbx_ctrl;
3914
3915 if (!test_bit(QLC_83XX_MBX_READY, &mbx->status))
3916 return -EBUSY;
3917
3918 host_mbx_ctrl = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
3919 if (host_mbx_ctrl) {
35570cfe 3920 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
e5c4e6c6
MC		 3921 ahw->idc.collect_dump = 1;
3922 return -EIO;
3923 }
3924
3925 return 0;
3926}
3927
3928static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter *adapter,
3929 u8 issue_cmd)
3930{
3931 if (issue_cmd)
3932 QLCWRX(adapter->ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
3933 else
3934 QLCWRX(adapter->ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
3935}
3936
60dcbcb0
MC		 3937static void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter *adapter,
3938 struct qlcnic_cmd_args *cmd)
e5c4e6c6
MC		 3939{
3940 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3941
233ac389 3942 spin_lock_bh(&mbx->queue_lock);
e5c4e6c6
MC		 3943
3944 list_del(&cmd->list);
3945 mbx->num_cmds--;
3946
233ac389 3947 spin_unlock_bh(&mbx->queue_lock);
e5c4e6c6
MC		 3948
3949 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3950}
3951
3952static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter *adapter,
3953 struct qlcnic_cmd_args *cmd)
3954{
3955 u32 mbx_cmd, fw_hal_version, hdr_size, total_size, tmp;
3956 struct qlcnic_hardware_context *ahw = adapter->ahw;
3957 int i, j;
3958
3959 if (cmd->op_type != QLC_83XX_MBX_POST_BC_OP) {
3960 mbx_cmd = cmd->req.arg[0];
3961 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3962 for (i = 1; i < cmd->req.num; i++)
3963 writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
3964 } else {
3965 fw_hal_version = ahw->fw_hal_version;
3966 hdr_size = sizeof(struct qlcnic_bc_hdr) / sizeof(u32);
3967 total_size = cmd->pay_size + hdr_size;
3968 tmp = QLCNIC_CMD_BC_EVENT_SETUP | total_size << 16;
3969 mbx_cmd = tmp | fw_hal_version << 29;
3970 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3971
3972 /* Back channel specific operations bits */
3973 mbx_cmd = 0x1 | 1 << 4;
3974
3975 if (qlcnic_sriov_pf_check(adapter))
3976 mbx_cmd |= cmd->func_num << 5;
3977
3978 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 1));
3979
3980 for (i = 2, j = 0; j < hdr_size; i++, j++)
3981 writel(*(cmd->hdr++), QLCNIC_MBX_HOST(ahw, i));
3982 for (j = 0; j < cmd->pay_size; j++, i++)
3983 writel(*(cmd->pay++), QLCNIC_MBX_HOST(ahw, i));
3984 }
3985}
3986
3987void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *adapter)
3988{
3989 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3990
78ea2d97
SC		 3991 if (!mbx)
3992 return;
3993
e5c4e6c6
MC		 3994 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3995 complete(&mbx->completion);
3996 cancel_work_sync(&mbx->work);
3997 flush_workqueue(mbx->work_q);
3998 qlcnic_83xx_flush_mbx_queue(adapter);
3999}
4000
60dcbcb0
MC		 4001static int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter *adapter,
4002 struct qlcnic_cmd_args *cmd,
4003 unsigned long *timeout)
e5c4e6c6
MC		 4004{
4005 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
4006
4007 if (test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
4008 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
4009 init_completion(&cmd->completion);
4010 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_UNKNOWN;
4011
233ac389 4012 spin_lock_bh(&mbx->queue_lock);
e5c4e6c6
MC		 4013
4014 list_add_tail(&cmd->list, &mbx->cmd_q);
4015 mbx->num_cmds++;
4016 cmd->total_cmds = mbx->num_cmds;
4017 *timeout = cmd->total_cmds * QLC_83XX_MBX_TIMEOUT;
4018 queue_work(mbx->work_q, &mbx->work);
4019
233ac389 4020 spin_unlock_bh(&mbx->queue_lock);
e5c4e6c6
MC		 4021
4022 return 0;
4023 }
4024
4025 return -EBUSY;
4026}
4027
60dcbcb0
MC		 4028static int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter *adapter,
4029 struct qlcnic_cmd_args *cmd)
e5c4e6c6
MC		 4030{
4031 u8 mac_cmd_rcode;
4032 u32 fw_data;
4033
4034 if (cmd->cmd_op == QLCNIC_CMD_CONFIG_MAC_VLAN) {
4035 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2));
4036 mac_cmd_rcode = (u8)fw_data;
4037 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE ||
4038 mac_cmd_rcode == QLC_83XX_MAC_PRESENT ||
4039 mac_cmd_rcode == QLC_83XX_MAC_ABSENT) {
4040 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
4041 return QLCNIC_RCODE_SUCCESS;
4042 }
4043 }
4044
4045 return -EINVAL;
4046}
4047
4048static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter *adapter,
4049 struct qlcnic_cmd_args *cmd)
4050{
4051 struct qlcnic_hardware_context *ahw = adapter->ahw;
4052 struct device *dev = &adapter->pdev->dev;
4053 u8 mbx_err_code;
4054 u32 fw_data;
4055
4056 fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
4057 mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
4058 qlcnic_83xx_get_mbx_data(adapter, cmd);
4059
4060 switch (mbx_err_code) {
4061 case QLCNIC_MBX_RSP_OK:
4062 case QLCNIC_MBX_PORT_RSP_OK:
4063 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
4064 break;
4065 default:
4066 if (!qlcnic_83xx_check_mac_rcode(adapter, cmd))
4067 break;
4068
4069 dev_err(dev, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n",
4070 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
4071 ahw->op_mode, mbx_err_code);
4072 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_FAILED;
4073 qlcnic_dump_mbx(adapter, cmd);
4074 }
4075
4076 return;
4077}
4078
0951c5c2
M		 4079static inline void qlcnic_dump_mailbox_registers(struct qlcnic_adapter *adapter)
4080{
4081 struct qlcnic_hardware_context *ahw = adapter->ahw;
4082 u32 offset;
4083
4084 offset = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
4085 dev_info(&adapter->pdev->dev, "Mbx interrupt mask=0x%x, Mbx interrupt enable=0x%x, Host mbx control=0x%x, Fw mbx control=0x%x",
4086 readl(ahw->pci_base0 + offset),
4087 QLCRDX(ahw, QLCNIC_MBX_INTR_ENBL),
4088 QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL),
4089 QLCRDX(ahw, QLCNIC_FW_MBX_CTRL));
4090}
4091
e5c4e6c6
MC		 4092static void qlcnic_83xx_mailbox_worker(struct work_struct *work)
4093{
4094 struct qlcnic_mailbox *mbx = container_of(work, struct qlcnic_mailbox,
4095 work);
4096 struct qlcnic_adapter *adapter = mbx->adapter;
571f2c11 4097 const struct qlcnic_mbx_ops *mbx_ops = mbx->ops;
e5c4e6c6 4098 struct device *dev = &adapter->pdev->dev;
e5c4e6c6
MC		 4099 struct list_head *head = &mbx->cmd_q;
4100 struct qlcnic_hardware_context *ahw;
4101 struct qlcnic_cmd_args *cmd = NULL;
819bfe76 4102 unsigned long flags;
e5c4e6c6
MC		 4103
4104 ahw = adapter->ahw;
4105
4106 while (true) {
35570cfe
MC		 4107 if (qlcnic_83xx_check_mbx_status(adapter)) {
4108 qlcnic_83xx_flush_mbx_queue(adapter);
e5c4e6c6 4109 return;
35570cfe 4110 }
e5c4e6c6 4111
819bfe76 4112 spin_lock_irqsave(&mbx->aen_lock, flags);
5bf93251 4113 mbx->rsp_status = QLC_83XX_MBX_RESPONSE_WAIT;
819bfe76 4114 spin_unlock_irqrestore(&mbx->aen_lock, flags);
e5c4e6c6 4115
233ac389 4116 spin_lock_bh(&mbx->queue_lock);
e5c4e6c6
MC		 4117
4118 if (list_empty(head)) {
233ac389 4119 spin_unlock_bh(&mbx->queue_lock);
e5c4e6c6
MC		 4120 return;
4121 }
4122 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
4123
233ac389 4124 spin_unlock_bh(&mbx->queue_lock);
e5c4e6c6
MC		 4125
4126 mbx_ops->encode_cmd(adapter, cmd);
4127 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_REQUEST);
4128
4129 if (wait_for_completion_timeout(&mbx->completion,
4130 QLC_83XX_MBX_TIMEOUT)) {
4131 mbx_ops->decode_resp(adapter, cmd);
4132 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_COMPLETION);
4133 } else {
4134 dev_err(dev, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n",
4135 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
4136 ahw->op_mode);
4137 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
0951c5c2
M		 4138 qlcnic_dump_mailbox_registers(adapter);
4139 qlcnic_83xx_get_mbx_data(adapter, cmd);
b942f44a 4140 qlcnic_dump_mbx(adapter, cmd);
e5c4e6c6
MC		 4141 qlcnic_83xx_idc_request_reset(adapter,
4142 QLCNIC_FORCE_FW_DUMP_KEY);
4143 cmd->rsp_opcode = QLCNIC_RCODE_TIMEOUT;
4144 }
4145 mbx_ops->dequeue_cmd(adapter, cmd);
4146 }
4147}
4148
571f2c11 4149static const struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops = {
e5c4e6c6
MC		 4150 .enqueue_cmd = qlcnic_83xx_enqueue_mbx_cmd,
4151 .dequeue_cmd = qlcnic_83xx_dequeue_mbx_cmd,
4152 .decode_resp = qlcnic_83xx_decode_mbx_rsp,
4153 .encode_cmd = qlcnic_83xx_encode_mbx_cmd,
4154 .nofity_fw = qlcnic_83xx_signal_mbx_cmd,
4155};
4156
4157int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *adapter)
4158{
4159 struct qlcnic_hardware_context *ahw = adapter->ahw;
4160 struct qlcnic_mailbox *mbx;
4161
4162 ahw->mailbox = kzalloc(sizeof(*mbx), GFP_KERNEL);
4163 if (!ahw->mailbox)
4164 return -ENOMEM;
4165
4166 mbx = ahw->mailbox;
4167 mbx->ops = &qlcnic_83xx_mbx_ops;
4168 mbx->adapter = adapter;
4169
4170 spin_lock_init(&mbx->queue_lock);
4171 spin_lock_init(&mbx->aen_lock);
4172 INIT_LIST_HEAD(&mbx->cmd_q);
4173 init_completion(&mbx->completion);
4174
4175 mbx->work_q = create_singlethread_workqueue("qlcnic_mailbox");
4176 if (mbx->work_q == NULL) {
4177 kfree(mbx);
4178 return -ENOMEM;
4179 }
4180
4181 INIT_WORK(&mbx->work, qlcnic_83xx_mailbox_worker);
4182 set_bit(QLC_83XX_MBX_READY, &mbx->status);
4183 return 0;
4184}
9ce226fa 4185
a91e6810
FW		 4186static pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *pdev,
4187 pci_channel_state_t state)
9ce226fa
PP		 4188{
4189 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
4190
4191 if (state == pci_channel_io_perm_failure)
4192 return PCI_ERS_RESULT_DISCONNECT;
4193
4194 if (state == pci_channel_io_normal)
4195 return PCI_ERS_RESULT_RECOVERED;
4196
4197 set_bit(__QLCNIC_AER, &adapter->state);
4198 set_bit(__QLCNIC_RESETTING, &adapter->state);
4199
4200 qlcnic_83xx_aer_stop_poll_work(adapter);
4201
4202 pci_save_state(pdev);
4203 pci_disable_device(pdev);
4204
4205 return PCI_ERS_RESULT_NEED_RESET;
4206}
4207
a91e6810 4208static pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *pdev)
9ce226fa
PP		 4209{
4210 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
4211 int err = 0;
4212
4213 pdev->error_state = pci_channel_io_normal;
4214 err = pci_enable_device(pdev);
4215 if (err)
4216 goto disconnect;
4217
4218 pci_set_power_state(pdev, PCI_D0);
4219 pci_set_master(pdev);
4220 pci_restore_state(pdev);
4221
4222 err = qlcnic_83xx_aer_reset(adapter);
4223 if (err == 0)
4224 return PCI_ERS_RESULT_RECOVERED;
4225disconnect:
4226 clear_bit(__QLCNIC_AER, &adapter->state);
4227 clear_bit(__QLCNIC_RESETTING, &adapter->state);
4228 return PCI_ERS_RESULT_DISCONNECT;
4229}
4230
a91e6810 4231static void qlcnic_83xx_io_resume(struct pci_dev *pdev)
9ce226fa
PP		 4232{
4233 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
4234
4235 pci_cleanup_aer_uncorrect_error_status(pdev);
4236 if (test_and_clear_bit(__QLCNIC_AER, &adapter->state))
4237 qlcnic_83xx_aer_start_poll_work(adapter);
4238}
Linux 6.x block layer and io_uring tree(s)