Commit | Line | Data |
---|---|---|
af19b491 | 1 | /* |
40839129 | 2 | * QLogic qlcnic NIC Driver |
577ae39d | 3 | * Copyright (c) 2009-2013 QLogic Corporation |
af19b491 | 4 | * |
40839129 | 5 | * See LICENSE.qlcnic for copyright and licensing details. |
af19b491 AKS |
6 | */ |
7 | ||
8 | #ifndef _QLCNIC_H_ | |
9 | #define _QLCNIC_H_ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/types.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/netdevice.h> | |
17 | #include <linux/etherdevice.h> | |
18 | #include <linux/ip.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/tcp.h> | |
21 | #include <linux/skbuff.h> | |
22 | #include <linux/firmware.h> | |
af19b491 AKS |
23 | #include <linux/ethtool.h> |
24 | #include <linux/mii.h> | |
25 | #include <linux/timer.h> | |
acdd32be | 26 | #include <linux/irq.h> |
af19b491 | 27 | #include <linux/vmalloc.h> |
af19b491 AKS |
28 | #include <linux/io.h> |
29 | #include <asm/byteorder.h> | |
b9796a14 AC |
30 | #include <linux/bitops.h> |
31 | #include <linux/if_vlan.h> | |
af19b491 AKS |
32 | |
33 | #include "qlcnic_hdr.h" | |
7f966452 SC |
34 | #include "qlcnic_hw.h" |
35 | #include "qlcnic_83xx_hw.h" | |
14d385b9 | 36 | #include "qlcnic_dcb.h" |
af19b491 AKS |
37 | |
38 | #define _QLCNIC_LINUX_MAJOR 5 | |
4cffa13d | 39 | #define _QLCNIC_LINUX_MINOR 3 |
45c78e02 MC |
40 | #define _QLCNIC_LINUX_SUBVERSION 64 |
41 | #define QLCNIC_LINUX_VERSIONID "5.3.64" | |
96f8118c | 42 | #define QLCNIC_DRV_IDC_VER 0x01 |
d4066833 SC |
43 | #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\ |
44 | (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION)) | |
af19b491 AKS |
45 | |
46 | #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c)) | |
47 | #define _major(v) (((v) >> 24) & 0xff) | |
48 | #define _minor(v) (((v) >> 16) & 0xff) | |
49 | #define _build(v) ((v) & 0xffff) | |
50 | ||
51 | /* version in image has weird encoding: | |
52 | * 7:0 - major | |
53 | * 15:8 - minor | |
54 | * 31:16 - build (little endian) | |
55 | */ | |
56 | #define QLCNIC_DECODE_VERSION(v) \ | |
57 | QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16)) | |
58 | ||
8f891387 | 59 | #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2) |
af19b491 AKS |
60 | #define QLCNIC_NUM_FLASH_SECTORS (64) |
61 | #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024) | |
62 | #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \ | |
63 | * QLCNIC_FLASH_SECTOR_SIZE) | |
64 | ||
65 | #define RCV_DESC_RINGSIZE(rds_ring) \ | |
66 | (sizeof(struct rcv_desc) * (rds_ring)->num_desc) | |
67 | #define RCV_BUFF_RINGSIZE(rds_ring) \ | |
68 | (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc) | |
69 | #define STATUS_DESC_RINGSIZE(sds_ring) \ | |
70 | (sizeof(struct status_desc) * (sds_ring)->num_desc) | |
71 | #define TX_BUFF_RINGSIZE(tx_ring) \ | |
72 | (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc) | |
73 | #define TX_DESC_RINGSIZE(tx_ring) \ | |
74 | (sizeof(struct cmd_desc_type0) * tx_ring->num_desc) | |
75 | ||
76 | #define QLCNIC_P3P_A0 0x50 | |
a2050c7e | 77 | #define QLCNIC_P3P_C0 0x58 |
af19b491 AKS |
78 | |
79 | #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0) | |
80 | ||
81 | #define FIRST_PAGE_GROUP_START 0 | |
82 | #define FIRST_PAGE_GROUP_END 0x100000 | |
83 | ||
ff1b1bf8 SV |
84 | #define P3P_MAX_MTU (9600) |
85 | #define P3P_MIN_MTU (68) | |
af19b491 AKS |
86 | #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */ |
87 | ||
ff1b1bf8 SV |
88 | #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN) |
89 | #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU) | |
af19b491 AKS |
90 | #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048 |
91 | #define QLCNIC_LRO_BUFFER_EXTRA 2048 | |
92 | ||
af19b491 | 93 | /* Tx defines */ |
91a403ca | 94 | #define QLCNIC_MAX_FRAGS_PER_TX 14 |
ef71ff83 RB |
95 | #define MAX_TSO_HEADER_DESC 2 |
96 | #define MGMT_CMD_DESC_RESV 4 | |
97 | #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \ | |
98 | + MGMT_CMD_DESC_RESV) | |
af19b491 | 99 | #define QLCNIC_MAX_TX_TIMEOUTS 2 |
34e8c406 HM |
100 | |
101 | /* Driver will use 1 Tx ring in INT-x/MSI/SRIOV mode. */ | |
102 | #define QLCNIC_SINGLE_RING 1 | |
103 | #define QLCNIC_DEF_SDS_RINGS 4 | |
104 | #define QLCNIC_DEF_TX_RINGS 4 | |
105 | #define QLCNIC_MAX_VNIC_TX_RINGS 4 | |
106 | #define QLCNIC_MAX_VNIC_SDS_RINGS 4 | |
cb9327d5 HM |
107 | #define QLCNIC_83XX_MINIMUM_VECTOR 3 |
108 | #define QLCNIC_82XX_MINIMUM_VECTOR 2 | |
34e8c406 HM |
109 | |
110 | enum qlcnic_queue_type { | |
111 | QLCNIC_TX_QUEUE = 1, | |
112 | QLCNIC_RX_QUEUE, | |
113 | }; | |
114 | ||
115 | /* Operational mode for driver */ | |
116 | #define QLCNIC_VNIC_MODE 0xFF | |
117 | #define QLCNIC_DEFAULT_MODE 0x0 | |
012ec812 | 118 | |
2f514c52 JK |
119 | /* Virtual NIC function count */ |
120 | #define QLC_DEFAULT_VNIC_COUNT 8 | |
121 | #define QLC_84XX_VNIC_COUNT 16 | |
122 | ||
af19b491 AKS |
123 | /* |
124 | * Following are the states of the Phantom. Phantom will set them and | |
125 | * Host will read to check if the fields are correct. | |
126 | */ | |
127 | #define PHAN_INITIALIZE_FAILED 0xffff | |
128 | #define PHAN_INITIALIZE_COMPLETE 0xff01 | |
129 | ||
130 | /* Host writes the following to notify that it has done the init-handshake */ | |
131 | #define PHAN_INITIALIZE_ACK 0xf00f | |
132 | #define PHAN_PEG_RCV_INITIALIZED 0xff01 | |
133 | ||
134 | #define NUM_RCV_DESC_RINGS 3 | |
af19b491 AKS |
135 | |
136 | #define RCV_RING_NORMAL 0 | |
137 | #define RCV_RING_JUMBO 1 | |
af19b491 AKS |
138 | |
139 | #define MIN_CMD_DESCRIPTORS 64 | |
140 | #define MIN_RCV_DESCRIPTORS 64 | |
141 | #define MIN_JUMBO_DESCRIPTORS 32 | |
142 | ||
143 | #define MAX_CMD_DESCRIPTORS 1024 | |
144 | #define MAX_RCV_DESCRIPTORS_1G 4096 | |
145 | #define MAX_RCV_DESCRIPTORS_10G 8192 | |
90d19005 | 146 | #define MAX_RCV_DESCRIPTORS_VF 2048 |
af19b491 AKS |
147 | #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512 |
148 | #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024 | |
af19b491 AKS |
149 | |
150 | #define DEFAULT_RCV_DESCRIPTORS_1G 2048 | |
151 | #define DEFAULT_RCV_DESCRIPTORS_10G 4096 | |
90d19005 | 152 | #define DEFAULT_RCV_DESCRIPTORS_VF 1024 |
251b036a | 153 | #define MAX_RDS_RINGS 2 |
af19b491 AKS |
154 | |
155 | #define get_next_index(index, length) \ | |
156 | (((index) + 1) & ((length) - 1)) | |
157 | ||
af19b491 AKS |
158 | /* |
159 | * Following data structures describe the descriptors that will be used. | |
160 | * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when | |
161 | * we are doing LSO (above the 1500 size packet) only. | |
162 | */ | |
af19b491 AKS |
163 | struct cmd_desc_type0 { |
164 | u8 tcp_hdr_offset; /* For LSO only */ | |
165 | u8 ip_hdr_offset; /* For LSO only */ | |
166 | __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */ | |
167 | __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */ | |
168 | ||
169 | __le64 addr_buffer2; | |
170 | ||
381709de SS |
171 | __le16 encap_descr; /* 15:10 offset of outer L3 header, |
172 | * 9:6 number of 32bit words in outer L3 header, | |
173 | * 5 offload outer L4 checksum, | |
174 | * 4 offload outer L3 checksum, | |
175 | * 3 Inner L4 type, TCP=0, UDP=1, | |
176 | * 2 Inner L3 type, IPv4=0, IPv6=1, | |
177 | * 1 Outer L3 type,IPv4=0, IPv6=1, | |
178 | * 0 type of encapsulation, GRE=0, VXLAN=1 | |
179 | */ | |
af19b491 AKS |
180 | __le16 mss; |
181 | u8 port_ctxid; /* 7:4 ctxid 3:0 port */ | |
381709de SS |
182 | u8 hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ |
183 | u8 outer_hdr_length; /* Encapsulation only */ | |
184 | u8 rsvd1; | |
af19b491 AKS |
185 | |
186 | __le64 addr_buffer3; | |
187 | __le64 addr_buffer1; | |
188 | ||
189 | __le16 buffer_length[4]; | |
190 | ||
191 | __le64 addr_buffer4; | |
192 | ||
2e9d722d | 193 | u8 eth_addr[ETH_ALEN]; |
381709de SS |
194 | __le16 vlan_TCI; /* In case of encapsulation, |
195 | * this is for outer VLAN | |
196 | */ | |
af19b491 AKS |
197 | |
198 | } __attribute__ ((aligned(64))); | |
199 | ||
200 | /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ | |
201 | struct rcv_desc { | |
202 | __le16 reference_handle; | |
203 | __le16 reserved; | |
204 | __le32 buffer_length; /* allocated buffer length (usually 2K) */ | |
205 | __le64 addr_buffer; | |
b1fc6d3c | 206 | } __packed; |
af19b491 | 207 | |
af19b491 AKS |
208 | struct status_desc { |
209 | __le64 status_desc_data[2]; | |
210 | } __attribute__ ((aligned(16))); | |
211 | ||
212 | /* UNIFIED ROMIMAGE */ | |
213 | #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000 | |
214 | #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0 | |
215 | #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6 | |
216 | #define QLCNIC_UNI_DIR_SECT_FW 0x7 | |
217 | ||
218 | /*Offsets */ | |
219 | #define QLCNIC_UNI_CHIP_REV_OFF 10 | |
220 | #define QLCNIC_UNI_FLAGS_OFF 11 | |
221 | #define QLCNIC_UNI_BIOS_VERSION_OFF 12 | |
222 | #define QLCNIC_UNI_BOOTLD_IDX_OFF 27 | |
223 | #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29 | |
224 | ||
225 | struct uni_table_desc{ | |
63507592 SS |
226 | __le32 findex; |
227 | __le32 num_entries; | |
228 | __le32 entry_size; | |
229 | __le32 reserved[5]; | |
af19b491 AKS |
230 | }; |
231 | ||
232 | struct uni_data_desc{ | |
63507592 SS |
233 | __le32 findex; |
234 | __le32 size; | |
235 | __le32 reserved[5]; | |
af19b491 AKS |
236 | }; |
237 | ||
0e5f20b6 | 238 | /* Flash Defines and Structures */ |
239 | #define QLCNIC_FLT_LOCATION 0x3F1000 | |
d865ebb4 | 240 | #define QLCNIC_FDT_LOCATION 0x3F0000 |
a2050c7e SV |
241 | #define QLCNIC_B0_FW_IMAGE_REGION 0x74 |
242 | #define QLCNIC_C0_FW_IMAGE_REGION 0x97 | |
f8d54811 | 243 | #define QLCNIC_BOOTLD_REGION 0X72 |
0e5f20b6 | 244 | struct qlcnic_flt_header { |
245 | u16 version; | |
246 | u16 len; | |
247 | u16 checksum; | |
248 | u16 reserved; | |
249 | }; | |
250 | ||
251 | struct qlcnic_flt_entry { | |
252 | u8 region; | |
253 | u8 reserved0; | |
254 | u8 attrib; | |
255 | u8 reserved1; | |
256 | u32 size; | |
257 | u32 start_addr; | |
f8d54811 | 258 | u32 end_addr; |
0e5f20b6 | 259 | }; |
260 | ||
d865ebb4 SC |
261 | /* Flash Descriptor Table */ |
262 | struct qlcnic_fdt { | |
263 | u32 valid; | |
264 | u16 ver; | |
265 | u16 len; | |
266 | u16 cksum; | |
267 | u16 unused; | |
268 | u8 model[16]; | |
26acc712 | 269 | u8 mfg_id; |
d865ebb4 SC |
270 | u16 id; |
271 | u8 flag; | |
272 | u8 erase_cmd; | |
273 | u8 alt_erase_cmd; | |
274 | u8 write_enable_cmd; | |
275 | u8 write_enable_bits; | |
276 | u8 write_statusreg_cmd; | |
277 | u8 unprotected_sec_cmd; | |
278 | u8 read_manuf_cmd; | |
279 | u32 block_size; | |
280 | u32 alt_block_size; | |
281 | u32 flash_size; | |
282 | u32 write_enable_data; | |
283 | u8 readid_addr_len; | |
284 | u8 write_disable_bits; | |
285 | u8 read_dev_id_len; | |
286 | u8 chip_erase_cmd; | |
287 | u16 read_timeo; | |
288 | u8 protected_sec_cmd; | |
289 | u8 resvd[65]; | |
290 | }; | |
af19b491 AKS |
291 | /* Magic number to let user know flash is programmed */ |
292 | #define QLCNIC_BDINFO_MAGIC 0x12345678 | |
293 | ||
ff1b1bf8 SV |
294 | #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021 |
295 | #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022 | |
296 | #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023 | |
297 | #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024 | |
298 | #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025 | |
299 | #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026 | |
300 | #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027 | |
301 | #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028 | |
302 | #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029 | |
303 | #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a | |
304 | #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b | |
305 | #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031 | |
306 | #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032 | |
307 | #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080 | |
af19b491 | 308 | |
2e9d722d AC |
309 | #define QLCNIC_MSIX_TABLE_OFFSET 0x44 |
310 | ||
af19b491 AKS |
311 | /* Flash memory map */ |
312 | #define QLCNIC_BRDCFG_START 0x4000 /* board config */ | |
313 | #define QLCNIC_BOOTLD_START 0x10000 /* bootld */ | |
314 | #define QLCNIC_IMAGE_START 0x43000 /* compressed image */ | |
00c7eb99 | 315 | #define QLCNIC_USER_START 0x3E8000 /* Firmware info */ |
af19b491 AKS |
316 | |
317 | #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408) | |
318 | #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c) | |
319 | #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c) | |
320 | #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c) | |
321 | ||
322 | #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8) | |
323 | #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128) | |
324 | ||
325 | #define QLCNIC_FW_MIN_SIZE (0x3fffff) | |
326 | #define QLCNIC_UNIFIED_ROMIMAGE 0 | |
327 | #define QLCNIC_FLASH_ROMIMAGE 1 | |
328 | #define QLCNIC_UNKNOWN_ROMIMAGE 0xff | |
329 | ||
330 | #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin" | |
331 | #define QLCNIC_FLASH_ROMIMAGE_NAME "flash" | |
332 | ||
333 | extern char qlcnic_driver_name[]; | |
334 | ||
629263ac SC |
335 | extern int qlcnic_use_msi; |
336 | extern int qlcnic_use_msi_x; | |
337 | extern int qlcnic_auto_fw_reset; | |
338 | extern int qlcnic_load_fw_file; | |
629263ac | 339 | |
af19b491 AKS |
340 | /* Number of status descriptors to handle per interrupt */ |
341 | #define MAX_STATUS_HANDLE (64) | |
342 | ||
343 | /* | |
344 | * qlcnic_skb_frag{} is to contain mapping info for each SG list. This | |
345 | * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}. | |
346 | */ | |
347 | struct qlcnic_skb_frag { | |
348 | u64 dma; | |
349 | u64 length; | |
350 | }; | |
351 | ||
af19b491 AKS |
352 | /* Following defines are for the state of the buffers */ |
353 | #define QLCNIC_BUFFER_FREE 0 | |
354 | #define QLCNIC_BUFFER_BUSY 1 | |
355 | ||
356 | /* | |
357 | * There will be one qlcnic_buffer per skb packet. These will be | |
358 | * used to save the dma info for pci_unmap_page() | |
359 | */ | |
360 | struct qlcnic_cmd_buffer { | |
361 | struct sk_buff *skb; | |
ef71ff83 | 362 | struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1]; |
af19b491 AKS |
363 | u32 frag_count; |
364 | }; | |
365 | ||
366 | /* In rx_buffer, we do not need multiple fragments as is a single buffer */ | |
367 | struct qlcnic_rx_buffer { | |
b1fc6d3c | 368 | u16 ref_handle; |
af19b491 | 369 | struct sk_buff *skb; |
b1fc6d3c | 370 | struct list_head list; |
af19b491 | 371 | u64 dma; |
af19b491 AKS |
372 | }; |
373 | ||
374 | /* Board types */ | |
375 | #define QLCNIC_GBE 0x01 | |
376 | #define QLCNIC_XGBE 0x02 | |
377 | ||
8816d009 AC |
378 | /* |
379 | * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is | |
380 | * adjusted based on configured MTU. | |
381 | */ | |
be273dc1 HM |
382 | #define QLCNIC_INTR_COAL_TYPE_RX 1 |
383 | #define QLCNIC_INTR_COAL_TYPE_TX 2 | |
a514722a | 384 | #define QLCNIC_INTR_COAL_TYPE_RX_TX 3 |
be273dc1 HM |
385 | |
386 | #define QLCNIC_DEF_INTR_COALESCE_RX_TIME_US 3 | |
387 | #define QLCNIC_DEF_INTR_COALESCE_RX_PACKETS 256 | |
388 | ||
389 | #define QLCNIC_DEF_INTR_COALESCE_TX_TIME_US 64 | |
390 | #define QLCNIC_DEF_INTR_COALESCE_TX_PACKETS 64 | |
8816d009 AC |
391 | |
392 | #define QLCNIC_INTR_DEFAULT 0x04 | |
393 | #define QLCNIC_CONFIG_INTR_COALESCE 3 | |
2f514c52 | 394 | #define QLCNIC_DEV_INFO_SIZE 2 |
8816d009 AC |
395 | |
396 | struct qlcnic_nic_intr_coalesce { | |
397 | u8 type; | |
398 | u8 sts_ring_mask; | |
399 | u16 rx_packets; | |
400 | u16 rx_time_us; | |
be273dc1 HM |
401 | u16 tx_packets; |
402 | u16 tx_time_us; | |
8816d009 AC |
403 | u16 flag; |
404 | u32 timer_out; | |
405 | }; | |
406 | ||
225837a0 | 407 | struct qlcnic_83xx_dump_template_hdr { |
63507592 SS |
408 | u32 type; |
409 | u32 offset; | |
410 | u32 size; | |
411 | u32 cap_mask; | |
412 | u32 num_entries; | |
413 | u32 version; | |
414 | u32 timestamp; | |
415 | u32 checksum; | |
416 | u32 drv_cap_mask; | |
417 | u32 sys_info[3]; | |
418 | u32 saved_state[16]; | |
419 | u32 cap_sizes[8]; | |
4e60ac46 | 420 | u32 ocm_wnd_reg[16]; |
63507592 | 421 | u32 rsvd[0]; |
18f2f616 AC |
422 | }; |
423 | ||
225837a0 SS |
424 | struct qlcnic_82xx_dump_template_hdr { |
425 | u32 type; | |
426 | u32 offset; | |
427 | u32 size; | |
428 | u32 cap_mask; | |
429 | u32 num_entries; | |
430 | u32 version; | |
431 | u32 timestamp; | |
432 | u32 checksum; | |
433 | u32 drv_cap_mask; | |
434 | u32 sys_info[3]; | |
435 | u32 saved_state[16]; | |
436 | u32 cap_sizes[8]; | |
437 | u32 rsvd[7]; | |
438 | u32 capabilities; | |
439 | u32 rsvd1[0]; | |
440 | }; | |
441 | ||
4da005cf SS |
442 | #define QLC_PEX_DMA_READ_SIZE (PAGE_SIZE * 16) |
443 | ||
18f2f616 AC |
444 | struct qlcnic_fw_dump { |
445 | u8 clr; /* flag to indicate if dump is cleared */ | |
890b6e02 | 446 | bool enable; /* enable/disable dump */ |
18f2f616 | 447 | u32 size; /* total size of the dump */ |
225837a0 | 448 | u32 cap_mask; /* Current capture mask */ |
18f2f616 | 449 | void *data; /* dump data area */ |
225837a0 | 450 | void *tmpl_hdr; |
9baf1aa9 SS |
451 | dma_addr_t phys_addr; |
452 | void *dma_buffer; | |
453 | bool use_pex_dma; | |
225837a0 SS |
454 | /* Read only elements which are common between 82xx and 83xx |
455 | * template header. Update these values immediately after we read | |
456 | * template header from Firmware | |
457 | */ | |
458 | u32 tmpl_hdr_size; | |
459 | u32 version; | |
460 | u32 num_entries; | |
461 | u32 offset; | |
18f2f616 AC |
462 | }; |
463 | ||
af19b491 AKS |
464 | /* |
465 | * One hardware_context{} per adapter | |
466 | * contains interrupt info as well shared hardware info. | |
467 | */ | |
468 | struct qlcnic_hardware_context { | |
469 | void __iomem *pci_base0; | |
470 | void __iomem *ocm_win_crb; | |
471 | ||
472 | unsigned long pci_len0; | |
473 | ||
af19b491 AKS |
474 | rwlock_t crb_lock; |
475 | struct mutex mem_lock; | |
476 | ||
af19b491 AKS |
477 | u8 revision_id; |
478 | u8 pci_func; | |
479 | u8 linkup; | |
22c8c934 | 480 | u8 loopback_state; |
79788450 SC |
481 | u8 beacon_state; |
482 | u8 has_link_events; | |
483 | u8 fw_type; | |
484 | u8 physical_port; | |
485 | u8 reset_context; | |
486 | u8 msix_supported; | |
487 | u8 max_mac_filters; | |
488 | u8 mc_enabled; | |
489 | u8 max_mc_count; | |
490 | u8 diag_test; | |
491 | u8 num_msix; | |
492 | u8 nic_mode; | |
97f3f6fc | 493 | int diag_cnt; |
79788450 | 494 | |
52e493d0 | 495 | u16 max_uc_count; |
af19b491 AKS |
496 | u16 port_type; |
497 | u16 board_type; | |
b938662d | 498 | u16 supported_type; |
8816d009 | 499 | |
79788450 SC |
500 | u16 link_speed; |
501 | u16 link_duplex; | |
502 | u16 link_autoneg; | |
503 | u16 module_type; | |
504 | ||
505 | u16 op_mode; | |
506 | u16 switch_mode; | |
507 | u16 max_tx_ques; | |
508 | u16 max_rx_ques; | |
509 | u16 max_mtu; | |
510 | u32 msg_enable; | |
2f514c52 | 511 | u16 total_nic_func; |
ee9e8b6c | 512 | u16 max_pci_func; |
2f514c52 JK |
513 | u32 max_vnic_func; |
514 | u32 total_pci_func; | |
728a98b8 | 515 | |
79788450 | 516 | u32 capabilities; |
db131786 | 517 | u32 extra_capability[3]; |
79788450 SC |
518 | u32 temp; |
519 | u32 int_vec_bit; | |
520 | u32 fw_hal_version; | |
7f966452 | 521 | u32 port_config; |
79788450 | 522 | struct qlcnic_hardware_ops *hw_ops; |
8816d009 | 523 | struct qlcnic_nic_intr_coalesce coal; |
18f2f616 | 524 | struct qlcnic_fw_dump fw_dump; |
d865ebb4 | 525 | struct qlcnic_fdt fdt; |
81d0aeb0 | 526 | struct qlc_83xx_reset reset; |
629263ac | 527 | struct qlc_83xx_idc idc; |
7000078a | 528 | struct qlc_83xx_fw_info *fw_info; |
7f966452 | 529 | struct qlcnic_intrpt_config *intr_tbl; |
02feda17 | 530 | struct qlcnic_sriov *sriov; |
7e2cf4fe | 531 | u32 *reg_tbl; |
7f966452 SC |
532 | u32 *ext_reg_tbl; |
533 | u32 mbox_aen[QLC_83XX_MBX_AEN_CNT]; | |
534 | u32 mbox_reg[4]; | |
e5c4e6c6 | 535 | struct qlcnic_mailbox *mailbox; |
77bead46 | 536 | u8 extend_lb_time; |
07a251c8 | 537 | u8 phys_port_id[ETH_ALEN]; |
d9c602f0 | 538 | u8 lb_mode; |
378fddc2 | 539 | u8 vxlan_port_count; |
2b3d7b75 | 540 | u16 vxlan_port; |
1f0f467b | 541 | struct device *hwmon_dev; |
3ced0a88 SS |
542 | u32 post_mode; |
543 | bool run_post; | |
af19b491 AKS |
544 | }; |
545 | ||
546 | struct qlcnic_adapter_stats { | |
547 | u64 xmitcalled; | |
548 | u64 xmitfinished; | |
549 | u64 rxdropped; | |
550 | u64 txdropped; | |
551 | u64 csummed; | |
552 | u64 rx_pkts; | |
553 | u64 lro_pkts; | |
554 | u64 rxbytes; | |
555 | u64 txbytes; | |
8bfe8b91 SC |
556 | u64 lrobytes; |
557 | u64 lso_frames; | |
381709de SS |
558 | u64 encap_lso_frames; |
559 | u64 encap_tx_csummed; | |
2b3d7b75 | 560 | u64 encap_rx_csummed; |
8bfe8b91 SC |
561 | u64 xmit_on; |
562 | u64 xmit_off; | |
563 | u64 skb_alloc_failure; | |
8ae6df97 AKS |
564 | u64 null_rxbuf; |
565 | u64 rx_dma_map_error; | |
566 | u64 tx_dma_map_error; | |
7f966452 | 567 | u64 spurious_intr; |
4be41e92 | 568 | u64 mac_filter_limit_overrun; |
819bfe76 | 569 | u64 mbx_spurious_intr; |
af19b491 AKS |
570 | }; |
571 | ||
572 | /* | |
573 | * Rcv Descriptor Context. One such per Rcv Descriptor. There may | |
574 | * be one Rcv Descriptor for normal packets, one for jumbo and may be others. | |
575 | */ | |
576 | struct qlcnic_host_rds_ring { | |
036d61f0 AC |
577 | void __iomem *crb_rcv_producer; |
578 | struct rcv_desc *desc_head; | |
579 | struct qlcnic_rx_buffer *rx_buf_arr; | |
af19b491 | 580 | u32 num_desc; |
036d61f0 | 581 | u32 producer; |
af19b491 AKS |
582 | u32 dma_size; |
583 | u32 skb_size; | |
584 | u32 flags; | |
af19b491 AKS |
585 | struct list_head free_list; |
586 | spinlock_t lock; | |
587 | dma_addr_t phys_addr; | |
036d61f0 | 588 | } ____cacheline_internodealigned_in_smp; |
af19b491 AKS |
589 | |
590 | struct qlcnic_host_sds_ring { | |
591 | u32 consumer; | |
592 | u32 num_desc; | |
593 | void __iomem *crb_sts_consumer; | |
af19b491 | 594 | |
012ec812 | 595 | struct qlcnic_host_tx_ring *tx_ring; |
af19b491 AKS |
596 | struct status_desc *desc_head; |
597 | struct qlcnic_adapter *adapter; | |
598 | struct napi_struct napi; | |
599 | struct list_head free_list[NUM_RCV_DESC_RINGS]; | |
600 | ||
036d61f0 | 601 | void __iomem *crb_intr_mask; |
af19b491 AKS |
602 | int irq; |
603 | ||
604 | dma_addr_t phys_addr; | |
ddb2e174 | 605 | char name[IFNAMSIZ + 12]; |
036d61f0 | 606 | } ____cacheline_internodealigned_in_smp; |
af19b491 | 607 | |
f27c75b3 HM |
608 | struct qlcnic_tx_queue_stats { |
609 | u64 xmit_on; | |
610 | u64 xmit_off; | |
611 | u64 xmit_called; | |
612 | u64 xmit_finished; | |
613 | u64 tx_bytes; | |
614 | }; | |
615 | ||
af19b491 | 616 | struct qlcnic_host_tx_ring { |
4be41e92 | 617 | int irq; |
7f966452 | 618 | void __iomem *crb_intr_mask; |
ddb2e174 | 619 | char name[IFNAMSIZ + 12]; |
79788450 | 620 | u16 ctx_id; |
012ec812 HM |
621 | |
622 | u32 state; | |
af19b491 | 623 | u32 producer; |
af19b491 | 624 | u32 sw_consumer; |
af19b491 | 625 | u32 num_desc; |
012ec812 | 626 | |
f27c75b3 | 627 | struct qlcnic_tx_queue_stats tx_stats; |
012ec812 | 628 | |
036d61f0 | 629 | void __iomem *crb_cmd_producer; |
af19b491 | 630 | struct cmd_desc_type0 *desc_head; |
4be41e92 SC |
631 | struct qlcnic_adapter *adapter; |
632 | struct napi_struct napi; | |
036d61f0 AC |
633 | struct qlcnic_cmd_buffer *cmd_buf_arr; |
634 | __le32 *hw_consumer; | |
635 | ||
af19b491 AKS |
636 | dma_addr_t phys_addr; |
637 | dma_addr_t hw_cons_phys_addr; | |
036d61f0 | 638 | struct netdev_queue *txq; |
a02bdd42 SS |
639 | /* Lock to protect Tx descriptors cleanup */ |
640 | spinlock_t tx_clean_lock; | |
036d61f0 | 641 | } ____cacheline_internodealigned_in_smp; |
af19b491 AKS |
642 | |
643 | /* | |
644 | * Receive context. There is one such structure per instance of the | |
645 | * receive processing. Any state information that is relevant to | |
646 | * the receive, and is must be in this structure. The global data may be | |
647 | * present elsewhere. | |
648 | */ | |
649 | struct qlcnic_recv_context { | |
b1fc6d3c AC |
650 | struct qlcnic_host_rds_ring *rds_rings; |
651 | struct qlcnic_host_sds_ring *sds_rings; | |
af19b491 AKS |
652 | u32 state; |
653 | u16 context_id; | |
654 | u16 virt_port; | |
af19b491 AKS |
655 | }; |
656 | ||
657 | /* HW context creation */ | |
658 | ||
659 | #define QLCNIC_OS_CRB_RETRY_COUNT 4000 | |
af19b491 AKS |
660 | |
661 | #define QLCNIC_CDRP_CMD_BIT 0x80000000 | |
662 | ||
663 | /* | |
664 | * All responses must have the QLCNIC_CDRP_CMD_BIT cleared | |
665 | * in the crb QLCNIC_CDRP_CRB_OFFSET. | |
666 | */ | |
667 | #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp) | |
668 | #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0) | |
669 | ||
670 | #define QLCNIC_CDRP_RSP_OK 0x00000001 | |
671 | #define QLCNIC_CDRP_RSP_FAIL 0x00000002 | |
672 | #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003 | |
673 | ||
674 | /* | |
675 | * All commands must have the QLCNIC_CDRP_CMD_BIT set in | |
676 | * the crb QLCNIC_CDRP_CRB_OFFSET. | |
677 | */ | |
678 | #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd)) | |
af19b491 AKS |
679 | |
680 | #define QLCNIC_RCODE_SUCCESS 0 | |
e42ede22 | 681 | #define QLCNIC_RCODE_INVALID_ARGS 6 |
7e610caa | 682 | #define QLCNIC_RCODE_NOT_SUPPORTED 9 |
e42ede22 JK |
683 | #define QLCNIC_RCODE_NOT_PERMITTED 10 |
684 | #define QLCNIC_RCODE_NOT_IMPL 15 | |
685 | #define QLCNIC_RCODE_INVALID 16 | |
af19b491 AKS |
686 | #define QLCNIC_RCODE_TIMEOUT 17 |
687 | #define QLCNIC_DESTROY_CTX_RESET 0 | |
688 | ||
689 | /* | |
690 | * Capabilities Announced | |
691 | */ | |
692 | #define QLCNIC_CAP0_LEGACY_CONTEXT (1) | |
693 | #define QLCNIC_CAP0_LEGACY_MN (1 << 2) | |
694 | #define QLCNIC_CAP0_LSO (1 << 6) | |
695 | #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7) | |
696 | #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8) | |
8f891387 | 697 | #define QLCNIC_CAP0_VALIDOFF (1 << 11) |
cae82d49 | 698 | #define QLCNIC_CAP0_LRO_MSS (1 << 21) |
012ec812 | 699 | #define QLCNIC_CAP0_TX_MULTI (1 << 22) |
af19b491 AKS |
700 | |
701 | /* | |
702 | * Context state | |
703 | */ | |
d626ad4d | 704 | #define QLCNIC_HOST_CTX_STATE_FREED 0 |
af19b491 AKS |
705 | #define QLCNIC_HOST_CTX_STATE_ACTIVE 2 |
706 | ||
707 | /* | |
708 | * Rx context | |
709 | */ | |
710 | ||
711 | struct qlcnic_hostrq_sds_ring { | |
712 | __le64 host_phys_addr; /* Ring base addr */ | |
713 | __le32 ring_size; /* Ring entries */ | |
714 | __le16 msi_index; | |
715 | __le16 rsvd; /* Padding */ | |
b1fc6d3c | 716 | } __packed; |
af19b491 AKS |
717 | |
718 | struct qlcnic_hostrq_rds_ring { | |
719 | __le64 host_phys_addr; /* Ring base addr */ | |
720 | __le64 buff_size; /* Packet buffer size */ | |
721 | __le32 ring_size; /* Ring entries */ | |
722 | __le32 ring_kind; /* Class of ring */ | |
b1fc6d3c | 723 | } __packed; |
af19b491 AKS |
724 | |
725 | struct qlcnic_hostrq_rx_ctx { | |
726 | __le64 host_rsp_dma_addr; /* Response dma'd here */ | |
012ec812 | 727 | __le32 capabilities[4]; /* Flag bit vector */ |
af19b491 AKS |
728 | __le32 host_int_crb_mode; /* Interrupt crb usage */ |
729 | __le32 host_rds_crb_mode; /* RDS crb usage */ | |
730 | /* These ring offsets are relative to data[0] below */ | |
731 | __le32 rds_ring_offset; /* Offset to RDS config */ | |
732 | __le32 sds_ring_offset; /* Offset to SDS config */ | |
733 | __le16 num_rds_rings; /* Count of RDS rings */ | |
734 | __le16 num_sds_rings; /* Count of SDS rings */ | |
8f891387 | 735 | __le16 valid_field_offset; |
736 | u8 txrx_sds_binding; | |
737 | u8 msix_handler; | |
738 | u8 reserved[128]; /* reserve space for future expansion*/ | |
af19b491 AKS |
739 | /* MUST BE 64-bit aligned. |
740 | The following is packed: | |
741 | - N hostrq_rds_rings | |
742 | - N hostrq_sds_rings */ | |
743 | char data[0]; | |
b1fc6d3c | 744 | } __packed; |
af19b491 AKS |
745 | |
746 | struct qlcnic_cardrsp_rds_ring{ | |
747 | __le32 host_producer_crb; /* Crb to use */ | |
748 | __le32 rsvd1; /* Padding */ | |
b1fc6d3c | 749 | } __packed; |
af19b491 AKS |
750 | |
751 | struct qlcnic_cardrsp_sds_ring { | |
752 | __le32 host_consumer_crb; /* Crb to use */ | |
753 | __le32 interrupt_crb; /* Crb to use */ | |
b1fc6d3c | 754 | } __packed; |
af19b491 AKS |
755 | |
756 | struct qlcnic_cardrsp_rx_ctx { | |
757 | /* These ring offsets are relative to data[0] below */ | |
758 | __le32 rds_ring_offset; /* Offset to RDS config */ | |
759 | __le32 sds_ring_offset; /* Offset to SDS config */ | |
760 | __le32 host_ctx_state; /* Starting State */ | |
761 | __le32 num_fn_per_port; /* How many PCI fn share the port */ | |
762 | __le16 num_rds_rings; /* Count of RDS rings */ | |
763 | __le16 num_sds_rings; /* Count of SDS rings */ | |
764 | __le16 context_id; /* Handle for context */ | |
765 | u8 phys_port; /* Physical id of port */ | |
766 | u8 virt_port; /* Virtual/Logical id of port */ | |
767 | u8 reserved[128]; /* save space for future expansion */ | |
768 | /* MUST BE 64-bit aligned. | |
769 | The following is packed: | |
770 | - N cardrsp_rds_rings | |
771 | - N cardrs_sds_rings */ | |
772 | char data[0]; | |
b1fc6d3c | 773 | } __packed; |
af19b491 AKS |
774 | |
775 | #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \ | |
776 | (sizeof(HOSTRQ_RX) + \ | |
777 | (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \ | |
778 | (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring))) | |
779 | ||
780 | #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \ | |
781 | (sizeof(CARDRSP_RX) + \ | |
782 | (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \ | |
783 | (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring))) | |
784 | ||
785 | /* | |
786 | * Tx context | |
787 | */ | |
788 | ||
789 | struct qlcnic_hostrq_cds_ring { | |
790 | __le64 host_phys_addr; /* Ring base addr */ | |
791 | __le32 ring_size; /* Ring entries */ | |
792 | __le32 rsvd; /* Padding */ | |
b1fc6d3c | 793 | } __packed; |
af19b491 AKS |
794 | |
795 | struct qlcnic_hostrq_tx_ctx { | |
796 | __le64 host_rsp_dma_addr; /* Response dma'd here */ | |
797 | __le64 cmd_cons_dma_addr; /* */ | |
798 | __le64 dummy_dma_addr; /* */ | |
799 | __le32 capabilities[4]; /* Flag bit vector */ | |
800 | __le32 host_int_crb_mode; /* Interrupt crb usage */ | |
801 | __le32 rsvd1; /* Padding */ | |
802 | __le16 rsvd2; /* Padding */ | |
803 | __le16 interrupt_ctl; | |
804 | __le16 msi_index; | |
805 | __le16 rsvd3; /* Padding */ | |
806 | struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */ | |
807 | u8 reserved[128]; /* future expansion */ | |
b1fc6d3c | 808 | } __packed; |
af19b491 AKS |
809 | |
810 | struct qlcnic_cardrsp_cds_ring { | |
811 | __le32 host_producer_crb; /* Crb to use */ | |
812 | __le32 interrupt_crb; /* Crb to use */ | |
b1fc6d3c | 813 | } __packed; |
af19b491 AKS |
814 | |
815 | struct qlcnic_cardrsp_tx_ctx { | |
816 | __le32 host_ctx_state; /* Starting state */ | |
817 | __le16 context_id; /* Handle for context */ | |
818 | u8 phys_port; /* Physical id of port */ | |
819 | u8 virt_port; /* Virtual/Logical id of port */ | |
820 | struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */ | |
821 | u8 reserved[128]; /* future expansion */ | |
b1fc6d3c | 822 | } __packed; |
af19b491 AKS |
823 | |
824 | #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX)) | |
825 | #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX)) | |
826 | ||
827 | /* CRB */ | |
828 | ||
829 | #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0 | |
830 | #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1 | |
831 | #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2 | |
832 | #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3 | |
833 | ||
834 | #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0 | |
835 | #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1 | |
836 | #define QLCNIC_HOST_INT_CRB_MODE_NORX 2 | |
837 | #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3 | |
838 | #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4 | |
839 | ||
840 | ||
841 | /* MAC */ | |
842 | ||
ff1b1bf8 | 843 | #define MC_COUNT_P3P 38 |
af19b491 AKS |
844 | |
845 | #define QLCNIC_MAC_NOOP 0 | |
846 | #define QLCNIC_MAC_ADD 1 | |
847 | #define QLCNIC_MAC_DEL 2 | |
03c5d770 AKS |
848 | #define QLCNIC_MAC_VLAN_ADD 3 |
849 | #define QLCNIC_MAC_VLAN_DEL 4 | |
af19b491 | 850 | |
fe79fabb SS |
851 | enum qlcnic_mac_type { |
852 | QLCNIC_UNICAST_MAC, | |
853 | QLCNIC_MULTICAST_MAC, | |
854 | QLCNIC_BROADCAST_MAC, | |
855 | }; | |
856 | ||
154d0c81 | 857 | struct qlcnic_mac_vlan_list { |
af19b491 AKS |
858 | struct list_head list; |
859 | uint8_t mac_addr[ETH_ALEN+2]; | |
154d0c81 | 860 | u16 vlan_id; |
fe79fabb | 861 | enum qlcnic_mac_type mac_type; |
af19b491 AKS |
862 | }; |
863 | ||
fe1adc6b JK |
864 | /* MAC Learn */ |
865 | #define NO_MAC_LEARN 0 | |
866 | #define DRV_MAC_LEARN 1 | |
867 | #define FDB_MAC_LEARN 2 | |
868 | ||
af19b491 AKS |
869 | #define QLCNIC_HOST_REQUEST 0x13 |
870 | #define QLCNIC_REQUEST 0x14 | |
871 | ||
872 | #define QLCNIC_MAC_EVENT 0x1 | |
873 | ||
874 | #define QLCNIC_IP_UP 2 | |
875 | #define QLCNIC_IP_DOWN 3 | |
876 | ||
22c8c934 | 877 | #define QLCNIC_ILB_MODE 0x1 |
e1428d26 | 878 | #define QLCNIC_ELB_MODE 0x2 |
d9c602f0 | 879 | #define QLCNIC_LB_MODE_MASK 0x3 |
22c8c934 SC |
880 | |
881 | #define QLCNIC_LINKEVENT 0x1 | |
882 | #define QLCNIC_LB_RESPONSE 0x2 | |
883 | #define QLCNIC_IS_LB_CONFIGURED(VAL) \ | |
884 | (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE)) | |
885 | ||
af19b491 AKS |
886 | /* |
887 | * Driver --> Firmware | |
888 | */ | |
b1fc6d3c AC |
889 | #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1 |
890 | #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3 | |
891 | #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4 | |
892 | #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7 | |
893 | #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc | |
894 | #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12 | |
22c8c934 | 895 | |
b1fc6d3c AC |
896 | #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15 |
897 | #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17 | |
898 | #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18 | |
22c8c934 SC |
899 | #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13 |
900 | ||
af19b491 AKS |
901 | /* |
902 | * Firmware --> Driver | |
903 | */ | |
904 | ||
22c8c934 | 905 | #define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f |
7f966452 | 906 | #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 0x8D |
2d8ebcab | 907 | #define QLCNIC_C2H_OPCODE_GET_DCB_AEN 0x90 |
af19b491 AKS |
908 | |
909 | #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ | |
910 | #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ | |
911 | #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ | |
912 | ||
913 | #define QLCNIC_LRO_REQUEST_CLEANUP 4 | |
914 | ||
915 | /* Capabilites received */ | |
ac8d0c4f AC |
916 | #define QLCNIC_FW_CAPABILITY_TSO BIT_1 |
917 | #define QLCNIC_FW_CAPABILITY_BDG BIT_8 | |
918 | #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9 | |
919 | #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10 | |
012ec812 | 920 | #define QLCNIC_FW_CAPABILITY_2_MULTI_TX BIT_4 |
fef0c060 | 921 | #define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK BIT_27 |
cae82d49 RB |
922 | #define QLCNIC_FW_CAPABILITY_MORE_CAPS BIT_31 |
923 | ||
924 | #define QLCNIC_FW_CAPABILITY_2_LRO_MAX_TCP_SEG BIT_2 | |
776e7bde | 925 | #define QLCNIC_FW_CAP2_HW_LRO_IPV6 BIT_3 |
8af3f33d | 926 | #define QLCNIC_FW_CAPABILITY_SET_DRV_VER BIT_5 |
487042af | 927 | #define QLCNIC_FW_CAPABILITY_2_BEACON BIT_7 |
2f514c52 | 928 | #define QLCNIC_FW_CAPABILITY_2_PER_PORT_ESWITCH_CFG BIT_9 |
d01a6d3c | 929 | #define QLCNIC_FW_CAPABILITY_2_EXT_ISCSI_DUMP BIT_13 |
af19b491 | 930 | |
2b3d7b75 | 931 | #define QLCNIC_83XX_FW_CAPAB_ENCAP_RX_OFFLOAD BIT_0 |
381709de SS |
932 | #define QLCNIC_83XX_FW_CAPAB_ENCAP_TX_OFFLOAD BIT_1 |
933 | #define QLCNIC_83XX_FW_CAPAB_ENCAP_CKO_OFFLOAD BIT_4 | |
934 | ||
af19b491 AKS |
935 | /* module types */ |
936 | #define LINKEVENT_MODULE_NOT_PRESENT 1 | |
937 | #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2 | |
938 | #define LINKEVENT_MODULE_OPTICAL_SRLR 3 | |
939 | #define LINKEVENT_MODULE_OPTICAL_LRM 4 | |
940 | #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5 | |
941 | #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6 | |
942 | #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7 | |
943 | #define LINKEVENT_MODULE_TWINAX 8 | |
944 | ||
945 | #define LINKSPEED_10GBPS 10000 | |
946 | #define LINKSPEED_1GBPS 1000 | |
947 | #define LINKSPEED_100MBPS 100 | |
948 | #define LINKSPEED_10MBPS 10 | |
949 | ||
950 | #define LINKSPEED_ENCODED_10MBPS 0 | |
951 | #define LINKSPEED_ENCODED_100MBPS 1 | |
952 | #define LINKSPEED_ENCODED_1GBPS 2 | |
953 | ||
954 | #define LINKEVENT_AUTONEG_DISABLED 0 | |
955 | #define LINKEVENT_AUTONEG_ENABLED 1 | |
956 | ||
957 | #define LINKEVENT_HALF_DUPLEX 0 | |
958 | #define LINKEVENT_FULL_DUPLEX 1 | |
959 | ||
960 | #define LINKEVENT_LINKSPEED_MBPS 0 | |
961 | #define LINKEVENT_LINKSPEED_ENCODED 1 | |
962 | ||
af19b491 AKS |
963 | /* firmware response header: |
964 | * 63:58 - message type | |
965 | * 57:56 - owner | |
966 | * 55:53 - desc count | |
967 | * 52:48 - reserved | |
968 | * 47:40 - completion id | |
969 | * 39:32 - opcode | |
970 | * 31:16 - error code | |
971 | * 15:00 - reserved | |
972 | */ | |
973 | #define qlcnic_get_nic_msg_opcode(msg_hdr) \ | |
974 | ((msg_hdr >> 32) & 0xFF) | |
975 | ||
976 | struct qlcnic_fw_msg { | |
977 | union { | |
978 | struct { | |
979 | u64 hdr; | |
980 | u64 body[7]; | |
981 | }; | |
982 | u64 words[8]; | |
983 | }; | |
984 | }; | |
985 | ||
986 | struct qlcnic_nic_req { | |
987 | __le64 qhdr; | |
988 | __le64 req_hdr; | |
989 | __le64 words[6]; | |
b1fc6d3c | 990 | } __packed; |
af19b491 AKS |
991 | |
992 | struct qlcnic_mac_req { | |
993 | u8 op; | |
994 | u8 tag; | |
995 | u8 mac_addr[6]; | |
996 | }; | |
997 | ||
7e56cac4 SC |
998 | struct qlcnic_vlan_req { |
999 | __le16 vlan_id; | |
1000 | __le16 rsvd[3]; | |
b1fc6d3c | 1001 | } __packed; |
7e56cac4 | 1002 | |
b501595c SC |
1003 | struct qlcnic_ipaddr { |
1004 | __be32 ipv4; | |
1005 | __be32 ipv6[4]; | |
1006 | }; | |
1007 | ||
af19b491 AKS |
1008 | #define QLCNIC_MSI_ENABLED 0x02 |
1009 | #define QLCNIC_MSIX_ENABLED 0x04 | |
7f966452 | 1010 | #define QLCNIC_LRO_ENABLED 0x01 |
24763d80 | 1011 | #define QLCNIC_LRO_DISABLED 0x00 |
af19b491 AKS |
1012 | #define QLCNIC_BRIDGE_ENABLED 0X10 |
1013 | #define QLCNIC_DIAG_ENABLED 0x20 | |
0e33c664 | 1014 | #define QLCNIC_ESWITCH_ENABLED 0x40 |
0866d96d | 1015 | #define QLCNIC_ADAPTER_INITIALIZED 0x80 |
8cf61f89 | 1016 | #define QLCNIC_TAGGING_ENABLED 0x100 |
fe4d434d | 1017 | #define QLCNIC_MACSPOOF 0x200 |
7373373d | 1018 | #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400 |
ee07c1a7 | 1019 | #define QLCNIC_PROMISC_DISABLED 0x800 |
b0044bcf | 1020 | #define QLCNIC_NEED_FLR 0x1000 |
602ca6f0 | 1021 | #define QLCNIC_FW_RESET_OWNER 0x2000 |
032a13c7 | 1022 | #define QLCNIC_FW_HANG 0x4000 |
cae82d49 | 1023 | #define QLCNIC_FW_LRO_MSS_CAP 0x8000 |
da6c8063 | 1024 | #define QLCNIC_TX_INTR_SHARED 0x10000 |
147a9088 | 1025 | #define QLCNIC_APP_CHANGED_FLAGS 0x20000 |
07a251c8 | 1026 | #define QLCNIC_HAS_PHYS_PORT_ID 0x40000 |
cb9327d5 | 1027 | #define QLCNIC_TSS_RSS 0x80000 |
7f1f6056 SS |
1028 | |
1029 | #ifdef CONFIG_QLCNIC_VXLAN | |
2b3d7b75 SS |
1030 | #define QLCNIC_ADD_VXLAN_PORT 0x100000 |
1031 | #define QLCNIC_DEL_VXLAN_PORT 0x200000 | |
7f1f6056 | 1032 | #endif |
07a251c8 | 1033 | |
d747c333 RB |
1034 | #define QLCNIC_VLAN_FILTERING 0x800000 |
1035 | ||
af19b491 AKS |
1036 | #define QLCNIC_IS_MSI_FAMILY(adapter) \ |
1037 | ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED)) | |
147a9088 SS |
1038 | #define QLCNIC_IS_TSO_CAPABLE(adapter) \ |
1039 | ((adapter)->ahw->capabilities & QLCNIC_FW_CAPABILITY_TSO) | |
af19b491 | 1040 | |
487042af HM |
1041 | #define QLCNIC_BEACON_EANBLE 0xC |
1042 | #define QLCNIC_BEACON_DISABLE 0xD | |
1043 | ||
a0431589 HM |
1044 | #define QLCNIC_BEACON_ON 2 |
1045 | #define QLCNIC_BEACON_OFF 0 | |
1046 | ||
af19b491 AKS |
1047 | #define QLCNIC_MSIX_TBL_SPACE 8192 |
1048 | #define QLCNIC_PCI_REG_MSIX_TBL 0x44 | |
2e9d722d | 1049 | #define QLCNIC_MSIX_TBL_PGSIZE 4096 |
af19b491 | 1050 | |
af19b491 AKS |
1051 | #define QLCNIC_ADAPTER_UP_MAGIC 777 |
1052 | ||
1053 | #define __QLCNIC_FW_ATTACHED 0 | |
1054 | #define __QLCNIC_DEV_UP 1 | |
1055 | #define __QLCNIC_RESETTING 2 | |
1056 | #define __QLCNIC_START_FW 4 | |
451724c8 | 1057 | #define __QLCNIC_AER 5 |
89b4208e | 1058 | #define __QLCNIC_DIAG_RES_ALLOC 6 |
728a98b8 | 1059 | #define __QLCNIC_LED_ENABLE 7 |
02feda17 | 1060 | #define __QLCNIC_ELB_INPROGRESS 8 |
012ec812 | 1061 | #define __QLCNIC_MULTI_TX_UNIQUE 9 |
02feda17 RB |
1062 | #define __QLCNIC_SRIOV_ENABLE 10 |
1063 | #define __QLCNIC_SRIOV_CAPABLE 11 | |
7ed3ce48 | 1064 | #define __QLCNIC_MBX_POLL_ENABLE 12 |
4690a7e4 | 1065 | #define __QLCNIC_DIAG_MODE 13 |
78ea2d97 | 1066 | #define __QLCNIC_MAINTENANCE_MODE 16 |
af19b491 | 1067 | |
7eb9855d | 1068 | #define QLCNIC_INTERRUPT_TEST 1 |
cdaff185 | 1069 | #define QLCNIC_LOOPBACK_TEST 2 |
c75822a3 | 1070 | #define QLCNIC_LED_TEST 3 |
7eb9855d | 1071 | |
b5e5492c | 1072 | #define QLCNIC_FILTER_AGE 80 |
e5edb7b1 | 1073 | #define QLCNIC_READD_AGE 20 |
b5e5492c | 1074 | #define QLCNIC_LB_MAX_FILTERS 64 |
7f966452 | 1075 | #define QLCNIC_LB_BUCKET_SIZE 32 |
629263ac | 1076 | #define QLCNIC_ILB_MAX_RCV_LOOP 10 |
fef0c060 | 1077 | |
b5e5492c AKS |
1078 | struct qlcnic_filter { |
1079 | struct hlist_node fnode; | |
1080 | u8 faddr[ETH_ALEN]; | |
f80bc8fe | 1081 | u16 vlan_id; |
b5e5492c AKS |
1082 | unsigned long ftime; |
1083 | }; | |
1084 | ||
1085 | struct qlcnic_filter_hash { | |
1086 | struct hlist_head *fhead; | |
1087 | u8 fnum; | |
7f966452 SC |
1088 | u16 fmax; |
1089 | u16 fbucket_size; | |
b5e5492c AKS |
1090 | }; |
1091 | ||
e5c4e6c6 MC |
1092 | /* Mailbox specific data structures */ |
1093 | struct qlcnic_mailbox { | |
1094 | struct workqueue_struct *work_q; | |
1095 | struct qlcnic_adapter *adapter; | |
571f2c11 | 1096 | const struct qlcnic_mbx_ops *ops; |
e5c4e6c6 MC |
1097 | struct work_struct work; |
1098 | struct completion completion; | |
1099 | struct list_head cmd_q; | |
1100 | unsigned long status; | |
1101 | spinlock_t queue_lock; /* Mailbox queue lock */ | |
1102 | spinlock_t aen_lock; /* Mailbox response/AEN lock */ | |
5bf93251 | 1103 | u32 rsp_status; |
e5c4e6c6 MC |
1104 | u32 num_cmds; |
1105 | }; | |
1106 | ||
af19b491 | 1107 | struct qlcnic_adapter { |
b1fc6d3c AC |
1108 | struct qlcnic_hardware_context *ahw; |
1109 | struct qlcnic_recv_context *recv_ctx; | |
1110 | struct qlcnic_host_tx_ring *tx_ring; | |
af19b491 AKS |
1111 | struct net_device *netdev; |
1112 | struct pci_dev *pdev; | |
af19b491 | 1113 | |
b1fc6d3c AC |
1114 | unsigned long state; |
1115 | u32 flags; | |
af19b491 AKS |
1116 | |
1117 | u16 num_txd; | |
1118 | u16 num_rxd; | |
1119 | u16 num_jumbo_rxd; | |
90d19005 SC |
1120 | u16 max_rxd; |
1121 | u16 max_jumbo_rxd; | |
af19b491 AKS |
1122 | |
1123 | u8 max_rds_rings; | |
34e8c406 HM |
1124 | |
1125 | u8 max_sds_rings; /* max sds rings supported by adapter */ | |
1126 | u8 max_tx_rings; /* max tx rings supported by adapter */ | |
1127 | ||
1128 | u8 drv_tx_rings; /* max tx rings supported by driver */ | |
1129 | u8 drv_sds_rings; /* max sds rings supported by driver */ | |
1130 | ||
cb9327d5 HM |
1131 | u8 drv_tss_rings; /* tss ring input */ |
1132 | u8 drv_rss_rings; /* rss ring input */ | |
1133 | ||
7f966452 | 1134 | u8 rx_csum; |
af19b491 | 1135 | u8 portnum; |
af19b491 | 1136 | |
af19b491 AKS |
1137 | u8 fw_wait_cnt; |
1138 | u8 fw_fail_cnt; | |
1139 | u8 tx_timeo_cnt; | |
1140 | u8 need_fw_reset; | |
f036e4f4 | 1141 | u8 reset_ctx_cnt; |
af19b491 | 1142 | |
af19b491 | 1143 | u16 is_up; |
91b7282b RB |
1144 | u16 rx_pvid; |
1145 | u16 tx_pvid; | |
2e9d722d | 1146 | |
af19b491 | 1147 | u32 irq; |
4e70812b | 1148 | u32 heartbeat; |
af19b491 AKS |
1149 | |
1150 | u8 dev_state; | |
aa5e18c0 SC |
1151 | u8 reset_ack_timeo; |
1152 | u8 dev_init_timeo; | |
af19b491 AKS |
1153 | |
1154 | u8 mac_addr[ETH_ALEN]; | |
1155 | ||
6df900e9 | 1156 | u64 dev_rst_time; |
fe1adc6b JK |
1157 | bool drv_mac_learn; |
1158 | bool fdb_mac_learn; | |
72ebe349 | 1159 | bool rx_mac_learn; |
b9796a14 | 1160 | unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
d865ebb4 | 1161 | u8 flash_mfg_id; |
346fe763 | 1162 | struct qlcnic_npar_info *npars; |
2e9d722d AC |
1163 | struct qlcnic_eswitch *eswitch; |
1164 | struct qlcnic_nic_template *nic_ops; | |
1165 | ||
af19b491 | 1166 | struct qlcnic_adapter_stats stats; |
b1fc6d3c | 1167 | struct list_head mac_list; |
af19b491 AKS |
1168 | |
1169 | void __iomem *tgt_mask_reg; | |
1170 | void __iomem *tgt_status_reg; | |
1171 | void __iomem *crb_int_state_reg; | |
1172 | void __iomem *isr_int_vec; | |
1173 | ||
f94bc1e7 | 1174 | struct msix_entry *msix_entries; |
7f966452 | 1175 | struct workqueue_struct *qlcnic_wq; |
af19b491 | 1176 | struct delayed_work fw_work; |
7f966452 | 1177 | struct delayed_work idc_aen_work; |
7ed3ce48 | 1178 | struct delayed_work mbx_poll_work; |
14d385b9 | 1179 | struct qlcnic_dcb *dcb; |
af19b491 | 1180 | |
b5e5492c | 1181 | struct qlcnic_filter_hash fhash; |
53643a75 | 1182 | struct qlcnic_filter_hash rx_fhash; |
e8b508ef | 1183 | struct list_head vf_mc_list; |
b5e5492c | 1184 | |
b1fc6d3c | 1185 | spinlock_t mac_learn_lock; |
53643a75 SS |
1186 | /* spinlock for catching rcv filters for eswitch traffic */ |
1187 | spinlock_t rx_mac_learn_lock; | |
63507592 | 1188 | u32 file_prd_off; /*File fw product offset*/ |
af19b491 | 1189 | u32 fw_version; |
147a9088 | 1190 | u32 offload_flags; |
af19b491 AKS |
1191 | const struct firmware *fw; |
1192 | }; | |
1193 | ||
63507592 | 1194 | struct qlcnic_info_le { |
2e9d722d | 1195 | __le16 pci_func; |
63507592 | 1196 | __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */ |
2e9d722d | 1197 | __le16 phys_port; |
63507592 | 1198 | __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */ |
2e9d722d AC |
1199 | |
1200 | __le32 capabilities; | |
1201 | u8 max_mac_filters; | |
1202 | u8 reserved1; | |
1203 | __le16 max_mtu; | |
1204 | ||
1205 | __le16 max_tx_ques; | |
1206 | __le16 max_rx_ques; | |
1207 | __le16 min_tx_bw; | |
1208 | __le16 max_tx_bw; | |
7f966452 SC |
1209 | __le32 op_type; |
1210 | __le16 max_bw_reg_offset; | |
1211 | __le16 max_linkspeed_reg_offset; | |
1212 | __le32 capability1; | |
1213 | __le32 capability2; | |
1214 | __le32 capability3; | |
1215 | __le16 max_tx_mac_filters; | |
1216 | __le16 max_rx_mcast_mac_filters; | |
1217 | __le16 max_rx_ucast_mac_filters; | |
1218 | __le16 max_rx_ip_addr; | |
1219 | __le16 max_rx_lro_flow; | |
1220 | __le16 max_rx_status_rings; | |
1221 | __le16 max_rx_buf_rings; | |
1222 | __le16 max_tx_vlan_keys; | |
1223 | u8 total_pf; | |
1224 | u8 total_rss_engines; | |
1225 | __le16 max_vports; | |
02feda17 RB |
1226 | __le16 linkstate_reg_offset; |
1227 | __le16 bit_offsets; | |
1228 | __le16 max_local_ipv6_addrs; | |
1229 | __le16 max_remote_ipv6_addrs; | |
1230 | u8 reserved2[56]; | |
b1fc6d3c | 1231 | } __packed; |
2e9d722d | 1232 | |
63507592 SS |
1233 | struct qlcnic_info { |
1234 | u16 pci_func; | |
1235 | u16 op_mode; | |
1236 | u16 phys_port; | |
1237 | u16 switch_mode; | |
1238 | u32 capabilities; | |
1239 | u8 max_mac_filters; | |
63507592 SS |
1240 | u16 max_mtu; |
1241 | u16 max_tx_ques; | |
1242 | u16 max_rx_ques; | |
1243 | u16 min_tx_bw; | |
1244 | u16 max_tx_bw; | |
7f966452 SC |
1245 | u32 op_type; |
1246 | u16 max_bw_reg_offset; | |
1247 | u16 max_linkspeed_reg_offset; | |
1248 | u32 capability1; | |
1249 | u32 capability2; | |
1250 | u32 capability3; | |
1251 | u16 max_tx_mac_filters; | |
1252 | u16 max_rx_mcast_mac_filters; | |
1253 | u16 max_rx_ucast_mac_filters; | |
1254 | u16 max_rx_ip_addr; | |
1255 | u16 max_rx_lro_flow; | |
1256 | u16 max_rx_status_rings; | |
1257 | u16 max_rx_buf_rings; | |
1258 | u16 max_tx_vlan_keys; | |
1259 | u8 total_pf; | |
1260 | u8 total_rss_engines; | |
1261 | u16 max_vports; | |
02feda17 RB |
1262 | u16 linkstate_reg_offset; |
1263 | u16 bit_offsets; | |
1264 | u16 max_local_ipv6_addrs; | |
1265 | u16 max_remote_ipv6_addrs; | |
63507592 | 1266 | }; |
2e9d722d | 1267 | |
63507592 SS |
1268 | struct qlcnic_pci_info_le { |
1269 | __le16 id; /* pci function id */ | |
1270 | __le16 active; /* 1 = Enabled */ | |
1271 | __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */ | |
1272 | __le16 default_port; /* default port number */ | |
1273 | ||
1274 | __le16 tx_min_bw; /* Multiple of 100mbpc */ | |
2e9d722d AC |
1275 | __le16 tx_max_bw; |
1276 | __le16 reserved1[2]; | |
1277 | ||
1278 | u8 mac[ETH_ALEN]; | |
7f966452 SC |
1279 | __le16 func_count; |
1280 | u8 reserved2[104]; | |
1281 | ||
b1fc6d3c | 1282 | } __packed; |
2e9d722d | 1283 | |
63507592 SS |
1284 | struct qlcnic_pci_info { |
1285 | u16 id; | |
1286 | u16 active; | |
1287 | u16 type; | |
1288 | u16 default_port; | |
1289 | u16 tx_min_bw; | |
1290 | u16 tx_max_bw; | |
1291 | u8 mac[ETH_ALEN]; | |
7f966452 | 1292 | u16 func_count; |
63507592 SS |
1293 | }; |
1294 | ||
346fe763 | 1295 | struct qlcnic_npar_info { |
35dafcb0 | 1296 | bool eswitch_status; |
4e8acb01 | 1297 | u16 pvid; |
cea8975e AC |
1298 | u16 min_bw; |
1299 | u16 max_bw; | |
346fe763 RB |
1300 | u8 phy_port; |
1301 | u8 type; | |
1302 | u8 active; | |
1303 | u8 enable_pm; | |
1304 | u8 dest_npar; | |
346fe763 | 1305 | u8 discard_tagged; |
7373373d | 1306 | u8 mac_override; |
4e8acb01 RB |
1307 | u8 mac_anti_spoof; |
1308 | u8 promisc_mode; | |
1309 | u8 offload_flags; | |
bff57d8e | 1310 | u8 pci_func; |
9e630955 | 1311 | u8 mac[ETH_ALEN]; |
346fe763 | 1312 | }; |
4e8acb01 | 1313 | |
2e9d722d AC |
1314 | struct qlcnic_eswitch { |
1315 | u8 port; | |
1316 | u8 active_vports; | |
1317 | u8 active_vlans; | |
1318 | u8 active_ucast_filters; | |
1319 | u8 max_ucast_filters; | |
1320 | u8 max_active_vlans; | |
1321 | ||
1322 | u32 flags; | |
1323 | #define QLCNIC_SWITCH_ENABLE BIT_1 | |
1324 | #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2 | |
1325 | #define QLCNIC_SWITCH_PROMISC_MODE BIT_3 | |
1326 | #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4 | |
1327 | }; | |
1328 | ||
346fe763 | 1329 | |
2abea2f0 | 1330 | #define MAX_BW 100 /* % of link speed */ |
ed616689 | 1331 | #define MIN_BW 1 /* % of link speed */ |
346fe763 RB |
1332 | #define MAX_VLAN_ID 4095 |
1333 | #define MIN_VLAN_ID 2 | |
346fe763 RB |
1334 | #define DEFAULT_MAC_LEARN 1 |
1335 | ||
0184bbba | 1336 | #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID) |
2abea2f0 | 1337 | #define IS_VALID_BW(bw) (bw <= MAX_BW) |
346fe763 RB |
1338 | |
1339 | struct qlcnic_pci_func_cfg { | |
1340 | u16 func_type; | |
1341 | u16 min_bw; | |
1342 | u16 max_bw; | |
1343 | u16 port_num; | |
1344 | u8 pci_func; | |
1345 | u8 func_state; | |
f3c0773f | 1346 | u8 def_mac_addr[ETH_ALEN]; |
346fe763 RB |
1347 | }; |
1348 | ||
1349 | struct qlcnic_npar_func_cfg { | |
1350 | u32 fw_capab; | |
1351 | u16 port_num; | |
1352 | u16 min_bw; | |
1353 | u16 max_bw; | |
1354 | u16 max_tx_queues; | |
1355 | u16 max_rx_queues; | |
1356 | u8 pci_func; | |
1357 | u8 op_mode; | |
1358 | }; | |
1359 | ||
1360 | struct qlcnic_pm_func_cfg { | |
1361 | u8 pci_func; | |
1362 | u8 action; | |
1363 | u8 dest_npar; | |
1364 | u8 reserved[5]; | |
1365 | }; | |
1366 | ||
1367 | struct qlcnic_esw_func_cfg { | |
1368 | u16 vlan_id; | |
4e8acb01 RB |
1369 | u8 op_mode; |
1370 | u8 op_type; | |
346fe763 RB |
1371 | u8 pci_func; |
1372 | u8 host_vlan_tag; | |
1373 | u8 promisc_mode; | |
1374 | u8 discard_tagged; | |
7373373d | 1375 | u8 mac_override; |
4e8acb01 RB |
1376 | u8 mac_anti_spoof; |
1377 | u8 offload_flags; | |
1378 | u8 reserved[5]; | |
346fe763 RB |
1379 | }; |
1380 | ||
b6021212 AKS |
1381 | #define QLCNIC_STATS_VERSION 1 |
1382 | #define QLCNIC_STATS_PORT 1 | |
1383 | #define QLCNIC_STATS_ESWITCH 2 | |
1384 | #define QLCNIC_QUERY_RX_COUNTER 0 | |
1385 | #define QLCNIC_QUERY_TX_COUNTER 1 | |
54a8997c JK |
1386 | #define QLCNIC_STATS_NOT_AVAIL 0xffffffffffffffffULL |
1387 | #define QLCNIC_FILL_STATS(VAL1) \ | |
1388 | (((VAL1) == QLCNIC_STATS_NOT_AVAIL) ? 0 : VAL1) | |
1389 | #define QLCNIC_MAC_STATS 1 | |
1390 | #define QLCNIC_ESW_STATS 2 | |
ef182805 AKS |
1391 | |
1392 | #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\ | |
1393 | do { \ | |
54a8997c JK |
1394 | if (((VAL1) == QLCNIC_STATS_NOT_AVAIL) && \ |
1395 | ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \ | |
ef182805 | 1396 | (VAL1) = (VAL2); \ |
54a8997c JK |
1397 | else if (((VAL1) != QLCNIC_STATS_NOT_AVAIL) && \ |
1398 | ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \ | |
ef182805 AKS |
1399 | (VAL1) += (VAL2); \ |
1400 | } while (0) | |
1401 | ||
63507592 | 1402 | struct qlcnic_mac_statistics_le { |
54a8997c JK |
1403 | __le64 mac_tx_frames; |
1404 | __le64 mac_tx_bytes; | |
1405 | __le64 mac_tx_mcast_pkts; | |
1406 | __le64 mac_tx_bcast_pkts; | |
1407 | __le64 mac_tx_pause_cnt; | |
1408 | __le64 mac_tx_ctrl_pkt; | |
1409 | __le64 mac_tx_lt_64b_pkts; | |
1410 | __le64 mac_tx_lt_127b_pkts; | |
1411 | __le64 mac_tx_lt_255b_pkts; | |
1412 | __le64 mac_tx_lt_511b_pkts; | |
1413 | __le64 mac_tx_lt_1023b_pkts; | |
1414 | __le64 mac_tx_lt_1518b_pkts; | |
1415 | __le64 mac_tx_gt_1518b_pkts; | |
1416 | __le64 rsvd1[3]; | |
1417 | ||
1418 | __le64 mac_rx_frames; | |
1419 | __le64 mac_rx_bytes; | |
1420 | __le64 mac_rx_mcast_pkts; | |
1421 | __le64 mac_rx_bcast_pkts; | |
1422 | __le64 mac_rx_pause_cnt; | |
1423 | __le64 mac_rx_ctrl_pkt; | |
1424 | __le64 mac_rx_lt_64b_pkts; | |
1425 | __le64 mac_rx_lt_127b_pkts; | |
1426 | __le64 mac_rx_lt_255b_pkts; | |
1427 | __le64 mac_rx_lt_511b_pkts; | |
1428 | __le64 mac_rx_lt_1023b_pkts; | |
1429 | __le64 mac_rx_lt_1518b_pkts; | |
1430 | __le64 mac_rx_gt_1518b_pkts; | |
1431 | __le64 rsvd2[3]; | |
1432 | ||
1433 | __le64 mac_rx_length_error; | |
1434 | __le64 mac_rx_length_small; | |
1435 | __le64 mac_rx_length_large; | |
1436 | __le64 mac_rx_jabber; | |
1437 | __le64 mac_rx_dropped; | |
1438 | __le64 mac_rx_crc_error; | |
1439 | __le64 mac_align_error; | |
1440 | } __packed; | |
1441 | ||
63507592 SS |
1442 | struct qlcnic_mac_statistics { |
1443 | u64 mac_tx_frames; | |
1444 | u64 mac_tx_bytes; | |
1445 | u64 mac_tx_mcast_pkts; | |
1446 | u64 mac_tx_bcast_pkts; | |
1447 | u64 mac_tx_pause_cnt; | |
1448 | u64 mac_tx_ctrl_pkt; | |
1449 | u64 mac_tx_lt_64b_pkts; | |
1450 | u64 mac_tx_lt_127b_pkts; | |
1451 | u64 mac_tx_lt_255b_pkts; | |
1452 | u64 mac_tx_lt_511b_pkts; | |
1453 | u64 mac_tx_lt_1023b_pkts; | |
1454 | u64 mac_tx_lt_1518b_pkts; | |
1455 | u64 mac_tx_gt_1518b_pkts; | |
1456 | u64 rsvd1[3]; | |
1457 | u64 mac_rx_frames; | |
1458 | u64 mac_rx_bytes; | |
1459 | u64 mac_rx_mcast_pkts; | |
1460 | u64 mac_rx_bcast_pkts; | |
1461 | u64 mac_rx_pause_cnt; | |
1462 | u64 mac_rx_ctrl_pkt; | |
1463 | u64 mac_rx_lt_64b_pkts; | |
1464 | u64 mac_rx_lt_127b_pkts; | |
1465 | u64 mac_rx_lt_255b_pkts; | |
1466 | u64 mac_rx_lt_511b_pkts; | |
1467 | u64 mac_rx_lt_1023b_pkts; | |
1468 | u64 mac_rx_lt_1518b_pkts; | |
1469 | u64 mac_rx_gt_1518b_pkts; | |
1470 | u64 rsvd2[3]; | |
1471 | u64 mac_rx_length_error; | |
1472 | u64 mac_rx_length_small; | |
1473 | u64 mac_rx_length_large; | |
1474 | u64 mac_rx_jabber; | |
1475 | u64 mac_rx_dropped; | |
1476 | u64 mac_rx_crc_error; | |
1477 | u64 mac_align_error; | |
1478 | }; | |
1479 | ||
1480 | struct qlcnic_esw_stats_le { | |
b6021212 AKS |
1481 | __le16 context_id; |
1482 | __le16 version; | |
1483 | __le16 size; | |
1484 | __le16 unused; | |
1485 | __le64 unicast_frames; | |
1486 | __le64 multicast_frames; | |
1487 | __le64 broadcast_frames; | |
1488 | __le64 dropped_frames; | |
1489 | __le64 errors; | |
1490 | __le64 local_frames; | |
1491 | __le64 numbytes; | |
1492 | __le64 rsvd[3]; | |
b1fc6d3c | 1493 | } __packed; |
b6021212 | 1494 | |
63507592 SS |
1495 | struct __qlcnic_esw_statistics { |
1496 | u16 context_id; | |
1497 | u16 version; | |
1498 | u16 size; | |
1499 | u16 unused; | |
1500 | u64 unicast_frames; | |
1501 | u64 multicast_frames; | |
1502 | u64 broadcast_frames; | |
1503 | u64 dropped_frames; | |
1504 | u64 errors; | |
1505 | u64 local_frames; | |
1506 | u64 numbytes; | |
1507 | u64 rsvd[3]; | |
1508 | }; | |
1509 | ||
b6021212 AKS |
1510 | struct qlcnic_esw_statistics { |
1511 | struct __qlcnic_esw_statistics rx; | |
1512 | struct __qlcnic_esw_statistics tx; | |
1513 | }; | |
1514 | ||
18f2f616 | 1515 | #define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed |
9d6a6440 AC |
1516 | #define QLCNIC_ENABLE_FW_DUMP 0xaddfeed |
1517 | #define QLCNIC_DISABLE_FW_DUMP 0xbadfeed | |
3d46512c | 1518 | #define QLCNIC_FORCE_FW_RESET 0xdeaddead |
b43e5ee7 SC |
1519 | #define QLCNIC_SET_QUIESCENT 0xadd00010 |
1520 | #define QLCNIC_RESET_QUIESCENT 0xadd00020 | |
18f2f616 | 1521 | |
7777de9a | 1522 | struct _cdrp_cmd { |
7e2cf4fe SC |
1523 | u32 num; |
1524 | u32 *arg; | |
7777de9a AC |
1525 | }; |
1526 | ||
1527 | struct qlcnic_cmd_args { | |
e5c4e6c6 MC |
1528 | struct completion completion; |
1529 | struct list_head list; | |
1530 | struct _cdrp_cmd req; | |
1531 | struct _cdrp_cmd rsp; | |
1532 | atomic_t rsp_status; | |
1533 | int pay_size; | |
1534 | u32 rsp_opcode; | |
1535 | u32 total_cmds; | |
1536 | u32 op_type; | |
1537 | u32 type; | |
1538 | u32 cmd_op; | |
1539 | u32 *hdr; /* Back channel message header */ | |
1540 | u32 *pay; /* Back channel message payload */ | |
1541 | u8 func_num; | |
7777de9a AC |
1542 | }; |
1543 | ||
18f2f616 | 1544 | int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter); |
7e610caa | 1545 | int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config); |
af19b491 AKS |
1546 | int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data); |
1547 | int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data); | |
897e8c7c DP |
1548 | |
1549 | #define ADDR_IN_RANGE(addr, low, high) \ | |
1550 | (((addr) < (high)) && ((addr) >= (low))) | |
af19b491 | 1551 | |
4bd8e738 HM |
1552 | #define QLCRD32(adapter, off, err) \ |
1553 | (adapter->ahw->hw_ops->read_reg)(adapter, off, err) | |
7e2cf4fe | 1554 | |
af19b491 | 1555 | #define QLCWR32(adapter, off, val) \ |
7e2cf4fe | 1556 | adapter->ahw->hw_ops->write_reg(adapter, off, val) |
af19b491 AKS |
1557 | |
1558 | int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32); | |
1559 | void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int); | |
1560 | ||
1561 | #define qlcnic_rom_lock(a) \ | |
1562 | qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID) | |
1563 | #define qlcnic_rom_unlock(a) \ | |
1564 | qlcnic_pcie_sem_unlock((a), 2) | |
1565 | #define qlcnic_phy_lock(a) \ | |
1566 | qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID) | |
1567 | #define qlcnic_phy_unlock(a) \ | |
1568 | qlcnic_pcie_sem_unlock((a), 3) | |
af19b491 AKS |
1569 | #define qlcnic_sw_lock(a) \ |
1570 | qlcnic_pcie_sem_lock((a), 6, 0) | |
1571 | #define qlcnic_sw_unlock(a) \ | |
1572 | qlcnic_pcie_sem_unlock((a), 6) | |
1573 | #define crb_win_lock(a) \ | |
1574 | qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID) | |
1575 | #define crb_win_unlock(a) \ | |
1576 | qlcnic_pcie_sem_unlock((a), 7) | |
1577 | ||
728a98b8 SC |
1578 | #define __QLCNIC_MAX_LED_RATE 0xf |
1579 | #define __QLCNIC_MAX_LED_STATE 0x2 | |
1580 | ||
58634e74 SC |
1581 | #define MAX_CTL_CHECK 1000 |
1582 | ||
b5e5492c AKS |
1583 | void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter); |
1584 | void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter); | |
18f2f616 | 1585 | int qlcnic_dump_fw(struct qlcnic_adapter *); |
890b6e02 SS |
1586 | int qlcnic_enable_fw_dump_state(struct qlcnic_adapter *); |
1587 | bool qlcnic_check_fw_dump_state(struct qlcnic_adapter *); | |
af19b491 AKS |
1588 | |
1589 | /* Functions from qlcnic_init.c */ | |
13159183 | 1590 | void qlcnic_schedule_work(struct qlcnic_adapter *, work_func_t, int); |
af19b491 AKS |
1591 | int qlcnic_load_firmware(struct qlcnic_adapter *adapter); |
1592 | int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter); | |
1593 | void qlcnic_request_firmware(struct qlcnic_adapter *adapter); | |
1594 | void qlcnic_release_firmware(struct qlcnic_adapter *adapter); | |
1595 | int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter); | |
b3a24649 | 1596 | int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter); |
8f891387 | 1597 | int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter); |
af19b491 | 1598 | |
18f2f616 | 1599 | int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp); |
af19b491 AKS |
1600 | int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr, |
1601 | u8 *bytes, size_t size); | |
1602 | int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter); | |
1603 | void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter); | |
1604 | ||
15087c2b | 1605 | void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *, u32); |
af19b491 AKS |
1606 | |
1607 | int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter); | |
1608 | void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter); | |
1609 | ||
8a15ad1f AKS |
1610 | int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter); |
1611 | void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter); | |
1612 | ||
1613 | void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter); | |
af19b491 | 1614 | void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter); |
012ec812 HM |
1615 | void qlcnic_release_tx_buffers(struct qlcnic_adapter *, |
1616 | struct qlcnic_host_tx_ring *); | |
af19b491 | 1617 | |
d4066833 | 1618 | int qlcnic_check_fw_status(struct qlcnic_adapter *adapter); |
af19b491 | 1619 | void qlcnic_watchdog_task(struct work_struct *work); |
b1fc6d3c | 1620 | void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, |
4be41e92 | 1621 | struct qlcnic_host_rds_ring *rds_ring, u8 ring_id); |
af19b491 | 1622 | void qlcnic_set_multi(struct net_device *netdev); |
fe79fabb SS |
1623 | void qlcnic_flush_mcast_mac(struct qlcnic_adapter *); |
1624 | int qlcnic_nic_add_mac(struct qlcnic_adapter *, const u8 *, u16, | |
1625 | enum qlcnic_mac_type); | |
fe1adc6b | 1626 | int qlcnic_nic_del_mac(struct qlcnic_adapter *, const u8 *); |
91b7282b | 1627 | void qlcnic_82xx_free_mac_list(struct qlcnic_adapter *adapter); |
07a251c8 | 1628 | int qlcnic_82xx_read_phys_port_id(struct qlcnic_adapter *); |
af19b491 AKS |
1629 | |
1630 | int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu); | |
8af3f33d | 1631 | int qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter *, u32); |
af19b491 | 1632 | int qlcnic_change_mtu(struct net_device *netdev, int new_mtu); |
c8f44aff MM |
1633 | netdev_features_t qlcnic_fix_features(struct net_device *netdev, |
1634 | netdev_features_t features); | |
1635 | int qlcnic_set_features(struct net_device *netdev, netdev_features_t features); | |
2e9d722d | 1636 | int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable); |
5ad6ff9d | 1637 | void qlcnic_update_cmd_producer(struct qlcnic_host_tx_ring *); |
22c8c934 SC |
1638 | |
1639 | /* Functions from qlcnic_ethtool.c */ | |
ba4468db JK |
1640 | int qlcnic_check_loopback_buff(unsigned char *, u8 []); |
1641 | int qlcnic_do_lb_test(struct qlcnic_adapter *, u8); | |
af19b491 AKS |
1642 | |
1643 | /* Functions from qlcnic_main.c */ | |
1644 | int qlcnic_reset_context(struct qlcnic_adapter *); | |
34e8c406 HM |
1645 | void qlcnic_diag_free_res(struct net_device *netdev, int); |
1646 | int qlcnic_diag_alloc_res(struct net_device *netdev, int); | |
1647 | netdev_tx_t qlcnic_xmit_frame(struct sk_buff *, struct net_device *); | |
1648 | void qlcnic_set_tx_ring_count(struct qlcnic_adapter *, u8); | |
1649 | void qlcnic_set_sds_ring_count(struct qlcnic_adapter *, u8); | |
cb9327d5 | 1650 | int qlcnic_setup_rings(struct qlcnic_adapter *); |
34e8c406 | 1651 | int qlcnic_validate_rings(struct qlcnic_adapter *, __u32, int); |
e5dcf6dc | 1652 | void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter); |
7f966452 | 1653 | int qlcnic_enable_msix(struct qlcnic_adapter *, u32); |
8af3f33d | 1654 | void qlcnic_set_drv_version(struct qlcnic_adapter *); |
af19b491 | 1655 | |
2e9d722d | 1656 | /* eSwitch management functions */ |
4e8acb01 RB |
1657 | int qlcnic_config_switch_port(struct qlcnic_adapter *, |
1658 | struct qlcnic_esw_func_cfg *); | |
629263ac | 1659 | |
4e8acb01 RB |
1660 | int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *, |
1661 | struct qlcnic_esw_func_cfg *); | |
2e9d722d | 1662 | int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8); |
b6021212 AKS |
1663 | int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8, |
1664 | struct __qlcnic_esw_statistics *); | |
1665 | int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8, | |
1666 | struct __qlcnic_esw_statistics *); | |
1667 | int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8); | |
54a8997c | 1668 | int qlcnic_get_mac_stats(struct qlcnic_adapter *, struct qlcnic_mac_statistics *); |
2e9d722d | 1669 | |
7e2cf4fe | 1670 | void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd); |
7e2cf4fe | 1671 | |
c70001a9 SC |
1672 | int qlcnic_alloc_sds_rings(struct qlcnic_recv_context *, int); |
1673 | void qlcnic_free_sds_rings(struct qlcnic_recv_context *); | |
7f966452 | 1674 | void qlcnic_advert_link_change(struct qlcnic_adapter *, int); |
c70001a9 SC |
1675 | void qlcnic_free_tx_rings(struct qlcnic_adapter *); |
1676 | int qlcnic_alloc_tx_rings(struct qlcnic_adapter *, struct net_device *); | |
012ec812 | 1677 | void qlcnic_dump_mbx(struct qlcnic_adapter *, struct qlcnic_cmd_args *); |
c70001a9 | 1678 | |
ec079a07 SC |
1679 | void qlcnic_create_sysfs_entries(struct qlcnic_adapter *adapter); |
1680 | void qlcnic_remove_sysfs_entries(struct qlcnic_adapter *adapter); | |
7e2cf4fe SC |
1681 | void qlcnic_82xx_add_sysfs(struct qlcnic_adapter *adapter); |
1682 | void qlcnic_82xx_remove_sysfs(struct qlcnic_adapter *adapter); | |
1683 | ||
ec079a07 SC |
1684 | int qlcnicvf_config_bridged_mode(struct qlcnic_adapter *, u32); |
1685 | int qlcnicvf_config_led(struct qlcnic_adapter *, u32, u32); | |
1686 | void qlcnic_set_vlan_config(struct qlcnic_adapter *, | |
1687 | struct qlcnic_esw_func_cfg *); | |
1688 | void qlcnic_set_eswitch_port_features(struct qlcnic_adapter *, | |
1689 | struct qlcnic_esw_func_cfg *); | |
cb9327d5 | 1690 | int qlcnic_setup_tss_rss_intr(struct qlcnic_adapter *); |
629263ac SC |
1691 | void qlcnic_down(struct qlcnic_adapter *, struct net_device *); |
1692 | int qlcnic_up(struct qlcnic_adapter *, struct net_device *); | |
319ecf12 SC |
1693 | void __qlcnic_down(struct qlcnic_adapter *, struct net_device *); |
1694 | void qlcnic_detach(struct qlcnic_adapter *); | |
1695 | void qlcnic_teardown_intr(struct qlcnic_adapter *); | |
1696 | int qlcnic_attach(struct qlcnic_adapter *); | |
1697 | int __qlcnic_up(struct qlcnic_adapter *, struct net_device *); | |
1698 | void qlcnic_restore_indev_addr(struct net_device *, unsigned long); | |
1699 | ||
629263ac | 1700 | int qlcnic_check_temp(struct qlcnic_adapter *); |
d71170fb SC |
1701 | int qlcnic_init_pci_info(struct qlcnic_adapter *); |
1702 | int qlcnic_set_default_offload_settings(struct qlcnic_adapter *); | |
1703 | int qlcnic_reset_npar_config(struct qlcnic_adapter *); | |
1704 | int qlcnic_set_eswitch_port_config(struct qlcnic_adapter *); | |
02feda17 | 1705 | int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter); |
f8468331 RB |
1706 | int qlcnic_read_mac_addr(struct qlcnic_adapter *); |
1707 | int qlcnic_setup_netdev(struct qlcnic_adapter *, struct net_device *, int); | |
147a9088 SS |
1708 | void qlcnic_set_netdev_features(struct qlcnic_adapter *, |
1709 | struct qlcnic_esw_func_cfg *); | |
74b7ba1a | 1710 | void qlcnic_sriov_vf_set_multi(struct net_device *); |
2f514c52 JK |
1711 | int qlcnic_is_valid_nic_func(struct qlcnic_adapter *, u8); |
1712 | int qlcnic_get_pci_func_type(struct qlcnic_adapter *, u16, u16 *, u16 *, | |
1713 | u16 *); | |
f8468331 | 1714 | |
af19b491 AKS |
1715 | /* |
1716 | * QLOGIC Board information | |
1717 | */ | |
1718 | ||
02420be6 | 1719 | #define QLCNIC_MAX_BOARD_NAME_LEN 100 |
22999798 | 1720 | struct qlcnic_board_info { |
af19b491 AKS |
1721 | unsigned short vendor; |
1722 | unsigned short device; | |
1723 | unsigned short sub_vendor; | |
1724 | unsigned short sub_device; | |
1725 | char short_name[QLCNIC_MAX_BOARD_NAME_LEN]; | |
1726 | }; | |
1727 | ||
af19b491 AKS |
1728 | static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring) |
1729 | { | |
036d61f0 | 1730 | if (likely(tx_ring->producer < tx_ring->sw_consumer)) |
af19b491 AKS |
1731 | return tx_ring->sw_consumer - tx_ring->producer; |
1732 | else | |
1733 | return tx_ring->sw_consumer + tx_ring->num_desc - | |
1734 | tx_ring->producer; | |
1735 | } | |
1736 | ||
7e2cf4fe SC |
1737 | struct qlcnic_nic_template { |
1738 | int (*config_bridged_mode) (struct qlcnic_adapter *, u32); | |
1739 | int (*config_led) (struct qlcnic_adapter *, u32, u32); | |
1740 | int (*start_firmware) (struct qlcnic_adapter *); | |
1741 | int (*init_driver) (struct qlcnic_adapter *); | |
1742 | void (*request_reset) (struct qlcnic_adapter *, u32); | |
1743 | void (*cancel_idc_work) (struct qlcnic_adapter *); | |
1744 | int (*napi_add)(struct qlcnic_adapter *, struct net_device *); | |
4be41e92 | 1745 | void (*napi_del)(struct qlcnic_adapter *); |
7e2cf4fe SC |
1746 | void (*config_ipaddr)(struct qlcnic_adapter *, __be32, int); |
1747 | irqreturn_t (*clear_legacy_intr)(struct qlcnic_adapter *); | |
486a5bc7 RB |
1748 | int (*shutdown)(struct pci_dev *); |
1749 | int (*resume)(struct qlcnic_adapter *); | |
7e2cf4fe SC |
1750 | }; |
1751 | ||
e5c4e6c6 MC |
1752 | struct qlcnic_mbx_ops { |
1753 | int (*enqueue_cmd) (struct qlcnic_adapter *, | |
1754 | struct qlcnic_cmd_args *, unsigned long *); | |
1755 | void (*dequeue_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); | |
1756 | void (*decode_resp) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); | |
1757 | void (*encode_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); | |
1758 | void (*nofity_fw) (struct qlcnic_adapter *, u8); | |
1759 | }; | |
1760 | ||
1761 | int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *); | |
1762 | void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *); | |
1763 | void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx); | |
1764 | void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx); | |
1ac6762a | 1765 | void qlcnic_update_stats(struct qlcnic_adapter *); |
e5c4e6c6 | 1766 | |
7e2cf4fe SC |
1767 | /* Adapter hardware abstraction */ |
1768 | struct qlcnic_hardware_ops { | |
1769 | void (*read_crb) (struct qlcnic_adapter *, char *, loff_t, size_t); | |
1770 | void (*write_crb) (struct qlcnic_adapter *, char *, loff_t, size_t); | |
4bd8e738 | 1771 | int (*read_reg) (struct qlcnic_adapter *, ulong, int *); |
7e2cf4fe SC |
1772 | int (*write_reg) (struct qlcnic_adapter *, ulong, u32); |
1773 | void (*get_ocm_win) (struct qlcnic_hardware_context *); | |
07a251c8 | 1774 | int (*get_mac_address) (struct qlcnic_adapter *, u8 *, u8); |
34e8c406 | 1775 | int (*setup_intr) (struct qlcnic_adapter *); |
7e2cf4fe SC |
1776 | int (*alloc_mbx_args)(struct qlcnic_cmd_args *, |
1777 | struct qlcnic_adapter *, u32); | |
1778 | int (*mbx_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); | |
1779 | void (*get_func_no) (struct qlcnic_adapter *); | |
1780 | int (*api_lock) (struct qlcnic_adapter *); | |
1781 | void (*api_unlock) (struct qlcnic_adapter *); | |
1782 | void (*add_sysfs) (struct qlcnic_adapter *); | |
1783 | void (*remove_sysfs) (struct qlcnic_adapter *); | |
1784 | void (*process_lb_rcv_ring_diag) (struct qlcnic_host_sds_ring *); | |
1785 | int (*create_rx_ctx) (struct qlcnic_adapter *); | |
1786 | int (*create_tx_ctx) (struct qlcnic_adapter *, | |
1787 | struct qlcnic_host_tx_ring *, int); | |
7cb03b23 RB |
1788 | void (*del_rx_ctx) (struct qlcnic_adapter *); |
1789 | void (*del_tx_ctx) (struct qlcnic_adapter *, | |
1790 | struct qlcnic_host_tx_ring *); | |
7e2cf4fe SC |
1791 | int (*setup_link_event) (struct qlcnic_adapter *, int); |
1792 | int (*get_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *, u8); | |
1793 | int (*get_pci_info) (struct qlcnic_adapter *, struct qlcnic_pci_info *); | |
1794 | int (*set_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *); | |
f80bc8fe | 1795 | int (*change_macvlan) (struct qlcnic_adapter *, u8*, u16, u8); |
7e2cf4fe SC |
1796 | void (*napi_enable) (struct qlcnic_adapter *); |
1797 | void (*napi_disable) (struct qlcnic_adapter *); | |
a514722a HM |
1798 | int (*config_intr_coal) (struct qlcnic_adapter *, |
1799 | struct ethtool_coalesce *); | |
7e2cf4fe SC |
1800 | int (*config_rss) (struct qlcnic_adapter *, int); |
1801 | int (*config_hw_lro) (struct qlcnic_adapter *, int); | |
1802 | int (*config_loopback) (struct qlcnic_adapter *, u8); | |
1803 | int (*clear_loopback) (struct qlcnic_adapter *, u8); | |
1804 | int (*config_promisc_mode) (struct qlcnic_adapter *, u32); | |
f80bc8fe | 1805 | void (*change_l2_filter) (struct qlcnic_adapter *, u64 *, u16); |
7e2cf4fe | 1806 | int (*get_board_info) (struct qlcnic_adapter *); |
52e493d0 | 1807 | void (*set_mac_filter_count) (struct qlcnic_adapter *); |
91b7282b | 1808 | void (*free_mac_list) (struct qlcnic_adapter *); |
07a251c8 | 1809 | int (*read_phys_port_id) (struct qlcnic_adapter *); |
4460f2e8 PP |
1810 | pci_ers_result_t (*io_error_detected) (struct pci_dev *, |
1811 | pci_channel_state_t); | |
1812 | pci_ers_result_t (*io_slot_reset) (struct pci_dev *); | |
1813 | void (*io_resume) (struct pci_dev *); | |
a0431589 | 1814 | void (*get_beacon_state)(struct qlcnic_adapter *); |
2cc5752e M |
1815 | void (*enable_sds_intr) (struct qlcnic_adapter *, |
1816 | struct qlcnic_host_sds_ring *); | |
1817 | void (*disable_sds_intr) (struct qlcnic_adapter *, | |
1818 | struct qlcnic_host_sds_ring *); | |
1819 | void (*enable_tx_intr) (struct qlcnic_adapter *, | |
1820 | struct qlcnic_host_tx_ring *); | |
1821 | void (*disable_tx_intr) (struct qlcnic_adapter *, | |
1822 | struct qlcnic_host_tx_ring *); | |
225837a0 SS |
1823 | u32 (*get_saved_state)(void *, u32); |
1824 | void (*set_saved_state)(void *, u32, u32); | |
1825 | void (*cache_tmpl_hdr_values)(struct qlcnic_fw_dump *); | |
1826 | u32 (*get_cap_size)(void *, int); | |
1827 | void (*set_sys_info)(void *, int, u32); | |
1828 | void (*store_cap_mask)(void *, u32); | |
7e2cf4fe SC |
1829 | }; |
1830 | ||
1831 | extern struct qlcnic_nic_template qlcnic_vf_ops; | |
1832 | ||
381709de SS |
1833 | static inline bool qlcnic_encap_tx_offload(struct qlcnic_adapter *adapter) |
1834 | { | |
1835 | return adapter->ahw->extra_capability[0] & | |
1836 | QLCNIC_83XX_FW_CAPAB_ENCAP_TX_OFFLOAD; | |
1837 | } | |
1838 | ||
2b3d7b75 SS |
1839 | static inline bool qlcnic_encap_rx_offload(struct qlcnic_adapter *adapter) |
1840 | { | |
1841 | return adapter->ahw->extra_capability[0] & | |
1842 | QLCNIC_83XX_FW_CAPAB_ENCAP_RX_OFFLOAD; | |
1843 | } | |
1844 | ||
7e2cf4fe SC |
1845 | static inline int qlcnic_start_firmware(struct qlcnic_adapter *adapter) |
1846 | { | |
1847 | return adapter->nic_ops->start_firmware(adapter); | |
1848 | } | |
1849 | ||
1850 | static inline void qlcnic_read_crb(struct qlcnic_adapter *adapter, char *buf, | |
1851 | loff_t offset, size_t size) | |
1852 | { | |
1853 | adapter->ahw->hw_ops->read_crb(adapter, buf, offset, size); | |
1854 | } | |
1855 | ||
1856 | static inline void qlcnic_write_crb(struct qlcnic_adapter *adapter, char *buf, | |
1857 | loff_t offset, size_t size) | |
1858 | { | |
1859 | adapter->ahw->hw_ops->write_crb(adapter, buf, offset, size); | |
1860 | } | |
1861 | ||
7e2cf4fe SC |
1862 | static inline int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, |
1863 | ulong off, u32 data) | |
1864 | { | |
1865 | return adapter->ahw->hw_ops->write_reg(adapter, off, data); | |
1866 | } | |
1867 | ||
1868 | static inline int qlcnic_get_mac_address(struct qlcnic_adapter *adapter, | |
07a251c8 | 1869 | u8 *mac, u8 function) |
7e2cf4fe | 1870 | { |
07a251c8 | 1871 | return adapter->ahw->hw_ops->get_mac_address(adapter, mac, function); |
7e2cf4fe SC |
1872 | } |
1873 | ||
34e8c406 | 1874 | static inline int qlcnic_setup_intr(struct qlcnic_adapter *adapter) |
7e2cf4fe | 1875 | { |
34e8c406 | 1876 | return adapter->ahw->hw_ops->setup_intr(adapter); |
7e2cf4fe SC |
1877 | } |
1878 | ||
1879 | static inline int qlcnic_alloc_mbx_args(struct qlcnic_cmd_args *mbx, | |
1880 | struct qlcnic_adapter *adapter, u32 arg) | |
1881 | { | |
1882 | return adapter->ahw->hw_ops->alloc_mbx_args(mbx, adapter, arg); | |
1883 | } | |
1884 | ||
1885 | static inline int qlcnic_issue_cmd(struct qlcnic_adapter *adapter, | |
1886 | struct qlcnic_cmd_args *cmd) | |
1887 | { | |
f8468331 RB |
1888 | if (adapter->ahw->hw_ops->mbx_cmd) |
1889 | return adapter->ahw->hw_ops->mbx_cmd(adapter, cmd); | |
1890 | ||
1891 | return -EIO; | |
7e2cf4fe SC |
1892 | } |
1893 | ||
1894 | static inline void qlcnic_get_func_no(struct qlcnic_adapter *adapter) | |
1895 | { | |
1896 | adapter->ahw->hw_ops->get_func_no(adapter); | |
1897 | } | |
1898 | ||
1899 | static inline int qlcnic_api_lock(struct qlcnic_adapter *adapter) | |
1900 | { | |
1901 | return adapter->ahw->hw_ops->api_lock(adapter); | |
1902 | } | |
1903 | ||
1904 | static inline void qlcnic_api_unlock(struct qlcnic_adapter *adapter) | |
1905 | { | |
1906 | adapter->ahw->hw_ops->api_unlock(adapter); | |
1907 | } | |
1908 | ||
1909 | static inline void qlcnic_add_sysfs(struct qlcnic_adapter *adapter) | |
1910 | { | |
f8468331 RB |
1911 | if (adapter->ahw->hw_ops->add_sysfs) |
1912 | adapter->ahw->hw_ops->add_sysfs(adapter); | |
7e2cf4fe SC |
1913 | } |
1914 | ||
1915 | static inline void qlcnic_remove_sysfs(struct qlcnic_adapter *adapter) | |
1916 | { | |
f8468331 RB |
1917 | if (adapter->ahw->hw_ops->remove_sysfs) |
1918 | adapter->ahw->hw_ops->remove_sysfs(adapter); | |
7e2cf4fe SC |
1919 | } |
1920 | ||
1921 | static inline void | |
1922 | qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring) | |
1923 | { | |
1924 | sds_ring->adapter->ahw->hw_ops->process_lb_rcv_ring_diag(sds_ring); | |
1925 | } | |
1926 | ||
1927 | static inline int qlcnic_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter) | |
1928 | { | |
1929 | return adapter->ahw->hw_ops->create_rx_ctx(adapter); | |
1930 | } | |
1931 | ||
1932 | static inline int qlcnic_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter, | |
1933 | struct qlcnic_host_tx_ring *ptr, | |
1934 | int ring) | |
1935 | { | |
1936 | return adapter->ahw->hw_ops->create_tx_ctx(adapter, ptr, ring); | |
1937 | } | |
1938 | ||
7cb03b23 RB |
1939 | static inline void qlcnic_fw_cmd_del_rx_ctx(struct qlcnic_adapter *adapter) |
1940 | { | |
1941 | return adapter->ahw->hw_ops->del_rx_ctx(adapter); | |
1942 | } | |
1943 | ||
1944 | static inline void qlcnic_fw_cmd_del_tx_ctx(struct qlcnic_adapter *adapter, | |
1945 | struct qlcnic_host_tx_ring *ptr) | |
1946 | { | |
1947 | return adapter->ahw->hw_ops->del_tx_ctx(adapter, ptr); | |
1948 | } | |
1949 | ||
7e2cf4fe SC |
1950 | static inline int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, |
1951 | int enable) | |
1952 | { | |
1953 | return adapter->ahw->hw_ops->setup_link_event(adapter, enable); | |
1954 | } | |
1955 | ||
1956 | static inline int qlcnic_get_nic_info(struct qlcnic_adapter *adapter, | |
1957 | struct qlcnic_info *info, u8 id) | |
1958 | { | |
1959 | return adapter->ahw->hw_ops->get_nic_info(adapter, info, id); | |
1960 | } | |
1961 | ||
1962 | static inline int qlcnic_get_pci_info(struct qlcnic_adapter *adapter, | |
1963 | struct qlcnic_pci_info *info) | |
1964 | { | |
1965 | return adapter->ahw->hw_ops->get_pci_info(adapter, info); | |
1966 | } | |
1967 | ||
1968 | static inline int qlcnic_set_nic_info(struct qlcnic_adapter *adapter, | |
1969 | struct qlcnic_info *info) | |
1970 | { | |
1971 | return adapter->ahw->hw_ops->set_nic_info(adapter, info); | |
1972 | } | |
1973 | ||
1974 | static inline int qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, | |
f80bc8fe | 1975 | u8 *addr, u16 id, u8 cmd) |
7e2cf4fe SC |
1976 | { |
1977 | return adapter->ahw->hw_ops->change_macvlan(adapter, addr, id, cmd); | |
1978 | } | |
1979 | ||
1980 | static inline int qlcnic_napi_add(struct qlcnic_adapter *adapter, | |
1981 | struct net_device *netdev) | |
1982 | { | |
1983 | return adapter->nic_ops->napi_add(adapter, netdev); | |
1984 | } | |
1985 | ||
4be41e92 SC |
1986 | static inline void qlcnic_napi_del(struct qlcnic_adapter *adapter) |
1987 | { | |
1988 | adapter->nic_ops->napi_del(adapter); | |
1989 | } | |
1990 | ||
7e2cf4fe SC |
1991 | static inline void qlcnic_napi_enable(struct qlcnic_adapter *adapter) |
1992 | { | |
1993 | adapter->ahw->hw_ops->napi_enable(adapter); | |
1994 | } | |
1995 | ||
486a5bc7 RB |
1996 | static inline int __qlcnic_shutdown(struct pci_dev *pdev) |
1997 | { | |
1998 | struct qlcnic_adapter *adapter = pci_get_drvdata(pdev); | |
1999 | ||
2000 | return adapter->nic_ops->shutdown(pdev); | |
2001 | } | |
2002 | ||
2003 | static inline int __qlcnic_resume(struct qlcnic_adapter *adapter) | |
2004 | { | |
2005 | return adapter->nic_ops->resume(adapter); | |
2006 | } | |
2007 | ||
7e2cf4fe SC |
2008 | static inline void qlcnic_napi_disable(struct qlcnic_adapter *adapter) |
2009 | { | |
2010 | adapter->ahw->hw_ops->napi_disable(adapter); | |
2011 | } | |
2012 | ||
a514722a HM |
2013 | static inline int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter, |
2014 | struct ethtool_coalesce *ethcoal) | |
7e2cf4fe | 2015 | { |
a514722a | 2016 | return adapter->ahw->hw_ops->config_intr_coal(adapter, ethcoal); |
7e2cf4fe SC |
2017 | } |
2018 | ||
2019 | static inline int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable) | |
2020 | { | |
2021 | return adapter->ahw->hw_ops->config_rss(adapter, enable); | |
2022 | } | |
2023 | ||
2024 | static inline int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, | |
2025 | int enable) | |
2026 | { | |
2027 | return adapter->ahw->hw_ops->config_hw_lro(adapter, enable); | |
2028 | } | |
2029 | ||
2030 | static inline int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode) | |
2031 | { | |
2032 | return adapter->ahw->hw_ops->config_loopback(adapter, mode); | |
2033 | } | |
2034 | ||
2035 | static inline int qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode) | |
2036 | { | |
d09529e6 | 2037 | return adapter->ahw->hw_ops->clear_loopback(adapter, mode); |
7e2cf4fe SC |
2038 | } |
2039 | ||
2040 | static inline int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, | |
2041 | u32 mode) | |
2042 | { | |
2043 | return adapter->ahw->hw_ops->config_promisc_mode(adapter, mode); | |
2044 | } | |
2045 | ||
2046 | static inline void qlcnic_change_filter(struct qlcnic_adapter *adapter, | |
f80bc8fe | 2047 | u64 *addr, u16 id) |
7e2cf4fe SC |
2048 | { |
2049 | adapter->ahw->hw_ops->change_l2_filter(adapter, addr, id); | |
2050 | } | |
2051 | ||
2052 | static inline int qlcnic_get_board_info(struct qlcnic_adapter *adapter) | |
2053 | { | |
2054 | return adapter->ahw->hw_ops->get_board_info(adapter); | |
2055 | } | |
2056 | ||
91b7282b RB |
2057 | static inline void qlcnic_free_mac_list(struct qlcnic_adapter *adapter) |
2058 | { | |
2059 | return adapter->ahw->hw_ops->free_mac_list(adapter); | |
2060 | } | |
2061 | ||
52e493d0 JK |
2062 | static inline void qlcnic_set_mac_filter_count(struct qlcnic_adapter *adapter) |
2063 | { | |
e9a355a9 SC |
2064 | if (adapter->ahw->hw_ops->set_mac_filter_count) |
2065 | adapter->ahw->hw_ops->set_mac_filter_count(adapter); | |
52e493d0 JK |
2066 | } |
2067 | ||
a0431589 HM |
2068 | static inline void qlcnic_get_beacon_state(struct qlcnic_adapter *adapter) |
2069 | { | |
2070 | adapter->ahw->hw_ops->get_beacon_state(adapter); | |
2071 | } | |
2072 | ||
07a251c8 SS |
2073 | static inline void qlcnic_read_phys_port_id(struct qlcnic_adapter *adapter) |
2074 | { | |
2075 | if (adapter->ahw->hw_ops->read_phys_port_id) | |
2076 | adapter->ahw->hw_ops->read_phys_port_id(adapter); | |
2077 | } | |
2078 | ||
225837a0 SS |
2079 | static inline u32 qlcnic_get_saved_state(struct qlcnic_adapter *adapter, |
2080 | void *t_hdr, u32 index) | |
2081 | { | |
2082 | return adapter->ahw->hw_ops->get_saved_state(t_hdr, index); | |
2083 | } | |
2084 | ||
2085 | static inline void qlcnic_set_saved_state(struct qlcnic_adapter *adapter, | |
2086 | void *t_hdr, u32 index, u32 value) | |
2087 | { | |
2088 | adapter->ahw->hw_ops->set_saved_state(t_hdr, index, value); | |
2089 | } | |
2090 | ||
2091 | static inline void qlcnic_cache_tmpl_hdr_values(struct qlcnic_adapter *adapter, | |
2092 | struct qlcnic_fw_dump *fw_dump) | |
2093 | { | |
2094 | adapter->ahw->hw_ops->cache_tmpl_hdr_values(fw_dump); | |
2095 | } | |
2096 | ||
2097 | static inline u32 qlcnic_get_cap_size(struct qlcnic_adapter *adapter, | |
2098 | void *tmpl_hdr, int index) | |
2099 | { | |
2100 | return adapter->ahw->hw_ops->get_cap_size(tmpl_hdr, index); | |
2101 | } | |
2102 | ||
2103 | static inline void qlcnic_set_sys_info(struct qlcnic_adapter *adapter, | |
2104 | void *tmpl_hdr, int idx, u32 value) | |
2105 | { | |
2106 | adapter->ahw->hw_ops->set_sys_info(tmpl_hdr, idx, value); | |
2107 | } | |
2108 | ||
2109 | static inline void qlcnic_store_cap_mask(struct qlcnic_adapter *adapter, | |
2110 | void *tmpl_hdr, u32 mask) | |
2111 | { | |
2112 | adapter->ahw->hw_ops->store_cap_mask(tmpl_hdr, mask); | |
2113 | } | |
2114 | ||
7e2cf4fe SC |
2115 | static inline void qlcnic_dev_request_reset(struct qlcnic_adapter *adapter, |
2116 | u32 key) | |
2117 | { | |
f8468331 RB |
2118 | if (adapter->nic_ops->request_reset) |
2119 | adapter->nic_ops->request_reset(adapter, key); | |
7e2cf4fe SC |
2120 | } |
2121 | ||
2122 | static inline void qlcnic_cancel_idc_work(struct qlcnic_adapter *adapter) | |
2123 | { | |
f8468331 RB |
2124 | if (adapter->nic_ops->cancel_idc_work) |
2125 | adapter->nic_ops->cancel_idc_work(adapter); | |
7e2cf4fe SC |
2126 | } |
2127 | ||
2128 | static inline irqreturn_t | |
2129 | qlcnic_clear_legacy_intr(struct qlcnic_adapter *adapter) | |
2130 | { | |
2131 | return adapter->nic_ops->clear_legacy_intr(adapter); | |
2132 | } | |
2133 | ||
2134 | static inline int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, | |
2135 | u32 rate) | |
2136 | { | |
2137 | return adapter->nic_ops->config_led(adapter, state, rate); | |
2138 | } | |
2139 | ||
2140 | static inline void qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, | |
2141 | __be32 ip, int cmd) | |
2142 | { | |
2143 | adapter->nic_ops->config_ipaddr(adapter, ip, cmd); | |
2144 | } | |
2145 | ||
012ec812 HM |
2146 | static inline bool qlcnic_check_multi_tx(struct qlcnic_adapter *adapter) |
2147 | { | |
2148 | return test_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state); | |
2149 | } | |
2150 | ||
2cc5752e M |
2151 | static inline void |
2152 | qlcnic_82xx_enable_tx_intr(struct qlcnic_adapter *adapter, | |
2153 | struct qlcnic_host_tx_ring *tx_ring) | |
2154 | { | |
2155 | if (qlcnic_check_multi_tx(adapter) && | |
2156 | !adapter->ahw->diag_test) | |
2157 | writel(0x0, tx_ring->crb_intr_mask); | |
2158 | } | |
2159 | ||
2160 | static inline void | |
2161 | qlcnic_82xx_disable_tx_intr(struct qlcnic_adapter *adapter, | |
2162 | struct qlcnic_host_tx_ring *tx_ring) | |
2163 | { | |
2164 | if (qlcnic_check_multi_tx(adapter) && | |
2165 | !adapter->ahw->diag_test) | |
2166 | writel(1, tx_ring->crb_intr_mask); | |
2167 | } | |
2168 | ||
2169 | static inline void | |
2170 | qlcnic_83xx_enable_tx_intr(struct qlcnic_adapter *adapter, | |
2171 | struct qlcnic_host_tx_ring *tx_ring) | |
2172 | { | |
2173 | writel(0, tx_ring->crb_intr_mask); | |
2174 | } | |
2175 | ||
2176 | static inline void | |
2177 | qlcnic_83xx_disable_tx_intr(struct qlcnic_adapter *adapter, | |
2178 | struct qlcnic_host_tx_ring *tx_ring) | |
2179 | { | |
2180 | writel(1, tx_ring->crb_intr_mask); | |
2181 | } | |
2182 | ||
2183 | /* Enable MSI-x and INT-x interrupts */ | |
2184 | static inline void | |
2185 | qlcnic_83xx_enable_sds_intr(struct qlcnic_adapter *adapter, | |
2186 | struct qlcnic_host_sds_ring *sds_ring) | |
2187 | { | |
2188 | writel(0, sds_ring->crb_intr_mask); | |
2189 | } | |
2190 | ||
2191 | /* Disable MSI-x and INT-x interrupts */ | |
2192 | static inline void | |
2193 | qlcnic_83xx_disable_sds_intr(struct qlcnic_adapter *adapter, | |
2194 | struct qlcnic_host_sds_ring *sds_ring) | |
2195 | { | |
2196 | writel(1, sds_ring->crb_intr_mask); | |
2197 | } | |
2198 | ||
012ec812 HM |
2199 | static inline void qlcnic_disable_multi_tx(struct qlcnic_adapter *adapter) |
2200 | { | |
2201 | test_and_clear_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state); | |
34e8c406 | 2202 | adapter->drv_tx_rings = QLCNIC_SINGLE_RING; |
012ec812 HM |
2203 | } |
2204 | ||
2205 | /* When operating in a muti tx mode, driver needs to write 0x1 | |
2206 | * to src register, instead of 0x0 to disable receiving interrupt. | |
2207 | */ | |
2cc5752e M |
2208 | static inline void |
2209 | qlcnic_82xx_disable_sds_intr(struct qlcnic_adapter *adapter, | |
2210 | struct qlcnic_host_sds_ring *sds_ring) | |
c70001a9 | 2211 | { |
012ec812 | 2212 | if (qlcnic_check_multi_tx(adapter) && |
c2c5e3a0 | 2213 | !adapter->ahw->diag_test && |
012ec812 HM |
2214 | (adapter->flags & QLCNIC_MSIX_ENABLED)) |
2215 | writel(0x1, sds_ring->crb_intr_mask); | |
2216 | else | |
2217 | writel(0, sds_ring->crb_intr_mask); | |
c70001a9 SC |
2218 | } |
2219 | ||
2cc5752e M |
2220 | static inline void qlcnic_enable_sds_intr(struct qlcnic_adapter *adapter, |
2221 | struct qlcnic_host_sds_ring *sds_ring) | |
2222 | { | |
2223 | if (adapter->ahw->hw_ops->enable_sds_intr) | |
2224 | adapter->ahw->hw_ops->enable_sds_intr(adapter, sds_ring); | |
2225 | } | |
2226 | ||
2227 | static inline void | |
2228 | qlcnic_disable_sds_intr(struct qlcnic_adapter *adapter, | |
2229 | struct qlcnic_host_sds_ring *sds_ring) | |
2230 | { | |
2231 | if (adapter->ahw->hw_ops->disable_sds_intr) | |
2232 | adapter->ahw->hw_ops->disable_sds_intr(adapter, sds_ring); | |
2233 | } | |
2234 | ||
2235 | static inline void qlcnic_enable_tx_intr(struct qlcnic_adapter *adapter, | |
2236 | struct qlcnic_host_tx_ring *tx_ring) | |
2237 | { | |
2238 | if (adapter->ahw->hw_ops->enable_tx_intr) | |
2239 | adapter->ahw->hw_ops->enable_tx_intr(adapter, tx_ring); | |
2240 | } | |
2241 | ||
2242 | static inline void qlcnic_disable_tx_intr(struct qlcnic_adapter *adapter, | |
2243 | struct qlcnic_host_tx_ring *tx_ring) | |
2244 | { | |
2245 | if (adapter->ahw->hw_ops->disable_tx_intr) | |
2246 | adapter->ahw->hw_ops->disable_tx_intr(adapter, tx_ring); | |
2247 | } | |
2248 | ||
012ec812 HM |
2249 | /* When operating in a muti tx mode, driver needs to write 0x0 |
2250 | * to src register, instead of 0x1 to enable receiving interrupts. | |
2251 | */ | |
2cc5752e M |
2252 | static inline void |
2253 | qlcnic_82xx_enable_sds_intr(struct qlcnic_adapter *adapter, | |
2254 | struct qlcnic_host_sds_ring *sds_ring) | |
c70001a9 | 2255 | { |
012ec812 | 2256 | if (qlcnic_check_multi_tx(adapter) && |
c2c5e3a0 | 2257 | !adapter->ahw->diag_test && |
012ec812 HM |
2258 | (adapter->flags & QLCNIC_MSIX_ENABLED)) |
2259 | writel(0, sds_ring->crb_intr_mask); | |
2260 | else | |
2261 | writel(0x1, sds_ring->crb_intr_mask); | |
c70001a9 SC |
2262 | |
2263 | if (!QLCNIC_IS_MSI_FAMILY(adapter)) | |
2264 | writel(0xfbff, adapter->tgt_mask_reg); | |
2265 | } | |
2266 | ||
4690a7e4 SC |
2267 | static inline int qlcnic_get_diag_lock(struct qlcnic_adapter *adapter) |
2268 | { | |
2269 | return test_and_set_bit(__QLCNIC_DIAG_MODE, &adapter->state); | |
2270 | } | |
2271 | ||
2272 | static inline void qlcnic_release_diag_lock(struct qlcnic_adapter *adapter) | |
2273 | { | |
2274 | clear_bit(__QLCNIC_DIAG_MODE, &adapter->state); | |
2275 | } | |
2276 | ||
099907fa SC |
2277 | static inline int qlcnic_check_diag_status(struct qlcnic_adapter *adapter) |
2278 | { | |
2279 | return test_bit(__QLCNIC_DIAG_MODE, &adapter->state); | |
2280 | } | |
2281 | ||
d1a1105e | 2282 | extern const struct ethtool_ops qlcnic_sriov_vf_ethtool_ops; |
af19b491 | 2283 | extern const struct ethtool_ops qlcnic_ethtool_ops; |
b43e5ee7 | 2284 | extern const struct ethtool_ops qlcnic_ethtool_failed_ops; |
af19b491 | 2285 | |
65b5b420 | 2286 | #define QLCDB(adapter, lvl, _fmt, _args...) do { \ |
79788450 | 2287 | if (NETIF_MSG_##lvl & adapter->ahw->msg_enable) \ |
65b5b420 AKS |
2288 | printk(KERN_INFO "%s: %s: " _fmt, \ |
2289 | dev_name(&adapter->pdev->dev), \ | |
2290 | __func__, ##_args); \ | |
2291 | } while (0) | |
2292 | ||
15ca140f MC |
2293 | #define PCI_DEVICE_ID_QLOGIC_QLE824X 0x8020 |
2294 | #define PCI_DEVICE_ID_QLOGIC_QLE834X 0x8030 | |
f8468331 | 2295 | #define PCI_DEVICE_ID_QLOGIC_VF_QLE834X 0x8430 |
da286a6f SS |
2296 | #define PCI_DEVICE_ID_QLOGIC_QLE8830 0x8830 |
2297 | #define PCI_DEVICE_ID_QLOGIC_VF_QLE8C30 0x8C30 | |
15ca140f MC |
2298 | #define PCI_DEVICE_ID_QLOGIC_QLE844X 0x8040 |
2299 | #define PCI_DEVICE_ID_QLOGIC_VF_QLE844X 0x8440 | |
f8468331 | 2300 | |
97ee45eb SC |
2301 | static inline bool qlcnic_82xx_check(struct qlcnic_adapter *adapter) |
2302 | { | |
2303 | unsigned short device = adapter->pdev->device; | |
2304 | return (device == PCI_DEVICE_ID_QLOGIC_QLE824X) ? true : false; | |
2305 | } | |
2306 | ||
991ca269 MC |
2307 | static inline bool qlcnic_84xx_check(struct qlcnic_adapter *adapter) |
2308 | { | |
2309 | unsigned short device = adapter->pdev->device; | |
2310 | ||
2311 | return ((device == PCI_DEVICE_ID_QLOGIC_QLE844X) || | |
2312 | (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X)) ? true : false; | |
2313 | } | |
2314 | ||
7f966452 SC |
2315 | static inline bool qlcnic_83xx_check(struct qlcnic_adapter *adapter) |
2316 | { | |
2317 | unsigned short device = adapter->pdev->device; | |
f8468331 RB |
2318 | bool status; |
2319 | ||
2320 | status = ((device == PCI_DEVICE_ID_QLOGIC_QLE834X) || | |
40e2b8ed | 2321 | (device == PCI_DEVICE_ID_QLOGIC_QLE8830) || |
15ca140f MC |
2322 | (device == PCI_DEVICE_ID_QLOGIC_QLE844X) || |
2323 | (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X) || | |
da286a6f SS |
2324 | (device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) || |
2325 | (device == PCI_DEVICE_ID_QLOGIC_VF_QLE8C30)) ? true : false; | |
f8468331 RB |
2326 | |
2327 | return status; | |
7f966452 SC |
2328 | } |
2329 | ||
02feda17 RB |
2330 | static inline bool qlcnic_sriov_pf_check(struct qlcnic_adapter *adapter) |
2331 | { | |
2332 | return (adapter->ahw->op_mode == QLCNIC_SRIOV_PF_FUNC) ? true : false; | |
2333 | } | |
7f966452 | 2334 | |
f8468331 RB |
2335 | static inline bool qlcnic_sriov_vf_check(struct qlcnic_adapter *adapter) |
2336 | { | |
2337 | unsigned short device = adapter->pdev->device; | |
15ca140f MC |
2338 | bool status; |
2339 | ||
2340 | status = ((device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) || | |
da286a6f SS |
2341 | (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X) || |
2342 | (device == PCI_DEVICE_ID_QLOGIC_VF_QLE8C30)) ? true : false; | |
f8468331 | 2343 | |
15ca140f | 2344 | return status; |
f8468331 | 2345 | } |
154d0c81 MC |
2346 | |
2347 | static inline bool qlcnic_83xx_pf_check(struct qlcnic_adapter *adapter) | |
2348 | { | |
2349 | unsigned short device = adapter->pdev->device; | |
2350 | ||
2351 | return (device == PCI_DEVICE_ID_QLOGIC_QLE834X) ? true : false; | |
2352 | } | |
2353 | ||
2354 | static inline bool qlcnic_83xx_vf_check(struct qlcnic_adapter *adapter) | |
2355 | { | |
2356 | unsigned short device = adapter->pdev->device; | |
2357 | ||
da286a6f SS |
2358 | return ((device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) || |
2359 | (device == PCI_DEVICE_ID_QLOGIC_VF_QLE8C30)) ? true : false; | |
154d0c81 | 2360 | } |
2f514c52 | 2361 | |
d747c333 RB |
2362 | static inline bool qlcnic_sriov_check(struct qlcnic_adapter *adapter) |
2363 | { | |
2364 | bool status; | |
2365 | ||
2366 | status = (qlcnic_sriov_pf_check(adapter) || | |
2367 | qlcnic_sriov_vf_check(adapter)) ? true : false; | |
2368 | ||
2369 | return status; | |
2370 | } | |
2371 | ||
2f514c52 JK |
2372 | static inline u32 qlcnic_get_vnic_func_count(struct qlcnic_adapter *adapter) |
2373 | { | |
2374 | if (qlcnic_84xx_check(adapter)) | |
2375 | return QLC_84XX_VNIC_COUNT; | |
2376 | else | |
2377 | return QLC_DEFAULT_VNIC_COUNT; | |
2378 | } | |
1f0f467b | 2379 | |
26acc712 JK |
2380 | static inline void qlcnic_swap32_buffer(u32 *buffer, int count) |
2381 | { | |
2382 | #if defined(__BIG_ENDIAN) | |
2383 | u32 *tmp = buffer; | |
2384 | int i; | |
2385 | ||
2386 | for (i = 0; i < count; i++) { | |
2387 | *tmp = swab32(*tmp); | |
2388 | tmp++; | |
2389 | } | |
2390 | #endif | |
2391 | } | |
2392 | ||
1f0f467b HP |
2393 | #ifdef CONFIG_QLCNIC_HWMON |
2394 | void qlcnic_register_hwmon_dev(struct qlcnic_adapter *); | |
2395 | void qlcnic_unregister_hwmon_dev(struct qlcnic_adapter *); | |
2396 | #else | |
2397 | static inline void qlcnic_register_hwmon_dev(struct qlcnic_adapter *adapter) | |
2398 | { | |
2399 | return; | |
2400 | } | |
2401 | static inline void qlcnic_unregister_hwmon_dev(struct qlcnic_adapter *adapter) | |
2402 | { | |
2403 | return; | |
2404 | } | |
2405 | #endif | |
af19b491 | 2406 | #endif /* __QLCNIC_H_ */ |