Commit | Line | Data |
---|---|---|
af19b491 | 1 | /* |
40839129 | 2 | * QLogic qlcnic NIC Driver |
577ae39d | 3 | * Copyright (c) 2009-2013 QLogic Corporation |
af19b491 | 4 | * |
40839129 | 5 | * See LICENSE.qlcnic for copyright and licensing details. |
af19b491 AKS |
6 | */ |
7 | ||
8 | #ifndef _QLCNIC_H_ | |
9 | #define _QLCNIC_H_ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/types.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/netdevice.h> | |
17 | #include <linux/etherdevice.h> | |
18 | #include <linux/ip.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/tcp.h> | |
21 | #include <linux/skbuff.h> | |
22 | #include <linux/firmware.h> | |
af19b491 AKS |
23 | #include <linux/ethtool.h> |
24 | #include <linux/mii.h> | |
25 | #include <linux/timer.h> | |
26 | ||
27 | #include <linux/vmalloc.h> | |
28 | ||
29 | #include <linux/io.h> | |
30 | #include <asm/byteorder.h> | |
b9796a14 AC |
31 | #include <linux/bitops.h> |
32 | #include <linux/if_vlan.h> | |
af19b491 AKS |
33 | |
34 | #include "qlcnic_hdr.h" | |
7f966452 SC |
35 | #include "qlcnic_hw.h" |
36 | #include "qlcnic_83xx_hw.h" | |
14d385b9 | 37 | #include "qlcnic_dcb.h" |
af19b491 AKS |
38 | |
39 | #define _QLCNIC_LINUX_MAJOR 5 | |
4cffa13d | 40 | #define _QLCNIC_LINUX_MINOR 3 |
693dcd2f SS |
41 | #define _QLCNIC_LINUX_SUBVERSION 50 |
42 | #define QLCNIC_LINUX_VERSIONID "5.3.50" | |
96f8118c | 43 | #define QLCNIC_DRV_IDC_VER 0x01 |
d4066833 SC |
44 | #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\ |
45 | (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION)) | |
af19b491 AKS |
46 | |
47 | #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c)) | |
48 | #define _major(v) (((v) >> 24) & 0xff) | |
49 | #define _minor(v) (((v) >> 16) & 0xff) | |
50 | #define _build(v) ((v) & 0xffff) | |
51 | ||
52 | /* version in image has weird encoding: | |
53 | * 7:0 - major | |
54 | * 15:8 - minor | |
55 | * 31:16 - build (little endian) | |
56 | */ | |
57 | #define QLCNIC_DECODE_VERSION(v) \ | |
58 | QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16)) | |
59 | ||
8f891387 | 60 | #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2) |
af19b491 AKS |
61 | #define QLCNIC_NUM_FLASH_SECTORS (64) |
62 | #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024) | |
63 | #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \ | |
64 | * QLCNIC_FLASH_SECTOR_SIZE) | |
65 | ||
66 | #define RCV_DESC_RINGSIZE(rds_ring) \ | |
67 | (sizeof(struct rcv_desc) * (rds_ring)->num_desc) | |
68 | #define RCV_BUFF_RINGSIZE(rds_ring) \ | |
69 | (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc) | |
70 | #define STATUS_DESC_RINGSIZE(sds_ring) \ | |
71 | (sizeof(struct status_desc) * (sds_ring)->num_desc) | |
72 | #define TX_BUFF_RINGSIZE(tx_ring) \ | |
73 | (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc) | |
74 | #define TX_DESC_RINGSIZE(tx_ring) \ | |
75 | (sizeof(struct cmd_desc_type0) * tx_ring->num_desc) | |
76 | ||
77 | #define QLCNIC_P3P_A0 0x50 | |
a2050c7e | 78 | #define QLCNIC_P3P_C0 0x58 |
af19b491 AKS |
79 | |
80 | #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0) | |
81 | ||
82 | #define FIRST_PAGE_GROUP_START 0 | |
83 | #define FIRST_PAGE_GROUP_END 0x100000 | |
84 | ||
ff1b1bf8 SV |
85 | #define P3P_MAX_MTU (9600) |
86 | #define P3P_MIN_MTU (68) | |
af19b491 AKS |
87 | #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */ |
88 | ||
ff1b1bf8 SV |
89 | #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN) |
90 | #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU) | |
af19b491 AKS |
91 | #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048 |
92 | #define QLCNIC_LRO_BUFFER_EXTRA 2048 | |
93 | ||
af19b491 | 94 | /* Tx defines */ |
91a403ca | 95 | #define QLCNIC_MAX_FRAGS_PER_TX 14 |
ef71ff83 RB |
96 | #define MAX_TSO_HEADER_DESC 2 |
97 | #define MGMT_CMD_DESC_RESV 4 | |
98 | #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \ | |
99 | + MGMT_CMD_DESC_RESV) | |
af19b491 | 100 | #define QLCNIC_MAX_TX_TIMEOUTS 2 |
012ec812 HM |
101 | #define QLCNIC_MAX_TX_RINGS 8 |
102 | #define QLCNIC_MAX_SDS_RINGS 8 | |
103 | ||
af19b491 AKS |
104 | /* |
105 | * Following are the states of the Phantom. Phantom will set them and | |
106 | * Host will read to check if the fields are correct. | |
107 | */ | |
108 | #define PHAN_INITIALIZE_FAILED 0xffff | |
109 | #define PHAN_INITIALIZE_COMPLETE 0xff01 | |
110 | ||
111 | /* Host writes the following to notify that it has done the init-handshake */ | |
112 | #define PHAN_INITIALIZE_ACK 0xf00f | |
113 | #define PHAN_PEG_RCV_INITIALIZED 0xff01 | |
114 | ||
115 | #define NUM_RCV_DESC_RINGS 3 | |
af19b491 AKS |
116 | |
117 | #define RCV_RING_NORMAL 0 | |
118 | #define RCV_RING_JUMBO 1 | |
af19b491 AKS |
119 | |
120 | #define MIN_CMD_DESCRIPTORS 64 | |
121 | #define MIN_RCV_DESCRIPTORS 64 | |
122 | #define MIN_JUMBO_DESCRIPTORS 32 | |
123 | ||
124 | #define MAX_CMD_DESCRIPTORS 1024 | |
125 | #define MAX_RCV_DESCRIPTORS_1G 4096 | |
126 | #define MAX_RCV_DESCRIPTORS_10G 8192 | |
90d19005 | 127 | #define MAX_RCV_DESCRIPTORS_VF 2048 |
af19b491 AKS |
128 | #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512 |
129 | #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024 | |
af19b491 AKS |
130 | |
131 | #define DEFAULT_RCV_DESCRIPTORS_1G 2048 | |
132 | #define DEFAULT_RCV_DESCRIPTORS_10G 4096 | |
90d19005 | 133 | #define DEFAULT_RCV_DESCRIPTORS_VF 1024 |
251b036a | 134 | #define MAX_RDS_RINGS 2 |
af19b491 AKS |
135 | |
136 | #define get_next_index(index, length) \ | |
137 | (((index) + 1) & ((length) - 1)) | |
138 | ||
af19b491 AKS |
139 | /* |
140 | * Following data structures describe the descriptors that will be used. | |
141 | * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when | |
142 | * we are doing LSO (above the 1500 size packet) only. | |
143 | */ | |
af19b491 AKS |
144 | struct cmd_desc_type0 { |
145 | u8 tcp_hdr_offset; /* For LSO only */ | |
146 | u8 ip_hdr_offset; /* For LSO only */ | |
147 | __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */ | |
148 | __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */ | |
149 | ||
150 | __le64 addr_buffer2; | |
151 | ||
152 | __le16 reference_handle; | |
153 | __le16 mss; | |
154 | u8 port_ctxid; /* 7:4 ctxid 3:0 port */ | |
155 | u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ | |
156 | __le16 conn_id; /* IPSec offoad only */ | |
157 | ||
158 | __le64 addr_buffer3; | |
159 | __le64 addr_buffer1; | |
160 | ||
161 | __le16 buffer_length[4]; | |
162 | ||
163 | __le64 addr_buffer4; | |
164 | ||
2e9d722d | 165 | u8 eth_addr[ETH_ALEN]; |
af19b491 AKS |
166 | __le16 vlan_TCI; |
167 | ||
168 | } __attribute__ ((aligned(64))); | |
169 | ||
170 | /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ | |
171 | struct rcv_desc { | |
172 | __le16 reference_handle; | |
173 | __le16 reserved; | |
174 | __le32 buffer_length; /* allocated buffer length (usually 2K) */ | |
175 | __le64 addr_buffer; | |
b1fc6d3c | 176 | } __packed; |
af19b491 | 177 | |
af19b491 AKS |
178 | struct status_desc { |
179 | __le64 status_desc_data[2]; | |
180 | } __attribute__ ((aligned(16))); | |
181 | ||
182 | /* UNIFIED ROMIMAGE */ | |
183 | #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000 | |
184 | #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0 | |
185 | #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6 | |
186 | #define QLCNIC_UNI_DIR_SECT_FW 0x7 | |
187 | ||
188 | /*Offsets */ | |
189 | #define QLCNIC_UNI_CHIP_REV_OFF 10 | |
190 | #define QLCNIC_UNI_FLAGS_OFF 11 | |
191 | #define QLCNIC_UNI_BIOS_VERSION_OFF 12 | |
192 | #define QLCNIC_UNI_BOOTLD_IDX_OFF 27 | |
193 | #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29 | |
194 | ||
195 | struct uni_table_desc{ | |
63507592 SS |
196 | __le32 findex; |
197 | __le32 num_entries; | |
198 | __le32 entry_size; | |
199 | __le32 reserved[5]; | |
af19b491 AKS |
200 | }; |
201 | ||
202 | struct uni_data_desc{ | |
63507592 SS |
203 | __le32 findex; |
204 | __le32 size; | |
205 | __le32 reserved[5]; | |
af19b491 AKS |
206 | }; |
207 | ||
0e5f20b6 | 208 | /* Flash Defines and Structures */ |
209 | #define QLCNIC_FLT_LOCATION 0x3F1000 | |
d865ebb4 | 210 | #define QLCNIC_FDT_LOCATION 0x3F0000 |
a2050c7e SV |
211 | #define QLCNIC_B0_FW_IMAGE_REGION 0x74 |
212 | #define QLCNIC_C0_FW_IMAGE_REGION 0x97 | |
f8d54811 | 213 | #define QLCNIC_BOOTLD_REGION 0X72 |
0e5f20b6 | 214 | struct qlcnic_flt_header { |
215 | u16 version; | |
216 | u16 len; | |
217 | u16 checksum; | |
218 | u16 reserved; | |
219 | }; | |
220 | ||
221 | struct qlcnic_flt_entry { | |
222 | u8 region; | |
223 | u8 reserved0; | |
224 | u8 attrib; | |
225 | u8 reserved1; | |
226 | u32 size; | |
227 | u32 start_addr; | |
f8d54811 | 228 | u32 end_addr; |
0e5f20b6 | 229 | }; |
230 | ||
d865ebb4 SC |
231 | /* Flash Descriptor Table */ |
232 | struct qlcnic_fdt { | |
233 | u32 valid; | |
234 | u16 ver; | |
235 | u16 len; | |
236 | u16 cksum; | |
237 | u16 unused; | |
238 | u8 model[16]; | |
239 | u16 mfg_id; | |
240 | u16 id; | |
241 | u8 flag; | |
242 | u8 erase_cmd; | |
243 | u8 alt_erase_cmd; | |
244 | u8 write_enable_cmd; | |
245 | u8 write_enable_bits; | |
246 | u8 write_statusreg_cmd; | |
247 | u8 unprotected_sec_cmd; | |
248 | u8 read_manuf_cmd; | |
249 | u32 block_size; | |
250 | u32 alt_block_size; | |
251 | u32 flash_size; | |
252 | u32 write_enable_data; | |
253 | u8 readid_addr_len; | |
254 | u8 write_disable_bits; | |
255 | u8 read_dev_id_len; | |
256 | u8 chip_erase_cmd; | |
257 | u16 read_timeo; | |
258 | u8 protected_sec_cmd; | |
259 | u8 resvd[65]; | |
260 | }; | |
af19b491 AKS |
261 | /* Magic number to let user know flash is programmed */ |
262 | #define QLCNIC_BDINFO_MAGIC 0x12345678 | |
263 | ||
ff1b1bf8 SV |
264 | #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021 |
265 | #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022 | |
266 | #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023 | |
267 | #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024 | |
268 | #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025 | |
269 | #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026 | |
270 | #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027 | |
271 | #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028 | |
272 | #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029 | |
273 | #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a | |
274 | #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b | |
275 | #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031 | |
276 | #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032 | |
277 | #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080 | |
af19b491 | 278 | |
2e9d722d AC |
279 | #define QLCNIC_MSIX_TABLE_OFFSET 0x44 |
280 | ||
af19b491 AKS |
281 | /* Flash memory map */ |
282 | #define QLCNIC_BRDCFG_START 0x4000 /* board config */ | |
283 | #define QLCNIC_BOOTLD_START 0x10000 /* bootld */ | |
284 | #define QLCNIC_IMAGE_START 0x43000 /* compressed image */ | |
285 | #define QLCNIC_USER_START 0x3E8000 /* Firmare info */ | |
286 | ||
287 | #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408) | |
288 | #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c) | |
289 | #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c) | |
290 | #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c) | |
291 | ||
292 | #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8) | |
293 | #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128) | |
294 | ||
295 | #define QLCNIC_FW_MIN_SIZE (0x3fffff) | |
296 | #define QLCNIC_UNIFIED_ROMIMAGE 0 | |
297 | #define QLCNIC_FLASH_ROMIMAGE 1 | |
298 | #define QLCNIC_UNKNOWN_ROMIMAGE 0xff | |
299 | ||
300 | #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin" | |
301 | #define QLCNIC_FLASH_ROMIMAGE_NAME "flash" | |
302 | ||
303 | extern char qlcnic_driver_name[]; | |
304 | ||
629263ac SC |
305 | extern int qlcnic_use_msi; |
306 | extern int qlcnic_use_msi_x; | |
307 | extern int qlcnic_auto_fw_reset; | |
308 | extern int qlcnic_load_fw_file; | |
629263ac | 309 | |
af19b491 AKS |
310 | /* Number of status descriptors to handle per interrupt */ |
311 | #define MAX_STATUS_HANDLE (64) | |
312 | ||
313 | /* | |
314 | * qlcnic_skb_frag{} is to contain mapping info for each SG list. This | |
315 | * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}. | |
316 | */ | |
317 | struct qlcnic_skb_frag { | |
318 | u64 dma; | |
319 | u64 length; | |
320 | }; | |
321 | ||
af19b491 AKS |
322 | /* Following defines are for the state of the buffers */ |
323 | #define QLCNIC_BUFFER_FREE 0 | |
324 | #define QLCNIC_BUFFER_BUSY 1 | |
325 | ||
326 | /* | |
327 | * There will be one qlcnic_buffer per skb packet. These will be | |
328 | * used to save the dma info for pci_unmap_page() | |
329 | */ | |
330 | struct qlcnic_cmd_buffer { | |
331 | struct sk_buff *skb; | |
ef71ff83 | 332 | struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1]; |
af19b491 AKS |
333 | u32 frag_count; |
334 | }; | |
335 | ||
336 | /* In rx_buffer, we do not need multiple fragments as is a single buffer */ | |
337 | struct qlcnic_rx_buffer { | |
b1fc6d3c | 338 | u16 ref_handle; |
af19b491 | 339 | struct sk_buff *skb; |
b1fc6d3c | 340 | struct list_head list; |
af19b491 | 341 | u64 dma; |
af19b491 AKS |
342 | }; |
343 | ||
344 | /* Board types */ | |
345 | #define QLCNIC_GBE 0x01 | |
346 | #define QLCNIC_XGBE 0x02 | |
347 | ||
8816d009 AC |
348 | /* |
349 | * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is | |
350 | * adjusted based on configured MTU. | |
351 | */ | |
be273dc1 HM |
352 | #define QLCNIC_INTR_COAL_TYPE_RX 1 |
353 | #define QLCNIC_INTR_COAL_TYPE_TX 2 | |
354 | ||
355 | #define QLCNIC_DEF_INTR_COALESCE_RX_TIME_US 3 | |
356 | #define QLCNIC_DEF_INTR_COALESCE_RX_PACKETS 256 | |
357 | ||
358 | #define QLCNIC_DEF_INTR_COALESCE_TX_TIME_US 64 | |
359 | #define QLCNIC_DEF_INTR_COALESCE_TX_PACKETS 64 | |
8816d009 AC |
360 | |
361 | #define QLCNIC_INTR_DEFAULT 0x04 | |
362 | #define QLCNIC_CONFIG_INTR_COALESCE 3 | |
7e38d04b | 363 | #define QLCNIC_DEV_INFO_SIZE 1 |
8816d009 AC |
364 | |
365 | struct qlcnic_nic_intr_coalesce { | |
366 | u8 type; | |
367 | u8 sts_ring_mask; | |
368 | u16 rx_packets; | |
369 | u16 rx_time_us; | |
be273dc1 HM |
370 | u16 tx_packets; |
371 | u16 tx_time_us; | |
8816d009 AC |
372 | u16 flag; |
373 | u32 timer_out; | |
374 | }; | |
375 | ||
18f2f616 | 376 | struct qlcnic_dump_template_hdr { |
63507592 SS |
377 | u32 type; |
378 | u32 offset; | |
379 | u32 size; | |
380 | u32 cap_mask; | |
381 | u32 num_entries; | |
382 | u32 version; | |
383 | u32 timestamp; | |
384 | u32 checksum; | |
385 | u32 drv_cap_mask; | |
386 | u32 sys_info[3]; | |
387 | u32 saved_state[16]; | |
388 | u32 cap_sizes[8]; | |
4e60ac46 | 389 | u32 ocm_wnd_reg[16]; |
63507592 | 390 | u32 rsvd[0]; |
18f2f616 AC |
391 | }; |
392 | ||
393 | struct qlcnic_fw_dump { | |
394 | u8 clr; /* flag to indicate if dump is cleared */ | |
890b6e02 | 395 | bool enable; /* enable/disable dump */ |
18f2f616 AC |
396 | u32 size; /* total size of the dump */ |
397 | void *data; /* dump data area */ | |
398 | struct qlcnic_dump_template_hdr *tmpl_hdr; | |
9baf1aa9 SS |
399 | dma_addr_t phys_addr; |
400 | void *dma_buffer; | |
401 | bool use_pex_dma; | |
18f2f616 AC |
402 | }; |
403 | ||
af19b491 AKS |
404 | /* |
405 | * One hardware_context{} per adapter | |
406 | * contains interrupt info as well shared hardware info. | |
407 | */ | |
408 | struct qlcnic_hardware_context { | |
409 | void __iomem *pci_base0; | |
410 | void __iomem *ocm_win_crb; | |
411 | ||
412 | unsigned long pci_len0; | |
413 | ||
af19b491 AKS |
414 | rwlock_t crb_lock; |
415 | struct mutex mem_lock; | |
416 | ||
af19b491 AKS |
417 | u8 revision_id; |
418 | u8 pci_func; | |
419 | u8 linkup; | |
22c8c934 | 420 | u8 loopback_state; |
79788450 SC |
421 | u8 beacon_state; |
422 | u8 has_link_events; | |
423 | u8 fw_type; | |
424 | u8 physical_port; | |
425 | u8 reset_context; | |
426 | u8 msix_supported; | |
427 | u8 max_mac_filters; | |
428 | u8 mc_enabled; | |
429 | u8 max_mc_count; | |
430 | u8 diag_test; | |
431 | u8 num_msix; | |
432 | u8 nic_mode; | |
433 | char diag_cnt; | |
434 | ||
52e493d0 | 435 | u16 max_uc_count; |
af19b491 AKS |
436 | u16 port_type; |
437 | u16 board_type; | |
b938662d | 438 | u16 supported_type; |
8816d009 | 439 | |
79788450 SC |
440 | u16 link_speed; |
441 | u16 link_duplex; | |
442 | u16 link_autoneg; | |
443 | u16 module_type; | |
444 | ||
445 | u16 op_mode; | |
446 | u16 switch_mode; | |
447 | u16 max_tx_ques; | |
448 | u16 max_rx_ques; | |
449 | u16 max_mtu; | |
450 | u32 msg_enable; | |
451 | u16 act_pci_func; | |
ee9e8b6c | 452 | u16 max_pci_func; |
728a98b8 | 453 | |
79788450 | 454 | u32 capabilities; |
db131786 | 455 | u32 extra_capability[3]; |
79788450 SC |
456 | u32 temp; |
457 | u32 int_vec_bit; | |
458 | u32 fw_hal_version; | |
7f966452 | 459 | u32 port_config; |
79788450 | 460 | struct qlcnic_hardware_ops *hw_ops; |
8816d009 | 461 | struct qlcnic_nic_intr_coalesce coal; |
18f2f616 | 462 | struct qlcnic_fw_dump fw_dump; |
d865ebb4 | 463 | struct qlcnic_fdt fdt; |
81d0aeb0 | 464 | struct qlc_83xx_reset reset; |
629263ac | 465 | struct qlc_83xx_idc idc; |
7000078a | 466 | struct qlc_83xx_fw_info *fw_info; |
7f966452 | 467 | struct qlcnic_intrpt_config *intr_tbl; |
02feda17 | 468 | struct qlcnic_sriov *sriov; |
7e2cf4fe | 469 | u32 *reg_tbl; |
7f966452 SC |
470 | u32 *ext_reg_tbl; |
471 | u32 mbox_aen[QLC_83XX_MBX_AEN_CNT]; | |
472 | u32 mbox_reg[4]; | |
e5c4e6c6 | 473 | struct qlcnic_mailbox *mailbox; |
77bead46 | 474 | u8 extend_lb_time; |
07a251c8 | 475 | u8 phys_port_id[ETH_ALEN]; |
af19b491 AKS |
476 | }; |
477 | ||
478 | struct qlcnic_adapter_stats { | |
479 | u64 xmitcalled; | |
480 | u64 xmitfinished; | |
481 | u64 rxdropped; | |
482 | u64 txdropped; | |
483 | u64 csummed; | |
484 | u64 rx_pkts; | |
485 | u64 lro_pkts; | |
486 | u64 rxbytes; | |
487 | u64 txbytes; | |
8bfe8b91 SC |
488 | u64 lrobytes; |
489 | u64 lso_frames; | |
490 | u64 xmit_on; | |
491 | u64 xmit_off; | |
492 | u64 skb_alloc_failure; | |
8ae6df97 AKS |
493 | u64 null_rxbuf; |
494 | u64 rx_dma_map_error; | |
495 | u64 tx_dma_map_error; | |
7f966452 | 496 | u64 spurious_intr; |
4be41e92 | 497 | u64 mac_filter_limit_overrun; |
af19b491 AKS |
498 | }; |
499 | ||
500 | /* | |
501 | * Rcv Descriptor Context. One such per Rcv Descriptor. There may | |
502 | * be one Rcv Descriptor for normal packets, one for jumbo and may be others. | |
503 | */ | |
504 | struct qlcnic_host_rds_ring { | |
036d61f0 AC |
505 | void __iomem *crb_rcv_producer; |
506 | struct rcv_desc *desc_head; | |
507 | struct qlcnic_rx_buffer *rx_buf_arr; | |
af19b491 | 508 | u32 num_desc; |
036d61f0 | 509 | u32 producer; |
af19b491 AKS |
510 | u32 dma_size; |
511 | u32 skb_size; | |
512 | u32 flags; | |
af19b491 AKS |
513 | struct list_head free_list; |
514 | spinlock_t lock; | |
515 | dma_addr_t phys_addr; | |
036d61f0 | 516 | } ____cacheline_internodealigned_in_smp; |
af19b491 AKS |
517 | |
518 | struct qlcnic_host_sds_ring { | |
519 | u32 consumer; | |
520 | u32 num_desc; | |
521 | void __iomem *crb_sts_consumer; | |
af19b491 | 522 | |
012ec812 | 523 | struct qlcnic_host_tx_ring *tx_ring; |
af19b491 AKS |
524 | struct status_desc *desc_head; |
525 | struct qlcnic_adapter *adapter; | |
526 | struct napi_struct napi; | |
527 | struct list_head free_list[NUM_RCV_DESC_RINGS]; | |
528 | ||
036d61f0 | 529 | void __iomem *crb_intr_mask; |
af19b491 AKS |
530 | int irq; |
531 | ||
532 | dma_addr_t phys_addr; | |
ddb2e174 | 533 | char name[IFNAMSIZ + 12]; |
036d61f0 | 534 | } ____cacheline_internodealigned_in_smp; |
af19b491 AKS |
535 | |
536 | struct qlcnic_host_tx_ring { | |
4be41e92 | 537 | int irq; |
7f966452 | 538 | void __iomem *crb_intr_mask; |
ddb2e174 | 539 | char name[IFNAMSIZ + 12]; |
79788450 | 540 | u16 ctx_id; |
012ec812 HM |
541 | |
542 | u32 state; | |
af19b491 | 543 | u32 producer; |
af19b491 | 544 | u32 sw_consumer; |
af19b491 | 545 | u32 num_desc; |
012ec812 HM |
546 | |
547 | u64 xmit_on; | |
548 | u64 xmit_off; | |
549 | u64 xmit_called; | |
550 | u64 xmit_finished; | |
551 | ||
036d61f0 | 552 | void __iomem *crb_cmd_producer; |
af19b491 | 553 | struct cmd_desc_type0 *desc_head; |
4be41e92 SC |
554 | struct qlcnic_adapter *adapter; |
555 | struct napi_struct napi; | |
036d61f0 AC |
556 | struct qlcnic_cmd_buffer *cmd_buf_arr; |
557 | __le32 *hw_consumer; | |
558 | ||
af19b491 AKS |
559 | dma_addr_t phys_addr; |
560 | dma_addr_t hw_cons_phys_addr; | |
036d61f0 AC |
561 | struct netdev_queue *txq; |
562 | } ____cacheline_internodealigned_in_smp; | |
af19b491 AKS |
563 | |
564 | /* | |
565 | * Receive context. There is one such structure per instance of the | |
566 | * receive processing. Any state information that is relevant to | |
567 | * the receive, and is must be in this structure. The global data may be | |
568 | * present elsewhere. | |
569 | */ | |
570 | struct qlcnic_recv_context { | |
b1fc6d3c AC |
571 | struct qlcnic_host_rds_ring *rds_rings; |
572 | struct qlcnic_host_sds_ring *sds_rings; | |
af19b491 AKS |
573 | u32 state; |
574 | u16 context_id; | |
575 | u16 virt_port; | |
af19b491 AKS |
576 | }; |
577 | ||
578 | /* HW context creation */ | |
579 | ||
580 | #define QLCNIC_OS_CRB_RETRY_COUNT 4000 | |
af19b491 AKS |
581 | |
582 | #define QLCNIC_CDRP_CMD_BIT 0x80000000 | |
583 | ||
584 | /* | |
585 | * All responses must have the QLCNIC_CDRP_CMD_BIT cleared | |
586 | * in the crb QLCNIC_CDRP_CRB_OFFSET. | |
587 | */ | |
588 | #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp) | |
589 | #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0) | |
590 | ||
591 | #define QLCNIC_CDRP_RSP_OK 0x00000001 | |
592 | #define QLCNIC_CDRP_RSP_FAIL 0x00000002 | |
593 | #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003 | |
594 | ||
595 | /* | |
596 | * All commands must have the QLCNIC_CDRP_CMD_BIT set in | |
597 | * the crb QLCNIC_CDRP_CRB_OFFSET. | |
598 | */ | |
599 | #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd)) | |
af19b491 AKS |
600 | |
601 | #define QLCNIC_RCODE_SUCCESS 0 | |
e42ede22 | 602 | #define QLCNIC_RCODE_INVALID_ARGS 6 |
7e610caa | 603 | #define QLCNIC_RCODE_NOT_SUPPORTED 9 |
e42ede22 JK |
604 | #define QLCNIC_RCODE_NOT_PERMITTED 10 |
605 | #define QLCNIC_RCODE_NOT_IMPL 15 | |
606 | #define QLCNIC_RCODE_INVALID 16 | |
af19b491 AKS |
607 | #define QLCNIC_RCODE_TIMEOUT 17 |
608 | #define QLCNIC_DESTROY_CTX_RESET 0 | |
609 | ||
610 | /* | |
611 | * Capabilities Announced | |
612 | */ | |
613 | #define QLCNIC_CAP0_LEGACY_CONTEXT (1) | |
614 | #define QLCNIC_CAP0_LEGACY_MN (1 << 2) | |
615 | #define QLCNIC_CAP0_LSO (1 << 6) | |
616 | #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7) | |
617 | #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8) | |
8f891387 | 618 | #define QLCNIC_CAP0_VALIDOFF (1 << 11) |
cae82d49 | 619 | #define QLCNIC_CAP0_LRO_MSS (1 << 21) |
012ec812 | 620 | #define QLCNIC_CAP0_TX_MULTI (1 << 22) |
af19b491 AKS |
621 | |
622 | /* | |
623 | * Context state | |
624 | */ | |
d626ad4d | 625 | #define QLCNIC_HOST_CTX_STATE_FREED 0 |
af19b491 AKS |
626 | #define QLCNIC_HOST_CTX_STATE_ACTIVE 2 |
627 | ||
628 | /* | |
629 | * Rx context | |
630 | */ | |
631 | ||
632 | struct qlcnic_hostrq_sds_ring { | |
633 | __le64 host_phys_addr; /* Ring base addr */ | |
634 | __le32 ring_size; /* Ring entries */ | |
635 | __le16 msi_index; | |
636 | __le16 rsvd; /* Padding */ | |
b1fc6d3c | 637 | } __packed; |
af19b491 AKS |
638 | |
639 | struct qlcnic_hostrq_rds_ring { | |
640 | __le64 host_phys_addr; /* Ring base addr */ | |
641 | __le64 buff_size; /* Packet buffer size */ | |
642 | __le32 ring_size; /* Ring entries */ | |
643 | __le32 ring_kind; /* Class of ring */ | |
b1fc6d3c | 644 | } __packed; |
af19b491 AKS |
645 | |
646 | struct qlcnic_hostrq_rx_ctx { | |
647 | __le64 host_rsp_dma_addr; /* Response dma'd here */ | |
012ec812 | 648 | __le32 capabilities[4]; /* Flag bit vector */ |
af19b491 AKS |
649 | __le32 host_int_crb_mode; /* Interrupt crb usage */ |
650 | __le32 host_rds_crb_mode; /* RDS crb usage */ | |
651 | /* These ring offsets are relative to data[0] below */ | |
652 | __le32 rds_ring_offset; /* Offset to RDS config */ | |
653 | __le32 sds_ring_offset; /* Offset to SDS config */ | |
654 | __le16 num_rds_rings; /* Count of RDS rings */ | |
655 | __le16 num_sds_rings; /* Count of SDS rings */ | |
8f891387 | 656 | __le16 valid_field_offset; |
657 | u8 txrx_sds_binding; | |
658 | u8 msix_handler; | |
659 | u8 reserved[128]; /* reserve space for future expansion*/ | |
af19b491 AKS |
660 | /* MUST BE 64-bit aligned. |
661 | The following is packed: | |
662 | - N hostrq_rds_rings | |
663 | - N hostrq_sds_rings */ | |
664 | char data[0]; | |
b1fc6d3c | 665 | } __packed; |
af19b491 AKS |
666 | |
667 | struct qlcnic_cardrsp_rds_ring{ | |
668 | __le32 host_producer_crb; /* Crb to use */ | |
669 | __le32 rsvd1; /* Padding */ | |
b1fc6d3c | 670 | } __packed; |
af19b491 AKS |
671 | |
672 | struct qlcnic_cardrsp_sds_ring { | |
673 | __le32 host_consumer_crb; /* Crb to use */ | |
674 | __le32 interrupt_crb; /* Crb to use */ | |
b1fc6d3c | 675 | } __packed; |
af19b491 AKS |
676 | |
677 | struct qlcnic_cardrsp_rx_ctx { | |
678 | /* These ring offsets are relative to data[0] below */ | |
679 | __le32 rds_ring_offset; /* Offset to RDS config */ | |
680 | __le32 sds_ring_offset; /* Offset to SDS config */ | |
681 | __le32 host_ctx_state; /* Starting State */ | |
682 | __le32 num_fn_per_port; /* How many PCI fn share the port */ | |
683 | __le16 num_rds_rings; /* Count of RDS rings */ | |
684 | __le16 num_sds_rings; /* Count of SDS rings */ | |
685 | __le16 context_id; /* Handle for context */ | |
686 | u8 phys_port; /* Physical id of port */ | |
687 | u8 virt_port; /* Virtual/Logical id of port */ | |
688 | u8 reserved[128]; /* save space for future expansion */ | |
689 | /* MUST BE 64-bit aligned. | |
690 | The following is packed: | |
691 | - N cardrsp_rds_rings | |
692 | - N cardrs_sds_rings */ | |
693 | char data[0]; | |
b1fc6d3c | 694 | } __packed; |
af19b491 AKS |
695 | |
696 | #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \ | |
697 | (sizeof(HOSTRQ_RX) + \ | |
698 | (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \ | |
699 | (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring))) | |
700 | ||
701 | #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \ | |
702 | (sizeof(CARDRSP_RX) + \ | |
703 | (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \ | |
704 | (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring))) | |
705 | ||
706 | /* | |
707 | * Tx context | |
708 | */ | |
709 | ||
710 | struct qlcnic_hostrq_cds_ring { | |
711 | __le64 host_phys_addr; /* Ring base addr */ | |
712 | __le32 ring_size; /* Ring entries */ | |
713 | __le32 rsvd; /* Padding */ | |
b1fc6d3c | 714 | } __packed; |
af19b491 AKS |
715 | |
716 | struct qlcnic_hostrq_tx_ctx { | |
717 | __le64 host_rsp_dma_addr; /* Response dma'd here */ | |
718 | __le64 cmd_cons_dma_addr; /* */ | |
719 | __le64 dummy_dma_addr; /* */ | |
720 | __le32 capabilities[4]; /* Flag bit vector */ | |
721 | __le32 host_int_crb_mode; /* Interrupt crb usage */ | |
722 | __le32 rsvd1; /* Padding */ | |
723 | __le16 rsvd2; /* Padding */ | |
724 | __le16 interrupt_ctl; | |
725 | __le16 msi_index; | |
726 | __le16 rsvd3; /* Padding */ | |
727 | struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */ | |
728 | u8 reserved[128]; /* future expansion */ | |
b1fc6d3c | 729 | } __packed; |
af19b491 AKS |
730 | |
731 | struct qlcnic_cardrsp_cds_ring { | |
732 | __le32 host_producer_crb; /* Crb to use */ | |
733 | __le32 interrupt_crb; /* Crb to use */ | |
b1fc6d3c | 734 | } __packed; |
af19b491 AKS |
735 | |
736 | struct qlcnic_cardrsp_tx_ctx { | |
737 | __le32 host_ctx_state; /* Starting state */ | |
738 | __le16 context_id; /* Handle for context */ | |
739 | u8 phys_port; /* Physical id of port */ | |
740 | u8 virt_port; /* Virtual/Logical id of port */ | |
741 | struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */ | |
742 | u8 reserved[128]; /* future expansion */ | |
b1fc6d3c | 743 | } __packed; |
af19b491 AKS |
744 | |
745 | #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX)) | |
746 | #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX)) | |
747 | ||
748 | /* CRB */ | |
749 | ||
750 | #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0 | |
751 | #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1 | |
752 | #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2 | |
753 | #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3 | |
754 | ||
755 | #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0 | |
756 | #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1 | |
757 | #define QLCNIC_HOST_INT_CRB_MODE_NORX 2 | |
758 | #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3 | |
759 | #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4 | |
760 | ||
761 | ||
762 | /* MAC */ | |
763 | ||
ff1b1bf8 | 764 | #define MC_COUNT_P3P 38 |
af19b491 AKS |
765 | |
766 | #define QLCNIC_MAC_NOOP 0 | |
767 | #define QLCNIC_MAC_ADD 1 | |
768 | #define QLCNIC_MAC_DEL 2 | |
03c5d770 AKS |
769 | #define QLCNIC_MAC_VLAN_ADD 3 |
770 | #define QLCNIC_MAC_VLAN_DEL 4 | |
af19b491 AKS |
771 | |
772 | struct qlcnic_mac_list_s { | |
773 | struct list_head list; | |
774 | uint8_t mac_addr[ETH_ALEN+2]; | |
775 | }; | |
776 | ||
fe1adc6b JK |
777 | /* MAC Learn */ |
778 | #define NO_MAC_LEARN 0 | |
779 | #define DRV_MAC_LEARN 1 | |
780 | #define FDB_MAC_LEARN 2 | |
781 | ||
af19b491 AKS |
782 | #define QLCNIC_HOST_REQUEST 0x13 |
783 | #define QLCNIC_REQUEST 0x14 | |
784 | ||
785 | #define QLCNIC_MAC_EVENT 0x1 | |
786 | ||
787 | #define QLCNIC_IP_UP 2 | |
788 | #define QLCNIC_IP_DOWN 3 | |
789 | ||
22c8c934 | 790 | #define QLCNIC_ILB_MODE 0x1 |
e1428d26 | 791 | #define QLCNIC_ELB_MODE 0x2 |
22c8c934 SC |
792 | |
793 | #define QLCNIC_LINKEVENT 0x1 | |
794 | #define QLCNIC_LB_RESPONSE 0x2 | |
795 | #define QLCNIC_IS_LB_CONFIGURED(VAL) \ | |
796 | (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE)) | |
797 | ||
af19b491 AKS |
798 | /* |
799 | * Driver --> Firmware | |
800 | */ | |
b1fc6d3c AC |
801 | #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1 |
802 | #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3 | |
803 | #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4 | |
804 | #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7 | |
805 | #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc | |
806 | #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12 | |
22c8c934 | 807 | |
b1fc6d3c AC |
808 | #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15 |
809 | #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17 | |
810 | #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18 | |
22c8c934 SC |
811 | #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13 |
812 | ||
af19b491 AKS |
813 | /* |
814 | * Firmware --> Driver | |
815 | */ | |
816 | ||
22c8c934 | 817 | #define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f |
7f966452 | 818 | #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 0x8D |
2d8ebcab | 819 | #define QLCNIC_C2H_OPCODE_GET_DCB_AEN 0x90 |
af19b491 AKS |
820 | |
821 | #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ | |
822 | #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ | |
823 | #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ | |
824 | ||
825 | #define QLCNIC_LRO_REQUEST_CLEANUP 4 | |
826 | ||
827 | /* Capabilites received */ | |
ac8d0c4f AC |
828 | #define QLCNIC_FW_CAPABILITY_TSO BIT_1 |
829 | #define QLCNIC_FW_CAPABILITY_BDG BIT_8 | |
830 | #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9 | |
831 | #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10 | |
012ec812 | 832 | #define QLCNIC_FW_CAPABILITY_2_MULTI_TX BIT_4 |
fef0c060 | 833 | #define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK BIT_27 |
cae82d49 RB |
834 | #define QLCNIC_FW_CAPABILITY_MORE_CAPS BIT_31 |
835 | ||
836 | #define QLCNIC_FW_CAPABILITY_2_LRO_MAX_TCP_SEG BIT_2 | |
776e7bde | 837 | #define QLCNIC_FW_CAP2_HW_LRO_IPV6 BIT_3 |
8af3f33d | 838 | #define QLCNIC_FW_CAPABILITY_SET_DRV_VER BIT_5 |
487042af | 839 | #define QLCNIC_FW_CAPABILITY_2_BEACON BIT_7 |
35dafcb0 | 840 | #define QLCNIC_FW_CAPABILITY_2_PER_PORT_ESWITCH_CFG BIT_8 |
af19b491 AKS |
841 | |
842 | /* module types */ | |
843 | #define LINKEVENT_MODULE_NOT_PRESENT 1 | |
844 | #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2 | |
845 | #define LINKEVENT_MODULE_OPTICAL_SRLR 3 | |
846 | #define LINKEVENT_MODULE_OPTICAL_LRM 4 | |
847 | #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5 | |
848 | #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6 | |
849 | #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7 | |
850 | #define LINKEVENT_MODULE_TWINAX 8 | |
851 | ||
852 | #define LINKSPEED_10GBPS 10000 | |
853 | #define LINKSPEED_1GBPS 1000 | |
854 | #define LINKSPEED_100MBPS 100 | |
855 | #define LINKSPEED_10MBPS 10 | |
856 | ||
857 | #define LINKSPEED_ENCODED_10MBPS 0 | |
858 | #define LINKSPEED_ENCODED_100MBPS 1 | |
859 | #define LINKSPEED_ENCODED_1GBPS 2 | |
860 | ||
861 | #define LINKEVENT_AUTONEG_DISABLED 0 | |
862 | #define LINKEVENT_AUTONEG_ENABLED 1 | |
863 | ||
864 | #define LINKEVENT_HALF_DUPLEX 0 | |
865 | #define LINKEVENT_FULL_DUPLEX 1 | |
866 | ||
867 | #define LINKEVENT_LINKSPEED_MBPS 0 | |
868 | #define LINKEVENT_LINKSPEED_ENCODED 1 | |
869 | ||
af19b491 AKS |
870 | /* firmware response header: |
871 | * 63:58 - message type | |
872 | * 57:56 - owner | |
873 | * 55:53 - desc count | |
874 | * 52:48 - reserved | |
875 | * 47:40 - completion id | |
876 | * 39:32 - opcode | |
877 | * 31:16 - error code | |
878 | * 15:00 - reserved | |
879 | */ | |
880 | #define qlcnic_get_nic_msg_opcode(msg_hdr) \ | |
881 | ((msg_hdr >> 32) & 0xFF) | |
882 | ||
883 | struct qlcnic_fw_msg { | |
884 | union { | |
885 | struct { | |
886 | u64 hdr; | |
887 | u64 body[7]; | |
888 | }; | |
889 | u64 words[8]; | |
890 | }; | |
891 | }; | |
892 | ||
893 | struct qlcnic_nic_req { | |
894 | __le64 qhdr; | |
895 | __le64 req_hdr; | |
896 | __le64 words[6]; | |
b1fc6d3c | 897 | } __packed; |
af19b491 AKS |
898 | |
899 | struct qlcnic_mac_req { | |
900 | u8 op; | |
901 | u8 tag; | |
902 | u8 mac_addr[6]; | |
903 | }; | |
904 | ||
7e56cac4 SC |
905 | struct qlcnic_vlan_req { |
906 | __le16 vlan_id; | |
907 | __le16 rsvd[3]; | |
b1fc6d3c | 908 | } __packed; |
7e56cac4 | 909 | |
b501595c SC |
910 | struct qlcnic_ipaddr { |
911 | __be32 ipv4; | |
912 | __be32 ipv6[4]; | |
913 | }; | |
914 | ||
af19b491 AKS |
915 | #define QLCNIC_MSI_ENABLED 0x02 |
916 | #define QLCNIC_MSIX_ENABLED 0x04 | |
7f966452 | 917 | #define QLCNIC_LRO_ENABLED 0x01 |
24763d80 | 918 | #define QLCNIC_LRO_DISABLED 0x00 |
af19b491 AKS |
919 | #define QLCNIC_BRIDGE_ENABLED 0X10 |
920 | #define QLCNIC_DIAG_ENABLED 0x20 | |
0e33c664 | 921 | #define QLCNIC_ESWITCH_ENABLED 0x40 |
0866d96d | 922 | #define QLCNIC_ADAPTER_INITIALIZED 0x80 |
8cf61f89 | 923 | #define QLCNIC_TAGGING_ENABLED 0x100 |
fe4d434d | 924 | #define QLCNIC_MACSPOOF 0x200 |
7373373d | 925 | #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400 |
ee07c1a7 | 926 | #define QLCNIC_PROMISC_DISABLED 0x800 |
b0044bcf | 927 | #define QLCNIC_NEED_FLR 0x1000 |
602ca6f0 | 928 | #define QLCNIC_FW_RESET_OWNER 0x2000 |
032a13c7 | 929 | #define QLCNIC_FW_HANG 0x4000 |
cae82d49 | 930 | #define QLCNIC_FW_LRO_MSS_CAP 0x8000 |
da6c8063 | 931 | #define QLCNIC_TX_INTR_SHARED 0x10000 |
147a9088 | 932 | #define QLCNIC_APP_CHANGED_FLAGS 0x20000 |
07a251c8 SS |
933 | #define QLCNIC_HAS_PHYS_PORT_ID 0x40000 |
934 | ||
af19b491 AKS |
935 | #define QLCNIC_IS_MSI_FAMILY(adapter) \ |
936 | ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED)) | |
147a9088 SS |
937 | #define QLCNIC_IS_TSO_CAPABLE(adapter) \ |
938 | ((adapter)->ahw->capabilities & QLCNIC_FW_CAPABILITY_TSO) | |
af19b491 | 939 | |
487042af HM |
940 | #define QLCNIC_BEACON_EANBLE 0xC |
941 | #define QLCNIC_BEACON_DISABLE 0xD | |
942 | ||
f94bc1e7 | 943 | #define QLCNIC_DEF_NUM_STS_DESC_RINGS 4 |
012ec812 | 944 | #define QLCNIC_DEF_NUM_TX_RINGS 4 |
af19b491 AKS |
945 | #define QLCNIC_MSIX_TBL_SPACE 8192 |
946 | #define QLCNIC_PCI_REG_MSIX_TBL 0x44 | |
2e9d722d | 947 | #define QLCNIC_MSIX_TBL_PGSIZE 4096 |
af19b491 AKS |
948 | |
949 | #define QLCNIC_NETDEV_WEIGHT 128 | |
950 | #define QLCNIC_ADAPTER_UP_MAGIC 777 | |
951 | ||
952 | #define __QLCNIC_FW_ATTACHED 0 | |
953 | #define __QLCNIC_DEV_UP 1 | |
954 | #define __QLCNIC_RESETTING 2 | |
955 | #define __QLCNIC_START_FW 4 | |
451724c8 | 956 | #define __QLCNIC_AER 5 |
89b4208e | 957 | #define __QLCNIC_DIAG_RES_ALLOC 6 |
728a98b8 | 958 | #define __QLCNIC_LED_ENABLE 7 |
02feda17 | 959 | #define __QLCNIC_ELB_INPROGRESS 8 |
012ec812 | 960 | #define __QLCNIC_MULTI_TX_UNIQUE 9 |
02feda17 RB |
961 | #define __QLCNIC_SRIOV_ENABLE 10 |
962 | #define __QLCNIC_SRIOV_CAPABLE 11 | |
7ed3ce48 | 963 | #define __QLCNIC_MBX_POLL_ENABLE 12 |
4690a7e4 | 964 | #define __QLCNIC_DIAG_MODE 13 |
14d385b9 | 965 | #define __QLCNIC_DCB_STATE 14 |
2d8ebcab | 966 | #define __QLCNIC_DCB_IN_AEN 15 |
af19b491 | 967 | |
7eb9855d | 968 | #define QLCNIC_INTERRUPT_TEST 1 |
cdaff185 | 969 | #define QLCNIC_LOOPBACK_TEST 2 |
c75822a3 | 970 | #define QLCNIC_LED_TEST 3 |
7eb9855d | 971 | |
b5e5492c | 972 | #define QLCNIC_FILTER_AGE 80 |
e5edb7b1 | 973 | #define QLCNIC_READD_AGE 20 |
b5e5492c | 974 | #define QLCNIC_LB_MAX_FILTERS 64 |
7f966452 | 975 | #define QLCNIC_LB_BUCKET_SIZE 32 |
629263ac | 976 | #define QLCNIC_ILB_MAX_RCV_LOOP 10 |
fef0c060 | 977 | |
b5e5492c AKS |
978 | struct qlcnic_filter { |
979 | struct hlist_node fnode; | |
980 | u8 faddr[ETH_ALEN]; | |
f80bc8fe | 981 | u16 vlan_id; |
b5e5492c AKS |
982 | unsigned long ftime; |
983 | }; | |
984 | ||
985 | struct qlcnic_filter_hash { | |
986 | struct hlist_head *fhead; | |
987 | u8 fnum; | |
7f966452 SC |
988 | u16 fmax; |
989 | u16 fbucket_size; | |
b5e5492c AKS |
990 | }; |
991 | ||
e5c4e6c6 MC |
992 | /* Mailbox specific data structures */ |
993 | struct qlcnic_mailbox { | |
994 | struct workqueue_struct *work_q; | |
995 | struct qlcnic_adapter *adapter; | |
996 | struct qlcnic_mbx_ops *ops; | |
997 | struct work_struct work; | |
998 | struct completion completion; | |
999 | struct list_head cmd_q; | |
1000 | unsigned long status; | |
1001 | spinlock_t queue_lock; /* Mailbox queue lock */ | |
1002 | spinlock_t aen_lock; /* Mailbox response/AEN lock */ | |
1003 | atomic_t rsp_status; | |
1004 | u32 num_cmds; | |
1005 | }; | |
1006 | ||
af19b491 | 1007 | struct qlcnic_adapter { |
b1fc6d3c AC |
1008 | struct qlcnic_hardware_context *ahw; |
1009 | struct qlcnic_recv_context *recv_ctx; | |
1010 | struct qlcnic_host_tx_ring *tx_ring; | |
af19b491 AKS |
1011 | struct net_device *netdev; |
1012 | struct pci_dev *pdev; | |
af19b491 | 1013 | |
b1fc6d3c AC |
1014 | unsigned long state; |
1015 | u32 flags; | |
af19b491 | 1016 | |
79788450 | 1017 | int max_drv_tx_rings; |
af19b491 AKS |
1018 | u16 num_txd; |
1019 | u16 num_rxd; | |
1020 | u16 num_jumbo_rxd; | |
90d19005 SC |
1021 | u16 max_rxd; |
1022 | u16 max_jumbo_rxd; | |
af19b491 AKS |
1023 | |
1024 | u8 max_rds_rings; | |
1025 | u8 max_sds_rings; | |
7f966452 | 1026 | u8 rx_csum; |
af19b491 | 1027 | u8 portnum; |
af19b491 | 1028 | |
af19b491 AKS |
1029 | u8 fw_wait_cnt; |
1030 | u8 fw_fail_cnt; | |
1031 | u8 tx_timeo_cnt; | |
1032 | u8 need_fw_reset; | |
f036e4f4 | 1033 | u8 reset_ctx_cnt; |
af19b491 | 1034 | |
af19b491 | 1035 | u16 is_up; |
91b7282b RB |
1036 | u16 rx_pvid; |
1037 | u16 tx_pvid; | |
2e9d722d | 1038 | |
af19b491 | 1039 | u32 irq; |
4e70812b | 1040 | u32 heartbeat; |
af19b491 AKS |
1041 | |
1042 | u8 dev_state; | |
aa5e18c0 SC |
1043 | u8 reset_ack_timeo; |
1044 | u8 dev_init_timeo; | |
af19b491 AKS |
1045 | |
1046 | u8 mac_addr[ETH_ALEN]; | |
1047 | ||
6df900e9 | 1048 | u64 dev_rst_time; |
fe1adc6b JK |
1049 | bool drv_mac_learn; |
1050 | bool fdb_mac_learn; | |
b9796a14 | 1051 | unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
d865ebb4 | 1052 | u8 flash_mfg_id; |
346fe763 | 1053 | struct qlcnic_npar_info *npars; |
2e9d722d AC |
1054 | struct qlcnic_eswitch *eswitch; |
1055 | struct qlcnic_nic_template *nic_ops; | |
1056 | ||
af19b491 | 1057 | struct qlcnic_adapter_stats stats; |
b1fc6d3c | 1058 | struct list_head mac_list; |
af19b491 AKS |
1059 | |
1060 | void __iomem *tgt_mask_reg; | |
1061 | void __iomem *tgt_status_reg; | |
1062 | void __iomem *crb_int_state_reg; | |
1063 | void __iomem *isr_int_vec; | |
1064 | ||
f94bc1e7 | 1065 | struct msix_entry *msix_entries; |
7f966452 | 1066 | struct workqueue_struct *qlcnic_wq; |
af19b491 | 1067 | struct delayed_work fw_work; |
7f966452 | 1068 | struct delayed_work idc_aen_work; |
7ed3ce48 | 1069 | struct delayed_work mbx_poll_work; |
14d385b9 | 1070 | struct qlcnic_dcb *dcb; |
af19b491 | 1071 | |
b5e5492c | 1072 | struct qlcnic_filter_hash fhash; |
53643a75 | 1073 | struct qlcnic_filter_hash rx_fhash; |
e8b508ef | 1074 | struct list_head vf_mc_list; |
b5e5492c | 1075 | |
b1fc6d3c AC |
1076 | spinlock_t tx_clean_lock; |
1077 | spinlock_t mac_learn_lock; | |
53643a75 SS |
1078 | /* spinlock for catching rcv filters for eswitch traffic */ |
1079 | spinlock_t rx_mac_learn_lock; | |
63507592 | 1080 | u32 file_prd_off; /*File fw product offset*/ |
af19b491 | 1081 | u32 fw_version; |
147a9088 | 1082 | u32 offload_flags; |
af19b491 AKS |
1083 | const struct firmware *fw; |
1084 | }; | |
1085 | ||
63507592 | 1086 | struct qlcnic_info_le { |
2e9d722d | 1087 | __le16 pci_func; |
63507592 | 1088 | __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */ |
2e9d722d | 1089 | __le16 phys_port; |
63507592 | 1090 | __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */ |
2e9d722d AC |
1091 | |
1092 | __le32 capabilities; | |
1093 | u8 max_mac_filters; | |
1094 | u8 reserved1; | |
1095 | __le16 max_mtu; | |
1096 | ||
1097 | __le16 max_tx_ques; | |
1098 | __le16 max_rx_ques; | |
1099 | __le16 min_tx_bw; | |
1100 | __le16 max_tx_bw; | |
7f966452 SC |
1101 | __le32 op_type; |
1102 | __le16 max_bw_reg_offset; | |
1103 | __le16 max_linkspeed_reg_offset; | |
1104 | __le32 capability1; | |
1105 | __le32 capability2; | |
1106 | __le32 capability3; | |
1107 | __le16 max_tx_mac_filters; | |
1108 | __le16 max_rx_mcast_mac_filters; | |
1109 | __le16 max_rx_ucast_mac_filters; | |
1110 | __le16 max_rx_ip_addr; | |
1111 | __le16 max_rx_lro_flow; | |
1112 | __le16 max_rx_status_rings; | |
1113 | __le16 max_rx_buf_rings; | |
1114 | __le16 max_tx_vlan_keys; | |
1115 | u8 total_pf; | |
1116 | u8 total_rss_engines; | |
1117 | __le16 max_vports; | |
02feda17 RB |
1118 | __le16 linkstate_reg_offset; |
1119 | __le16 bit_offsets; | |
1120 | __le16 max_local_ipv6_addrs; | |
1121 | __le16 max_remote_ipv6_addrs; | |
1122 | u8 reserved2[56]; | |
b1fc6d3c | 1123 | } __packed; |
2e9d722d | 1124 | |
63507592 SS |
1125 | struct qlcnic_info { |
1126 | u16 pci_func; | |
1127 | u16 op_mode; | |
1128 | u16 phys_port; | |
1129 | u16 switch_mode; | |
1130 | u32 capabilities; | |
1131 | u8 max_mac_filters; | |
63507592 SS |
1132 | u16 max_mtu; |
1133 | u16 max_tx_ques; | |
1134 | u16 max_rx_ques; | |
1135 | u16 min_tx_bw; | |
1136 | u16 max_tx_bw; | |
7f966452 SC |
1137 | u32 op_type; |
1138 | u16 max_bw_reg_offset; | |
1139 | u16 max_linkspeed_reg_offset; | |
1140 | u32 capability1; | |
1141 | u32 capability2; | |
1142 | u32 capability3; | |
1143 | u16 max_tx_mac_filters; | |
1144 | u16 max_rx_mcast_mac_filters; | |
1145 | u16 max_rx_ucast_mac_filters; | |
1146 | u16 max_rx_ip_addr; | |
1147 | u16 max_rx_lro_flow; | |
1148 | u16 max_rx_status_rings; | |
1149 | u16 max_rx_buf_rings; | |
1150 | u16 max_tx_vlan_keys; | |
1151 | u8 total_pf; | |
1152 | u8 total_rss_engines; | |
1153 | u16 max_vports; | |
02feda17 RB |
1154 | u16 linkstate_reg_offset; |
1155 | u16 bit_offsets; | |
1156 | u16 max_local_ipv6_addrs; | |
1157 | u16 max_remote_ipv6_addrs; | |
63507592 | 1158 | }; |
2e9d722d | 1159 | |
63507592 SS |
1160 | struct qlcnic_pci_info_le { |
1161 | __le16 id; /* pci function id */ | |
1162 | __le16 active; /* 1 = Enabled */ | |
1163 | __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */ | |
1164 | __le16 default_port; /* default port number */ | |
1165 | ||
1166 | __le16 tx_min_bw; /* Multiple of 100mbpc */ | |
2e9d722d AC |
1167 | __le16 tx_max_bw; |
1168 | __le16 reserved1[2]; | |
1169 | ||
1170 | u8 mac[ETH_ALEN]; | |
7f966452 SC |
1171 | __le16 func_count; |
1172 | u8 reserved2[104]; | |
1173 | ||
b1fc6d3c | 1174 | } __packed; |
2e9d722d | 1175 | |
63507592 SS |
1176 | struct qlcnic_pci_info { |
1177 | u16 id; | |
1178 | u16 active; | |
1179 | u16 type; | |
1180 | u16 default_port; | |
1181 | u16 tx_min_bw; | |
1182 | u16 tx_max_bw; | |
1183 | u8 mac[ETH_ALEN]; | |
7f966452 | 1184 | u16 func_count; |
63507592 SS |
1185 | }; |
1186 | ||
346fe763 | 1187 | struct qlcnic_npar_info { |
35dafcb0 | 1188 | bool eswitch_status; |
4e8acb01 | 1189 | u16 pvid; |
cea8975e AC |
1190 | u16 min_bw; |
1191 | u16 max_bw; | |
346fe763 RB |
1192 | u8 phy_port; |
1193 | u8 type; | |
1194 | u8 active; | |
1195 | u8 enable_pm; | |
1196 | u8 dest_npar; | |
346fe763 | 1197 | u8 discard_tagged; |
7373373d | 1198 | u8 mac_override; |
4e8acb01 RB |
1199 | u8 mac_anti_spoof; |
1200 | u8 promisc_mode; | |
1201 | u8 offload_flags; | |
bff57d8e | 1202 | u8 pci_func; |
346fe763 | 1203 | }; |
4e8acb01 | 1204 | |
2e9d722d AC |
1205 | struct qlcnic_eswitch { |
1206 | u8 port; | |
1207 | u8 active_vports; | |
1208 | u8 active_vlans; | |
1209 | u8 active_ucast_filters; | |
1210 | u8 max_ucast_filters; | |
1211 | u8 max_active_vlans; | |
1212 | ||
1213 | u32 flags; | |
1214 | #define QLCNIC_SWITCH_ENABLE BIT_1 | |
1215 | #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2 | |
1216 | #define QLCNIC_SWITCH_PROMISC_MODE BIT_3 | |
1217 | #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4 | |
1218 | }; | |
1219 | ||
346fe763 RB |
1220 | |
1221 | /* Return codes for Error handling */ | |
1222 | #define QL_STATUS_INVALID_PARAM -1 | |
1223 | ||
2abea2f0 | 1224 | #define MAX_BW 100 /* % of link speed */ |
346fe763 RB |
1225 | #define MAX_VLAN_ID 4095 |
1226 | #define MIN_VLAN_ID 2 | |
346fe763 RB |
1227 | #define DEFAULT_MAC_LEARN 1 |
1228 | ||
0184bbba | 1229 | #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID) |
2abea2f0 | 1230 | #define IS_VALID_BW(bw) (bw <= MAX_BW) |
346fe763 RB |
1231 | |
1232 | struct qlcnic_pci_func_cfg { | |
1233 | u16 func_type; | |
1234 | u16 min_bw; | |
1235 | u16 max_bw; | |
1236 | u16 port_num; | |
1237 | u8 pci_func; | |
1238 | u8 func_state; | |
1239 | u8 def_mac_addr[6]; | |
1240 | }; | |
1241 | ||
1242 | struct qlcnic_npar_func_cfg { | |
1243 | u32 fw_capab; | |
1244 | u16 port_num; | |
1245 | u16 min_bw; | |
1246 | u16 max_bw; | |
1247 | u16 max_tx_queues; | |
1248 | u16 max_rx_queues; | |
1249 | u8 pci_func; | |
1250 | u8 op_mode; | |
1251 | }; | |
1252 | ||
1253 | struct qlcnic_pm_func_cfg { | |
1254 | u8 pci_func; | |
1255 | u8 action; | |
1256 | u8 dest_npar; | |
1257 | u8 reserved[5]; | |
1258 | }; | |
1259 | ||
1260 | struct qlcnic_esw_func_cfg { | |
1261 | u16 vlan_id; | |
4e8acb01 RB |
1262 | u8 op_mode; |
1263 | u8 op_type; | |
346fe763 RB |
1264 | u8 pci_func; |
1265 | u8 host_vlan_tag; | |
1266 | u8 promisc_mode; | |
1267 | u8 discard_tagged; | |
7373373d | 1268 | u8 mac_override; |
4e8acb01 RB |
1269 | u8 mac_anti_spoof; |
1270 | u8 offload_flags; | |
1271 | u8 reserved[5]; | |
346fe763 RB |
1272 | }; |
1273 | ||
b6021212 AKS |
1274 | #define QLCNIC_STATS_VERSION 1 |
1275 | #define QLCNIC_STATS_PORT 1 | |
1276 | #define QLCNIC_STATS_ESWITCH 2 | |
1277 | #define QLCNIC_QUERY_RX_COUNTER 0 | |
1278 | #define QLCNIC_QUERY_TX_COUNTER 1 | |
54a8997c JK |
1279 | #define QLCNIC_STATS_NOT_AVAIL 0xffffffffffffffffULL |
1280 | #define QLCNIC_FILL_STATS(VAL1) \ | |
1281 | (((VAL1) == QLCNIC_STATS_NOT_AVAIL) ? 0 : VAL1) | |
1282 | #define QLCNIC_MAC_STATS 1 | |
1283 | #define QLCNIC_ESW_STATS 2 | |
ef182805 AKS |
1284 | |
1285 | #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\ | |
1286 | do { \ | |
54a8997c JK |
1287 | if (((VAL1) == QLCNIC_STATS_NOT_AVAIL) && \ |
1288 | ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \ | |
ef182805 | 1289 | (VAL1) = (VAL2); \ |
54a8997c JK |
1290 | else if (((VAL1) != QLCNIC_STATS_NOT_AVAIL) && \ |
1291 | ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \ | |
ef182805 AKS |
1292 | (VAL1) += (VAL2); \ |
1293 | } while (0) | |
1294 | ||
63507592 | 1295 | struct qlcnic_mac_statistics_le { |
54a8997c JK |
1296 | __le64 mac_tx_frames; |
1297 | __le64 mac_tx_bytes; | |
1298 | __le64 mac_tx_mcast_pkts; | |
1299 | __le64 mac_tx_bcast_pkts; | |
1300 | __le64 mac_tx_pause_cnt; | |
1301 | __le64 mac_tx_ctrl_pkt; | |
1302 | __le64 mac_tx_lt_64b_pkts; | |
1303 | __le64 mac_tx_lt_127b_pkts; | |
1304 | __le64 mac_tx_lt_255b_pkts; | |
1305 | __le64 mac_tx_lt_511b_pkts; | |
1306 | __le64 mac_tx_lt_1023b_pkts; | |
1307 | __le64 mac_tx_lt_1518b_pkts; | |
1308 | __le64 mac_tx_gt_1518b_pkts; | |
1309 | __le64 rsvd1[3]; | |
1310 | ||
1311 | __le64 mac_rx_frames; | |
1312 | __le64 mac_rx_bytes; | |
1313 | __le64 mac_rx_mcast_pkts; | |
1314 | __le64 mac_rx_bcast_pkts; | |
1315 | __le64 mac_rx_pause_cnt; | |
1316 | __le64 mac_rx_ctrl_pkt; | |
1317 | __le64 mac_rx_lt_64b_pkts; | |
1318 | __le64 mac_rx_lt_127b_pkts; | |
1319 | __le64 mac_rx_lt_255b_pkts; | |
1320 | __le64 mac_rx_lt_511b_pkts; | |
1321 | __le64 mac_rx_lt_1023b_pkts; | |
1322 | __le64 mac_rx_lt_1518b_pkts; | |
1323 | __le64 mac_rx_gt_1518b_pkts; | |
1324 | __le64 rsvd2[3]; | |
1325 | ||
1326 | __le64 mac_rx_length_error; | |
1327 | __le64 mac_rx_length_small; | |
1328 | __le64 mac_rx_length_large; | |
1329 | __le64 mac_rx_jabber; | |
1330 | __le64 mac_rx_dropped; | |
1331 | __le64 mac_rx_crc_error; | |
1332 | __le64 mac_align_error; | |
1333 | } __packed; | |
1334 | ||
63507592 SS |
1335 | struct qlcnic_mac_statistics { |
1336 | u64 mac_tx_frames; | |
1337 | u64 mac_tx_bytes; | |
1338 | u64 mac_tx_mcast_pkts; | |
1339 | u64 mac_tx_bcast_pkts; | |
1340 | u64 mac_tx_pause_cnt; | |
1341 | u64 mac_tx_ctrl_pkt; | |
1342 | u64 mac_tx_lt_64b_pkts; | |
1343 | u64 mac_tx_lt_127b_pkts; | |
1344 | u64 mac_tx_lt_255b_pkts; | |
1345 | u64 mac_tx_lt_511b_pkts; | |
1346 | u64 mac_tx_lt_1023b_pkts; | |
1347 | u64 mac_tx_lt_1518b_pkts; | |
1348 | u64 mac_tx_gt_1518b_pkts; | |
1349 | u64 rsvd1[3]; | |
1350 | u64 mac_rx_frames; | |
1351 | u64 mac_rx_bytes; | |
1352 | u64 mac_rx_mcast_pkts; | |
1353 | u64 mac_rx_bcast_pkts; | |
1354 | u64 mac_rx_pause_cnt; | |
1355 | u64 mac_rx_ctrl_pkt; | |
1356 | u64 mac_rx_lt_64b_pkts; | |
1357 | u64 mac_rx_lt_127b_pkts; | |
1358 | u64 mac_rx_lt_255b_pkts; | |
1359 | u64 mac_rx_lt_511b_pkts; | |
1360 | u64 mac_rx_lt_1023b_pkts; | |
1361 | u64 mac_rx_lt_1518b_pkts; | |
1362 | u64 mac_rx_gt_1518b_pkts; | |
1363 | u64 rsvd2[3]; | |
1364 | u64 mac_rx_length_error; | |
1365 | u64 mac_rx_length_small; | |
1366 | u64 mac_rx_length_large; | |
1367 | u64 mac_rx_jabber; | |
1368 | u64 mac_rx_dropped; | |
1369 | u64 mac_rx_crc_error; | |
1370 | u64 mac_align_error; | |
1371 | }; | |
1372 | ||
1373 | struct qlcnic_esw_stats_le { | |
b6021212 AKS |
1374 | __le16 context_id; |
1375 | __le16 version; | |
1376 | __le16 size; | |
1377 | __le16 unused; | |
1378 | __le64 unicast_frames; | |
1379 | __le64 multicast_frames; | |
1380 | __le64 broadcast_frames; | |
1381 | __le64 dropped_frames; | |
1382 | __le64 errors; | |
1383 | __le64 local_frames; | |
1384 | __le64 numbytes; | |
1385 | __le64 rsvd[3]; | |
b1fc6d3c | 1386 | } __packed; |
b6021212 | 1387 | |
63507592 SS |
1388 | struct __qlcnic_esw_statistics { |
1389 | u16 context_id; | |
1390 | u16 version; | |
1391 | u16 size; | |
1392 | u16 unused; | |
1393 | u64 unicast_frames; | |
1394 | u64 multicast_frames; | |
1395 | u64 broadcast_frames; | |
1396 | u64 dropped_frames; | |
1397 | u64 errors; | |
1398 | u64 local_frames; | |
1399 | u64 numbytes; | |
1400 | u64 rsvd[3]; | |
1401 | }; | |
1402 | ||
b6021212 AKS |
1403 | struct qlcnic_esw_statistics { |
1404 | struct __qlcnic_esw_statistics rx; | |
1405 | struct __qlcnic_esw_statistics tx; | |
1406 | }; | |
1407 | ||
18f2f616 | 1408 | #define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed |
9d6a6440 AC |
1409 | #define QLCNIC_ENABLE_FW_DUMP 0xaddfeed |
1410 | #define QLCNIC_DISABLE_FW_DUMP 0xbadfeed | |
3d46512c | 1411 | #define QLCNIC_FORCE_FW_RESET 0xdeaddead |
b43e5ee7 SC |
1412 | #define QLCNIC_SET_QUIESCENT 0xadd00010 |
1413 | #define QLCNIC_RESET_QUIESCENT 0xadd00020 | |
18f2f616 | 1414 | |
7777de9a | 1415 | struct _cdrp_cmd { |
7e2cf4fe SC |
1416 | u32 num; |
1417 | u32 *arg; | |
7777de9a AC |
1418 | }; |
1419 | ||
1420 | struct qlcnic_cmd_args { | |
e5c4e6c6 MC |
1421 | struct completion completion; |
1422 | struct list_head list; | |
1423 | struct _cdrp_cmd req; | |
1424 | struct _cdrp_cmd rsp; | |
1425 | atomic_t rsp_status; | |
1426 | int pay_size; | |
1427 | u32 rsp_opcode; | |
1428 | u32 total_cmds; | |
1429 | u32 op_type; | |
1430 | u32 type; | |
1431 | u32 cmd_op; | |
1432 | u32 *hdr; /* Back channel message header */ | |
1433 | u32 *pay; /* Back channel message payload */ | |
1434 | u8 func_num; | |
7777de9a AC |
1435 | }; |
1436 | ||
18f2f616 | 1437 | int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter); |
7e610caa | 1438 | int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config); |
af19b491 AKS |
1439 | int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data); |
1440 | int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data); | |
897e8c7c DP |
1441 | void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *); |
1442 | void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64); | |
1443 | ||
1444 | #define ADDR_IN_RANGE(addr, low, high) \ | |
1445 | (((addr) < (high)) && ((addr) >= (low))) | |
af19b491 | 1446 | |
4bd8e738 HM |
1447 | #define QLCRD32(adapter, off, err) \ |
1448 | (adapter->ahw->hw_ops->read_reg)(adapter, off, err) | |
7e2cf4fe | 1449 | |
af19b491 | 1450 | #define QLCWR32(adapter, off, val) \ |
7e2cf4fe | 1451 | adapter->ahw->hw_ops->write_reg(adapter, off, val) |
af19b491 AKS |
1452 | |
1453 | int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32); | |
1454 | void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int); | |
1455 | ||
1456 | #define qlcnic_rom_lock(a) \ | |
1457 | qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID) | |
1458 | #define qlcnic_rom_unlock(a) \ | |
1459 | qlcnic_pcie_sem_unlock((a), 2) | |
1460 | #define qlcnic_phy_lock(a) \ | |
1461 | qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID) | |
1462 | #define qlcnic_phy_unlock(a) \ | |
1463 | qlcnic_pcie_sem_unlock((a), 3) | |
af19b491 AKS |
1464 | #define qlcnic_sw_lock(a) \ |
1465 | qlcnic_pcie_sem_lock((a), 6, 0) | |
1466 | #define qlcnic_sw_unlock(a) \ | |
1467 | qlcnic_pcie_sem_unlock((a), 6) | |
1468 | #define crb_win_lock(a) \ | |
1469 | qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID) | |
1470 | #define crb_win_unlock(a) \ | |
1471 | qlcnic_pcie_sem_unlock((a), 7) | |
1472 | ||
728a98b8 SC |
1473 | #define __QLCNIC_MAX_LED_RATE 0xf |
1474 | #define __QLCNIC_MAX_LED_STATE 0x2 | |
1475 | ||
58634e74 SC |
1476 | #define MAX_CTL_CHECK 1000 |
1477 | ||
af19b491 | 1478 | int qlcnic_wol_supported(struct qlcnic_adapter *adapter); |
b5e5492c AKS |
1479 | void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter); |
1480 | void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter); | |
18f2f616 | 1481 | int qlcnic_dump_fw(struct qlcnic_adapter *); |
890b6e02 SS |
1482 | int qlcnic_enable_fw_dump_state(struct qlcnic_adapter *); |
1483 | bool qlcnic_check_fw_dump_state(struct qlcnic_adapter *); | |
4460f2e8 PP |
1484 | pci_ers_result_t qlcnic_82xx_io_error_detected(struct pci_dev *, |
1485 | pci_channel_state_t); | |
1486 | pci_ers_result_t qlcnic_82xx_io_slot_reset(struct pci_dev *); | |
1487 | void qlcnic_82xx_io_resume(struct pci_dev *); | |
af19b491 AKS |
1488 | |
1489 | /* Functions from qlcnic_init.c */ | |
13159183 | 1490 | void qlcnic_schedule_work(struct qlcnic_adapter *, work_func_t, int); |
af19b491 AKS |
1491 | int qlcnic_load_firmware(struct qlcnic_adapter *adapter); |
1492 | int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter); | |
1493 | void qlcnic_request_firmware(struct qlcnic_adapter *adapter); | |
1494 | void qlcnic_release_firmware(struct qlcnic_adapter *adapter); | |
1495 | int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter); | |
b3a24649 | 1496 | int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter); |
8f891387 | 1497 | int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter); |
af19b491 | 1498 | |
18f2f616 | 1499 | int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp); |
af19b491 AKS |
1500 | int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr, |
1501 | u8 *bytes, size_t size); | |
1502 | int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter); | |
1503 | void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter); | |
1504 | ||
15087c2b | 1505 | void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *, u32); |
af19b491 AKS |
1506 | |
1507 | int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter); | |
1508 | void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter); | |
1509 | ||
8a15ad1f AKS |
1510 | int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter); |
1511 | void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter); | |
1512 | ||
1513 | void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter); | |
af19b491 | 1514 | void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter); |
012ec812 HM |
1515 | void qlcnic_release_tx_buffers(struct qlcnic_adapter *, |
1516 | struct qlcnic_host_tx_ring *); | |
af19b491 | 1517 | |
d4066833 | 1518 | int qlcnic_check_fw_status(struct qlcnic_adapter *adapter); |
af19b491 | 1519 | void qlcnic_watchdog_task(struct work_struct *work); |
b1fc6d3c | 1520 | void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, |
4be41e92 | 1521 | struct qlcnic_host_rds_ring *rds_ring, u8 ring_id); |
af19b491 AKS |
1522 | int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max); |
1523 | void qlcnic_set_multi(struct net_device *netdev); | |
91b7282b RB |
1524 | void __qlcnic_set_multi(struct net_device *, u16); |
1525 | int qlcnic_nic_add_mac(struct qlcnic_adapter *, const u8 *, u16); | |
fe1adc6b | 1526 | int qlcnic_nic_del_mac(struct qlcnic_adapter *, const u8 *); |
91b7282b | 1527 | void qlcnic_82xx_free_mac_list(struct qlcnic_adapter *adapter); |
07a251c8 | 1528 | int qlcnic_82xx_read_phys_port_id(struct qlcnic_adapter *); |
af19b491 AKS |
1529 | |
1530 | int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu); | |
8af3f33d | 1531 | int qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter *, u32); |
af19b491 | 1532 | int qlcnic_change_mtu(struct net_device *netdev, int new_mtu); |
c8f44aff MM |
1533 | netdev_features_t qlcnic_fix_features(struct net_device *netdev, |
1534 | netdev_features_t features); | |
1535 | int qlcnic_set_features(struct net_device *netdev, netdev_features_t features); | |
2e9d722d | 1536 | int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable); |
af19b491 | 1537 | int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter); |
5ad6ff9d | 1538 | void qlcnic_update_cmd_producer(struct qlcnic_host_tx_ring *); |
22c8c934 SC |
1539 | |
1540 | /* Functions from qlcnic_ethtool.c */ | |
ba4468db JK |
1541 | int qlcnic_check_loopback_buff(unsigned char *, u8 []); |
1542 | int qlcnic_do_lb_test(struct qlcnic_adapter *, u8); | |
1543 | int qlcnic_loopback_test(struct net_device *, u8); | |
af19b491 AKS |
1544 | |
1545 | /* Functions from qlcnic_main.c */ | |
1546 | int qlcnic_reset_context(struct qlcnic_adapter *); | |
7eb9855d AKS |
1547 | void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings); |
1548 | int qlcnic_diag_alloc_res(struct net_device *netdev, int test); | |
cdaff185 | 1549 | netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev); |
aa4a1f7d | 1550 | int qlcnic_set_max_rss(struct qlcnic_adapter *, u8, int); |
6389b76d | 1551 | int qlcnic_validate_max_rss(struct qlcnic_adapter *, __u32); |
80b17be7 | 1552 | int qlcnic_validate_max_tx_rings(struct qlcnic_adapter *, u32 txq); |
e5dcf6dc | 1553 | void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter); |
52e493d0 | 1554 | void qlcnic_82xx_set_mac_filter_count(struct qlcnic_adapter *); |
7f966452 | 1555 | int qlcnic_enable_msix(struct qlcnic_adapter *, u32); |
8af3f33d | 1556 | void qlcnic_set_drv_version(struct qlcnic_adapter *); |
af19b491 | 1557 | |
2e9d722d | 1558 | /* eSwitch management functions */ |
4e8acb01 RB |
1559 | int qlcnic_config_switch_port(struct qlcnic_adapter *, |
1560 | struct qlcnic_esw_func_cfg *); | |
629263ac | 1561 | |
4e8acb01 RB |
1562 | int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *, |
1563 | struct qlcnic_esw_func_cfg *); | |
2e9d722d | 1564 | int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8); |
b6021212 AKS |
1565 | int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8, |
1566 | struct __qlcnic_esw_statistics *); | |
1567 | int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8, | |
1568 | struct __qlcnic_esw_statistics *); | |
1569 | int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8); | |
54a8997c | 1570 | int qlcnic_get_mac_stats(struct qlcnic_adapter *, struct qlcnic_mac_statistics *); |
2e9d722d | 1571 | |
7e2cf4fe | 1572 | void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd); |
7e2cf4fe | 1573 | |
c70001a9 SC |
1574 | int qlcnic_alloc_sds_rings(struct qlcnic_recv_context *, int); |
1575 | void qlcnic_free_sds_rings(struct qlcnic_recv_context *); | |
7f966452 | 1576 | void qlcnic_advert_link_change(struct qlcnic_adapter *, int); |
c70001a9 SC |
1577 | void qlcnic_free_tx_rings(struct qlcnic_adapter *); |
1578 | int qlcnic_alloc_tx_rings(struct qlcnic_adapter *, struct net_device *); | |
012ec812 | 1579 | void qlcnic_dump_mbx(struct qlcnic_adapter *, struct qlcnic_cmd_args *); |
c70001a9 | 1580 | |
ec079a07 SC |
1581 | void qlcnic_create_sysfs_entries(struct qlcnic_adapter *adapter); |
1582 | void qlcnic_remove_sysfs_entries(struct qlcnic_adapter *adapter); | |
1583 | void qlcnic_create_diag_entries(struct qlcnic_adapter *adapter); | |
1584 | void qlcnic_remove_diag_entries(struct qlcnic_adapter *adapter); | |
7e2cf4fe SC |
1585 | void qlcnic_82xx_add_sysfs(struct qlcnic_adapter *adapter); |
1586 | void qlcnic_82xx_remove_sysfs(struct qlcnic_adapter *adapter); | |
b938662d | 1587 | int qlcnic_82xx_get_settings(struct qlcnic_adapter *, struct ethtool_cmd *); |
7e2cf4fe | 1588 | |
ec079a07 SC |
1589 | int qlcnicvf_config_bridged_mode(struct qlcnic_adapter *, u32); |
1590 | int qlcnicvf_config_led(struct qlcnic_adapter *, u32, u32); | |
1591 | void qlcnic_set_vlan_config(struct qlcnic_adapter *, | |
1592 | struct qlcnic_esw_func_cfg *); | |
1593 | void qlcnic_set_eswitch_port_features(struct qlcnic_adapter *, | |
1594 | struct qlcnic_esw_func_cfg *); | |
629263ac SC |
1595 | |
1596 | void qlcnic_down(struct qlcnic_adapter *, struct net_device *); | |
1597 | int qlcnic_up(struct qlcnic_adapter *, struct net_device *); | |
319ecf12 SC |
1598 | void __qlcnic_down(struct qlcnic_adapter *, struct net_device *); |
1599 | void qlcnic_detach(struct qlcnic_adapter *); | |
1600 | void qlcnic_teardown_intr(struct qlcnic_adapter *); | |
1601 | int qlcnic_attach(struct qlcnic_adapter *); | |
1602 | int __qlcnic_up(struct qlcnic_adapter *, struct net_device *); | |
1603 | void qlcnic_restore_indev_addr(struct net_device *, unsigned long); | |
1604 | ||
629263ac | 1605 | int qlcnic_check_temp(struct qlcnic_adapter *); |
d71170fb SC |
1606 | int qlcnic_init_pci_info(struct qlcnic_adapter *); |
1607 | int qlcnic_set_default_offload_settings(struct qlcnic_adapter *); | |
1608 | int qlcnic_reset_npar_config(struct qlcnic_adapter *); | |
1609 | int qlcnic_set_eswitch_port_config(struct qlcnic_adapter *); | |
f80bc8fe | 1610 | void qlcnic_add_lb_filter(struct qlcnic_adapter *, struct sk_buff *, int, u16); |
487042af | 1611 | int qlcnic_get_beacon_state(struct qlcnic_adapter *, u8 *); |
02feda17 | 1612 | int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter); |
f8468331 RB |
1613 | int qlcnic_read_mac_addr(struct qlcnic_adapter *); |
1614 | int qlcnic_setup_netdev(struct qlcnic_adapter *, struct net_device *, int); | |
147a9088 SS |
1615 | void qlcnic_set_netdev_features(struct qlcnic_adapter *, |
1616 | struct qlcnic_esw_func_cfg *); | |
e8b508ef | 1617 | void qlcnic_sriov_vf_schedule_multi(struct net_device *); |
91b7282b | 1618 | void qlcnic_vf_add_mc_list(struct net_device *, u16); |
f8468331 | 1619 | |
af19b491 AKS |
1620 | /* |
1621 | * QLOGIC Board information | |
1622 | */ | |
1623 | ||
02420be6 | 1624 | #define QLCNIC_MAX_BOARD_NAME_LEN 100 |
22999798 | 1625 | struct qlcnic_board_info { |
af19b491 AKS |
1626 | unsigned short vendor; |
1627 | unsigned short device; | |
1628 | unsigned short sub_vendor; | |
1629 | unsigned short sub_device; | |
1630 | char short_name[QLCNIC_MAX_BOARD_NAME_LEN]; | |
1631 | }; | |
1632 | ||
af19b491 AKS |
1633 | static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring) |
1634 | { | |
036d61f0 | 1635 | if (likely(tx_ring->producer < tx_ring->sw_consumer)) |
af19b491 AKS |
1636 | return tx_ring->sw_consumer - tx_ring->producer; |
1637 | else | |
1638 | return tx_ring->sw_consumer + tx_ring->num_desc - | |
1639 | tx_ring->producer; | |
1640 | } | |
1641 | ||
012ec812 HM |
1642 | static inline int qlcnic_set_real_num_queues(struct qlcnic_adapter *adapter, |
1643 | struct net_device *netdev) | |
1644 | { | |
1645 | int err, tx_q; | |
1646 | ||
1647 | tx_q = adapter->max_drv_tx_rings; | |
1648 | ||
1649 | netdev->num_tx_queues = tx_q; | |
1650 | netdev->real_num_tx_queues = tx_q; | |
1651 | ||
1652 | err = netif_set_real_num_tx_queues(netdev, tx_q); | |
1653 | if (err) | |
1654 | dev_err(&adapter->pdev->dev, "failed to set %d Tx queues\n", | |
1655 | tx_q); | |
1656 | else | |
1657 | dev_info(&adapter->pdev->dev, "set %d Tx queues\n", tx_q); | |
1658 | ||
1659 | return err; | |
1660 | } | |
1661 | ||
7e2cf4fe SC |
1662 | struct qlcnic_nic_template { |
1663 | int (*config_bridged_mode) (struct qlcnic_adapter *, u32); | |
1664 | int (*config_led) (struct qlcnic_adapter *, u32, u32); | |
1665 | int (*start_firmware) (struct qlcnic_adapter *); | |
1666 | int (*init_driver) (struct qlcnic_adapter *); | |
1667 | void (*request_reset) (struct qlcnic_adapter *, u32); | |
1668 | void (*cancel_idc_work) (struct qlcnic_adapter *); | |
1669 | int (*napi_add)(struct qlcnic_adapter *, struct net_device *); | |
4be41e92 | 1670 | void (*napi_del)(struct qlcnic_adapter *); |
7e2cf4fe SC |
1671 | void (*config_ipaddr)(struct qlcnic_adapter *, __be32, int); |
1672 | irqreturn_t (*clear_legacy_intr)(struct qlcnic_adapter *); | |
486a5bc7 RB |
1673 | int (*shutdown)(struct pci_dev *); |
1674 | int (*resume)(struct qlcnic_adapter *); | |
7e2cf4fe SC |
1675 | }; |
1676 | ||
e5c4e6c6 MC |
1677 | struct qlcnic_mbx_ops { |
1678 | int (*enqueue_cmd) (struct qlcnic_adapter *, | |
1679 | struct qlcnic_cmd_args *, unsigned long *); | |
1680 | void (*dequeue_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); | |
1681 | void (*decode_resp) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); | |
1682 | void (*encode_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); | |
1683 | void (*nofity_fw) (struct qlcnic_adapter *, u8); | |
1684 | }; | |
1685 | ||
1686 | int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *); | |
1687 | void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *); | |
1688 | void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx); | |
1689 | void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx); | |
1690 | ||
7e2cf4fe SC |
1691 | /* Adapter hardware abstraction */ |
1692 | struct qlcnic_hardware_ops { | |
1693 | void (*read_crb) (struct qlcnic_adapter *, char *, loff_t, size_t); | |
1694 | void (*write_crb) (struct qlcnic_adapter *, char *, loff_t, size_t); | |
4bd8e738 | 1695 | int (*read_reg) (struct qlcnic_adapter *, ulong, int *); |
7e2cf4fe SC |
1696 | int (*write_reg) (struct qlcnic_adapter *, ulong, u32); |
1697 | void (*get_ocm_win) (struct qlcnic_hardware_context *); | |
07a251c8 | 1698 | int (*get_mac_address) (struct qlcnic_adapter *, u8 *, u8); |
aa4a1f7d | 1699 | int (*setup_intr) (struct qlcnic_adapter *, u8, int); |
7e2cf4fe SC |
1700 | int (*alloc_mbx_args)(struct qlcnic_cmd_args *, |
1701 | struct qlcnic_adapter *, u32); | |
1702 | int (*mbx_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); | |
1703 | void (*get_func_no) (struct qlcnic_adapter *); | |
1704 | int (*api_lock) (struct qlcnic_adapter *); | |
1705 | void (*api_unlock) (struct qlcnic_adapter *); | |
1706 | void (*add_sysfs) (struct qlcnic_adapter *); | |
1707 | void (*remove_sysfs) (struct qlcnic_adapter *); | |
1708 | void (*process_lb_rcv_ring_diag) (struct qlcnic_host_sds_ring *); | |
1709 | int (*create_rx_ctx) (struct qlcnic_adapter *); | |
1710 | int (*create_tx_ctx) (struct qlcnic_adapter *, | |
1711 | struct qlcnic_host_tx_ring *, int); | |
7cb03b23 RB |
1712 | void (*del_rx_ctx) (struct qlcnic_adapter *); |
1713 | void (*del_tx_ctx) (struct qlcnic_adapter *, | |
1714 | struct qlcnic_host_tx_ring *); | |
7e2cf4fe SC |
1715 | int (*setup_link_event) (struct qlcnic_adapter *, int); |
1716 | int (*get_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *, u8); | |
1717 | int (*get_pci_info) (struct qlcnic_adapter *, struct qlcnic_pci_info *); | |
1718 | int (*set_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *); | |
f80bc8fe | 1719 | int (*change_macvlan) (struct qlcnic_adapter *, u8*, u16, u8); |
7e2cf4fe SC |
1720 | void (*napi_enable) (struct qlcnic_adapter *); |
1721 | void (*napi_disable) (struct qlcnic_adapter *); | |
1722 | void (*config_intr_coal) (struct qlcnic_adapter *); | |
1723 | int (*config_rss) (struct qlcnic_adapter *, int); | |
1724 | int (*config_hw_lro) (struct qlcnic_adapter *, int); | |
1725 | int (*config_loopback) (struct qlcnic_adapter *, u8); | |
1726 | int (*clear_loopback) (struct qlcnic_adapter *, u8); | |
1727 | int (*config_promisc_mode) (struct qlcnic_adapter *, u32); | |
f80bc8fe | 1728 | void (*change_l2_filter) (struct qlcnic_adapter *, u64 *, u16); |
7e2cf4fe | 1729 | int (*get_board_info) (struct qlcnic_adapter *); |
52e493d0 | 1730 | void (*set_mac_filter_count) (struct qlcnic_adapter *); |
91b7282b | 1731 | void (*free_mac_list) (struct qlcnic_adapter *); |
07a251c8 | 1732 | int (*read_phys_port_id) (struct qlcnic_adapter *); |
4460f2e8 PP |
1733 | pci_ers_result_t (*io_error_detected) (struct pci_dev *, |
1734 | pci_channel_state_t); | |
1735 | pci_ers_result_t (*io_slot_reset) (struct pci_dev *); | |
1736 | void (*io_resume) (struct pci_dev *); | |
7e2cf4fe SC |
1737 | }; |
1738 | ||
1739 | extern struct qlcnic_nic_template qlcnic_vf_ops; | |
1740 | ||
1741 | static inline int qlcnic_start_firmware(struct qlcnic_adapter *adapter) | |
1742 | { | |
1743 | return adapter->nic_ops->start_firmware(adapter); | |
1744 | } | |
1745 | ||
1746 | static inline void qlcnic_read_crb(struct qlcnic_adapter *adapter, char *buf, | |
1747 | loff_t offset, size_t size) | |
1748 | { | |
1749 | adapter->ahw->hw_ops->read_crb(adapter, buf, offset, size); | |
1750 | } | |
1751 | ||
1752 | static inline void qlcnic_write_crb(struct qlcnic_adapter *adapter, char *buf, | |
1753 | loff_t offset, size_t size) | |
1754 | { | |
1755 | adapter->ahw->hw_ops->write_crb(adapter, buf, offset, size); | |
1756 | } | |
1757 | ||
7e2cf4fe SC |
1758 | static inline int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, |
1759 | ulong off, u32 data) | |
1760 | { | |
1761 | return adapter->ahw->hw_ops->write_reg(adapter, off, data); | |
1762 | } | |
1763 | ||
1764 | static inline int qlcnic_get_mac_address(struct qlcnic_adapter *adapter, | |
07a251c8 | 1765 | u8 *mac, u8 function) |
7e2cf4fe | 1766 | { |
07a251c8 | 1767 | return adapter->ahw->hw_ops->get_mac_address(adapter, mac, function); |
7e2cf4fe SC |
1768 | } |
1769 | ||
aa4a1f7d HM |
1770 | static inline int qlcnic_setup_intr(struct qlcnic_adapter *adapter, |
1771 | u8 num_intr, int txq) | |
7e2cf4fe | 1772 | { |
aa4a1f7d | 1773 | return adapter->ahw->hw_ops->setup_intr(adapter, num_intr, txq); |
7e2cf4fe SC |
1774 | } |
1775 | ||
1776 | static inline int qlcnic_alloc_mbx_args(struct qlcnic_cmd_args *mbx, | |
1777 | struct qlcnic_adapter *adapter, u32 arg) | |
1778 | { | |
1779 | return adapter->ahw->hw_ops->alloc_mbx_args(mbx, adapter, arg); | |
1780 | } | |
1781 | ||
1782 | static inline int qlcnic_issue_cmd(struct qlcnic_adapter *adapter, | |
1783 | struct qlcnic_cmd_args *cmd) | |
1784 | { | |
f8468331 RB |
1785 | if (adapter->ahw->hw_ops->mbx_cmd) |
1786 | return adapter->ahw->hw_ops->mbx_cmd(adapter, cmd); | |
1787 | ||
1788 | return -EIO; | |
7e2cf4fe SC |
1789 | } |
1790 | ||
1791 | static inline void qlcnic_get_func_no(struct qlcnic_adapter *adapter) | |
1792 | { | |
1793 | adapter->ahw->hw_ops->get_func_no(adapter); | |
1794 | } | |
1795 | ||
1796 | static inline int qlcnic_api_lock(struct qlcnic_adapter *adapter) | |
1797 | { | |
1798 | return adapter->ahw->hw_ops->api_lock(adapter); | |
1799 | } | |
1800 | ||
1801 | static inline void qlcnic_api_unlock(struct qlcnic_adapter *adapter) | |
1802 | { | |
1803 | adapter->ahw->hw_ops->api_unlock(adapter); | |
1804 | } | |
1805 | ||
1806 | static inline void qlcnic_add_sysfs(struct qlcnic_adapter *adapter) | |
1807 | { | |
f8468331 RB |
1808 | if (adapter->ahw->hw_ops->add_sysfs) |
1809 | adapter->ahw->hw_ops->add_sysfs(adapter); | |
7e2cf4fe SC |
1810 | } |
1811 | ||
1812 | static inline void qlcnic_remove_sysfs(struct qlcnic_adapter *adapter) | |
1813 | { | |
f8468331 RB |
1814 | if (adapter->ahw->hw_ops->remove_sysfs) |
1815 | adapter->ahw->hw_ops->remove_sysfs(adapter); | |
7e2cf4fe SC |
1816 | } |
1817 | ||
1818 | static inline void | |
1819 | qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring) | |
1820 | { | |
1821 | sds_ring->adapter->ahw->hw_ops->process_lb_rcv_ring_diag(sds_ring); | |
1822 | } | |
1823 | ||
1824 | static inline int qlcnic_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter) | |
1825 | { | |
1826 | return adapter->ahw->hw_ops->create_rx_ctx(adapter); | |
1827 | } | |
1828 | ||
1829 | static inline int qlcnic_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter, | |
1830 | struct qlcnic_host_tx_ring *ptr, | |
1831 | int ring) | |
1832 | { | |
1833 | return adapter->ahw->hw_ops->create_tx_ctx(adapter, ptr, ring); | |
1834 | } | |
1835 | ||
7cb03b23 RB |
1836 | static inline void qlcnic_fw_cmd_del_rx_ctx(struct qlcnic_adapter *adapter) |
1837 | { | |
1838 | return adapter->ahw->hw_ops->del_rx_ctx(adapter); | |
1839 | } | |
1840 | ||
1841 | static inline void qlcnic_fw_cmd_del_tx_ctx(struct qlcnic_adapter *adapter, | |
1842 | struct qlcnic_host_tx_ring *ptr) | |
1843 | { | |
1844 | return adapter->ahw->hw_ops->del_tx_ctx(adapter, ptr); | |
1845 | } | |
1846 | ||
7e2cf4fe SC |
1847 | static inline int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, |
1848 | int enable) | |
1849 | { | |
1850 | return adapter->ahw->hw_ops->setup_link_event(adapter, enable); | |
1851 | } | |
1852 | ||
1853 | static inline int qlcnic_get_nic_info(struct qlcnic_adapter *adapter, | |
1854 | struct qlcnic_info *info, u8 id) | |
1855 | { | |
1856 | return adapter->ahw->hw_ops->get_nic_info(adapter, info, id); | |
1857 | } | |
1858 | ||
1859 | static inline int qlcnic_get_pci_info(struct qlcnic_adapter *adapter, | |
1860 | struct qlcnic_pci_info *info) | |
1861 | { | |
1862 | return adapter->ahw->hw_ops->get_pci_info(adapter, info); | |
1863 | } | |
1864 | ||
1865 | static inline int qlcnic_set_nic_info(struct qlcnic_adapter *adapter, | |
1866 | struct qlcnic_info *info) | |
1867 | { | |
1868 | return adapter->ahw->hw_ops->set_nic_info(adapter, info); | |
1869 | } | |
1870 | ||
1871 | static inline int qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, | |
f80bc8fe | 1872 | u8 *addr, u16 id, u8 cmd) |
7e2cf4fe SC |
1873 | { |
1874 | return adapter->ahw->hw_ops->change_macvlan(adapter, addr, id, cmd); | |
1875 | } | |
1876 | ||
1877 | static inline int qlcnic_napi_add(struct qlcnic_adapter *adapter, | |
1878 | struct net_device *netdev) | |
1879 | { | |
1880 | return adapter->nic_ops->napi_add(adapter, netdev); | |
1881 | } | |
1882 | ||
4be41e92 SC |
1883 | static inline void qlcnic_napi_del(struct qlcnic_adapter *adapter) |
1884 | { | |
1885 | adapter->nic_ops->napi_del(adapter); | |
1886 | } | |
1887 | ||
7e2cf4fe SC |
1888 | static inline void qlcnic_napi_enable(struct qlcnic_adapter *adapter) |
1889 | { | |
1890 | adapter->ahw->hw_ops->napi_enable(adapter); | |
1891 | } | |
1892 | ||
486a5bc7 RB |
1893 | static inline int __qlcnic_shutdown(struct pci_dev *pdev) |
1894 | { | |
1895 | struct qlcnic_adapter *adapter = pci_get_drvdata(pdev); | |
1896 | ||
1897 | return adapter->nic_ops->shutdown(pdev); | |
1898 | } | |
1899 | ||
1900 | static inline int __qlcnic_resume(struct qlcnic_adapter *adapter) | |
1901 | { | |
1902 | return adapter->nic_ops->resume(adapter); | |
1903 | } | |
1904 | ||
7e2cf4fe SC |
1905 | static inline void qlcnic_napi_disable(struct qlcnic_adapter *adapter) |
1906 | { | |
1907 | adapter->ahw->hw_ops->napi_disable(adapter); | |
1908 | } | |
1909 | ||
1910 | static inline void qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter) | |
1911 | { | |
1912 | adapter->ahw->hw_ops->config_intr_coal(adapter); | |
1913 | } | |
1914 | ||
1915 | static inline int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable) | |
1916 | { | |
1917 | return adapter->ahw->hw_ops->config_rss(adapter, enable); | |
1918 | } | |
1919 | ||
1920 | static inline int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, | |
1921 | int enable) | |
1922 | { | |
1923 | return adapter->ahw->hw_ops->config_hw_lro(adapter, enable); | |
1924 | } | |
1925 | ||
1926 | static inline int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode) | |
1927 | { | |
1928 | return adapter->ahw->hw_ops->config_loopback(adapter, mode); | |
1929 | } | |
1930 | ||
1931 | static inline int qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode) | |
1932 | { | |
d09529e6 | 1933 | return adapter->ahw->hw_ops->clear_loopback(adapter, mode); |
7e2cf4fe SC |
1934 | } |
1935 | ||
1936 | static inline int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, | |
1937 | u32 mode) | |
1938 | { | |
1939 | return adapter->ahw->hw_ops->config_promisc_mode(adapter, mode); | |
1940 | } | |
1941 | ||
1942 | static inline void qlcnic_change_filter(struct qlcnic_adapter *adapter, | |
f80bc8fe | 1943 | u64 *addr, u16 id) |
7e2cf4fe SC |
1944 | { |
1945 | adapter->ahw->hw_ops->change_l2_filter(adapter, addr, id); | |
1946 | } | |
1947 | ||
1948 | static inline int qlcnic_get_board_info(struct qlcnic_adapter *adapter) | |
1949 | { | |
1950 | return adapter->ahw->hw_ops->get_board_info(adapter); | |
1951 | } | |
1952 | ||
91b7282b RB |
1953 | static inline void qlcnic_free_mac_list(struct qlcnic_adapter *adapter) |
1954 | { | |
1955 | return adapter->ahw->hw_ops->free_mac_list(adapter); | |
1956 | } | |
1957 | ||
52e493d0 JK |
1958 | static inline void qlcnic_set_mac_filter_count(struct qlcnic_adapter *adapter) |
1959 | { | |
e9a355a9 SC |
1960 | if (adapter->ahw->hw_ops->set_mac_filter_count) |
1961 | adapter->ahw->hw_ops->set_mac_filter_count(adapter); | |
52e493d0 JK |
1962 | } |
1963 | ||
07a251c8 SS |
1964 | static inline void qlcnic_read_phys_port_id(struct qlcnic_adapter *adapter) |
1965 | { | |
1966 | if (adapter->ahw->hw_ops->read_phys_port_id) | |
1967 | adapter->ahw->hw_ops->read_phys_port_id(adapter); | |
1968 | } | |
1969 | ||
7e2cf4fe SC |
1970 | static inline void qlcnic_dev_request_reset(struct qlcnic_adapter *adapter, |
1971 | u32 key) | |
1972 | { | |
f8468331 RB |
1973 | if (adapter->nic_ops->request_reset) |
1974 | adapter->nic_ops->request_reset(adapter, key); | |
7e2cf4fe SC |
1975 | } |
1976 | ||
1977 | static inline void qlcnic_cancel_idc_work(struct qlcnic_adapter *adapter) | |
1978 | { | |
f8468331 RB |
1979 | if (adapter->nic_ops->cancel_idc_work) |
1980 | adapter->nic_ops->cancel_idc_work(adapter); | |
7e2cf4fe SC |
1981 | } |
1982 | ||
1983 | static inline irqreturn_t | |
1984 | qlcnic_clear_legacy_intr(struct qlcnic_adapter *adapter) | |
1985 | { | |
1986 | return adapter->nic_ops->clear_legacy_intr(adapter); | |
1987 | } | |
1988 | ||
1989 | static inline int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, | |
1990 | u32 rate) | |
1991 | { | |
1992 | return adapter->nic_ops->config_led(adapter, state, rate); | |
1993 | } | |
1994 | ||
1995 | static inline void qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, | |
1996 | __be32 ip, int cmd) | |
1997 | { | |
1998 | adapter->nic_ops->config_ipaddr(adapter, ip, cmd); | |
1999 | } | |
2000 | ||
012ec812 HM |
2001 | static inline bool qlcnic_check_multi_tx(struct qlcnic_adapter *adapter) |
2002 | { | |
2003 | return test_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state); | |
2004 | } | |
2005 | ||
2006 | static inline void qlcnic_disable_multi_tx(struct qlcnic_adapter *adapter) | |
2007 | { | |
2008 | test_and_clear_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state); | |
2009 | adapter->max_drv_tx_rings = 1; | |
2010 | } | |
2011 | ||
2012 | /* When operating in a muti tx mode, driver needs to write 0x1 | |
2013 | * to src register, instead of 0x0 to disable receiving interrupt. | |
2014 | */ | |
c70001a9 SC |
2015 | static inline void qlcnic_disable_int(struct qlcnic_host_sds_ring *sds_ring) |
2016 | { | |
012ec812 HM |
2017 | struct qlcnic_adapter *adapter = sds_ring->adapter; |
2018 | ||
2019 | if (qlcnic_check_multi_tx(adapter) && | |
c2c5e3a0 | 2020 | !adapter->ahw->diag_test && |
012ec812 HM |
2021 | (adapter->flags & QLCNIC_MSIX_ENABLED)) |
2022 | writel(0x1, sds_ring->crb_intr_mask); | |
2023 | else | |
2024 | writel(0, sds_ring->crb_intr_mask); | |
c70001a9 SC |
2025 | } |
2026 | ||
012ec812 HM |
2027 | /* When operating in a muti tx mode, driver needs to write 0x0 |
2028 | * to src register, instead of 0x1 to enable receiving interrupts. | |
2029 | */ | |
c70001a9 SC |
2030 | static inline void qlcnic_enable_int(struct qlcnic_host_sds_ring *sds_ring) |
2031 | { | |
2032 | struct qlcnic_adapter *adapter = sds_ring->adapter; | |
2033 | ||
012ec812 | 2034 | if (qlcnic_check_multi_tx(adapter) && |
c2c5e3a0 | 2035 | !adapter->ahw->diag_test && |
012ec812 HM |
2036 | (adapter->flags & QLCNIC_MSIX_ENABLED)) |
2037 | writel(0, sds_ring->crb_intr_mask); | |
2038 | else | |
2039 | writel(0x1, sds_ring->crb_intr_mask); | |
c70001a9 SC |
2040 | |
2041 | if (!QLCNIC_IS_MSI_FAMILY(adapter)) | |
2042 | writel(0xfbff, adapter->tgt_mask_reg); | |
2043 | } | |
2044 | ||
4690a7e4 SC |
2045 | static inline int qlcnic_get_diag_lock(struct qlcnic_adapter *adapter) |
2046 | { | |
2047 | return test_and_set_bit(__QLCNIC_DIAG_MODE, &adapter->state); | |
2048 | } | |
2049 | ||
2050 | static inline void qlcnic_release_diag_lock(struct qlcnic_adapter *adapter) | |
2051 | { | |
2052 | clear_bit(__QLCNIC_DIAG_MODE, &adapter->state); | |
2053 | } | |
2054 | ||
099907fa SC |
2055 | static inline int qlcnic_check_diag_status(struct qlcnic_adapter *adapter) |
2056 | { | |
2057 | return test_bit(__QLCNIC_DIAG_MODE, &adapter->state); | |
2058 | } | |
2059 | ||
d1a1105e | 2060 | extern const struct ethtool_ops qlcnic_sriov_vf_ethtool_ops; |
af19b491 | 2061 | extern const struct ethtool_ops qlcnic_ethtool_ops; |
b43e5ee7 | 2062 | extern const struct ethtool_ops qlcnic_ethtool_failed_ops; |
af19b491 | 2063 | |
65b5b420 | 2064 | #define QLCDB(adapter, lvl, _fmt, _args...) do { \ |
79788450 | 2065 | if (NETIF_MSG_##lvl & adapter->ahw->msg_enable) \ |
65b5b420 AKS |
2066 | printk(KERN_INFO "%s: %s: " _fmt, \ |
2067 | dev_name(&adapter->pdev->dev), \ | |
2068 | __func__, ##_args); \ | |
2069 | } while (0) | |
2070 | ||
15ca140f MC |
2071 | #define PCI_DEVICE_ID_QLOGIC_QLE824X 0x8020 |
2072 | #define PCI_DEVICE_ID_QLOGIC_QLE834X 0x8030 | |
f8468331 | 2073 | #define PCI_DEVICE_ID_QLOGIC_VF_QLE834X 0x8430 |
15ca140f MC |
2074 | #define PCI_DEVICE_ID_QLOGIC_QLE844X 0x8040 |
2075 | #define PCI_DEVICE_ID_QLOGIC_VF_QLE844X 0x8440 | |
f8468331 | 2076 | |
97ee45eb SC |
2077 | static inline bool qlcnic_82xx_check(struct qlcnic_adapter *adapter) |
2078 | { | |
2079 | unsigned short device = adapter->pdev->device; | |
2080 | return (device == PCI_DEVICE_ID_QLOGIC_QLE824X) ? true : false; | |
2081 | } | |
2082 | ||
991ca269 MC |
2083 | static inline bool qlcnic_84xx_check(struct qlcnic_adapter *adapter) |
2084 | { | |
2085 | unsigned short device = adapter->pdev->device; | |
2086 | ||
2087 | return ((device == PCI_DEVICE_ID_QLOGIC_QLE844X) || | |
2088 | (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X)) ? true : false; | |
2089 | } | |
2090 | ||
7f966452 SC |
2091 | static inline bool qlcnic_83xx_check(struct qlcnic_adapter *adapter) |
2092 | { | |
2093 | unsigned short device = adapter->pdev->device; | |
f8468331 RB |
2094 | bool status; |
2095 | ||
2096 | status = ((device == PCI_DEVICE_ID_QLOGIC_QLE834X) || | |
15ca140f MC |
2097 | (device == PCI_DEVICE_ID_QLOGIC_QLE844X) || |
2098 | (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X) || | |
f8468331 RB |
2099 | (device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X)) ? true : false; |
2100 | ||
2101 | return status; | |
7f966452 SC |
2102 | } |
2103 | ||
02feda17 RB |
2104 | static inline bool qlcnic_sriov_pf_check(struct qlcnic_adapter *adapter) |
2105 | { | |
2106 | return (adapter->ahw->op_mode == QLCNIC_SRIOV_PF_FUNC) ? true : false; | |
2107 | } | |
7f966452 | 2108 | |
f8468331 RB |
2109 | static inline bool qlcnic_sriov_vf_check(struct qlcnic_adapter *adapter) |
2110 | { | |
2111 | unsigned short device = adapter->pdev->device; | |
15ca140f MC |
2112 | bool status; |
2113 | ||
2114 | status = ((device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) || | |
2115 | (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X)) ? true : false; | |
f8468331 | 2116 | |
15ca140f | 2117 | return status; |
f8468331 | 2118 | } |
14d385b9 SC |
2119 | |
2120 | static inline int qlcnic_dcb_get_hw_capability(struct qlcnic_adapter *adapter) | |
2121 | { | |
2122 | struct qlcnic_dcb *dcb = adapter->dcb; | |
2123 | ||
2124 | if (dcb && dcb->ops->get_hw_capability) | |
2125 | return dcb->ops->get_hw_capability(adapter); | |
2126 | ||
2127 | return 0; | |
2128 | } | |
2129 | ||
2130 | static inline void qlcnic_dcb_free(struct qlcnic_adapter *adapter) | |
2131 | { | |
2132 | struct qlcnic_dcb *dcb = adapter->dcb; | |
2133 | ||
2134 | if (dcb && dcb->ops->free) | |
2135 | dcb->ops->free(adapter); | |
2136 | } | |
2137 | ||
2138 | static inline int qlcnic_dcb_attach(struct qlcnic_adapter *adapter) | |
2139 | { | |
2140 | struct qlcnic_dcb *dcb = adapter->dcb; | |
2141 | ||
2142 | if (dcb && dcb->ops->attach) | |
2143 | return dcb->ops->attach(adapter); | |
2144 | ||
2145 | return 0; | |
2146 | } | |
2147 | ||
2148 | static inline int | |
2149 | qlcnic_dcb_query_hw_capability(struct qlcnic_adapter *adapter, char *buf) | |
2150 | { | |
2151 | struct qlcnic_dcb *dcb = adapter->dcb; | |
2152 | ||
2153 | if (dcb && dcb->ops->query_hw_capability) | |
2154 | return dcb->ops->query_hw_capability(adapter, buf); | |
2155 | ||
2156 | return 0; | |
2157 | } | |
2158 | ||
2159 | static inline void qlcnic_dcb_get_info(struct qlcnic_adapter *adapter) | |
2160 | { | |
2161 | struct qlcnic_dcb *dcb = adapter->dcb; | |
2162 | ||
2163 | if (dcb && dcb->ops->get_info) | |
2164 | dcb->ops->get_info(adapter); | |
2165 | } | |
fb859ed6 SC |
2166 | |
2167 | static inline int | |
2168 | qlcnic_dcb_query_cee_param(struct qlcnic_adapter *adapter, char *buf, u8 type) | |
2169 | { | |
2170 | struct qlcnic_dcb *dcb = adapter->dcb; | |
2171 | ||
2172 | if (dcb && dcb->ops->query_cee_param) | |
2173 | return dcb->ops->query_cee_param(adapter, buf, type); | |
2174 | ||
2175 | return 0; | |
2176 | } | |
2177 | ||
2178 | static inline int qlcnic_dcb_get_cee_cfg(struct qlcnic_adapter *adapter) | |
2179 | { | |
2180 | struct qlcnic_dcb *dcb = adapter->dcb; | |
2181 | ||
2182 | if (dcb && dcb->ops->get_cee_cfg) | |
2183 | return dcb->ops->get_cee_cfg(adapter); | |
2184 | ||
2185 | return 0; | |
2186 | } | |
2d8ebcab SC |
2187 | |
2188 | static inline void | |
2189 | qlcnic_dcb_register_aen(struct qlcnic_adapter *adapter, u8 flag) | |
2190 | { | |
2191 | struct qlcnic_dcb *dcb = adapter->dcb; | |
2192 | ||
2193 | if (dcb && dcb->ops->register_aen) | |
2194 | dcb->ops->register_aen(adapter, flag); | |
2195 | } | |
2196 | ||
2197 | static inline void qlcnic_dcb_handle_aen(struct qlcnic_adapter *adapter, | |
2198 | void *msg) | |
2199 | { | |
2200 | struct qlcnic_dcb *dcb = adapter->dcb; | |
2201 | ||
2202 | if (dcb && dcb->ops->handle_aen) | |
2203 | dcb->ops->handle_aen(adapter, msg); | |
2204 | } | |
48365e48 SC |
2205 | |
2206 | static inline void qlcnic_dcb_init_dcbnl_ops(struct qlcnic_adapter *adapter) | |
2207 | { | |
2208 | struct qlcnic_dcb *dcb = adapter->dcb; | |
2209 | ||
2210 | if (dcb && dcb->ops->init_dcbnl_ops) | |
2211 | dcb->ops->init_dcbnl_ops(adapter); | |
2212 | } | |
af19b491 | 2213 | #endif /* __QLCNIC_H_ */ |