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951f3e9f | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
5a4faa87 RM |
2 | /* |
3 | * QLogic QLA3xxx NIC HBA Driver | |
4 | * Copyright (c) 2003-2006 QLogic Corporation | |
5a4faa87 RM |
5 | */ |
6 | #ifndef _QLA3XXX_H_ | |
7 | #define _QLA3XXX_H_ | |
8 | ||
9 | /* | |
10 | * IOCB Definitions... | |
11 | */ | |
12 | #pragma pack(1) | |
13 | ||
14 | #define OPCODE_OB_MAC_IOCB_FN0 0x01 | |
15 | #define OPCODE_OB_MAC_IOCB_FN2 0x21 | |
5a4faa87 | 16 | |
5a4faa87 | 17 | #define OPCODE_IB_MAC_IOCB 0xF9 |
bd36b0ac | 18 | #define OPCODE_IB_3032_MAC_IOCB 0x09 |
5a4faa87 | 19 | #define OPCODE_IB_IP_IOCB 0xFA |
bd36b0ac | 20 | #define OPCODE_IB_3032_IP_IOCB 0x0A |
5a4faa87 RM |
21 | |
22 | #define OPCODE_FUNC_ID_MASK 0x30 | |
23 | #define OUTBOUND_MAC_IOCB 0x01 /* plus function bits */ | |
5a4faa87 RM |
24 | |
25 | #define FN0_MA_BITS_MASK 0x00 | |
26 | #define FN1_MA_BITS_MASK 0x80 | |
27 | ||
28 | struct ob_mac_iocb_req { | |
29 | u8 opcode; | |
30 | u8 flags; | |
bd36b0ac RM |
31 | #define OB_MAC_IOCB_REQ_MA 0xe0 |
32 | #define OB_MAC_IOCB_REQ_F 0x10 | |
33 | #define OB_MAC_IOCB_REQ_X 0x08 | |
5a4faa87 RM |
34 | #define OB_MAC_IOCB_REQ_D 0x02 |
35 | #define OB_MAC_IOCB_REQ_I 0x01 | |
bd36b0ac RM |
36 | u8 flags1; |
37 | #define OB_3032MAC_IOCB_REQ_IC 0x04 | |
38 | #define OB_3032MAC_IOCB_REQ_TC 0x02 | |
39 | #define OB_3032MAC_IOCB_REQ_UC 0x01 | |
40 | u8 reserved0; | |
5a4faa87 | 41 | |
804d8541 | 42 | u32 transaction_id; /* opaque for hardware */ |
5a4faa87 | 43 | __le16 data_len; |
bd36b0ac RM |
44 | u8 ip_hdr_off; |
45 | u8 ip_hdr_len; | |
46 | __le32 reserved1; | |
5a4faa87 | 47 | __le32 reserved2; |
5a4faa87 RM |
48 | __le32 buf_addr0_low; |
49 | __le32 buf_addr0_high; | |
50 | __le32 buf_0_len; | |
51 | __le32 buf_addr1_low; | |
52 | __le32 buf_addr1_high; | |
53 | __le32 buf_1_len; | |
54 | __le32 buf_addr2_low; | |
55 | __le32 buf_addr2_high; | |
56 | __le32 buf_2_len; | |
bd36b0ac | 57 | __le32 reserved3; |
5a4faa87 | 58 | __le32 reserved4; |
5a4faa87 RM |
59 | }; |
60 | /* | |
61 | * The following constants define control bits for buffer | |
62 | * length fields for all IOCB's. | |
63 | */ | |
64 | #define OB_MAC_IOCB_REQ_E 0x80000000 /* Last valid buffer in list. */ | |
65 | #define OB_MAC_IOCB_REQ_C 0x40000000 /* points to an OAL. (continuation) */ | |
66 | #define OB_MAC_IOCB_REQ_L 0x20000000 /* Auburn local address pointer. */ | |
67 | #define OB_MAC_IOCB_REQ_R 0x10000000 /* 32-bit address pointer. */ | |
68 | ||
69 | struct ob_mac_iocb_rsp { | |
70 | u8 opcode; | |
71 | u8 flags; | |
72 | #define OB_MAC_IOCB_RSP_P 0x08 | |
bd36b0ac | 73 | #define OB_MAC_IOCB_RSP_L 0x04 |
5a4faa87 RM |
74 | #define OB_MAC_IOCB_RSP_S 0x02 |
75 | #define OB_MAC_IOCB_RSP_I 0x01 | |
76 | ||
77 | __le16 reserved0; | |
804d8541 | 78 | u32 transaction_id; /* opaque for hardware */ |
5a4faa87 RM |
79 | __le32 reserved1; |
80 | __le32 reserved2; | |
81 | }; | |
82 | ||
83 | struct ib_mac_iocb_rsp { | |
84 | u8 opcode; | |
bd36b0ac | 85 | #define IB_MAC_IOCB_RSP_V 0x80 |
5a4faa87 RM |
86 | u8 flags; |
87 | #define IB_MAC_IOCB_RSP_S 0x80 | |
88 | #define IB_MAC_IOCB_RSP_H1 0x40 | |
89 | #define IB_MAC_IOCB_RSP_H0 0x20 | |
90 | #define IB_MAC_IOCB_RSP_B 0x10 | |
91 | #define IB_MAC_IOCB_RSP_M 0x08 | |
92 | #define IB_MAC_IOCB_RSP_MA 0x07 | |
93 | ||
94 | __le16 length; | |
95 | __le32 reserved; | |
96 | __le32 ial_low; | |
97 | __le32 ial_high; | |
98 | ||
99 | }; | |
100 | ||
101 | struct ob_ip_iocb_req { | |
102 | u8 opcode; | |
103 | __le16 flags; | |
104 | #define OB_IP_IOCB_REQ_O 0x100 | |
105 | #define OB_IP_IOCB_REQ_H 0x008 | |
106 | #define OB_IP_IOCB_REQ_U 0x004 | |
107 | #define OB_IP_IOCB_REQ_D 0x002 | |
108 | #define OB_IP_IOCB_REQ_I 0x001 | |
109 | ||
110 | u8 reserved0; | |
111 | ||
112 | __le32 transaction_id; | |
113 | __le16 data_len; | |
114 | __le16 reserved1; | |
115 | __le32 hncb_ptr_low; | |
116 | __le32 hncb_ptr_high; | |
117 | __le32 buf_addr0_low; | |
118 | __le32 buf_addr0_high; | |
119 | __le32 buf_0_len; | |
120 | __le32 buf_addr1_low; | |
121 | __le32 buf_addr1_high; | |
122 | __le32 buf_1_len; | |
123 | __le32 buf_addr2_low; | |
124 | __le32 buf_addr2_high; | |
125 | __le32 buf_2_len; | |
126 | __le32 reserved2; | |
127 | __le32 reserved3; | |
128 | }; | |
129 | ||
130 | /* defines for BufferLength fields above */ | |
131 | #define OB_IP_IOCB_REQ_E 0x80000000 | |
132 | #define OB_IP_IOCB_REQ_C 0x40000000 | |
133 | #define OB_IP_IOCB_REQ_L 0x20000000 | |
134 | #define OB_IP_IOCB_REQ_R 0x10000000 | |
135 | ||
136 | struct ob_ip_iocb_rsp { | |
137 | u8 opcode; | |
138 | u8 flags; | |
bd36b0ac | 139 | #define OB_MAC_IOCB_RSP_H 0x10 |
5a4faa87 RM |
140 | #define OB_MAC_IOCB_RSP_E 0x08 |
141 | #define OB_MAC_IOCB_RSP_L 0x04 | |
142 | #define OB_MAC_IOCB_RSP_S 0x02 | |
143 | #define OB_MAC_IOCB_RSP_I 0x01 | |
144 | ||
145 | __le16 reserved0; | |
146 | __le32 transaction_id; | |
147 | __le32 reserved1; | |
148 | __le32 reserved2; | |
149 | }; | |
150 | ||
5a4faa87 RM |
151 | struct ib_ip_iocb_rsp { |
152 | u8 opcode; | |
bd36b0ac RM |
153 | #define IB_IP_IOCB_RSP_3032_V 0x80 |
154 | #define IB_IP_IOCB_RSP_3032_O 0x40 | |
155 | #define IB_IP_IOCB_RSP_3032_I 0x20 | |
156 | #define IB_IP_IOCB_RSP_3032_R 0x10 | |
5a4faa87 RM |
157 | u8 flags; |
158 | #define IB_IP_IOCB_RSP_S 0x80 | |
159 | #define IB_IP_IOCB_RSP_H1 0x40 | |
160 | #define IB_IP_IOCB_RSP_H0 0x20 | |
161 | #define IB_IP_IOCB_RSP_B 0x10 | |
162 | #define IB_IP_IOCB_RSP_M 0x08 | |
163 | #define IB_IP_IOCB_RSP_MA 0x07 | |
164 | ||
165 | __le16 length; | |
166 | __le16 checksum; | |
bd36b0ac RM |
167 | #define IB_IP_IOCB_RSP_3032_ICE 0x01 |
168 | #define IB_IP_IOCB_RSP_3032_CE 0x02 | |
169 | #define IB_IP_IOCB_RSP_3032_NUC 0x04 | |
170 | #define IB_IP_IOCB_RSP_3032_UDP 0x08 | |
171 | #define IB_IP_IOCB_RSP_3032_TCP 0x10 | |
172 | #define IB_IP_IOCB_RSP_3032_IPE 0x20 | |
5a4faa87 RM |
173 | __le16 reserved; |
174 | #define IB_IP_IOCB_RSP_R 0x01 | |
175 | __le32 ial_low; | |
176 | __le32 ial_high; | |
177 | }; | |
178 | ||
5a4faa87 RM |
179 | struct net_rsp_iocb { |
180 | u8 opcode; | |
181 | u8 flags; | |
182 | __le16 reserved0; | |
183 | __le32 reserved[3]; | |
184 | }; | |
185 | #pragma pack() | |
186 | ||
187 | /* | |
188 | * Register Definitions... | |
189 | */ | |
190 | #define PORT0_PHY_ADDRESS 0x1e00 | |
191 | #define PORT1_PHY_ADDRESS 0x1f00 | |
192 | ||
193 | #define ETHERNET_CRC_SIZE 4 | |
194 | ||
195 | #define MII_SCAN_REGISTER 0x00000001 | |
196 | ||
3efedf2e RM |
197 | #define PHY_ID_0_REG 2 |
198 | #define PHY_ID_1_REG 3 | |
199 | ||
200 | #define PHY_OUI_1_MASK 0xfc00 | |
201 | #define PHY_MODEL_MASK 0x03f0 | |
202 | ||
203 | /* Address for the Agere Phy */ | |
204 | #define MII_AGERE_ADDR_1 0x00001000 | |
205 | #define MII_AGERE_ADDR_2 0x00001100 | |
206 | ||
5a4faa87 RM |
207 | /* 32-bit ispControlStatus */ |
208 | enum { | |
209 | ISP_CONTROL_NP_MASK = 0x0003, | |
210 | ISP_CONTROL_NP_PCSR = 0x0000, | |
211 | ISP_CONTROL_NP_HMCR = 0x0001, | |
212 | ISP_CONTROL_NP_LRAMCR = 0x0002, | |
213 | ISP_CONTROL_NP_PSR = 0x0003, | |
214 | ISP_CONTROL_RI = 0x0008, | |
215 | ISP_CONTROL_CI = 0x0010, | |
216 | ISP_CONTROL_PI = 0x0020, | |
217 | ISP_CONTROL_IN = 0x0040, | |
218 | ISP_CONTROL_BE = 0x0080, | |
219 | ISP_CONTROL_FN_MASK = 0x0700, | |
220 | ISP_CONTROL_FN0_NET = 0x0400, | |
221 | ISP_CONTROL_FN0_SCSI = 0x0500, | |
222 | ISP_CONTROL_FN1_NET = 0x0600, | |
223 | ISP_CONTROL_FN1_SCSI = 0x0700, | |
224 | ISP_CONTROL_LINK_DN_0 = 0x0800, | |
225 | ISP_CONTROL_LINK_DN_1 = 0x1000, | |
226 | ISP_CONTROL_FSR = 0x2000, | |
227 | ISP_CONTROL_FE = 0x4000, | |
228 | ISP_CONTROL_SR = 0x8000, | |
229 | }; | |
230 | ||
231 | /* 32-bit ispInterruptMaskReg */ | |
232 | enum { | |
233 | ISP_IMR_ENABLE_INT = 0x0004, | |
234 | ISP_IMR_DISABLE_RESET_INT = 0x0008, | |
235 | ISP_IMR_DISABLE_CMPL_INT = 0x0010, | |
236 | ISP_IMR_DISABLE_PROC_INT = 0x0020, | |
237 | }; | |
238 | ||
239 | /* 32-bit serialPortInterfaceReg */ | |
240 | enum { | |
241 | ISP_SERIAL_PORT_IF_CLK = 0x0001, | |
242 | ISP_SERIAL_PORT_IF_CS = 0x0002, | |
243 | ISP_SERIAL_PORT_IF_D0 = 0x0004, | |
244 | ISP_SERIAL_PORT_IF_DI = 0x0008, | |
245 | ISP_NVRAM_MASK = (0x000F << 16), | |
246 | ISP_SERIAL_PORT_IF_WE = 0x0010, | |
247 | ISP_SERIAL_PORT_IF_NVR_MASK = 0x001F, | |
248 | ISP_SERIAL_PORT_IF_SCI = 0x0400, | |
249 | ISP_SERIAL_PORT_IF_SC0 = 0x0800, | |
250 | ISP_SERIAL_PORT_IF_SCE = 0x1000, | |
251 | ISP_SERIAL_PORT_IF_SDI = 0x2000, | |
252 | ISP_SERIAL_PORT_IF_SDO = 0x4000, | |
253 | ISP_SERIAL_PORT_IF_SDE = 0x8000, | |
254 | ISP_SERIAL_PORT_IF_I2C_MASK = 0xFC00, | |
255 | }; | |
256 | ||
257 | /* semaphoreReg */ | |
258 | enum { | |
259 | QL_RESOURCE_MASK_BASE_CODE = 0x7, | |
260 | QL_RESOURCE_BITS_BASE_CODE = 0x4, | |
261 | QL_DRVR_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 1), | |
262 | QL_DDR_RAM_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 4), | |
263 | QL_PHY_GIO_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 7), | |
264 | QL_NVRAM_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 10), | |
265 | QL_FLASH_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 13), | |
266 | QL_DRVR_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (1 + 16)), | |
267 | QL_DDR_RAM_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (4 + 16)), | |
268 | QL_PHY_GIO_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (7 + 16)), | |
269 | QL_NVRAM_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (10 + 16)), | |
270 | QL_FLASH_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (13 + 16)), | |
271 | }; | |
272 | ||
273 | /* | |
274 | * QL3XXX memory-mapped registers | |
275 | * QL3XXX has 4 "pages" of registers, each page occupying | |
276 | * 256 bytes. Each page has a "common" area at the start and then | |
277 | * page-specific registers after that. | |
278 | */ | |
279 | struct ql3xxx_common_registers { | |
280 | u32 MB0; /* Offset 0x00 */ | |
281 | u32 MB1; /* Offset 0x04 */ | |
282 | u32 MB2; /* Offset 0x08 */ | |
283 | u32 MB3; /* Offset 0x0c */ | |
284 | u32 MB4; /* Offset 0x10 */ | |
285 | u32 MB5; /* Offset 0x14 */ | |
286 | u32 MB6; /* Offset 0x18 */ | |
287 | u32 MB7; /* Offset 0x1c */ | |
288 | u32 flashBiosAddr; | |
289 | u32 flashBiosData; | |
290 | u32 ispControlStatus; | |
291 | u32 ispInterruptMaskReg; | |
292 | u32 serialPortInterfaceReg; | |
293 | u32 semaphoreReg; | |
294 | u32 reqQProducerIndex; | |
295 | u32 rspQConsumerIndex; | |
296 | ||
297 | u32 rxLargeQProducerIndex; | |
298 | u32 rxSmallQProducerIndex; | |
299 | u32 arcMadiCommand; | |
300 | u32 arcMadiData; | |
301 | }; | |
302 | ||
303 | enum { | |
304 | EXT_HW_CONFIG_SP_MASK = 0x0006, | |
305 | EXT_HW_CONFIG_SP_NONE = 0x0000, | |
306 | EXT_HW_CONFIG_SP_BYTE_PARITY = 0x0002, | |
307 | EXT_HW_CONFIG_SP_ECC = 0x0004, | |
308 | EXT_HW_CONFIG_SP_ECCx = 0x0006, | |
309 | EXT_HW_CONFIG_SIZE_MASK = 0x0060, | |
310 | EXT_HW_CONFIG_SIZE_128M = 0x0000, | |
311 | EXT_HW_CONFIG_SIZE_256M = 0x0020, | |
312 | EXT_HW_CONFIG_SIZE_512M = 0x0040, | |
313 | EXT_HW_CONFIG_SIZE_INVALID = 0x0060, | |
314 | EXT_HW_CONFIG_PD = 0x0080, | |
315 | EXT_HW_CONFIG_FW = 0x0200, | |
316 | EXT_HW_CONFIG_US = 0x0400, | |
317 | EXT_HW_CONFIG_DCS_MASK = 0x1800, | |
318 | EXT_HW_CONFIG_DCS_9MA = 0x0000, | |
319 | EXT_HW_CONFIG_DCS_15MA = 0x0800, | |
320 | EXT_HW_CONFIG_DCS_18MA = 0x1000, | |
321 | EXT_HW_CONFIG_DCS_24MA = 0x1800, | |
322 | EXT_HW_CONFIG_DDS_MASK = 0x6000, | |
323 | EXT_HW_CONFIG_DDS_9MA = 0x0000, | |
324 | EXT_HW_CONFIG_DDS_15MA = 0x2000, | |
325 | EXT_HW_CONFIG_DDS_18MA = 0x4000, | |
326 | EXT_HW_CONFIG_DDS_24MA = 0x6000, | |
327 | }; | |
328 | ||
329 | /* InternalChipConfig */ | |
330 | enum { | |
331 | INTERNAL_CHIP_DM = 0x0001, | |
332 | INTERNAL_CHIP_SD = 0x0002, | |
333 | INTERNAL_CHIP_RAP_MASK = 0x000C, | |
334 | INTERNAL_CHIP_RAP_RR = 0x0000, | |
335 | INTERNAL_CHIP_RAP_NRM = 0x0004, | |
336 | INTERNAL_CHIP_RAP_ERM = 0x0008, | |
337 | INTERNAL_CHIP_RAP_ERMx = 0x000C, | |
338 | INTERNAL_CHIP_WE = 0x0010, | |
339 | INTERNAL_CHIP_EF = 0x0020, | |
340 | INTERNAL_CHIP_FR = 0x0040, | |
341 | INTERNAL_CHIP_FW = 0x0080, | |
342 | INTERNAL_CHIP_FI = 0x0100, | |
343 | INTERNAL_CHIP_FT = 0x0200, | |
344 | }; | |
345 | ||
346 | /* portControl */ | |
347 | enum { | |
348 | PORT_CONTROL_DS = 0x0001, | |
349 | PORT_CONTROL_HH = 0x0002, | |
350 | PORT_CONTROL_EI = 0x0004, | |
351 | PORT_CONTROL_ET = 0x0008, | |
352 | PORT_CONTROL_EF = 0x0010, | |
353 | PORT_CONTROL_DRM = 0x0020, | |
354 | PORT_CONTROL_RLB = 0x0040, | |
355 | PORT_CONTROL_RCB = 0x0080, | |
356 | PORT_CONTROL_MAC = 0x0100, | |
357 | PORT_CONTROL_IPV = 0x0200, | |
358 | PORT_CONTROL_IFP = 0x0400, | |
359 | PORT_CONTROL_ITP = 0x0800, | |
360 | PORT_CONTROL_FI = 0x1000, | |
361 | PORT_CONTROL_DFP = 0x2000, | |
362 | PORT_CONTROL_OI = 0x4000, | |
363 | PORT_CONTROL_CC = 0x8000, | |
364 | }; | |
365 | ||
366 | /* portStatus */ | |
367 | enum { | |
368 | PORT_STATUS_SM0 = 0x0001, | |
369 | PORT_STATUS_SM1 = 0x0002, | |
370 | PORT_STATUS_X = 0x0008, | |
371 | PORT_STATUS_DL = 0x0080, | |
372 | PORT_STATUS_IC = 0x0200, | |
373 | PORT_STATUS_MRC = 0x0400, | |
374 | PORT_STATUS_NL = 0x0800, | |
375 | PORT_STATUS_REV_ID_MASK = 0x7000, | |
376 | PORT_STATUS_REV_ID_1 = 0x1000, | |
377 | PORT_STATUS_REV_ID_2 = 0x2000, | |
378 | PORT_STATUS_REV_ID_3 = 0x3000, | |
379 | PORT_STATUS_64 = 0x8000, | |
380 | PORT_STATUS_UP0 = 0x10000, | |
381 | PORT_STATUS_AC0 = 0x20000, | |
382 | PORT_STATUS_AE0 = 0x40000, | |
383 | PORT_STATUS_UP1 = 0x100000, | |
384 | PORT_STATUS_AC1 = 0x200000, | |
385 | PORT_STATUS_AE1 = 0x400000, | |
386 | PORT_STATUS_F0_ENABLED = 0x1000000, | |
387 | PORT_STATUS_F1_ENABLED = 0x2000000, | |
388 | PORT_STATUS_F2_ENABLED = 0x4000000, | |
389 | PORT_STATUS_F3_ENABLED = 0x8000000, | |
390 | }; | |
391 | ||
392 | /* macMIIMgmtControlReg */ | |
393 | enum { | |
394 | MAC_ADDR_INDIRECT_PTR_REG_RP_MASK = 0x0003, | |
395 | MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_LWR = 0x0000, | |
396 | MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_UPR = 0x0001, | |
397 | MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_LWR = 0x0002, | |
398 | MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_UPR = 0x0003, | |
399 | MAC_ADDR_INDIRECT_PTR_REG_PR = 0x0008, | |
400 | MAC_ADDR_INDIRECT_PTR_REG_SS = 0x0010, | |
401 | MAC_ADDR_INDIRECT_PTR_REG_SE = 0x0020, | |
402 | MAC_ADDR_INDIRECT_PTR_REG_SP = 0x0040, | |
403 | MAC_ADDR_INDIRECT_PTR_REG_PE = 0x0080, | |
404 | }; | |
405 | ||
406 | /* macMIIMgmtControlReg */ | |
407 | enum { | |
408 | MAC_MII_CONTROL_RC = 0x0001, | |
409 | MAC_MII_CONTROL_SC = 0x0002, | |
410 | MAC_MII_CONTROL_AS = 0x0004, | |
411 | MAC_MII_CONTROL_NP = 0x0008, | |
412 | MAC_MII_CONTROL_CLK_SEL_MASK = 0x0070, | |
413 | MAC_MII_CONTROL_CLK_SEL_DIV2 = 0x0000, | |
414 | MAC_MII_CONTROL_CLK_SEL_DIV4 = 0x0010, | |
415 | MAC_MII_CONTROL_CLK_SEL_DIV6 = 0x0020, | |
416 | MAC_MII_CONTROL_CLK_SEL_DIV8 = 0x0030, | |
417 | MAC_MII_CONTROL_CLK_SEL_DIV10 = 0x0040, | |
418 | MAC_MII_CONTROL_CLK_SEL_DIV14 = 0x0050, | |
419 | MAC_MII_CONTROL_CLK_SEL_DIV20 = 0x0060, | |
420 | MAC_MII_CONTROL_CLK_SEL_DIV28 = 0x0070, | |
421 | MAC_MII_CONTROL_RM = 0x8000, | |
422 | }; | |
423 | ||
424 | /* macMIIStatusReg */ | |
425 | enum { | |
426 | MAC_MII_STATUS_BSY = 0x0001, | |
427 | MAC_MII_STATUS_SC = 0x0002, | |
428 | MAC_MII_STATUS_NV = 0x0004, | |
429 | }; | |
430 | ||
431 | enum { | |
432 | MAC_CONFIG_REG_PE = 0x0001, | |
433 | MAC_CONFIG_REG_TF = 0x0002, | |
434 | MAC_CONFIG_REG_RF = 0x0004, | |
435 | MAC_CONFIG_REG_FD = 0x0008, | |
436 | MAC_CONFIG_REG_GM = 0x0010, | |
437 | MAC_CONFIG_REG_LB = 0x0020, | |
438 | MAC_CONFIG_REG_SR = 0x8000, | |
439 | }; | |
440 | ||
441 | enum { | |
442 | MAC_HALF_DUPLEX_REG_ED = 0x10000, | |
443 | MAC_HALF_DUPLEX_REG_NB = 0x20000, | |
444 | MAC_HALF_DUPLEX_REG_BNB = 0x40000, | |
445 | MAC_HALF_DUPLEX_REG_ALT = 0x80000, | |
446 | }; | |
447 | ||
448 | enum { | |
449 | IP_ADDR_INDEX_REG_MASK = 0x000f, | |
450 | IP_ADDR_INDEX_REG_FUNC_0_PRI = 0x0000, | |
451 | IP_ADDR_INDEX_REG_FUNC_0_SEC = 0x0001, | |
452 | IP_ADDR_INDEX_REG_FUNC_1_PRI = 0x0002, | |
453 | IP_ADDR_INDEX_REG_FUNC_1_SEC = 0x0003, | |
454 | IP_ADDR_INDEX_REG_FUNC_2_PRI = 0x0004, | |
455 | IP_ADDR_INDEX_REG_FUNC_2_SEC = 0x0005, | |
456 | IP_ADDR_INDEX_REG_FUNC_3_PRI = 0x0006, | |
457 | IP_ADDR_INDEX_REG_FUNC_3_SEC = 0x0007, | |
bd36b0ac RM |
458 | IP_ADDR_INDEX_REG_6 = 0x0008, |
459 | IP_ADDR_INDEX_REG_OFFSET_MASK = 0x0030, | |
9ddf7774 | 460 | IP_ADDR_INDEX_REG_E = 0x0040, |
bd36b0ac RM |
461 | }; |
462 | enum { | |
463 | QL3032_PORT_CONTROL_DS = 0x0001, | |
464 | QL3032_PORT_CONTROL_HH = 0x0002, | |
465 | QL3032_PORT_CONTROL_EIv6 = 0x0004, | |
466 | QL3032_PORT_CONTROL_EIv4 = 0x0008, | |
467 | QL3032_PORT_CONTROL_ET = 0x0010, | |
468 | QL3032_PORT_CONTROL_EF = 0x0020, | |
469 | QL3032_PORT_CONTROL_DRM = 0x0040, | |
470 | QL3032_PORT_CONTROL_RLB = 0x0080, | |
471 | QL3032_PORT_CONTROL_RCB = 0x0100, | |
472 | QL3032_PORT_CONTROL_KIE = 0x0200, | |
5a4faa87 RM |
473 | }; |
474 | ||
475 | enum { | |
476 | PROBE_MUX_ADDR_REG_MUX_SEL_MASK = 0x003f, | |
477 | PROBE_MUX_ADDR_REG_SYSCLK = 0x0000, | |
478 | PROBE_MUX_ADDR_REG_PCICLK = 0x0040, | |
479 | PROBE_MUX_ADDR_REG_NRXCLK = 0x0080, | |
480 | PROBE_MUX_ADDR_REG_CPUCLK = 0x00C0, | |
481 | PROBE_MUX_ADDR_REG_MODULE_SEL_MASK = 0x3f00, | |
482 | PROBE_MUX_ADDR_REG_UP = 0x4000, | |
483 | PROBE_MUX_ADDR_REG_RE = 0x8000, | |
484 | }; | |
485 | ||
486 | enum { | |
487 | STATISTICS_INDEX_REG_MASK = 0x01ff, | |
488 | STATISTICS_INDEX_REG_MAC0_TX_FRAME = 0x0000, | |
489 | STATISTICS_INDEX_REG_MAC0_TX_BYTES = 0x0001, | |
490 | STATISTICS_INDEX_REG_MAC0_TX_STAT1 = 0x0002, | |
491 | STATISTICS_INDEX_REG_MAC0_TX_STAT2 = 0x0003, | |
492 | STATISTICS_INDEX_REG_MAC0_TX_STAT3 = 0x0004, | |
493 | STATISTICS_INDEX_REG_MAC0_TX_STAT4 = 0x0005, | |
494 | STATISTICS_INDEX_REG_MAC0_TX_STAT5 = 0x0006, | |
495 | STATISTICS_INDEX_REG_MAC0_RX_FRAME = 0x0007, | |
496 | STATISTICS_INDEX_REG_MAC0_RX_BYTES = 0x0008, | |
497 | STATISTICS_INDEX_REG_MAC0_RX_STAT1 = 0x0009, | |
498 | STATISTICS_INDEX_REG_MAC0_RX_STAT2 = 0x000a, | |
499 | STATISTICS_INDEX_REG_MAC0_RX_STAT3 = 0x000b, | |
500 | STATISTICS_INDEX_REG_MAC0_RX_ERR_CRC = 0x000c, | |
501 | STATISTICS_INDEX_REG_MAC0_RX_ERR_ENC = 0x000d, | |
502 | STATISTICS_INDEX_REG_MAC0_RX_ERR_LEN = 0x000e, | |
503 | STATISTICS_INDEX_REG_MAC0_RX_STAT4 = 0x000f, | |
504 | STATISTICS_INDEX_REG_MAC1_TX_FRAME = 0x0010, | |
505 | STATISTICS_INDEX_REG_MAC1_TX_BYTES = 0x0011, | |
506 | STATISTICS_INDEX_REG_MAC1_TX_STAT1 = 0x0012, | |
507 | STATISTICS_INDEX_REG_MAC1_TX_STAT2 = 0x0013, | |
508 | STATISTICS_INDEX_REG_MAC1_TX_STAT3 = 0x0014, | |
509 | STATISTICS_INDEX_REG_MAC1_TX_STAT4 = 0x0015, | |
510 | STATISTICS_INDEX_REG_MAC1_TX_STAT5 = 0x0016, | |
511 | STATISTICS_INDEX_REG_MAC1_RX_FRAME = 0x0017, | |
512 | STATISTICS_INDEX_REG_MAC1_RX_BYTES = 0x0018, | |
513 | STATISTICS_INDEX_REG_MAC1_RX_STAT1 = 0x0019, | |
514 | STATISTICS_INDEX_REG_MAC1_RX_STAT2 = 0x001a, | |
515 | STATISTICS_INDEX_REG_MAC1_RX_STAT3 = 0x001b, | |
516 | STATISTICS_INDEX_REG_MAC1_RX_ERR_CRC = 0x001c, | |
517 | STATISTICS_INDEX_REG_MAC1_RX_ERR_ENC = 0x001d, | |
518 | STATISTICS_INDEX_REG_MAC1_RX_ERR_LEN = 0x001e, | |
519 | STATISTICS_INDEX_REG_MAC1_RX_STAT4 = 0x001f, | |
520 | STATISTICS_INDEX_REG_IP_TX_PKTS = 0x0020, | |
521 | STATISTICS_INDEX_REG_IP_TX_BYTES = 0x0021, | |
522 | STATISTICS_INDEX_REG_IP_TX_FRAG = 0x0022, | |
523 | STATISTICS_INDEX_REG_IP_RX_PKTS = 0x0023, | |
524 | STATISTICS_INDEX_REG_IP_RX_BYTES = 0x0024, | |
525 | STATISTICS_INDEX_REG_IP_RX_FRAG = 0x0025, | |
526 | STATISTICS_INDEX_REG_IP_DGRM_REASSEMBLY = 0x0026, | |
527 | STATISTICS_INDEX_REG_IP_V6_RX_PKTS = 0x0027, | |
528 | STATISTICS_INDEX_REG_IP_RX_PKTERR = 0x0028, | |
529 | STATISTICS_INDEX_REG_IP_REASSEMBLY_ERR = 0x0029, | |
530 | STATISTICS_INDEX_REG_TCP_TX_SEG = 0x0030, | |
531 | STATISTICS_INDEX_REG_TCP_TX_BYTES = 0x0031, | |
532 | STATISTICS_INDEX_REG_TCP_RX_SEG = 0x0032, | |
533 | STATISTICS_INDEX_REG_TCP_RX_BYTES = 0x0033, | |
534 | STATISTICS_INDEX_REG_TCP_TIMER_EXP = 0x0034, | |
535 | STATISTICS_INDEX_REG_TCP_RX_ACK = 0x0035, | |
536 | STATISTICS_INDEX_REG_TCP_TX_ACK = 0x0036, | |
537 | STATISTICS_INDEX_REG_TCP_RX_ERR = 0x0037, | |
538 | STATISTICS_INDEX_REG_TCP_RX_WIN_PROBE = 0x0038, | |
539 | STATISTICS_INDEX_REG_TCP_ECC_ERR_CORR = 0x003f, | |
540 | }; | |
541 | ||
542 | enum { | |
543 | PORT_FATAL_ERROR_STATUS_OFB_RE_MAC0 = 0x00000001, | |
544 | PORT_FATAL_ERROR_STATUS_OFB_RE_MAC1 = 0x00000002, | |
545 | PORT_FATAL_ERROR_STATUS_OFB_WE = 0x00000004, | |
546 | PORT_FATAL_ERROR_STATUS_IFB_RE = 0x00000008, | |
547 | PORT_FATAL_ERROR_STATUS_IFB_WE_MAC0 = 0x00000010, | |
548 | PORT_FATAL_ERROR_STATUS_IFB_WE_MAC1 = 0x00000020, | |
549 | PORT_FATAL_ERROR_STATUS_ODE_RE = 0x00000040, | |
550 | PORT_FATAL_ERROR_STATUS_ODE_WE = 0x00000080, | |
551 | PORT_FATAL_ERROR_STATUS_IDE_RE = 0x00000100, | |
552 | PORT_FATAL_ERROR_STATUS_IDE_WE = 0x00000200, | |
553 | PORT_FATAL_ERROR_STATUS_SDE_RE = 0x00000400, | |
554 | PORT_FATAL_ERROR_STATUS_SDE_WE = 0x00000800, | |
555 | PORT_FATAL_ERROR_STATUS_BLE = 0x00001000, | |
556 | PORT_FATAL_ERROR_STATUS_SPE = 0x00002000, | |
557 | PORT_FATAL_ERROR_STATUS_EP0 = 0x00004000, | |
558 | PORT_FATAL_ERROR_STATUS_EP1 = 0x00008000, | |
559 | PORT_FATAL_ERROR_STATUS_ICE = 0x00010000, | |
560 | PORT_FATAL_ERROR_STATUS_ILE = 0x00020000, | |
561 | PORT_FATAL_ERROR_STATUS_OPE = 0x00040000, | |
562 | PORT_FATAL_ERROR_STATUS_TA = 0x00080000, | |
563 | PORT_FATAL_ERROR_STATUS_MA = 0x00100000, | |
564 | PORT_FATAL_ERROR_STATUS_SCE = 0x00200000, | |
565 | PORT_FATAL_ERROR_STATUS_RPE = 0x00400000, | |
566 | PORT_FATAL_ERROR_STATUS_MPE = 0x00800000, | |
567 | PORT_FATAL_ERROR_STATUS_OCE = 0x01000000, | |
568 | }; | |
569 | ||
570 | /* | |
571 | * port control and status page - page 0 | |
572 | */ | |
573 | ||
574 | struct ql3xxx_port_registers { | |
575 | struct ql3xxx_common_registers CommonRegs; | |
576 | ||
577 | u32 ExternalHWConfig; | |
578 | u32 InternalChipConfig; | |
579 | u32 portControl; | |
580 | u32 portStatus; | |
581 | u32 macAddrIndirectPtrReg; | |
582 | u32 macAddrDataReg; | |
583 | u32 macMIIMgmtControlReg; | |
584 | u32 macMIIMgmtAddrReg; | |
585 | u32 macMIIMgmtDataReg; | |
586 | u32 macMIIStatusReg; | |
587 | u32 mac0ConfigReg; | |
588 | u32 mac0IpgIfgReg; | |
589 | u32 mac0HalfDuplexReg; | |
590 | u32 mac0MaxFrameLengthReg; | |
591 | u32 mac0PauseThresholdReg; | |
592 | u32 mac1ConfigReg; | |
593 | u32 mac1IpgIfgReg; | |
594 | u32 mac1HalfDuplexReg; | |
595 | u32 mac1MaxFrameLengthReg; | |
596 | u32 mac1PauseThresholdReg; | |
597 | u32 ipAddrIndexReg; | |
598 | u32 ipAddrDataReg; | |
599 | u32 ipReassemblyTimeout; | |
600 | u32 tcpMaxWindow; | |
601 | u32 currentTcpTimestamp[2]; | |
602 | u32 internalRamRWAddrReg; | |
603 | u32 internalRamWDataReg; | |
604 | u32 reclaimedBufferAddrRegLow; | |
605 | u32 reclaimedBufferAddrRegHigh; | |
bd36b0ac RM |
606 | u32 tcpConfiguration; |
607 | u32 functionControl; | |
5a4faa87 RM |
608 | u32 fpgaRevID; |
609 | u32 localRamAddr; | |
610 | u32 localRamDataAutoIncr; | |
611 | u32 localRamDataNonIncr; | |
612 | u32 gpOutput; | |
613 | u32 gpInput; | |
614 | u32 probeMuxAddr; | |
615 | u32 probeMuxData; | |
616 | u32 statisticsIndexReg; | |
617 | u32 statisticsReadDataRegAutoIncr; | |
618 | u32 statisticsReadDataRegNoIncr; | |
619 | u32 PortFatalErrStatus; | |
620 | }; | |
621 | ||
622 | /* | |
623 | * port host memory config page - page 1 | |
624 | */ | |
625 | struct ql3xxx_host_memory_registers { | |
626 | struct ql3xxx_common_registers CommonRegs; | |
627 | ||
628 | u32 reserved[12]; | |
629 | ||
630 | /* Network Request Queue */ | |
631 | u32 reqConsumerIndex; | |
632 | u32 reqConsumerIndexAddrLow; | |
633 | u32 reqConsumerIndexAddrHigh; | |
634 | u32 reqBaseAddrLow; | |
635 | u32 reqBaseAddrHigh; | |
636 | u32 reqLength; | |
637 | ||
638 | /* Network Completion Queue */ | |
639 | u32 rspProducerIndex; | |
640 | u32 rspProducerIndexAddrLow; | |
641 | u32 rspProducerIndexAddrHigh; | |
642 | u32 rspBaseAddrLow; | |
643 | u32 rspBaseAddrHigh; | |
644 | u32 rspLength; | |
645 | ||
646 | /* RX Large Buffer Queue */ | |
647 | u32 rxLargeQConsumerIndex; | |
648 | u32 rxLargeQBaseAddrLow; | |
649 | u32 rxLargeQBaseAddrHigh; | |
650 | u32 rxLargeQLength; | |
651 | u32 rxLargeBufferLength; | |
652 | ||
653 | /* RX Small Buffer Queue */ | |
654 | u32 rxSmallQConsumerIndex; | |
655 | u32 rxSmallQBaseAddrLow; | |
656 | u32 rxSmallQBaseAddrHigh; | |
657 | u32 rxSmallQLength; | |
658 | u32 rxSmallBufferLength; | |
659 | ||
660 | }; | |
661 | ||
662 | /* | |
663 | * port local RAM page - page 2 | |
664 | */ | |
665 | struct ql3xxx_local_ram_registers { | |
666 | struct ql3xxx_common_registers CommonRegs; | |
667 | u32 bufletSize; | |
668 | u32 maxBufletCount; | |
669 | u32 currentBufletCount; | |
670 | u32 reserved; | |
671 | u32 freeBufletThresholdLow; | |
672 | u32 freeBufletThresholdHigh; | |
673 | u32 ipHashTableBase; | |
674 | u32 ipHashTableCount; | |
675 | u32 tcpHashTableBase; | |
676 | u32 tcpHashTableCount; | |
677 | u32 ncbBase; | |
678 | u32 maxNcbCount; | |
679 | u32 currentNcbCount; | |
680 | u32 drbBase; | |
681 | u32 maxDrbCount; | |
682 | u32 currentDrbCount; | |
683 | }; | |
684 | ||
685 | /* | |
686 | * definitions for Semaphore bits in Semaphore/Serial NVRAM interface register | |
687 | */ | |
688 | ||
689 | #define LS_64BITS(x) (u32)(0xffffffff & ((u64)x)) | |
690 | #define MS_64BITS(x) (u32)(0xffffffff & (((u64)x)>>16>>16) ) | |
691 | ||
692 | /* | |
693 | * I/O register | |
694 | */ | |
695 | ||
696 | enum { | |
697 | CONTROL_REG = 0, | |
698 | STATUS_REG = 1, | |
699 | PHY_STAT_LINK_UP = 0x0004, | |
700 | PHY_CTRL_LOOPBACK = 0x4000, | |
701 | ||
702 | PETBI_CONTROL_REG = 0x00, | |
3efedf2e | 703 | PETBI_CTRL_ALL_PARAMS = 0x7140, |
5a4faa87 RM |
704 | PETBI_CTRL_SOFT_RESET = 0x8000, |
705 | PETBI_CTRL_AUTO_NEG = 0x1000, | |
706 | PETBI_CTRL_RESTART_NEG = 0x0200, | |
707 | PETBI_CTRL_FULL_DUPLEX = 0x0100, | |
708 | PETBI_CTRL_SPEED_1000 = 0x0040, | |
709 | ||
710 | PETBI_STATUS_REG = 0x01, | |
711 | PETBI_STAT_NEG_DONE = 0x0020, | |
712 | PETBI_STAT_LINK_UP = 0x0004, | |
713 | ||
714 | PETBI_NEG_ADVER = 0x04, | |
715 | PETBI_NEG_PAUSE = 0x0080, | |
716 | PETBI_NEG_PAUSE_MASK = 0x0180, | |
717 | PETBI_NEG_DUPLEX = 0x0020, | |
718 | PETBI_NEG_DUPLEX_MASK = 0x0060, | |
719 | ||
720 | PETBI_NEG_PARTNER = 0x05, | |
721 | PETBI_NEG_ERROR_MASK = 0x3000, | |
722 | ||
723 | PETBI_EXPANSION_REG = 0x06, | |
724 | PETBI_EXP_PAGE_RX = 0x0002, | |
725 | ||
3efedf2e RM |
726 | PHY_GIG_CONTROL = 9, |
727 | PHY_GIG_ENABLE_MAN = 0x1000, /* Enable Master/Slave Manual Config*/ | |
728 | PHY_GIG_SET_MASTER = 0x0800, /* Set Master (slave if clear)*/ | |
729 | PHY_GIG_ALL_PARAMS = 0x0300, | |
730 | PHY_GIG_ADV_1000F = 0x0200, | |
731 | PHY_GIG_ADV_1000H = 0x0100, | |
732 | ||
733 | PHY_NEG_ADVER = 4, | |
734 | PHY_NEG_ALL_PARAMS = 0x0fe0, | |
735 | PHY_NEG_ASY_PAUSE = 0x0800, | |
736 | PHY_NEG_SYM_PAUSE = 0x0400, | |
737 | PHY_NEG_ADV_SPEED = 0x01e0, | |
738 | PHY_NEG_ADV_100F = 0x0100, | |
739 | PHY_NEG_ADV_100H = 0x0080, | |
740 | PHY_NEG_ADV_10F = 0x0040, | |
741 | PHY_NEG_ADV_10H = 0x0020, | |
742 | ||
5a4faa87 RM |
743 | PETBI_TBI_CTRL = 0x11, |
744 | PETBI_TBI_RESET = 0x8000, | |
745 | PETBI_TBI_AUTO_SENSE = 0x0100, | |
746 | PETBI_TBI_SERDES_MODE = 0x0010, | |
747 | PETBI_TBI_SERDES_WRAP = 0x0002, | |
748 | ||
749 | AUX_CONTROL_STATUS = 0x1c, | |
750 | PHY_AUX_NEG_DONE = 0x8000, | |
751 | PHY_NEG_PARTNER = 5, | |
752 | PHY_AUX_DUPLEX_STAT = 0x0020, | |
753 | PHY_AUX_SPEED_STAT = 0x0018, | |
754 | PHY_AUX_NO_HW_STRAP = 0x0004, | |
755 | PHY_AUX_RESET_STICK = 0x0002, | |
756 | PHY_NEG_PAUSE = 0x0400, | |
757 | PHY_CTRL_SOFT_RESET = 0x8000, | |
3efedf2e | 758 | PHY_CTRL_AUTO_NEG = 0x1000, |
5a4faa87 RM |
759 | PHY_CTRL_RESTART_NEG = 0x0200, |
760 | }; | |
761 | enum { | |
762 | /* AM29LV Flash definitions */ | |
763 | FM93C56A_START = 0x1, | |
764 | /* Commands */ | |
765 | FM93C56A_READ = 0x2, | |
766 | FM93C56A_WEN = 0x0, | |
767 | FM93C56A_WRITE = 0x1, | |
768 | FM93C56A_WRITE_ALL = 0x0, | |
769 | FM93C56A_WDS = 0x0, | |
770 | FM93C56A_ERASE = 0x3, | |
771 | FM93C56A_ERASE_ALL = 0x0, | |
25985edc | 772 | /* Command Extensions */ |
5a4faa87 RM |
773 | FM93C56A_WEN_EXT = 0x3, |
774 | FM93C56A_WRITE_ALL_EXT = 0x1, | |
775 | FM93C56A_WDS_EXT = 0x0, | |
776 | FM93C56A_ERASE_ALL_EXT = 0x2, | |
777 | /* Special Bits */ | |
778 | FM93C56A_READ_DUMMY_BITS = 1, | |
779 | FM93C56A_READY = 0, | |
780 | FM93C56A_BUSY = 1, | |
781 | FM93C56A_CMD_BITS = 2, | |
782 | /* AM29LV Flash definitions */ | |
783 | FM93C56A_SIZE_8 = 0x100, | |
784 | FM93C56A_SIZE_16 = 0x80, | |
785 | FM93C66A_SIZE_8 = 0x200, | |
786 | FM93C66A_SIZE_16 = 0x100, | |
787 | FM93C86A_SIZE_16 = 0x400, | |
788 | /* Address Bits */ | |
789 | FM93C56A_NO_ADDR_BITS_16 = 8, | |
790 | FM93C56A_NO_ADDR_BITS_8 = 9, | |
791 | FM93C86A_NO_ADDR_BITS_16 = 10, | |
792 | /* Data Bits */ | |
793 | FM93C56A_DATA_BITS_16 = 16, | |
794 | FM93C56A_DATA_BITS_8 = 8, | |
795 | }; | |
796 | enum { | |
797 | /* Auburn Bits */ | |
798 | AUBURN_EEPROM_DI = 0x8, | |
799 | AUBURN_EEPROM_DI_0 = 0x0, | |
800 | AUBURN_EEPROM_DI_1 = 0x8, | |
801 | AUBURN_EEPROM_DO = 0x4, | |
802 | AUBURN_EEPROM_DO_0 = 0x0, | |
803 | AUBURN_EEPROM_DO_1 = 0x4, | |
804 | AUBURN_EEPROM_CS = 0x2, | |
805 | AUBURN_EEPROM_CS_0 = 0x0, | |
806 | AUBURN_EEPROM_CS_1 = 0x2, | |
807 | AUBURN_EEPROM_CLK_RISE = 0x1, | |
808 | AUBURN_EEPROM_CLK_FALL = 0x0, | |
809 | }; | |
810 | enum {EEPROM_SIZE = FM93C86A_SIZE_16, | |
811 | EEPROM_NO_ADDR_BITS = FM93C86A_NO_ADDR_BITS_16, | |
812 | EEPROM_NO_DATA_BITS = FM93C56A_DATA_BITS_16, | |
813 | }; | |
814 | ||
815 | /* | |
816 | * MAC Config data structure | |
817 | */ | |
818 | struct eeprom_port_cfg { | |
819 | u16 etherMtu_mac; | |
820 | u16 pauseThreshold_mac; | |
821 | u16 resumeThreshold_mac; | |
822 | u16 portConfiguration; | |
3efedf2e | 823 | #define PORT_CONFIG_DEFAULT 0xf700 |
5a4faa87 RM |
824 | #define PORT_CONFIG_AUTO_NEG_ENABLED 0x8000 |
825 | #define PORT_CONFIG_SYM_PAUSE_ENABLED 0x4000 | |
826 | #define PORT_CONFIG_FULL_DUPLEX_ENABLED 0x2000 | |
827 | #define PORT_CONFIG_HALF_DUPLEX_ENABLED 0x1000 | |
828 | #define PORT_CONFIG_1000MB_SPEED 0x0400 | |
829 | #define PORT_CONFIG_100MB_SPEED 0x0200 | |
830 | #define PORT_CONFIG_10MB_SPEED 0x0100 | |
831 | #define PORT_CONFIG_LINK_SPEED_MASK 0x0F00 | |
832 | u16 reserved[12]; | |
833 | ||
834 | }; | |
835 | ||
836 | /* | |
837 | * BIOS data structure | |
838 | */ | |
839 | struct eeprom_bios_cfg { | |
840 | u16 SpinDlyEn:1, disBios:1, EnMemMap:1, EnSelectBoot:1, Reserved:12; | |
841 | ||
842 | u8 bootID0:7, boodID0Valid:1; | |
843 | u8 bootLun0[8]; | |
844 | ||
845 | u8 bootID1:7, boodID1Valid:1; | |
846 | u8 bootLun1[8]; | |
847 | ||
848 | u16 MaxLunsTrgt; | |
849 | u8 reserved[10]; | |
850 | }; | |
851 | ||
852 | /* | |
853 | * Function Specific Data structure | |
854 | */ | |
855 | struct eeprom_function_cfg { | |
856 | u8 reserved[30]; | |
804d8541 AV |
857 | u16 macAddress[3]; |
858 | u16 macAddressSecondary[3]; | |
5a4faa87 RM |
859 | |
860 | u16 subsysVendorId; | |
861 | u16 subsysDeviceId; | |
862 | }; | |
863 | ||
864 | /* | |
865 | * EEPROM format | |
866 | */ | |
867 | struct eeprom_data { | |
868 | u8 asicId[4]; | |
804d8541 | 869 | u16 version_and_numPorts; /* together to avoid endianness crap */ |
5a4faa87 RM |
870 | u16 boardId; |
871 | ||
872 | #define EEPROM_BOARDID_STR_SIZE 16 | |
873 | #define EEPROM_SERIAL_NUM_SIZE 16 | |
874 | ||
875 | u8 boardIdStr[16]; | |
876 | u8 serialNumber[16]; | |
877 | u16 extHwConfig; | |
878 | struct eeprom_port_cfg macCfg_port0; | |
879 | struct eeprom_port_cfg macCfg_port1; | |
880 | u16 bufletSize; | |
881 | u16 bufletCount; | |
882 | u16 tcpWindowThreshold50; | |
883 | u16 tcpWindowThreshold25; | |
884 | u16 tcpWindowThreshold0; | |
885 | u16 ipHashTableBaseHi; | |
886 | u16 ipHashTableBaseLo; | |
887 | u16 ipHashTableSize; | |
888 | u16 tcpHashTableBaseHi; | |
889 | u16 tcpHashTableBaseLo; | |
890 | u16 tcpHashTableSize; | |
891 | u16 ncbTableBaseHi; | |
892 | u16 ncbTableBaseLo; | |
893 | u16 ncbTableSize; | |
894 | u16 drbTableBaseHi; | |
895 | u16 drbTableBaseLo; | |
896 | u16 drbTableSize; | |
897 | u16 reserved_142[4]; | |
898 | u16 ipReassemblyTimeout; | |
899 | u16 tcpMaxWindowSize; | |
900 | u16 ipSecurity; | |
901 | #define IPSEC_CONFIG_PRESENT 0x0001 | |
902 | u8 reserved_156[294]; | |
903 | u16 qDebug[8]; | |
904 | struct eeprom_function_cfg funcCfg_fn0; | |
905 | u16 reserved_510; | |
906 | u8 oemSpace[432]; | |
907 | struct eeprom_bios_cfg biosCfg_fn1; | |
908 | struct eeprom_function_cfg funcCfg_fn1; | |
909 | u16 reserved_1022; | |
910 | u8 reserved_1024[464]; | |
911 | struct eeprom_function_cfg funcCfg_fn2; | |
912 | u16 reserved_1534; | |
913 | u8 reserved_1536[432]; | |
914 | struct eeprom_bios_cfg biosCfg_fn3; | |
915 | struct eeprom_function_cfg funcCfg_fn3; | |
916 | u16 checksum; | |
917 | }; | |
918 | ||
919 | /* | |
920 | * General definitions... | |
921 | */ | |
922 | ||
923 | /* | |
924 | * Below are a number compiler switches for controlling driver behavior. | |
925 | * Some are not supported under certain conditions and are notated as such. | |
926 | */ | |
927 | ||
928 | #define QL3XXX_VENDOR_ID 0x1077 | |
929 | #define QL3022_DEVICE_ID 0x3022 | |
bd36b0ac | 930 | #define QL3032_DEVICE_ID 0x3032 |
5a4faa87 RM |
931 | |
932 | /* MTU & Frame Size stuff */ | |
933 | #define NORMAL_MTU_SIZE ETH_DATA_LEN | |
934 | #define JUMBO_MTU_SIZE 9000 | |
935 | #define VLAN_ID_LEN 2 | |
936 | ||
937 | /* Request Queue Related Definitions */ | |
938 | #define NUM_REQ_Q_ENTRIES 256 /* so that 64 * 64 = 4096 (1 page) */ | |
939 | ||
940 | /* Response Queue Related Definitions */ | |
941 | #define NUM_RSP_Q_ENTRIES 256 /* so that 256 * 16 = 4096 (1 page) */ | |
942 | ||
943 | /* Transmit and Receive Buffers */ | |
944 | #define NUM_LBUFQ_ENTRIES 128 | |
b3b1514c | 945 | #define JUMBO_NUM_LBUFQ_ENTRIES 32 |
5a4faa87 RM |
946 | #define NUM_SBUFQ_ENTRIES 64 |
947 | #define QL_SMALL_BUFFER_SIZE 32 | |
948 | #define QL_ADDR_ELE_PER_BUFQ_ENTRY \ | |
949 | (sizeof(struct lrg_buf_q_entry) / sizeof(struct bufq_addr_element)) | |
950 | /* Each send has at least control block. This is how many we keep. */ | |
951 | #define NUM_SMALL_BUFFERS NUM_SBUFQ_ENTRIES * QL_ADDR_ELE_PER_BUFQ_ENTRY | |
1357bfcf | 952 | |
5a4faa87 RM |
953 | #define QL_HEADER_SPACE 32 /* make header space at top of skb. */ |
954 | /* | |
955 | * Large & Small Buffers for Receives | |
956 | */ | |
957 | struct lrg_buf_q_entry { | |
958 | ||
804d8541 | 959 | __le32 addr0_lower; |
5a4faa87 RM |
960 | #define IAL_LAST_ENTRY 0x00000001 |
961 | #define IAL_CONT_ENTRY 0x00000002 | |
962 | #define IAL_FLAG_MASK 0x00000003 | |
804d8541 AV |
963 | __le32 addr0_upper; |
964 | __le32 addr1_lower; | |
965 | __le32 addr1_upper; | |
966 | __le32 addr2_lower; | |
967 | __le32 addr2_upper; | |
968 | __le32 addr3_lower; | |
969 | __le32 addr3_upper; | |
970 | __le32 addr4_lower; | |
971 | __le32 addr4_upper; | |
972 | __le32 addr5_lower; | |
973 | __le32 addr5_upper; | |
974 | __le32 addr6_lower; | |
975 | __le32 addr6_upper; | |
976 | __le32 addr7_lower; | |
977 | __le32 addr7_upper; | |
5a4faa87 RM |
978 | |
979 | }; | |
980 | ||
981 | struct bufq_addr_element { | |
804d8541 AV |
982 | __le32 addr_low; |
983 | __le32 addr_high; | |
5a4faa87 RM |
984 | }; |
985 | ||
986 | #define QL_NO_RESET 0 | |
987 | #define QL_DO_RESET 1 | |
988 | ||
989 | enum link_state_t { | |
990 | LS_UNKNOWN = 0, | |
991 | LS_DOWN, | |
992 | LS_DEGRADE, | |
993 | LS_RECOVER, | |
994 | LS_UP, | |
995 | }; | |
996 | ||
997 | struct ql_rcv_buf_cb { | |
998 | struct ql_rcv_buf_cb *next; | |
999 | struct sk_buff *skb; | |
87196eb7 FT |
1000 | DEFINE_DMA_UNMAP_ADDR(mapaddr); |
1001 | DEFINE_DMA_UNMAP_LEN(maplen); | |
5a4faa87 RM |
1002 | __le32 buf_phy_addr_low; |
1003 | __le32 buf_phy_addr_high; | |
1004 | int index; | |
1005 | }; | |
1006 | ||
bd36b0ac RM |
1007 | /* |
1008 | * Original IOCB has 3 sg entries: | |
1009 | * first points to skb-data area | |
1010 | * second points to first frag | |
1011 | * third points to next oal. | |
1012 | * OAL has 5 entries: | |
1013 | * 1 thru 4 point to frags | |
1014 | * fifth points to next oal. | |
9ddf7774 | 1015 | */ |
bd36b0ac RM |
1016 | #define MAX_OAL_CNT ((MAX_SKB_FRAGS-1)/4 + 1) |
1017 | ||
1018 | struct oal_entry { | |
804d8541 AV |
1019 | __le32 dma_lo; |
1020 | __le32 dma_hi; | |
1021 | __le32 len; | |
bd36b0ac RM |
1022 | #define OAL_LAST_ENTRY 0x80000000 /* Last valid buffer in list. */ |
1023 | #define OAL_CONT_ENTRY 0x40000000 /* points to an OAL. (continuation) */ | |
bd36b0ac RM |
1024 | }; |
1025 | ||
1026 | struct oal { | |
1027 | struct oal_entry oal_entry[5]; | |
1028 | }; | |
1029 | ||
1030 | struct map_list { | |
87196eb7 FT |
1031 | DEFINE_DMA_UNMAP_ADDR(mapaddr); |
1032 | DEFINE_DMA_UNMAP_LEN(maplen); | |
bd36b0ac RM |
1033 | }; |
1034 | ||
5a4faa87 RM |
1035 | struct ql_tx_buf_cb { |
1036 | struct sk_buff *skb; | |
1037 | struct ob_mac_iocb_req *queue_entry ; | |
bd36b0ac RM |
1038 | int seg_count; |
1039 | struct oal *oal; | |
9ddf7774 | 1040 | struct map_list map[MAX_SKB_FRAGS+1]; |
5a4faa87 RM |
1041 | }; |
1042 | ||
1043 | /* definitions for type field */ | |
1044 | #define QL_BUF_TYPE_MACIOCB 0x01 | |
1045 | #define QL_BUF_TYPE_IPIOCB 0x02 | |
1046 | #define QL_BUF_TYPE_TCPIOCB 0x03 | |
1047 | ||
1048 | /* qdev->flags definitions. */ | |
1049 | enum { QL_RESET_DONE = 1, /* Reset finished. */ | |
1050 | QL_RESET_ACTIVE = 2, /* Waiting for reset to finish. */ | |
1051 | QL_RESET_START = 3, /* Please reset the chip. */ | |
1052 | QL_RESET_PER_SCSI = 4, /* SCSI driver requests reset. */ | |
1053 | QL_TX_TIMEOUT = 5, /* Timeout in progress. */ | |
1054 | QL_LINK_MASTER = 6, /* This driver controls the link. */ | |
1055 | QL_ADAPTER_UP = 7, /* Adapter has been brought up. */ | |
1056 | QL_THREAD_UP = 8, /* This flag is available. */ | |
1057 | QL_LINK_UP = 9, /* Link Status. */ | |
1058 | QL_ALLOC_REQ_RSP_Q_DONE = 10, | |
1059 | QL_ALLOC_BUFQS_DONE = 11, | |
1060 | QL_ALLOC_SMALL_BUF_DONE = 12, | |
1061 | QL_LINK_OPTICAL = 13, | |
1062 | QL_MSI_ENABLED = 14, | |
1063 | }; | |
1064 | ||
1065 | /* | |
1066 | * ql3_adapter - The main Adapter structure definition. | |
1067 | * This structure has all fields relevant to the hardware. | |
1068 | */ | |
1069 | ||
1070 | struct ql3_adapter { | |
1071 | u32 reserved_00; | |
1072 | unsigned long flags; | |
1073 | ||
1074 | /* PCI Configuration information for this device */ | |
1075 | struct pci_dev *pdev; | |
1076 | struct net_device *ndev; /* Parent NET device */ | |
1077 | ||
bea3348e SH |
1078 | struct napi_struct napi; |
1079 | ||
5a4faa87 RM |
1080 | /* Hardware information */ |
1081 | u8 chip_rev_id; | |
1082 | u8 pci_slot; | |
1083 | u8 pci_width; | |
1084 | u8 pci_x; | |
1085 | u32 msi; | |
1086 | int index; | |
1087 | struct timer_list adapter_timer; /* timer used for various functions */ | |
1088 | ||
1089 | spinlock_t adapter_lock; | |
1090 | spinlock_t hw_lock; | |
1091 | ||
1092 | /* PCI Bus Relative Register Addresses */ | |
ee111d11 | 1093 | u8 __iomem *mmap_virt_base; /* stores return value from ioremap() */ |
5a4faa87 RM |
1094 | struct ql3xxx_port_registers __iomem *mem_map_registers; |
1095 | u32 current_page; /* tracks current register page */ | |
1096 | ||
1097 | u32 msg_enable; | |
1098 | u8 reserved_01[2]; | |
1099 | u8 reserved_02[2]; | |
1100 | ||
1101 | /* Page for Shadow Registers */ | |
1102 | void *shadow_reg_virt_addr; | |
1103 | dma_addr_t shadow_reg_phy_addr; | |
1104 | ||
1105 | /* Net Request Queue */ | |
1106 | u32 req_q_size; | |
1107 | u32 reserved_03; | |
1108 | struct ob_mac_iocb_req *req_q_virt_addr; | |
1109 | dma_addr_t req_q_phy_addr; | |
1110 | u16 req_producer_index; | |
1111 | u16 reserved_04; | |
1112 | u16 *preq_consumer_index; | |
1113 | u32 req_consumer_index_phy_addr_high; | |
1114 | u32 req_consumer_index_phy_addr_low; | |
1115 | atomic_t tx_count; | |
1116 | struct ql_tx_buf_cb tx_buf[NUM_REQ_Q_ENTRIES]; | |
1117 | ||
1118 | /* Net Response Queue */ | |
1119 | u32 rsp_q_size; | |
1120 | u32 eeprom_cmd_data; | |
1121 | struct net_rsp_iocb *rsp_q_virt_addr; | |
1122 | dma_addr_t rsp_q_phy_addr; | |
1123 | struct net_rsp_iocb *rsp_current; | |
1124 | u16 rsp_consumer_index; | |
1125 | u16 reserved_06; | |
804d8541 | 1126 | volatile __le32 *prsp_producer_index; |
5a4faa87 RM |
1127 | u32 rsp_producer_index_phy_addr_high; |
1128 | u32 rsp_producer_index_phy_addr_low; | |
1129 | ||
1130 | /* Large Buffer Queue */ | |
1131 | u32 lrg_buf_q_alloc_size; | |
1132 | u32 lrg_buf_q_size; | |
1133 | void *lrg_buf_q_alloc_virt_addr; | |
1134 | void *lrg_buf_q_virt_addr; | |
1135 | dma_addr_t lrg_buf_q_alloc_phy_addr; | |
1136 | dma_addr_t lrg_buf_q_phy_addr; | |
1137 | u32 lrg_buf_q_producer_index; | |
1138 | u32 lrg_buf_release_cnt; | |
1139 | struct bufq_addr_element *lrg_buf_next_free; | |
1357bfcf RM |
1140 | u32 num_large_buffers; |
1141 | u32 num_lbufq_entries; | |
5a4faa87 RM |
1142 | |
1143 | /* Large (Receive) Buffers */ | |
1357bfcf | 1144 | struct ql_rcv_buf_cb *lrg_buf; |
5a4faa87 RM |
1145 | struct ql_rcv_buf_cb *lrg_buf_free_head; |
1146 | struct ql_rcv_buf_cb *lrg_buf_free_tail; | |
1147 | u32 lrg_buf_free_count; | |
1148 | u32 lrg_buffer_len; | |
1149 | u32 lrg_buf_index; | |
1150 | u32 lrg_buf_skb_check; | |
1151 | ||
1152 | /* Small Buffer Queue */ | |
1153 | u32 small_buf_q_alloc_size; | |
1154 | u32 small_buf_q_size; | |
1155 | u32 small_buf_q_producer_index; | |
1156 | void *small_buf_q_alloc_virt_addr; | |
1157 | void *small_buf_q_virt_addr; | |
1158 | dma_addr_t small_buf_q_alloc_phy_addr; | |
1159 | dma_addr_t small_buf_q_phy_addr; | |
1160 | u32 small_buf_index; | |
1161 | ||
1162 | /* Small (Receive) Buffers */ | |
1163 | void *small_buf_virt_addr; | |
1164 | dma_addr_t small_buf_phy_addr; | |
1165 | u32 small_buf_phy_addr_low; | |
1166 | u32 small_buf_phy_addr_high; | |
1167 | u32 small_buf_release_cnt; | |
1168 | u32 small_buf_total_size; | |
1169 | ||
5a4faa87 | 1170 | struct eeprom_data nvram_data; |
5a4faa87 | 1171 | u32 port_link_state; |
5a4faa87 RM |
1172 | |
1173 | /* 4022 specific */ | |
1174 | u32 mac_index; /* Driver's MAC number can be 0 or 1 for first and second networking functions respectively */ | |
1175 | u32 PHYAddr; /* Address of PHY 0x1e00 Port 0 and 0x1f00 Port 1 */ | |
1176 | u32 mac_ob_opcode; /* Opcode to use on mac transmission */ | |
5a4faa87 RM |
1177 | u32 mb_bit_mask; /* MA Bits mask to use on transmission */ |
1178 | u32 numPorts; | |
5a4faa87 | 1179 | struct workqueue_struct *workqueue; |
c4028958 DH |
1180 | struct delayed_work reset_work; |
1181 | struct delayed_work tx_timeout_work; | |
3e23b7d3 | 1182 | struct delayed_work link_state_work; |
5a4faa87 | 1183 | u32 max_frame_size; |
bd36b0ac | 1184 | u32 device_id; |
3efedf2e | 1185 | u16 phyType; |
5a4faa87 RM |
1186 | }; |
1187 | ||
1188 | #endif /* _QLA3XXX_H_ */ |