[linux-2.6-block.git] / drivers / net / ethernet / qlogic / qed / qed_sp_commands.c

/* QLogic qed NIC Driver
 * Copyright (c) 2015-2017  QLogic Corporation
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and /or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include <linux/types.h>
#include <asm/byteorder.h>
#include <linux/bitops.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include "qed.h"
#include <linux/qed/qed_chain.h>
#include "qed_cxt.h"
#include "qed_dcbx.h"
#include "qed_hsi.h"
#include "qed_hw.h"
#include "qed_int.h"
#include "qed_reg_addr.h"
#include "qed_sp.h"
#include "qed_sriov.h"

void qed_sp_destroy_request(struct qed_hwfn *p_hwfn,
			    struct qed_spq_entry *p_ent)
{
	/* qed_spq_get_entry() can either get an entry from the free_pool,
	 * or, if no entries are left, allocate a new entry and add it to
	 * the unlimited_pending list.
	 */
	if (p_ent->queue == &p_hwfn->p_spq->unlimited_pending)
		kfree(p_ent);
	else
		qed_spq_return_entry(p_hwfn, p_ent);
}

int qed_sp_init_request(struct qed_hwfn *p_hwfn,
			struct qed_spq_entry **pp_ent,
			u8 cmd, u8 protocol, struct qed_sp_init_data *p_data)
{
	u32 opaque_cid = p_data->opaque_fid << 16 | p_data->cid;
	struct qed_spq_entry *p_ent = NULL;
	int rc;

	if (!pp_ent)
		return -ENOMEM;

	rc = qed_spq_get_entry(p_hwfn, pp_ent);

	if (rc)
		return rc;

	p_ent = *pp_ent;

	p_ent->elem.hdr.cid		= cpu_to_le32(opaque_cid);
	p_ent->elem.hdr.cmd_id		= cmd;
	p_ent->elem.hdr.protocol_id	= protocol;

	p_ent->priority		= QED_SPQ_PRIORITY_NORMAL;
	p_ent->comp_mode	= p_data->comp_mode;
	p_ent->comp_done.done	= 0;

	switch (p_ent->comp_mode) {
	case QED_SPQ_MODE_EBLOCK:
		p_ent->comp_cb.cookie = &p_ent->comp_done;
		break;

	case QED_SPQ_MODE_BLOCK:
		if (!p_data->p_comp_data)
			goto err;

		p_ent->comp_cb.cookie = p_data->p_comp_data->cookie;
		break;

	case QED_SPQ_MODE_CB:
		if (!p_data->p_comp_data)
			p_ent->comp_cb.function = NULL;
		else
			p_ent->comp_cb = *p_data->p_comp_data;
		break;

	default:
		DP_NOTICE(p_hwfn, "Unknown SPQE completion mode %d\n",
			  p_ent->comp_mode);
		goto err;
	}

	DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
		   "Initialized: CID %08x cmd %02x protocol %02x data_addr %lu comp_mode [%s]\n",
		   opaque_cid, cmd, protocol,
		   (unsigned long)&p_ent->ramrod,
		   D_TRINE(p_ent->comp_mode, QED_SPQ_MODE_EBLOCK,
			   QED_SPQ_MODE_BLOCK, "MODE_EBLOCK", "MODE_BLOCK",
			   "MODE_CB"));

	memset(&p_ent->ramrod, 0, sizeof(p_ent->ramrod));

	return 0;

err:
	qed_sp_destroy_request(p_hwfn, p_ent);

	return -EINVAL;
}

static enum tunnel_clss qed_tunn_clss_to_fw_clss(u8 type)
{
	switch (type) {
	case QED_TUNN_CLSS_MAC_VLAN:
		return TUNNEL_CLSS_MAC_VLAN;
	case QED_TUNN_CLSS_MAC_VNI:
		return TUNNEL_CLSS_MAC_VNI;
	case QED_TUNN_CLSS_INNER_MAC_VLAN:
		return TUNNEL_CLSS_INNER_MAC_VLAN;
	case QED_TUNN_CLSS_INNER_MAC_VNI:
		return TUNNEL_CLSS_INNER_MAC_VNI;
	case QED_TUNN_CLSS_MAC_VLAN_DUAL_STAGE:
		return TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE;
	default:
		return TUNNEL_CLSS_MAC_VLAN;
	}
}

static void
qed_set_pf_update_tunn_mode(struct qed_tunnel_info *p_tun,
			    struct qed_tunnel_info *p_src, bool b_pf_start)
{
	if (p_src->vxlan.b_update_mode || b_pf_start)
		p_tun->vxlan.b_mode_enabled = p_src->vxlan.b_mode_enabled;

	if (p_src->l2_gre.b_update_mode || b_pf_start)
		p_tun->l2_gre.b_mode_enabled = p_src->l2_gre.b_mode_enabled;

	if (p_src->ip_gre.b_update_mode || b_pf_start)
		p_tun->ip_gre.b_mode_enabled = p_src->ip_gre.b_mode_enabled;

	if (p_src->l2_geneve.b_update_mode || b_pf_start)
		p_tun->l2_geneve.b_mode_enabled =
		    p_src->l2_geneve.b_mode_enabled;

	if (p_src->ip_geneve.b_update_mode || b_pf_start)
		p_tun->ip_geneve.b_mode_enabled =
		    p_src->ip_geneve.b_mode_enabled;
}

static void qed_set_tunn_cls_info(struct qed_tunnel_info *p_tun,
				  struct qed_tunnel_info *p_src)
{
	int type;

	p_tun->b_update_rx_cls = p_src->b_update_rx_cls;
	p_tun->b_update_tx_cls = p_src->b_update_tx_cls;

	type = qed_tunn_clss_to_fw_clss(p_src->vxlan.tun_cls);
	p_tun->vxlan.tun_cls = type;
	type = qed_tunn_clss_to_fw_clss(p_src->l2_gre.tun_cls);
	p_tun->l2_gre.tun_cls = type;
	type = qed_tunn_clss_to_fw_clss(p_src->ip_gre.tun_cls);
	p_tun->ip_gre.tun_cls = type;
	type = qed_tunn_clss_to_fw_clss(p_src->l2_geneve.tun_cls);
	p_tun->l2_geneve.tun_cls = type;
	type = qed_tunn_clss_to_fw_clss(p_src->ip_geneve.tun_cls);
	p_tun->ip_geneve.tun_cls = type;
}

static void qed_set_tunn_ports(struct qed_tunnel_info *p_tun,
			       struct qed_tunnel_info *p_src)
{
	p_tun->geneve_port.b_update_port = p_src->geneve_port.b_update_port;
	p_tun->vxlan_port.b_update_port = p_src->vxlan_port.b_update_port;

	if (p_src->geneve_port.b_update_port)
		p_tun->geneve_port.port = p_src->geneve_port.port;

	if (p_src->vxlan_port.b_update_port)
		p_tun->vxlan_port.port = p_src->vxlan_port.port;
}

static void
__qed_set_ramrod_tunnel_param(u8 *p_tunn_cls,
			      struct qed_tunn_update_type *tun_type)
{
	*p_tunn_cls = tun_type->tun_cls;
}

static void
qed_set_ramrod_tunnel_param(u8 *p_tunn_cls,
			    struct qed_tunn_update_type *tun_type,
			    u8 *p_update_port,
			    __le16 *p_port,
			    struct qed_tunn_update_udp_port *p_udp_port)
{
	__qed_set_ramrod_tunnel_param(p_tunn_cls, tun_type);
	if (p_udp_port->b_update_port) {
		*p_update_port = 1;
		*p_port = cpu_to_le16(p_udp_port->port);
	}
}

static void
qed_tunn_set_pf_update_params(struct qed_hwfn *p_hwfn,
			      struct qed_tunnel_info *p_src,
			      struct pf_update_tunnel_config *p_tunn_cfg)
{
	struct qed_tunnel_info *p_tun = &p_hwfn->cdev->tunnel;

	qed_set_pf_update_tunn_mode(p_tun, p_src, false);
	qed_set_tunn_cls_info(p_tun, p_src);
	qed_set_tunn_ports(p_tun, p_src);

	qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan,
				    &p_tun->vxlan,
				    &p_tunn_cfg->set_vxlan_udp_port_flg,
				    &p_tunn_cfg->vxlan_udp_port,
				    &p_tun->vxlan_port);

	qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve,
				    &p_tun->l2_geneve,
				    &p_tunn_cfg->set_geneve_udp_port_flg,
				    &p_tunn_cfg->geneve_udp_port,
				    &p_tun->geneve_port);

	__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve,
				      &p_tun->ip_geneve);

	__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre,
				      &p_tun->l2_gre);

	__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre,
				      &p_tun->ip_gre);

	p_tunn_cfg->update_rx_pf_clss = p_tun->b_update_rx_cls;
}

static void qed_set_hw_tunn_mode(struct qed_hwfn *p_hwfn,
				 struct qed_ptt *p_ptt,
				 struct qed_tunnel_info *p_tun)
{
	qed_set_gre_enable(p_hwfn, p_ptt, p_tun->l2_gre.b_mode_enabled,
			   p_tun->ip_gre.b_mode_enabled);
	qed_set_vxlan_enable(p_hwfn, p_ptt, p_tun->vxlan.b_mode_enabled);

	qed_set_geneve_enable(p_hwfn, p_ptt, p_tun->l2_geneve.b_mode_enabled,
			      p_tun->ip_geneve.b_mode_enabled);
}

static void qed_set_hw_tunn_mode_port(struct qed_hwfn *p_hwfn,
				      struct qed_ptt *p_ptt,
				      struct qed_tunnel_info *p_tunn)
{
	if (p_tunn->vxlan_port.b_update_port)
		qed_set_vxlan_dest_port(p_hwfn, p_ptt,
					p_tunn->vxlan_port.port);

	if (p_tunn->geneve_port.b_update_port)
		qed_set_geneve_dest_port(p_hwfn, p_ptt,
					 p_tunn->geneve_port.port);

	qed_set_hw_tunn_mode(p_hwfn, p_ptt, p_tunn);
}

static void
qed_tunn_set_pf_start_params(struct qed_hwfn *p_hwfn,
			     struct qed_tunnel_info *p_src,
			     struct pf_start_tunnel_config *p_tunn_cfg)
{
	struct qed_tunnel_info *p_tun = &p_hwfn->cdev->tunnel;

	if (!p_src)
		return;

	qed_set_pf_update_tunn_mode(p_tun, p_src, true);
	qed_set_tunn_cls_info(p_tun, p_src);
	qed_set_tunn_ports(p_tun, p_src);

	qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan,
				    &p_tun->vxlan,
				    &p_tunn_cfg->set_vxlan_udp_port_flg,
				    &p_tunn_cfg->vxlan_udp_port,
				    &p_tun->vxlan_port);

	qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve,
				    &p_tun->l2_geneve,
				    &p_tunn_cfg->set_geneve_udp_port_flg,
				    &p_tunn_cfg->geneve_udp_port,
				    &p_tun->geneve_port);

	__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve,
				      &p_tun->ip_geneve);

	__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre,
				      &p_tun->l2_gre);

	__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre,
				      &p_tun->ip_gre);
}

int qed_sp_pf_start(struct qed_hwfn *p_hwfn,
		    struct qed_ptt *p_ptt,
		    struct qed_tunnel_info *p_tunn,
		    bool allow_npar_tx_switch)
{
	struct pf_start_ramrod_data *p_ramrod = NULL;
	u16 sb = qed_int_get_sp_sb_id(p_hwfn);
	u8 sb_index = p_hwfn->p_eq->eq_sb_index;
	struct qed_spq_entry *p_ent = NULL;
	struct qed_sp_init_data init_data;
	int rc = -EINVAL;
	u8 page_cnt, i;

	/* update initial eq producer */
	qed_eq_prod_update(p_hwfn,
			   qed_chain_get_prod_idx(&p_hwfn->p_eq->chain));

	memset(&init_data, 0, sizeof(init_data));
	init_data.cid = qed_spq_get_cid(p_hwfn);
	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;

	rc = qed_sp_init_request(p_hwfn, &p_ent,
				 COMMON_RAMROD_PF_START,
				 PROTOCOLID_COMMON, &init_data);
	if (rc)
		return rc;

	p_ramrod = &p_ent->ramrod.pf_start;

	p_ramrod->event_ring_sb_id	= cpu_to_le16(sb);
	p_ramrod->event_ring_sb_index	= sb_index;
	p_ramrod->path_id		= QED_PATH_ID(p_hwfn);
	p_ramrod->dont_log_ramrods	= 0;
	p_ramrod->log_type_mask		= cpu_to_le16(0xf);

	if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits))
		p_ramrod->mf_mode = MF_OVLAN;
	else
		p_ramrod->mf_mode = MF_NPAR;

	p_ramrod->outer_tag_config.outer_tag.tci =
				cpu_to_le16(p_hwfn->hw_info.ovlan);
	if (test_bit(QED_MF_8021Q_TAGGING, &p_hwfn->cdev->mf_bits)) {
		p_ramrod->outer_tag_config.outer_tag.tpid = ETH_P_8021Q;
	} else if (test_bit(QED_MF_8021AD_TAGGING, &p_hwfn->cdev->mf_bits)) {
		p_ramrod->outer_tag_config.outer_tag.tpid = ETH_P_8021AD;
		p_ramrod->outer_tag_config.enable_stag_pri_change = 1;
	}

	p_ramrod->outer_tag_config.pri_map_valid = 1;
	for (i = 0; i < QED_MAX_PFC_PRIORITIES; i++)
		p_ramrod->outer_tag_config.inner_to_outer_pri_map[i] = i;

	/* enable_stag_pri_change should be set if port is in BD mode or,
	 * UFP with Host Control mode.
	 */
	if (test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits)) {
		if (p_hwfn->ufp_info.pri_type == QED_UFP_PRI_OS)
			p_ramrod->outer_tag_config.enable_stag_pri_change = 1;
		else
			p_ramrod->outer_tag_config.enable_stag_pri_change = 0;

		p_ramrod->outer_tag_config.outer_tag.tci |=
		    cpu_to_le16(((u16)p_hwfn->ufp_info.tc << 13));
	}

	/* Place EQ address in RAMROD */
	DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr,
		       p_hwfn->p_eq->chain.pbl_sp.p_phys_table);
	page_cnt = (u8)qed_chain_get_page_cnt(&p_hwfn->p_eq->chain);
	p_ramrod->event_ring_num_pages = page_cnt;
	DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_addr,
		       p_hwfn->p_consq->chain.pbl_sp.p_phys_table);

	qed_tunn_set_pf_start_params(p_hwfn, p_tunn, &p_ramrod->tunnel_config);

	if (test_bit(QED_MF_INTER_PF_SWITCH, &p_hwfn->cdev->mf_bits))
		p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch;

	switch (p_hwfn->hw_info.personality) {
	case QED_PCI_ETH:
		p_ramrod->personality = PERSONALITY_ETH;
		break;
	case QED_PCI_FCOE:
		p_ramrod->personality = PERSONALITY_FCOE;
		break;
	case QED_PCI_ISCSI:
		p_ramrod->personality = PERSONALITY_ISCSI;
		break;
	case QED_PCI_ETH_ROCE:
	case QED_PCI_ETH_IWARP:
		p_ramrod->personality = PERSONALITY_RDMA_AND_ETH;
		break;
	default:
		DP_NOTICE(p_hwfn, "Unknown personality %d\n",
			  p_hwfn->hw_info.personality);
		p_ramrod->personality = PERSONALITY_ETH;
	}

	if (p_hwfn->cdev->p_iov_info) {
		struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;

		p_ramrod->base_vf_id = (u8) p_iov->first_vf_in_pf;
		p_ramrod->num_vfs = (u8) p_iov->total_vfs;
	}
	p_ramrod->hsi_fp_ver.major_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MAJOR;
	p_ramrod->hsi_fp_ver.minor_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MINOR;

	DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
		   "Setting event_ring_sb [id %04x index %02x], outer_tag.tci [%d]\n",
		   sb, sb_index, p_ramrod->outer_tag_config.outer_tag.tci);

	rc = qed_spq_post(p_hwfn, p_ent, NULL);

	if (p_tunn)
		qed_set_hw_tunn_mode_port(p_hwfn, p_ptt,
					  &p_hwfn->cdev->tunnel);

	return rc;
}

int qed_sp_pf_update(struct qed_hwfn *p_hwfn)
{
	struct qed_spq_entry *p_ent = NULL;
	struct qed_sp_init_data init_data;
	int rc = -EINVAL;

	/* Get SPQ entry */
	memset(&init_data, 0, sizeof(init_data));
	init_data.cid = qed_spq_get_cid(p_hwfn);
	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	init_data.comp_mode = QED_SPQ_MODE_CB;

	rc = qed_sp_init_request(p_hwfn, &p_ent,
				 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
				 &init_data);
	if (rc)
		return rc;

	qed_dcbx_set_pf_update_params(&p_hwfn->p_dcbx_info->results,
				      &p_ent->ramrod.pf_update);

	return qed_spq_post(p_hwfn, p_ent, NULL);
}

int qed_sp_pf_update_ufp(struct qed_hwfn *p_hwfn)
{
	struct qed_spq_entry *p_ent = NULL;
	struct qed_sp_init_data init_data;
	int rc = -EOPNOTSUPP;

	if (p_hwfn->ufp_info.pri_type == QED_UFP_PRI_UNKNOWN) {
		DP_INFO(p_hwfn, "Invalid priority type %d\n",
			p_hwfn->ufp_info.pri_type);
		return -EINVAL;
	}

	/* Get SPQ entry */
	memset(&init_data, 0, sizeof(init_data));
	init_data.cid = qed_spq_get_cid(p_hwfn);
	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	init_data.comp_mode = QED_SPQ_MODE_CB;

	rc = qed_sp_init_request(p_hwfn, &p_ent,
				 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
				 &init_data);
	if (rc)
		return rc;

	p_ent->ramrod.pf_update.update_enable_stag_pri_change = true;
	if (p_hwfn->ufp_info.pri_type == QED_UFP_PRI_OS)
		p_ent->ramrod.pf_update.enable_stag_pri_change = 1;
	else
		p_ent->ramrod.pf_update.enable_stag_pri_change = 0;

	return qed_spq_post(p_hwfn, p_ent, NULL);
}

/* Set pf update ramrod command params */
int qed_sp_pf_update_tunn_cfg(struct qed_hwfn *p_hwfn,
			      struct qed_ptt *p_ptt,
			      struct qed_tunnel_info *p_tunn,
			      enum spq_mode comp_mode,
			      struct qed_spq_comp_cb *p_comp_data)
{
	struct qed_spq_entry *p_ent = NULL;
	struct qed_sp_init_data init_data;
	int rc = -EINVAL;

	if (IS_VF(p_hwfn->cdev))
		return qed_vf_pf_tunnel_param_update(p_hwfn, p_tunn);

	if (!p_tunn)
		return -EINVAL;

	/* Get SPQ entry */
	memset(&init_data, 0, sizeof(init_data));
	init_data.cid = qed_spq_get_cid(p_hwfn);
	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	init_data.comp_mode = comp_mode;
	init_data.p_comp_data = p_comp_data;

	rc = qed_sp_init_request(p_hwfn, &p_ent,
				 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
				 &init_data);
	if (rc)
		return rc;

	qed_tunn_set_pf_update_params(p_hwfn, p_tunn,
				      &p_ent->ramrod.pf_update.tunnel_config);

	rc = qed_spq_post(p_hwfn, p_ent, NULL);
	if (rc)
		return rc;

	qed_set_hw_tunn_mode_port(p_hwfn, p_ptt, &p_hwfn->cdev->tunnel);

	return rc;
}

int qed_sp_pf_stop(struct qed_hwfn *p_hwfn)
{
	struct qed_spq_entry *p_ent = NULL;
	struct qed_sp_init_data init_data;
	int rc = -EINVAL;

	/* Get SPQ entry */
	memset(&init_data, 0, sizeof(init_data));
	init_data.cid = qed_spq_get_cid(p_hwfn);
	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;

	rc = qed_sp_init_request(p_hwfn, &p_ent,
				 COMMON_RAMROD_PF_STOP, PROTOCOLID_COMMON,
				 &init_data);
	if (rc)
		return rc;

	return qed_spq_post(p_hwfn, p_ent, NULL);
}

int qed_sp_heartbeat_ramrod(struct qed_hwfn *p_hwfn)
{
	struct qed_spq_entry *p_ent = NULL;
	struct qed_sp_init_data init_data;
	int rc;

	/* Get SPQ entry */
	memset(&init_data, 0, sizeof(init_data));
	init_data.cid = qed_spq_get_cid(p_hwfn);
	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;

	rc = qed_sp_init_request(p_hwfn, &p_ent,
				 COMMON_RAMROD_EMPTY, PROTOCOLID_COMMON,
				 &init_data);
	if (rc)
		return rc;

	return qed_spq_post(p_hwfn, p_ent, NULL);
}

int qed_sp_pf_update_stag(struct qed_hwfn *p_hwfn)
{
	struct qed_spq_entry *p_ent = NULL;
	struct qed_sp_init_data init_data;
	int rc = -EINVAL;

	/* Get SPQ entry */
	memset(&init_data, 0, sizeof(init_data));
	init_data.cid = qed_spq_get_cid(p_hwfn);
	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	init_data.comp_mode = QED_SPQ_MODE_CB;

	rc = qed_sp_init_request(p_hwfn, &p_ent,
				 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
				 &init_data);
	if (rc)
		return rc;

	p_ent->ramrod.pf_update.update_mf_vlan_flag = true;
	p_ent->ramrod.pf_update.mf_vlan = cpu_to_le16(p_hwfn->hw_info.ovlan);

	return qed_spq_post(p_hwfn, p_ent, NULL);
}
Commit	Line	Data
fe56b9e6	1	/* QLogic qed NIC Driver
e8f1cb50	2	* Copyright (c) 2015-2017 QLogic Corporation
fe56b9e6	3	*
e8f1cb50 MY	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and /or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
fe56b9e6 YM	31	*/
	32
	33	#include <linux/types.h>
	34	#include <asm/byteorder.h>
	35	#include <linux/bitops.h>
	36	#include <linux/errno.h>
	37	#include <linux/kernel.h>
	38	#include <linux/string.h>
	39	#include "qed.h"
	40	#include <linux/qed/qed_chain.h>
	41	#include "qed_cxt.h"
39651abd	42	#include "qed_dcbx.h"
fe56b9e6 YM	43	#include "qed_hsi.h"
	44	#include "qed_hw.h"
	45	#include "qed_int.h"
	46	#include "qed_reg_addr.h"
	47	#include "qed_sp.h"
1408cc1f	48	#include "qed_sriov.h"
fe56b9e6	49
fb5e7438 DB	50	void qed_sp_destroy_request(struct qed_hwfn *p_hwfn,
	51	struct qed_spq_entry *p_ent)
	52	{
	53	/* qed_spq_get_entry() can either get an entry from the free_pool,
	54	* or, if no entries are left, allocate a new entry and add it to
	55	* the unlimited_pending list.
	56	*/
	57	if (p_ent->queue == &p_hwfn->p_spq->unlimited_pending)
	58	kfree(p_ent);
	59	else
	60	qed_spq_return_entry(p_hwfn, p_ent);
	61	}
	62
fe56b9e6 YM	63	int qed_sp_init_request(struct qed_hwfn *p_hwfn,
fe56b9e6 YM	64	struct qed_spq_entry **pp_ent,
1a635e48	65	u8 cmd, u8 protocol, struct qed_sp_init_data *p_data)
fe56b9e6	66	{
06f56b81	67	u32 opaque_cid = p_data->opaque_fid << 16 \| p_data->cid;
fe56b9e6	68	struct qed_spq_entry *p_ent = NULL;
06f56b81	69	int rc;
fe56b9e6 YM	70
	71	if (!pp_ent)
	72	return -ENOMEM;
	73
	74	rc = qed_spq_get_entry(p_hwfn, pp_ent);
	75
1a635e48	76	if (rc)
fe56b9e6 YM	77	return rc;
	78
	79	p_ent = *pp_ent;
	80
	81	p_ent->elem.hdr.cid = cpu_to_le32(opaque_cid);
	82	p_ent->elem.hdr.cmd_id = cmd;
	83	p_ent->elem.hdr.protocol_id = protocol;
	84
	85	p_ent->priority = QED_SPQ_PRIORITY_NORMAL;
06f56b81	86	p_ent->comp_mode = p_data->comp_mode;
fe56b9e6 YM	87	p_ent->comp_done.done = 0;
	88
	89	switch (p_ent->comp_mode) {
	90	case QED_SPQ_MODE_EBLOCK:
	91	p_ent->comp_cb.cookie = &p_ent->comp_done;
	92	break;
	93
	94	case QED_SPQ_MODE_BLOCK:
06f56b81	95	if (!p_data->p_comp_data)
39477551	96	goto err;
fe56b9e6	97
06f56b81	98	p_ent->comp_cb.cookie = p_data->p_comp_data->cookie;
fe56b9e6 YM	99	break;
	100
	101	case QED_SPQ_MODE_CB:
06f56b81	102	if (!p_data->p_comp_data)
fe56b9e6 YM	103	p_ent->comp_cb.function = NULL;
fe56b9e6 YM	104	else
06f56b81	105	p_ent->comp_cb = *p_data->p_comp_data;
fe56b9e6 YM	106	break;
	107
	108	default:
	109	DP_NOTICE(p_hwfn, "Unknown SPQE completion mode %d\n",
	110	p_ent->comp_mode);
39477551	111	goto err;
fe56b9e6 YM	112	}
	113
	114	DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
	115	"Initialized: CID %08x cmd %02x protocol %02x data_addr %lu comp_mode [%s]\n",
	116	opaque_cid, cmd, protocol,
	117	(unsigned long)&p_ent->ramrod,
	118	D_TRINE(p_ent->comp_mode, QED_SPQ_MODE_EBLOCK,
	119	QED_SPQ_MODE_BLOCK, "MODE_EBLOCK", "MODE_BLOCK",
	120	"MODE_CB"));
06f56b81 YM	121
06f56b81 YM	122	memset(&p_ent->ramrod, 0, sizeof(p_ent->ramrod));
fe56b9e6 YM	123
fe56b9e6 YM	124	return 0;
39477551 DB	125
39477551 DB	126	err:
fb5e7438	127	qed_sp_destroy_request(p_hwfn, p_ent);
39477551 DB	128
39477551 DB	129	return -EINVAL;
fe56b9e6 YM	130	}
fe56b9e6 YM	131
19968430	132	static enum tunnel_clss qed_tunn_clss_to_fw_clss(u8 type)
464f6645 MC	133	{
	134	switch (type) {
	135	case QED_TUNN_CLSS_MAC_VLAN:
	136	return TUNNEL_CLSS_MAC_VLAN;
	137	case QED_TUNN_CLSS_MAC_VNI:
	138	return TUNNEL_CLSS_MAC_VNI;
	139	case QED_TUNN_CLSS_INNER_MAC_VLAN:
	140	return TUNNEL_CLSS_INNER_MAC_VLAN;
	141	case QED_TUNN_CLSS_INNER_MAC_VNI:
	142	return TUNNEL_CLSS_INNER_MAC_VNI;
19968430 CM	143	case QED_TUNN_CLSS_MAC_VLAN_DUAL_STAGE:
19968430 CM	144	return TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE;
464f6645 MC	145	default:
	146	return TUNNEL_CLSS_MAC_VLAN;
	147	}
	148	}
	149
	150	static void
19968430 CM	151	qed_set_pf_update_tunn_mode(struct qed_tunnel_info *p_tun,
19968430 CM	152	struct qed_tunnel_info *p_src, bool b_pf_start)
464f6645	153	{
19968430 CM	154	if (p_src->vxlan.b_update_mode \|\| b_pf_start)
19968430 CM	155	p_tun->vxlan.b_mode_enabled = p_src->vxlan.b_mode_enabled;
464f6645	156
19968430 CM	157	if (p_src->l2_gre.b_update_mode \|\| b_pf_start)
19968430 CM	158	p_tun->l2_gre.b_mode_enabled = p_src->l2_gre.b_mode_enabled;
464f6645	159
19968430 CM	160	if (p_src->ip_gre.b_update_mode \|\| b_pf_start)
19968430 CM	161	p_tun->ip_gre.b_mode_enabled = p_src->ip_gre.b_mode_enabled;
464f6645	162
19968430 CM	163	if (p_src->l2_geneve.b_update_mode \|\| b_pf_start)
	164	p_tun->l2_geneve.b_mode_enabled =
	165	p_src->l2_geneve.b_mode_enabled;
464f6645	166
19968430 CM	167	if (p_src->ip_geneve.b_update_mode \|\| b_pf_start)
	168	p_tun->ip_geneve.b_mode_enabled =
	169	p_src->ip_geneve.b_mode_enabled;
464f6645 MC	170	}
464f6645 MC	171
19968430 CM	172	static void qed_set_tunn_cls_info(struct qed_tunnel_info *p_tun,
19968430 CM	173	struct qed_tunnel_info *p_src)
464f6645	174	{
a898fba3	175	int type;
464f6645	176
19968430 CM	177	p_tun->b_update_rx_cls = p_src->b_update_rx_cls;
	178	p_tun->b_update_tx_cls = p_src->b_update_tx_cls;
	179
	180	type = qed_tunn_clss_to_fw_clss(p_src->vxlan.tun_cls);
	181	p_tun->vxlan.tun_cls = type;
	182	type = qed_tunn_clss_to_fw_clss(p_src->l2_gre.tun_cls);
	183	p_tun->l2_gre.tun_cls = type;
	184	type = qed_tunn_clss_to_fw_clss(p_src->ip_gre.tun_cls);
	185	p_tun->ip_gre.tun_cls = type;
	186	type = qed_tunn_clss_to_fw_clss(p_src->l2_geneve.tun_cls);
	187	p_tun->l2_geneve.tun_cls = type;
	188	type = qed_tunn_clss_to_fw_clss(p_src->ip_geneve.tun_cls);
	189	p_tun->ip_geneve.tun_cls = type;
	190	}
464f6645	191
19968430 CM	192	static void qed_set_tunn_ports(struct qed_tunnel_info *p_tun,
	193	struct qed_tunnel_info *p_src)
	194	{
	195	p_tun->geneve_port.b_update_port = p_src->geneve_port.b_update_port;
	196	p_tun->vxlan_port.b_update_port = p_src->vxlan_port.b_update_port;
464f6645	197
19968430 CM	198	if (p_src->geneve_port.b_update_port)
19968430 CM	199	p_tun->geneve_port.port = p_src->geneve_port.port;
464f6645	200
19968430 CM	201	if (p_src->vxlan_port.b_update_port)
	202	p_tun->vxlan_port.port = p_src->vxlan_port.port;
	203	}
464f6645	204
19968430	205	static void
7b6859fb	206	__qed_set_ramrod_tunnel_param(u8 *p_tunn_cls,
19968430 CM	207	struct qed_tunn_update_type *tun_type)
	208	{
	209	*p_tunn_cls = tun_type->tun_cls;
19968430	210	}
464f6645	211
19968430	212	static void
7b6859fb	213	qed_set_ramrod_tunnel_param(u8 *p_tunn_cls,
19968430	214	struct qed_tunn_update_type *tun_type,
7b6859fb MY	215	u8 *p_update_port,
7b6859fb MY	216	__le16 *p_port,
19968430 CM	217	struct qed_tunn_update_udp_port *p_udp_port)
19968430 CM	218	{
7b6859fb	219	__qed_set_ramrod_tunnel_param(p_tunn_cls, tun_type);
19968430 CM	220	if (p_udp_port->b_update_port) {
	221	*p_update_port = 1;
	222	*p_port = cpu_to_le16(p_udp_port->port);
464f6645	223	}
19968430	224	}
464f6645	225
19968430 CM	226	static void
	227	qed_tunn_set_pf_update_params(struct qed_hwfn *p_hwfn,
	228	struct qed_tunnel_info *p_src,
	229	struct pf_update_tunnel_config *p_tunn_cfg)
	230	{
	231	struct qed_tunnel_info *p_tun = &p_hwfn->cdev->tunnel;
	232
	233	qed_set_pf_update_tunn_mode(p_tun, p_src, false);
	234	qed_set_tunn_cls_info(p_tun, p_src);
	235	qed_set_tunn_ports(p_tun, p_src);
	236
	237	qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan,
19968430 CM	238	&p_tun->vxlan,
	239	&p_tunn_cfg->set_vxlan_udp_port_flg,
	240	&p_tunn_cfg->vxlan_udp_port,
	241	&p_tun->vxlan_port);
	242
	243	qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve,
19968430 CM	244	&p_tun->l2_geneve,
	245	&p_tunn_cfg->set_geneve_udp_port_flg,
	246	&p_tunn_cfg->geneve_udp_port,
	247	&p_tun->geneve_port);
	248
	249	__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve,
19968430 CM	250	&p_tun->ip_geneve);
	251
	252	__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre,
19968430 CM	253	&p_tun->l2_gre);
	254
	255	__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre,
19968430 CM	256	&p_tun->ip_gre);
	257
	258	p_tunn_cfg->update_rx_pf_clss = p_tun->b_update_rx_cls;
464f6645 MC	259	}
	260
	261	static void qed_set_hw_tunn_mode(struct qed_hwfn *p_hwfn,
	262	struct qed_ptt *p_ptt,
19968430	263	struct qed_tunnel_info *p_tun)
464f6645	264	{
19968430 CM	265	qed_set_gre_enable(p_hwfn, p_ptt, p_tun->l2_gre.b_mode_enabled,
	266	p_tun->ip_gre.b_mode_enabled);
	267	qed_set_vxlan_enable(p_hwfn, p_ptt, p_tun->vxlan.b_mode_enabled);
464f6645	268
19968430 CM	269	qed_set_geneve_enable(p_hwfn, p_ptt, p_tun->l2_geneve.b_mode_enabled,
	270	p_tun->ip_geneve.b_mode_enabled);
	271	}
464f6645	272
19968430	273	static void qed_set_hw_tunn_mode_port(struct qed_hwfn *p_hwfn,
4f64675f	274	struct qed_ptt *p_ptt,
19968430 CM	275	struct qed_tunnel_info *p_tunn)
	276	{
	277	if (p_tunn->vxlan_port.b_update_port)
4f64675f	278	qed_set_vxlan_dest_port(p_hwfn, p_ptt,
19968430	279	p_tunn->vxlan_port.port);
464f6645	280
19968430	281	if (p_tunn->geneve_port.b_update_port)
4f64675f	282	qed_set_geneve_dest_port(p_hwfn, p_ptt,
19968430	283	p_tunn->geneve_port.port);
464f6645	284
4f64675f	285	qed_set_hw_tunn_mode(p_hwfn, p_ptt, p_tunn);
464f6645 MC	286	}
	287
	288	static void
	289	qed_tunn_set_pf_start_params(struct qed_hwfn *p_hwfn,
19968430	290	struct qed_tunnel_info *p_src,
464f6645 MC	291	struct pf_start_tunnel_config *p_tunn_cfg)
464f6645 MC	292	{
19968430	293	struct qed_tunnel_info *p_tun = &p_hwfn->cdev->tunnel;
464f6645 MC	294
	295	if (!p_src)
	296	return;
	297
19968430 CM	298	qed_set_pf_update_tunn_mode(p_tun, p_src, true);
	299	qed_set_tunn_cls_info(p_tun, p_src);
	300	qed_set_tunn_ports(p_tun, p_src);
	301
	302	qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan,
19968430 CM	303	&p_tun->vxlan,
	304	&p_tunn_cfg->set_vxlan_udp_port_flg,
	305	&p_tunn_cfg->vxlan_udp_port,
	306	&p_tun->vxlan_port);
	307
	308	qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve,
19968430 CM	309	&p_tun->l2_geneve,
	310	&p_tunn_cfg->set_geneve_udp_port_flg,
	311	&p_tunn_cfg->geneve_udp_port,
	312	&p_tun->geneve_port);
	313
	314	__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve,
19968430 CM	315	&p_tun->ip_geneve);
	316
	317	__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre,
19968430 CM	318	&p_tun->l2_gre);
	319
	320	__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre,
19968430	321	&p_tun->ip_gre);
464f6645 MC	322	}
464f6645 MC	323
fe56b9e6	324	int qed_sp_pf_start(struct qed_hwfn *p_hwfn,
4f64675f	325	struct qed_ptt *p_ptt,
19968430	326	struct qed_tunnel_info *p_tunn,
0bc5fe85	327	bool allow_npar_tx_switch)
fe56b9e6	328	{
fe56b9e6 YM	329	struct pf_start_ramrod_data *p_ramrod = NULL;
	330	u16 sb = qed_int_get_sp_sb_id(p_hwfn);
	331	u8 sb_index = p_hwfn->p_eq->eq_sb_index;
	332	struct qed_spq_entry *p_ent = NULL;
06f56b81	333	struct qed_sp_init_data init_data;
fe56b9e6	334	int rc = -EINVAL;
cac6f691	335	u8 page_cnt, i;
fe56b9e6 YM	336
	337	/* update initial eq producer */
	338	qed_eq_prod_update(p_hwfn,
	339	qed_chain_get_prod_idx(&p_hwfn->p_eq->chain));
	340
06f56b81 YM	341	memset(&init_data, 0, sizeof(init_data));
	342	init_data.cid = qed_spq_get_cid(p_hwfn);
	343	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	344	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
fe56b9e6	345
06f56b81	346	rc = qed_sp_init_request(p_hwfn, &p_ent,
fe56b9e6	347	COMMON_RAMROD_PF_START,
1a635e48	348	PROTOCOLID_COMMON, &init_data);
fe56b9e6 YM	349	if (rc)
	350	return rc;
	351
	352	p_ramrod = &p_ent->ramrod.pf_start;
	353
	354	p_ramrod->event_ring_sb_id = cpu_to_le16(sb);
	355	p_ramrod->event_ring_sb_index = sb_index;
	356	p_ramrod->path_id = QED_PATH_ID(p_hwfn);
	357	p_ramrod->dont_log_ramrods = 0;
	358	p_ramrod->log_type_mask = cpu_to_le16(0xf);
351a4ded	359
0bc5fe85	360	if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits))
fc48b7a6	361	p_ramrod->mf_mode = MF_OVLAN;
0bc5fe85	362	else
fc48b7a6	363	p_ramrod->mf_mode = MF_NPAR;
da090917 TT	364
da090917 TT	365	p_ramrod->outer_tag_config.outer_tag.tci =
cac6f691 SRK	366	cpu_to_le16(p_hwfn->hw_info.ovlan);
	367	if (test_bit(QED_MF_8021Q_TAGGING, &p_hwfn->cdev->mf_bits)) {
	368	p_ramrod->outer_tag_config.outer_tag.tpid = ETH_P_8021Q;
	369	} else if (test_bit(QED_MF_8021AD_TAGGING, &p_hwfn->cdev->mf_bits)) {
b51bdfb9 SRK	370	p_ramrod->outer_tag_config.outer_tag.tpid = ETH_P_8021AD;
	371	p_ramrod->outer_tag_config.enable_stag_pri_change = 1;
	372	}
	373
cac6f691 SRK	374	p_ramrod->outer_tag_config.pri_map_valid = 1;
	375	for (i = 0; i < QED_MAX_PFC_PRIORITIES; i++)
	376	p_ramrod->outer_tag_config.inner_to_outer_pri_map[i] = i;
	377
	378	/* enable_stag_pri_change should be set if port is in BD mode or,
	379	* UFP with Host Control mode.
	380	*/
	381	if (test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits)) {
	382	if (p_hwfn->ufp_info.pri_type == QED_UFP_PRI_OS)
	383	p_ramrod->outer_tag_config.enable_stag_pri_change = 1;
	384	else
	385	p_ramrod->outer_tag_config.enable_stag_pri_change = 0;
	386
	387	p_ramrod->outer_tag_config.outer_tag.tci \|=
	388	cpu_to_le16(((u16)p_hwfn->ufp_info.tc << 13));
	389	}
fe56b9e6 YM	390
fe56b9e6 YM	391	/* Place EQ address in RAMROD */
94494598	392	DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr,
6d937acf	393	p_hwfn->p_eq->chain.pbl_sp.p_phys_table);
a91eb52a YM	394	page_cnt = (u8)qed_chain_get_page_cnt(&p_hwfn->p_eq->chain);
a91eb52a YM	395	p_ramrod->event_ring_num_pages = page_cnt;
94494598	396	DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_addr,
6d937acf	397	p_hwfn->p_consq->chain.pbl_sp.p_phys_table);
fe56b9e6	398
1a635e48	399	qed_tunn_set_pf_start_params(p_hwfn, p_tunn, &p_ramrod->tunnel_config);
fe56b9e6	400
0bc5fe85	401	if (test_bit(QED_MF_INTER_PF_SWITCH, &p_hwfn->cdev->mf_bits))
831bfb0e YM	402	p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch;
831bfb0e YM	403
c5ac9319 YM	404	switch (p_hwfn->hw_info.personality) {
	405	case QED_PCI_ETH:
	406	p_ramrod->personality = PERSONALITY_ETH;
	407	break;
1e128c81 AE	408	case QED_PCI_FCOE:
	409	p_ramrod->personality = PERSONALITY_FCOE;
	410	break;
c5ac9319 YM	411	case QED_PCI_ISCSI:
	412	p_ramrod->personality = PERSONALITY_ISCSI;
	413	break;
	414	case QED_PCI_ETH_ROCE:
e0a8f9de	415	case QED_PCI_ETH_IWARP:
c5ac9319 YM	416	p_ramrod->personality = PERSONALITY_RDMA_AND_ETH;
	417	break;
	418	default:
9165dabb	419	DP_NOTICE(p_hwfn, "Unknown personality %d\n",
c5ac9319 YM	420	p_hwfn->hw_info.personality);
	421	p_ramrod->personality = PERSONALITY_ETH;
	422	}
	423
1408cc1f YM	424	if (p_hwfn->cdev->p_iov_info) {
	425	struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
	426
	427	p_ramrod->base_vf_id = (u8) p_iov->first_vf_in_pf;
	428	p_ramrod->num_vfs = (u8) p_iov->total_vfs;
	429	}
351a4ded YM	430	p_ramrod->hsi_fp_ver.major_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MAJOR;
351a4ded YM	431	p_ramrod->hsi_fp_ver.minor_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MINOR;
1408cc1f	432
fe56b9e6	433	DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
da090917 TT	434	"Setting event_ring_sb [id %04x index %02x], outer_tag.tci [%d]\n",
da090917 TT	435	sb, sb_index, p_ramrod->outer_tag_config.outer_tag.tci);
fe56b9e6	436
c0f31a05 MC	437	rc = qed_spq_post(p_hwfn, p_ent, NULL);
c0f31a05 MC	438
19968430	439	if (p_tunn)
4f64675f MC	440	qed_set_hw_tunn_mode_port(p_hwfn, p_ptt,
4f64675f MC	441	&p_hwfn->cdev->tunnel);
c0f31a05 MC	442
c0f31a05 MC	443	return rc;
fe56b9e6 YM	444	}
fe56b9e6 YM	445
39651abd SRK	446	int qed_sp_pf_update(struct qed_hwfn *p_hwfn)
	447	{
	448	struct qed_spq_entry *p_ent = NULL;
	449	struct qed_sp_init_data init_data;
	450	int rc = -EINVAL;
	451
	452	/* Get SPQ entry */
	453	memset(&init_data, 0, sizeof(init_data));
	454	init_data.cid = qed_spq_get_cid(p_hwfn);
	455	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	456	init_data.comp_mode = QED_SPQ_MODE_CB;
	457
	458	rc = qed_sp_init_request(p_hwfn, &p_ent,
	459	COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
	460	&init_data);
	461	if (rc)
	462	return rc;
	463
	464	qed_dcbx_set_pf_update_params(&p_hwfn->p_dcbx_info->results,
	465	&p_ent->ramrod.pf_update);
	466
	467	return qed_spq_post(p_hwfn, p_ent, NULL);
	468	}
	469
cac6f691 SRK	470	int qed_sp_pf_update_ufp(struct qed_hwfn *p_hwfn)
	471	{
	472	struct qed_spq_entry *p_ent = NULL;
	473	struct qed_sp_init_data init_data;
	474	int rc = -EOPNOTSUPP;
	475
	476	if (p_hwfn->ufp_info.pri_type == QED_UFP_PRI_UNKNOWN) {
	477	DP_INFO(p_hwfn, "Invalid priority type %d\n",
	478	p_hwfn->ufp_info.pri_type);
	479	return -EINVAL;
	480	}
	481
	482	/* Get SPQ entry */
	483	memset(&init_data, 0, sizeof(init_data));
	484	init_data.cid = qed_spq_get_cid(p_hwfn);
	485	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	486	init_data.comp_mode = QED_SPQ_MODE_CB;
	487
	488	rc = qed_sp_init_request(p_hwfn, &p_ent,
	489	COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
	490	&init_data);
	491	if (rc)
	492	return rc;
	493
	494	p_ent->ramrod.pf_update.update_enable_stag_pri_change = true;
	495	if (p_hwfn->ufp_info.pri_type == QED_UFP_PRI_OS)
	496	p_ent->ramrod.pf_update.enable_stag_pri_change = 1;
	497	else
	498	p_ent->ramrod.pf_update.enable_stag_pri_change = 0;
	499
	500	return qed_spq_post(p_hwfn, p_ent, NULL);
	501	}
	502
464f6645 MC	503	/* Set pf update ramrod command params */
464f6645 MC	504	int qed_sp_pf_update_tunn_cfg(struct qed_hwfn *p_hwfn,
4f64675f	505	struct qed_ptt *p_ptt,
19968430	506	struct qed_tunnel_info *p_tunn,
464f6645 MC	507	enum spq_mode comp_mode,
	508	struct qed_spq_comp_cb *p_comp_data)
	509	{
	510	struct qed_spq_entry *p_ent = NULL;
	511	struct qed_sp_init_data init_data;
	512	int rc = -EINVAL;
	513
eaf3c0c6 CM	514	if (IS_VF(p_hwfn->cdev))
	515	return qed_vf_pf_tunnel_param_update(p_hwfn, p_tunn);
	516
19968430 CM	517	if (!p_tunn)
	518	return -EINVAL;
	519
464f6645 MC	520	/* Get SPQ entry */
	521	memset(&init_data, 0, sizeof(init_data));
	522	init_data.cid = qed_spq_get_cid(p_hwfn);
	523	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	524	init_data.comp_mode = comp_mode;
	525	init_data.p_comp_data = p_comp_data;
	526
	527	rc = qed_sp_init_request(p_hwfn, &p_ent,
	528	COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
	529	&init_data);
	530	if (rc)
	531	return rc;
	532
	533	qed_tunn_set_pf_update_params(p_hwfn, p_tunn,
	534	&p_ent->ramrod.pf_update.tunnel_config);
	535
	536	rc = qed_spq_post(p_hwfn, p_ent, NULL);
	537	if (rc)
	538	return rc;
	539
4f64675f	540	qed_set_hw_tunn_mode_port(p_hwfn, p_ptt, &p_hwfn->cdev->tunnel);
464f6645 MC	541
	542	return rc;
	543	}
	544
fe56b9e6 YM	545	int qed_sp_pf_stop(struct qed_hwfn *p_hwfn)
fe56b9e6 YM	546	{
fe56b9e6	547	struct qed_spq_entry *p_ent = NULL;
06f56b81	548	struct qed_sp_init_data init_data;
fe56b9e6 YM	549	int rc = -EINVAL;
fe56b9e6 YM	550
06f56b81 YM	551	/* Get SPQ entry */
	552	memset(&init_data, 0, sizeof(init_data));
	553	init_data.cid = qed_spq_get_cid(p_hwfn);
	554	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	555	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
fe56b9e6	556
06f56b81	557	rc = qed_sp_init_request(p_hwfn, &p_ent,
fe56b9e6	558	COMMON_RAMROD_PF_STOP, PROTOCOLID_COMMON,
06f56b81	559	&init_data);
fe56b9e6 YM	560	if (rc)
	561	return rc;
	562
	563	return qed_spq_post(p_hwfn, p_ent, NULL);
	564	}
03dc76ca SRK	565
	566	int qed_sp_heartbeat_ramrod(struct qed_hwfn *p_hwfn)
	567	{
	568	struct qed_spq_entry *p_ent = NULL;
	569	struct qed_sp_init_data init_data;
	570	int rc;
	571
	572	/* Get SPQ entry */
	573	memset(&init_data, 0, sizeof(init_data));
	574	init_data.cid = qed_spq_get_cid(p_hwfn);
	575	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	576	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
	577
	578	rc = qed_sp_init_request(p_hwfn, &p_ent,
	579	COMMON_RAMROD_EMPTY, PROTOCOLID_COMMON,
	580	&init_data);
	581	if (rc)
	582	return rc;
	583
	584	return qed_spq_post(p_hwfn, p_ent, NULL);
	585	}
2a351fd9 MY	586
	587	int qed_sp_pf_update_stag(struct qed_hwfn *p_hwfn)
	588	{
	589	struct qed_spq_entry *p_ent = NULL;
	590	struct qed_sp_init_data init_data;
	591	int rc = -EINVAL;
	592
	593	/* Get SPQ entry */
	594	memset(&init_data, 0, sizeof(init_data));
	595	init_data.cid = qed_spq_get_cid(p_hwfn);
	596	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	597	init_data.comp_mode = QED_SPQ_MODE_CB;
	598
	599	rc = qed_sp_init_request(p_hwfn, &p_ent,
	600	COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
	601	&init_data);
	602	if (rc)
	603	return rc;
	604
	605	p_ent->ramrod.pf_update.update_mf_vlan_flag = true;
	606	p_ent->ramrod.pf_update.mf_vlan = cpu_to_le16(p_hwfn->hw_info.ovlan);
	607
	608	return qed_spq_post(p_hwfn, p_ent, NULL);
	609	}