[linux-2.6-block.git] / drivers / net / ethernet / qlogic / qed / qed_sp_commands.c

/* QLogic qed NIC Driver
 * Copyright (c) 2015-2017  QLogic Corporation
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and /or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include <linux/types.h>
#include <asm/byteorder.h>
#include <linux/bitops.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include "qed.h"
#include <linux/qed/qed_chain.h>
#include "qed_cxt.h"
#include "qed_dcbx.h"
#include "qed_hsi.h"
#include "qed_hw.h"
#include "qed_int.h"
#include "qed_reg_addr.h"
#include "qed_sp.h"
#include "qed_sriov.h"

int qed_sp_init_request(struct qed_hwfn *p_hwfn,
			struct qed_spq_entry **pp_ent,
			u8 cmd, u8 protocol, struct qed_sp_init_data *p_data)
{
	u32 opaque_cid = p_data->opaque_fid << 16 | p_data->cid;
	struct qed_spq_entry *p_ent = NULL;
	int rc;

	if (!pp_ent)
		return -ENOMEM;

	rc = qed_spq_get_entry(p_hwfn, pp_ent);

	if (rc)
		return rc;

	p_ent = *pp_ent;

	p_ent->elem.hdr.cid		= cpu_to_le32(opaque_cid);
	p_ent->elem.hdr.cmd_id		= cmd;
	p_ent->elem.hdr.protocol_id	= protocol;

	p_ent->priority		= QED_SPQ_PRIORITY_NORMAL;
	p_ent->comp_mode	= p_data->comp_mode;
	p_ent->comp_done.done	= 0;

	switch (p_ent->comp_mode) {
	case QED_SPQ_MODE_EBLOCK:
		p_ent->comp_cb.cookie = &p_ent->comp_done;
		break;

	case QED_SPQ_MODE_BLOCK:
		if (!p_data->p_comp_data)
			return -EINVAL;

		p_ent->comp_cb.cookie = p_data->p_comp_data->cookie;
		break;

	case QED_SPQ_MODE_CB:
		if (!p_data->p_comp_data)
			p_ent->comp_cb.function = NULL;
		else
			p_ent->comp_cb = *p_data->p_comp_data;
		break;

	default:
		DP_NOTICE(p_hwfn, "Unknown SPQE completion mode %d\n",
			  p_ent->comp_mode);
		return -EINVAL;
	}

	DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
		   "Initialized: CID %08x cmd %02x protocol %02x data_addr %lu comp_mode [%s]\n",
		   opaque_cid, cmd, protocol,
		   (unsigned long)&p_ent->ramrod,
		   D_TRINE(p_ent->comp_mode, QED_SPQ_MODE_EBLOCK,
			   QED_SPQ_MODE_BLOCK, "MODE_EBLOCK", "MODE_BLOCK",
			   "MODE_CB"));

	memset(&p_ent->ramrod, 0, sizeof(p_ent->ramrod));

	return 0;
}

static enum tunnel_clss qed_tunn_get_clss_type(u8 type)
{
	switch (type) {
	case QED_TUNN_CLSS_MAC_VLAN:
		return TUNNEL_CLSS_MAC_VLAN;
	case QED_TUNN_CLSS_MAC_VNI:
		return TUNNEL_CLSS_MAC_VNI;
	case QED_TUNN_CLSS_INNER_MAC_VLAN:
		return TUNNEL_CLSS_INNER_MAC_VLAN;
	case QED_TUNN_CLSS_INNER_MAC_VNI:
		return TUNNEL_CLSS_INNER_MAC_VNI;
	default:
		return TUNNEL_CLSS_MAC_VLAN;
	}
}

static void
qed_tunn_set_pf_fix_tunn_mode(struct qed_hwfn *p_hwfn,
			      struct qed_tunn_update_params *p_src,
			      struct pf_update_tunnel_config *p_tunn_cfg)
{
	unsigned long cached_tunn_mode = p_hwfn->cdev->tunn_mode;
	unsigned long update_mask = p_src->tunn_mode_update_mask;
	unsigned long tunn_mode = p_src->tunn_mode;
	unsigned long new_tunn_mode = 0;

	if (test_bit(QED_MODE_L2GRE_TUNN, &update_mask)) {
		if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
			__set_bit(QED_MODE_L2GRE_TUNN, &new_tunn_mode);
	} else {
		if (test_bit(QED_MODE_L2GRE_TUNN, &cached_tunn_mode))
			__set_bit(QED_MODE_L2GRE_TUNN, &new_tunn_mode);
	}

	if (test_bit(QED_MODE_IPGRE_TUNN, &update_mask)) {
		if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
			__set_bit(QED_MODE_IPGRE_TUNN, &new_tunn_mode);
	} else {
		if (test_bit(QED_MODE_IPGRE_TUNN, &cached_tunn_mode))
			__set_bit(QED_MODE_IPGRE_TUNN, &new_tunn_mode);
	}

	if (test_bit(QED_MODE_VXLAN_TUNN, &update_mask)) {
		if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
			__set_bit(QED_MODE_VXLAN_TUNN, &new_tunn_mode);
	} else {
		if (test_bit(QED_MODE_VXLAN_TUNN, &cached_tunn_mode))
			__set_bit(QED_MODE_VXLAN_TUNN, &new_tunn_mode);
	}

	if (p_src->update_geneve_udp_port) {
		p_tunn_cfg->set_geneve_udp_port_flg = 1;
		p_tunn_cfg->geneve_udp_port =
				cpu_to_le16(p_src->geneve_udp_port);
	}

	if (test_bit(QED_MODE_L2GENEVE_TUNN, &update_mask)) {
		if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
			__set_bit(QED_MODE_L2GENEVE_TUNN, &new_tunn_mode);
	} else {
		if (test_bit(QED_MODE_L2GENEVE_TUNN, &cached_tunn_mode))
			__set_bit(QED_MODE_L2GENEVE_TUNN, &new_tunn_mode);
	}

	if (test_bit(QED_MODE_IPGENEVE_TUNN, &update_mask)) {
		if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
			__set_bit(QED_MODE_IPGENEVE_TUNN, &new_tunn_mode);
	} else {
		if (test_bit(QED_MODE_IPGENEVE_TUNN, &cached_tunn_mode))
			__set_bit(QED_MODE_IPGENEVE_TUNN, &new_tunn_mode);
	}

	p_src->tunn_mode = new_tunn_mode;
}

static void
qed_tunn_set_pf_update_params(struct qed_hwfn *p_hwfn,
			      struct qed_tunn_update_params *p_src,
			      struct pf_update_tunnel_config *p_tunn_cfg)
{
	unsigned long tunn_mode = p_src->tunn_mode;
	enum tunnel_clss type;

	qed_tunn_set_pf_fix_tunn_mode(p_hwfn, p_src, p_tunn_cfg);
	p_tunn_cfg->update_rx_pf_clss = p_src->update_rx_pf_clss;
	p_tunn_cfg->update_tx_pf_clss = p_src->update_tx_pf_clss;

	type = qed_tunn_get_clss_type(p_src->tunn_clss_vxlan);
	p_tunn_cfg->tunnel_clss_vxlan  = type;

	type = qed_tunn_get_clss_type(p_src->tunn_clss_l2gre);
	p_tunn_cfg->tunnel_clss_l2gre = type;

	type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgre);
	p_tunn_cfg->tunnel_clss_ipgre = type;

	if (p_src->update_vxlan_udp_port) {
		p_tunn_cfg->set_vxlan_udp_port_flg = 1;
		p_tunn_cfg->vxlan_udp_port = cpu_to_le16(p_src->vxlan_udp_port);
	}

	if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
		p_tunn_cfg->tx_enable_l2gre = 1;

	if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
		p_tunn_cfg->tx_enable_ipgre = 1;

	if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
		p_tunn_cfg->tx_enable_vxlan = 1;

	if (p_src->update_geneve_udp_port) {
		p_tunn_cfg->set_geneve_udp_port_flg = 1;
		p_tunn_cfg->geneve_udp_port =
				cpu_to_le16(p_src->geneve_udp_port);
	}

	if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
		p_tunn_cfg->tx_enable_l2geneve = 1;

	if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
		p_tunn_cfg->tx_enable_ipgeneve = 1;

	type = qed_tunn_get_clss_type(p_src->tunn_clss_l2geneve);
	p_tunn_cfg->tunnel_clss_l2geneve = type;

	type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgeneve);
	p_tunn_cfg->tunnel_clss_ipgeneve = type;
}

static void qed_set_hw_tunn_mode(struct qed_hwfn *p_hwfn,
				 struct qed_ptt *p_ptt,
				 unsigned long tunn_mode)
{
	u8 l2gre_enable = 0, ipgre_enable = 0, vxlan_enable = 0;
	u8 l2geneve_enable = 0, ipgeneve_enable = 0;

	if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
		l2gre_enable = 1;

	if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
		ipgre_enable = 1;

	if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
		vxlan_enable = 1;

	qed_set_gre_enable(p_hwfn, p_ptt, l2gre_enable, ipgre_enable);
	qed_set_vxlan_enable(p_hwfn, p_ptt, vxlan_enable);

	if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
		l2geneve_enable = 1;

	if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
		ipgeneve_enable = 1;

	qed_set_geneve_enable(p_hwfn, p_ptt, l2geneve_enable,
			      ipgeneve_enable);
}

static void
qed_tunn_set_pf_start_params(struct qed_hwfn *p_hwfn,
			     struct qed_tunn_start_params *p_src,
			     struct pf_start_tunnel_config *p_tunn_cfg)
{
	unsigned long tunn_mode;
	enum tunnel_clss type;

	if (!p_src)
		return;

	tunn_mode = p_src->tunn_mode;
	type = qed_tunn_get_clss_type(p_src->tunn_clss_vxlan);
	p_tunn_cfg->tunnel_clss_vxlan = type;
	type = qed_tunn_get_clss_type(p_src->tunn_clss_l2gre);
	p_tunn_cfg->tunnel_clss_l2gre = type;
	type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgre);
	p_tunn_cfg->tunnel_clss_ipgre = type;

	if (p_src->update_vxlan_udp_port) {
		p_tunn_cfg->set_vxlan_udp_port_flg = 1;
		p_tunn_cfg->vxlan_udp_port = cpu_to_le16(p_src->vxlan_udp_port);
	}

	if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
		p_tunn_cfg->tx_enable_l2gre = 1;

	if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
		p_tunn_cfg->tx_enable_ipgre = 1;

	if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
		p_tunn_cfg->tx_enable_vxlan = 1;

	if (p_src->update_geneve_udp_port) {
		p_tunn_cfg->set_geneve_udp_port_flg = 1;
		p_tunn_cfg->geneve_udp_port =
				cpu_to_le16(p_src->geneve_udp_port);
	}

	if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
		p_tunn_cfg->tx_enable_l2geneve = 1;

	if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
		p_tunn_cfg->tx_enable_ipgeneve = 1;

	type = qed_tunn_get_clss_type(p_src->tunn_clss_l2geneve);
	p_tunn_cfg->tunnel_clss_l2geneve = type;
	type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgeneve);
	p_tunn_cfg->tunnel_clss_ipgeneve = type;
}

int qed_sp_pf_start(struct qed_hwfn *p_hwfn,
		    struct qed_tunn_start_params *p_tunn,
		    enum qed_mf_mode mode, bool allow_npar_tx_switch)
{
	struct pf_start_ramrod_data *p_ramrod = NULL;
	u16 sb = qed_int_get_sp_sb_id(p_hwfn);
	u8 sb_index = p_hwfn->p_eq->eq_sb_index;
	struct qed_spq_entry *p_ent = NULL;
	struct qed_sp_init_data init_data;
	int rc = -EINVAL;
	u8 page_cnt;

	/* update initial eq producer */
	qed_eq_prod_update(p_hwfn,
			   qed_chain_get_prod_idx(&p_hwfn->p_eq->chain));

	memset(&init_data, 0, sizeof(init_data));
	init_data.cid = qed_spq_get_cid(p_hwfn);
	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;

	rc = qed_sp_init_request(p_hwfn, &p_ent,
				 COMMON_RAMROD_PF_START,
				 PROTOCOLID_COMMON, &init_data);
	if (rc)
		return rc;

	p_ramrod = &p_ent->ramrod.pf_start;

	p_ramrod->event_ring_sb_id	= cpu_to_le16(sb);
	p_ramrod->event_ring_sb_index	= sb_index;
	p_ramrod->path_id		= QED_PATH_ID(p_hwfn);
	p_ramrod->dont_log_ramrods	= 0;
	p_ramrod->log_type_mask		= cpu_to_le16(0xf);

	switch (mode) {
	case QED_MF_DEFAULT:
	case QED_MF_NPAR:
		p_ramrod->mf_mode = MF_NPAR;
		break;
	case QED_MF_OVLAN:
		p_ramrod->mf_mode = MF_OVLAN;
		break;
	default:
		DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
		p_ramrod->mf_mode = MF_NPAR;
	}
	p_ramrod->outer_tag = p_hwfn->hw_info.ovlan;

	/* Place EQ address in RAMROD */
	DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr,
		       p_hwfn->p_eq->chain.pbl_sp.p_phys_table);
	page_cnt = (u8)qed_chain_get_page_cnt(&p_hwfn->p_eq->chain);
	p_ramrod->event_ring_num_pages = page_cnt;
	DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_addr,
		       p_hwfn->p_consq->chain.pbl_sp.p_phys_table);

	qed_tunn_set_pf_start_params(p_hwfn, p_tunn, &p_ramrod->tunnel_config);

	if (IS_MF_SI(p_hwfn))
		p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch;

	switch (p_hwfn->hw_info.personality) {
	case QED_PCI_ETH:
		p_ramrod->personality = PERSONALITY_ETH;
		break;
	case QED_PCI_FCOE:
		p_ramrod->personality = PERSONALITY_FCOE;
		break;
	case QED_PCI_ISCSI:
		p_ramrod->personality = PERSONALITY_ISCSI;
		break;
	case QED_PCI_ETH_ROCE:
		p_ramrod->personality = PERSONALITY_RDMA_AND_ETH;
		break;
	default:
		DP_NOTICE(p_hwfn, "Unknown personality %d\n",
			  p_hwfn->hw_info.personality);
		p_ramrod->personality = PERSONALITY_ETH;
	}

	if (p_hwfn->cdev->p_iov_info) {
		struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;

		p_ramrod->base_vf_id = (u8) p_iov->first_vf_in_pf;
		p_ramrod->num_vfs = (u8) p_iov->total_vfs;
	}
	p_ramrod->hsi_fp_ver.major_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MAJOR;
	p_ramrod->hsi_fp_ver.minor_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MINOR;

	DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
		   "Setting event_ring_sb [id %04x index %02x], outer_tag [%d]\n",
		   sb, sb_index, p_ramrod->outer_tag);

	rc = qed_spq_post(p_hwfn, p_ent, NULL);

	if (p_tunn) {
		qed_set_hw_tunn_mode(p_hwfn, p_hwfn->p_main_ptt,
				     p_tunn->tunn_mode);
		p_hwfn->cdev->tunn_mode = p_tunn->tunn_mode;
	}

	return rc;
}

int qed_sp_pf_update(struct qed_hwfn *p_hwfn)
{
	struct qed_spq_entry *p_ent = NULL;
	struct qed_sp_init_data init_data;
	int rc = -EINVAL;

	/* Get SPQ entry */
	memset(&init_data, 0, sizeof(init_data));
	init_data.cid = qed_spq_get_cid(p_hwfn);
	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	init_data.comp_mode = QED_SPQ_MODE_CB;

	rc = qed_sp_init_request(p_hwfn, &p_ent,
				 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
				 &init_data);
	if (rc)
		return rc;

	qed_dcbx_set_pf_update_params(&p_hwfn->p_dcbx_info->results,
				      &p_ent->ramrod.pf_update);

	return qed_spq_post(p_hwfn, p_ent, NULL);
}

/* Set pf update ramrod command params */
int qed_sp_pf_update_tunn_cfg(struct qed_hwfn *p_hwfn,
			      struct qed_tunn_update_params *p_tunn,
			      enum spq_mode comp_mode,
			      struct qed_spq_comp_cb *p_comp_data)
{
	struct qed_spq_entry *p_ent = NULL;
	struct qed_sp_init_data init_data;
	int rc = -EINVAL;

	/* Get SPQ entry */
	memset(&init_data, 0, sizeof(init_data));
	init_data.cid = qed_spq_get_cid(p_hwfn);
	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	init_data.comp_mode = comp_mode;
	init_data.p_comp_data = p_comp_data;

	rc = qed_sp_init_request(p_hwfn, &p_ent,
				 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
				 &init_data);
	if (rc)
		return rc;

	qed_tunn_set_pf_update_params(p_hwfn, p_tunn,
				      &p_ent->ramrod.pf_update.tunnel_config);

	rc = qed_spq_post(p_hwfn, p_ent, NULL);
	if (rc)
		return rc;

	if (p_tunn->update_vxlan_udp_port)
		qed_set_vxlan_dest_port(p_hwfn, p_hwfn->p_main_ptt,
					p_tunn->vxlan_udp_port);
	if (p_tunn->update_geneve_udp_port)
		qed_set_geneve_dest_port(p_hwfn, p_hwfn->p_main_ptt,
					 p_tunn->geneve_udp_port);

	qed_set_hw_tunn_mode(p_hwfn, p_hwfn->p_main_ptt, p_tunn->tunn_mode);
	p_hwfn->cdev->tunn_mode = p_tunn->tunn_mode;

	return rc;
}

int qed_sp_pf_stop(struct qed_hwfn *p_hwfn)
{
	struct qed_spq_entry *p_ent = NULL;
	struct qed_sp_init_data init_data;
	int rc = -EINVAL;

	/* Get SPQ entry */
	memset(&init_data, 0, sizeof(init_data));
	init_data.cid = qed_spq_get_cid(p_hwfn);
	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;

	rc = qed_sp_init_request(p_hwfn, &p_ent,
				 COMMON_RAMROD_PF_STOP, PROTOCOLID_COMMON,
				 &init_data);
	if (rc)
		return rc;

	return qed_spq_post(p_hwfn, p_ent, NULL);
}

int qed_sp_heartbeat_ramrod(struct qed_hwfn *p_hwfn)
{
	struct qed_spq_entry *p_ent = NULL;
	struct qed_sp_init_data init_data;
	int rc;

	/* Get SPQ entry */
	memset(&init_data, 0, sizeof(init_data));
	init_data.cid = qed_spq_get_cid(p_hwfn);
	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;

	rc = qed_sp_init_request(p_hwfn, &p_ent,
				 COMMON_RAMROD_EMPTY, PROTOCOLID_COMMON,
				 &init_data);
	if (rc)
		return rc;

	return qed_spq_post(p_hwfn, p_ent, NULL);
}
Commit	Line	Data
fe56b9e6	1	/* QLogic qed NIC Driver
e8f1cb50	2	* Copyright (c) 2015-2017 QLogic Corporation
fe56b9e6	3	*
e8f1cb50 MY	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and /or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
fe56b9e6 YM	31	*/
	32
	33	#include <linux/types.h>
	34	#include <asm/byteorder.h>
	35	#include <linux/bitops.h>
	36	#include <linux/errno.h>
	37	#include <linux/kernel.h>
	38	#include <linux/string.h>
	39	#include "qed.h"
	40	#include <linux/qed/qed_chain.h>
	41	#include "qed_cxt.h"
39651abd	42	#include "qed_dcbx.h"
fe56b9e6 YM	43	#include "qed_hsi.h"
	44	#include "qed_hw.h"
	45	#include "qed_int.h"
	46	#include "qed_reg_addr.h"
	47	#include "qed_sp.h"
1408cc1f	48	#include "qed_sriov.h"
fe56b9e6 YM	49
	50	int qed_sp_init_request(struct qed_hwfn *p_hwfn,
	51	struct qed_spq_entry **pp_ent,
1a635e48	52	u8 cmd, u8 protocol, struct qed_sp_init_data *p_data)
fe56b9e6	53	{
06f56b81	54	u32 opaque_cid = p_data->opaque_fid << 16 \| p_data->cid;
fe56b9e6	55	struct qed_spq_entry *p_ent = NULL;
06f56b81	56	int rc;
fe56b9e6 YM	57
	58	if (!pp_ent)
	59	return -ENOMEM;
	60
	61	rc = qed_spq_get_entry(p_hwfn, pp_ent);
	62
1a635e48	63	if (rc)
fe56b9e6 YM	64	return rc;
	65
	66	p_ent = *pp_ent;
	67
	68	p_ent->elem.hdr.cid = cpu_to_le32(opaque_cid);
	69	p_ent->elem.hdr.cmd_id = cmd;
	70	p_ent->elem.hdr.protocol_id = protocol;
	71
	72	p_ent->priority = QED_SPQ_PRIORITY_NORMAL;
06f56b81	73	p_ent->comp_mode = p_data->comp_mode;
fe56b9e6 YM	74	p_ent->comp_done.done = 0;
	75
	76	switch (p_ent->comp_mode) {
	77	case QED_SPQ_MODE_EBLOCK:
	78	p_ent->comp_cb.cookie = &p_ent->comp_done;
	79	break;
	80
	81	case QED_SPQ_MODE_BLOCK:
06f56b81	82	if (!p_data->p_comp_data)
fe56b9e6 YM	83	return -EINVAL;
fe56b9e6 YM	84
06f56b81	85	p_ent->comp_cb.cookie = p_data->p_comp_data->cookie;
fe56b9e6 YM	86	break;
	87
	88	case QED_SPQ_MODE_CB:
06f56b81	89	if (!p_data->p_comp_data)
fe56b9e6 YM	90	p_ent->comp_cb.function = NULL;
fe56b9e6 YM	91	else
06f56b81	92	p_ent->comp_cb = *p_data->p_comp_data;
fe56b9e6 YM	93	break;
	94
	95	default:
	96	DP_NOTICE(p_hwfn, "Unknown SPQE completion mode %d\n",
	97	p_ent->comp_mode);
	98	return -EINVAL;
	99	}
	100
	101	DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
	102	"Initialized: CID %08x cmd %02x protocol %02x data_addr %lu comp_mode [%s]\n",
	103	opaque_cid, cmd, protocol,
	104	(unsigned long)&p_ent->ramrod,
	105	D_TRINE(p_ent->comp_mode, QED_SPQ_MODE_EBLOCK,
	106	QED_SPQ_MODE_BLOCK, "MODE_EBLOCK", "MODE_BLOCK",
	107	"MODE_CB"));
06f56b81 YM	108
06f56b81 YM	109	memset(&p_ent->ramrod, 0, sizeof(p_ent->ramrod));
fe56b9e6 YM	110
	111	return 0;
	112	}
	113
464f6645 MC	114	static enum tunnel_clss qed_tunn_get_clss_type(u8 type)
	115	{
	116	switch (type) {
	117	case QED_TUNN_CLSS_MAC_VLAN:
	118	return TUNNEL_CLSS_MAC_VLAN;
	119	case QED_TUNN_CLSS_MAC_VNI:
	120	return TUNNEL_CLSS_MAC_VNI;
	121	case QED_TUNN_CLSS_INNER_MAC_VLAN:
	122	return TUNNEL_CLSS_INNER_MAC_VLAN;
	123	case QED_TUNN_CLSS_INNER_MAC_VNI:
	124	return TUNNEL_CLSS_INNER_MAC_VNI;
	125	default:
	126	return TUNNEL_CLSS_MAC_VLAN;
	127	}
	128	}
	129
	130	static void
	131	qed_tunn_set_pf_fix_tunn_mode(struct qed_hwfn *p_hwfn,
	132	struct qed_tunn_update_params *p_src,
	133	struct pf_update_tunnel_config *p_tunn_cfg)
	134	{
	135	unsigned long cached_tunn_mode = p_hwfn->cdev->tunn_mode;
	136	unsigned long update_mask = p_src->tunn_mode_update_mask;
	137	unsigned long tunn_mode = p_src->tunn_mode;
	138	unsigned long new_tunn_mode = 0;
	139
	140	if (test_bit(QED_MODE_L2GRE_TUNN, &update_mask)) {
	141	if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
	142	__set_bit(QED_MODE_L2GRE_TUNN, &new_tunn_mode);
	143	} else {
	144	if (test_bit(QED_MODE_L2GRE_TUNN, &cached_tunn_mode))
	145	__set_bit(QED_MODE_L2GRE_TUNN, &new_tunn_mode);
	146	}
	147
	148	if (test_bit(QED_MODE_IPGRE_TUNN, &update_mask)) {
	149	if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
	150	__set_bit(QED_MODE_IPGRE_TUNN, &new_tunn_mode);
	151	} else {
	152	if (test_bit(QED_MODE_IPGRE_TUNN, &cached_tunn_mode))
	153	__set_bit(QED_MODE_IPGRE_TUNN, &new_tunn_mode);
	154	}
	155
	156	if (test_bit(QED_MODE_VXLAN_TUNN, &update_mask)) {
	157	if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
	158	__set_bit(QED_MODE_VXLAN_TUNN, &new_tunn_mode);
	159	} else {
	160	if (test_bit(QED_MODE_VXLAN_TUNN, &cached_tunn_mode))
	161	__set_bit(QED_MODE_VXLAN_TUNN, &new_tunn_mode);
	162	}
	163
	164	if (p_src->update_geneve_udp_port) {
	165	p_tunn_cfg->set_geneve_udp_port_flg = 1;
	166	p_tunn_cfg->geneve_udp_port =
	167	cpu_to_le16(p_src->geneve_udp_port);
	168	}
	169
	170	if (test_bit(QED_MODE_L2GENEVE_TUNN, &update_mask)) {
	171	if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
	172	__set_bit(QED_MODE_L2GENEVE_TUNN, &new_tunn_mode);
	173	} else {
	174	if (test_bit(QED_MODE_L2GENEVE_TUNN, &cached_tunn_mode))
	175	__set_bit(QED_MODE_L2GENEVE_TUNN, &new_tunn_mode);
	176	}
	177
178	if (test_bit(QED_MODE_IPGENEVE_TUNN, &update_mask)) {
179	if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
180	__set_bit(QED_MODE_IPGENEVE_TUNN, &new_tunn_mode);
181	} else {
182	if (test_bit(QED_MODE_IPGENEVE_TUNN, &cached_tunn_mode))
183	__set_bit(QED_MODE_IPGENEVE_TUNN, &new_tunn_mode);
184	}
185
186	p_src->tunn_mode = new_tunn_mode;
187	}
188
189	static void
190	qed_tunn_set_pf_update_params(struct qed_hwfn *p_hwfn,
191	struct qed_tunn_update_params *p_src,
192	struct pf_update_tunnel_config *p_tunn_cfg)
193	{
194	unsigned long tunn_mode = p_src->tunn_mode;
195	enum tunnel_clss type;
196
197	qed_tunn_set_pf_fix_tunn_mode(p_hwfn, p_src, p_tunn_cfg);
198	p_tunn_cfg->update_rx_pf_clss = p_src->update_rx_pf_clss;
199	p_tunn_cfg->update_tx_pf_clss = p_src->update_tx_pf_clss;
200
201	type = qed_tunn_get_clss_type(p_src->tunn_clss_vxlan);
202	p_tunn_cfg->tunnel_clss_vxlan = type;
203
204	type = qed_tunn_get_clss_type(p_src->tunn_clss_l2gre);
205	p_tunn_cfg->tunnel_clss_l2gre = type;
206
207	type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgre);
208	p_tunn_cfg->tunnel_clss_ipgre = type;
209
210	if (p_src->update_vxlan_udp_port) {
211	p_tunn_cfg->set_vxlan_udp_port_flg = 1;
212	p_tunn_cfg->vxlan_udp_port = cpu_to_le16(p_src->vxlan_udp_port);
213	}
214
215	if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
216	p_tunn_cfg->tx_enable_l2gre = 1;
217
218	if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
219	p_tunn_cfg->tx_enable_ipgre = 1;
220
221	if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
222	p_tunn_cfg->tx_enable_vxlan = 1;
223
224	if (p_src->update_geneve_udp_port) {
225	p_tunn_cfg->set_geneve_udp_port_flg = 1;
226	p_tunn_cfg->geneve_udp_port =
227	cpu_to_le16(p_src->geneve_udp_port);
228	}
229
230	if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
231	p_tunn_cfg->tx_enable_l2geneve = 1;
232
233	if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
234	p_tunn_cfg->tx_enable_ipgeneve = 1;
235
236	type = qed_tunn_get_clss_type(p_src->tunn_clss_l2geneve);
237	p_tunn_cfg->tunnel_clss_l2geneve = type;
238
239	type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgeneve);
240	p_tunn_cfg->tunnel_clss_ipgeneve = type;
241	}
242
243	static void qed_set_hw_tunn_mode(struct qed_hwfn *p_hwfn,
244	struct qed_ptt *p_ptt,
245	unsigned long tunn_mode)
246	{
247	u8 l2gre_enable = 0, ipgre_enable = 0, vxlan_enable = 0;
248	u8 l2geneve_enable = 0, ipgeneve_enable = 0;
249
250	if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
251	l2gre_enable = 1;
252
253	if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
254	ipgre_enable = 1;
255
256	if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
257	vxlan_enable = 1;
258
259	qed_set_gre_enable(p_hwfn, p_ptt, l2gre_enable, ipgre_enable);
260	qed_set_vxlan_enable(p_hwfn, p_ptt, vxlan_enable);
261
262	if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
263	l2geneve_enable = 1;
264
265	if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
266	ipgeneve_enable = 1;
267
268	qed_set_geneve_enable(p_hwfn, p_ptt, l2geneve_enable,
269	ipgeneve_enable);
270	}
271
272	static void
273	qed_tunn_set_pf_start_params(struct qed_hwfn *p_hwfn,
274	struct qed_tunn_start_params *p_src,
275	struct pf_start_tunnel_config *p_tunn_cfg)
276	{
277	unsigned long tunn_mode;
278	enum tunnel_clss type;
279
280	if (!p_src)
281	return;
282
283	tunn_mode = p_src->tunn_mode;
284	type = qed_tunn_get_clss_type(p_src->tunn_clss_vxlan);
285	p_tunn_cfg->tunnel_clss_vxlan = type;
286	type = qed_tunn_get_clss_type(p_src->tunn_clss_l2gre);
287	p_tunn_cfg->tunnel_clss_l2gre = type;
288	type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgre);
289	p_tunn_cfg->tunnel_clss_ipgre = type;
290
291	if (p_src->update_vxlan_udp_port) {
292	p_tunn_cfg->set_vxlan_udp_port_flg = 1;
293	p_tunn_cfg->vxlan_udp_port = cpu_to_le16(p_src->vxlan_udp_port);
294	}
295
296	if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
297	p_tunn_cfg->tx_enable_l2gre = 1;
298
299	if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
300	p_tunn_cfg->tx_enable_ipgre = 1;
301
302	if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
303	p_tunn_cfg->tx_enable_vxlan = 1;
304
305	if (p_src->update_geneve_udp_port) {
306	p_tunn_cfg->set_geneve_udp_port_flg = 1;
307	p_tunn_cfg->geneve_udp_port =
308	cpu_to_le16(p_src->geneve_udp_port);
309	}
310
311	if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
312	p_tunn_cfg->tx_enable_l2geneve = 1;
313
314	if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
315	p_tunn_cfg->tx_enable_ipgeneve = 1;
316
317	type = qed_tunn_get_clss_type(p_src->tunn_clss_l2geneve);
318	p_tunn_cfg->tunnel_clss_l2geneve = type;
319	type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgeneve);
320	p_tunn_cfg->tunnel_clss_ipgeneve = type;
321	}
322
fe56b9e6	323	int qed_sp_pf_start(struct qed_hwfn *p_hwfn,
464f6645	324	struct qed_tunn_start_params *p_tunn,
831bfb0e	325	enum qed_mf_mode mode, bool allow_npar_tx_switch)
fe56b9e6	326	{
fe56b9e6 YM	327	struct pf_start_ramrod_data *p_ramrod = NULL;
	328	u16 sb = qed_int_get_sp_sb_id(p_hwfn);
	329	u8 sb_index = p_hwfn->p_eq->eq_sb_index;
	330	struct qed_spq_entry *p_ent = NULL;
06f56b81	331	struct qed_sp_init_data init_data;
fe56b9e6	332	int rc = -EINVAL;
a91eb52a	333	u8 page_cnt;
fe56b9e6 YM	334
	335	/* update initial eq producer */
	336	qed_eq_prod_update(p_hwfn,
	337	qed_chain_get_prod_idx(&p_hwfn->p_eq->chain));
	338
06f56b81 YM	339	memset(&init_data, 0, sizeof(init_data));
	340	init_data.cid = qed_spq_get_cid(p_hwfn);
	341	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	342	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
fe56b9e6	343
06f56b81	344	rc = qed_sp_init_request(p_hwfn, &p_ent,
fe56b9e6	345	COMMON_RAMROD_PF_START,
1a635e48	346	PROTOCOLID_COMMON, &init_data);
fe56b9e6 YM	347	if (rc)
	348	return rc;
	349
	350	p_ramrod = &p_ent->ramrod.pf_start;
	351
	352	p_ramrod->event_ring_sb_id = cpu_to_le16(sb);
	353	p_ramrod->event_ring_sb_index = sb_index;
	354	p_ramrod->path_id = QED_PATH_ID(p_hwfn);
	355	p_ramrod->dont_log_ramrods = 0;
	356	p_ramrod->log_type_mask = cpu_to_le16(0xf);
351a4ded	357
fc48b7a6 YM	358	switch (mode) {
	359	case QED_MF_DEFAULT:
	360	case QED_MF_NPAR:
	361	p_ramrod->mf_mode = MF_NPAR;
	362	break;
	363	case QED_MF_OVLAN:
	364	p_ramrod->mf_mode = MF_OVLAN;
	365	break;
	366	default:
	367	DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
	368	p_ramrod->mf_mode = MF_NPAR;
	369	}
fe56b9e6 YM	370	p_ramrod->outer_tag = p_hwfn->hw_info.ovlan;
	371
	372	/* Place EQ address in RAMROD */
94494598	373	DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr,
6d937acf	374	p_hwfn->p_eq->chain.pbl_sp.p_phys_table);
a91eb52a YM	375	page_cnt = (u8)qed_chain_get_page_cnt(&p_hwfn->p_eq->chain);
a91eb52a YM	376	p_ramrod->event_ring_num_pages = page_cnt;
94494598	377	DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_addr,
6d937acf	378	p_hwfn->p_consq->chain.pbl_sp.p_phys_table);
fe56b9e6	379
1a635e48	380	qed_tunn_set_pf_start_params(p_hwfn, p_tunn, &p_ramrod->tunnel_config);
fe56b9e6	381
831bfb0e YM	382	if (IS_MF_SI(p_hwfn))
	383	p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch;
	384
c5ac9319 YM	385	switch (p_hwfn->hw_info.personality) {
	386	case QED_PCI_ETH:
	387	p_ramrod->personality = PERSONALITY_ETH;
	388	break;
1e128c81 AE	389	case QED_PCI_FCOE:
	390	p_ramrod->personality = PERSONALITY_FCOE;
	391	break;
c5ac9319 YM	392	case QED_PCI_ISCSI:
	393	p_ramrod->personality = PERSONALITY_ISCSI;
	394	break;
	395	case QED_PCI_ETH_ROCE:
	396	p_ramrod->personality = PERSONALITY_RDMA_AND_ETH;
	397	break;
	398	default:
9165dabb	399	DP_NOTICE(p_hwfn, "Unknown personality %d\n",
c5ac9319 YM	400	p_hwfn->hw_info.personality);
	401	p_ramrod->personality = PERSONALITY_ETH;
	402	}
	403
1408cc1f YM	404	if (p_hwfn->cdev->p_iov_info) {
	405	struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
	406
	407	p_ramrod->base_vf_id = (u8) p_iov->first_vf_in_pf;
	408	p_ramrod->num_vfs = (u8) p_iov->total_vfs;
	409	}
351a4ded YM	410	p_ramrod->hsi_fp_ver.major_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MAJOR;
351a4ded YM	411	p_ramrod->hsi_fp_ver.minor_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MINOR;
1408cc1f	412
fe56b9e6	413	DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
fc48b7a6	414	"Setting event_ring_sb [id %04x index %02x], outer_tag [%d]\n",
1a635e48	415	sb, sb_index, p_ramrod->outer_tag);
fe56b9e6	416
c0f31a05 MC	417	rc = qed_spq_post(p_hwfn, p_ent, NULL);
	418
	419	if (p_tunn) {
	420	qed_set_hw_tunn_mode(p_hwfn, p_hwfn->p_main_ptt,
	421	p_tunn->tunn_mode);
	422	p_hwfn->cdev->tunn_mode = p_tunn->tunn_mode;
	423	}
	424
	425	return rc;
fe56b9e6 YM	426	}
fe56b9e6 YM	427
39651abd SRK	428	int qed_sp_pf_update(struct qed_hwfn *p_hwfn)
	429	{
	430	struct qed_spq_entry *p_ent = NULL;
	431	struct qed_sp_init_data init_data;
	432	int rc = -EINVAL;
	433
	434	/* Get SPQ entry */
	435	memset(&init_data, 0, sizeof(init_data));
	436	init_data.cid = qed_spq_get_cid(p_hwfn);
	437	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	438	init_data.comp_mode = QED_SPQ_MODE_CB;
	439
	440	rc = qed_sp_init_request(p_hwfn, &p_ent,
	441	COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
	442	&init_data);
	443	if (rc)
	444	return rc;
	445
	446	qed_dcbx_set_pf_update_params(&p_hwfn->p_dcbx_info->results,
	447	&p_ent->ramrod.pf_update);
	448
	449	return qed_spq_post(p_hwfn, p_ent, NULL);
	450	}
	451
464f6645 MC	452	/* Set pf update ramrod command params */
	453	int qed_sp_pf_update_tunn_cfg(struct qed_hwfn *p_hwfn,
	454	struct qed_tunn_update_params *p_tunn,
	455	enum spq_mode comp_mode,
	456	struct qed_spq_comp_cb *p_comp_data)
	457	{
	458	struct qed_spq_entry *p_ent = NULL;
	459	struct qed_sp_init_data init_data;
	460	int rc = -EINVAL;
	461
	462	/* Get SPQ entry */
	463	memset(&init_data, 0, sizeof(init_data));
	464	init_data.cid = qed_spq_get_cid(p_hwfn);
	465	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	466	init_data.comp_mode = comp_mode;
	467	init_data.p_comp_data = p_comp_data;
	468
	469	rc = qed_sp_init_request(p_hwfn, &p_ent,
	470	COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
	471	&init_data);
	472	if (rc)
	473	return rc;
	474
	475	qed_tunn_set_pf_update_params(p_hwfn, p_tunn,
	476	&p_ent->ramrod.pf_update.tunnel_config);
	477
	478	rc = qed_spq_post(p_hwfn, p_ent, NULL);
	479	if (rc)
	480	return rc;
	481
	482	if (p_tunn->update_vxlan_udp_port)
	483	qed_set_vxlan_dest_port(p_hwfn, p_hwfn->p_main_ptt,
	484	p_tunn->vxlan_udp_port);
	485	if (p_tunn->update_geneve_udp_port)
	486	qed_set_geneve_dest_port(p_hwfn, p_hwfn->p_main_ptt,
	487	p_tunn->geneve_udp_port);
	488
	489	qed_set_hw_tunn_mode(p_hwfn, p_hwfn->p_main_ptt, p_tunn->tunn_mode);
	490	p_hwfn->cdev->tunn_mode = p_tunn->tunn_mode;
	491
	492	return rc;
	493	}
	494
fe56b9e6 YM	495	int qed_sp_pf_stop(struct qed_hwfn *p_hwfn)
fe56b9e6 YM	496	{
fe56b9e6	497	struct qed_spq_entry *p_ent = NULL;
06f56b81	498	struct qed_sp_init_data init_data;
fe56b9e6 YM	499	int rc = -EINVAL;
fe56b9e6 YM	500
06f56b81 YM	501	/* Get SPQ entry */
	502	memset(&init_data, 0, sizeof(init_data));
	503	init_data.cid = qed_spq_get_cid(p_hwfn);
	504	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	505	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
fe56b9e6	506
06f56b81	507	rc = qed_sp_init_request(p_hwfn, &p_ent,
fe56b9e6	508	COMMON_RAMROD_PF_STOP, PROTOCOLID_COMMON,
06f56b81	509	&init_data);
fe56b9e6 YM	510	if (rc)
	511	return rc;
	512
	513	return qed_spq_post(p_hwfn, p_ent, NULL);
	514	}
03dc76ca SRK	515
	516	int qed_sp_heartbeat_ramrod(struct qed_hwfn *p_hwfn)
	517	{
	518	struct qed_spq_entry *p_ent = NULL;
	519	struct qed_sp_init_data init_data;
	520	int rc;
	521
	522	/* Get SPQ entry */
	523	memset(&init_data, 0, sizeof(init_data));
	524	init_data.cid = qed_spq_get_cid(p_hwfn);
	525	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	526	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
	527
	528	rc = qed_sp_init_request(p_hwfn, &p_ent,
	529	COMMON_RAMROD_EMPTY, PROTOCOLID_COMMON,
	530	&init_data);
	531	if (rc)
	532	return rc;
	533
	534	return qed_spq_post(p_hwfn, p_ent, NULL);
	535	}