Commit | Line | Data |
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1f4d4ed6 | 1 | /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ |
fe56b9e6 | 2 | /* QLogic qed NIC Driver |
e8f1cb50 | 3 | * Copyright (c) 2015-2017 QLogic Corporation |
663eacd8 | 4 | * Copyright (c) 2019-2020 Marvell International Ltd. |
fe56b9e6 YM |
5 | */ |
6 | ||
7 | #ifndef _QED_MCP_H | |
8 | #define _QED_MCP_H | |
9 | ||
10 | #include <linux/types.h> | |
11 | #include <linux/delay.h> | |
fe56b9e6 | 12 | #include <linux/slab.h> |
5529bad9 | 13 | #include <linux/spinlock.h> |
1e128c81 | 14 | #include <linux/qed/qed_fcoe_if.h> |
fe56b9e6 | 15 | #include "qed_hsi.h" |
5d24bcf1 | 16 | #include "qed_dev_api.h" |
fe56b9e6 | 17 | |
cc875c2e | 18 | struct qed_mcp_link_speed_params { |
5d4193c6 | 19 | bool autoneg; |
99785a87 | 20 | |
5d4193c6 | 21 | u32 advertised_speeds; |
99785a87 AL |
22 | #define QED_EXT_SPEED_MASK_RES 0x1 |
23 | #define QED_EXT_SPEED_MASK_1G 0x2 | |
24 | #define QED_EXT_SPEED_MASK_10G 0x4 | |
25 | #define QED_EXT_SPEED_MASK_20G 0x8 | |
26 | #define QED_EXT_SPEED_MASK_25G 0x10 | |
27 | #define QED_EXT_SPEED_MASK_40G 0x20 | |
28 | #define QED_EXT_SPEED_MASK_50G_R 0x40 | |
29 | #define QED_EXT_SPEED_MASK_50G_R2 0x80 | |
30 | #define QED_EXT_SPEED_MASK_100G_R2 0x100 | |
31 | #define QED_EXT_SPEED_MASK_100G_R4 0x200 | |
32 | #define QED_EXT_SPEED_MASK_100G_P4 0x400 | |
33 | ||
5d4193c6 | 34 | u32 forced_speed; /* In Mb/s */ |
99785a87 AL |
35 | #define QED_EXT_SPEED_1G 0x1 |
36 | #define QED_EXT_SPEED_10G 0x2 | |
37 | #define QED_EXT_SPEED_20G 0x4 | |
38 | #define QED_EXT_SPEED_25G 0x8 | |
39 | #define QED_EXT_SPEED_40G 0x10 | |
40 | #define QED_EXT_SPEED_50G_R 0x20 | |
41 | #define QED_EXT_SPEED_50G_R2 0x40 | |
42 | #define QED_EXT_SPEED_100G_R2 0x80 | |
43 | #define QED_EXT_SPEED_100G_R4 0x100 | |
44 | #define QED_EXT_SPEED_100G_P4 0x200 | |
cc875c2e YM |
45 | }; |
46 | ||
47 | struct qed_mcp_link_pause_params { | |
5d4193c6 AL |
48 | bool autoneg; |
49 | bool forced_rx; | |
50 | bool forced_tx; | |
cc875c2e YM |
51 | }; |
52 | ||
645874e5 SRK |
53 | enum qed_mcp_eee_mode { |
54 | QED_MCP_EEE_DISABLED, | |
55 | QED_MCP_EEE_ENABLED, | |
56 | QED_MCP_EEE_UNSUPPORTED | |
57 | }; | |
58 | ||
cc875c2e | 59 | struct qed_mcp_link_params { |
37237b5b AL |
60 | struct qed_mcp_link_speed_params speed; |
61 | struct qed_mcp_link_pause_params pause; | |
62 | u32 loopback_mode; | |
63 | struct qed_link_eee_params eee; | |
ae7e6937 | 64 | u32 fec; |
99785a87 AL |
65 | |
66 | struct qed_mcp_link_speed_params ext_speed; | |
67 | u32 ext_fec_mode; | |
cc875c2e YM |
68 | }; |
69 | ||
70 | struct qed_mcp_link_capabilities { | |
37237b5b AL |
71 | u32 speed_capabilities; |
72 | bool default_speed_autoneg; | |
ae7e6937 | 73 | u32 fec_default; |
37237b5b AL |
74 | enum qed_mcp_eee_mode default_eee; |
75 | u32 eee_lpi_timer; | |
76 | u8 eee_speed_caps; | |
99785a87 AL |
77 | |
78 | u32 default_ext_speed_caps; | |
79 | u32 default_ext_autoneg; | |
80 | u32 default_ext_speed; | |
81 | u32 default_ext_fec; | |
cc875c2e YM |
82 | }; |
83 | ||
84 | struct qed_mcp_link_state { | |
37237b5b AL |
85 | bool link_up; |
86 | u32 min_pf_rate; | |
a64b02d5 | 87 | |
4b01e519 | 88 | /* Actual link speed in Mb/s */ |
37237b5b | 89 | u32 line_speed; |
4b01e519 MC |
90 | |
91 | /* PF max speed in Mb/s, deduced from line_speed | |
92 | * according to PF max bandwidth configuration. | |
93 | */ | |
37237b5b AL |
94 | u32 speed; |
95 | ||
96 | bool full_duplex; | |
97 | bool an; | |
98 | bool an_complete; | |
99 | bool parallel_detection; | |
100 | bool pfc_enabled; | |
101 | ||
102 | u32 partner_adv_speed; | |
103 | #define QED_LINK_PARTNER_SPEED_1G_HD BIT(0) | |
104 | #define QED_LINK_PARTNER_SPEED_1G_FD BIT(1) | |
105 | #define QED_LINK_PARTNER_SPEED_10G BIT(2) | |
106 | #define QED_LINK_PARTNER_SPEED_20G BIT(3) | |
107 | #define QED_LINK_PARTNER_SPEED_25G BIT(4) | |
108 | #define QED_LINK_PARTNER_SPEED_40G BIT(5) | |
109 | #define QED_LINK_PARTNER_SPEED_50G BIT(6) | |
110 | #define QED_LINK_PARTNER_SPEED_100G BIT(7) | |
111 | ||
112 | bool partner_tx_flow_ctrl_en; | |
113 | bool partner_rx_flow_ctrl_en; | |
114 | ||
115 | u8 partner_adv_pause; | |
116 | #define QED_LINK_PARTNER_SYMMETRIC_PAUSE 0x1 | |
117 | #define QED_LINK_PARTNER_ASYMMETRIC_PAUSE 0x2 | |
118 | #define QED_LINK_PARTNER_BOTH_PAUSE 0x3 | |
119 | ||
120 | bool sfp_tx_fault; | |
121 | bool eee_active; | |
122 | u8 eee_adv_caps; | |
123 | u8 eee_lp_adv_caps; | |
ae7e6937 AL |
124 | |
125 | u32 fec_active; | |
cc875c2e YM |
126 | }; |
127 | ||
fe56b9e6 YM |
128 | struct qed_mcp_function_info { |
129 | u8 pause_on_host; | |
130 | ||
131 | enum qed_pci_personality protocol; | |
132 | ||
133 | u8 bandwidth_min; | |
134 | u8 bandwidth_max; | |
135 | ||
136 | u8 mac[ETH_ALEN]; | |
137 | ||
138 | u64 wwn_port; | |
139 | u64 wwn_node; | |
140 | ||
141 | #define QED_MCP_VLAN_UNSET (0xffff) | |
142 | u16 ovlan; | |
0fefbfba SK |
143 | |
144 | u16 mtu; | |
fe56b9e6 YM |
145 | }; |
146 | ||
147 | struct qed_mcp_nvm_common { | |
148 | u32 offset; | |
149 | u32 param; | |
150 | u32 resp; | |
151 | u32 cmd; | |
152 | }; | |
153 | ||
154 | struct qed_mcp_drv_version { | |
155 | u32 version; | |
156 | u8 name[MCP_DRV_VER_STR_SIZE - 4]; | |
157 | }; | |
158 | ||
6c754246 SRK |
159 | struct qed_mcp_lan_stats { |
160 | u64 ucast_rx_pkts; | |
161 | u64 ucast_tx_pkts; | |
162 | u32 fcs_err; | |
163 | }; | |
164 | ||
165 | struct qed_mcp_fcoe_stats { | |
166 | u64 rx_pkts; | |
167 | u64 tx_pkts; | |
168 | u32 fcs_err; | |
169 | u32 login_failure; | |
170 | }; | |
171 | ||
172 | struct qed_mcp_iscsi_stats { | |
173 | u64 rx_pdus; | |
174 | u64 tx_pdus; | |
175 | u64 rx_bytes; | |
176 | u64 tx_bytes; | |
177 | }; | |
178 | ||
179 | struct qed_mcp_rdma_stats { | |
180 | u64 rx_pkts; | |
181 | u64 tx_pkts; | |
182 | u64 rx_bytes; | |
183 | u64 tx_byts; | |
184 | }; | |
185 | ||
186 | enum qed_mcp_protocol_type { | |
187 | QED_MCP_LAN_STATS, | |
188 | QED_MCP_FCOE_STATS, | |
189 | QED_MCP_ISCSI_STATS, | |
190 | QED_MCP_RDMA_STATS | |
191 | }; | |
192 | ||
193 | union qed_mcp_protocol_stats { | |
194 | struct qed_mcp_lan_stats lan_stats; | |
195 | struct qed_mcp_fcoe_stats fcoe_stats; | |
196 | struct qed_mcp_iscsi_stats iscsi_stats; | |
197 | struct qed_mcp_rdma_stats rdma_stats; | |
198 | }; | |
199 | ||
0fefbfba SK |
200 | enum qed_ov_eswitch { |
201 | QED_OV_ESWITCH_NONE, | |
202 | QED_OV_ESWITCH_VEB, | |
203 | QED_OV_ESWITCH_VEPA | |
204 | }; | |
205 | ||
206 | enum qed_ov_client { | |
207 | QED_OV_CLIENT_DRV, | |
208 | QED_OV_CLIENT_USER, | |
209 | QED_OV_CLIENT_VENDOR_SPEC | |
210 | }; | |
211 | ||
212 | enum qed_ov_driver_state { | |
213 | QED_OV_DRIVER_STATE_NOT_LOADED, | |
214 | QED_OV_DRIVER_STATE_DISABLED, | |
215 | QED_OV_DRIVER_STATE_ACTIVE | |
216 | }; | |
217 | ||
218 | enum qed_ov_wol { | |
219 | QED_OV_WOL_DEFAULT, | |
220 | QED_OV_WOL_DISABLED, | |
221 | QED_OV_WOL_ENABLED | |
222 | }; | |
223 | ||
2528c389 SRK |
224 | enum qed_mfw_tlv_type { |
225 | QED_MFW_TLV_GENERIC = 0x1, /* Core driver TLVs */ | |
226 | QED_MFW_TLV_ETH = 0x2, /* L2 driver TLVs */ | |
f240b688 | 227 | QED_MFW_TLV_FCOE = 0x4, /* FCoE protocol TLVs */ |
77a509e4 SRK |
228 | QED_MFW_TLV_ISCSI = 0x8, /* SCSI protocol TLVs */ |
229 | QED_MFW_TLV_MAX = 0x16, | |
2528c389 SRK |
230 | }; |
231 | ||
232 | struct qed_mfw_tlv_generic { | |
233 | #define QED_MFW_TLV_FLAGS_SIZE 2 | |
234 | struct { | |
235 | u8 ipv4_csum_offload; | |
236 | u8 lso_supported; | |
237 | bool b_set; | |
238 | } flags; | |
239 | ||
240 | #define QED_MFW_TLV_MAC_COUNT 3 | |
241 | /* First entry for primary MAC, 2 secondary MACs possible */ | |
242 | u8 mac[QED_MFW_TLV_MAC_COUNT][6]; | |
243 | bool mac_set[QED_MFW_TLV_MAC_COUNT]; | |
244 | ||
245 | u64 rx_frames; | |
246 | bool rx_frames_set; | |
247 | u64 rx_bytes; | |
248 | bool rx_bytes_set; | |
249 | u64 tx_frames; | |
250 | bool tx_frames_set; | |
251 | u64 tx_bytes; | |
252 | bool tx_bytes_set; | |
253 | }; | |
254 | ||
255 | union qed_mfw_tlv_data { | |
256 | struct qed_mfw_tlv_generic generic; | |
257 | struct qed_mfw_tlv_eth eth; | |
f240b688 | 258 | struct qed_mfw_tlv_fcoe fcoe; |
77a509e4 | 259 | struct qed_mfw_tlv_iscsi iscsi; |
2528c389 SRK |
260 | }; |
261 | ||
38eabdf0 SRK |
262 | #define QED_NVM_CFG_OPTION_ALL BIT(0) |
263 | #define QED_NVM_CFG_OPTION_INIT BIT(1) | |
264 | #define QED_NVM_CFG_OPTION_COMMIT BIT(2) | |
265 | #define QED_NVM_CFG_OPTION_FREE BIT(3) | |
266 | #define QED_NVM_CFG_OPTION_ENTITY_SEL BIT(4) | |
267 | ||
cc875c2e | 268 | /** |
19198e4e | 269 | * qed_mcp_get_link_params(): Returns the link params of the hw function. |
cc875c2e | 270 | * |
19198e4e | 271 | * @p_hwfn: HW device data. |
cc875c2e | 272 | * |
19198e4e | 273 | * Returns: Pointer to link params. |
cc875c2e | 274 | */ |
19198e4e | 275 | struct qed_mcp_link_params *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn); |
cc875c2e YM |
276 | |
277 | /** | |
19198e4e | 278 | * qed_mcp_get_link_state(): Return the link state of the hw function. |
cc875c2e | 279 | * |
19198e4e | 280 | * @p_hwfn: HW device data. |
cc875c2e | 281 | * |
19198e4e | 282 | * Returns: Pointer to link state. |
cc875c2e | 283 | */ |
19198e4e | 284 | struct qed_mcp_link_state *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn); |
cc875c2e YM |
285 | |
286 | /** | |
19198e4e PK |
287 | * qed_mcp_get_link_capabilities(): Return the link capabilities of the |
288 | * hw function. | |
cc875c2e | 289 | * |
19198e4e | 290 | * @p_hwfn: HW device data. |
cc875c2e | 291 | * |
19198e4e | 292 | * Returns: Pointer to link capabilities. |
cc875c2e YM |
293 | */ |
294 | struct qed_mcp_link_capabilities | |
295 | *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn); | |
296 | ||
297 | /** | |
19198e4e PK |
298 | * qed_mcp_set_link(): Request the MFW to set the link according |
299 | * to 'link_input'. | |
cc875c2e | 300 | * |
19198e4e PK |
301 | * @p_hwfn: HW device data. |
302 | * @p_ptt: P_ptt. | |
303 | * @b_up: Raise link if `true'. Reset link if `false'. | |
cc875c2e | 304 | * |
19198e4e | 305 | * Return: Int. |
cc875c2e YM |
306 | */ |
307 | int qed_mcp_set_link(struct qed_hwfn *p_hwfn, | |
308 | struct qed_ptt *p_ptt, | |
309 | bool b_up); | |
310 | ||
fe56b9e6 | 311 | /** |
19198e4e | 312 | * qed_mcp_get_mfw_ver(): Get the management firmware version value. |
fe56b9e6 | 313 | * |
19198e4e PK |
314 | * @p_hwfn: HW device data. |
315 | * @p_ptt: P_ptt. | |
316 | * @p_mfw_ver: MFW version value. | |
317 | * @p_running_bundle_id: Image id in nvram; Optional. | |
fe56b9e6 | 318 | * |
19198e4e | 319 | * Return: Int - 0 - operation was successful. |
fe56b9e6 | 320 | */ |
1408cc1f YM |
321 | int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn, |
322 | struct qed_ptt *p_ptt, | |
323 | u32 *p_mfw_ver, u32 *p_running_bundle_id); | |
fe56b9e6 | 324 | |
ae33666a | 325 | /** |
19198e4e | 326 | * qed_mcp_get_mbi_ver(): Get the MBI version value. |
ae33666a | 327 | * |
19198e4e PK |
328 | * @p_hwfn: HW device data. |
329 | * @p_ptt: P_ptt. | |
330 | * @p_mbi_ver: A pointer to a variable to be filled with the MBI version. | |
ae33666a | 331 | * |
19198e4e | 332 | * Return: Int - 0 - operation was successful. |
ae33666a TT |
333 | */ |
334 | int qed_mcp_get_mbi_ver(struct qed_hwfn *p_hwfn, | |
335 | struct qed_ptt *p_ptt, u32 *p_mbi_ver); | |
336 | ||
cc875c2e | 337 | /** |
19198e4e | 338 | * qed_mcp_get_media_type(): Get media type value of the port. |
cc875c2e | 339 | * |
19198e4e PK |
340 | * @p_hwfn: HW device data. |
341 | * @p_ptt: P_ptt. | |
342 | * @media_type: Media type value | |
cc875c2e | 343 | * |
19198e4e PK |
344 | * Return: Int - 0 - Operation was successul. |
345 | * -EBUSY - Operation failed | |
cc875c2e | 346 | */ |
706d0891 RV |
347 | int qed_mcp_get_media_type(struct qed_hwfn *p_hwfn, |
348 | struct qed_ptt *p_ptt, u32 *media_type); | |
cc875c2e | 349 | |
c56a8be7 | 350 | /** |
19198e4e | 351 | * qed_mcp_get_transceiver_data(): Get transceiver data of the port. |
c56a8be7 | 352 | * |
19198e4e PK |
353 | * @p_hwfn: HW device data. |
354 | * @p_ptt: P_ptt. | |
355 | * @p_transceiver_state: Transceiver state. | |
356 | * @p_tranceiver_type: Media type value. | |
c56a8be7 | 357 | * |
19198e4e PK |
358 | * Return: Int - 0 - Operation was successul. |
359 | * -EBUSY - Operation failed | |
c56a8be7 RV |
360 | */ |
361 | int qed_mcp_get_transceiver_data(struct qed_hwfn *p_hwfn, | |
362 | struct qed_ptt *p_ptt, | |
363 | u32 *p_transceiver_state, | |
364 | u32 *p_tranceiver_type); | |
365 | ||
366 | /** | |
19198e4e | 367 | * qed_mcp_trans_speed_mask(): Get transceiver supported speed mask. |
c56a8be7 | 368 | * |
19198e4e PK |
369 | * @p_hwfn: HW device data. |
370 | * @p_ptt: P_ptt. | |
371 | * @p_speed_mask: Bit mask of all supported speeds. | |
c56a8be7 | 372 | * |
19198e4e PK |
373 | * Return: Int - 0 - Operation was successul. |
374 | * -EBUSY - Operation failed | |
c56a8be7 RV |
375 | */ |
376 | ||
377 | int qed_mcp_trans_speed_mask(struct qed_hwfn *p_hwfn, | |
378 | struct qed_ptt *p_ptt, u32 *p_speed_mask); | |
379 | ||
380 | /** | |
19198e4e | 381 | * qed_mcp_get_board_config(): Get board configuration. |
c56a8be7 | 382 | * |
19198e4e PK |
383 | * @p_hwfn: HW device data. |
384 | * @p_ptt: P_ptt. | |
385 | * @p_board_config: Board config. | |
c56a8be7 | 386 | * |
19198e4e PK |
387 | * Return: Int - 0 - Operation was successul. |
388 | * -EBUSY - Operation failed | |
c56a8be7 RV |
389 | */ |
390 | int qed_mcp_get_board_config(struct qed_hwfn *p_hwfn, | |
391 | struct qed_ptt *p_ptt, u32 *p_board_config); | |
392 | ||
fe56b9e6 | 393 | /** |
19198e4e PK |
394 | * qed_mcp_cmd(): General function for sending commands to the MCP |
395 | * mailbox. It acquire mutex lock for the entire | |
396 | * operation, from sending the request until the MCP | |
397 | * response. Waiting for MCP response will be checked up | |
398 | * to 5 seconds every 5ms. | |
fe56b9e6 | 399 | * |
19198e4e PK |
400 | * @p_hwfn: HW device data. |
401 | * @p_ptt: PTT required for register access. | |
402 | * @cmd: command to be sent to the MCP. | |
403 | * @param: Optional param | |
404 | * @o_mcp_resp: The MCP response code (exclude sequence). | |
405 | * @o_mcp_param: Optional parameter provided by the MCP | |
fe56b9e6 | 406 | * response |
19198e4e PK |
407 | * |
408 | * Return: Int - 0 - Operation was successul. | |
fe56b9e6 YM |
409 | */ |
410 | int qed_mcp_cmd(struct qed_hwfn *p_hwfn, | |
411 | struct qed_ptt *p_ptt, | |
412 | u32 cmd, | |
413 | u32 param, | |
414 | u32 *o_mcp_resp, | |
415 | u32 *o_mcp_param); | |
416 | ||
417 | /** | |
19198e4e PK |
418 | * qed_mcp_drain(): drains the nig, allowing completion to pass in |
419 | * case of pauses. | |
420 | * (Should be called only from sleepable context) | |
fe56b9e6 | 421 | * |
19198e4e PK |
422 | * @p_hwfn: HW device data. |
423 | * @p_ptt: PTT required for register access. | |
424 | * | |
425 | * Return: Int. | |
fe56b9e6 YM |
426 | */ |
427 | int qed_mcp_drain(struct qed_hwfn *p_hwfn, | |
428 | struct qed_ptt *p_ptt); | |
429 | ||
cee4d264 | 430 | /** |
19198e4e | 431 | * qed_mcp_get_flash_size(): Get the flash size value. |
cee4d264 | 432 | * |
19198e4e PK |
433 | * @p_hwfn: HW device data. |
434 | * @p_ptt: PTT required for register access. | |
435 | * @p_flash_size: Flash size in bytes to be filled. | |
cee4d264 | 436 | * |
19198e4e | 437 | * Return: Int - 0 - Operation was successul. |
cee4d264 MC |
438 | */ |
439 | int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn, | |
440 | struct qed_ptt *p_ptt, | |
441 | u32 *p_flash_size); | |
442 | ||
fe56b9e6 | 443 | /** |
19198e4e | 444 | * qed_mcp_send_drv_version(): Send driver version to MFW. |
fe56b9e6 | 445 | * |
19198e4e PK |
446 | * @p_hwfn: HW device data. |
447 | * @p_ptt: PTT required for register access. | |
448 | * @p_ver: Version value. | |
fe56b9e6 | 449 | * |
19198e4e | 450 | * Return: Int - 0 - Operation was successul. |
fe56b9e6 YM |
451 | */ |
452 | int | |
453 | qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn, | |
454 | struct qed_ptt *p_ptt, | |
455 | struct qed_mcp_drv_version *p_ver); | |
456 | ||
64515dc8 | 457 | /** |
19198e4e | 458 | * qed_get_process_kill_counter(): Read the MFW process kill counter. |
64515dc8 | 459 | * |
19198e4e PK |
460 | * @p_hwfn: HW device data. |
461 | * @p_ptt: PTT required for register access. | |
64515dc8 | 462 | * |
19198e4e | 463 | * Return: u32. |
64515dc8 TT |
464 | */ |
465 | u32 qed_get_process_kill_counter(struct qed_hwfn *p_hwfn, | |
466 | struct qed_ptt *p_ptt); | |
467 | ||
468 | /** | |
19198e4e | 469 | * qed_start_recovery_process(): Trigger a recovery process. |
64515dc8 | 470 | * |
19198e4e PK |
471 | * @p_hwfn: HW device data. |
472 | * @p_ptt: PTT required for register access. | |
64515dc8 | 473 | * |
19198e4e | 474 | * Return: Int. |
64515dc8 TT |
475 | */ |
476 | int qed_start_recovery_process(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); | |
477 | ||
478 | /** | |
19198e4e PK |
479 | * qed_recovery_prolog(): A recovery handler must call this function |
480 | * as its first step. | |
481 | * It is assumed that the handler is not run from | |
482 | * an interrupt context. | |
64515dc8 | 483 | * |
19198e4e | 484 | * @cdev: Qed dev pointer. |
64515dc8 | 485 | * |
19198e4e | 486 | * Return: int. |
64515dc8 TT |
487 | */ |
488 | int qed_recovery_prolog(struct qed_dev *cdev); | |
489 | ||
0fefbfba | 490 | /** |
19198e4e PK |
491 | * qed_mcp_ov_update_current_config(): Notify MFW about the change in base |
492 | * device properties | |
0fefbfba | 493 | * |
19198e4e PK |
494 | * @p_hwfn: HW device data. |
495 | * @p_ptt: P_ptt. | |
496 | * @client: Qed client type. | |
0fefbfba | 497 | * |
19198e4e | 498 | * Return: Int - 0 - Operation was successul. |
0fefbfba SK |
499 | */ |
500 | int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn, | |
501 | struct qed_ptt *p_ptt, | |
502 | enum qed_ov_client client); | |
503 | ||
504 | /** | |
19198e4e | 505 | * qed_mcp_ov_update_driver_state(): Notify MFW about the driver state. |
0fefbfba | 506 | * |
19198e4e PK |
507 | * @p_hwfn: HW device data. |
508 | * @p_ptt: P_ptt. | |
509 | * @drv_state: Driver state. | |
0fefbfba | 510 | * |
19198e4e | 511 | * Return: Int - 0 - Operation was successul. |
0fefbfba SK |
512 | */ |
513 | int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn, | |
514 | struct qed_ptt *p_ptt, | |
515 | enum qed_ov_driver_state drv_state); | |
516 | ||
517 | /** | |
19198e4e | 518 | * qed_mcp_ov_update_mtu(): Send MTU size to MFW. |
0fefbfba | 519 | * |
19198e4e PK |
520 | * @p_hwfn: HW device data. |
521 | * @p_ptt: P_ptt. | |
522 | * @mtu: MTU size. | |
0fefbfba | 523 | * |
19198e4e | 524 | * Return: Int - 0 - Operation was successul. |
0fefbfba SK |
525 | */ |
526 | int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn, | |
527 | struct qed_ptt *p_ptt, u16 mtu); | |
528 | ||
529 | /** | |
19198e4e | 530 | * qed_mcp_ov_update_mac(): Send MAC address to MFW. |
0fefbfba | 531 | * |
19198e4e PK |
532 | * @p_hwfn: HW device data. |
533 | * @p_ptt: P_ptt. | |
534 | * @mac: MAC address. | |
0fefbfba | 535 | * |
19198e4e | 536 | * Return: Int - 0 - Operation was successul. |
0fefbfba SK |
537 | */ |
538 | int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn, | |
539 | struct qed_ptt *p_ptt, u8 *mac); | |
540 | ||
541 | /** | |
19198e4e | 542 | * qed_mcp_ov_update_wol(): Send WOL mode to MFW. |
0fefbfba | 543 | * |
19198e4e PK |
544 | * @p_hwfn: HW device data. |
545 | * @p_ptt: P_ptt. | |
546 | * @wol: WOL mode. | |
0fefbfba | 547 | * |
19198e4e | 548 | * Return: Int - 0 - Operation was successul. |
0fefbfba SK |
549 | */ |
550 | int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn, | |
551 | struct qed_ptt *p_ptt, | |
552 | enum qed_ov_wol wol); | |
553 | ||
91420b83 | 554 | /** |
19198e4e | 555 | * qed_mcp_set_led(): Set LED status. |
91420b83 | 556 | * |
19198e4e PK |
557 | * @p_hwfn: HW device data. |
558 | * @p_ptt: P_ptt. | |
559 | * @mode: LED mode. | |
91420b83 | 560 | * |
19198e4e | 561 | * Return: Int - 0 - Operation was successul. |
91420b83 SK |
562 | */ |
563 | int qed_mcp_set_led(struct qed_hwfn *p_hwfn, | |
564 | struct qed_ptt *p_ptt, | |
565 | enum qed_led_mode mode); | |
566 | ||
7a4b21b7 | 567 | /** |
19198e4e | 568 | * qed_mcp_nvm_read(): Read from NVM. |
7a4b21b7 | 569 | * |
19198e4e PK |
570 | * @cdev: Qed dev pointer. |
571 | * @addr: NVM offset. | |
572 | * @p_buf: NVM read buffer. | |
573 | * @len: Buffer len. | |
7a4b21b7 | 574 | * |
19198e4e | 575 | * Return: Int - 0 - Operation was successul. |
7a4b21b7 MY |
576 | */ |
577 | int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len); | |
578 | ||
62e4d438 | 579 | /** |
19198e4e | 580 | * qed_mcp_nvm_write(): Write to NVM. |
62e4d438 | 581 | * |
19198e4e PK |
582 | * @cdev: Qed dev pointer. |
583 | * @addr: NVM offset. | |
584 | * @cmd: NVM command. | |
585 | * @p_buf: NVM write buffer. | |
586 | * @len: Buffer len. | |
62e4d438 | 587 | * |
19198e4e | 588 | * Return: Int - 0 - Operation was successul. |
62e4d438 SRK |
589 | */ |
590 | int qed_mcp_nvm_write(struct qed_dev *cdev, | |
591 | u32 cmd, u32 addr, u8 *p_buf, u32 len); | |
592 | ||
62e4d438 | 593 | /** |
19198e4e | 594 | * qed_mcp_nvm_resp(): Check latest response. |
62e4d438 | 595 | * |
19198e4e PK |
596 | * @cdev: Qed dev pointer. |
597 | * @p_buf: NVM write buffer. | |
62e4d438 | 598 | * |
19198e4e | 599 | * Return: Int - 0 - Operation was successul. |
62e4d438 SRK |
600 | */ |
601 | int qed_mcp_nvm_resp(struct qed_dev *cdev, u8 *p_buf); | |
602 | ||
20675b37 MY |
603 | struct qed_nvm_image_att { |
604 | u32 start_addr; | |
605 | u32 length; | |
606 | }; | |
607 | ||
1ac4329a | 608 | /** |
19198e4e | 609 | * qed_mcp_get_nvm_image_att(): Allows reading a whole nvram image. |
1ac4329a | 610 | * |
19198e4e PK |
611 | * @p_hwfn: HW device data. |
612 | * @image_id: Image to get attributes for. | |
613 | * @p_image_att: Image attributes structure into which to fill data. | |
1ac4329a | 614 | * |
19198e4e | 615 | * Return: Int - 0 - Operation was successul. |
1ac4329a DB |
616 | */ |
617 | int | |
618 | qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn, | |
619 | enum qed_nvm_images image_id, | |
620 | struct qed_nvm_image_att *p_image_att); | |
621 | ||
20675b37 | 622 | /** |
19198e4e | 623 | * qed_mcp_get_nvm_image(): Allows reading a whole nvram image. |
20675b37 | 624 | * |
19198e4e PK |
625 | * @p_hwfn: HW device data. |
626 | * @image_id: image requested for reading. | |
627 | * @p_buffer: allocated buffer into which to fill data. | |
628 | * @buffer_len: length of the allocated buffer. | |
20675b37 | 629 | * |
19198e4e | 630 | * Return: 0 if p_buffer now contains the nvram image. |
20675b37 MY |
631 | */ |
632 | int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn, | |
20675b37 MY |
633 | enum qed_nvm_images image_id, |
634 | u8 *p_buffer, u32 buffer_len); | |
635 | ||
03dc76ca | 636 | /** |
19198e4e | 637 | * qed_mcp_bist_register_test(): Bist register test. |
03dc76ca | 638 | * |
19198e4e PK |
639 | * @p_hwfn: HW device data. |
640 | * @p_ptt: PTT required for register access. | |
03dc76ca | 641 | * |
19198e4e | 642 | * Return: Int - 0 - Operation was successul. |
03dc76ca SRK |
643 | */ |
644 | int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, | |
645 | struct qed_ptt *p_ptt); | |
646 | ||
647 | /** | |
19198e4e | 648 | * qed_mcp_bist_clock_test(): Bist clock test. |
03dc76ca | 649 | * |
19198e4e PK |
650 | * @p_hwfn: HW device data. |
651 | * @p_ptt: PTT required for register access. | |
03dc76ca | 652 | * |
19198e4e | 653 | * Return: Int - 0 - Operation was successul. |
03dc76ca SRK |
654 | */ |
655 | int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, | |
656 | struct qed_ptt *p_ptt); | |
657 | ||
7a4b21b7 | 658 | /** |
19198e4e | 659 | * qed_mcp_bist_nvm_get_num_images(): Bist nvm test - get number of images. |
7a4b21b7 | 660 | * |
19198e4e PK |
661 | * @p_hwfn: HW device data. |
662 | * @p_ptt: PTT required for register access. | |
663 | * @num_images: number of images if operation was | |
7a4b21b7 MY |
664 | * successful. 0 if not. |
665 | * | |
19198e4e | 666 | * Return: Int - 0 - Operation was successul. |
7a4b21b7 | 667 | */ |
43645ce0 SRK |
668 | int qed_mcp_bist_nvm_get_num_images(struct qed_hwfn *p_hwfn, |
669 | struct qed_ptt *p_ptt, | |
670 | u32 *num_images); | |
7a4b21b7 MY |
671 | |
672 | /** | |
19198e4e PK |
673 | * qed_mcp_bist_nvm_get_image_att(): Bist nvm test - get image attributes |
674 | * by index. | |
7a4b21b7 | 675 | * |
19198e4e PK |
676 | * @p_hwfn: HW device data. |
677 | * @p_ptt: PTT required for register access. | |
678 | * @p_image_att: Attributes of image. | |
679 | * @image_index: Index of image to get information for. | |
7a4b21b7 | 680 | * |
19198e4e | 681 | * Return: Int - 0 - Operation was successul. |
7a4b21b7 | 682 | */ |
43645ce0 SRK |
683 | int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn, |
684 | struct qed_ptt *p_ptt, | |
685 | struct bist_nvm_image_att *p_image_att, | |
686 | u32 image_index); | |
7a4b21b7 | 687 | |
2528c389 | 688 | /** |
19198e4e PK |
689 | * qed_mfw_process_tlv_req(): Processes the TLV request from MFW i.e., |
690 | * get the required TLV info | |
691 | * from the qed client and send it to the MFW. | |
2528c389 | 692 | * |
19198e4e PK |
693 | * @p_hwfn: HW device data. |
694 | * @p_ptt: P_ptt. | |
2528c389 | 695 | * |
19198e4e | 696 | * Return: 0 upon success. |
2528c389 SRK |
697 | */ |
698 | int qed_mfw_process_tlv_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); | |
699 | ||
d8d6c5a7 | 700 | /** |
19198e4e PK |
701 | * qed_mcp_send_raw_debug_data(): Send raw debug data to the MFW |
702 | * | |
703 | * @p_hwfn: HW device data. | |
704 | * @p_ptt: P_ptt. | |
705 | * @p_buf: raw debug data buffer. | |
706 | * @size: Buffer size. | |
d8d6c5a7 | 707 | * |
19198e4e | 708 | * Return : Int. |
d8d6c5a7 IR |
709 | */ |
710 | int | |
711 | qed_mcp_send_raw_debug_data(struct qed_hwfn *p_hwfn, | |
712 | struct qed_ptt *p_ptt, u8 *p_buf, u32 size); | |
713 | ||
fe56b9e6 YM |
714 | /* Using hwfn number (and not pf_num) is required since in CMT mode, |
715 | * same pf_num may be used by two different hwfn | |
716 | * TODO - this shouldn't really be in .h file, but until all fields | |
717 | * required during hw-init will be placed in their correct place in shmem | |
718 | * we need it in qed_dev.c [for readin the nvram reflection in shmem]. | |
719 | */ | |
720 | #define MCP_PF_ID_BY_REL(p_hwfn, rel_pfid) (QED_IS_BB((p_hwfn)->cdev) ? \ | |
721 | ((rel_pfid) | \ | |
722 | ((p_hwfn)->abs_pf_id & 1) << 3) : \ | |
723 | rel_pfid) | |
724 | #define MCP_PF_ID(p_hwfn) MCP_PF_ID_BY_REL(p_hwfn, (p_hwfn)->rel_pf_id) | |
725 | ||
fe56b9e6 | 726 | struct qed_mcp_info { |
4ed1eea8 TT |
727 | /* List for mailbox commands which were sent and wait for a response */ |
728 | struct list_head cmd_list; | |
729 | ||
730 | /* Spinlock used for protecting the access to the mailbox commands list | |
731 | * and the sending of the commands. | |
732 | */ | |
733 | spinlock_t cmd_lock; | |
65ed2ffd | 734 | |
b310974e TT |
735 | /* Flag to indicate whether sending a MFW mailbox command is blocked */ |
736 | bool b_block_cmd; | |
737 | ||
65ed2ffd MY |
738 | /* Spinlock used for syncing SW link-changes and link-changes |
739 | * originating from attention context. | |
740 | */ | |
741 | spinlock_t link_lock; | |
b310974e | 742 | |
fe56b9e6 YM |
743 | u32 public_base; |
744 | u32 drv_mb_addr; | |
745 | u32 mfw_mb_addr; | |
746 | u32 port_addr; | |
747 | u16 drv_mb_seq; | |
748 | u16 drv_pulse_seq; | |
cc875c2e YM |
749 | struct qed_mcp_link_params link_input; |
750 | struct qed_mcp_link_state link_output; | |
751 | struct qed_mcp_link_capabilities link_capabilities; | |
fe56b9e6 | 752 | struct qed_mcp_function_info func_info; |
fe56b9e6 YM |
753 | u8 *mfw_mb_cur; |
754 | u8 *mfw_mb_shadow; | |
755 | u16 mfw_mb_length; | |
4ed1eea8 | 756 | u32 mcp_hist; |
645874e5 SRK |
757 | |
758 | /* Capabilties negotiated with the MFW */ | |
759 | u32 capabilities; | |
d8d6c5a7 IR |
760 | |
761 | /* S/N for debug data mailbox commands */ | |
762 | atomic_t dbg_data_seq; | |
fe56b9e6 YM |
763 | }; |
764 | ||
5529bad9 | 765 | struct qed_mcp_mb_params { |
eaa50fc5 TT |
766 | u32 cmd; |
767 | u32 param; | |
768 | void *p_data_src; | |
769 | void *p_data_dst; | |
770 | u8 data_src_size; | |
771 | u8 data_dst_size; | |
772 | u32 mcp_resp; | |
773 | u32 mcp_param; | |
774 | u32 flags; | |
775 | #define QED_MB_FLAG_CAN_SLEEP (0x1 << 0) | |
b310974e | 776 | #define QED_MB_FLAG_AVOID_BLOCK (0x1 << 1) |
eaa50fc5 TT |
777 | #define QED_MB_FLAGS_IS_SET(params, flag) \ |
778 | ({ typeof(params) __params = (params); \ | |
779 | (__params && (__params->flags & QED_MB_FLAG_ ## flag)); }) | |
5529bad9 TT |
780 | }; |
781 | ||
2528c389 SRK |
782 | struct qed_drv_tlv_hdr { |
783 | u8 tlv_type; | |
784 | u8 tlv_length; /* In dwords - not including this header */ | |
785 | u8 tlv_reserved; | |
786 | #define QED_DRV_TLV_FLAGS_CHANGED 0x01 | |
787 | u8 tlv_flags; | |
788 | }; | |
789 | ||
99785a87 AL |
790 | /** |
791 | * qed_mcp_is_ext_speed_supported() - Check if management firmware supports | |
792 | * extended speeds. | |
793 | * @p_hwfn: HW device data. | |
794 | * | |
795 | * Return: true if supported, false otherwise. | |
796 | */ | |
797 | static inline bool | |
798 | qed_mcp_is_ext_speed_supported(const struct qed_hwfn *p_hwfn) | |
799 | { | |
800 | return !!(p_hwfn->mcp_info->capabilities & | |
801 | FW_MB_PARAM_FEATURE_SUPPORT_EXT_SPEED_FEC_CONTROL); | |
802 | } | |
803 | ||
fe56b9e6 | 804 | /** |
19198e4e | 805 | * qed_mcp_cmd_init(): Initialize the interface with the MCP. |
fe56b9e6 | 806 | * |
19198e4e PK |
807 | * @p_hwfn: HW device data. |
808 | * @p_ptt: PTT required for register access. | |
fe56b9e6 | 809 | * |
19198e4e | 810 | * Return: Int. |
fe56b9e6 YM |
811 | */ |
812 | int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, | |
813 | struct qed_ptt *p_ptt); | |
814 | ||
815 | /** | |
19198e4e PK |
816 | * qed_mcp_cmd_port_init(): Initialize the port interface with the MCP |
817 | * | |
818 | * @p_hwfn: HW device data. | |
819 | * @p_ptt: P_ptt. | |
820 | * | |
821 | * Return: Void. | |
fe56b9e6 | 822 | * |
fe56b9e6 YM |
823 | * Can only be called after `num_ports_in_engines' is set |
824 | */ | |
825 | void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, | |
826 | struct qed_ptt *p_ptt); | |
827 | /** | |
19198e4e | 828 | * qed_mcp_free(): Releases resources allocated during the init process. |
fe56b9e6 | 829 | * |
19198e4e | 830 | * @p_hwfn: HW function. |
fe56b9e6 | 831 | * |
19198e4e | 832 | * Return: Int. |
fe56b9e6 YM |
833 | */ |
834 | ||
835 | int qed_mcp_free(struct qed_hwfn *p_hwfn); | |
836 | ||
cc875c2e | 837 | /** |
19198e4e PK |
838 | * qed_mcp_handle_events(): This function is called from the DPC context. |
839 | * After pointing PTT to the mfw mb, check for events sent by | |
840 | * the MCP to the driver and ack them. In case a critical event | |
841 | * detected, it will be handled here, otherwise the work will be | |
842 | * queued to a sleepable work-queue. | |
843 | * | |
844 | * @p_hwfn: HW function. | |
845 | * @p_ptt: PTT required for register access. | |
cc875c2e | 846 | * |
19198e4e | 847 | * Return: Int - 0 - Operation was successul. |
cc875c2e YM |
848 | */ |
849 | int qed_mcp_handle_events(struct qed_hwfn *p_hwfn, | |
850 | struct qed_ptt *p_ptt); | |
851 | ||
5d24bcf1 TT |
852 | enum qed_drv_role { |
853 | QED_DRV_ROLE_OS, | |
854 | QED_DRV_ROLE_KDUMP, | |
855 | }; | |
856 | ||
857 | struct qed_load_req_params { | |
858 | /* Input params */ | |
859 | enum qed_drv_role drv_role; | |
860 | u8 timeout_val; | |
861 | bool avoid_eng_reset; | |
862 | enum qed_override_force_load override_force_load; | |
863 | ||
864 | /* Output params */ | |
865 | u32 load_code; | |
866 | }; | |
867 | ||
fe56b9e6 | 868 | /** |
19198e4e PK |
869 | * qed_mcp_load_req(): Sends a LOAD_REQ to the MFW, and in case the |
870 | * operation succeeds, returns whether this PF is | |
871 | * the first on the engine/port or function. | |
5d24bcf1 | 872 | * |
19198e4e PK |
873 | * @p_hwfn: HW device data. |
874 | * @p_ptt: P_ptt. | |
875 | * @p_params: Params. | |
5d24bcf1 | 876 | * |
19198e4e | 877 | * Return: Int - 0 - Operation was successul. |
fe56b9e6 YM |
878 | */ |
879 | int qed_mcp_load_req(struct qed_hwfn *p_hwfn, | |
880 | struct qed_ptt *p_ptt, | |
5d24bcf1 | 881 | struct qed_load_req_params *p_params); |
fe56b9e6 | 882 | |
666db486 | 883 | /** |
19198e4e | 884 | * qed_mcp_load_done(): Sends a LOAD_DONE message to the MFW. |
666db486 | 885 | * |
19198e4e PK |
886 | * @p_hwfn: HW device data. |
887 | * @p_ptt: P_ptt. | |
666db486 | 888 | * |
19198e4e | 889 | * Return: Int - 0 - Operation was successul. |
666db486 TT |
890 | */ |
891 | int qed_mcp_load_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); | |
892 | ||
1226337a | 893 | /** |
19198e4e | 894 | * qed_mcp_unload_req(): Sends a UNLOAD_REQ message to the MFW. |
1226337a | 895 | * |
19198e4e PK |
896 | * @p_hwfn: HW device data. |
897 | * @p_ptt: P_ptt. | |
1226337a | 898 | * |
19198e4e | 899 | * Return: Int - 0 - Operation was successul. |
1226337a TT |
900 | */ |
901 | int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); | |
902 | ||
903 | /** | |
19198e4e | 904 | * qed_mcp_unload_done(): Sends a UNLOAD_DONE message to the MFW |
1226337a | 905 | * |
19198e4e PK |
906 | * @p_hwfn: HW device data. |
907 | * @p_ptt: P_ptt. | |
1226337a | 908 | * |
19198e4e | 909 | * Return: Int - 0 - Operation was successul. |
1226337a TT |
910 | */ |
911 | int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); | |
912 | ||
fe56b9e6 | 913 | /** |
19198e4e | 914 | * qed_mcp_read_mb(): Read the MFW mailbox into Current buffer. |
fe56b9e6 | 915 | * |
19198e4e PK |
916 | * @p_hwfn: HW device data. |
917 | * @p_ptt: P_ptt. | |
918 | * | |
919 | * Return: Void. | |
fe56b9e6 YM |
920 | */ |
921 | void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, | |
922 | struct qed_ptt *p_ptt); | |
923 | ||
0b55e27d | 924 | /** |
19198e4e | 925 | * qed_mcp_ack_vf_flr(): Ack to mfw that driver finished FLR process for VFs |
0b55e27d | 926 | * |
19198e4e PK |
927 | * @p_hwfn: HW device data. |
928 | * @p_ptt: P_ptt. | |
929 | * @vfs_to_ack: bit mask of all engine VFs for which the PF acks. | |
0b55e27d | 930 | * |
19198e4e | 931 | * Return: Int - 0 - Operation was successul. |
0b55e27d YM |
932 | */ |
933 | int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn, | |
934 | struct qed_ptt *p_ptt, u32 *vfs_to_ack); | |
935 | ||
fe56b9e6 | 936 | /** |
19198e4e PK |
937 | * qed_mcp_fill_shmem_func_info(): Calls during init to read shmem of |
938 | * all function-related info. | |
fe56b9e6 | 939 | * |
19198e4e PK |
940 | * @p_hwfn: HW device data. |
941 | * @p_ptt: P_ptt. | |
fe56b9e6 | 942 | * |
19198e4e | 943 | * Return: 0 upon success. |
fe56b9e6 YM |
944 | */ |
945 | int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn, | |
946 | struct qed_ptt *p_ptt); | |
947 | ||
948 | /** | |
19198e4e | 949 | * qed_mcp_reset(): Reset the MCP using mailbox command. |
fe56b9e6 | 950 | * |
19198e4e PK |
951 | * @p_hwfn: HW device data. |
952 | * @p_ptt: P_ptt. | |
fe56b9e6 | 953 | * |
19198e4e | 954 | * Return: 0 upon success. |
fe56b9e6 YM |
955 | */ |
956 | int qed_mcp_reset(struct qed_hwfn *p_hwfn, | |
957 | struct qed_ptt *p_ptt); | |
958 | ||
4102426f | 959 | /** |
19198e4e PK |
960 | * qed_mcp_nvm_rd_cmd(): Sends an NVM read command request to the MFW to get |
961 | * a buffer. | |
4102426f | 962 | * |
19198e4e PK |
963 | * @p_hwfn: HW device data. |
964 | * @p_ptt: P_ptt. | |
965 | * @cmd: (Command) DRV_MSG_CODE_NVM_GET_FILE_DATA or | |
966 | * DRV_MSG_CODE_NVM_READ_NVRAM commands. | |
967 | * @param: [0:23] - Offset [24:31] - Size. | |
968 | * @o_mcp_resp: MCP response. | |
969 | * @o_mcp_param: MCP response param. | |
970 | * @o_txn_size: Buffer size output. | |
971 | * @o_buf: Pointer to the buffer returned by the MFW. | |
4102426f | 972 | * |
19198e4e | 973 | * Return: 0 upon success. |
4102426f TT |
974 | */ |
975 | int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn, | |
976 | struct qed_ptt *p_ptt, | |
977 | u32 cmd, | |
978 | u32 param, | |
979 | u32 *o_mcp_resp, | |
980 | u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf); | |
981 | ||
b51dab46 | 982 | /** |
19198e4e | 983 | * qed_mcp_phy_sfp_read(): Read from sfp. |
b51dab46 | 984 | * |
19198e4e PK |
985 | * @p_hwfn: HW device data. |
986 | * @p_ptt: PTT required for register access. | |
987 | * @port: transceiver port. | |
988 | * @addr: I2C address. | |
989 | * @offset: offset in sfp. | |
990 | * @len: buffer length. | |
991 | * @p_buf: buffer to read into. | |
b51dab46 | 992 | * |
19198e4e | 993 | * Return: Int - 0 - Operation was successul. |
b51dab46 SRK |
994 | */ |
995 | int qed_mcp_phy_sfp_read(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, | |
996 | u32 port, u32 addr, u32 offset, u32 len, u8 *p_buf); | |
997 | ||
fe56b9e6 | 998 | /** |
19198e4e PK |
999 | * qed_mcp_is_init(): indicates whether the MFW objects [under mcp_info] |
1000 | * are accessible | |
fe56b9e6 | 1001 | * |
19198e4e | 1002 | * @p_hwfn: HW device data. |
fe56b9e6 | 1003 | * |
19198e4e | 1004 | * Return: true if MFW is running and mcp_info is initialized. |
fe56b9e6 YM |
1005 | */ |
1006 | bool qed_mcp_is_init(struct qed_hwfn *p_hwfn); | |
1408cc1f YM |
1007 | |
1008 | /** | |
19198e4e | 1009 | * qed_mcp_config_vf_msix(): Request MFW to configure MSI-X for a VF. |
1408cc1f | 1010 | * |
19198e4e PK |
1011 | * @p_hwfn: HW device data. |
1012 | * @p_ptt: P_ptt. | |
1013 | * @vf_id: absolute inside engine. | |
1014 | * @num: number of entries to request. | |
1408cc1f | 1015 | * |
19198e4e | 1016 | * Return: Int. |
1408cc1f YM |
1017 | */ |
1018 | int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn, | |
1019 | struct qed_ptt *p_ptt, u8 vf_id, u8 num); | |
1020 | ||
4102426f | 1021 | /** |
19198e4e | 1022 | * qed_mcp_halt(): Halt the MCP. |
4102426f | 1023 | * |
19198e4e PK |
1024 | * @p_hwfn: HW device data. |
1025 | * @p_ptt: P_ptt. | |
4102426f | 1026 | * |
19198e4e | 1027 | * Return: 0 upon success. |
4102426f TT |
1028 | */ |
1029 | int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); | |
1030 | ||
1031 | /** | |
19198e4e | 1032 | * qed_mcp_resume: Wake up the MCP. |
4102426f | 1033 | * |
19198e4e PK |
1034 | * @p_hwfn: HW device data. |
1035 | * @p_ptt: P_ptt. | |
4102426f | 1036 | * |
19198e4e | 1037 | * Return: 0 upon success. |
4102426f TT |
1038 | */ |
1039 | int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); | |
1040 | ||
a64b02d5 | 1041 | int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw); |
4b01e519 MC |
1042 | int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw); |
1043 | int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn, | |
1044 | struct qed_ptt *p_ptt, | |
1045 | struct qed_mcp_link_state *p_link, | |
1046 | u8 max_bw); | |
a64b02d5 MC |
1047 | int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn, |
1048 | struct qed_ptt *p_ptt, | |
1049 | struct qed_mcp_link_state *p_link, | |
1050 | u8 min_bw); | |
351a4ded | 1051 | |
4102426f TT |
1052 | int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn, |
1053 | struct qed_ptt *p_ptt, u32 mask_parities); | |
1054 | ||
19198e4e | 1055 | /* qed_mcp_mdump_get_retain(): Gets the mdump retained data from the MFW. |
ebf64bf4 | 1056 | * |
19198e4e PK |
1057 | * @p_hwfn: HW device data. |
1058 | * @p_ptt: P_ptt. | |
1059 | * @p_mdump_retain: mdump retain. | |
ebf64bf4 | 1060 | * |
19198e4e | 1061 | * Return: Int - 0 - Operation was successul. |
ebf64bf4 IR |
1062 | */ |
1063 | int | |
1064 | qed_mcp_mdump_get_retain(struct qed_hwfn *p_hwfn, | |
1065 | struct qed_ptt *p_ptt, | |
1066 | struct mdump_retain_data_stc *p_mdump_retain); | |
1067 | ||
0fefbfba | 1068 | /** |
19198e4e | 1069 | * qed_mcp_set_resc_max_val(): Sets the MFW's max value for the given resource. |
0fefbfba | 1070 | * |
19198e4e PK |
1071 | * @p_hwfn: HW device data. |
1072 | * @p_ptt: P_ptt. | |
1073 | * @res_id: RES ID. | |
1074 | * @resc_max_val: Resec max val. | |
1075 | * @p_mcp_resp: MCP Resp | |
0fefbfba | 1076 | * |
19198e4e | 1077 | * Return: Int - 0 - Operation was successul. |
0fefbfba | 1078 | */ |
9c8517c4 TT |
1079 | int |
1080 | qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn, | |
1081 | struct qed_ptt *p_ptt, | |
1082 | enum qed_resources res_id, | |
1083 | u32 resc_max_val, u32 *p_mcp_resp); | |
0fefbfba | 1084 | |
2edbff8d | 1085 | /** |
19198e4e PK |
1086 | * qed_mcp_get_resc_info(): Gets the MFW allocation info for the given |
1087 | * resource. | |
2edbff8d | 1088 | * |
19198e4e PK |
1089 | * @p_hwfn: HW device data. |
1090 | * @p_ptt: P_ptt. | |
1091 | * @res_id: Res ID. | |
1092 | * @p_mcp_resp: MCP resp. | |
1093 | * @p_resc_num: Resc num. | |
1094 | * @p_resc_start: Resc start. | |
2edbff8d | 1095 | * |
19198e4e | 1096 | * Return: Int - 0 - Operation was successul. |
2edbff8d | 1097 | */ |
9c8517c4 TT |
1098 | int |
1099 | qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn, | |
1100 | struct qed_ptt *p_ptt, | |
1101 | enum qed_resources res_id, | |
1102 | u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start); | |
1103 | ||
1104 | /** | |
19198e4e | 1105 | * qed_mcp_ov_update_eswitch(): Send eswitch mode to MFW. |
9c8517c4 | 1106 | * |
19198e4e PK |
1107 | * @p_hwfn: HW device data. |
1108 | * @p_ptt: P_ptt. | |
1109 | * @eswitch: eswitch mode. | |
9c8517c4 | 1110 | * |
19198e4e | 1111 | * Return: Int - 0 - Operation was successul. |
9c8517c4 TT |
1112 | */ |
1113 | int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn, | |
1114 | struct qed_ptt *p_ptt, | |
1115 | enum qed_ov_eswitch eswitch); | |
1116 | ||
1117 | #define QED_MCP_RESC_LOCK_MIN_VAL RESOURCE_DUMP | |
1118 | #define QED_MCP_RESC_LOCK_MAX_VAL 31 | |
1119 | ||
1120 | enum qed_resc_lock { | |
1121 | QED_RESC_LOCK_DBG_DUMP = QED_MCP_RESC_LOCK_MIN_VAL, | |
db82f70e | 1122 | QED_RESC_LOCK_PTP_PORT0, |
1123 | QED_RESC_LOCK_PTP_PORT1, | |
1124 | QED_RESC_LOCK_PTP_PORT2, | |
1125 | QED_RESC_LOCK_PTP_PORT3, | |
f470f22c | 1126 | QED_RESC_LOCK_RESC_ALLOC = QED_MCP_RESC_LOCK_MAX_VAL, |
1127 | QED_RESC_LOCK_RESC_INVALID | |
9c8517c4 | 1128 | }; |
18a69e36 MY |
1129 | |
1130 | /** | |
19198e4e | 1131 | * qed_mcp_initiate_pf_flr(): Initiates PF FLR. |
18a69e36 | 1132 | * |
19198e4e PK |
1133 | * @p_hwfn: HW device data. |
1134 | * @p_ptt: P_ptt. | |
18a69e36 | 1135 | * |
19198e4e | 1136 | * Return: Int - 0 - Operation was successul. |
18a69e36 MY |
1137 | */ |
1138 | int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); | |
95691c9c TT |
1139 | struct qed_resc_lock_params { |
1140 | /* Resource number [valid values are 0..31] */ | |
1141 | u8 resource; | |
1142 | ||
1143 | /* Lock timeout value in seconds [default, none or 1..254] */ | |
1144 | u8 timeout; | |
1145 | #define QED_MCP_RESC_LOCK_TO_DEFAULT 0 | |
1146 | #define QED_MCP_RESC_LOCK_TO_NONE 255 | |
1147 | ||
1148 | /* Number of times to retry locking */ | |
1149 | u8 retry_num; | |
f470f22c | 1150 | #define QED_MCP_RESC_LOCK_RETRY_CNT_DFLT 10 |
95691c9c TT |
1151 | |
1152 | /* The interval in usec between retries */ | |
1153 | u16 retry_interval; | |
f470f22c | 1154 | #define QED_MCP_RESC_LOCK_RETRY_VAL_DFLT 10000 |
95691c9c TT |
1155 | |
1156 | /* Use sleep or delay between retries */ | |
1157 | bool sleep_b4_retry; | |
1158 | ||
1159 | /* Will be set as true if the resource is free and granted */ | |
1160 | bool b_granted; | |
1161 | ||
1162 | /* Will be filled with the resource owner. | |
1163 | * [0..15 = PF0-15, 16 = MFW] | |
1164 | */ | |
1165 | u8 owner; | |
1166 | }; | |
1167 | ||
1168 | /** | |
19198e4e | 1169 | * qed_mcp_resc_lock(): Acquires MFW generic resource lock. |
95691c9c | 1170 | * |
19198e4e PK |
1171 | * @p_hwfn: HW device data. |
1172 | * @p_ptt: P_ptt. | |
1173 | * @p_params: Params. | |
95691c9c | 1174 | * |
19198e4e | 1175 | * Return: Int - 0 - Operation was successul. |
95691c9c TT |
1176 | */ |
1177 | int | |
1178 | qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, | |
1179 | struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params); | |
1180 | ||
1181 | struct qed_resc_unlock_params { | |
1182 | /* Resource number [valid values are 0..31] */ | |
1183 | u8 resource; | |
1184 | ||
1185 | /* Allow to release a resource even if belongs to another PF */ | |
1186 | bool b_force; | |
1187 | ||
1188 | /* Will be set as true if the resource is released */ | |
1189 | bool b_released; | |
1190 | }; | |
1191 | ||
1192 | /** | |
19198e4e | 1193 | * qed_mcp_resc_unlock(): Releases MFW generic resource lock. |
95691c9c | 1194 | * |
19198e4e PK |
1195 | * @p_hwfn: HW device data. |
1196 | * @p_ptt: P_ptt. | |
1197 | * @p_params: Params. | |
95691c9c | 1198 | * |
19198e4e | 1199 | * Return: Int - 0 - Operation was successul. |
95691c9c TT |
1200 | */ |
1201 | int | |
1202 | qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn, | |
1203 | struct qed_ptt *p_ptt, | |
1204 | struct qed_resc_unlock_params *p_params); | |
1205 | ||
f470f22c | 1206 | /** |
19198e4e PK |
1207 | * qed_mcp_resc_lock_default_init(): Default initialization for |
1208 | * lock/unlock resource structs. | |
f470f22c | 1209 | * |
19198e4e PK |
1210 | * @p_lock: lock params struct to be initialized; Can be NULL. |
1211 | * @p_unlock: unlock params struct to be initialized; Can be NULL. | |
1212 | * @resource: the requested resource. | |
1213 | * @b_is_permanent: disable retries & aging when set. | |
1214 | * | |
1215 | * Return: Void. | |
f470f22c | 1216 | */ |
1217 | void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock, | |
1218 | struct qed_resc_unlock_params *p_unlock, | |
1219 | enum qed_resc_lock | |
1220 | resource, bool b_is_permanent); | |
df9c716d SRK |
1221 | |
1222 | /** | |
19198e4e PK |
1223 | * qed_mcp_is_smart_an_supported(): Return whether management firmware |
1224 | * support smart AN | |
df9c716d | 1225 | * |
19198e4e | 1226 | * @p_hwfn: HW device data. |
df9c716d | 1227 | * |
19198e4e | 1228 | * Return: bool true if feature is supported. |
df9c716d SRK |
1229 | */ |
1230 | bool qed_mcp_is_smart_an_supported(struct qed_hwfn *p_hwfn); | |
1231 | ||
645874e5 | 1232 | /** |
19198e4e PK |
1233 | * qed_mcp_get_capabilities(): Learn of supported MFW features; |
1234 | * To be done during early init. | |
645874e5 | 1235 | * |
19198e4e PK |
1236 | * @p_hwfn: HW device data. |
1237 | * @p_ptt: P_ptt. | |
1238 | * | |
1239 | * Return: Int. | |
645874e5 SRK |
1240 | */ |
1241 | int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); | |
f470f22c | 1242 | |
645874e5 | 1243 | /** |
19198e4e PK |
1244 | * qed_mcp_set_capabilities(): Inform MFW of set of features supported |
1245 | * by driver. Should be done inside the content | |
1246 | * of the LOAD_REQ. | |
1247 | * | |
1248 | * @p_hwfn: HW device data. | |
1249 | * @p_ptt: P_ptt. | |
645874e5 | 1250 | * |
19198e4e | 1251 | * Return: Int. |
645874e5 SRK |
1252 | */ |
1253 | int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); | |
43645ce0 | 1254 | |
cac6f691 | 1255 | /** |
19198e4e PK |
1256 | * qed_mcp_read_ufp_config(): Read ufp config from the shared memory. |
1257 | * | |
1258 | * @p_hwfn: HW device data. | |
1259 | * @p_ptt: P_ptt. | |
cac6f691 | 1260 | * |
19198e4e | 1261 | * Return: Void. |
cac6f691 SRK |
1262 | */ |
1263 | void qed_mcp_read_ufp_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); | |
1264 | ||
43645ce0 | 1265 | /** |
19198e4e PK |
1266 | * qed_mcp_nvm_info_populate(): Populate the nvm info shadow in the given |
1267 | * hardware function. | |
1268 | * | |
1269 | * @p_hwfn: HW device data. | |
43645ce0 | 1270 | * |
19198e4e | 1271 | * Return: Int. |
43645ce0 SRK |
1272 | */ |
1273 | int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn); | |
1274 | ||
13cf8aab | 1275 | /** |
19198e4e PK |
1276 | * qed_mcp_nvm_info_free(): Delete nvm info shadow in the given |
1277 | * hardware function. | |
13cf8aab | 1278 | * |
19198e4e PK |
1279 | * @p_hwfn: HW device data. |
1280 | * | |
1281 | * Return: Void. | |
13cf8aab SRK |
1282 | */ |
1283 | void qed_mcp_nvm_info_free(struct qed_hwfn *p_hwfn); | |
1284 | ||
79284ade | 1285 | /** |
19198e4e | 1286 | * qed_mcp_get_engine_config(): Get the engine affinity configuration. |
79284ade | 1287 | * |
19198e4e PK |
1288 | * @p_hwfn: HW device data. |
1289 | * @p_ptt: P_ptt. | |
1290 | * | |
1291 | * Return: Int. | |
79284ade MK |
1292 | */ |
1293 | int qed_mcp_get_engine_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); | |
1294 | ||
1295 | /** | |
19198e4e | 1296 | * qed_mcp_get_ppfid_bitmap(): Get the PPFID bitmap. |
79284ade | 1297 | * |
19198e4e PK |
1298 | * @p_hwfn: HW device data. |
1299 | * @p_ptt: P_ptt. | |
1300 | * | |
1301 | * Return: Int. | |
79284ade MK |
1302 | */ |
1303 | int qed_mcp_get_ppfid_bitmap(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); | |
1304 | ||
2d4c8495 | 1305 | /** |
19198e4e PK |
1306 | * qed_mcp_nvm_get_cfg(): Get NVM config attribute value. |
1307 | * | |
1308 | * @p_hwfn: HW device data. | |
1309 | * @p_ptt: P_ptt. | |
1310 | * @option_id: Option ID. | |
1311 | * @entity_id: Entity ID. | |
1312 | * @flags: Flags. | |
1313 | * @p_buf: Buf. | |
1314 | * @p_len: Len. | |
2d4c8495 | 1315 | * |
19198e4e | 1316 | * Return: Int. |
2d4c8495 SRK |
1317 | */ |
1318 | int qed_mcp_nvm_get_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, | |
1319 | u16 option_id, u8 entity_id, u16 flags, u8 *p_buf, | |
1320 | u32 *p_len); | |
1321 | ||
38eabdf0 | 1322 | /** |
19198e4e | 1323 | * qed_mcp_nvm_set_cfg(): Set NVM config attribute value. |
38eabdf0 | 1324 | * |
19198e4e PK |
1325 | * @p_hwfn: HW device data. |
1326 | * @p_ptt: P_ptt. | |
1327 | * @option_id: Option ID. | |
1328 | * @entity_id: Entity ID. | |
1329 | * @flags: Flags. | |
1330 | * @p_buf: Buf. | |
1331 | * @len: Len. | |
1332 | * | |
1333 | * Return: Int. | |
38eabdf0 SRK |
1334 | */ |
1335 | int qed_mcp_nvm_set_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, | |
1336 | u16 option_id, u8 entity_id, u16 flags, u8 *p_buf, | |
1337 | u32 len); | |
fe56b9e6 | 1338 | #endif |