[linux-2.6-block.git] / drivers / net / ethernet / qlogic / qed / qed_int.h

/* QLogic qed NIC Driver
 * Copyright (c) 2015 QLogic Corporation
 *
 * This software is available under the terms of the GNU General Public License
 * (GPL) Version 2, available from the file COPYING in the main directory of
 * this source tree.
 */

#ifndef _QED_INT_H
#define _QED_INT_H

#include <linux/types.h>
#include <linux/slab.h>
#include "qed.h"

/* Fields of IGU PF CONFIGRATION REGISTER */
#define IGU_PF_CONF_FUNC_EN       (0x1 << 0)    /* function enable        */
#define IGU_PF_CONF_MSI_MSIX_EN   (0x1 << 1)    /* MSI/MSIX enable        */
#define IGU_PF_CONF_INT_LINE_EN   (0x1 << 2)    /* INT enable             */
#define IGU_PF_CONF_ATTN_BIT_EN   (0x1 << 3)    /* attention enable       */
#define IGU_PF_CONF_SINGLE_ISR_EN (0x1 << 4)    /* single ISR mode enable */
#define IGU_PF_CONF_SIMD_MODE     (0x1 << 5)    /* simd all ones mode     */
/* Fields of IGU VF CONFIGRATION REGISTER */
#define IGU_VF_CONF_FUNC_EN        (0x1 << 0)	/* function enable        */
#define IGU_VF_CONF_MSI_MSIX_EN    (0x1 << 1)	/* MSI/MSIX enable        */
#define IGU_VF_CONF_SINGLE_ISR_EN  (0x1 << 4)	/* single ISR mode enable */
#define IGU_VF_CONF_PARENT_MASK    (0xF)	/* Parent PF              */
#define IGU_VF_CONF_PARENT_SHIFT   5		/* Parent PF              */

/* Igu control commands
 */
enum igu_ctrl_cmd {
	IGU_CTRL_CMD_TYPE_RD,
	IGU_CTRL_CMD_TYPE_WR,
	MAX_IGU_CTRL_CMD
};

/* Control register for the IGU command register
 */
struct igu_ctrl_reg {
	u32 ctrl_data;
#define IGU_CTRL_REG_FID_MASK           0xFFFF  /* Opaque_FID	 */
#define IGU_CTRL_REG_FID_SHIFT          0
#define IGU_CTRL_REG_PXP_ADDR_MASK      0xFFF   /* Command address */
#define IGU_CTRL_REG_PXP_ADDR_SHIFT     16
#define IGU_CTRL_REG_RESERVED_MASK      0x1
#define IGU_CTRL_REG_RESERVED_SHIFT     28
#define IGU_CTRL_REG_TYPE_MASK          0x1 /* use enum igu_ctrl_cmd */
#define IGU_CTRL_REG_TYPE_SHIFT         31
};

enum qed_coalescing_fsm {
	QED_COAL_RX_STATE_MACHINE,
	QED_COAL_TX_STATE_MACHINE
};

/**
 * @brief qed_int_cau_conf_pi - configure cau for a given
 *        status block
 *
 * @param p_hwfn
 * @param p_ptt
 * @param igu_sb_id
 * @param pi_index
 * @param state
 * @param timeset
 */
void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn,
			 struct qed_ptt *p_ptt,
			 u16 igu_sb_id,
			 u32 pi_index,
			 enum qed_coalescing_fsm coalescing_fsm,
			 u8 timeset);

/**
 * @brief qed_int_igu_enable_int - enable device interrupts
 *
 * @param p_hwfn
 * @param p_ptt
 * @param int_mode - interrupt mode to use
 */
void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn,
			    struct qed_ptt *p_ptt,
			    enum qed_int_mode int_mode);

/**
 * @brief qed_int_igu_disable_int - disable device interrupts
 *
 * @param p_hwfn
 * @param p_ptt
 */
void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn,
			     struct qed_ptt *p_ptt);

/**
 * @brief qed_int_igu_read_sisr_reg - Reads the single isr multiple dpc
 *        register from igu.
 *
 * @param p_hwfn
 *
 * @return u64
 */
u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn);

#define QED_SP_SB_ID 0xffff
/**
 * @brief qed_int_sb_init - Initializes the sb_info structure.
 *
 * once the structure is initialized it can be passed to sb related functions.
 *
 * @param p_hwfn
 * @param p_ptt
 * @param sb_info	points to an uninitialized (but
 *			allocated) sb_info structure
 * @param sb_virt_addr
 * @param sb_phy_addr
 * @param sb_id	the sb_id to be used (zero based in driver)
 *			should use QED_SP_SB_ID for SP Status block
 *
 * @return int
 */
int qed_int_sb_init(struct qed_hwfn *p_hwfn,
		    struct qed_ptt *p_ptt,
		    struct qed_sb_info *sb_info,
		    void *sb_virt_addr,
		    dma_addr_t sb_phy_addr,
		    u16 sb_id);
/**
 * @brief qed_int_sb_setup - Setup the sb.
 *
 * @param p_hwfn
 * @param p_ptt
 * @param sb_info	initialized sb_info structure
 */
void qed_int_sb_setup(struct qed_hwfn *p_hwfn,
		      struct qed_ptt *p_ptt,
		      struct qed_sb_info *sb_info);

/**
 * @brief qed_int_sb_release - releases the sb_info structure.
 *
 * once the structure is released, it's memory can be freed
 *
 * @param p_hwfn
 * @param sb_info	points to an allocated sb_info structure
 * @param sb_id		the sb_id to be used (zero based in driver)
 *			should never be equal to QED_SP_SB_ID
 *			(SP Status block)
 *
 * @return int
 */
int qed_int_sb_release(struct qed_hwfn *p_hwfn,
		       struct qed_sb_info *sb_info,
		       u16 sb_id);

/**
 * @brief qed_int_sp_dpc - To be called when an interrupt is received on the
 *        default status block.
 *
 * @param p_hwfn - pointer to hwfn
 *
 */
void qed_int_sp_dpc(unsigned long hwfn_cookie);

/**
 * @brief qed_int_get_num_sbs - get the number of status
 *        blocks configured for this funciton in the igu.
 *
 * @param p_hwfn
 * @param p_sb_cnt_info
 *
 * @return int - number of status blocks configured
 */
void qed_int_get_num_sbs(struct qed_hwfn	*p_hwfn,
			 struct qed_sb_cnt_info *p_sb_cnt_info);

/**
 * @brief qed_int_disable_post_isr_release - performs the cleanup post ISR
 *        release. The API need to be called after releasing all slowpath IRQs
 *        of the device.
 *
 * @param cdev
 *
 */
void qed_int_disable_post_isr_release(struct qed_dev *cdev);

#define QED_CAU_DEF_RX_TIMER_RES 0
#define QED_CAU_DEF_TX_TIMER_RES 0

#define QED_SB_ATT_IDX  0x0001
#define QED_SB_EVENT_MASK       0x0003

#define SB_ALIGNED_SIZE(p_hwfn)	\
	ALIGNED_TYPE_SIZE(struct status_block, p_hwfn)

struct qed_igu_block {
	u8	status;
#define QED_IGU_STATUS_FREE     0x01
#define QED_IGU_STATUS_VALID    0x02
#define QED_IGU_STATUS_PF       0x04

	u8	vector_number;
	u8	function_id;
	u8	is_pf;
};

struct qed_igu_map {
	struct qed_igu_block igu_blocks[MAX_TOT_SB_PER_PATH];
};

struct qed_igu_info {
	struct qed_igu_map	igu_map;
	u16			igu_dsb_id;
	u16			igu_base_sb;
	u16			igu_base_sb_iov;
	u16			igu_sb_cnt;
	u16			igu_sb_cnt_iov;
	u16			free_blks;
};

/* TODO Names of function may change... */
void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn,
			      struct qed_ptt *p_ptt,
			      bool b_set,
			      bool b_slowpath);

void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn);

/**
 * @brief qed_int_igu_read_cam - Reads the IGU CAM.
 *	This function needs to be called during hardware
 *	prepare. It reads the info from igu cam to know which
 *	status block is the default / base status block etc.
 *
 * @param p_hwfn
 * @param p_ptt
 *
 * @return int
 */
int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn,
			 struct qed_ptt *p_ptt);

typedef int (*qed_int_comp_cb_t)(struct qed_hwfn *p_hwfn,
				 void *cookie);
/**
 * @brief qed_int_register_cb - Register callback func for
 *      slowhwfn statusblock.
 *
 *	Every protocol that uses the slowhwfn status block
 *	should register a callback function that will be called
 *	once there is an update of the sp status block.
 *
 * @param p_hwfn
 * @param comp_cb - function to be called when there is an
 *                  interrupt on the sp sb
 *
 * @param cookie  - passed to the callback function
 * @param sb_idx  - OUT parameter which gives the chosen index
 *                  for this protocol.
 * @param p_fw_cons  - pointer to the actual address of the
 *                     consumer for this protocol.
 *
 * @return int
 */
int qed_int_register_cb(struct qed_hwfn *p_hwfn,
			qed_int_comp_cb_t comp_cb,
			void *cookie,
			u8 *sb_idx,
			__le16 **p_fw_cons);

/**
 * @brief qed_int_unregister_cb - Unregisters callback
 *      function from sp sb.
 *      Partner of qed_int_register_cb -> should be called
 *      when no longer required.
 *
 * @param p_hwfn
 * @param pi
 *
 * @return int
 */
int qed_int_unregister_cb(struct qed_hwfn *p_hwfn,
			  u8 pi);

/**
 * @brief qed_int_get_sp_sb_id - Get the slowhwfn sb id.
 *
 * @param p_hwfn
 *
 * @return u16
 */
u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn);

/**
 * @brief Status block cleanup. Should be called for each status
 *        block that will be used -> both PF / VF
 *
 * @param p_hwfn
 * @param p_ptt
 * @param sb_id		- igu status block id
 * @param cleanup_set	- set(1) / clear(0)
 * @param opaque_fid    - the function for which to perform
 *			cleanup, for example a PF on behalf of
 *			its VFs.
 */
void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn,
			    struct qed_ptt *p_ptt,
			    u32 sb_id,
			    bool cleanup_set,
			    u16 opaque_fid);

/**
 * @brief Status block cleanup. Should be called for each status
 *        block that will be used -> both PF / VF
 *
 * @param p_hwfn
 * @param p_ptt
 * @param sb_id		- igu status block id
 * @param opaque	- opaque fid of the sb owner.
 * @param cleanup_set	- set(1) / clear(0)
 */
void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn,
				     struct qed_ptt *p_ptt,
				     u32 sb_id,
				     u16 opaque,
				     bool b_set);

/**
 * @brief qed_int_cau_conf - configure cau for a given status
 *        block
 *
 * @param p_hwfn
 * @param ptt
 * @param sb_phys
 * @param igu_sb_id
 * @param vf_number
 * @param vf_valid
 */
void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn,
			 struct qed_ptt *p_ptt,
			 dma_addr_t sb_phys,
			 u16 igu_sb_id,
			 u16 vf_number,
			 u8 vf_valid);

/**
 * @brief qed_int_alloc
 *
 * @param p_hwfn
 * @param p_ptt
 *
 * @return int
 */
int qed_int_alloc(struct qed_hwfn *p_hwfn,
		  struct qed_ptt *p_ptt);

/**
 * @brief qed_int_free
 *
 * @param p_hwfn
 */
void qed_int_free(struct qed_hwfn *p_hwfn);

/**
 * @brief qed_int_setup
 *
 * @param p_hwfn
 * @param p_ptt
 */
void qed_int_setup(struct qed_hwfn *p_hwfn,
		   struct qed_ptt *p_ptt);

/**
 * @brief - Returns an Rx queue index appropriate for usage with given SB.
 *
 * @param p_hwfn
 * @param sb_id - absolute index of SB
 *
 * @return index of Rx queue
 */
u16 qed_int_queue_id_from_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id);

/**
 * @brief - Enable Interrupt & Attention for hw function
 *
 * @param p_hwfn
 * @param p_ptt
 * @param int_mode
 *
 * @return int
 */
int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
		       enum qed_int_mode int_mode);

/**
 * @brief - Initialize CAU status block entry
 *
 * @param p_hwfn
 * @param p_sb_entry
 * @param pf_id
 * @param vf_number
 * @param vf_valid
 */
void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn,
			   struct cau_sb_entry *p_sb_entry,
			   u8 pf_id,
			   u16 vf_number,
			   u8 vf_valid);

#define QED_MAPPING_MEMORY_SIZE(dev)	(NUM_OF_SBS(dev))

#endif
Commit	Line	Data
fe56b9e6 YM	1	/* QLogic qed NIC Driver
	2	* Copyright (c) 2015 QLogic Corporation
	3	*
	4	* This software is available under the terms of the GNU General Public License
	5	* (GPL) Version 2, available from the file COPYING in the main directory of
	6	* this source tree.
	7	*/
	8
	9	#ifndef _QED_INT_H
	10	#define _QED_INT_H
	11
	12	#include <linux/types.h>
	13	#include <linux/slab.h>
	14	#include "qed.h"
	15
	16	/* Fields of IGU PF CONFIGRATION REGISTER */
	17	#define IGU_PF_CONF_FUNC_EN (0x1 << 0) /* function enable */
	18	#define IGU_PF_CONF_MSI_MSIX_EN (0x1 << 1) /* MSI/MSIX enable */
	19	#define IGU_PF_CONF_INT_LINE_EN (0x1 << 2) /* INT enable */
	20	#define IGU_PF_CONF_ATTN_BIT_EN (0x1 << 3) /* attention enable */
	21	#define IGU_PF_CONF_SINGLE_ISR_EN (0x1 << 4) /* single ISR mode enable */
	22	#define IGU_PF_CONF_SIMD_MODE (0x1 << 5) /* simd all ones mode */
1408cc1f YM	23	/* Fields of IGU VF CONFIGRATION REGISTER */
	24	#define IGU_VF_CONF_FUNC_EN (0x1 << 0) /* function enable */
	25	#define IGU_VF_CONF_MSI_MSIX_EN (0x1 << 1) /* MSI/MSIX enable */
	26	#define IGU_VF_CONF_SINGLE_ISR_EN (0x1 << 4) /* single ISR mode enable */
	27	#define IGU_VF_CONF_PARENT_MASK (0xF) /* Parent PF */
	28	#define IGU_VF_CONF_PARENT_SHIFT 5 /* Parent PF */
fe56b9e6 YM	29
	30	/* Igu control commands
	31	*/
	32	enum igu_ctrl_cmd {
	33	IGU_CTRL_CMD_TYPE_RD,
	34	IGU_CTRL_CMD_TYPE_WR,
	35	MAX_IGU_CTRL_CMD
	36	};
	37
	38	/* Control register for the IGU command register
	39	*/
	40	struct igu_ctrl_reg {
	41	u32 ctrl_data;
	42	#define IGU_CTRL_REG_FID_MASK 0xFFFF /* Opaque_FID */
	43	#define IGU_CTRL_REG_FID_SHIFT 0
	44	#define IGU_CTRL_REG_PXP_ADDR_MASK 0xFFF /* Command address */
	45	#define IGU_CTRL_REG_PXP_ADDR_SHIFT 16
	46	#define IGU_CTRL_REG_RESERVED_MASK 0x1
	47	#define IGU_CTRL_REG_RESERVED_SHIFT 28
	48	#define IGU_CTRL_REG_TYPE_MASK 0x1 /* use enum igu_ctrl_cmd */
	49	#define IGU_CTRL_REG_TYPE_SHIFT 31
	50	};
	51
	52	enum qed_coalescing_fsm {
	53	QED_COAL_RX_STATE_MACHINE,
	54	QED_COAL_TX_STATE_MACHINE
	55	};
	56
	57	/**
	58	* @brief qed_int_cau_conf_pi - configure cau for a given
	59	* status block
	60	*
	61	* @param p_hwfn
	62	* @param p_ptt
	63	* @param igu_sb_id
	64	* @param pi_index
	65	* @param state
	66	* @param timeset
	67	*/
	68	void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn,
	69	struct qed_ptt *p_ptt,
	70	u16 igu_sb_id,
	71	u32 pi_index,
	72	enum qed_coalescing_fsm coalescing_fsm,
	73	u8 timeset);
	74
	75	/**
	76	* @brief qed_int_igu_enable_int - enable device interrupts
	77	*
	78	* @param p_hwfn
	79	* @param p_ptt
	80	* @param int_mode - interrupt mode to use
	81	*/
	82	void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn,
	83	struct qed_ptt *p_ptt,
	84	enum qed_int_mode int_mode);
	85
	86	/**
	87	* @brief qed_int_igu_disable_int - disable device interrupts
	88	*
	89	* @param p_hwfn
	90	* @param p_ptt
	91	*/
	92	void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn,
93	struct qed_ptt *p_ptt);
94
95	/**
96	* @brief qed_int_igu_read_sisr_reg - Reads the single isr multiple dpc
97	* register from igu.
98	*
99	* @param p_hwfn
100	*
101	* @return u64
102	*/
103	u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn);
104
105	#define QED_SP_SB_ID 0xffff
106	/**
107	* @brief qed_int_sb_init - Initializes the sb_info structure.
108	*
109	* once the structure is initialized it can be passed to sb related functions.
110	*
111	* @param p_hwfn
112	* @param p_ptt
113	* @param sb_info points to an uninitialized (but
114	* allocated) sb_info structure
115	* @param sb_virt_addr
116	* @param sb_phy_addr
117	* @param sb_id the sb_id to be used (zero based in driver)
118	* should use QED_SP_SB_ID for SP Status block
119	*
120	* @return int
121	*/
122	int qed_int_sb_init(struct qed_hwfn *p_hwfn,
123	struct qed_ptt *p_ptt,
124	struct qed_sb_info *sb_info,
125	void *sb_virt_addr,
126	dma_addr_t sb_phy_addr,
127	u16 sb_id);
128	/**
129	* @brief qed_int_sb_setup - Setup the sb.
130	*
131	* @param p_hwfn
132	* @param p_ptt
133	* @param sb_info initialized sb_info structure
134	*/
135	void qed_int_sb_setup(struct qed_hwfn *p_hwfn,
136	struct qed_ptt *p_ptt,
137	struct qed_sb_info *sb_info);
138
139	/**
140	* @brief qed_int_sb_release - releases the sb_info structure.
141	*
142	* once the structure is released, it's memory can be freed
143	*
144	* @param p_hwfn
145	* @param sb_info points to an allocated sb_info structure
146	* @param sb_id the sb_id to be used (zero based in driver)
147	* should never be equal to QED_SP_SB_ID
148	* (SP Status block)
149	*
150	* @return int
151	*/
152	int qed_int_sb_release(struct qed_hwfn *p_hwfn,
153	struct qed_sb_info *sb_info,
154	u16 sb_id);
155
156	/**
157	* @brief qed_int_sp_dpc - To be called when an interrupt is received on the
158	* default status block.
159	*
160	* @param p_hwfn - pointer to hwfn
161	*
162	*/
163	void qed_int_sp_dpc(unsigned long hwfn_cookie);
164
165	/**
166	* @brief qed_int_get_num_sbs - get the number of status
167	* blocks configured for this funciton in the igu.
168	*
169	* @param p_hwfn
4ac801b7	170	* @param p_sb_cnt_info
fe56b9e6 YM	171	*
	172	* @return int - number of status blocks configured
	173	*/
4ac801b7 YM	174	void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn,
4ac801b7 YM	175	struct qed_sb_cnt_info *p_sb_cnt_info);
fe56b9e6 YM	176
fe56b9e6 YM	177	/**
8f16bc97 SK	178	* @brief qed_int_disable_post_isr_release - performs the cleanup post ISR
	179	* release. The API need to be called after releasing all slowpath IRQs
	180	* of the device.
	181	*
	182	* @param cdev
fe56b9e6	183	*
fe56b9e6	184	*/
8f16bc97	185	void qed_int_disable_post_isr_release(struct qed_dev *cdev);
fe56b9e6 YM	186
	187	#define QED_CAU_DEF_RX_TIMER_RES 0
	188	#define QED_CAU_DEF_TX_TIMER_RES 0
	189
	190	#define QED_SB_ATT_IDX 0x0001
	191	#define QED_SB_EVENT_MASK 0x0003
	192
	193	#define SB_ALIGNED_SIZE(p_hwfn) \
	194	ALIGNED_TYPE_SIZE(struct status_block, p_hwfn)
	195
	196	struct qed_igu_block {
	197	u8 status;
	198	#define QED_IGU_STATUS_FREE 0x01
	199	#define QED_IGU_STATUS_VALID 0x02
	200	#define QED_IGU_STATUS_PF 0x04
	201
	202	u8 vector_number;
	203	u8 function_id;
	204	u8 is_pf;
	205	};
	206
	207	struct qed_igu_map {
	208	struct qed_igu_block igu_blocks[MAX_TOT_SB_PER_PATH];
	209	};
	210
	211	struct qed_igu_info {
	212	struct qed_igu_map igu_map;
	213	u16 igu_dsb_id;
	214	u16 igu_base_sb;
	215	u16 igu_base_sb_iov;
	216	u16 igu_sb_cnt;
	217	u16 igu_sb_cnt_iov;
	218	u16 free_blks;
	219	};
	220
	221	/* TODO Names of function may change... */
	222	void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn,
	223	struct qed_ptt *p_ptt,
	224	bool b_set,
	225	bool b_slowpath);
	226
	227	void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn);
	228
	229	/**
	230	* @brief qed_int_igu_read_cam - Reads the IGU CAM.
	231	* This function needs to be called during hardware
	232	* prepare. It reads the info from igu cam to know which
	233	* status block is the default / base status block etc.
	234	*
	235	* @param p_hwfn
	236	* @param p_ptt
	237	*
	238	* @return int
	239	*/
	240	int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn,
	241	struct qed_ptt *p_ptt);
	242
	243	typedef int (qed_int_comp_cb_t)(struct qed_hwfn p_hwfn,
	244	void *cookie);
	245	/**
	246	* @brief qed_int_register_cb - Register callback func for
	247	* slowhwfn statusblock.
	248	*
	249	* Every protocol that uses the slowhwfn status block
250	* should register a callback function that will be called
251	* once there is an update of the sp status block.
252	*
253	* @param p_hwfn
254	* @param comp_cb - function to be called when there is an
255	* interrupt on the sp sb
256	*
257	* @param cookie - passed to the callback function
258	* @param sb_idx - OUT parameter which gives the chosen index
259	* for this protocol.
260	* @param p_fw_cons - pointer to the actual address of the
261	* consumer for this protocol.
262	*
263	* @return int
264	*/
265	int qed_int_register_cb(struct qed_hwfn *p_hwfn,
266	qed_int_comp_cb_t comp_cb,
267	void *cookie,
268	u8 *sb_idx,
269	__le16 **p_fw_cons);
270
271	/**
272	* @brief qed_int_unregister_cb - Unregisters callback
273	* function from sp sb.
274	* Partner of qed_int_register_cb -> should be called
275	* when no longer required.
276	*
277	* @param p_hwfn
278	* @param pi
279	*
280	* @return int
281	*/
282	int qed_int_unregister_cb(struct qed_hwfn *p_hwfn,
283	u8 pi);
284
285	/**
286	* @brief qed_int_get_sp_sb_id - Get the slowhwfn sb id.
287	*
288	* @param p_hwfn
289	*
290	* @return u16
291	*/
292	u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn);
293
294	/**
295	* @brief Status block cleanup. Should be called for each status
296	* block that will be used -> both PF / VF
297	*
298	* @param p_hwfn
299	* @param p_ptt
300	* @param sb_id - igu status block id
301	* @param cleanup_set - set(1) / clear(0)
302	* @param opaque_fid - the function for which to perform
303	* cleanup, for example a PF on behalf of
304	* its VFs.
305	*/
306	void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn,
307	struct qed_ptt *p_ptt,
308	u32 sb_id,
309	bool cleanup_set,
310	u16 opaque_fid);
311
312	/**
313	* @brief Status block cleanup. Should be called for each status
314	* block that will be used -> both PF / VF
315	*
316	* @param p_hwfn
317	* @param p_ptt
318	* @param sb_id - igu status block id
319	* @param opaque - opaque fid of the sb owner.
320	* @param cleanup_set - set(1) / clear(0)
321	*/
322	void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn,
323	struct qed_ptt *p_ptt,
324	u32 sb_id,
325	u16 opaque,
326	bool b_set);
327
328	/**
329	* @brief qed_int_cau_conf - configure cau for a given status
330	* block
331	*
332	* @param p_hwfn
333	* @param ptt
334	* @param sb_phys
335	* @param igu_sb_id
336	* @param vf_number
337	* @param vf_valid
338	*/
339	void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn,
340	struct qed_ptt *p_ptt,
341	dma_addr_t sb_phys,
342	u16 igu_sb_id,
343	u16 vf_number,
344	u8 vf_valid);
345
346	/**
347	* @brief qed_int_alloc
348	*
349	* @param p_hwfn
350	* @param p_ptt
351	*
352	* @return int
353	*/
354	int qed_int_alloc(struct qed_hwfn *p_hwfn,
355	struct qed_ptt *p_ptt);
356
357	/**
358	* @brief qed_int_free
359	*
360	* @param p_hwfn
361	*/
362	void qed_int_free(struct qed_hwfn *p_hwfn);
363
364	/**
365	* @brief qed_int_setup
366	*
367	* @param p_hwfn
368	* @param p_ptt
369	*/
370	void qed_int_setup(struct qed_hwfn *p_hwfn,
371	struct qed_ptt *p_ptt);
372
1408cc1f YM	373	/**
	374	* @brief - Returns an Rx queue index appropriate for usage with given SB.
	375	*
	376	* @param p_hwfn
	377	* @param sb_id - absolute index of SB
	378	*
	379	* @return index of Rx queue
	380	*/
	381	u16 qed_int_queue_id_from_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id);
	382
fe56b9e6 YM	383	/**
	384	* @brief - Enable Interrupt & Attention for hw function
	385	*
	386	* @param p_hwfn
	387	* @param p_ptt
	388	* @param int_mode
8f16bc97 SK	389	*
8f16bc97 SK	390	* @return int
fe56b9e6	391	*/
8f16bc97 SK	392	int qed_int_igu_enable(struct qed_hwfn p_hwfn, struct qed_ptt p_ptt,
8f16bc97 SK	393	enum qed_int_mode int_mode);
fe56b9e6 YM	394
	395	/**
	396	* @brief - Initialize CAU status block entry
	397	*
	398	* @param p_hwfn
	399	* @param p_sb_entry
	400	* @param pf_id
	401	* @param vf_number
	402	* @param vf_valid
	403	*/
	404	void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn,
	405	struct cau_sb_entry *p_sb_entry,
	406	u8 pf_id,
	407	u16 vf_number,
	408	u8 vf_valid);
	409
	410	#define QED_MAPPING_MEMORY_SIZE(dev) (NUM_OF_SBS(dev))
	411
	412	#endif