[linux-2.6-block.git] / drivers / net / ethernet / qlogic / qed / qed.h

/* QLogic qed NIC Driver
 * Copyright (c) 2015-2017  QLogic Corporation
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and /or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef _QED_H
#define _QED_H

#include <linux/types.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/mutex.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/workqueue.h>
#include <linux/zlib.h>
#include <linux/hashtable.h>
#include <linux/qed/qed_if.h>
#include "qed_debug.h"
#include "qed_hsi.h"

extern const struct qed_common_ops qed_common_ops_pass;
#define DRV_MODULE_VERSION "8.10.10.20"

#define MAX_HWFNS_PER_DEVICE    (4)
#define NAME_SIZE 16
#define VER_SIZE 16

#define QED_WFQ_UNIT	100

#define ISCSI_BDQ_ID(_port_id) (_port_id)
#define FCOE_BDQ_ID(_port_id) ((_port_id) + 2)
#define QED_WID_SIZE            (1024)
#define QED_PF_DEMS_SIZE        (4)

/* cau states */
enum qed_coalescing_mode {
	QED_COAL_MODE_DISABLE,
	QED_COAL_MODE_ENABLE
};

struct qed_eth_cb_ops;
struct qed_dev_info;
union qed_mcp_protocol_stats;
enum qed_mcp_protocol_type;

/* helpers */
static inline u32 qed_db_addr(u32 cid, u32 DEMS)
{
	u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
		      (cid * QED_PF_DEMS_SIZE);

	return db_addr;
}

static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS)
{
	u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
		      FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);

	return db_addr;
}

#define ALIGNED_TYPE_SIZE(type_name, p_hwfn)				     \
	((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
	 ~((1 << (p_hwfn->cdev->cache_shift)) - 1))

#define for_each_hwfn(cdev, i)  for (i = 0; i < cdev->num_hwfns; i++)

#define D_TRINE(val, cond1, cond2, true1, true2, def) \
	(val == (cond1) ? true1 :		      \
	 (val == (cond2) ? true2 : def))

/* forward */
struct qed_ptt_pool;
struct qed_spq;
struct qed_sb_info;
struct qed_sb_attn_info;
struct qed_cxt_mngr;
struct qed_sb_sp_info;
struct qed_ll2_info;
struct qed_mcp_info;

struct qed_rt_data {
	u32	*init_val;
	bool	*b_valid;
};

enum qed_tunn_mode {
	QED_MODE_L2GENEVE_TUNN,
	QED_MODE_IPGENEVE_TUNN,
	QED_MODE_L2GRE_TUNN,
	QED_MODE_IPGRE_TUNN,
	QED_MODE_VXLAN_TUNN,
};

enum qed_tunn_clss {
	QED_TUNN_CLSS_MAC_VLAN,
	QED_TUNN_CLSS_MAC_VNI,
	QED_TUNN_CLSS_INNER_MAC_VLAN,
	QED_TUNN_CLSS_INNER_MAC_VNI,
	MAX_QED_TUNN_CLSS,
};

struct qed_tunn_start_params {
	unsigned long	tunn_mode;
	u16		vxlan_udp_port;
	u16		geneve_udp_port;
	u8		update_vxlan_udp_port;
	u8		update_geneve_udp_port;
	u8		tunn_clss_vxlan;
	u8		tunn_clss_l2geneve;
	u8		tunn_clss_ipgeneve;
	u8		tunn_clss_l2gre;
	u8		tunn_clss_ipgre;
};

struct qed_tunn_update_params {
	unsigned long	tunn_mode_update_mask;
	unsigned long	tunn_mode;
	u16		vxlan_udp_port;
	u16		geneve_udp_port;
	u8		update_rx_pf_clss;
	u8		update_tx_pf_clss;
	u8		update_vxlan_udp_port;
	u8		update_geneve_udp_port;
	u8		tunn_clss_vxlan;
	u8		tunn_clss_l2geneve;
	u8		tunn_clss_ipgeneve;
	u8		tunn_clss_l2gre;
	u8		tunn_clss_ipgre;
};

/* The PCI personality is not quite synonymous to protocol ID:
 * 1. All personalities need CORE connections
 * 2. The Ethernet personality may support also the RoCE protocol
 */
enum qed_pci_personality {
	QED_PCI_ETH,
	QED_PCI_FCOE,
	QED_PCI_ISCSI,
	QED_PCI_ETH_ROCE,
	QED_PCI_DEFAULT /* default in shmem */
};

/* All VFs are symmetric, all counters are PF + all VFs */
struct qed_qm_iids {
	u32 cids;
	u32 vf_cids;
	u32 tids;
};

/* HW / FW resources, output of features supported below, most information
 * is received from MFW.
 */
enum qed_resources {
	QED_SB,
	QED_L2_QUEUE,
	QED_VPORT,
	QED_RSS_ENG,
	QED_PQ,
	QED_RL,
	QED_MAC,
	QED_VLAN,
	QED_RDMA_CNQ_RAM,
	QED_ILT,
	QED_LL2_QUEUE,
	QED_CMDQS_CQS,
	QED_RDMA_STATS_QUEUE,
	QED_MAX_RESC,
};

enum QED_FEATURE {
	QED_PF_L2_QUE,
	QED_VF,
	QED_RDMA_CNQ,
	QED_VF_L2_QUE,
	QED_FCOE_CQ,
	QED_MAX_FEATURES,
};

enum QED_PORT_MODE {
	QED_PORT_MODE_DE_2X40G,
	QED_PORT_MODE_DE_2X50G,
	QED_PORT_MODE_DE_1X100G,
	QED_PORT_MODE_DE_4X10G_F,
	QED_PORT_MODE_DE_4X10G_E,
	QED_PORT_MODE_DE_4X20G,
	QED_PORT_MODE_DE_1X40G,
	QED_PORT_MODE_DE_2X25G,
	QED_PORT_MODE_DE_1X25G
};

enum qed_dev_cap {
	QED_DEV_CAP_ETH,
	QED_DEV_CAP_FCOE,
	QED_DEV_CAP_ISCSI,
	QED_DEV_CAP_ROCE,
};

enum qed_wol_support {
	QED_WOL_SUPPORT_NONE,
	QED_WOL_SUPPORT_PME,
};

struct qed_hw_info {
	/* PCI personality */
	enum qed_pci_personality	personality;

	/* Resource Allocation scheme results */
	u32				resc_start[QED_MAX_RESC];
	u32				resc_num[QED_MAX_RESC];
	u32				feat_num[QED_MAX_FEATURES];

#define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
#define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
#define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
				 RESC_NUM(_p_hwfn, resc))
#define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])

	u8				num_tc;
	u8				offload_tc;
	u8				non_offload_tc;

	u32				concrete_fid;
	u16				opaque_fid;
	u16				ovlan;
	u32				part_num[4];

	unsigned char			hw_mac_addr[ETH_ALEN];
	u64				node_wwn;
	u64				port_wwn;

	u16				num_fcoe_conns;

	struct qed_igu_info		*p_igu_info;

	u32				port_mode;
	u32				hw_mode;
	unsigned long		device_capabilities;
	u16				mtu;

	enum qed_wol_support b_wol_support;
};

/* maximun size of read/write commands (HW limit) */
#define DMAE_MAX_RW_SIZE        0x2000

struct qed_dmae_info {
	/* Mutex for synchronizing access to functions */
	struct mutex	mutex;

	u8		channel;

	dma_addr_t	completion_word_phys_addr;

	/* The memory location where the DMAE writes the completion
	 * value when an operation is finished on this context.
	 */
	u32		*p_completion_word;

	dma_addr_t	intermediate_buffer_phys_addr;

	/* An intermediate buffer for DMAE operations that use virtual
	 * addresses - data is DMA'd to/from this buffer and then
	 * memcpy'd to/from the virtual address
	 */
	u32		*p_intermediate_buffer;

	dma_addr_t	dmae_cmd_phys_addr;
	struct dmae_cmd *p_dmae_cmd;
};

struct qed_wfq_data {
	/* when feature is configured for at least 1 vport */
	u32	min_speed;
	bool	configured;
};

struct qed_qm_info {
	struct init_qm_pq_params	*qm_pq_params;
	struct init_qm_vport_params	*qm_vport_params;
	struct init_qm_port_params	*qm_port_params;
	u16				start_pq;
	u8				start_vport;
	u8				pure_lb_pq;
	u8				offload_pq;
	u8				pure_ack_pq;
	u8 ooo_pq;
	u8				vf_queues_offset;
	u16				num_pqs;
	u16				num_vf_pqs;
	u8				num_vports;
	u8				max_phys_tcs_per_port;
	bool				pf_rl_en;
	bool				pf_wfq_en;
	bool				vport_rl_en;
	bool				vport_wfq_en;
	u8				pf_wfq;
	u32				pf_rl;
	struct qed_wfq_data		*wfq_data;
	u8 num_pf_rls;
};

struct storm_stats {
	u32     address;
	u32     len;
};

struct qed_storm_stats {
	struct storm_stats mstats;
	struct storm_stats pstats;
	struct storm_stats tstats;
	struct storm_stats ustats;
};

struct qed_fw_data {
	struct fw_ver_info	*fw_ver_info;
	const u8		*modes_tree_buf;
	union init_op		*init_ops;
	const u32		*arr_data;
	u32			init_ops_size;
};

struct qed_simd_fp_handler {
	void	*token;
	void	(*func)(void *);
};

struct qed_hwfn {
	struct qed_dev			*cdev;
	u8				my_id;          /* ID inside the PF */
#define IS_LEAD_HWFN(edev)              (!((edev)->my_id))
	u8				rel_pf_id;      /* Relative to engine*/
	u8				abs_pf_id;
#define QED_PATH_ID(_p_hwfn)		((_p_hwfn)->abs_pf_id & 1)
	u8				port_id;
	bool				b_active;

	u32				dp_module;
	u8				dp_level;
	char				name[NAME_SIZE];

	bool				first_on_engine;
	bool				hw_init_done;

	u8				num_funcs_on_engine;
	u8 enabled_func_idx;

	/* BAR access */
	void __iomem			*regview;
	void __iomem			*doorbells;
	u64				db_phys_addr;
	unsigned long			db_size;

	/* PTT pool */
	struct qed_ptt_pool		*p_ptt_pool;

	/* HW info */
	struct qed_hw_info		hw_info;

	/* rt_array (for init-tool) */
	struct qed_rt_data		rt_data;

	/* SPQ */
	struct qed_spq			*p_spq;

	/* EQ */
	struct qed_eq			*p_eq;

	/* Consolidate Q*/
	struct qed_consq		*p_consq;

	/* Slow-Path definitions */
	struct tasklet_struct		*sp_dpc;
	bool				b_sp_dpc_enabled;

	struct qed_ptt			*p_main_ptt;
	struct qed_ptt			*p_dpc_ptt;

	struct qed_sb_sp_info		*p_sp_sb;
	struct qed_sb_attn_info		*p_sb_attn;

	/* Protocol related */
	bool				using_ll2;
	struct qed_ll2_info		*p_ll2_info;
	struct qed_ooo_info		*p_ooo_info;
	struct qed_rdma_info		*p_rdma_info;
	struct qed_iscsi_info		*p_iscsi_info;
	struct qed_fcoe_info		*p_fcoe_info;
	struct qed_pf_params		pf_params;

	bool b_rdma_enabled_in_prs;
	u32 rdma_prs_search_reg;

	/* Array of sb_info of all status blocks */
	struct qed_sb_info		*sbs_info[MAX_SB_PER_PF_MIMD];
	u16				num_sbs;

	struct qed_cxt_mngr		*p_cxt_mngr;

	/* Flag indicating whether interrupts are enabled or not*/
	bool				b_int_enabled;
	bool				b_int_requested;

	/* True if the driver requests for the link */
	bool				b_drv_link_init;

	struct qed_vf_iov		*vf_iov_info;
	struct qed_pf_iov		*pf_iov_info;
	struct qed_mcp_info		*mcp_info;

	struct qed_dcbx_info		*p_dcbx_info;

	struct qed_dmae_info		dmae_info;

	/* QM init */
	struct qed_qm_info		qm_info;
	struct qed_storm_stats		storm_stats;

	/* Buffer for unzipping firmware data */
	void				*unzip_buf;

	struct dbg_tools_data		dbg_info;

	/* PWM region specific data */
	u32				dpi_size;
	u32				dpi_count;

	/* This is used to calculate the doorbell address */
	u32 dpi_start_offset;

	/* If one of the following is set then EDPM shouldn't be used */
	u8 dcbx_no_edpm;
	u8 db_bar_no_edpm;

	/* p_ptp_ptt is valid for leading HWFN only */
	struct qed_ptt *p_ptp_ptt;
	struct qed_simd_fp_handler	simd_proto_handler[64];

#ifdef CONFIG_QED_SRIOV
	struct workqueue_struct *iov_wq;
	struct delayed_work iov_task;
	unsigned long iov_task_flags;
#endif

	struct z_stream_s		*stream;
	struct qed_roce_ll2_info	*ll2;
};

struct pci_params {
	int		pm_cap;

	unsigned long	mem_start;
	unsigned long	mem_end;
	unsigned int	irq;
	u8		pf_num;
};

struct qed_int_param {
	u32	int_mode;
	u8	num_vectors;
	u8	min_msix_cnt; /* for minimal functionality */
};

struct qed_int_params {
	struct qed_int_param	in;
	struct qed_int_param	out;
	struct msix_entry	*msix_table;
	bool			fp_initialized;
	u8			fp_msix_base;
	u8			fp_msix_cnt;
	u8			rdma_msix_base;
	u8			rdma_msix_cnt;
};

struct qed_dbg_feature {
	struct dentry *dentry;
	u8 *dump_buf;
	u32 buf_size;
	u32 dumped_dwords;
};

struct qed_dbg_params {
	struct qed_dbg_feature features[DBG_FEATURE_NUM];
	u8 engine_for_debug;
	bool print_data;
};

struct qed_dev {
	u32	dp_module;
	u8	dp_level;
	char	name[NAME_SIZE];

	u8	type;
#define QED_DEV_TYPE_BB (0 << 0)
#define QED_DEV_TYPE_AH BIT(0)
/* Translate type/revision combo into the proper conditions */
#define QED_IS_BB(dev)  ((dev)->type == QED_DEV_TYPE_BB)
#define QED_IS_BB_A0(dev)       (QED_IS_BB(dev) && \
				 CHIP_REV_IS_A0(dev))
#define QED_IS_BB_B0(dev)       (QED_IS_BB(dev) && \
				 CHIP_REV_IS_B0(dev))
#define QED_IS_AH(dev)  ((dev)->type == QED_DEV_TYPE_AH)
#define QED_IS_K2(dev)  QED_IS_AH(dev)

#define QED_GET_TYPE(dev)       (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \
				 QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2)

	u16	vendor_id;
	u16	device_id;

	u16	chip_num;
#define CHIP_NUM_MASK                   0xffff
#define CHIP_NUM_SHIFT                  16

	u16	chip_rev;
#define CHIP_REV_MASK                   0xf
#define CHIP_REV_SHIFT                  12
#define CHIP_REV_IS_A0(_cdev)   (!(_cdev)->chip_rev)
#define CHIP_REV_IS_B0(_cdev)   ((_cdev)->chip_rev == 1)

	u16				chip_metal;
#define CHIP_METAL_MASK                 0xff
#define CHIP_METAL_SHIFT                4

	u16				chip_bond_id;
#define CHIP_BOND_ID_MASK               0xf
#define CHIP_BOND_ID_SHIFT              0

	u8				num_engines;
	u8				num_ports_in_engines;
	u8				num_funcs_in_port;

	u8				path_id;
	enum qed_mf_mode		mf_mode;
#define IS_MF_DEFAULT(_p_hwfn)  (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT)
#define IS_MF_SI(_p_hwfn)       (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR)
#define IS_MF_SD(_p_hwfn)       (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN)

	int				pcie_width;
	int				pcie_speed;
	u8				ver_str[VER_SIZE];

	/* Add MF related configuration */
	u8				mcp_rev;
	u8				boot_mode;

	/* WoL related configurations */
	u8 wol_config;
	u8 wol_mac[ETH_ALEN];

	u32				int_mode;
	enum qed_coalescing_mode	int_coalescing_mode;
	u16				rx_coalesce_usecs;
	u16				tx_coalesce_usecs;

	/* Start Bar offset of first hwfn */
	void __iomem			*regview;
	void __iomem			*doorbells;
	u64				db_phys_addr;
	unsigned long			db_size;

	/* PCI */
	u8				cache_shift;

	/* Init */
	const struct iro		*iro_arr;
#define IRO (p_hwfn->cdev->iro_arr)

	/* HW functions */
	u8				num_hwfns;
	struct qed_hwfn			hwfns[MAX_HWFNS_PER_DEVICE];

	/* SRIOV */
	struct qed_hw_sriov_info *p_iov_info;
#define IS_QED_SRIOV(cdev)              (!!(cdev)->p_iov_info)

	unsigned long			tunn_mode;

	bool				b_is_vf;
	u32				drv_type;
	struct qed_eth_stats		*reset_stats;
	struct qed_fw_data		*fw_data;

	u32				mcp_nvm_resp;

	/* Linux specific here */
	struct  qede_dev		*edev;
	struct  pci_dev			*pdev;
	u32 flags;
#define QED_FLAG_STORAGE_STARTED	(BIT(0))
	int				msg_enable;

	struct pci_params		pci_params;

	struct qed_int_params		int_params;

	u8				protocol;
#define IS_QED_ETH_IF(cdev)     ((cdev)->protocol == QED_PROTOCOL_ETH)
#define IS_QED_FCOE_IF(cdev)    ((cdev)->protocol == QED_PROTOCOL_FCOE)

	/* Callbacks to protocol driver */
	union {
		struct qed_common_cb_ops	*common;
		struct qed_eth_cb_ops		*eth;
		struct qed_fcoe_cb_ops		*fcoe;
		struct qed_iscsi_cb_ops		*iscsi;
	} protocol_ops;
	void				*ops_cookie;

	struct qed_dbg_params		dbg_params;

#ifdef CONFIG_QED_LL2
	struct qed_cb_ll2_info		*ll2;
	u8				ll2_mac_address[ETH_ALEN];
#endif
	DECLARE_HASHTABLE(connections, 10);
	const struct firmware		*firmware;

	u32 rdma_max_sge;
	u32 rdma_max_inline;
	u32 rdma_max_srq_sge;
};

#define NUM_OF_VFS(dev)         MAX_NUM_VFS_BB
#define NUM_OF_L2_QUEUES(dev)	MAX_NUM_L2_QUEUES_BB
#define NUM_OF_SBS(dev)         MAX_SB_PER_PATH_BB
#define NUM_OF_ENG_PFS(dev)     MAX_NUM_PFS_BB

/**
 * @brief qed_concrete_to_sw_fid - get the sw function id from
 *        the concrete value.
 *
 * @param concrete_fid
 *
 * @return inline u8
 */
static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
					u32 concrete_fid)
{
	u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
	u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
	u8 vf_valid = GET_FIELD(concrete_fid,
				PXP_CONCRETE_FID_VFVALID);
	u8 sw_fid;

	if (vf_valid)
		sw_fid = vfid + MAX_NUM_PFS;
	else
		sw_fid = pfid;

	return sw_fid;
}

#define PURE_LB_TC 8
#define OOO_LB_TC 9

int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate);
void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate);

void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
#define QED_LEADING_HWFN(dev)   (&dev->hwfns[0])

/* Other Linux specific common definitions */
#define DP_NAME(cdev) ((cdev)->name)

#define REG_ADDR(cdev, offset)          (void __iomem *)((u8 __iomem *)\
						(cdev->regview) + \
							 (offset))

#define REG_RD(cdev, offset)            readl(REG_ADDR(cdev, offset))
#define REG_WR(cdev, offset, val)       writel((u32)val, REG_ADDR(cdev, offset))
#define REG_WR16(cdev, offset, val)     writew((u16)val, REG_ADDR(cdev, offset))

#define DOORBELL(cdev, db_addr, val)			 \
	writel((u32)val, (void __iomem *)((u8 __iomem *)\
					  (cdev->doorbells) + (db_addr)))

/* Prototypes */
int qed_fill_dev_info(struct qed_dev *cdev,
		      struct qed_dev_info *dev_info);
void qed_link_update(struct qed_hwfn *hwfn);
u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
		   u32 input_len, u8 *input_buf,
		   u32 max_size, u8 *unzip_buf);
void qed_get_protocol_stats(struct qed_dev *cdev,
			    enum qed_mcp_protocol_type type,
			    union qed_mcp_protocol_stats *stats);
int qed_slowpath_irq_req(struct qed_hwfn *hwfn);

#endif /* _QED_H */
Commit	Line	Data
fe56b9e6	1	/* QLogic qed NIC Driver
e8f1cb50	2	* Copyright (c) 2015-2017 QLogic Corporation
fe56b9e6	3	*
e8f1cb50 MY	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and /or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
fe56b9e6 YM	31	*/
	32
	33	#ifndef _QED_H
	34	#define _QED_H
	35
	36	#include <linux/types.h>
	37	#include <linux/io.h>
	38	#include <linux/delay.h>
	39	#include <linux/firmware.h>
	40	#include <linux/interrupt.h>
	41	#include <linux/list.h>
	42	#include <linux/mutex.h>
	43	#include <linux/pci.h>
	44	#include <linux/slab.h>
	45	#include <linux/string.h>
	46	#include <linux/workqueue.h>
	47	#include <linux/zlib.h>
	48	#include <linux/hashtable.h>
	49	#include <linux/qed/qed_if.h>
c965db44	50	#include "qed_debug.h"
fe56b9e6 YM	51	#include "qed_hsi.h"
fe56b9e6 YM	52
25c089d7	53	extern const struct qed_common_ops qed_common_ops_pass;
ce742922	54	#define DRV_MODULE_VERSION "8.10.10.20"
fe56b9e6 YM	55
	56	#define MAX_HWFNS_PER_DEVICE (4)
	57	#define NAME_SIZE 16
	58	#define VER_SIZE 16
	59
bcd197c8 MC	60	#define QED_WFQ_UNIT 100
bcd197c8 MC	61
fc831825	62	#define ISCSI_BDQ_ID(_port_id) (_port_id)
1e128c81	63	#define FCOE_BDQ_ID(_port_id) ((_port_id) + 2)
51ff1725 RA	64	#define QED_WID_SIZE (1024)
	65	#define QED_PF_DEMS_SIZE (4)
	66
fe56b9e6 YM	67	/* cau states */
	68	enum qed_coalescing_mode {
	69	QED_COAL_MODE_DISABLE,
	70	QED_COAL_MODE_ENABLE
	71	};
	72
	73	struct qed_eth_cb_ops;
	74	struct qed_dev_info;
6c754246 SRK	75	union qed_mcp_protocol_stats;
6c754246 SRK	76	enum qed_mcp_protocol_type;
fe56b9e6 YM	77
	78	/* helpers */
	79	static inline u32 qed_db_addr(u32 cid, u32 DEMS)
51ff1725 RA	80	{
	81	u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) \|
	82	(cid * QED_PF_DEMS_SIZE);
	83
	84	return db_addr;
	85	}
	86
	87	static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS)
fe56b9e6 YM	88	{
	89	u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) \|
	90	FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
	91
	92	return db_addr;
	93	}
	94
	95	#define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
	96	((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
	97	~((1 << (p_hwfn->cdev->cache_shift)) - 1))
	98
	99	#define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++)
	100
	101	#define D_TRINE(val, cond1, cond2, true1, true2, def) \
	102	(val == (cond1) ? true1 : \
	103	(val == (cond2) ? true2 : def))
	104
	105	/* forward */
	106	struct qed_ptt_pool;
	107	struct qed_spq;
	108	struct qed_sb_info;
	109	struct qed_sb_attn_info;
	110	struct qed_cxt_mngr;
	111	struct qed_sb_sp_info;
0a7fb11c	112	struct qed_ll2_info;
fe56b9e6 YM	113	struct qed_mcp_info;
	114
	115	struct qed_rt_data {
fc48b7a6 YM	116	u32 *init_val;
fc48b7a6 YM	117	bool *b_valid;
fe56b9e6 YM	118	};
fe56b9e6 YM	119
464f6645 MC	120	enum qed_tunn_mode {
	121	QED_MODE_L2GENEVE_TUNN,
	122	QED_MODE_IPGENEVE_TUNN,
	123	QED_MODE_L2GRE_TUNN,
	124	QED_MODE_IPGRE_TUNN,
	125	QED_MODE_VXLAN_TUNN,
	126	};
	127
	128	enum qed_tunn_clss {
	129	QED_TUNN_CLSS_MAC_VLAN,
	130	QED_TUNN_CLSS_MAC_VNI,
	131	QED_TUNN_CLSS_INNER_MAC_VLAN,
	132	QED_TUNN_CLSS_INNER_MAC_VNI,
	133	MAX_QED_TUNN_CLSS,
	134	};
	135
	136	struct qed_tunn_start_params {
	137	unsigned long tunn_mode;
	138	u16 vxlan_udp_port;
	139	u16 geneve_udp_port;
	140	u8 update_vxlan_udp_port;
	141	u8 update_geneve_udp_port;
	142	u8 tunn_clss_vxlan;
	143	u8 tunn_clss_l2geneve;
	144	u8 tunn_clss_ipgeneve;
	145	u8 tunn_clss_l2gre;
	146	u8 tunn_clss_ipgre;
	147	};
	148
	149	struct qed_tunn_update_params {
	150	unsigned long tunn_mode_update_mask;
	151	unsigned long tunn_mode;
	152	u16 vxlan_udp_port;
	153	u16 geneve_udp_port;
	154	u8 update_rx_pf_clss;
	155	u8 update_tx_pf_clss;
	156	u8 update_vxlan_udp_port;
	157	u8 update_geneve_udp_port;
	158	u8 tunn_clss_vxlan;
	159	u8 tunn_clss_l2geneve;
	160	u8 tunn_clss_ipgeneve;
	161	u8 tunn_clss_l2gre;
	162	u8 tunn_clss_ipgre;
	163	};
	164
fe56b9e6 YM	165	/* The PCI personality is not quite synonymous to protocol ID:
	166	* 1. All personalities need CORE connections
	167	* 2. The Ethernet personality may support also the RoCE protocol
	168	*/
	169	enum qed_pci_personality {
	170	QED_PCI_ETH,
1e128c81	171	QED_PCI_FCOE,
c5ac9319 YM	172	QED_PCI_ISCSI,
c5ac9319 YM	173	QED_PCI_ETH_ROCE,
fe56b9e6 YM	174	QED_PCI_DEFAULT /* default in shmem */
	175	};
	176
	177	/* All VFs are symmetric, all counters are PF + all VFs */
	178	struct qed_qm_iids {
	179	u32 cids;
	180	u32 vf_cids;
	181	u32 tids;
	182	};
	183
2edbff8d TT	184	/* HW / FW resources, output of features supported below, most information
	185	* is received from MFW.
	186	*/
	187	enum qed_resources {
fe56b9e6	188	QED_SB,
25c089d7	189	QED_L2_QUEUE,
fe56b9e6	190	QED_VPORT,
25c089d7	191	QED_RSS_ENG,
fe56b9e6 YM	192	QED_PQ,
fe56b9e6 YM	193	QED_RL,
25c089d7 YM	194	QED_MAC,
25c089d7 YM	195	QED_VLAN,
51ff1725	196	QED_RDMA_CNQ_RAM,
fe56b9e6	197	QED_ILT,
0a7fb11c	198	QED_LL2_QUEUE,
2edbff8d	199	QED_CMDQS_CQS,
51ff1725	200	QED_RDMA_STATS_QUEUE,
fe56b9e6 YM	201	QED_MAX_RESC,
	202	};
	203
25c089d7 YM	204	enum QED_FEATURE {
25c089d7 YM	205	QED_PF_L2_QUE,
32a47e72	206	QED_VF,
51ff1725	207	QED_RDMA_CNQ,
5a1f965a	208	QED_VF_L2_QUE,
1e128c81	209	QED_FCOE_CQ,
25c089d7 YM	210	QED_MAX_FEATURES,
	211	};
	212
cc875c2e YM	213	enum QED_PORT_MODE {
	214	QED_PORT_MODE_DE_2X40G,
	215	QED_PORT_MODE_DE_2X50G,
	216	QED_PORT_MODE_DE_1X100G,
	217	QED_PORT_MODE_DE_4X10G_F,
	218	QED_PORT_MODE_DE_4X10G_E,
	219	QED_PORT_MODE_DE_4X20G,
	220	QED_PORT_MODE_DE_1X40G,
	221	QED_PORT_MODE_DE_2X25G,
	222	QED_PORT_MODE_DE_1X25G
	223	};
	224
fc48b7a6 YM	225	enum qed_dev_cap {
fc48b7a6 YM	226	QED_DEV_CAP_ETH,
1e128c81	227	QED_DEV_CAP_FCOE,
c5ac9319 YM	228	QED_DEV_CAP_ISCSI,
c5ac9319 YM	229	QED_DEV_CAP_ROCE,
fc48b7a6 YM	230	};
fc48b7a6 YM	231
14d39648 MY	232	enum qed_wol_support {
	233	QED_WOL_SUPPORT_NONE,
	234	QED_WOL_SUPPORT_PME,
	235	};
	236
fe56b9e6 YM	237	struct qed_hw_info {
	238	/* PCI personality */
	239	enum qed_pci_personality personality;
	240
	241	/* Resource Allocation scheme results */
	242	u32 resc_start[QED_MAX_RESC];
	243	u32 resc_num[QED_MAX_RESC];
25c089d7	244	u32 feat_num[QED_MAX_FEATURES];
fe56b9e6 YM	245
	246	#define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
	247	#define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
dbb799c3 YM	248	#define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
dbb799c3 YM	249	RESC_NUM(_p_hwfn, resc))
fe56b9e6 YM	250	#define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
	251
	252	u8 num_tc;
	253	u8 offload_tc;
	254	u8 non_offload_tc;
	255
	256	u32 concrete_fid;
	257	u16 opaque_fid;
	258	u16 ovlan;
	259	u32 part_num[4];
	260
fe56b9e6	261	unsigned char hw_mac_addr[ETH_ALEN];
1e128c81 AE	262	u64 node_wwn;
	263	u64 port_wwn;
	264
	265	u16 num_fcoe_conns;
fe56b9e6 YM	266
	267	struct qed_igu_info *p_igu_info;
	268
	269	u32 port_mode;
	270	u32 hw_mode;
fc48b7a6	271	unsigned long device_capabilities;
0fefbfba	272	u16 mtu;
14d39648 MY	273
14d39648 MY	274	enum qed_wol_support b_wol_support;
fe56b9e6 YM	275	};
fe56b9e6 YM	276
fe56b9e6 YM	277	/* maximun size of read/write commands (HW limit) */
	278	#define DMAE_MAX_RW_SIZE 0x2000
	279
	280	struct qed_dmae_info {
	281	/* Mutex for synchronizing access to functions */
	282	struct mutex mutex;
	283
	284	u8 channel;
	285
	286	dma_addr_t completion_word_phys_addr;
	287
	288	/* The memory location where the DMAE writes the completion
	289	* value when an operation is finished on this context.
	290	*/
	291	u32 *p_completion_word;
	292
	293	dma_addr_t intermediate_buffer_phys_addr;
	294
	295	/* An intermediate buffer for DMAE operations that use virtual
	296	* addresses - data is DMA'd to/from this buffer and then
	297	* memcpy'd to/from the virtual address
	298	*/
	299	u32 *p_intermediate_buffer;
	300
	301	dma_addr_t dmae_cmd_phys_addr;
	302	struct dmae_cmd *p_dmae_cmd;
	303	};
	304
bcd197c8 MC	305	struct qed_wfq_data {
	306	/* when feature is configured for at least 1 vport */
	307	u32 min_speed;
	308	bool configured;
	309	};
	310
fe56b9e6 YM	311	struct qed_qm_info {
	312	struct init_qm_pq_params *qm_pq_params;
	313	struct init_qm_vport_params *qm_vport_params;
	314	struct init_qm_port_params *qm_port_params;
	315	u16 start_pq;
	316	u8 start_vport;
	317	u8 pure_lb_pq;
	318	u8 offload_pq;
	319	u8 pure_ack_pq;
dbb799c3	320	u8 ooo_pq;
fe56b9e6 YM	321	u8 vf_queues_offset;
	322	u16 num_pqs;
	323	u16 num_vf_pqs;
	324	u8 num_vports;
	325	u8 max_phys_tcs_per_port;
	326	bool pf_rl_en;
	327	bool pf_wfq_en;
	328	bool vport_rl_en;
	329	bool vport_wfq_en;
	330	u8 pf_wfq;
	331	u32 pf_rl;
bcd197c8	332	struct qed_wfq_data *wfq_data;
dbb799c3	333	u8 num_pf_rls;
fe56b9e6 YM	334	};
fe56b9e6 YM	335
9df2ed04 MC	336	struct storm_stats {
	337	u32 address;
	338	u32 len;
	339	};
	340
	341	struct qed_storm_stats {
	342	struct storm_stats mstats;
	343	struct storm_stats pstats;
	344	struct storm_stats tstats;
	345	struct storm_stats ustats;
	346	};
	347
fe56b9e6	348	struct qed_fw_data {
9df2ed04	349	struct fw_ver_info *fw_ver_info;
fe56b9e6 YM	350	const u8 *modes_tree_buf;
	351	union init_op *init_ops;
	352	const u32 *arr_data;
	353	u32 init_ops_size;
	354	};
	355
	356	struct qed_simd_fp_handler {
	357	void *token;
	358	void (func)(void );
	359	};
	360
	361	struct qed_hwfn {
	362	struct qed_dev *cdev;
	363	u8 my_id; /* ID inside the PF */
	364	#define IS_LEAD_HWFN(edev) (!((edev)->my_id))
	365	u8 rel_pf_id; /* Relative to engine*/
	366	u8 abs_pf_id;
	367	#define QED_PATH_ID(_p_hwfn) ((_p_hwfn)->abs_pf_id & 1)
	368	u8 port_id;
	369	bool b_active;
	370
	371	u32 dp_module;
	372	u8 dp_level;
	373	char name[NAME_SIZE];
	374
	375	bool first_on_engine;
	376	bool hw_init_done;
	377
1408cc1f	378	u8 num_funcs_on_engine;
dbb799c3	379	u8 enabled_func_idx;
1408cc1f	380
fe56b9e6 YM	381	/* BAR access */
	382	void __iomem *regview;
	383	void __iomem *doorbells;
	384	u64 db_phys_addr;
	385	unsigned long db_size;
	386
	387	/* PTT pool */
	388	struct qed_ptt_pool *p_ptt_pool;
	389
	390	/* HW info */
	391	struct qed_hw_info hw_info;
	392
	393	/* rt_array (for init-tool) */
fc48b7a6	394	struct qed_rt_data rt_data;
fe56b9e6 YM	395
	396	/* SPQ */
	397	struct qed_spq *p_spq;
	398
	399	/* EQ */
	400	struct qed_eq *p_eq;
	401
	402	/* Consolidate Q*/
	403	struct qed_consq *p_consq;
	404
	405	/* Slow-Path definitions */
	406	struct tasklet_struct *sp_dpc;
	407	bool b_sp_dpc_enabled;
	408
	409	struct qed_ptt *p_main_ptt;
	410	struct qed_ptt *p_dpc_ptt;
	411
	412	struct qed_sb_sp_info *p_sp_sb;
	413	struct qed_sb_attn_info *p_sb_attn;
	414
	415	/* Protocol related */
0a7fb11c YM	416	bool using_ll2;
0a7fb11c YM	417	struct qed_ll2_info *p_ll2_info;
1d6cff4f	418	struct qed_ooo_info *p_ooo_info;
51ff1725	419	struct qed_rdma_info *p_rdma_info;
fc831825	420	struct qed_iscsi_info *p_iscsi_info;
1e128c81	421	struct qed_fcoe_info *p_fcoe_info;
fe56b9e6 YM	422	struct qed_pf_params pf_params;
fe56b9e6 YM	423
dbb799c3 YM	424	bool b_rdma_enabled_in_prs;
	425	u32 rdma_prs_search_reg;
	426
fe56b9e6 YM	427	/* Array of sb_info of all status blocks */
	428	struct qed_sb_info *sbs_info[MAX_SB_PER_PF_MIMD];
	429	u16 num_sbs;
	430
	431	struct qed_cxt_mngr *p_cxt_mngr;
	432
	433	/* Flag indicating whether interrupts are enabled or not*/
	434	bool b_int_enabled;
8f16bc97	435	bool b_int_requested;
fe56b9e6	436
fc916ff2 SRK	437	/* True if the driver requests for the link */
	438	bool b_drv_link_init;
	439
1408cc1f	440	struct qed_vf_iov *vf_iov_info;
32a47e72	441	struct qed_pf_iov *pf_iov_info;
fe56b9e6 YM	442	struct qed_mcp_info *mcp_info;
fe56b9e6 YM	443
39651abd SRK	444	struct qed_dcbx_info *p_dcbx_info;
39651abd SRK	445
fe56b9e6 YM	446	struct qed_dmae_info dmae_info;
	447
	448	/* QM init */
	449	struct qed_qm_info qm_info;
9df2ed04	450	struct qed_storm_stats storm_stats;
fe56b9e6 YM	451
	452	/* Buffer for unzipping firmware data */
	453	void *unzip_buf;
	454
c965db44 TT	455	struct dbg_tools_data dbg_info;
c965db44 TT	456
51ff1725 RA	457	/* PWM region specific data */
	458	u32 dpi_size;
	459	u32 dpi_count;
	460
	461	/* This is used to calculate the doorbell address */
	462	u32 dpi_start_offset;
	463
	464	/* If one of the following is set then EDPM shouldn't be used */
	465	u8 dcbx_no_edpm;
	466	u8 db_bar_no_edpm;
	467
c78c70fa SRK	468	/* p_ptp_ptt is valid for leading HWFN only */
c78c70fa SRK	469	struct qed_ptt *p_ptp_ptt;
fe56b9e6 YM	470	struct qed_simd_fp_handler simd_proto_handler[64];
fe56b9e6 YM	471
37bff2b9 YM	472	#ifdef CONFIG_QED_SRIOV
	473	struct workqueue_struct *iov_wq;
	474	struct delayed_work iov_task;
	475	unsigned long iov_task_flags;
	476	#endif
	477
fe56b9e6	478	struct z_stream_s *stream;
abd49676	479	struct qed_roce_ll2_info *ll2;
fe56b9e6 YM	480	};
	481
	482	struct pci_params {
	483	int pm_cap;
	484
	485	unsigned long mem_start;
	486	unsigned long mem_end;
	487	unsigned int irq;
	488	u8 pf_num;
	489	};
	490
	491	struct qed_int_param {
	492	u32 int_mode;
	493	u8 num_vectors;
	494	u8 min_msix_cnt; /* for minimal functionality */
	495	};
	496
	497	struct qed_int_params {
	498	struct qed_int_param in;
	499	struct qed_int_param out;
	500	struct msix_entry *msix_table;
	501	bool fp_initialized;
	502	u8 fp_msix_base;
	503	u8 fp_msix_cnt;
51ff1725 RA	504	u8 rdma_msix_base;
51ff1725 RA	505	u8 rdma_msix_cnt;
fe56b9e6 YM	506	};
fe56b9e6 YM	507
c965db44 TT	508	struct qed_dbg_feature {
	509	struct dentry *dentry;
	510	u8 *dump_buf;
	511	u32 buf_size;
	512	u32 dumped_dwords;
	513	};
	514
	515	struct qed_dbg_params {
	516	struct qed_dbg_feature features[DBG_FEATURE_NUM];
	517	u8 engine_for_debug;
	518	bool print_data;
	519	};
	520
fe56b9e6 YM	521	struct qed_dev {
	522	u32 dp_module;
	523	u8 dp_level;
	524	char name[NAME_SIZE];
	525
	526	u8 type;
fc48b7a6 YM	527	#define QED_DEV_TYPE_BB (0 << 0)
	528	#define QED_DEV_TYPE_AH BIT(0)
	529	/* Translate type/revision combo into the proper conditions */
	530	#define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB)
	531	#define QED_IS_BB_A0(dev) (QED_IS_BB(dev) && \
	532	CHIP_REV_IS_A0(dev))
	533	#define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \
	534	CHIP_REV_IS_B0(dev))
c965db44 TT	535	#define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH)
c965db44 TT	536	#define QED_IS_K2(dev) QED_IS_AH(dev)
fc48b7a6 YM	537
	538	#define QED_GET_TYPE(dev) (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \
	539	QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2)
	540
	541	u16 vendor_id;
	542	u16 device_id;
fe56b9e6 YM	543
	544	u16 chip_num;
	545	#define CHIP_NUM_MASK 0xffff
	546	#define CHIP_NUM_SHIFT 16
	547
	548	u16 chip_rev;
	549	#define CHIP_REV_MASK 0xf
	550	#define CHIP_REV_SHIFT 12
fc48b7a6 YM	551	#define CHIP_REV_IS_A0(_cdev) (!(_cdev)->chip_rev)
fc48b7a6 YM	552	#define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1)
fe56b9e6 YM	553
	554	u16 chip_metal;
	555	#define CHIP_METAL_MASK 0xff
	556	#define CHIP_METAL_SHIFT 4
	557
	558	u16 chip_bond_id;
	559	#define CHIP_BOND_ID_MASK 0xf
	560	#define CHIP_BOND_ID_SHIFT 0
	561
	562	u8 num_engines;
	563	u8 num_ports_in_engines;
	564	u8 num_funcs_in_port;
	565
	566	u8 path_id;
fc48b7a6 YM	567	enum qed_mf_mode mf_mode;
	568	#define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT)
	569	#define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR)
	570	#define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN)
fe56b9e6 YM	571
	572	int pcie_width;
	573	int pcie_speed;
	574	u8 ver_str[VER_SIZE];
	575
	576	/* Add MF related configuration */
	577	u8 mcp_rev;
	578	u8 boot_mode;
	579
14d39648 MY	580	/* WoL related configurations */
	581	u8 wol_config;
	582	u8 wol_mac[ETH_ALEN];
fe56b9e6 YM	583
	584	u32 int_mode;
	585	enum qed_coalescing_mode int_coalescing_mode;
51d99880 SRK	586	u16 rx_coalesce_usecs;
51d99880 SRK	587	u16 tx_coalesce_usecs;
fe56b9e6 YM	588
	589	/* Start Bar offset of first hwfn */
	590	void __iomem *regview;
	591	void __iomem *doorbells;
	592	u64 db_phys_addr;
	593	unsigned long db_size;
	594
	595	/* PCI */
	596	u8 cache_shift;
	597
	598	/* Init */
	599	const struct iro *iro_arr;
	600	#define IRO (p_hwfn->cdev->iro_arr)
	601
	602	/* HW functions */
	603	u8 num_hwfns;
	604	struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
	605
32a47e72 YM	606	/* SRIOV */
	607	struct qed_hw_sriov_info *p_iov_info;
	608	#define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info)
	609
464f6645	610	unsigned long tunn_mode;
1408cc1f YM	611
1408cc1f YM	612	bool b_is_vf;
fe56b9e6	613	u32 drv_type;
fe56b9e6 YM	614	struct qed_eth_stats *reset_stats;
	615	struct qed_fw_data *fw_data;
	616
	617	u32 mcp_nvm_resp;
	618
	619	/* Linux specific here */
	620	struct qede_dev *edev;
	621	struct pci_dev *pdev;
fc831825 YM	622	u32 flags;
fc831825 YM	623	#define QED_FLAG_STORAGE_STARTED (BIT(0))
fe56b9e6 YM	624	int msg_enable;
	625
	626	struct pci_params pci_params;
	627
	628	struct qed_int_params int_params;
	629
	630	u8 protocol;
	631	#define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH)
1e128c81	632	#define IS_QED_FCOE_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_FCOE)
fe56b9e6	633
cc875c2e YM	634	/* Callbacks to protocol driver */
	635	union {
	636	struct qed_common_cb_ops *common;
	637	struct qed_eth_cb_ops *eth;
1e128c81	638	struct qed_fcoe_cb_ops *fcoe;
fc831825	639	struct qed_iscsi_cb_ops *iscsi;
cc875c2e YM	640	} protocol_ops;
	641	void *ops_cookie;
	642
c965db44 TT	643	struct qed_dbg_params dbg_params;
c965db44 TT	644
0a7fb11c YM	645	#ifdef CONFIG_QED_LL2
	646	struct qed_cb_ll2_info *ll2;
	647	u8 ll2_mac_address[ETH_ALEN];
	648	#endif
fc831825	649	DECLARE_HASHTABLE(connections, 10);
fe56b9e6	650	const struct firmware *firmware;
51ff1725 RA	651
	652	u32 rdma_max_sge;
	653	u32 rdma_max_inline;
	654	u32 rdma_max_srq_sge;
fe56b9e6 YM	655	};
fe56b9e6 YM	656
32a47e72	657	#define NUM_OF_VFS(dev) MAX_NUM_VFS_BB
dacd88d6	658	#define NUM_OF_L2_QUEUES(dev) MAX_NUM_L2_QUEUES_BB
fe56b9e6 YM	659	#define NUM_OF_SBS(dev) MAX_SB_PER_PATH_BB
	660	#define NUM_OF_ENG_PFS(dev) MAX_NUM_PFS_BB
	661
	662	/**
	663	* @brief qed_concrete_to_sw_fid - get the sw function id from
	664	* the concrete value.
	665	*
	666	* @param concrete_fid
	667	*
	668	* @return inline u8
	669	*/
	670	static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
	671	u32 concrete_fid)
	672	{
4870e704	673	u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
fe56b9e6	674	u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
4870e704 YM	675	u8 vf_valid = GET_FIELD(concrete_fid,
	676	PXP_CONCRETE_FID_VFVALID);
	677	u8 sw_fid;
fe56b9e6	678
4870e704 YM	679	if (vf_valid)
	680	sw_fid = vfid + MAX_NUM_PFS;
	681	else
	682	sw_fid = pfid;
	683
	684	return sw_fid;
fe56b9e6 YM	685	}
	686
	687	#define PURE_LB_TC 8
dbb799c3	688	#define OOO_LB_TC 9
fe56b9e6	689
733def6a	690	int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate);
bcd197c8 MC	691	void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate);
bcd197c8 MC	692
733def6a	693	void qed_clean_wfq_db(struct qed_hwfn p_hwfn, struct qed_ptt p_ptt);
fe56b9e6 YM	694	#define QED_LEADING_HWFN(dev) (&dev->hwfns[0])
	695
	696	/* Other Linux specific common definitions */
	697	#define DP_NAME(cdev) ((cdev)->name)
	698
	699	#define REG_ADDR(cdev, offset) (void __iomem )((u8 __iomem )\
	700	(cdev->regview) + \
	701	(offset))
	702
	703	#define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset))
	704	#define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset))
	705	#define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset))
	706
	707	#define DOORBELL(cdev, db_addr, val) \
	708	writel((u32)val, (void __iomem )((u8 __iomem )\
	709	(cdev->doorbells) + (db_addr)))
	710
	711	/* Prototypes */
	712	int qed_fill_dev_info(struct qed_dev *cdev,
	713	struct qed_dev_info *dev_info);
cc875c2e	714	void qed_link_update(struct qed_hwfn *hwfn);
fe56b9e6 YM	715	u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
	716	u32 input_len, u8 *input_buf,
	717	u32 max_size, u8 *unzip_buf);
6c754246 SRK	718	void qed_get_protocol_stats(struct qed_dev *cdev,
	719	enum qed_mcp_protocol_type type,
	720	union qed_mcp_protocol_stats *stats);
8f16bc97 SK	721	int qed_slowpath_irq_req(struct qed_hwfn *hwfn);
8f16bc97 SK	722
fe56b9e6	723	#endif /* _QED_H */