Commit | Line | Data |
---|---|---|
fe56b9e6 YM |
1 | /* QLogic qed NIC Driver |
2 | * Copyright (c) 2015 QLogic Corporation | |
3 | * | |
4 | * This software is available under the terms of the GNU General Public License | |
5 | * (GPL) Version 2, available from the file COPYING in the main directory of | |
6 | * this source tree. | |
7 | */ | |
8 | ||
9 | #ifndef _QED_H | |
10 | #define _QED_H | |
11 | ||
12 | #include <linux/types.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/firmware.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/list.h> | |
18 | #include <linux/mutex.h> | |
19 | #include <linux/pci.h> | |
20 | #include <linux/slab.h> | |
21 | #include <linux/string.h> | |
22 | #include <linux/workqueue.h> | |
23 | #include <linux/zlib.h> | |
24 | #include <linux/hashtable.h> | |
25 | #include <linux/qed/qed_if.h> | |
c965db44 | 26 | #include "qed_debug.h" |
fe56b9e6 YM |
27 | #include "qed_hsi.h" |
28 | ||
25c089d7 | 29 | extern const struct qed_common_ops qed_common_ops_pass; |
05fafbfb | 30 | #define DRV_MODULE_VERSION "8.10.9.20" |
fe56b9e6 YM |
31 | |
32 | #define MAX_HWFNS_PER_DEVICE (4) | |
33 | #define NAME_SIZE 16 | |
34 | #define VER_SIZE 16 | |
35 | ||
bcd197c8 MC |
36 | #define QED_WFQ_UNIT 100 |
37 | ||
fc831825 | 38 | #define ISCSI_BDQ_ID(_port_id) (_port_id) |
51ff1725 RA |
39 | #define QED_WID_SIZE (1024) |
40 | #define QED_PF_DEMS_SIZE (4) | |
41 | ||
fe56b9e6 YM |
42 | /* cau states */ |
43 | enum qed_coalescing_mode { | |
44 | QED_COAL_MODE_DISABLE, | |
45 | QED_COAL_MODE_ENABLE | |
46 | }; | |
47 | ||
48 | struct qed_eth_cb_ops; | |
49 | struct qed_dev_info; | |
6c754246 SRK |
50 | union qed_mcp_protocol_stats; |
51 | enum qed_mcp_protocol_type; | |
fe56b9e6 YM |
52 | |
53 | /* helpers */ | |
54 | static inline u32 qed_db_addr(u32 cid, u32 DEMS) | |
51ff1725 RA |
55 | { |
56 | u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | | |
57 | (cid * QED_PF_DEMS_SIZE); | |
58 | ||
59 | return db_addr; | |
60 | } | |
61 | ||
62 | static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS) | |
fe56b9e6 YM |
63 | { |
64 | u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | | |
65 | FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid); | |
66 | ||
67 | return db_addr; | |
68 | } | |
69 | ||
70 | #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \ | |
71 | ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \ | |
72 | ~((1 << (p_hwfn->cdev->cache_shift)) - 1)) | |
73 | ||
74 | #define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++) | |
75 | ||
76 | #define D_TRINE(val, cond1, cond2, true1, true2, def) \ | |
77 | (val == (cond1) ? true1 : \ | |
78 | (val == (cond2) ? true2 : def)) | |
79 | ||
80 | /* forward */ | |
81 | struct qed_ptt_pool; | |
82 | struct qed_spq; | |
83 | struct qed_sb_info; | |
84 | struct qed_sb_attn_info; | |
85 | struct qed_cxt_mngr; | |
86 | struct qed_sb_sp_info; | |
0a7fb11c | 87 | struct qed_ll2_info; |
fe56b9e6 YM |
88 | struct qed_mcp_info; |
89 | ||
90 | struct qed_rt_data { | |
fc48b7a6 YM |
91 | u32 *init_val; |
92 | bool *b_valid; | |
fe56b9e6 YM |
93 | }; |
94 | ||
464f6645 MC |
95 | enum qed_tunn_mode { |
96 | QED_MODE_L2GENEVE_TUNN, | |
97 | QED_MODE_IPGENEVE_TUNN, | |
98 | QED_MODE_L2GRE_TUNN, | |
99 | QED_MODE_IPGRE_TUNN, | |
100 | QED_MODE_VXLAN_TUNN, | |
101 | }; | |
102 | ||
103 | enum qed_tunn_clss { | |
104 | QED_TUNN_CLSS_MAC_VLAN, | |
105 | QED_TUNN_CLSS_MAC_VNI, | |
106 | QED_TUNN_CLSS_INNER_MAC_VLAN, | |
107 | QED_TUNN_CLSS_INNER_MAC_VNI, | |
108 | MAX_QED_TUNN_CLSS, | |
109 | }; | |
110 | ||
111 | struct qed_tunn_start_params { | |
112 | unsigned long tunn_mode; | |
113 | u16 vxlan_udp_port; | |
114 | u16 geneve_udp_port; | |
115 | u8 update_vxlan_udp_port; | |
116 | u8 update_geneve_udp_port; | |
117 | u8 tunn_clss_vxlan; | |
118 | u8 tunn_clss_l2geneve; | |
119 | u8 tunn_clss_ipgeneve; | |
120 | u8 tunn_clss_l2gre; | |
121 | u8 tunn_clss_ipgre; | |
122 | }; | |
123 | ||
124 | struct qed_tunn_update_params { | |
125 | unsigned long tunn_mode_update_mask; | |
126 | unsigned long tunn_mode; | |
127 | u16 vxlan_udp_port; | |
128 | u16 geneve_udp_port; | |
129 | u8 update_rx_pf_clss; | |
130 | u8 update_tx_pf_clss; | |
131 | u8 update_vxlan_udp_port; | |
132 | u8 update_geneve_udp_port; | |
133 | u8 tunn_clss_vxlan; | |
134 | u8 tunn_clss_l2geneve; | |
135 | u8 tunn_clss_ipgeneve; | |
136 | u8 tunn_clss_l2gre; | |
137 | u8 tunn_clss_ipgre; | |
138 | }; | |
139 | ||
fe56b9e6 YM |
140 | /* The PCI personality is not quite synonymous to protocol ID: |
141 | * 1. All personalities need CORE connections | |
142 | * 2. The Ethernet personality may support also the RoCE protocol | |
143 | */ | |
144 | enum qed_pci_personality { | |
145 | QED_PCI_ETH, | |
c5ac9319 YM |
146 | QED_PCI_ISCSI, |
147 | QED_PCI_ETH_ROCE, | |
fe56b9e6 YM |
148 | QED_PCI_DEFAULT /* default in shmem */ |
149 | }; | |
150 | ||
151 | /* All VFs are symmetric, all counters are PF + all VFs */ | |
152 | struct qed_qm_iids { | |
153 | u32 cids; | |
154 | u32 vf_cids; | |
155 | u32 tids; | |
156 | }; | |
157 | ||
2edbff8d TT |
158 | /* HW / FW resources, output of features supported below, most information |
159 | * is received from MFW. | |
160 | */ | |
161 | enum qed_resources { | |
fe56b9e6 | 162 | QED_SB, |
25c089d7 | 163 | QED_L2_QUEUE, |
fe56b9e6 | 164 | QED_VPORT, |
25c089d7 | 165 | QED_RSS_ENG, |
fe56b9e6 YM |
166 | QED_PQ, |
167 | QED_RL, | |
25c089d7 YM |
168 | QED_MAC, |
169 | QED_VLAN, | |
51ff1725 | 170 | QED_RDMA_CNQ_RAM, |
fe56b9e6 | 171 | QED_ILT, |
0a7fb11c | 172 | QED_LL2_QUEUE, |
2edbff8d | 173 | QED_CMDQS_CQS, |
51ff1725 | 174 | QED_RDMA_STATS_QUEUE, |
fe56b9e6 YM |
175 | QED_MAX_RESC, |
176 | }; | |
177 | ||
25c089d7 YM |
178 | enum QED_FEATURE { |
179 | QED_PF_L2_QUE, | |
32a47e72 | 180 | QED_VF, |
51ff1725 | 181 | QED_RDMA_CNQ, |
5a1f965a | 182 | QED_VF_L2_QUE, |
25c089d7 YM |
183 | QED_MAX_FEATURES, |
184 | }; | |
185 | ||
cc875c2e YM |
186 | enum QED_PORT_MODE { |
187 | QED_PORT_MODE_DE_2X40G, | |
188 | QED_PORT_MODE_DE_2X50G, | |
189 | QED_PORT_MODE_DE_1X100G, | |
190 | QED_PORT_MODE_DE_4X10G_F, | |
191 | QED_PORT_MODE_DE_4X10G_E, | |
192 | QED_PORT_MODE_DE_4X20G, | |
193 | QED_PORT_MODE_DE_1X40G, | |
194 | QED_PORT_MODE_DE_2X25G, | |
195 | QED_PORT_MODE_DE_1X25G | |
196 | }; | |
197 | ||
fc48b7a6 YM |
198 | enum qed_dev_cap { |
199 | QED_DEV_CAP_ETH, | |
c5ac9319 YM |
200 | QED_DEV_CAP_ISCSI, |
201 | QED_DEV_CAP_ROCE, | |
fc48b7a6 YM |
202 | }; |
203 | ||
14d39648 MY |
204 | enum qed_wol_support { |
205 | QED_WOL_SUPPORT_NONE, | |
206 | QED_WOL_SUPPORT_PME, | |
207 | }; | |
208 | ||
fe56b9e6 YM |
209 | struct qed_hw_info { |
210 | /* PCI personality */ | |
211 | enum qed_pci_personality personality; | |
212 | ||
213 | /* Resource Allocation scheme results */ | |
214 | u32 resc_start[QED_MAX_RESC]; | |
215 | u32 resc_num[QED_MAX_RESC]; | |
25c089d7 | 216 | u32 feat_num[QED_MAX_FEATURES]; |
fe56b9e6 YM |
217 | |
218 | #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) | |
219 | #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) | |
dbb799c3 YM |
220 | #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \ |
221 | RESC_NUM(_p_hwfn, resc)) | |
fe56b9e6 YM |
222 | #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) |
223 | ||
224 | u8 num_tc; | |
225 | u8 offload_tc; | |
226 | u8 non_offload_tc; | |
227 | ||
228 | u32 concrete_fid; | |
229 | u16 opaque_fid; | |
230 | u16 ovlan; | |
231 | u32 part_num[4]; | |
232 | ||
fe56b9e6 YM |
233 | unsigned char hw_mac_addr[ETH_ALEN]; |
234 | ||
235 | struct qed_igu_info *p_igu_info; | |
236 | ||
237 | u32 port_mode; | |
238 | u32 hw_mode; | |
fc48b7a6 | 239 | unsigned long device_capabilities; |
0fefbfba | 240 | u16 mtu; |
14d39648 MY |
241 | |
242 | enum qed_wol_support b_wol_support; | |
fe56b9e6 YM |
243 | }; |
244 | ||
fe56b9e6 YM |
245 | /* maximun size of read/write commands (HW limit) */ |
246 | #define DMAE_MAX_RW_SIZE 0x2000 | |
247 | ||
248 | struct qed_dmae_info { | |
249 | /* Mutex for synchronizing access to functions */ | |
250 | struct mutex mutex; | |
251 | ||
252 | u8 channel; | |
253 | ||
254 | dma_addr_t completion_word_phys_addr; | |
255 | ||
256 | /* The memory location where the DMAE writes the completion | |
257 | * value when an operation is finished on this context. | |
258 | */ | |
259 | u32 *p_completion_word; | |
260 | ||
261 | dma_addr_t intermediate_buffer_phys_addr; | |
262 | ||
263 | /* An intermediate buffer for DMAE operations that use virtual | |
264 | * addresses - data is DMA'd to/from this buffer and then | |
265 | * memcpy'd to/from the virtual address | |
266 | */ | |
267 | u32 *p_intermediate_buffer; | |
268 | ||
269 | dma_addr_t dmae_cmd_phys_addr; | |
270 | struct dmae_cmd *p_dmae_cmd; | |
271 | }; | |
272 | ||
bcd197c8 MC |
273 | struct qed_wfq_data { |
274 | /* when feature is configured for at least 1 vport */ | |
275 | u32 min_speed; | |
276 | bool configured; | |
277 | }; | |
278 | ||
fe56b9e6 YM |
279 | struct qed_qm_info { |
280 | struct init_qm_pq_params *qm_pq_params; | |
281 | struct init_qm_vport_params *qm_vport_params; | |
282 | struct init_qm_port_params *qm_port_params; | |
283 | u16 start_pq; | |
284 | u8 start_vport; | |
285 | u8 pure_lb_pq; | |
286 | u8 offload_pq; | |
287 | u8 pure_ack_pq; | |
dbb799c3 | 288 | u8 ooo_pq; |
fe56b9e6 YM |
289 | u8 vf_queues_offset; |
290 | u16 num_pqs; | |
291 | u16 num_vf_pqs; | |
292 | u8 num_vports; | |
293 | u8 max_phys_tcs_per_port; | |
294 | bool pf_rl_en; | |
295 | bool pf_wfq_en; | |
296 | bool vport_rl_en; | |
297 | bool vport_wfq_en; | |
298 | u8 pf_wfq; | |
299 | u32 pf_rl; | |
bcd197c8 | 300 | struct qed_wfq_data *wfq_data; |
dbb799c3 | 301 | u8 num_pf_rls; |
fe56b9e6 YM |
302 | }; |
303 | ||
9df2ed04 MC |
304 | struct storm_stats { |
305 | u32 address; | |
306 | u32 len; | |
307 | }; | |
308 | ||
309 | struct qed_storm_stats { | |
310 | struct storm_stats mstats; | |
311 | struct storm_stats pstats; | |
312 | struct storm_stats tstats; | |
313 | struct storm_stats ustats; | |
314 | }; | |
315 | ||
fe56b9e6 | 316 | struct qed_fw_data { |
9df2ed04 | 317 | struct fw_ver_info *fw_ver_info; |
fe56b9e6 YM |
318 | const u8 *modes_tree_buf; |
319 | union init_op *init_ops; | |
320 | const u32 *arr_data; | |
321 | u32 init_ops_size; | |
322 | }; | |
323 | ||
324 | struct qed_simd_fp_handler { | |
325 | void *token; | |
326 | void (*func)(void *); | |
327 | }; | |
328 | ||
329 | struct qed_hwfn { | |
330 | struct qed_dev *cdev; | |
331 | u8 my_id; /* ID inside the PF */ | |
332 | #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) | |
333 | u8 rel_pf_id; /* Relative to engine*/ | |
334 | u8 abs_pf_id; | |
335 | #define QED_PATH_ID(_p_hwfn) ((_p_hwfn)->abs_pf_id & 1) | |
336 | u8 port_id; | |
337 | bool b_active; | |
338 | ||
339 | u32 dp_module; | |
340 | u8 dp_level; | |
341 | char name[NAME_SIZE]; | |
342 | ||
343 | bool first_on_engine; | |
344 | bool hw_init_done; | |
345 | ||
1408cc1f | 346 | u8 num_funcs_on_engine; |
dbb799c3 | 347 | u8 enabled_func_idx; |
1408cc1f | 348 | |
fe56b9e6 YM |
349 | /* BAR access */ |
350 | void __iomem *regview; | |
351 | void __iomem *doorbells; | |
352 | u64 db_phys_addr; | |
353 | unsigned long db_size; | |
354 | ||
355 | /* PTT pool */ | |
356 | struct qed_ptt_pool *p_ptt_pool; | |
357 | ||
358 | /* HW info */ | |
359 | struct qed_hw_info hw_info; | |
360 | ||
361 | /* rt_array (for init-tool) */ | |
fc48b7a6 | 362 | struct qed_rt_data rt_data; |
fe56b9e6 YM |
363 | |
364 | /* SPQ */ | |
365 | struct qed_spq *p_spq; | |
366 | ||
367 | /* EQ */ | |
368 | struct qed_eq *p_eq; | |
369 | ||
370 | /* Consolidate Q*/ | |
371 | struct qed_consq *p_consq; | |
372 | ||
373 | /* Slow-Path definitions */ | |
374 | struct tasklet_struct *sp_dpc; | |
375 | bool b_sp_dpc_enabled; | |
376 | ||
377 | struct qed_ptt *p_main_ptt; | |
378 | struct qed_ptt *p_dpc_ptt; | |
379 | ||
380 | struct qed_sb_sp_info *p_sp_sb; | |
381 | struct qed_sb_attn_info *p_sb_attn; | |
382 | ||
383 | /* Protocol related */ | |
0a7fb11c YM |
384 | bool using_ll2; |
385 | struct qed_ll2_info *p_ll2_info; | |
51ff1725 | 386 | struct qed_rdma_info *p_rdma_info; |
fc831825 | 387 | struct qed_iscsi_info *p_iscsi_info; |
fe56b9e6 YM |
388 | struct qed_pf_params pf_params; |
389 | ||
dbb799c3 YM |
390 | bool b_rdma_enabled_in_prs; |
391 | u32 rdma_prs_search_reg; | |
392 | ||
fe56b9e6 YM |
393 | /* Array of sb_info of all status blocks */ |
394 | struct qed_sb_info *sbs_info[MAX_SB_PER_PF_MIMD]; | |
395 | u16 num_sbs; | |
396 | ||
397 | struct qed_cxt_mngr *p_cxt_mngr; | |
398 | ||
399 | /* Flag indicating whether interrupts are enabled or not*/ | |
400 | bool b_int_enabled; | |
8f16bc97 | 401 | bool b_int_requested; |
fe56b9e6 | 402 | |
fc916ff2 SRK |
403 | /* True if the driver requests for the link */ |
404 | bool b_drv_link_init; | |
405 | ||
1408cc1f | 406 | struct qed_vf_iov *vf_iov_info; |
32a47e72 | 407 | struct qed_pf_iov *pf_iov_info; |
fe56b9e6 YM |
408 | struct qed_mcp_info *mcp_info; |
409 | ||
39651abd SRK |
410 | struct qed_dcbx_info *p_dcbx_info; |
411 | ||
fe56b9e6 YM |
412 | struct qed_dmae_info dmae_info; |
413 | ||
414 | /* QM init */ | |
415 | struct qed_qm_info qm_info; | |
9df2ed04 | 416 | struct qed_storm_stats storm_stats; |
fe56b9e6 YM |
417 | |
418 | /* Buffer for unzipping firmware data */ | |
419 | void *unzip_buf; | |
420 | ||
c965db44 TT |
421 | struct dbg_tools_data dbg_info; |
422 | ||
51ff1725 RA |
423 | /* PWM region specific data */ |
424 | u32 dpi_size; | |
425 | u32 dpi_count; | |
426 | ||
427 | /* This is used to calculate the doorbell address */ | |
428 | u32 dpi_start_offset; | |
429 | ||
430 | /* If one of the following is set then EDPM shouldn't be used */ | |
431 | u8 dcbx_no_edpm; | |
432 | u8 db_bar_no_edpm; | |
433 | ||
fe56b9e6 YM |
434 | struct qed_simd_fp_handler simd_proto_handler[64]; |
435 | ||
37bff2b9 YM |
436 | #ifdef CONFIG_QED_SRIOV |
437 | struct workqueue_struct *iov_wq; | |
438 | struct delayed_work iov_task; | |
439 | unsigned long iov_task_flags; | |
440 | #endif | |
441 | ||
fe56b9e6 | 442 | struct z_stream_s *stream; |
abd49676 | 443 | struct qed_roce_ll2_info *ll2; |
fe56b9e6 YM |
444 | }; |
445 | ||
446 | struct pci_params { | |
447 | int pm_cap; | |
448 | ||
449 | unsigned long mem_start; | |
450 | unsigned long mem_end; | |
451 | unsigned int irq; | |
452 | u8 pf_num; | |
453 | }; | |
454 | ||
455 | struct qed_int_param { | |
456 | u32 int_mode; | |
457 | u8 num_vectors; | |
458 | u8 min_msix_cnt; /* for minimal functionality */ | |
459 | }; | |
460 | ||
461 | struct qed_int_params { | |
462 | struct qed_int_param in; | |
463 | struct qed_int_param out; | |
464 | struct msix_entry *msix_table; | |
465 | bool fp_initialized; | |
466 | u8 fp_msix_base; | |
467 | u8 fp_msix_cnt; | |
51ff1725 RA |
468 | u8 rdma_msix_base; |
469 | u8 rdma_msix_cnt; | |
fe56b9e6 YM |
470 | }; |
471 | ||
c965db44 TT |
472 | struct qed_dbg_feature { |
473 | struct dentry *dentry; | |
474 | u8 *dump_buf; | |
475 | u32 buf_size; | |
476 | u32 dumped_dwords; | |
477 | }; | |
478 | ||
479 | struct qed_dbg_params { | |
480 | struct qed_dbg_feature features[DBG_FEATURE_NUM]; | |
481 | u8 engine_for_debug; | |
482 | bool print_data; | |
483 | }; | |
484 | ||
fe56b9e6 YM |
485 | struct qed_dev { |
486 | u32 dp_module; | |
487 | u8 dp_level; | |
488 | char name[NAME_SIZE]; | |
489 | ||
490 | u8 type; | |
fc48b7a6 YM |
491 | #define QED_DEV_TYPE_BB (0 << 0) |
492 | #define QED_DEV_TYPE_AH BIT(0) | |
493 | /* Translate type/revision combo into the proper conditions */ | |
494 | #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB) | |
495 | #define QED_IS_BB_A0(dev) (QED_IS_BB(dev) && \ | |
496 | CHIP_REV_IS_A0(dev)) | |
497 | #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \ | |
498 | CHIP_REV_IS_B0(dev)) | |
c965db44 TT |
499 | #define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH) |
500 | #define QED_IS_K2(dev) QED_IS_AH(dev) | |
fc48b7a6 YM |
501 | |
502 | #define QED_GET_TYPE(dev) (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \ | |
503 | QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2) | |
504 | ||
505 | u16 vendor_id; | |
506 | u16 device_id; | |
fe56b9e6 YM |
507 | |
508 | u16 chip_num; | |
509 | #define CHIP_NUM_MASK 0xffff | |
510 | #define CHIP_NUM_SHIFT 16 | |
511 | ||
512 | u16 chip_rev; | |
513 | #define CHIP_REV_MASK 0xf | |
514 | #define CHIP_REV_SHIFT 12 | |
fc48b7a6 YM |
515 | #define CHIP_REV_IS_A0(_cdev) (!(_cdev)->chip_rev) |
516 | #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1) | |
fe56b9e6 YM |
517 | |
518 | u16 chip_metal; | |
519 | #define CHIP_METAL_MASK 0xff | |
520 | #define CHIP_METAL_SHIFT 4 | |
521 | ||
522 | u16 chip_bond_id; | |
523 | #define CHIP_BOND_ID_MASK 0xf | |
524 | #define CHIP_BOND_ID_SHIFT 0 | |
525 | ||
526 | u8 num_engines; | |
527 | u8 num_ports_in_engines; | |
528 | u8 num_funcs_in_port; | |
529 | ||
530 | u8 path_id; | |
fc48b7a6 YM |
531 | enum qed_mf_mode mf_mode; |
532 | #define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT) | |
533 | #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR) | |
534 | #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN) | |
fe56b9e6 YM |
535 | |
536 | int pcie_width; | |
537 | int pcie_speed; | |
538 | u8 ver_str[VER_SIZE]; | |
539 | ||
540 | /* Add MF related configuration */ | |
541 | u8 mcp_rev; | |
542 | u8 boot_mode; | |
543 | ||
14d39648 MY |
544 | /* WoL related configurations */ |
545 | u8 wol_config; | |
546 | u8 wol_mac[ETH_ALEN]; | |
fe56b9e6 YM |
547 | |
548 | u32 int_mode; | |
549 | enum qed_coalescing_mode int_coalescing_mode; | |
51d99880 SRK |
550 | u16 rx_coalesce_usecs; |
551 | u16 tx_coalesce_usecs; | |
fe56b9e6 YM |
552 | |
553 | /* Start Bar offset of first hwfn */ | |
554 | void __iomem *regview; | |
555 | void __iomem *doorbells; | |
556 | u64 db_phys_addr; | |
557 | unsigned long db_size; | |
558 | ||
559 | /* PCI */ | |
560 | u8 cache_shift; | |
561 | ||
562 | /* Init */ | |
563 | const struct iro *iro_arr; | |
564 | #define IRO (p_hwfn->cdev->iro_arr) | |
565 | ||
566 | /* HW functions */ | |
567 | u8 num_hwfns; | |
568 | struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; | |
569 | ||
32a47e72 YM |
570 | /* SRIOV */ |
571 | struct qed_hw_sriov_info *p_iov_info; | |
572 | #define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info) | |
573 | ||
464f6645 | 574 | unsigned long tunn_mode; |
1408cc1f YM |
575 | |
576 | bool b_is_vf; | |
fe56b9e6 | 577 | u32 drv_type; |
fe56b9e6 YM |
578 | struct qed_eth_stats *reset_stats; |
579 | struct qed_fw_data *fw_data; | |
580 | ||
581 | u32 mcp_nvm_resp; | |
582 | ||
583 | /* Linux specific here */ | |
584 | struct qede_dev *edev; | |
585 | struct pci_dev *pdev; | |
fc831825 YM |
586 | u32 flags; |
587 | #define QED_FLAG_STORAGE_STARTED (BIT(0)) | |
fe56b9e6 YM |
588 | int msg_enable; |
589 | ||
590 | struct pci_params pci_params; | |
591 | ||
592 | struct qed_int_params int_params; | |
593 | ||
594 | u8 protocol; | |
595 | #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH) | |
596 | ||
cc875c2e YM |
597 | /* Callbacks to protocol driver */ |
598 | union { | |
599 | struct qed_common_cb_ops *common; | |
600 | struct qed_eth_cb_ops *eth; | |
fc831825 | 601 | struct qed_iscsi_cb_ops *iscsi; |
cc875c2e YM |
602 | } protocol_ops; |
603 | void *ops_cookie; | |
604 | ||
c965db44 TT |
605 | struct qed_dbg_params dbg_params; |
606 | ||
0a7fb11c YM |
607 | #ifdef CONFIG_QED_LL2 |
608 | struct qed_cb_ll2_info *ll2; | |
609 | u8 ll2_mac_address[ETH_ALEN]; | |
610 | #endif | |
fc831825 | 611 | DECLARE_HASHTABLE(connections, 10); |
fe56b9e6 | 612 | const struct firmware *firmware; |
51ff1725 RA |
613 | |
614 | u32 rdma_max_sge; | |
615 | u32 rdma_max_inline; | |
616 | u32 rdma_max_srq_sge; | |
fe56b9e6 YM |
617 | }; |
618 | ||
32a47e72 | 619 | #define NUM_OF_VFS(dev) MAX_NUM_VFS_BB |
dacd88d6 | 620 | #define NUM_OF_L2_QUEUES(dev) MAX_NUM_L2_QUEUES_BB |
fe56b9e6 YM |
621 | #define NUM_OF_SBS(dev) MAX_SB_PER_PATH_BB |
622 | #define NUM_OF_ENG_PFS(dev) MAX_NUM_PFS_BB | |
623 | ||
624 | /** | |
625 | * @brief qed_concrete_to_sw_fid - get the sw function id from | |
626 | * the concrete value. | |
627 | * | |
628 | * @param concrete_fid | |
629 | * | |
630 | * @return inline u8 | |
631 | */ | |
632 | static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev, | |
633 | u32 concrete_fid) | |
634 | { | |
4870e704 | 635 | u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); |
fe56b9e6 | 636 | u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); |
4870e704 YM |
637 | u8 vf_valid = GET_FIELD(concrete_fid, |
638 | PXP_CONCRETE_FID_VFVALID); | |
639 | u8 sw_fid; | |
fe56b9e6 | 640 | |
4870e704 YM |
641 | if (vf_valid) |
642 | sw_fid = vfid + MAX_NUM_PFS; | |
643 | else | |
644 | sw_fid = pfid; | |
645 | ||
646 | return sw_fid; | |
fe56b9e6 YM |
647 | } |
648 | ||
649 | #define PURE_LB_TC 8 | |
dbb799c3 | 650 | #define OOO_LB_TC 9 |
fe56b9e6 | 651 | |
733def6a | 652 | int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate); |
bcd197c8 MC |
653 | void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate); |
654 | ||
733def6a | 655 | void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); |
fe56b9e6 YM |
656 | #define QED_LEADING_HWFN(dev) (&dev->hwfns[0]) |
657 | ||
658 | /* Other Linux specific common definitions */ | |
659 | #define DP_NAME(cdev) ((cdev)->name) | |
660 | ||
661 | #define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\ | |
662 | (cdev->regview) + \ | |
663 | (offset)) | |
664 | ||
665 | #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset)) | |
666 | #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset)) | |
667 | #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset)) | |
668 | ||
669 | #define DOORBELL(cdev, db_addr, val) \ | |
670 | writel((u32)val, (void __iomem *)((u8 __iomem *)\ | |
671 | (cdev->doorbells) + (db_addr))) | |
672 | ||
673 | /* Prototypes */ | |
674 | int qed_fill_dev_info(struct qed_dev *cdev, | |
675 | struct qed_dev_info *dev_info); | |
cc875c2e | 676 | void qed_link_update(struct qed_hwfn *hwfn); |
fe56b9e6 YM |
677 | u32 qed_unzip_data(struct qed_hwfn *p_hwfn, |
678 | u32 input_len, u8 *input_buf, | |
679 | u32 max_size, u8 *unzip_buf); | |
6c754246 SRK |
680 | void qed_get_protocol_stats(struct qed_dev *cdev, |
681 | enum qed_mcp_protocol_type type, | |
682 | union qed_mcp_protocol_stats *stats); | |
8f16bc97 SK |
683 | int qed_slowpath_irq_req(struct qed_hwfn *hwfn); |
684 | ||
fe56b9e6 | 685 | #endif /* _QED_H */ |