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fe56b9e6 | 1 | /* QLogic qed NIC Driver |
e8f1cb50 | 2 | * Copyright (c) 2015-2017 QLogic Corporation |
fe56b9e6 | 3 | * |
e8f1cb50 MY |
4 | * This software is available to you under a choice of one of two |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and /or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
fe56b9e6 YM |
31 | */ |
32 | ||
33 | #ifndef _QED_H | |
34 | #define _QED_H | |
35 | ||
36 | #include <linux/types.h> | |
37 | #include <linux/io.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/firmware.h> | |
40 | #include <linux/interrupt.h> | |
41 | #include <linux/list.h> | |
42 | #include <linux/mutex.h> | |
43 | #include <linux/pci.h> | |
44 | #include <linux/slab.h> | |
45 | #include <linux/string.h> | |
46 | #include <linux/workqueue.h> | |
47 | #include <linux/zlib.h> | |
48 | #include <linux/hashtable.h> | |
49 | #include <linux/qed/qed_if.h> | |
c965db44 | 50 | #include "qed_debug.h" |
fe56b9e6 YM |
51 | #include "qed_hsi.h" |
52 | ||
25c089d7 | 53 | extern const struct qed_common_ops qed_common_ops_pass; |
ce742922 | 54 | #define DRV_MODULE_VERSION "8.10.10.20" |
fe56b9e6 YM |
55 | |
56 | #define MAX_HWFNS_PER_DEVICE (4) | |
57 | #define NAME_SIZE 16 | |
58 | #define VER_SIZE 16 | |
59 | ||
bcd197c8 MC |
60 | #define QED_WFQ_UNIT 100 |
61 | ||
fc831825 | 62 | #define ISCSI_BDQ_ID(_port_id) (_port_id) |
51ff1725 RA |
63 | #define QED_WID_SIZE (1024) |
64 | #define QED_PF_DEMS_SIZE (4) | |
65 | ||
fe56b9e6 YM |
66 | /* cau states */ |
67 | enum qed_coalescing_mode { | |
68 | QED_COAL_MODE_DISABLE, | |
69 | QED_COAL_MODE_ENABLE | |
70 | }; | |
71 | ||
72 | struct qed_eth_cb_ops; | |
73 | struct qed_dev_info; | |
6c754246 SRK |
74 | union qed_mcp_protocol_stats; |
75 | enum qed_mcp_protocol_type; | |
fe56b9e6 YM |
76 | |
77 | /* helpers */ | |
78 | static inline u32 qed_db_addr(u32 cid, u32 DEMS) | |
51ff1725 RA |
79 | { |
80 | u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | | |
81 | (cid * QED_PF_DEMS_SIZE); | |
82 | ||
83 | return db_addr; | |
84 | } | |
85 | ||
86 | static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS) | |
fe56b9e6 YM |
87 | { |
88 | u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | | |
89 | FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid); | |
90 | ||
91 | return db_addr; | |
92 | } | |
93 | ||
94 | #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \ | |
95 | ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \ | |
96 | ~((1 << (p_hwfn->cdev->cache_shift)) - 1)) | |
97 | ||
98 | #define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++) | |
99 | ||
100 | #define D_TRINE(val, cond1, cond2, true1, true2, def) \ | |
101 | (val == (cond1) ? true1 : \ | |
102 | (val == (cond2) ? true2 : def)) | |
103 | ||
104 | /* forward */ | |
105 | struct qed_ptt_pool; | |
106 | struct qed_spq; | |
107 | struct qed_sb_info; | |
108 | struct qed_sb_attn_info; | |
109 | struct qed_cxt_mngr; | |
110 | struct qed_sb_sp_info; | |
0a7fb11c | 111 | struct qed_ll2_info; |
fe56b9e6 YM |
112 | struct qed_mcp_info; |
113 | ||
114 | struct qed_rt_data { | |
fc48b7a6 YM |
115 | u32 *init_val; |
116 | bool *b_valid; | |
fe56b9e6 YM |
117 | }; |
118 | ||
464f6645 MC |
119 | enum qed_tunn_mode { |
120 | QED_MODE_L2GENEVE_TUNN, | |
121 | QED_MODE_IPGENEVE_TUNN, | |
122 | QED_MODE_L2GRE_TUNN, | |
123 | QED_MODE_IPGRE_TUNN, | |
124 | QED_MODE_VXLAN_TUNN, | |
125 | }; | |
126 | ||
127 | enum qed_tunn_clss { | |
128 | QED_TUNN_CLSS_MAC_VLAN, | |
129 | QED_TUNN_CLSS_MAC_VNI, | |
130 | QED_TUNN_CLSS_INNER_MAC_VLAN, | |
131 | QED_TUNN_CLSS_INNER_MAC_VNI, | |
132 | MAX_QED_TUNN_CLSS, | |
133 | }; | |
134 | ||
135 | struct qed_tunn_start_params { | |
136 | unsigned long tunn_mode; | |
137 | u16 vxlan_udp_port; | |
138 | u16 geneve_udp_port; | |
139 | u8 update_vxlan_udp_port; | |
140 | u8 update_geneve_udp_port; | |
141 | u8 tunn_clss_vxlan; | |
142 | u8 tunn_clss_l2geneve; | |
143 | u8 tunn_clss_ipgeneve; | |
144 | u8 tunn_clss_l2gre; | |
145 | u8 tunn_clss_ipgre; | |
146 | }; | |
147 | ||
148 | struct qed_tunn_update_params { | |
149 | unsigned long tunn_mode_update_mask; | |
150 | unsigned long tunn_mode; | |
151 | u16 vxlan_udp_port; | |
152 | u16 geneve_udp_port; | |
153 | u8 update_rx_pf_clss; | |
154 | u8 update_tx_pf_clss; | |
155 | u8 update_vxlan_udp_port; | |
156 | u8 update_geneve_udp_port; | |
157 | u8 tunn_clss_vxlan; | |
158 | u8 tunn_clss_l2geneve; | |
159 | u8 tunn_clss_ipgeneve; | |
160 | u8 tunn_clss_l2gre; | |
161 | u8 tunn_clss_ipgre; | |
162 | }; | |
163 | ||
fe56b9e6 YM |
164 | /* The PCI personality is not quite synonymous to protocol ID: |
165 | * 1. All personalities need CORE connections | |
166 | * 2. The Ethernet personality may support also the RoCE protocol | |
167 | */ | |
168 | enum qed_pci_personality { | |
169 | QED_PCI_ETH, | |
c5ac9319 YM |
170 | QED_PCI_ISCSI, |
171 | QED_PCI_ETH_ROCE, | |
fe56b9e6 YM |
172 | QED_PCI_DEFAULT /* default in shmem */ |
173 | }; | |
174 | ||
175 | /* All VFs are symmetric, all counters are PF + all VFs */ | |
176 | struct qed_qm_iids { | |
177 | u32 cids; | |
178 | u32 vf_cids; | |
179 | u32 tids; | |
180 | }; | |
181 | ||
2edbff8d TT |
182 | /* HW / FW resources, output of features supported below, most information |
183 | * is received from MFW. | |
184 | */ | |
185 | enum qed_resources { | |
fe56b9e6 | 186 | QED_SB, |
25c089d7 | 187 | QED_L2_QUEUE, |
fe56b9e6 | 188 | QED_VPORT, |
25c089d7 | 189 | QED_RSS_ENG, |
fe56b9e6 YM |
190 | QED_PQ, |
191 | QED_RL, | |
25c089d7 YM |
192 | QED_MAC, |
193 | QED_VLAN, | |
51ff1725 | 194 | QED_RDMA_CNQ_RAM, |
fe56b9e6 | 195 | QED_ILT, |
0a7fb11c | 196 | QED_LL2_QUEUE, |
2edbff8d | 197 | QED_CMDQS_CQS, |
51ff1725 | 198 | QED_RDMA_STATS_QUEUE, |
fe56b9e6 YM |
199 | QED_MAX_RESC, |
200 | }; | |
201 | ||
25c089d7 YM |
202 | enum QED_FEATURE { |
203 | QED_PF_L2_QUE, | |
32a47e72 | 204 | QED_VF, |
51ff1725 | 205 | QED_RDMA_CNQ, |
5a1f965a | 206 | QED_VF_L2_QUE, |
25c089d7 YM |
207 | QED_MAX_FEATURES, |
208 | }; | |
209 | ||
cc875c2e YM |
210 | enum QED_PORT_MODE { |
211 | QED_PORT_MODE_DE_2X40G, | |
212 | QED_PORT_MODE_DE_2X50G, | |
213 | QED_PORT_MODE_DE_1X100G, | |
214 | QED_PORT_MODE_DE_4X10G_F, | |
215 | QED_PORT_MODE_DE_4X10G_E, | |
216 | QED_PORT_MODE_DE_4X20G, | |
217 | QED_PORT_MODE_DE_1X40G, | |
218 | QED_PORT_MODE_DE_2X25G, | |
219 | QED_PORT_MODE_DE_1X25G | |
220 | }; | |
221 | ||
fc48b7a6 YM |
222 | enum qed_dev_cap { |
223 | QED_DEV_CAP_ETH, | |
c5ac9319 YM |
224 | QED_DEV_CAP_ISCSI, |
225 | QED_DEV_CAP_ROCE, | |
fc48b7a6 YM |
226 | }; |
227 | ||
14d39648 MY |
228 | enum qed_wol_support { |
229 | QED_WOL_SUPPORT_NONE, | |
230 | QED_WOL_SUPPORT_PME, | |
231 | }; | |
232 | ||
fe56b9e6 YM |
233 | struct qed_hw_info { |
234 | /* PCI personality */ | |
235 | enum qed_pci_personality personality; | |
236 | ||
237 | /* Resource Allocation scheme results */ | |
238 | u32 resc_start[QED_MAX_RESC]; | |
239 | u32 resc_num[QED_MAX_RESC]; | |
25c089d7 | 240 | u32 feat_num[QED_MAX_FEATURES]; |
fe56b9e6 YM |
241 | |
242 | #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) | |
243 | #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) | |
dbb799c3 YM |
244 | #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \ |
245 | RESC_NUM(_p_hwfn, resc)) | |
fe56b9e6 YM |
246 | #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) |
247 | ||
248 | u8 num_tc; | |
249 | u8 offload_tc; | |
250 | u8 non_offload_tc; | |
251 | ||
252 | u32 concrete_fid; | |
253 | u16 opaque_fid; | |
254 | u16 ovlan; | |
255 | u32 part_num[4]; | |
256 | ||
fe56b9e6 YM |
257 | unsigned char hw_mac_addr[ETH_ALEN]; |
258 | ||
259 | struct qed_igu_info *p_igu_info; | |
260 | ||
261 | u32 port_mode; | |
262 | u32 hw_mode; | |
fc48b7a6 | 263 | unsigned long device_capabilities; |
0fefbfba | 264 | u16 mtu; |
14d39648 MY |
265 | |
266 | enum qed_wol_support b_wol_support; | |
fe56b9e6 YM |
267 | }; |
268 | ||
fe56b9e6 YM |
269 | /* maximun size of read/write commands (HW limit) */ |
270 | #define DMAE_MAX_RW_SIZE 0x2000 | |
271 | ||
272 | struct qed_dmae_info { | |
273 | /* Mutex for synchronizing access to functions */ | |
274 | struct mutex mutex; | |
275 | ||
276 | u8 channel; | |
277 | ||
278 | dma_addr_t completion_word_phys_addr; | |
279 | ||
280 | /* The memory location where the DMAE writes the completion | |
281 | * value when an operation is finished on this context. | |
282 | */ | |
283 | u32 *p_completion_word; | |
284 | ||
285 | dma_addr_t intermediate_buffer_phys_addr; | |
286 | ||
287 | /* An intermediate buffer for DMAE operations that use virtual | |
288 | * addresses - data is DMA'd to/from this buffer and then | |
289 | * memcpy'd to/from the virtual address | |
290 | */ | |
291 | u32 *p_intermediate_buffer; | |
292 | ||
293 | dma_addr_t dmae_cmd_phys_addr; | |
294 | struct dmae_cmd *p_dmae_cmd; | |
295 | }; | |
296 | ||
bcd197c8 MC |
297 | struct qed_wfq_data { |
298 | /* when feature is configured for at least 1 vport */ | |
299 | u32 min_speed; | |
300 | bool configured; | |
301 | }; | |
302 | ||
fe56b9e6 YM |
303 | struct qed_qm_info { |
304 | struct init_qm_pq_params *qm_pq_params; | |
305 | struct init_qm_vport_params *qm_vport_params; | |
306 | struct init_qm_port_params *qm_port_params; | |
307 | u16 start_pq; | |
308 | u8 start_vport; | |
309 | u8 pure_lb_pq; | |
310 | u8 offload_pq; | |
311 | u8 pure_ack_pq; | |
dbb799c3 | 312 | u8 ooo_pq; |
fe56b9e6 YM |
313 | u8 vf_queues_offset; |
314 | u16 num_pqs; | |
315 | u16 num_vf_pqs; | |
316 | u8 num_vports; | |
317 | u8 max_phys_tcs_per_port; | |
318 | bool pf_rl_en; | |
319 | bool pf_wfq_en; | |
320 | bool vport_rl_en; | |
321 | bool vport_wfq_en; | |
322 | u8 pf_wfq; | |
323 | u32 pf_rl; | |
bcd197c8 | 324 | struct qed_wfq_data *wfq_data; |
dbb799c3 | 325 | u8 num_pf_rls; |
fe56b9e6 YM |
326 | }; |
327 | ||
9df2ed04 MC |
328 | struct storm_stats { |
329 | u32 address; | |
330 | u32 len; | |
331 | }; | |
332 | ||
333 | struct qed_storm_stats { | |
334 | struct storm_stats mstats; | |
335 | struct storm_stats pstats; | |
336 | struct storm_stats tstats; | |
337 | struct storm_stats ustats; | |
338 | }; | |
339 | ||
fe56b9e6 | 340 | struct qed_fw_data { |
9df2ed04 | 341 | struct fw_ver_info *fw_ver_info; |
fe56b9e6 YM |
342 | const u8 *modes_tree_buf; |
343 | union init_op *init_ops; | |
344 | const u32 *arr_data; | |
345 | u32 init_ops_size; | |
346 | }; | |
347 | ||
348 | struct qed_simd_fp_handler { | |
349 | void *token; | |
350 | void (*func)(void *); | |
351 | }; | |
352 | ||
353 | struct qed_hwfn { | |
354 | struct qed_dev *cdev; | |
355 | u8 my_id; /* ID inside the PF */ | |
356 | #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) | |
357 | u8 rel_pf_id; /* Relative to engine*/ | |
358 | u8 abs_pf_id; | |
359 | #define QED_PATH_ID(_p_hwfn) ((_p_hwfn)->abs_pf_id & 1) | |
360 | u8 port_id; | |
361 | bool b_active; | |
362 | ||
363 | u32 dp_module; | |
364 | u8 dp_level; | |
365 | char name[NAME_SIZE]; | |
366 | ||
367 | bool first_on_engine; | |
368 | bool hw_init_done; | |
369 | ||
1408cc1f | 370 | u8 num_funcs_on_engine; |
dbb799c3 | 371 | u8 enabled_func_idx; |
1408cc1f | 372 | |
fe56b9e6 YM |
373 | /* BAR access */ |
374 | void __iomem *regview; | |
375 | void __iomem *doorbells; | |
376 | u64 db_phys_addr; | |
377 | unsigned long db_size; | |
378 | ||
379 | /* PTT pool */ | |
380 | struct qed_ptt_pool *p_ptt_pool; | |
381 | ||
382 | /* HW info */ | |
383 | struct qed_hw_info hw_info; | |
384 | ||
385 | /* rt_array (for init-tool) */ | |
fc48b7a6 | 386 | struct qed_rt_data rt_data; |
fe56b9e6 YM |
387 | |
388 | /* SPQ */ | |
389 | struct qed_spq *p_spq; | |
390 | ||
391 | /* EQ */ | |
392 | struct qed_eq *p_eq; | |
393 | ||
394 | /* Consolidate Q*/ | |
395 | struct qed_consq *p_consq; | |
396 | ||
397 | /* Slow-Path definitions */ | |
398 | struct tasklet_struct *sp_dpc; | |
399 | bool b_sp_dpc_enabled; | |
400 | ||
401 | struct qed_ptt *p_main_ptt; | |
402 | struct qed_ptt *p_dpc_ptt; | |
403 | ||
404 | struct qed_sb_sp_info *p_sp_sb; | |
405 | struct qed_sb_attn_info *p_sb_attn; | |
406 | ||
407 | /* Protocol related */ | |
0a7fb11c YM |
408 | bool using_ll2; |
409 | struct qed_ll2_info *p_ll2_info; | |
1d6cff4f | 410 | struct qed_ooo_info *p_ooo_info; |
51ff1725 | 411 | struct qed_rdma_info *p_rdma_info; |
fc831825 | 412 | struct qed_iscsi_info *p_iscsi_info; |
fe56b9e6 YM |
413 | struct qed_pf_params pf_params; |
414 | ||
dbb799c3 YM |
415 | bool b_rdma_enabled_in_prs; |
416 | u32 rdma_prs_search_reg; | |
417 | ||
fe56b9e6 YM |
418 | /* Array of sb_info of all status blocks */ |
419 | struct qed_sb_info *sbs_info[MAX_SB_PER_PF_MIMD]; | |
420 | u16 num_sbs; | |
421 | ||
422 | struct qed_cxt_mngr *p_cxt_mngr; | |
423 | ||
424 | /* Flag indicating whether interrupts are enabled or not*/ | |
425 | bool b_int_enabled; | |
8f16bc97 | 426 | bool b_int_requested; |
fe56b9e6 | 427 | |
fc916ff2 SRK |
428 | /* True if the driver requests for the link */ |
429 | bool b_drv_link_init; | |
430 | ||
1408cc1f | 431 | struct qed_vf_iov *vf_iov_info; |
32a47e72 | 432 | struct qed_pf_iov *pf_iov_info; |
fe56b9e6 YM |
433 | struct qed_mcp_info *mcp_info; |
434 | ||
39651abd SRK |
435 | struct qed_dcbx_info *p_dcbx_info; |
436 | ||
fe56b9e6 YM |
437 | struct qed_dmae_info dmae_info; |
438 | ||
439 | /* QM init */ | |
440 | struct qed_qm_info qm_info; | |
9df2ed04 | 441 | struct qed_storm_stats storm_stats; |
fe56b9e6 YM |
442 | |
443 | /* Buffer for unzipping firmware data */ | |
444 | void *unzip_buf; | |
445 | ||
c965db44 TT |
446 | struct dbg_tools_data dbg_info; |
447 | ||
51ff1725 RA |
448 | /* PWM region specific data */ |
449 | u32 dpi_size; | |
450 | u32 dpi_count; | |
451 | ||
452 | /* This is used to calculate the doorbell address */ | |
453 | u32 dpi_start_offset; | |
454 | ||
455 | /* If one of the following is set then EDPM shouldn't be used */ | |
456 | u8 dcbx_no_edpm; | |
457 | u8 db_bar_no_edpm; | |
458 | ||
c78c70fa SRK |
459 | /* p_ptp_ptt is valid for leading HWFN only */ |
460 | struct qed_ptt *p_ptp_ptt; | |
fe56b9e6 YM |
461 | struct qed_simd_fp_handler simd_proto_handler[64]; |
462 | ||
37bff2b9 YM |
463 | #ifdef CONFIG_QED_SRIOV |
464 | struct workqueue_struct *iov_wq; | |
465 | struct delayed_work iov_task; | |
466 | unsigned long iov_task_flags; | |
467 | #endif | |
468 | ||
fe56b9e6 | 469 | struct z_stream_s *stream; |
abd49676 | 470 | struct qed_roce_ll2_info *ll2; |
fe56b9e6 YM |
471 | }; |
472 | ||
473 | struct pci_params { | |
474 | int pm_cap; | |
475 | ||
476 | unsigned long mem_start; | |
477 | unsigned long mem_end; | |
478 | unsigned int irq; | |
479 | u8 pf_num; | |
480 | }; | |
481 | ||
482 | struct qed_int_param { | |
483 | u32 int_mode; | |
484 | u8 num_vectors; | |
485 | u8 min_msix_cnt; /* for minimal functionality */ | |
486 | }; | |
487 | ||
488 | struct qed_int_params { | |
489 | struct qed_int_param in; | |
490 | struct qed_int_param out; | |
491 | struct msix_entry *msix_table; | |
492 | bool fp_initialized; | |
493 | u8 fp_msix_base; | |
494 | u8 fp_msix_cnt; | |
51ff1725 RA |
495 | u8 rdma_msix_base; |
496 | u8 rdma_msix_cnt; | |
fe56b9e6 YM |
497 | }; |
498 | ||
c965db44 TT |
499 | struct qed_dbg_feature { |
500 | struct dentry *dentry; | |
501 | u8 *dump_buf; | |
502 | u32 buf_size; | |
503 | u32 dumped_dwords; | |
504 | }; | |
505 | ||
506 | struct qed_dbg_params { | |
507 | struct qed_dbg_feature features[DBG_FEATURE_NUM]; | |
508 | u8 engine_for_debug; | |
509 | bool print_data; | |
510 | }; | |
511 | ||
fe56b9e6 YM |
512 | struct qed_dev { |
513 | u32 dp_module; | |
514 | u8 dp_level; | |
515 | char name[NAME_SIZE]; | |
516 | ||
517 | u8 type; | |
fc48b7a6 YM |
518 | #define QED_DEV_TYPE_BB (0 << 0) |
519 | #define QED_DEV_TYPE_AH BIT(0) | |
520 | /* Translate type/revision combo into the proper conditions */ | |
521 | #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB) | |
522 | #define QED_IS_BB_A0(dev) (QED_IS_BB(dev) && \ | |
523 | CHIP_REV_IS_A0(dev)) | |
524 | #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \ | |
525 | CHIP_REV_IS_B0(dev)) | |
c965db44 TT |
526 | #define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH) |
527 | #define QED_IS_K2(dev) QED_IS_AH(dev) | |
fc48b7a6 YM |
528 | |
529 | #define QED_GET_TYPE(dev) (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \ | |
530 | QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2) | |
531 | ||
532 | u16 vendor_id; | |
533 | u16 device_id; | |
fe56b9e6 YM |
534 | |
535 | u16 chip_num; | |
536 | #define CHIP_NUM_MASK 0xffff | |
537 | #define CHIP_NUM_SHIFT 16 | |
538 | ||
539 | u16 chip_rev; | |
540 | #define CHIP_REV_MASK 0xf | |
541 | #define CHIP_REV_SHIFT 12 | |
fc48b7a6 YM |
542 | #define CHIP_REV_IS_A0(_cdev) (!(_cdev)->chip_rev) |
543 | #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1) | |
fe56b9e6 YM |
544 | |
545 | u16 chip_metal; | |
546 | #define CHIP_METAL_MASK 0xff | |
547 | #define CHIP_METAL_SHIFT 4 | |
548 | ||
549 | u16 chip_bond_id; | |
550 | #define CHIP_BOND_ID_MASK 0xf | |
551 | #define CHIP_BOND_ID_SHIFT 0 | |
552 | ||
553 | u8 num_engines; | |
554 | u8 num_ports_in_engines; | |
555 | u8 num_funcs_in_port; | |
556 | ||
557 | u8 path_id; | |
fc48b7a6 YM |
558 | enum qed_mf_mode mf_mode; |
559 | #define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT) | |
560 | #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR) | |
561 | #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN) | |
fe56b9e6 YM |
562 | |
563 | int pcie_width; | |
564 | int pcie_speed; | |
565 | u8 ver_str[VER_SIZE]; | |
566 | ||
567 | /* Add MF related configuration */ | |
568 | u8 mcp_rev; | |
569 | u8 boot_mode; | |
570 | ||
14d39648 MY |
571 | /* WoL related configurations */ |
572 | u8 wol_config; | |
573 | u8 wol_mac[ETH_ALEN]; | |
fe56b9e6 YM |
574 | |
575 | u32 int_mode; | |
576 | enum qed_coalescing_mode int_coalescing_mode; | |
51d99880 SRK |
577 | u16 rx_coalesce_usecs; |
578 | u16 tx_coalesce_usecs; | |
fe56b9e6 YM |
579 | |
580 | /* Start Bar offset of first hwfn */ | |
581 | void __iomem *regview; | |
582 | void __iomem *doorbells; | |
583 | u64 db_phys_addr; | |
584 | unsigned long db_size; | |
585 | ||
586 | /* PCI */ | |
587 | u8 cache_shift; | |
588 | ||
589 | /* Init */ | |
590 | const struct iro *iro_arr; | |
591 | #define IRO (p_hwfn->cdev->iro_arr) | |
592 | ||
593 | /* HW functions */ | |
594 | u8 num_hwfns; | |
595 | struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; | |
596 | ||
32a47e72 YM |
597 | /* SRIOV */ |
598 | struct qed_hw_sriov_info *p_iov_info; | |
599 | #define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info) | |
600 | ||
464f6645 | 601 | unsigned long tunn_mode; |
1408cc1f YM |
602 | |
603 | bool b_is_vf; | |
fe56b9e6 | 604 | u32 drv_type; |
fe56b9e6 YM |
605 | struct qed_eth_stats *reset_stats; |
606 | struct qed_fw_data *fw_data; | |
607 | ||
608 | u32 mcp_nvm_resp; | |
609 | ||
610 | /* Linux specific here */ | |
611 | struct qede_dev *edev; | |
612 | struct pci_dev *pdev; | |
fc831825 YM |
613 | u32 flags; |
614 | #define QED_FLAG_STORAGE_STARTED (BIT(0)) | |
fe56b9e6 YM |
615 | int msg_enable; |
616 | ||
617 | struct pci_params pci_params; | |
618 | ||
619 | struct qed_int_params int_params; | |
620 | ||
621 | u8 protocol; | |
622 | #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH) | |
623 | ||
cc875c2e YM |
624 | /* Callbacks to protocol driver */ |
625 | union { | |
626 | struct qed_common_cb_ops *common; | |
627 | struct qed_eth_cb_ops *eth; | |
fc831825 | 628 | struct qed_iscsi_cb_ops *iscsi; |
cc875c2e YM |
629 | } protocol_ops; |
630 | void *ops_cookie; | |
631 | ||
c965db44 TT |
632 | struct qed_dbg_params dbg_params; |
633 | ||
0a7fb11c YM |
634 | #ifdef CONFIG_QED_LL2 |
635 | struct qed_cb_ll2_info *ll2; | |
636 | u8 ll2_mac_address[ETH_ALEN]; | |
637 | #endif | |
fc831825 | 638 | DECLARE_HASHTABLE(connections, 10); |
fe56b9e6 | 639 | const struct firmware *firmware; |
51ff1725 RA |
640 | |
641 | u32 rdma_max_sge; | |
642 | u32 rdma_max_inline; | |
643 | u32 rdma_max_srq_sge; | |
fe56b9e6 YM |
644 | }; |
645 | ||
32a47e72 | 646 | #define NUM_OF_VFS(dev) MAX_NUM_VFS_BB |
dacd88d6 | 647 | #define NUM_OF_L2_QUEUES(dev) MAX_NUM_L2_QUEUES_BB |
fe56b9e6 YM |
648 | #define NUM_OF_SBS(dev) MAX_SB_PER_PATH_BB |
649 | #define NUM_OF_ENG_PFS(dev) MAX_NUM_PFS_BB | |
650 | ||
651 | /** | |
652 | * @brief qed_concrete_to_sw_fid - get the sw function id from | |
653 | * the concrete value. | |
654 | * | |
655 | * @param concrete_fid | |
656 | * | |
657 | * @return inline u8 | |
658 | */ | |
659 | static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev, | |
660 | u32 concrete_fid) | |
661 | { | |
4870e704 | 662 | u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); |
fe56b9e6 | 663 | u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); |
4870e704 YM |
664 | u8 vf_valid = GET_FIELD(concrete_fid, |
665 | PXP_CONCRETE_FID_VFVALID); | |
666 | u8 sw_fid; | |
fe56b9e6 | 667 | |
4870e704 YM |
668 | if (vf_valid) |
669 | sw_fid = vfid + MAX_NUM_PFS; | |
670 | else | |
671 | sw_fid = pfid; | |
672 | ||
673 | return sw_fid; | |
fe56b9e6 YM |
674 | } |
675 | ||
676 | #define PURE_LB_TC 8 | |
dbb799c3 | 677 | #define OOO_LB_TC 9 |
fe56b9e6 | 678 | |
733def6a | 679 | int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate); |
bcd197c8 MC |
680 | void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate); |
681 | ||
733def6a | 682 | void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); |
fe56b9e6 YM |
683 | #define QED_LEADING_HWFN(dev) (&dev->hwfns[0]) |
684 | ||
685 | /* Other Linux specific common definitions */ | |
686 | #define DP_NAME(cdev) ((cdev)->name) | |
687 | ||
688 | #define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\ | |
689 | (cdev->regview) + \ | |
690 | (offset)) | |
691 | ||
692 | #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset)) | |
693 | #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset)) | |
694 | #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset)) | |
695 | ||
696 | #define DOORBELL(cdev, db_addr, val) \ | |
697 | writel((u32)val, (void __iomem *)((u8 __iomem *)\ | |
698 | (cdev->doorbells) + (db_addr))) | |
699 | ||
700 | /* Prototypes */ | |
701 | int qed_fill_dev_info(struct qed_dev *cdev, | |
702 | struct qed_dev_info *dev_info); | |
cc875c2e | 703 | void qed_link_update(struct qed_hwfn *hwfn); |
fe56b9e6 YM |
704 | u32 qed_unzip_data(struct qed_hwfn *p_hwfn, |
705 | u32 input_len, u8 *input_buf, | |
706 | u32 max_size, u8 *unzip_buf); | |
6c754246 SRK |
707 | void qed_get_protocol_stats(struct qed_dev *cdev, |
708 | enum qed_mcp_protocol_type type, | |
709 | union qed_mcp_protocol_stats *stats); | |
8f16bc97 SK |
710 | int qed_slowpath_irq_req(struct qed_hwfn *hwfn); |
711 | ||
fe56b9e6 | 712 | #endif /* _QED_H */ |