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fe56b9e6 YM |
1 | /* QLogic qed NIC Driver |
2 | * Copyright (c) 2015 QLogic Corporation | |
3 | * | |
4 | * This software is available under the terms of the GNU General Public License | |
5 | * (GPL) Version 2, available from the file COPYING in the main directory of | |
6 | * this source tree. | |
7 | */ | |
8 | ||
9 | #ifndef _QED_H | |
10 | #define _QED_H | |
11 | ||
12 | #include <linux/types.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/firmware.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/list.h> | |
18 | #include <linux/mutex.h> | |
19 | #include <linux/pci.h> | |
20 | #include <linux/slab.h> | |
21 | #include <linux/string.h> | |
22 | #include <linux/workqueue.h> | |
23 | #include <linux/zlib.h> | |
24 | #include <linux/hashtable.h> | |
25 | #include <linux/qed/qed_if.h> | |
c965db44 | 26 | #include "qed_debug.h" |
fe56b9e6 YM |
27 | #include "qed_hsi.h" |
28 | ||
25c089d7 | 29 | extern const struct qed_common_ops qed_common_ops_pass; |
05fafbfb | 30 | #define DRV_MODULE_VERSION "8.10.9.20" |
fe56b9e6 YM |
31 | |
32 | #define MAX_HWFNS_PER_DEVICE (4) | |
33 | #define NAME_SIZE 16 | |
34 | #define VER_SIZE 16 | |
35 | ||
bcd197c8 MC |
36 | #define QED_WFQ_UNIT 100 |
37 | ||
51ff1725 RA |
38 | #define QED_WID_SIZE (1024) |
39 | #define QED_PF_DEMS_SIZE (4) | |
40 | ||
fe56b9e6 YM |
41 | /* cau states */ |
42 | enum qed_coalescing_mode { | |
43 | QED_COAL_MODE_DISABLE, | |
44 | QED_COAL_MODE_ENABLE | |
45 | }; | |
46 | ||
47 | struct qed_eth_cb_ops; | |
48 | struct qed_dev_info; | |
6c754246 SRK |
49 | union qed_mcp_protocol_stats; |
50 | enum qed_mcp_protocol_type; | |
fe56b9e6 YM |
51 | |
52 | /* helpers */ | |
53 | static inline u32 qed_db_addr(u32 cid, u32 DEMS) | |
51ff1725 RA |
54 | { |
55 | u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | | |
56 | (cid * QED_PF_DEMS_SIZE); | |
57 | ||
58 | return db_addr; | |
59 | } | |
60 | ||
61 | static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS) | |
fe56b9e6 YM |
62 | { |
63 | u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | | |
64 | FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid); | |
65 | ||
66 | return db_addr; | |
67 | } | |
68 | ||
69 | #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \ | |
70 | ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \ | |
71 | ~((1 << (p_hwfn->cdev->cache_shift)) - 1)) | |
72 | ||
73 | #define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++) | |
74 | ||
75 | #define D_TRINE(val, cond1, cond2, true1, true2, def) \ | |
76 | (val == (cond1) ? true1 : \ | |
77 | (val == (cond2) ? true2 : def)) | |
78 | ||
79 | /* forward */ | |
80 | struct qed_ptt_pool; | |
81 | struct qed_spq; | |
82 | struct qed_sb_info; | |
83 | struct qed_sb_attn_info; | |
84 | struct qed_cxt_mngr; | |
85 | struct qed_sb_sp_info; | |
0a7fb11c | 86 | struct qed_ll2_info; |
fe56b9e6 YM |
87 | struct qed_mcp_info; |
88 | ||
89 | struct qed_rt_data { | |
fc48b7a6 YM |
90 | u32 *init_val; |
91 | bool *b_valid; | |
fe56b9e6 YM |
92 | }; |
93 | ||
464f6645 MC |
94 | enum qed_tunn_mode { |
95 | QED_MODE_L2GENEVE_TUNN, | |
96 | QED_MODE_IPGENEVE_TUNN, | |
97 | QED_MODE_L2GRE_TUNN, | |
98 | QED_MODE_IPGRE_TUNN, | |
99 | QED_MODE_VXLAN_TUNN, | |
100 | }; | |
101 | ||
102 | enum qed_tunn_clss { | |
103 | QED_TUNN_CLSS_MAC_VLAN, | |
104 | QED_TUNN_CLSS_MAC_VNI, | |
105 | QED_TUNN_CLSS_INNER_MAC_VLAN, | |
106 | QED_TUNN_CLSS_INNER_MAC_VNI, | |
107 | MAX_QED_TUNN_CLSS, | |
108 | }; | |
109 | ||
110 | struct qed_tunn_start_params { | |
111 | unsigned long tunn_mode; | |
112 | u16 vxlan_udp_port; | |
113 | u16 geneve_udp_port; | |
114 | u8 update_vxlan_udp_port; | |
115 | u8 update_geneve_udp_port; | |
116 | u8 tunn_clss_vxlan; | |
117 | u8 tunn_clss_l2geneve; | |
118 | u8 tunn_clss_ipgeneve; | |
119 | u8 tunn_clss_l2gre; | |
120 | u8 tunn_clss_ipgre; | |
121 | }; | |
122 | ||
123 | struct qed_tunn_update_params { | |
124 | unsigned long tunn_mode_update_mask; | |
125 | unsigned long tunn_mode; | |
126 | u16 vxlan_udp_port; | |
127 | u16 geneve_udp_port; | |
128 | u8 update_rx_pf_clss; | |
129 | u8 update_tx_pf_clss; | |
130 | u8 update_vxlan_udp_port; | |
131 | u8 update_geneve_udp_port; | |
132 | u8 tunn_clss_vxlan; | |
133 | u8 tunn_clss_l2geneve; | |
134 | u8 tunn_clss_ipgeneve; | |
135 | u8 tunn_clss_l2gre; | |
136 | u8 tunn_clss_ipgre; | |
137 | }; | |
138 | ||
fe56b9e6 YM |
139 | /* The PCI personality is not quite synonymous to protocol ID: |
140 | * 1. All personalities need CORE connections | |
141 | * 2. The Ethernet personality may support also the RoCE protocol | |
142 | */ | |
143 | enum qed_pci_personality { | |
144 | QED_PCI_ETH, | |
c5ac9319 YM |
145 | QED_PCI_ISCSI, |
146 | QED_PCI_ETH_ROCE, | |
fe56b9e6 YM |
147 | QED_PCI_DEFAULT /* default in shmem */ |
148 | }; | |
149 | ||
150 | /* All VFs are symmetric, all counters are PF + all VFs */ | |
151 | struct qed_qm_iids { | |
152 | u32 cids; | |
153 | u32 vf_cids; | |
154 | u32 tids; | |
155 | }; | |
156 | ||
157 | enum QED_RESOURCES { | |
158 | QED_SB, | |
25c089d7 | 159 | QED_L2_QUEUE, |
fe56b9e6 | 160 | QED_VPORT, |
25c089d7 | 161 | QED_RSS_ENG, |
fe56b9e6 YM |
162 | QED_PQ, |
163 | QED_RL, | |
25c089d7 YM |
164 | QED_MAC, |
165 | QED_VLAN, | |
51ff1725 | 166 | QED_RDMA_CNQ_RAM, |
fe56b9e6 | 167 | QED_ILT, |
0a7fb11c | 168 | QED_LL2_QUEUE, |
51ff1725 | 169 | QED_RDMA_STATS_QUEUE, |
fe56b9e6 YM |
170 | QED_MAX_RESC, |
171 | }; | |
172 | ||
25c089d7 YM |
173 | enum QED_FEATURE { |
174 | QED_PF_L2_QUE, | |
32a47e72 | 175 | QED_VF, |
51ff1725 | 176 | QED_RDMA_CNQ, |
25c089d7 YM |
177 | QED_MAX_FEATURES, |
178 | }; | |
179 | ||
cc875c2e YM |
180 | enum QED_PORT_MODE { |
181 | QED_PORT_MODE_DE_2X40G, | |
182 | QED_PORT_MODE_DE_2X50G, | |
183 | QED_PORT_MODE_DE_1X100G, | |
184 | QED_PORT_MODE_DE_4X10G_F, | |
185 | QED_PORT_MODE_DE_4X10G_E, | |
186 | QED_PORT_MODE_DE_4X20G, | |
187 | QED_PORT_MODE_DE_1X40G, | |
188 | QED_PORT_MODE_DE_2X25G, | |
189 | QED_PORT_MODE_DE_1X25G | |
190 | }; | |
191 | ||
fc48b7a6 YM |
192 | enum qed_dev_cap { |
193 | QED_DEV_CAP_ETH, | |
c5ac9319 YM |
194 | QED_DEV_CAP_ISCSI, |
195 | QED_DEV_CAP_ROCE, | |
fc48b7a6 YM |
196 | }; |
197 | ||
fe56b9e6 YM |
198 | struct qed_hw_info { |
199 | /* PCI personality */ | |
200 | enum qed_pci_personality personality; | |
201 | ||
202 | /* Resource Allocation scheme results */ | |
203 | u32 resc_start[QED_MAX_RESC]; | |
204 | u32 resc_num[QED_MAX_RESC]; | |
25c089d7 | 205 | u32 feat_num[QED_MAX_FEATURES]; |
fe56b9e6 YM |
206 | |
207 | #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) | |
208 | #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) | |
dbb799c3 YM |
209 | #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \ |
210 | RESC_NUM(_p_hwfn, resc)) | |
fe56b9e6 YM |
211 | #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) |
212 | ||
213 | u8 num_tc; | |
214 | u8 offload_tc; | |
215 | u8 non_offload_tc; | |
216 | ||
217 | u32 concrete_fid; | |
218 | u16 opaque_fid; | |
219 | u16 ovlan; | |
220 | u32 part_num[4]; | |
221 | ||
fe56b9e6 YM |
222 | unsigned char hw_mac_addr[ETH_ALEN]; |
223 | ||
224 | struct qed_igu_info *p_igu_info; | |
225 | ||
226 | u32 port_mode; | |
227 | u32 hw_mode; | |
fc48b7a6 | 228 | unsigned long device_capabilities; |
fe56b9e6 YM |
229 | }; |
230 | ||
231 | struct qed_hw_cid_data { | |
232 | u32 cid; | |
233 | bool b_cid_allocated; | |
234 | ||
235 | /* Additional identifiers */ | |
236 | u16 opaque_fid; | |
237 | u8 vport_id; | |
238 | }; | |
239 | ||
240 | /* maximun size of read/write commands (HW limit) */ | |
241 | #define DMAE_MAX_RW_SIZE 0x2000 | |
242 | ||
243 | struct qed_dmae_info { | |
244 | /* Mutex for synchronizing access to functions */ | |
245 | struct mutex mutex; | |
246 | ||
247 | u8 channel; | |
248 | ||
249 | dma_addr_t completion_word_phys_addr; | |
250 | ||
251 | /* The memory location where the DMAE writes the completion | |
252 | * value when an operation is finished on this context. | |
253 | */ | |
254 | u32 *p_completion_word; | |
255 | ||
256 | dma_addr_t intermediate_buffer_phys_addr; | |
257 | ||
258 | /* An intermediate buffer for DMAE operations that use virtual | |
259 | * addresses - data is DMA'd to/from this buffer and then | |
260 | * memcpy'd to/from the virtual address | |
261 | */ | |
262 | u32 *p_intermediate_buffer; | |
263 | ||
264 | dma_addr_t dmae_cmd_phys_addr; | |
265 | struct dmae_cmd *p_dmae_cmd; | |
266 | }; | |
267 | ||
bcd197c8 MC |
268 | struct qed_wfq_data { |
269 | /* when feature is configured for at least 1 vport */ | |
270 | u32 min_speed; | |
271 | bool configured; | |
272 | }; | |
273 | ||
fe56b9e6 YM |
274 | struct qed_qm_info { |
275 | struct init_qm_pq_params *qm_pq_params; | |
276 | struct init_qm_vport_params *qm_vport_params; | |
277 | struct init_qm_port_params *qm_port_params; | |
278 | u16 start_pq; | |
279 | u8 start_vport; | |
280 | u8 pure_lb_pq; | |
281 | u8 offload_pq; | |
282 | u8 pure_ack_pq; | |
dbb799c3 | 283 | u8 ooo_pq; |
fe56b9e6 YM |
284 | u8 vf_queues_offset; |
285 | u16 num_pqs; | |
286 | u16 num_vf_pqs; | |
287 | u8 num_vports; | |
288 | u8 max_phys_tcs_per_port; | |
289 | bool pf_rl_en; | |
290 | bool pf_wfq_en; | |
291 | bool vport_rl_en; | |
292 | bool vport_wfq_en; | |
293 | u8 pf_wfq; | |
294 | u32 pf_rl; | |
bcd197c8 | 295 | struct qed_wfq_data *wfq_data; |
dbb799c3 | 296 | u8 num_pf_rls; |
fe56b9e6 YM |
297 | }; |
298 | ||
9df2ed04 MC |
299 | struct storm_stats { |
300 | u32 address; | |
301 | u32 len; | |
302 | }; | |
303 | ||
304 | struct qed_storm_stats { | |
305 | struct storm_stats mstats; | |
306 | struct storm_stats pstats; | |
307 | struct storm_stats tstats; | |
308 | struct storm_stats ustats; | |
309 | }; | |
310 | ||
fe56b9e6 | 311 | struct qed_fw_data { |
9df2ed04 | 312 | struct fw_ver_info *fw_ver_info; |
fe56b9e6 YM |
313 | const u8 *modes_tree_buf; |
314 | union init_op *init_ops; | |
315 | const u32 *arr_data; | |
316 | u32 init_ops_size; | |
317 | }; | |
318 | ||
319 | struct qed_simd_fp_handler { | |
320 | void *token; | |
321 | void (*func)(void *); | |
322 | }; | |
323 | ||
324 | struct qed_hwfn { | |
325 | struct qed_dev *cdev; | |
326 | u8 my_id; /* ID inside the PF */ | |
327 | #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) | |
328 | u8 rel_pf_id; /* Relative to engine*/ | |
329 | u8 abs_pf_id; | |
330 | #define QED_PATH_ID(_p_hwfn) ((_p_hwfn)->abs_pf_id & 1) | |
331 | u8 port_id; | |
332 | bool b_active; | |
333 | ||
334 | u32 dp_module; | |
335 | u8 dp_level; | |
336 | char name[NAME_SIZE]; | |
337 | ||
338 | bool first_on_engine; | |
339 | bool hw_init_done; | |
340 | ||
1408cc1f | 341 | u8 num_funcs_on_engine; |
dbb799c3 | 342 | u8 enabled_func_idx; |
1408cc1f | 343 | |
fe56b9e6 YM |
344 | /* BAR access */ |
345 | void __iomem *regview; | |
346 | void __iomem *doorbells; | |
347 | u64 db_phys_addr; | |
348 | unsigned long db_size; | |
349 | ||
350 | /* PTT pool */ | |
351 | struct qed_ptt_pool *p_ptt_pool; | |
352 | ||
353 | /* HW info */ | |
354 | struct qed_hw_info hw_info; | |
355 | ||
356 | /* rt_array (for init-tool) */ | |
fc48b7a6 | 357 | struct qed_rt_data rt_data; |
fe56b9e6 YM |
358 | |
359 | /* SPQ */ | |
360 | struct qed_spq *p_spq; | |
361 | ||
362 | /* EQ */ | |
363 | struct qed_eq *p_eq; | |
364 | ||
365 | /* Consolidate Q*/ | |
366 | struct qed_consq *p_consq; | |
367 | ||
368 | /* Slow-Path definitions */ | |
369 | struct tasklet_struct *sp_dpc; | |
370 | bool b_sp_dpc_enabled; | |
371 | ||
372 | struct qed_ptt *p_main_ptt; | |
373 | struct qed_ptt *p_dpc_ptt; | |
374 | ||
375 | struct qed_sb_sp_info *p_sp_sb; | |
376 | struct qed_sb_attn_info *p_sb_attn; | |
377 | ||
378 | /* Protocol related */ | |
0a7fb11c YM |
379 | bool using_ll2; |
380 | struct qed_ll2_info *p_ll2_info; | |
51ff1725 | 381 | struct qed_rdma_info *p_rdma_info; |
fe56b9e6 YM |
382 | struct qed_pf_params pf_params; |
383 | ||
dbb799c3 YM |
384 | bool b_rdma_enabled_in_prs; |
385 | u32 rdma_prs_search_reg; | |
386 | ||
fe56b9e6 YM |
387 | /* Array of sb_info of all status blocks */ |
388 | struct qed_sb_info *sbs_info[MAX_SB_PER_PF_MIMD]; | |
389 | u16 num_sbs; | |
390 | ||
391 | struct qed_cxt_mngr *p_cxt_mngr; | |
392 | ||
393 | /* Flag indicating whether interrupts are enabled or not*/ | |
394 | bool b_int_enabled; | |
8f16bc97 | 395 | bool b_int_requested; |
fe56b9e6 | 396 | |
fc916ff2 SRK |
397 | /* True if the driver requests for the link */ |
398 | bool b_drv_link_init; | |
399 | ||
1408cc1f | 400 | struct qed_vf_iov *vf_iov_info; |
32a47e72 | 401 | struct qed_pf_iov *pf_iov_info; |
fe56b9e6 YM |
402 | struct qed_mcp_info *mcp_info; |
403 | ||
39651abd SRK |
404 | struct qed_dcbx_info *p_dcbx_info; |
405 | ||
25c089d7 YM |
406 | struct qed_hw_cid_data *p_tx_cids; |
407 | struct qed_hw_cid_data *p_rx_cids; | |
408 | ||
fe56b9e6 YM |
409 | struct qed_dmae_info dmae_info; |
410 | ||
411 | /* QM init */ | |
412 | struct qed_qm_info qm_info; | |
9df2ed04 | 413 | struct qed_storm_stats storm_stats; |
fe56b9e6 YM |
414 | |
415 | /* Buffer for unzipping firmware data */ | |
416 | void *unzip_buf; | |
417 | ||
c965db44 TT |
418 | struct dbg_tools_data dbg_info; |
419 | ||
51ff1725 RA |
420 | /* PWM region specific data */ |
421 | u32 dpi_size; | |
422 | u32 dpi_count; | |
423 | ||
424 | /* This is used to calculate the doorbell address */ | |
425 | u32 dpi_start_offset; | |
426 | ||
427 | /* If one of the following is set then EDPM shouldn't be used */ | |
428 | u8 dcbx_no_edpm; | |
429 | u8 db_bar_no_edpm; | |
430 | ||
fe56b9e6 YM |
431 | struct qed_simd_fp_handler simd_proto_handler[64]; |
432 | ||
37bff2b9 YM |
433 | #ifdef CONFIG_QED_SRIOV |
434 | struct workqueue_struct *iov_wq; | |
435 | struct delayed_work iov_task; | |
436 | unsigned long iov_task_flags; | |
437 | #endif | |
438 | ||
fe56b9e6 YM |
439 | struct z_stream_s *stream; |
440 | }; | |
441 | ||
442 | struct pci_params { | |
443 | int pm_cap; | |
444 | ||
445 | unsigned long mem_start; | |
446 | unsigned long mem_end; | |
447 | unsigned int irq; | |
448 | u8 pf_num; | |
449 | }; | |
450 | ||
451 | struct qed_int_param { | |
452 | u32 int_mode; | |
453 | u8 num_vectors; | |
454 | u8 min_msix_cnt; /* for minimal functionality */ | |
455 | }; | |
456 | ||
457 | struct qed_int_params { | |
458 | struct qed_int_param in; | |
459 | struct qed_int_param out; | |
460 | struct msix_entry *msix_table; | |
461 | bool fp_initialized; | |
462 | u8 fp_msix_base; | |
463 | u8 fp_msix_cnt; | |
51ff1725 RA |
464 | u8 rdma_msix_base; |
465 | u8 rdma_msix_cnt; | |
fe56b9e6 YM |
466 | }; |
467 | ||
c965db44 TT |
468 | struct qed_dbg_feature { |
469 | struct dentry *dentry; | |
470 | u8 *dump_buf; | |
471 | u32 buf_size; | |
472 | u32 dumped_dwords; | |
473 | }; | |
474 | ||
475 | struct qed_dbg_params { | |
476 | struct qed_dbg_feature features[DBG_FEATURE_NUM]; | |
477 | u8 engine_for_debug; | |
478 | bool print_data; | |
479 | }; | |
480 | ||
fe56b9e6 YM |
481 | struct qed_dev { |
482 | u32 dp_module; | |
483 | u8 dp_level; | |
484 | char name[NAME_SIZE]; | |
485 | ||
486 | u8 type; | |
fc48b7a6 YM |
487 | #define QED_DEV_TYPE_BB (0 << 0) |
488 | #define QED_DEV_TYPE_AH BIT(0) | |
489 | /* Translate type/revision combo into the proper conditions */ | |
490 | #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB) | |
491 | #define QED_IS_BB_A0(dev) (QED_IS_BB(dev) && \ | |
492 | CHIP_REV_IS_A0(dev)) | |
493 | #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \ | |
494 | CHIP_REV_IS_B0(dev)) | |
c965db44 TT |
495 | #define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH) |
496 | #define QED_IS_K2(dev) QED_IS_AH(dev) | |
fc48b7a6 YM |
497 | |
498 | #define QED_GET_TYPE(dev) (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \ | |
499 | QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2) | |
500 | ||
501 | u16 vendor_id; | |
502 | u16 device_id; | |
fe56b9e6 YM |
503 | |
504 | u16 chip_num; | |
505 | #define CHIP_NUM_MASK 0xffff | |
506 | #define CHIP_NUM_SHIFT 16 | |
507 | ||
508 | u16 chip_rev; | |
509 | #define CHIP_REV_MASK 0xf | |
510 | #define CHIP_REV_SHIFT 12 | |
fc48b7a6 YM |
511 | #define CHIP_REV_IS_A0(_cdev) (!(_cdev)->chip_rev) |
512 | #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1) | |
fe56b9e6 YM |
513 | |
514 | u16 chip_metal; | |
515 | #define CHIP_METAL_MASK 0xff | |
516 | #define CHIP_METAL_SHIFT 4 | |
517 | ||
518 | u16 chip_bond_id; | |
519 | #define CHIP_BOND_ID_MASK 0xf | |
520 | #define CHIP_BOND_ID_SHIFT 0 | |
521 | ||
522 | u8 num_engines; | |
523 | u8 num_ports_in_engines; | |
524 | u8 num_funcs_in_port; | |
525 | ||
526 | u8 path_id; | |
fc48b7a6 YM |
527 | enum qed_mf_mode mf_mode; |
528 | #define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT) | |
529 | #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR) | |
530 | #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN) | |
fe56b9e6 YM |
531 | |
532 | int pcie_width; | |
533 | int pcie_speed; | |
534 | u8 ver_str[VER_SIZE]; | |
535 | ||
536 | /* Add MF related configuration */ | |
537 | u8 mcp_rev; | |
538 | u8 boot_mode; | |
539 | ||
540 | u8 wol; | |
541 | ||
542 | u32 int_mode; | |
543 | enum qed_coalescing_mode int_coalescing_mode; | |
51d99880 SRK |
544 | u16 rx_coalesce_usecs; |
545 | u16 tx_coalesce_usecs; | |
fe56b9e6 YM |
546 | |
547 | /* Start Bar offset of first hwfn */ | |
548 | void __iomem *regview; | |
549 | void __iomem *doorbells; | |
550 | u64 db_phys_addr; | |
551 | unsigned long db_size; | |
552 | ||
553 | /* PCI */ | |
554 | u8 cache_shift; | |
555 | ||
556 | /* Init */ | |
557 | const struct iro *iro_arr; | |
558 | #define IRO (p_hwfn->cdev->iro_arr) | |
559 | ||
560 | /* HW functions */ | |
561 | u8 num_hwfns; | |
562 | struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; | |
563 | ||
32a47e72 YM |
564 | /* SRIOV */ |
565 | struct qed_hw_sriov_info *p_iov_info; | |
566 | #define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info) | |
567 | ||
464f6645 | 568 | unsigned long tunn_mode; |
1408cc1f YM |
569 | |
570 | bool b_is_vf; | |
fe56b9e6 | 571 | u32 drv_type; |
fe56b9e6 YM |
572 | struct qed_eth_stats *reset_stats; |
573 | struct qed_fw_data *fw_data; | |
574 | ||
575 | u32 mcp_nvm_resp; | |
576 | ||
577 | /* Linux specific here */ | |
578 | struct qede_dev *edev; | |
579 | struct pci_dev *pdev; | |
580 | int msg_enable; | |
581 | ||
582 | struct pci_params pci_params; | |
583 | ||
584 | struct qed_int_params int_params; | |
585 | ||
586 | u8 protocol; | |
587 | #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH) | |
588 | ||
cc875c2e YM |
589 | /* Callbacks to protocol driver */ |
590 | union { | |
591 | struct qed_common_cb_ops *common; | |
592 | struct qed_eth_cb_ops *eth; | |
593 | } protocol_ops; | |
594 | void *ops_cookie; | |
595 | ||
c965db44 TT |
596 | struct qed_dbg_params dbg_params; |
597 | ||
0a7fb11c YM |
598 | #ifdef CONFIG_QED_LL2 |
599 | struct qed_cb_ll2_info *ll2; | |
600 | u8 ll2_mac_address[ETH_ALEN]; | |
601 | #endif | |
602 | ||
fe56b9e6 | 603 | const struct firmware *firmware; |
51ff1725 RA |
604 | |
605 | u32 rdma_max_sge; | |
606 | u32 rdma_max_inline; | |
607 | u32 rdma_max_srq_sge; | |
fe56b9e6 YM |
608 | }; |
609 | ||
32a47e72 | 610 | #define NUM_OF_VFS(dev) MAX_NUM_VFS_BB |
dacd88d6 | 611 | #define NUM_OF_L2_QUEUES(dev) MAX_NUM_L2_QUEUES_BB |
fe56b9e6 YM |
612 | #define NUM_OF_SBS(dev) MAX_SB_PER_PATH_BB |
613 | #define NUM_OF_ENG_PFS(dev) MAX_NUM_PFS_BB | |
614 | ||
615 | /** | |
616 | * @brief qed_concrete_to_sw_fid - get the sw function id from | |
617 | * the concrete value. | |
618 | * | |
619 | * @param concrete_fid | |
620 | * | |
621 | * @return inline u8 | |
622 | */ | |
623 | static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev, | |
624 | u32 concrete_fid) | |
625 | { | |
4870e704 | 626 | u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); |
fe56b9e6 | 627 | u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); |
4870e704 YM |
628 | u8 vf_valid = GET_FIELD(concrete_fid, |
629 | PXP_CONCRETE_FID_VFVALID); | |
630 | u8 sw_fid; | |
fe56b9e6 | 631 | |
4870e704 YM |
632 | if (vf_valid) |
633 | sw_fid = vfid + MAX_NUM_PFS; | |
634 | else | |
635 | sw_fid = pfid; | |
636 | ||
637 | return sw_fid; | |
fe56b9e6 YM |
638 | } |
639 | ||
640 | #define PURE_LB_TC 8 | |
dbb799c3 | 641 | #define OOO_LB_TC 9 |
fe56b9e6 | 642 | |
733def6a | 643 | int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate); |
bcd197c8 MC |
644 | void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate); |
645 | ||
733def6a | 646 | void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); |
fe56b9e6 YM |
647 | #define QED_LEADING_HWFN(dev) (&dev->hwfns[0]) |
648 | ||
649 | /* Other Linux specific common definitions */ | |
650 | #define DP_NAME(cdev) ((cdev)->name) | |
651 | ||
652 | #define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\ | |
653 | (cdev->regview) + \ | |
654 | (offset)) | |
655 | ||
656 | #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset)) | |
657 | #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset)) | |
658 | #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset)) | |
659 | ||
660 | #define DOORBELL(cdev, db_addr, val) \ | |
661 | writel((u32)val, (void __iomem *)((u8 __iomem *)\ | |
662 | (cdev->doorbells) + (db_addr))) | |
663 | ||
664 | /* Prototypes */ | |
665 | int qed_fill_dev_info(struct qed_dev *cdev, | |
666 | struct qed_dev_info *dev_info); | |
cc875c2e | 667 | void qed_link_update(struct qed_hwfn *hwfn); |
fe56b9e6 YM |
668 | u32 qed_unzip_data(struct qed_hwfn *p_hwfn, |
669 | u32 input_len, u8 *input_buf, | |
670 | u32 max_size, u8 *unzip_buf); | |
6c754246 SRK |
671 | void qed_get_protocol_stats(struct qed_dev *cdev, |
672 | enum qed_mcp_protocol_type type, | |
673 | union qed_mcp_protocol_stats *stats); | |
8f16bc97 SK |
674 | int qed_slowpath_irq_req(struct qed_hwfn *hwfn); |
675 | ||
fe56b9e6 | 676 | #endif /* _QED_H */ |