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fe56b9e6 | 1 | /* QLogic qed NIC Driver |
e8f1cb50 | 2 | * Copyright (c) 2015-2017 QLogic Corporation |
fe56b9e6 | 3 | * |
e8f1cb50 MY |
4 | * This software is available to you under a choice of one of two |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and /or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
fe56b9e6 YM |
31 | */ |
32 | ||
33 | #ifndef _QED_H | |
34 | #define _QED_H | |
35 | ||
36 | #include <linux/types.h> | |
37 | #include <linux/io.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/firmware.h> | |
40 | #include <linux/interrupt.h> | |
41 | #include <linux/list.h> | |
42 | #include <linux/mutex.h> | |
43 | #include <linux/pci.h> | |
44 | #include <linux/slab.h> | |
45 | #include <linux/string.h> | |
46 | #include <linux/workqueue.h> | |
47 | #include <linux/zlib.h> | |
48 | #include <linux/hashtable.h> | |
49 | #include <linux/qed/qed_if.h> | |
c965db44 | 50 | #include "qed_debug.h" |
fe56b9e6 YM |
51 | #include "qed_hsi.h" |
52 | ||
25c089d7 | 53 | extern const struct qed_common_ops qed_common_ops_pass; |
5d24bcf1 TT |
54 | |
55 | #define QED_MAJOR_VERSION 8 | |
56 | #define QED_MINOR_VERSION 10 | |
57 | #define QED_REVISION_VERSION 10 | |
58 | #define QED_ENGINEERING_VERSION 21 | |
59 | ||
60 | #define QED_VERSION \ | |
61 | ((QED_MAJOR_VERSION << 24) | (QED_MINOR_VERSION << 16) | \ | |
62 | (QED_REVISION_VERSION << 8) | QED_ENGINEERING_VERSION) | |
63 | ||
64 | #define STORM_FW_VERSION \ | |
65 | ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \ | |
66 | (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION) | |
fe56b9e6 YM |
67 | |
68 | #define MAX_HWFNS_PER_DEVICE (4) | |
69 | #define NAME_SIZE 16 | |
70 | #define VER_SIZE 16 | |
71 | ||
bcd197c8 MC |
72 | #define QED_WFQ_UNIT 100 |
73 | ||
fc831825 | 74 | #define ISCSI_BDQ_ID(_port_id) (_port_id) |
1e128c81 | 75 | #define FCOE_BDQ_ID(_port_id) ((_port_id) + 2) |
51ff1725 RA |
76 | #define QED_WID_SIZE (1024) |
77 | #define QED_PF_DEMS_SIZE (4) | |
78 | ||
fe56b9e6 YM |
79 | /* cau states */ |
80 | enum qed_coalescing_mode { | |
81 | QED_COAL_MODE_DISABLE, | |
82 | QED_COAL_MODE_ENABLE | |
83 | }; | |
84 | ||
85 | struct qed_eth_cb_ops; | |
86 | struct qed_dev_info; | |
6c754246 SRK |
87 | union qed_mcp_protocol_stats; |
88 | enum qed_mcp_protocol_type; | |
fe56b9e6 YM |
89 | |
90 | /* helpers */ | |
5d24bcf1 TT |
91 | #define QED_MFW_GET_FIELD(name, field) \ |
92 | (((name) & (field ## _MASK)) >> (field ## _SHIFT)) | |
93 | ||
94 | #define QED_MFW_SET_FIELD(name, field, value) \ | |
95 | do { \ | |
96 | (name) &= ~((field ## _MASK) << (field ## _SHIFT)); \ | |
97 | (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK));\ | |
98 | } while (0) | |
99 | ||
fe56b9e6 | 100 | static inline u32 qed_db_addr(u32 cid, u32 DEMS) |
51ff1725 RA |
101 | { |
102 | u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | | |
103 | (cid * QED_PF_DEMS_SIZE); | |
104 | ||
105 | return db_addr; | |
106 | } | |
107 | ||
108 | static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS) | |
fe56b9e6 YM |
109 | { |
110 | u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | | |
111 | FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid); | |
112 | ||
113 | return db_addr; | |
114 | } | |
115 | ||
116 | #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \ | |
117 | ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \ | |
118 | ~((1 << (p_hwfn->cdev->cache_shift)) - 1)) | |
119 | ||
120 | #define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++) | |
121 | ||
122 | #define D_TRINE(val, cond1, cond2, true1, true2, def) \ | |
123 | (val == (cond1) ? true1 : \ | |
124 | (val == (cond2) ? true2 : def)) | |
125 | ||
126 | /* forward */ | |
127 | struct qed_ptt_pool; | |
128 | struct qed_spq; | |
129 | struct qed_sb_info; | |
130 | struct qed_sb_attn_info; | |
131 | struct qed_cxt_mngr; | |
132 | struct qed_sb_sp_info; | |
0a7fb11c | 133 | struct qed_ll2_info; |
fe56b9e6 YM |
134 | struct qed_mcp_info; |
135 | ||
136 | struct qed_rt_data { | |
fc48b7a6 YM |
137 | u32 *init_val; |
138 | bool *b_valid; | |
fe56b9e6 YM |
139 | }; |
140 | ||
464f6645 MC |
141 | enum qed_tunn_mode { |
142 | QED_MODE_L2GENEVE_TUNN, | |
143 | QED_MODE_IPGENEVE_TUNN, | |
144 | QED_MODE_L2GRE_TUNN, | |
145 | QED_MODE_IPGRE_TUNN, | |
146 | QED_MODE_VXLAN_TUNN, | |
147 | }; | |
148 | ||
149 | enum qed_tunn_clss { | |
150 | QED_TUNN_CLSS_MAC_VLAN, | |
151 | QED_TUNN_CLSS_MAC_VNI, | |
152 | QED_TUNN_CLSS_INNER_MAC_VLAN, | |
153 | QED_TUNN_CLSS_INNER_MAC_VNI, | |
154 | MAX_QED_TUNN_CLSS, | |
155 | }; | |
156 | ||
157 | struct qed_tunn_start_params { | |
158 | unsigned long tunn_mode; | |
159 | u16 vxlan_udp_port; | |
160 | u16 geneve_udp_port; | |
161 | u8 update_vxlan_udp_port; | |
162 | u8 update_geneve_udp_port; | |
163 | u8 tunn_clss_vxlan; | |
164 | u8 tunn_clss_l2geneve; | |
165 | u8 tunn_clss_ipgeneve; | |
166 | u8 tunn_clss_l2gre; | |
167 | u8 tunn_clss_ipgre; | |
168 | }; | |
169 | ||
170 | struct qed_tunn_update_params { | |
171 | unsigned long tunn_mode_update_mask; | |
172 | unsigned long tunn_mode; | |
173 | u16 vxlan_udp_port; | |
174 | u16 geneve_udp_port; | |
175 | u8 update_rx_pf_clss; | |
176 | u8 update_tx_pf_clss; | |
177 | u8 update_vxlan_udp_port; | |
178 | u8 update_geneve_udp_port; | |
179 | u8 tunn_clss_vxlan; | |
180 | u8 tunn_clss_l2geneve; | |
181 | u8 tunn_clss_ipgeneve; | |
182 | u8 tunn_clss_l2gre; | |
183 | u8 tunn_clss_ipgre; | |
184 | }; | |
185 | ||
fe56b9e6 YM |
186 | /* The PCI personality is not quite synonymous to protocol ID: |
187 | * 1. All personalities need CORE connections | |
188 | * 2. The Ethernet personality may support also the RoCE protocol | |
189 | */ | |
190 | enum qed_pci_personality { | |
191 | QED_PCI_ETH, | |
1e128c81 | 192 | QED_PCI_FCOE, |
c5ac9319 YM |
193 | QED_PCI_ISCSI, |
194 | QED_PCI_ETH_ROCE, | |
fe56b9e6 YM |
195 | QED_PCI_DEFAULT /* default in shmem */ |
196 | }; | |
197 | ||
198 | /* All VFs are symmetric, all counters are PF + all VFs */ | |
199 | struct qed_qm_iids { | |
200 | u32 cids; | |
201 | u32 vf_cids; | |
202 | u32 tids; | |
203 | }; | |
204 | ||
2edbff8d TT |
205 | /* HW / FW resources, output of features supported below, most information |
206 | * is received from MFW. | |
207 | */ | |
208 | enum qed_resources { | |
fe56b9e6 | 209 | QED_SB, |
25c089d7 | 210 | QED_L2_QUEUE, |
fe56b9e6 | 211 | QED_VPORT, |
25c089d7 | 212 | QED_RSS_ENG, |
fe56b9e6 YM |
213 | QED_PQ, |
214 | QED_RL, | |
25c089d7 YM |
215 | QED_MAC, |
216 | QED_VLAN, | |
51ff1725 | 217 | QED_RDMA_CNQ_RAM, |
fe56b9e6 | 218 | QED_ILT, |
0a7fb11c | 219 | QED_LL2_QUEUE, |
2edbff8d | 220 | QED_CMDQS_CQS, |
51ff1725 | 221 | QED_RDMA_STATS_QUEUE, |
fe56b9e6 YM |
222 | QED_MAX_RESC, |
223 | }; | |
224 | ||
25c089d7 YM |
225 | enum QED_FEATURE { |
226 | QED_PF_L2_QUE, | |
32a47e72 | 227 | QED_VF, |
51ff1725 | 228 | QED_RDMA_CNQ, |
5a1f965a | 229 | QED_VF_L2_QUE, |
1e128c81 | 230 | QED_FCOE_CQ, |
25c089d7 YM |
231 | QED_MAX_FEATURES, |
232 | }; | |
233 | ||
cc875c2e YM |
234 | enum QED_PORT_MODE { |
235 | QED_PORT_MODE_DE_2X40G, | |
236 | QED_PORT_MODE_DE_2X50G, | |
237 | QED_PORT_MODE_DE_1X100G, | |
238 | QED_PORT_MODE_DE_4X10G_F, | |
239 | QED_PORT_MODE_DE_4X10G_E, | |
240 | QED_PORT_MODE_DE_4X20G, | |
241 | QED_PORT_MODE_DE_1X40G, | |
242 | QED_PORT_MODE_DE_2X25G, | |
9c79ddaa MY |
243 | QED_PORT_MODE_DE_1X25G, |
244 | QED_PORT_MODE_DE_4X25G, | |
245 | QED_PORT_MODE_DE_2X10G, | |
cc875c2e YM |
246 | }; |
247 | ||
fc48b7a6 YM |
248 | enum qed_dev_cap { |
249 | QED_DEV_CAP_ETH, | |
1e128c81 | 250 | QED_DEV_CAP_FCOE, |
c5ac9319 YM |
251 | QED_DEV_CAP_ISCSI, |
252 | QED_DEV_CAP_ROCE, | |
fc48b7a6 YM |
253 | }; |
254 | ||
14d39648 MY |
255 | enum qed_wol_support { |
256 | QED_WOL_SUPPORT_NONE, | |
257 | QED_WOL_SUPPORT_PME, | |
258 | }; | |
259 | ||
fe56b9e6 YM |
260 | struct qed_hw_info { |
261 | /* PCI personality */ | |
262 | enum qed_pci_personality personality; | |
263 | ||
264 | /* Resource Allocation scheme results */ | |
265 | u32 resc_start[QED_MAX_RESC]; | |
266 | u32 resc_num[QED_MAX_RESC]; | |
25c089d7 | 267 | u32 feat_num[QED_MAX_FEATURES]; |
fe56b9e6 YM |
268 | |
269 | #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) | |
270 | #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) | |
dbb799c3 YM |
271 | #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \ |
272 | RESC_NUM(_p_hwfn, resc)) | |
fe56b9e6 YM |
273 | #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) |
274 | ||
275 | u8 num_tc; | |
276 | u8 offload_tc; | |
277 | u8 non_offload_tc; | |
278 | ||
279 | u32 concrete_fid; | |
280 | u16 opaque_fid; | |
281 | u16 ovlan; | |
282 | u32 part_num[4]; | |
283 | ||
fe56b9e6 | 284 | unsigned char hw_mac_addr[ETH_ALEN]; |
1e128c81 AE |
285 | u64 node_wwn; |
286 | u64 port_wwn; | |
287 | ||
288 | u16 num_fcoe_conns; | |
fe56b9e6 YM |
289 | |
290 | struct qed_igu_info *p_igu_info; | |
291 | ||
292 | u32 port_mode; | |
293 | u32 hw_mode; | |
fc48b7a6 | 294 | unsigned long device_capabilities; |
0fefbfba | 295 | u16 mtu; |
14d39648 MY |
296 | |
297 | enum qed_wol_support b_wol_support; | |
fe56b9e6 YM |
298 | }; |
299 | ||
fe56b9e6 YM |
300 | /* maximun size of read/write commands (HW limit) */ |
301 | #define DMAE_MAX_RW_SIZE 0x2000 | |
302 | ||
303 | struct qed_dmae_info { | |
304 | /* Mutex for synchronizing access to functions */ | |
305 | struct mutex mutex; | |
306 | ||
307 | u8 channel; | |
308 | ||
309 | dma_addr_t completion_word_phys_addr; | |
310 | ||
311 | /* The memory location where the DMAE writes the completion | |
312 | * value when an operation is finished on this context. | |
313 | */ | |
314 | u32 *p_completion_word; | |
315 | ||
316 | dma_addr_t intermediate_buffer_phys_addr; | |
317 | ||
318 | /* An intermediate buffer for DMAE operations that use virtual | |
319 | * addresses - data is DMA'd to/from this buffer and then | |
320 | * memcpy'd to/from the virtual address | |
321 | */ | |
322 | u32 *p_intermediate_buffer; | |
323 | ||
324 | dma_addr_t dmae_cmd_phys_addr; | |
325 | struct dmae_cmd *p_dmae_cmd; | |
326 | }; | |
327 | ||
bcd197c8 MC |
328 | struct qed_wfq_data { |
329 | /* when feature is configured for at least 1 vport */ | |
330 | u32 min_speed; | |
331 | bool configured; | |
332 | }; | |
333 | ||
fe56b9e6 YM |
334 | struct qed_qm_info { |
335 | struct init_qm_pq_params *qm_pq_params; | |
336 | struct init_qm_vport_params *qm_vport_params; | |
337 | struct init_qm_port_params *qm_port_params; | |
338 | u16 start_pq; | |
339 | u8 start_vport; | |
340 | u8 pure_lb_pq; | |
341 | u8 offload_pq; | |
342 | u8 pure_ack_pq; | |
dbb799c3 | 343 | u8 ooo_pq; |
fe56b9e6 YM |
344 | u8 vf_queues_offset; |
345 | u16 num_pqs; | |
346 | u16 num_vf_pqs; | |
347 | u8 num_vports; | |
348 | u8 max_phys_tcs_per_port; | |
349 | bool pf_rl_en; | |
350 | bool pf_wfq_en; | |
351 | bool vport_rl_en; | |
352 | bool vport_wfq_en; | |
353 | u8 pf_wfq; | |
354 | u32 pf_rl; | |
bcd197c8 | 355 | struct qed_wfq_data *wfq_data; |
dbb799c3 | 356 | u8 num_pf_rls; |
fe56b9e6 YM |
357 | }; |
358 | ||
9df2ed04 MC |
359 | struct storm_stats { |
360 | u32 address; | |
361 | u32 len; | |
362 | }; | |
363 | ||
364 | struct qed_storm_stats { | |
365 | struct storm_stats mstats; | |
366 | struct storm_stats pstats; | |
367 | struct storm_stats tstats; | |
368 | struct storm_stats ustats; | |
369 | }; | |
370 | ||
fe56b9e6 | 371 | struct qed_fw_data { |
9df2ed04 | 372 | struct fw_ver_info *fw_ver_info; |
fe56b9e6 YM |
373 | const u8 *modes_tree_buf; |
374 | union init_op *init_ops; | |
375 | const u32 *arr_data; | |
376 | u32 init_ops_size; | |
377 | }; | |
378 | ||
5d24bcf1 TT |
379 | #define DRV_MODULE_VERSION \ |
380 | __stringify(QED_MAJOR_VERSION) "." \ | |
381 | __stringify(QED_MINOR_VERSION) "." \ | |
382 | __stringify(QED_REVISION_VERSION) "." \ | |
383 | __stringify(QED_ENGINEERING_VERSION) | |
384 | ||
fe56b9e6 YM |
385 | struct qed_simd_fp_handler { |
386 | void *token; | |
387 | void (*func)(void *); | |
388 | }; | |
389 | ||
390 | struct qed_hwfn { | |
391 | struct qed_dev *cdev; | |
392 | u8 my_id; /* ID inside the PF */ | |
393 | #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) | |
394 | u8 rel_pf_id; /* Relative to engine*/ | |
395 | u8 abs_pf_id; | |
9c79ddaa MY |
396 | #define QED_PATH_ID(_p_hwfn) \ |
397 | (QED_IS_K2((_p_hwfn)->cdev) ? 0 : ((_p_hwfn)->abs_pf_id & 1)) | |
fe56b9e6 YM |
398 | u8 port_id; |
399 | bool b_active; | |
400 | ||
401 | u32 dp_module; | |
402 | u8 dp_level; | |
403 | char name[NAME_SIZE]; | |
404 | ||
405 | bool first_on_engine; | |
406 | bool hw_init_done; | |
407 | ||
1408cc1f | 408 | u8 num_funcs_on_engine; |
dbb799c3 | 409 | u8 enabled_func_idx; |
1408cc1f | 410 | |
fe56b9e6 YM |
411 | /* BAR access */ |
412 | void __iomem *regview; | |
413 | void __iomem *doorbells; | |
414 | u64 db_phys_addr; | |
415 | unsigned long db_size; | |
416 | ||
417 | /* PTT pool */ | |
418 | struct qed_ptt_pool *p_ptt_pool; | |
419 | ||
420 | /* HW info */ | |
421 | struct qed_hw_info hw_info; | |
422 | ||
423 | /* rt_array (for init-tool) */ | |
fc48b7a6 | 424 | struct qed_rt_data rt_data; |
fe56b9e6 YM |
425 | |
426 | /* SPQ */ | |
427 | struct qed_spq *p_spq; | |
428 | ||
429 | /* EQ */ | |
430 | struct qed_eq *p_eq; | |
431 | ||
432 | /* Consolidate Q*/ | |
433 | struct qed_consq *p_consq; | |
434 | ||
435 | /* Slow-Path definitions */ | |
436 | struct tasklet_struct *sp_dpc; | |
437 | bool b_sp_dpc_enabled; | |
438 | ||
439 | struct qed_ptt *p_main_ptt; | |
440 | struct qed_ptt *p_dpc_ptt; | |
441 | ||
442 | struct qed_sb_sp_info *p_sp_sb; | |
443 | struct qed_sb_attn_info *p_sb_attn; | |
444 | ||
445 | /* Protocol related */ | |
0a7fb11c YM |
446 | bool using_ll2; |
447 | struct qed_ll2_info *p_ll2_info; | |
1d6cff4f | 448 | struct qed_ooo_info *p_ooo_info; |
51ff1725 | 449 | struct qed_rdma_info *p_rdma_info; |
fc831825 | 450 | struct qed_iscsi_info *p_iscsi_info; |
1e128c81 | 451 | struct qed_fcoe_info *p_fcoe_info; |
fe56b9e6 YM |
452 | struct qed_pf_params pf_params; |
453 | ||
dbb799c3 YM |
454 | bool b_rdma_enabled_in_prs; |
455 | u32 rdma_prs_search_reg; | |
456 | ||
fe56b9e6 YM |
457 | /* Array of sb_info of all status blocks */ |
458 | struct qed_sb_info *sbs_info[MAX_SB_PER_PF_MIMD]; | |
459 | u16 num_sbs; | |
460 | ||
461 | struct qed_cxt_mngr *p_cxt_mngr; | |
462 | ||
463 | /* Flag indicating whether interrupts are enabled or not*/ | |
464 | bool b_int_enabled; | |
8f16bc97 | 465 | bool b_int_requested; |
fe56b9e6 | 466 | |
fc916ff2 SRK |
467 | /* True if the driver requests for the link */ |
468 | bool b_drv_link_init; | |
469 | ||
1408cc1f | 470 | struct qed_vf_iov *vf_iov_info; |
32a47e72 | 471 | struct qed_pf_iov *pf_iov_info; |
fe56b9e6 YM |
472 | struct qed_mcp_info *mcp_info; |
473 | ||
39651abd SRK |
474 | struct qed_dcbx_info *p_dcbx_info; |
475 | ||
fe56b9e6 YM |
476 | struct qed_dmae_info dmae_info; |
477 | ||
478 | /* QM init */ | |
479 | struct qed_qm_info qm_info; | |
9df2ed04 | 480 | struct qed_storm_stats storm_stats; |
fe56b9e6 YM |
481 | |
482 | /* Buffer for unzipping firmware data */ | |
483 | void *unzip_buf; | |
484 | ||
c965db44 TT |
485 | struct dbg_tools_data dbg_info; |
486 | ||
51ff1725 RA |
487 | /* PWM region specific data */ |
488 | u32 dpi_size; | |
489 | u32 dpi_count; | |
490 | ||
491 | /* This is used to calculate the doorbell address */ | |
492 | u32 dpi_start_offset; | |
493 | ||
494 | /* If one of the following is set then EDPM shouldn't be used */ | |
495 | u8 dcbx_no_edpm; | |
496 | u8 db_bar_no_edpm; | |
497 | ||
c78c70fa SRK |
498 | /* p_ptp_ptt is valid for leading HWFN only */ |
499 | struct qed_ptt *p_ptp_ptt; | |
fe56b9e6 YM |
500 | struct qed_simd_fp_handler simd_proto_handler[64]; |
501 | ||
37bff2b9 YM |
502 | #ifdef CONFIG_QED_SRIOV |
503 | struct workqueue_struct *iov_wq; | |
504 | struct delayed_work iov_task; | |
505 | unsigned long iov_task_flags; | |
506 | #endif | |
507 | ||
fe56b9e6 | 508 | struct z_stream_s *stream; |
abd49676 | 509 | struct qed_roce_ll2_info *ll2; |
fe56b9e6 YM |
510 | }; |
511 | ||
512 | struct pci_params { | |
513 | int pm_cap; | |
514 | ||
515 | unsigned long mem_start; | |
516 | unsigned long mem_end; | |
517 | unsigned int irq; | |
518 | u8 pf_num; | |
519 | }; | |
520 | ||
521 | struct qed_int_param { | |
522 | u32 int_mode; | |
523 | u8 num_vectors; | |
524 | u8 min_msix_cnt; /* for minimal functionality */ | |
525 | }; | |
526 | ||
527 | struct qed_int_params { | |
528 | struct qed_int_param in; | |
529 | struct qed_int_param out; | |
530 | struct msix_entry *msix_table; | |
531 | bool fp_initialized; | |
532 | u8 fp_msix_base; | |
533 | u8 fp_msix_cnt; | |
51ff1725 RA |
534 | u8 rdma_msix_base; |
535 | u8 rdma_msix_cnt; | |
fe56b9e6 YM |
536 | }; |
537 | ||
c965db44 TT |
538 | struct qed_dbg_feature { |
539 | struct dentry *dentry; | |
540 | u8 *dump_buf; | |
541 | u32 buf_size; | |
542 | u32 dumped_dwords; | |
543 | }; | |
544 | ||
545 | struct qed_dbg_params { | |
546 | struct qed_dbg_feature features[DBG_FEATURE_NUM]; | |
547 | u8 engine_for_debug; | |
548 | bool print_data; | |
549 | }; | |
550 | ||
fe56b9e6 YM |
551 | struct qed_dev { |
552 | u32 dp_module; | |
553 | u8 dp_level; | |
554 | char name[NAME_SIZE]; | |
555 | ||
9c79ddaa | 556 | enum qed_dev_type type; |
fc48b7a6 YM |
557 | /* Translate type/revision combo into the proper conditions */ |
558 | #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB) | |
559 | #define QED_IS_BB_A0(dev) (QED_IS_BB(dev) && \ | |
560 | CHIP_REV_IS_A0(dev)) | |
561 | #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \ | |
562 | CHIP_REV_IS_B0(dev)) | |
c965db44 TT |
563 | #define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH) |
564 | #define QED_IS_K2(dev) QED_IS_AH(dev) | |
fc48b7a6 YM |
565 | |
566 | #define QED_GET_TYPE(dev) (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \ | |
567 | QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2) | |
568 | ||
569 | u16 vendor_id; | |
570 | u16 device_id; | |
9c79ddaa MY |
571 | #define QED_DEV_ID_MASK 0xff00 |
572 | #define QED_DEV_ID_MASK_BB 0x1600 | |
573 | #define QED_DEV_ID_MASK_AH 0x8000 | |
fe56b9e6 YM |
574 | |
575 | u16 chip_num; | |
576 | #define CHIP_NUM_MASK 0xffff | |
577 | #define CHIP_NUM_SHIFT 16 | |
578 | ||
579 | u16 chip_rev; | |
580 | #define CHIP_REV_MASK 0xf | |
581 | #define CHIP_REV_SHIFT 12 | |
fc48b7a6 YM |
582 | #define CHIP_REV_IS_A0(_cdev) (!(_cdev)->chip_rev) |
583 | #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1) | |
fe56b9e6 YM |
584 | |
585 | u16 chip_metal; | |
586 | #define CHIP_METAL_MASK 0xff | |
587 | #define CHIP_METAL_SHIFT 4 | |
588 | ||
589 | u16 chip_bond_id; | |
590 | #define CHIP_BOND_ID_MASK 0xf | |
591 | #define CHIP_BOND_ID_SHIFT 0 | |
592 | ||
593 | u8 num_engines; | |
594 | u8 num_ports_in_engines; | |
595 | u8 num_funcs_in_port; | |
596 | ||
597 | u8 path_id; | |
fc48b7a6 YM |
598 | enum qed_mf_mode mf_mode; |
599 | #define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT) | |
600 | #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR) | |
601 | #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN) | |
fe56b9e6 YM |
602 | |
603 | int pcie_width; | |
604 | int pcie_speed; | |
605 | u8 ver_str[VER_SIZE]; | |
606 | ||
607 | /* Add MF related configuration */ | |
608 | u8 mcp_rev; | |
609 | u8 boot_mode; | |
610 | ||
14d39648 MY |
611 | /* WoL related configurations */ |
612 | u8 wol_config; | |
613 | u8 wol_mac[ETH_ALEN]; | |
fe56b9e6 YM |
614 | |
615 | u32 int_mode; | |
616 | enum qed_coalescing_mode int_coalescing_mode; | |
51d99880 SRK |
617 | u16 rx_coalesce_usecs; |
618 | u16 tx_coalesce_usecs; | |
fe56b9e6 YM |
619 | |
620 | /* Start Bar offset of first hwfn */ | |
621 | void __iomem *regview; | |
622 | void __iomem *doorbells; | |
623 | u64 db_phys_addr; | |
624 | unsigned long db_size; | |
625 | ||
626 | /* PCI */ | |
627 | u8 cache_shift; | |
628 | ||
629 | /* Init */ | |
630 | const struct iro *iro_arr; | |
631 | #define IRO (p_hwfn->cdev->iro_arr) | |
632 | ||
633 | /* HW functions */ | |
634 | u8 num_hwfns; | |
635 | struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; | |
636 | ||
32a47e72 YM |
637 | /* SRIOV */ |
638 | struct qed_hw_sriov_info *p_iov_info; | |
639 | #define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info) | |
640 | ||
464f6645 | 641 | unsigned long tunn_mode; |
1408cc1f YM |
642 | |
643 | bool b_is_vf; | |
fe56b9e6 | 644 | u32 drv_type; |
fe56b9e6 YM |
645 | struct qed_eth_stats *reset_stats; |
646 | struct qed_fw_data *fw_data; | |
647 | ||
648 | u32 mcp_nvm_resp; | |
649 | ||
650 | /* Linux specific here */ | |
651 | struct qede_dev *edev; | |
652 | struct pci_dev *pdev; | |
fc831825 YM |
653 | u32 flags; |
654 | #define QED_FLAG_STORAGE_STARTED (BIT(0)) | |
fe56b9e6 YM |
655 | int msg_enable; |
656 | ||
657 | struct pci_params pci_params; | |
658 | ||
659 | struct qed_int_params int_params; | |
660 | ||
661 | u8 protocol; | |
662 | #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH) | |
1e128c81 | 663 | #define IS_QED_FCOE_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_FCOE) |
fe56b9e6 | 664 | |
cc875c2e YM |
665 | /* Callbacks to protocol driver */ |
666 | union { | |
667 | struct qed_common_cb_ops *common; | |
668 | struct qed_eth_cb_ops *eth; | |
1e128c81 | 669 | struct qed_fcoe_cb_ops *fcoe; |
fc831825 | 670 | struct qed_iscsi_cb_ops *iscsi; |
cc875c2e YM |
671 | } protocol_ops; |
672 | void *ops_cookie; | |
673 | ||
c965db44 TT |
674 | struct qed_dbg_params dbg_params; |
675 | ||
0a7fb11c YM |
676 | #ifdef CONFIG_QED_LL2 |
677 | struct qed_cb_ll2_info *ll2; | |
678 | u8 ll2_mac_address[ETH_ALEN]; | |
679 | #endif | |
fc831825 | 680 | DECLARE_HASHTABLE(connections, 10); |
fe56b9e6 | 681 | const struct firmware *firmware; |
51ff1725 RA |
682 | |
683 | u32 rdma_max_sge; | |
684 | u32 rdma_max_inline; | |
685 | u32 rdma_max_srq_sge; | |
fe56b9e6 YM |
686 | }; |
687 | ||
9c79ddaa MY |
688 | #define NUM_OF_VFS(dev) (QED_IS_BB(dev) ? MAX_NUM_VFS_BB \ |
689 | : MAX_NUM_VFS_K2) | |
690 | #define NUM_OF_L2_QUEUES(dev) (QED_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \ | |
691 | : MAX_NUM_L2_QUEUES_K2) | |
692 | #define NUM_OF_PORTS(dev) (QED_IS_BB(dev) ? MAX_NUM_PORTS_BB \ | |
693 | : MAX_NUM_PORTS_K2) | |
694 | #define NUM_OF_SBS(dev) (QED_IS_BB(dev) ? MAX_SB_PER_PATH_BB \ | |
695 | : MAX_SB_PER_PATH_K2) | |
696 | #define NUM_OF_ENG_PFS(dev) (QED_IS_BB(dev) ? MAX_NUM_PFS_BB \ | |
697 | : MAX_NUM_PFS_K2) | |
fe56b9e6 YM |
698 | |
699 | /** | |
700 | * @brief qed_concrete_to_sw_fid - get the sw function id from | |
701 | * the concrete value. | |
702 | * | |
703 | * @param concrete_fid | |
704 | * | |
705 | * @return inline u8 | |
706 | */ | |
707 | static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev, | |
708 | u32 concrete_fid) | |
709 | { | |
4870e704 | 710 | u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); |
fe56b9e6 | 711 | u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); |
4870e704 YM |
712 | u8 vf_valid = GET_FIELD(concrete_fid, |
713 | PXP_CONCRETE_FID_VFVALID); | |
714 | u8 sw_fid; | |
fe56b9e6 | 715 | |
4870e704 YM |
716 | if (vf_valid) |
717 | sw_fid = vfid + MAX_NUM_PFS; | |
718 | else | |
719 | sw_fid = pfid; | |
720 | ||
721 | return sw_fid; | |
fe56b9e6 YM |
722 | } |
723 | ||
724 | #define PURE_LB_TC 8 | |
dbb799c3 | 725 | #define OOO_LB_TC 9 |
fe56b9e6 | 726 | |
733def6a | 727 | int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate); |
6f437d43 MY |
728 | void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, |
729 | struct qed_ptt *p_ptt, | |
730 | u32 min_pf_rate); | |
bcd197c8 | 731 | |
733def6a | 732 | void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); |
fe56b9e6 | 733 | #define QED_LEADING_HWFN(dev) (&dev->hwfns[0]) |
9c79ddaa | 734 | int qed_device_num_engines(struct qed_dev *cdev); |
fe56b9e6 YM |
735 | |
736 | /* Other Linux specific common definitions */ | |
737 | #define DP_NAME(cdev) ((cdev)->name) | |
738 | ||
739 | #define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\ | |
740 | (cdev->regview) + \ | |
741 | (offset)) | |
742 | ||
743 | #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset)) | |
744 | #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset)) | |
745 | #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset)) | |
746 | ||
747 | #define DOORBELL(cdev, db_addr, val) \ | |
748 | writel((u32)val, (void __iomem *)((u8 __iomem *)\ | |
749 | (cdev->doorbells) + (db_addr))) | |
750 | ||
751 | /* Prototypes */ | |
752 | int qed_fill_dev_info(struct qed_dev *cdev, | |
753 | struct qed_dev_info *dev_info); | |
cc875c2e | 754 | void qed_link_update(struct qed_hwfn *hwfn); |
fe56b9e6 YM |
755 | u32 qed_unzip_data(struct qed_hwfn *p_hwfn, |
756 | u32 input_len, u8 *input_buf, | |
757 | u32 max_size, u8 *unzip_buf); | |
6c754246 SRK |
758 | void qed_get_protocol_stats(struct qed_dev *cdev, |
759 | enum qed_mcp_protocol_type type, | |
760 | union qed_mcp_protocol_stats *stats); | |
8f16bc97 | 761 | int qed_slowpath_irq_req(struct qed_hwfn *hwfn); |
1226337a | 762 | void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn); |
8f16bc97 | 763 | |
fe56b9e6 | 764 | #endif /* _QED_H */ |